diff options
author | Dimitry Andric <dim@FreeBSD.org> | 2020-07-31 21:22:58 +0000 |
---|---|---|
committer | Dimitry Andric <dim@FreeBSD.org> | 2020-07-31 21:22:58 +0000 |
commit | 5ffd83dbcc34f10e07f6d3e968ae6365869615f4 (patch) | |
tree | 0e9f5cf729dde39f949698fddef45a34e2bc7f44 /contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonScheduleV67.td | |
parent | 1799696096df87b52968b8996d00c91e0a5de8d9 (diff) | |
parent | cfca06d7963fa0909f90483b42a6d7d194d01e08 (diff) | |
download | src-5ffd83dbcc34f10e07f6d3e968ae6365869615f4.tar.gz src-5ffd83dbcc34f10e07f6d3e968ae6365869615f4.zip |
Merge llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmp
master 2e10b7a39b9, the last commit before the llvmorg-12-init tag, from
which release/11.x was branched.
Note that for now, I rolled back all our local changes to make merging
easier, and I will reapply the still-relevant ones after updating to
11.0.0-rc1.
Notes
Notes:
svn path=/projects/clang1100-import/; revision=363742
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonScheduleV67.td')
-rw-r--r-- | contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonScheduleV67.td | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonScheduleV67.td b/contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonScheduleV67.td new file mode 100644 index 000000000000..4f9d861a5504 --- /dev/null +++ b/contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonScheduleV67.td @@ -0,0 +1,39 @@ +//=-HexagonScheduleV67.td - HexagonV67 Scheduling Definitions *- tablegen -*-=// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// +// ScalarItin and HVXItin contain some old itineraries +// still used by a handful of instructions. Hopefully, we will be able +// to get rid of them soon. + +def HexagonV67ItinList : DepScalarItinV66, ScalarItin, + DepHVXItinV66, HVXItin, PseudoItin { + list<InstrItinData> ItinList = + !listconcat(DepScalarItinV66_list, ScalarItin_list, + DepHVXItinV66_list, HVXItin_list, PseudoItin_list); +} + +def HexagonItinerariesV67 : + ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP, + CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1, + CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL, + CVI_ALL_NOMEM, CVI_ZW], + [Hex_FWD, HVX_FWD], + HexagonV67ItinList.ItinList>; + +def HexagonModelV67 : SchedMachineModel { + // Max issue per cycle == bundle width. + let IssueWidth = 4; + let Itineraries = HexagonItinerariesV67; + let LoadLatency = 1; + let CompleteModel = 0; +} + +//===----------------------------------------------------------------------===// +// Hexagon V67 Resource Definitions - +//===----------------------------------------------------------------------===// |