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author | Emmanuel Vadot <manu@FreeBSD.org> | 2017-03-07 12:41:06 +0000 |
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committer | Emmanuel Vadot <manu@FreeBSD.org> | 2017-03-07 12:41:06 +0000 |
commit | ff018dbf5bb142aa83bd955e5b6c55d66e9e9c1e (patch) | |
tree | 5cd0b74d984dae06ea54b6b09998163538d3c162 /include/dt-bindings/clock/r8a7745-cpg-mssr.h | |
parent | c7716441be3a4a48aa7b7cdf69a15625c1cd8ef5 (diff) | |
download | src-ff018dbf5bb142aa83bd955e5b6c55d66e9e9c1e.tar.gz src-ff018dbf5bb142aa83bd955e5b6c55d66e9e9c1e.zip |
Update to Linux 4.10vendor/device-tree/4.10
Notes
Notes:
svn path=/vendor/device-tree/dist/; revision=314847
svn path=/vendor/device-tree/4.10/; revision=314848; tag=vendor/device-tree/4.10
Diffstat (limited to 'include/dt-bindings/clock/r8a7745-cpg-mssr.h')
-rw-r--r-- | include/dt-bindings/clock/r8a7745-cpg-mssr.h | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/r8a7745-cpg-mssr.h b/include/dt-bindings/clock/r8a7745-cpg-mssr.h new file mode 100644 index 000000000000..56ad6f0c6760 --- /dev/null +++ b/include/dt-bindings/clock/r8a7745-cpg-mssr.h @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2016 Cogent Embedded Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* r8a7745 CPG Core Clocks */ +#define R8A7745_CLK_Z2 0 +#define R8A7745_CLK_ZG 1 +#define R8A7745_CLK_ZTR 2 +#define R8A7745_CLK_ZTRD2 3 +#define R8A7745_CLK_ZT 4 +#define R8A7745_CLK_ZX 5 +#define R8A7745_CLK_ZS 6 +#define R8A7745_CLK_HP 7 +#define R8A7745_CLK_B 9 +#define R8A7745_CLK_LB 10 +#define R8A7745_CLK_P 11 +#define R8A7745_CLK_CL 12 +#define R8A7745_CLK_CP 13 +#define R8A7745_CLK_M2 14 +#define R8A7745_CLK_ZB3 16 +#define R8A7745_CLK_ZB3D2 17 +#define R8A7745_CLK_DDR 18 +#define R8A7745_CLK_SDH 19 +#define R8A7745_CLK_SD0 20 +#define R8A7745_CLK_SD2 21 +#define R8A7745_CLK_SD3 22 +#define R8A7745_CLK_MMC0 23 +#define R8A7745_CLK_MP 24 +#define R8A7745_CLK_QSPI 25 +#define R8A7745_CLK_CPEX 26 +#define R8A7745_CLK_RCAN 27 +#define R8A7745_CLK_R 28 +#define R8A7745_CLK_OSC 29 + +#endif /* __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__ */ |