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author | Dimitry Andric <dim@FreeBSD.org> | 2019-08-20 20:50:12 +0000 |
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committer | Dimitry Andric <dim@FreeBSD.org> | 2019-08-20 20:50:12 +0000 |
commit | e6d1592492a3a379186bfb02bd0f4eda0669c0d5 (patch) | |
tree | 599ab169a01f1c86eda9adc774edaedde2f2db5b /lib/Target/ARM/ARMBaseRegisterInfo.cpp | |
parent | 1a56a5ead7a2e84bee8240f5f6b033b5f1707154 (diff) | |
download | src-e6d1592492a3a379186bfb02bd0f4eda0669c0d5.tar.gz src-e6d1592492a3a379186bfb02bd0f4eda0669c0d5.zip |
Vendor import of stripped llvm trunk r366426 (just before the release_90vendor/llvm/llvm-trunk-r366426
branch point):
https://llvm.org/svn/llvm-project/llvm/trunk@366426
Notes
Notes:
svn path=/vendor/llvm/dist/; revision=351278
svn path=/vendor/llvm/llvm-trunk-r366426/; revision=351279; tag=vendor/llvm/llvm-trunk-r366426
Diffstat (limited to 'lib/Target/ARM/ARMBaseRegisterInfo.cpp')
-rw-r--r-- | lib/Target/ARM/ARMBaseRegisterInfo.cpp | 51 |
1 files changed, 29 insertions, 22 deletions
diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp index 02b3daf3c6fd..dc99b37742da 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -1,9 +1,8 @@ //===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===// // -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // @@ -150,7 +149,7 @@ ARMBaseRegisterInfo::getTLSCallPreservedMask(const MachineFunction &MF) const { const uint32_t * ARMBaseRegisterInfo::getSjLjDispatchPreservedMask(const MachineFunction &MF) const { const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>(); - if (!STI.useSoftFloat() && STI.hasVFP2() && !STI.isThumb1Only()) + if (!STI.useSoftFloat() && STI.hasVFP2Base() && !STI.isThumb1Only()) return CSR_NoRegs_RegMask; else return CSR_FPRegs_RegMask; @@ -194,7 +193,7 @@ getReservedRegs(const MachineFunction &MF) const { if (STI.isR9Reserved()) markSuperRegs(Reserved, ARM::R9); // Reserve D16-D31 if the subtarget doesn't support them. - if (!STI.hasVFP3() || STI.hasD16()) { + if (!STI.hasD32()) { static_assert(ARM::D31 == ARM::D16 + 15, "Register list not consecutive!"); for (unsigned R = 0; R < 16; ++R) markSuperRegs(Reserved, ARM::D16 + R); @@ -204,6 +203,8 @@ getReservedRegs(const MachineFunction &MF) const { for (MCSubRegIterator SI(Reg, this); SI.isValid(); ++SI) if (Reserved.test(*SI)) markSuperRegs(Reserved, Reg); + // For v8.1m architecture + markSuperRegs(Reserved, ARM::ZR); assert(checkAllSuperRegsMarked(Reserved)); return Reserved; @@ -369,29 +370,35 @@ bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const { const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); const ARMFrameLowering *TFI = getFrameLowering(MF); - // When outgoing call frames are so large that we adjust the stack pointer - // around the call, we can no longer use the stack pointer to reach the - // emergency spill slot. + // If we have stack realignment and VLAs, we have no pointer to use to + // access the stack. If we have stack realignment, and a large call frame, + // we have no place to allocate the emergency spill slot. if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF)) return true; // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited // negative range for ldr/str (255), and thumb1 is positive offsets only. + // // It's going to be better to use the SP or Base Pointer instead. When there // are variable sized objects, we can't reference off of the SP, so we // reserve a Base Pointer. - if (AFI->isThumbFunction() && MFI.hasVarSizedObjects()) { - // Conservatively estimate whether the negative offset from the frame - // pointer will be sufficient to reach. If a function has a smallish - // frame, it's less likely to have lots of spills and callee saved - // space, so it's all more likely to be within range of the frame pointer. - // If it's wrong, the scavenger will still enable access to work, it just - // won't be optimal. - if (AFI->isThumb2Function() && MFI.getLocalFrameSize() < 128) - return false; + // + // For Thumb2, estimate whether a negative offset from the frame pointer + // will be sufficient to reach the whole stack frame. If a function has a + // smallish frame, it's less likely to have lots of spills and callee saved + // space, so it's all more likely to be within range of the frame pointer. + // If it's wrong, the scavenger will still enable access to work, it just + // won't be optimal. (We should always be able to reach the emergency + // spill slot from the frame pointer.) + if (AFI->isThumb2Function() && MFI.hasVarSizedObjects() && + MFI.getLocalFrameSize() >= 128) + return true; + // For Thumb1, if sp moves, nothing is in range, so force a base pointer. + // This is necessary for correctness in cases where we need an emergency + // spill slot. (In Thumb1, we can't use a negative offset from the frame + // pointer.) + if (AFI->isThumb1OnlyFunction() && !TFI->hasReservedCallFrame(MF)) return true; - } - return false; } @@ -425,7 +432,7 @@ cannotEliminateFrame(const MachineFunction &MF) const { || needsStackRealignment(MF); } -unsigned +Register ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const { const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>(); const ARMFrameLowering *TFI = getFrameLowering(MF); @@ -785,7 +792,7 @@ ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int PIdx = MI.findFirstPredOperandIdx(); ARMCC::CondCodes Pred = (PIdx == -1) ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); - unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); + Register PredReg = (PIdx == -1) ? Register() : MI.getOperand(PIdx+1).getReg(); if (Offset == 0) // Must be addrmode4/6. MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false); |