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author | Dimitry Andric <dim@FreeBSD.org> | 2017-12-24 01:00:08 +0000 |
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committer | Dimitry Andric <dim@FreeBSD.org> | 2017-12-24 01:00:08 +0000 |
commit | c7dac04c3480f3c20487f912f77343139fce2d99 (patch) | |
tree | 21a09bce0171e27bd1e92649db9df797fa097cea /lib/Target/ARM/ARMRegisterBankInfo.cpp | |
parent | 044eb2f6afba375a914ac9d8024f8f5142bb912e (diff) | |
download | src-c7dac04c3480f3c20487f912f77343139fce2d99.tar.gz src-c7dac04c3480f3c20487f912f77343139fce2d99.zip |
Vendor import of llvm trunk r321414:vendor/llvm/llvm-trunk-r321414
Notes
Notes:
svn path=/vendor/llvm/dist/; revision=327122
svn path=/vendor/llvm/llvm-trunk-r321414/; revision=327123; tag=vendor/llvm/llvm-trunk-r321414
Diffstat (limited to 'lib/Target/ARM/ARMRegisterBankInfo.cpp')
-rw-r--r-- | lib/Target/ARM/ARMRegisterBankInfo.cpp | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMRegisterBankInfo.cpp b/lib/Target/ARM/ARMRegisterBankInfo.cpp index b32bfd449544..fad0e98285e6 100644 --- a/lib/Target/ARM/ARMRegisterBankInfo.cpp +++ b/lib/Target/ARM/ARMRegisterBankInfo.cpp @@ -226,12 +226,30 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { case G_SEXT: case G_ZEXT: case G_ANYEXT: - case G_TRUNC: case G_GEP: + case G_INTTOPTR: + case G_PTRTOINT: // FIXME: We're abusing the fact that everything lives in a GPR for now; in // the real world we would use different mappings. OperandsMapping = &ARM::ValueMappings[ARM::GPR3OpsIdx]; break; + case G_TRUNC: { + // In some cases we may end up with a G_TRUNC from a 64-bit value to a + // 32-bit value. This isn't a real floating point trunc (that would be a + // G_FPTRUNC). Instead it is an integer trunc in disguise, which can appear + // because the legalizer doesn't distinguish between integer and floating + // point values so it may leave some 64-bit integers un-narrowed. Until we + // have a more principled solution that doesn't let such things sneak all + // the way to this point, just map the source to a DPR and the destination + // to a GPR. + LLT LargeTy = MRI.getType(MI.getOperand(1).getReg()); + OperandsMapping = + LargeTy.getSizeInBits() <= 32 + ? &ARM::ValueMappings[ARM::GPR3OpsIdx] + : getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], + &ARM::ValueMappings[ARM::DPR3OpsIdx]}); + break; + } case G_LOAD: case G_STORE: { LLT Ty = MRI.getType(MI.getOperand(0).getReg()); |