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author | Dimitry Andric <dim@FreeBSD.org> | 2012-04-14 13:54:10 +0000 |
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committer | Dimitry Andric <dim@FreeBSD.org> | 2012-04-14 13:54:10 +0000 |
commit | 63faed5b8e4f2755f127fcb8aa440480c0649327 (patch) | |
tree | 19c69a04768629f2d440944b71cbe90adae0b615 /lib/Target/ARM/README.txt | |
parent | d4c8b5d2e851b0e8a063c6bf8543a4823a26c15a (diff) | |
download | src-63faed5b8e4f2755f127fcb8aa440480c0649327.tar.gz src-63faed5b8e4f2755f127fcb8aa440480c0649327.zip |
Vendor import of llvm trunk r154661:vendor/llvm/llvm-trunk-r154661
Notes
Notes:
svn path=/vendor/llvm/dist/; revision=234285
svn path=/vendor/llvm/llvm-trunk-r154661/; revision=234286; tag=vendor/llvm/llvm-trunk-r154661
Diffstat (limited to 'lib/Target/ARM/README.txt')
-rw-r--r-- | lib/Target/ARM/README.txt | 21 |
1 files changed, 16 insertions, 5 deletions
diff --git a/lib/Target/ARM/README.txt b/lib/Target/ARM/README.txt index 2f6842e8cb60..3eddda812f84 100644 --- a/lib/Target/ARM/README.txt +++ b/lib/Target/ARM/README.txt @@ -501,11 +501,6 @@ those operations and the ARMv6 scalar versions. //===---------------------------------------------------------------------===// -ARM::MOVCCr is commutable (by flipping the condition). But we need to implement -ARMInstrInfo::commuteInstruction() to support it. - -//===---------------------------------------------------------------------===// - Split out LDR (literal) from normal ARM LDR instruction. Also consider spliting LDR into imm12 and so_reg forms. This allows us to clean up some code. e.g. ARMLoadStoreOptimizer does not need to look at LDR (literal) and LDR (so_reg) @@ -699,3 +694,19 @@ test is equality test so it's more a conditional move rather than a select: Currently this is a ARM specific dag combine. We probably should make it into a target-neutral one. + +//===---------------------------------------------------------------------===// + +Optimize unnecessary checks for zero with __builtin_clz/ctz. Those builtins +are specified to be undefined at zero, so portable code must check for zero +and handle it as a special case. That is unnecessary on ARM where those +operations are implemented in a way that is well-defined for zero. For +example: + +int f(int x) { return x ? __builtin_clz(x) : sizeof(int)*8; } + +should just be implemented with a CLZ instruction. Since there are other +targets, e.g., PPC, that share this behavior, it would be best to implement +this in a target-independent way: we should probably fold that (when using +"undefined at zero" semantics) to set the "defined at zero" bit and have +the code generator expand out the right code. |