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authorDimitry Andric <dim@FreeBSD.org>2018-06-27 19:14:09 +0000
committerDimitry Andric <dim@FreeBSD.org>2018-06-27 19:14:09 +0000
commiteb1edd4d5902fdc561fd68fa70400fbd11127998 (patch)
tree0b10ccde4b5d3acf243966db54f4f3afef10cf93 /lib/Target/Mips/MicroMips32r6InstrInfo.td
parent2ed8710148a921286717212737771dd31c518fb7 (diff)
Vendor import of llvm 6.0.1 release r335540:vendor/llvm/llvm-release_601-r335540vendor/llvm-60
Notes
Notes: svn path=/vendor/llvm/dist-release_60/; revision=335720 svn path=/vendor/llvm/llvm-release_601-r335540/; revision=335721; tag=vendor/llvm/llvm-release_601-r335540
Diffstat (limited to 'lib/Target/Mips/MicroMips32r6InstrInfo.td')
-rw-r--r--lib/Target/Mips/MicroMips32r6InstrInfo.td6
1 files changed, 6 insertions, 0 deletions
diff --git a/lib/Target/Mips/MicroMips32r6InstrInfo.td b/lib/Target/Mips/MicroMips32r6InstrInfo.td
index 3ff3f07654d9..326897dc5c63 100644
--- a/lib/Target/Mips/MicroMips32r6InstrInfo.td
+++ b/lib/Target/Mips/MicroMips32r6InstrInfo.td
@@ -1886,6 +1886,12 @@ let AddedComplexity = 41 in {
def TAILCALL_MMR6 : TailCall<BC_MMR6, brtarget26_mm>, ISA_MICROMIPS32R6;
+def TAILCALLREG_MMR6 : TailCallReg<JRC16_MM, GPR32Opnd>, ISA_MICROMIPS32R6;
+
+def PseudoIndirectBranch_MMR6 : PseudoIndirectBranchBase<JRC16_MMR6,
+ GPR32Opnd>,
+ ISA_MICROMIPS32R6;
+
def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
(TAILCALL_MMR6 tglobaladdr:$dst)>, ISA_MICROMIPS32R6;