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author | Dimitry Andric <dim@FreeBSD.org> | 2017-04-16 16:01:22 +0000 |
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committer | Dimitry Andric <dim@FreeBSD.org> | 2017-04-16 16:01:22 +0000 |
commit | 71d5a2540a98c81f5bcaeb48805e0e2881f530ef (patch) | |
tree | 5343938942df402b49ec7300a1c25a2d4ccd5821 /lib/Target/SystemZ/SystemZTargetMachine.cpp | |
parent | 31bbf64f3a4974a2d6c8b3b27ad2f519caf74057 (diff) | |
download | src-71d5a2540a98c81f5bcaeb48805e0e2881f530ef.tar.gz src-71d5a2540a98c81f5bcaeb48805e0e2881f530ef.zip |
Vendor import of llvm trunk r300422:vendor/llvm/llvm-trunk-r300422
Notes
Notes:
svn path=/vendor/llvm/dist/; revision=317017
svn path=/vendor/llvm/llvm-trunk-r300422/; revision=317018; tag=vendor/llvm/llvm-trunk-r300422
Diffstat (limited to 'lib/Target/SystemZ/SystemZTargetMachine.cpp')
-rw-r--r-- | lib/Target/SystemZ/SystemZTargetMachine.cpp | 27 |
1 files changed, 20 insertions, 7 deletions
diff --git a/lib/Target/SystemZ/SystemZTargetMachine.cpp b/lib/Target/SystemZ/SystemZTargetMachine.cpp index 33fdb8f90825..ede5005fa491 100644 --- a/lib/Target/SystemZ/SystemZTargetMachine.cpp +++ b/lib/Target/SystemZ/SystemZTargetMachine.cpp @@ -7,14 +7,25 @@ // //===----------------------------------------------------------------------===// +#include "MCTargetDesc/SystemZMCTargetDesc.h" +#include "SystemZ.h" +#include "SystemZMachineScheduler.h" #include "SystemZTargetMachine.h" #include "SystemZTargetTransformInfo.h" -#include "SystemZMachineScheduler.h" +#include "llvm/ADT/Optional.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/StringRef.h" +#include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/CodeGen/Passes.h" +#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" #include "llvm/CodeGen/TargetPassConfig.h" +#include "llvm/IR/DataLayout.h" +#include "llvm/Support/CodeGen.h" #include "llvm/Support/TargetRegistry.h" +#include "llvm/Target/TargetLoweringObjectFile.h" #include "llvm/Transforms/Scalar.h" -#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" +#include <string> using namespace llvm; @@ -48,7 +59,7 @@ static bool UsesVectorABI(StringRef CPU, StringRef FS) { static std::string computeDataLayout(const Triple &TT, StringRef CPU, StringRef FS) { bool VectorABI = UsesVectorABI(CPU, FS); - std::string Ret = ""; + std::string Ret; // Big endian. Ret += "E"; @@ -96,14 +107,15 @@ SystemZTargetMachine::SystemZTargetMachine(const Target &T, const Triple &TT, CodeGenOpt::Level OL) : LLVMTargetMachine(T, computeDataLayout(TT, CPU, FS), TT, CPU, FS, Options, getEffectiveRelocModel(RM), CM, OL), - TLOF(make_unique<TargetLoweringObjectFileELF>()), + TLOF(llvm::make_unique<TargetLoweringObjectFileELF>()), Subtarget(TT, CPU, FS, *this) { initAsmInfo(); } -SystemZTargetMachine::~SystemZTargetMachine() {} +SystemZTargetMachine::~SystemZTargetMachine() = default; namespace { + /// SystemZ Code Generator Pass Configuration Options. class SystemZPassConfig : public TargetPassConfig { public: @@ -116,7 +128,8 @@ public: ScheduleDAGInstrs * createPostMachineScheduler(MachineSchedContext *C) const override { - return new ScheduleDAGMI(C, make_unique<SystemZPostRASchedStrategy>(C), + return new ScheduleDAGMI(C, + llvm::make_unique<SystemZPostRASchedStrategy>(C), /*RemoveKillFlags=*/true); } @@ -126,6 +139,7 @@ public: void addPreSched2() override; void addPreEmitPass() override; }; + } // end anonymous namespace void SystemZPassConfig::addIRPasses() { @@ -157,7 +171,6 @@ void SystemZPassConfig::addPreSched2() { } void SystemZPassConfig::addPreEmitPass() { - // Do instruction shortening before compare elimination because some // vector instructions will be shortened into opcodes that compare // elimination recognizes. |