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| author | Dimitry Andric <dim@FreeBSD.org> | 2018-08-18 08:26:46 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2018-08-18 08:26:46 +0000 |
| commit | d0a9cbdae159210824ddf2da138e2dcaecbe1cd4 (patch) | |
| tree | c539e15a2dbf52df82eb2a72fb6581db604faab4 /lib/Target/X86/X86FlagsCopyLowering.cpp | |
| parent | ac3a3c134038429abacef8c5d8069674f98d6b34 (diff) | |
| download | src-d0a9cbdae159210824ddf2da138e2dcaecbe1cd4.tar.gz src-d0a9cbdae159210824ddf2da138e2dcaecbe1cd4.zip | |
Vendor import of llvm release_70 branch r339999:vendor/llvm/llvm-release_70-r339999
Notes
Notes:
svn path=/vendor/llvm/dist-release_70/; revision=338000
svn path=/vendor/llvm/llvm-release_70-r339999/; revision=338001; tag=vendor/llvm/llvm-release_70-r339999
Diffstat (limited to 'lib/Target/X86/X86FlagsCopyLowering.cpp')
| -rw-r--r-- | lib/Target/X86/X86FlagsCopyLowering.cpp | 17 |
1 files changed, 11 insertions, 6 deletions
diff --git a/lib/Target/X86/X86FlagsCopyLowering.cpp b/lib/Target/X86/X86FlagsCopyLowering.cpp index c17c51a7aeac..d2f2f21542a9 100644 --- a/lib/Target/X86/X86FlagsCopyLowering.cpp +++ b/lib/Target/X86/X86FlagsCopyLowering.cpp @@ -97,6 +97,7 @@ public: private: MachineRegisterInfo *MRI; + const X86Subtarget *Subtarget; const X86InstrInfo *TII; const TargetRegisterInfo *TRI; const TargetRegisterClass *PromoteRC; @@ -346,10 +347,10 @@ bool X86FlagsCopyLoweringPass::runOnMachineFunction(MachineFunction &MF) { LLVM_DEBUG(dbgs() << "********** " << getPassName() << " : " << MF.getName() << " **********\n"); - auto &Subtarget = MF.getSubtarget<X86Subtarget>(); + Subtarget = &MF.getSubtarget<X86Subtarget>(); MRI = &MF.getRegInfo(); - TII = Subtarget.getInstrInfo(); - TRI = Subtarget.getRegisterInfo(); + TII = Subtarget->getInstrInfo(); + TRI = Subtarget->getRegisterInfo(); MDT = &getAnalysis<MachineDominatorTree>(); PromoteRC = &X86::GR8RegClass; @@ -960,10 +961,14 @@ void X86FlagsCopyLoweringPass::rewriteSetCarryExtended( .addReg(Reg) .addImm(SubRegIdx[OrigRegSize]); } else if (OrigRegSize > TargetRegSize) { - BuildMI(MBB, SetPos, SetLoc, TII->get(TargetOpcode::EXTRACT_SUBREG), + if (TargetRegSize == 1 && !Subtarget->is64Bit()) { + // Need to constrain the register class. + MRI->constrainRegClass(Reg, &X86::GR32_ABCDRegClass); + } + + BuildMI(MBB, SetPos, SetLoc, TII->get(TargetOpcode::COPY), NewReg) - .addReg(Reg) - .addImm(SubRegIdx[TargetRegSize]); + .addReg(Reg, 0, SubRegIdx[TargetRegSize]); } else { BuildMI(MBB, SetPos, SetLoc, TII->get(TargetOpcode::COPY), NewReg) .addReg(Reg); |