Merge ^/head r279759 through r279892.

31 files changed, 1681 insertions, 436 deletions

diff --git a/lib/libc/net/sctp_sys_calls.c b/lib/libc/net/sctp_sys_calls.c
index 6971c606dbcd..f07aa4321ca8 100644
--- a/lib/libc/net/sctp_sys_calls.c
+++ b/lib/libc/net/sctp_sys_calls.c
@@ -383,6 +383,9 @@ sctp_opt_info(int sd, sctp_assoc_t id, int opt, void *arg, socklen_t * size)
 	case SCTP_PR_ASSOC_STATUS:
 		((struct sctp_prstatus *)arg)->sprstat_assoc_id = id;
 		break;
+	case SCTP_MAX_CWND:
+		((struct sctp_assoc_value *)arg)->assoc_id = id;
+		break;
 	default:
 		break;
 	}
diff --git a/lib/libc/powerpc/gen/_setjmp.S b/lib/libc/powerpc/gen/_setjmp.S
index e28386c24b9c..f7f3d64e1b73 100644
--- a/lib/libc/powerpc/gen/_setjmp.S
+++ b/lib/libc/powerpc/gen/_setjmp.S
@@ -56,12 +56,54 @@ ENTRY(_setjmp)
 	mr	%r10,%r1
 	mr	%r9,%r2
 	stmw	%r9,20(%r3)
+
+	/* FPRs */
+	stfd	%f14,92+0*8(%r3)
+	stfd	%f15,92+1*8(%r3)
+	stfd	%f16,92+2*8(%r3)
+	stfd	%f17,92+3*8(%r3)
+	stfd	%f18,92+4*8(%r3)
+	stfd	%f19,92+5*8(%r3)
+	stfd	%f20,92+6*8(%r3)
+	stfd	%f21,92+7*8(%r3)
+	stfd	%f22,92+8*8(%r3)
+	stfd	%f23,92+9*8(%r3)
+	stfd	%f24,92+10*8(%r3)
+	stfd	%f25,92+11*8(%r3)
+	stfd	%f26,92+12*8(%r3)
+	stfd	%f27,92+13*8(%r3)
+	stfd	%f28,93+13*8(%r3)
+	stfd	%f29,93+14*8(%r3)
+	stfd	%f30,93+15*8(%r3)
+	stfd	%f31,93+16*8(%r3)
+
 	li	%r3,0
 	blr
 END(_setjmp)
 
 ENTRY(_longjmp)
 	lmw	%r9,20(%r3)
+
+	/* FPRs */
+	lfd	%f14,92+0*8(%r3)
+	lfd	%f15,92+1*8(%r3)
+	lfd	%f16,92+2*8(%r3)
+	lfd	%f17,92+3*8(%r3)
+	lfd	%f18,92+4*8(%r3)
+	lfd	%f19,92+5*8(%r3)
+	lfd	%f20,92+6*8(%r3)
+	lfd	%f21,92+7*8(%r3)
+	lfd	%f22,92+8*8(%r3)
+	lfd	%f23,92+9*8(%r3)
+	lfd	%f24,92+10*8(%r3)
+	lfd	%f25,92+11*8(%r3)
+	lfd	%f26,92+12*8(%r3)
+	lfd	%f27,92+13*8(%r3)
+	lfd	%f28,93+13*8(%r3)
+	lfd	%f29,93+14*8(%r3)
+	lfd	%f30,93+15*8(%r3)
+	lfd	%f31,93+16*8(%r3)
+
 	mtlr	%r11
 	mtcr	%r12
 	mr	%r1,%r10
diff --git a/lib/libc/powerpc/gen/setjmp.S b/lib/libc/powerpc/gen/setjmp.S
index 9325fc2378cb..881c24e1e813 100644
--- a/lib/libc/powerpc/gen/setjmp.S
+++ b/lib/libc/powerpc/gen/setjmp.S
@@ -66,6 +66,27 @@ ENTRY(setjmp)
 	mr	%r10,%r1		/* r10 <- stackptr */
 	mr	%r9,%r2			/*  r9 <- global ptr */
 	stmw	%r9,20(%r6)
+
+	/* FPRs */
+	stfd	%f14,92+0*8(%r6)
+	stfd	%f15,92+1*8(%r6)
+	stfd	%f16,92+2*8(%r6)
+	stfd	%f17,92+3*8(%r6)
+	stfd	%f18,92+4*8(%r6)
+	stfd	%f19,92+5*8(%r6)
+	stfd	%f20,92+6*8(%r6)
+	stfd	%f21,92+7*8(%r6)
+	stfd	%f22,92+8*8(%r6)
+	stfd	%f23,92+9*8(%r6)
+	stfd	%f24,92+10*8(%r6)
+	stfd	%f25,92+11*8(%r6)
+	stfd	%f26,92+12*8(%r6)
+	stfd	%f27,92+13*8(%r6)
+	stfd	%f28,93+13*8(%r6)
+	stfd	%f29,93+14*8(%r6)
+	stfd	%f30,93+15*8(%r6)
+	stfd	%f31,93+16*8(%r6)
+
 	li	%r3,0			/* return (0) */
 	blr
 END(setjmp)
@@ -73,6 +94,27 @@ END(setjmp)
 	WEAK_REFERENCE(CNAME(__longjmp), longjmp)
 ENTRY(__longjmp)
 	lmw	%r9,20(%r3)		/* restore regs */
+
+	/* FPRs */
+	lfd	%f14,92+0*8(%r3)
+	lfd	%f15,92+1*8(%r3)
+	lfd	%f16,92+2*8(%r3)
+	lfd	%f17,92+3*8(%r3)
+	lfd	%f18,92+4*8(%r3)
+	lfd	%f19,92+5*8(%r3)
+	lfd	%f20,92+6*8(%r3)
+	lfd	%f21,92+7*8(%r3)
+	lfd	%f22,92+8*8(%r3)
+	lfd	%f23,92+9*8(%r3)
+	lfd	%f24,92+10*8(%r3)
+	lfd	%f25,92+11*8(%r3)
+	lfd	%f26,92+12*8(%r3)
+	lfd	%f27,92+13*8(%r3)
+	lfd	%f28,93+13*8(%r3)
+	lfd	%f29,93+14*8(%r3)
+	lfd	%f30,93+15*8(%r3)
+	lfd	%f31,93+16*8(%r3)
+
 	mr	%r6,%r4			/* save val param */
 	mtlr	%r11			/* r11 -> link reg */
 	mtcr	%r12			/* r12 -> condition reg */
diff --git a/lib/libc/powerpc/gen/sigsetjmp.S b/lib/libc/powerpc/gen/sigsetjmp.S
index c67afc610316..ec7460aacaa3 100644
--- a/lib/libc/powerpc/gen/sigsetjmp.S
+++ b/lib/libc/powerpc/gen/sigsetjmp.S
@@ -71,12 +71,54 @@ ENTRY(sigsetjmp)
 	mr	%r10,%r1
 	mr	%r9,%r2
 	stmw	%r9,20(%r6)
+
+	/* FPRs */
+	stfd	%f14,92+0*8(%r6)
+	stfd	%f15,92+1*8(%r6)
+	stfd	%f16,92+2*8(%r6)
+	stfd	%f17,92+3*8(%r6)
+	stfd	%f18,92+4*8(%r6)
+	stfd	%f19,92+5*8(%r6)
+	stfd	%f20,92+6*8(%r6)
+	stfd	%f21,92+7*8(%r6)
+	stfd	%f22,92+8*8(%r6)
+	stfd	%f23,92+9*8(%r6)
+	stfd	%f24,92+10*8(%r6)
+	stfd	%f25,92+11*8(%r6)
+	stfd	%f26,92+12*8(%r6)
+	stfd	%f27,92+13*8(%r6)
+	stfd	%f28,93+13*8(%r6)
+	stfd	%f29,93+14*8(%r6)
+	stfd	%f30,93+15*8(%r6)
+	stfd	%f31,93+16*8(%r6)
+
 	li	%r3,0
 	blr
 END(sigsetjmp)
 
 ENTRY(siglongjmp)
 	lmw	%r9,20(%r3)
+
+	/* FPRs */
+	lfd	%f14,92+0*8(%r3)
+	lfd	%f15,92+1*8(%r3)
+	lfd	%f16,92+2*8(%r3)
+	lfd	%f17,92+3*8(%r3)
+	lfd	%f18,92+4*8(%r3)
+	lfd	%f19,92+5*8(%r3)
+	lfd	%f20,92+6*8(%r3)
+	lfd	%f21,92+7*8(%r3)
+	lfd	%f22,92+8*8(%r3)
+	lfd	%f23,92+9*8(%r3)
+	lfd	%f24,92+10*8(%r3)
+	lfd	%f25,92+11*8(%r3)
+	lfd	%f26,92+12*8(%r3)
+	lfd	%f27,92+13*8(%r3)
+	lfd	%f28,93+13*8(%r3)
+	lfd	%f29,93+14*8(%r3)
+	lfd	%f30,93+15*8(%r3)
+	lfd	%f31,93+16*8(%r3)
+
 	lwz	%r7,0(%r3)
 	mr	%r6,%r4
 	mtlr	%r11
diff --git a/lib/libc/powerpc64/gen/_setjmp.S b/lib/libc/powerpc64/gen/_setjmp.S
index 207c4f7d10d9..f7689aeba350 100644
--- a/lib/libc/powerpc64/gen/_setjmp.S
+++ b/lib/libc/powerpc64/gen/_setjmp.S
@@ -56,23 +56,41 @@ ENTRY(_setjmp)
 	mr	%r10,%r1
 	mr	%r9,%r2
 	std	%r9,40 + 0*8(%r3)
+	stfd	%f14,40 + 23*8(%r3)
 	std	%r10,40 + 1*8(%r3)
+	stfd	%f15,40 + 24*8(%r3)
 	std	%r11,40 + 2*8(%r3)
+	stfd	%f16,40 + 25*8(%r3)
 	std	%r12,40 + 3*8(%r3)
+	stfd	%f17,40 + 26*8(%r3)
 	std	%r13,40 + 4*8(%r3)
+	stfd	%f18,40 + 27*8(%r3)
 	std	%r14,40 + 5*8(%r3)
+	stfd	%f19,40 + 28*8(%r3)
 	std	%r15,40 + 6*8(%r3)
+	stfd	%f20,40 + 29*8(%r3)
 	std	%r16,40 + 7*8(%r3)
+	stfd	%f21,40 + 30*8(%r3)
 	std	%r17,40 + 8*8(%r3)
+	stfd	%f22,40 + 31*8(%r3)
 	std	%r18,40 + 9*8(%r3)
+	stfd	%f23,40 + 32*8(%r3)
 	std	%r19,40 + 10*8(%r3)
+	stfd	%f24,40 + 33*8(%r3)
 	std	%r20,40 + 11*8(%r3)
+	stfd	%f25,40 + 34*8(%r3)
 	std	%r21,40 + 12*8(%r3)
+	stfd	%f26,40 + 35*8(%r3)
 	std	%r22,40 + 13*8(%r3)
+	stfd	%f27,40 + 36*8(%r3)
 	std	%r23,40 + 14*8(%r3)
+	stfd	%f28,40 + 37*8(%r3)
 	std	%r24,40 + 15*8(%r3)
+	stfd	%f29,40 + 38*8(%r3)
 	std	%r25,40 + 16*8(%r3)
+	stfd	%f30,40 + 39*8(%r3)
 	std	%r26,40 + 17*8(%r3)
+	stfd	%f31,40 + 40*8(%r3)
 	std	%r27,40 + 18*8(%r3)
 	std	%r28,40 + 19*8(%r3)
 	std	%r29,40 + 20*8(%r3)
@@ -84,23 +102,41 @@ END(_setjmp)
 
 ENTRY(_longjmp)
 	ld	%r9,40 + 0*8(%r3)
+	lfd	%f14,40 + 23*8(%r3)
 	ld	%r10,40 + 1*8(%r3)
+	lfd	%f15,40 + 24*8(%r3)
 	ld	%r11,40 + 2*8(%r3)
+	lfd	%f16,40 + 25*8(%r3)
 	ld	%r12,40 + 3*8(%r3)
+	lfd	%f17,40 + 26*8(%r3)
 	ld	%r14,40 + 5*8(%r3)
+	lfd	%f18,40 + 27*8(%r3)
 	ld	%r15,40 + 6*8(%r3)
+	lfd	%f19,40 + 28*8(%r3)
 	ld	%r16,40 + 7*8(%r3)
+	lfd	%f20,40 + 29*8(%r3)
 	ld	%r17,40 + 8*8(%r3)
+	lfd	%f21,40 + 30*8(%r3)
 	ld	%r18,40 + 9*8(%r3)
+	lfd	%f22,40 + 31*8(%r3)
 	ld	%r19,40 + 10*8(%r3)
+	lfd	%f23,40 + 32*8(%r3)
 	ld	%r20,40 + 11*8(%r3)
+	lfd	%f24,40 + 33*8(%r3)
 	ld	%r21,40 + 12*8(%r3)
+	lfd	%f25,40 + 34*8(%r3)
 	ld	%r22,40 + 13*8(%r3)
+	lfd	%f26,40 + 35*8(%r3)
 	ld	%r23,40 + 14*8(%r3)
+	lfd	%f27,40 + 36*8(%r3)
 	ld	%r24,40 + 15*8(%r3)
+	lfd	%f28,40 + 37*8(%r3)
 	ld	%r25,40 + 16*8(%r3)
+	lfd	%f29,40 + 38*8(%r3)
 	ld	%r26,40 + 17*8(%r3)
+	lfd	%f30,40 + 39*8(%r3)
 	ld	%r27,40 + 18*8(%r3)
+	lfd	%f31,40 + 40*8(%r3)
 	ld	%r28,40 + 19*8(%r3)
 	ld	%r29,40 + 20*8(%r3)
 	ld	%r30,40 + 21*8(%r3)
diff --git a/lib/libc/powerpc64/gen/setjmp.S b/lib/libc/powerpc64/gen/setjmp.S
index 14954667b9b4..5eb395e7c30d 100644
--- a/lib/libc/powerpc64/gen/setjmp.S
+++ b/lib/libc/powerpc64/gen/setjmp.S
@@ -67,29 +67,49 @@ ENTRY(setjmp)
 	mr	%r9,%r2			/*  r9 <- global ptr */
 
 	std	%r9,40 + 0*8(%r6)
+	stfd	%f14,40 + 23*8(%r6)
 	std	%r10,40 + 1*8(%r6)
+	stfd	%f15,40 + 24*8(%r6)
 	std	%r11,40 + 2*8(%r6)
+	stfd	%f16,40 + 25*8(%r6)
 	std	%r12,40 + 3*8(%r6)
+	stfd	%f17,40 + 26*8(%r6)
 	std	%r13,40 + 4*8(%r6)
+	stfd	%f18,40 + 27*8(%r6)
 	std	%r14,40 + 5*8(%r6)
+	stfd	%f19,40 + 28*8(%r6)
 	std	%r15,40 + 6*8(%r6)
+	stfd	%f20,40 + 29*8(%r6)
 	std	%r16,40 + 7*8(%r6)
+	stfd	%f21,40 + 30*8(%r6)
 	std	%r17,40 + 8*8(%r6)
+	stfd	%f22,40 + 31*8(%r6)
 	std	%r18,40 + 9*8(%r6)
+	stfd	%f23,40 + 32*8(%r6)
 	std	%r19,40 + 10*8(%r6)
+	stfd	%f24,40 + 33*8(%r6)
 	std	%r20,40 + 11*8(%r6)
+	stfd	%f25,40 + 34*8(%r6)
 	std	%r21,40 + 12*8(%r6)
+	stfd	%f26,40 + 35*8(%r6)
 	std	%r22,40 + 13*8(%r6)
+	stfd	%f27,40 + 36*8(%r6)
 	std	%r23,40 + 14*8(%r6)
+	stfd	%f28,40 + 37*8(%r6)
 	std	%r24,40 + 15*8(%r6)
+	stfd	%f29,40 + 38*8(%r6)
 	std	%r25,40 + 16*8(%r6)
+	stfd	%f30,40 + 39*8(%r6)
 	std	%r26,40 + 17*8(%r6)
+	stfd	%f31,40 + 40*8(%r6)
 	std	%r27,40 + 18*8(%r6)
 	std	%r28,40 + 19*8(%r6)
 	std	%r29,40 + 20*8(%r6)
 	std	%r30,40 + 21*8(%r6)
 	std	%r31,40 + 22*8(%r6)
 
+	/* XXX Altivec regs */
+
 	li	%r3,0			/* return (0) */
 	blr
 END(setjmp)
@@ -97,23 +117,41 @@ END(setjmp)
 	WEAK_REFERENCE(__longjmp, longjmp)
 ENTRY(__longjmp)
 	ld	%r9,40 + 0*8(%r3)
+	lfd	%f14,40 + 23*8(%r3)
 	ld	%r10,40 + 1*8(%r3)
+	lfd	%f15,40 + 24*8(%r3)
 	ld	%r11,40 + 2*8(%r3)
+	lfd	%f16,40 + 25*8(%r3)
 	ld	%r12,40 + 3*8(%r3)
+	lfd	%f17,40 + 26*8(%r3)
 	ld	%r14,40 + 5*8(%r3)
+	lfd	%f18,40 + 27*8(%r3)
 	ld	%r15,40 + 6*8(%r3)
+	lfd	%f19,40 + 28*8(%r3)
 	ld	%r16,40 + 7*8(%r3)
+	lfd	%f20,40 + 29*8(%r3)
 	ld	%r17,40 + 8*8(%r3)
+	lfd	%f21,40 + 30*8(%r3)
 	ld	%r18,40 + 9*8(%r3)
+	lfd	%f22,40 + 31*8(%r3)
 	ld	%r19,40 + 10*8(%r3)
+	lfd	%f23,40 + 32*8(%r3)
 	ld	%r20,40 + 11*8(%r3)
+	lfd	%f24,40 + 33*8(%r3)
 	ld	%r21,40 + 12*8(%r3)
+	lfd	%f25,40 + 34*8(%r3)
 	ld	%r22,40 + 13*8(%r3)
+	lfd	%f26,40 + 35*8(%r3)
 	ld	%r23,40 + 14*8(%r3)
+	lfd	%f27,40 + 36*8(%r3)
 	ld	%r24,40 + 15*8(%r3)
+	lfd	%f28,40 + 37*8(%r3)
 	ld	%r25,40 + 16*8(%r3)
+	lfd	%f29,40 + 38*8(%r3)
 	ld	%r26,40 + 17*8(%r3)
+	lfd	%f30,40 + 39*8(%r3)
 	ld	%r27,40 + 18*8(%r3)
+	lfd	%f31,40 + 40*8(%r3)
 	ld	%r28,40 + 19*8(%r3)
 	ld	%r29,40 + 20*8(%r3)
 	ld	%r30,40 + 21*8(%r3)
diff --git a/lib/libc/powerpc64/gen/sigsetjmp.S b/lib/libc/powerpc64/gen/sigsetjmp.S
index 5cfd684d38da..c0648a632f1e 100644
--- a/lib/libc/powerpc64/gen/sigsetjmp.S
+++ b/lib/libc/powerpc64/gen/sigsetjmp.S
@@ -72,23 +72,41 @@ ENTRY(sigsetjmp)
 	mr	%r9,%r2
 
 	std	%r9,40 + 0*8(%r6)
+	stfd	%f14,40 + 23*8(%r6)
 	std	%r10,40 + 1*8(%r6)
+	stfd	%f15,40 + 24*8(%r6)
 	std	%r11,40 + 2*8(%r6)
+	stfd	%f16,40 + 25*8(%r6)
 	std	%r12,40 + 3*8(%r6)
+	stfd	%f17,40 + 26*8(%r6)
 	std	%r13,40 + 4*8(%r6)
+	stfd	%f18,40 + 27*8(%r6)
 	std	%r14,40 + 5*8(%r6)
+	stfd	%f19,40 + 28*8(%r6)
 	std	%r15,40 + 6*8(%r6)
+	stfd	%f20,40 + 29*8(%r6)
 	std	%r16,40 + 7*8(%r6)
+	stfd	%f21,40 + 30*8(%r6)
 	std	%r17,40 + 8*8(%r6)
+	stfd	%f22,40 + 31*8(%r6)
 	std	%r18,40 + 9*8(%r6)
+	stfd	%f23,40 + 32*8(%r6)
 	std	%r19,40 + 10*8(%r6)
+	stfd	%f24,40 + 33*8(%r6)
 	std	%r20,40 + 11*8(%r6)
+	stfd	%f25,40 + 34*8(%r6)
 	std	%r21,40 + 12*8(%r6)
+	stfd	%f26,40 + 35*8(%r6)
 	std	%r22,40 + 13*8(%r6)
+	stfd	%f27,40 + 36*8(%r6)
 	std	%r23,40 + 14*8(%r6)
+	stfd	%f28,40 + 37*8(%r6)
 	std	%r24,40 + 15*8(%r6)
+	stfd	%f29,40 + 38*8(%r6)
 	std	%r25,40 + 16*8(%r6)
+	stfd	%f30,40 + 39*8(%r6)
 	std	%r26,40 + 17*8(%r6)
+	stfd	%f31,40 + 40*8(%r6)
 	std	%r27,40 + 18*8(%r6)
 	std	%r28,40 + 19*8(%r6)
 	std	%r29,40 + 20*8(%r6)
@@ -101,23 +119,41 @@ END(sigsetjmp)
 
 ENTRY(siglongjmp)
 	ld	%r9,40 + 0*8(%r3)
+	lfd	%f14,40 + 23*8(%r3)
 	ld	%r10,40 + 1*8(%r3)
+	lfd	%f15,40 + 24*8(%r3)
 	ld	%r11,40 + 2*8(%r3)
+	lfd	%f16,40 + 25*8(%r3)
 	ld	%r12,40 + 3*8(%r3)
+	lfd	%f17,40 + 26*8(%r3)
 	ld	%r14,40 + 5*8(%r3)
+	lfd	%f18,40 + 27*8(%r3)
 	ld	%r15,40 + 6*8(%r3)
+	lfd	%f19,40 + 28*8(%r3)
 	ld	%r16,40 + 7*8(%r3)
+	lfd	%f20,40 + 29*8(%r3)
 	ld	%r17,40 + 8*8(%r3)
+	lfd	%f21,40 + 30*8(%r3)
 	ld	%r18,40 + 9*8(%r3)
+	lfd	%f22,40 + 31*8(%r3)
 	ld	%r19,40 + 10*8(%r3)
+	lfd	%f23,40 + 32*8(%r3)
 	ld	%r20,40 + 11*8(%r3)
+	lfd	%f24,40 + 33*8(%r3)
 	ld	%r21,40 + 12*8(%r3)
+	lfd	%f25,40 + 34*8(%r3)
 	ld	%r22,40 + 13*8(%r3)
+	lfd	%f26,40 + 35*8(%r3)
 	ld	%r23,40 + 14*8(%r3)
+	lfd	%f27,40 + 36*8(%r3)
 	ld	%r24,40 + 15*8(%r3)
+	lfd	%f28,40 + 37*8(%r3)
 	ld	%r25,40 + 16*8(%r3)
+	lfd	%f29,40 + 38*8(%r3)
 	ld	%r26,40 + 17*8(%r3)
+	lfd	%f30,40 + 39*8(%r3)
 	ld	%r27,40 + 18*8(%r3)
+	lfd	%f31,40 + 40*8(%r3)
 	ld	%r28,40 + 19*8(%r3)
 	ld	%r29,40 + 20*8(%r3)
 	ld	%r30,40 + 21*8(%r3)
diff --git a/lib/libgpio/gpio.3 b/lib/libgpio/gpio.3
index 12b2d1eeed1f..70f6b38c0622 100644
--- a/lib/libgpio/gpio.3
+++ b/lib/libgpio/gpio.3
@@ -25,7 +25,7 @@
 .\"
 .\" $FreeBSD$
 .\"
-.Dd November 17, 2014
+.Dd March 8, 2015
 .Dt GPIO 3
 .Os
 .Sh NAME
@@ -43,41 +43,43 @@
 .Ft void
 .Fn gpio_close "gpio_handle_t handle"
 .Ft int
-.Fn gpio_pin_list "gpio_handle_t handle, gpio_config_t **pcfgs"
+.Fn gpio_pin_list "gpio_handle_t handle" "gpio_config_t **pcfgs"
 .Ft int
-.Fn gpio_pin_config "gpio_handle_t handle, gpio_config *cfg"
+.Fn gpio_pin_config "gpio_handle_t handle" "gpio_config_t *cfg"
 .Ft int
-.Fn gpio_pin_set_flags "gpio_handle_t handle, gpio_config_t *cfg"
+.Fn gpio_pin_set_name "gpio_handle_t handle" "gpio_pin_t pin" "char *name"
+.Ft int
+.Fn gpio_pin_set_flags "gpio_handle_t handle" "gpio_config_t *cfg"
 .Ft gpio_value_t
-.Fn gpio_pin_get "gpio_handle_t handle, gpio_pin_t pin"
+.Fn gpio_pin_get "gpio_handle_t handle" "gpio_pin_t pin"
 .Ft int
-.Fn gpio_pin_set "gpio_handle_t handle, gpio_pin_t pin, gpio_value_t value"
+.Fn gpio_pin_set "gpio_handle_t handle" "gpio_pin_t pin" "gpio_value_t value"
 .Ft int
-.Fn gpio_pin_toggle "gpio_handle_t handle, gpio_pin_t pin"
+.Fn gpio_pin_toggle "gpio_handle_t handle" "gpio_pin_t pin"
 .Ft int
-.Fn gpio_pin_low "gpio_handle_t handle, gpio_pin_t pin"
+.Fn gpio_pin_low "gpio_handle_t handle" "gpio_pin_t pin"
 .Ft int
-.Fn gpio_pin_high "gpio_handle_t handle, gpio_pin_t pin"
+.Fn gpio_pin_high "gpio_handle_t handle" "gpio_pin_t pin"
 .Ft int
-.Fn gpio_pin_input "gpio_handle_t handle, gpio_pin_t pin"
+.Fn gpio_pin_input "gpio_handle_t handle" "gpio_pin_t pin"
 .Ft int
-.Fn gpio_pin_output "gpio_handle_t handle, gpio_pin_t pin"
+.Fn gpio_pin_output "gpio_handle_t handle" "gpio_pin_t pin"
 .Ft int
-.Fn gpio_pin_opendrain "gpio_handle_t handle, gpio_pin_t pin"
+.Fn gpio_pin_opendrain "gpio_handle_t handle" "gpio_pin_t pin"
 .Ft int
-.Fn gpio_pin_pushpull "gpio_handle_t handle, gpio_pin_t pin"
+.Fn gpio_pin_pushpull "gpio_handle_t handle" "gpio_pin_t pin"
 .Ft int
-.Fn gpio_pin_tristate "gpio_handle_t handle, gpio_pin_t pin"
+.Fn gpio_pin_tristate "gpio_handle_t handle" "gpio_pin_t pin"
 .Ft int
-.Fn gpio_pin_pullup "gpio_handle_t handle, gpio_pin_t pin"
+.Fn gpio_pin_pullup "gpio_handle_t handle" "gpio_pin_t pin"
 .Ft int
-.Fn gpio_pin_pulldown "gpio_handle_t handle, gpio_pin_t pin"
+.Fn gpio_pin_pulldown "gpio_handle_t handle" "gpio_pin_t pin"
 .Ft int
-.Fn gpio_pin_invin "gpio_handle_t handle, gpio_pin_t pin"
+.Fn gpio_pin_invin "gpio_handle_t handle" "gpio_pin_t pin"
 .Ft int
-.Fn gpio_pin_invout "gpio_handle_t handle, gpio_pin_t pin"
+.Fn gpio_pin_invout "gpio_handle_t handle" "gpio_pin_t pin"
 .Ft int
-.Fn gpio_pin_pulsate "gpio_handle_t handle, gpio_pin_t pin"
+.Fn gpio_pin_pulsate "gpio_handle_t handle" "gpio_pin_t pin"
 .Sh DESCRIPTION
 The
 .Nm libgpio
@@ -99,7 +101,7 @@ This function takes a pointer to a
 which is dynamically allocated.
 This pointer should be freed with
 .Xr free 3
-when it's no longer necessary.
+when it is no longer necessary.
 .Pp
 The function
 .Fn gpio_pin_config
@@ -111,6 +113,10 @@ variable which is part of the
 structure.
 .Pp
 The function
+.Fn gpio_pin_set_name
+sets the name used to describe a pin.
+.Pp
+The function
 .Fn gpio_pin_set_flags
 configures a pin with the flags passed in by the
 .Ft gpio_config_t
diff --git a/lib/libgpio/gpio.c b/lib/libgpio/gpio.c
index 8eb68712057a..7ec0955b096b 100644
--- a/lib/libgpio/gpio.c
+++ b/lib/libgpio/gpio.c
@@ -119,6 +119,22 @@ gpio_pin_config(gpio_handle_t handle, gpio_config_t *cfg)
 }
 
 int
+gpio_pin_set_name(gpio_handle_t handle, gpio_pin_t pin, char *name)
+{
+	struct gpio_pin gppin;
+
+	if (name == NULL)
+		return (-1);
+	bzero(&gppin, sizeof(gppin));
+	gppin.gp_pin = pin;
+	strlcpy(gppin.gp_name, name, GPIOMAXNAME);
+	if (ioctl(handle, GPIOSETNAME, &gppin) < 0)
+		return (-1);
+
+	return (0);
+}
+
+int
 gpio_pin_set_flags(gpio_handle_t handle, gpio_config_t *cfg)
 {
 	struct gpio_pin gppin;
diff --git a/lib/libgpio/libgpio.h b/lib/libgpio/libgpio.h
index b7486ebc5472..a832234ca13e 100644
--- a/lib/libgpio/libgpio.h
+++ b/lib/libgpio/libgpio.h
@@ -71,6 +71,11 @@ int		gpio_pin_list(gpio_handle_t, gpio_config_t **);
  */
 int		gpio_pin_config(gpio_handle_t, gpio_config_t *);
 /*
+ * Sets the GPIO pin name.  The pin number and pin name to be set are passed
+ * as parameters.
+ */
+int		gpio_pin_set_name(gpio_handle_t, gpio_pin_t, char *);
+/*
  * Sets the GPIO flags on a specific GPIO pin.  The pin number and the flags
  * to be set are passed through the gpio_config_t structure.
  */
diff --git a/lib/libnv/tests/dnv_tests.cc b/lib/libnv/tests/dnv_tests.cc
index 9d6987fa255d..ad26f38bb073 100644
--- a/lib/libnv/tests/dnv_tests.cc
+++ b/lib/libnv/tests/dnv_tests.cc
@@ -450,7 +450,7 @@ ATF_TEST_CASE_BODY(dnvlist_take_nvlist__empty)
 	nvl = nvlist_create(0);
 
 	actual_val = dnvlist_take_nvlist(nvl, "123", NULL);
-	ATF_REQUIRE_EQ(actual_val, NULL);
+	ATF_REQUIRE_EQ(actual_val, static_cast<nvlist_t *>(NULL));
 
 	free(actual_val);
 	nvlist_destroy(nvl);
diff --git a/lib/libnv/tests/nv_tests.cc b/lib/libnv/tests/nv_tests.cc
index 94d8b56d297b..bfdc97231274 100644
--- a/lib/libnv/tests/nv_tests.cc
+++ b/lib/libnv/tests/nv_tests.cc
@@ -54,7 +54,7 @@ ATF_TEST_CASE_BODY(nvlist_create__is_empty)
 	ATF_REQUIRE(nvlist_empty(nvl));
 
 	it = NULL;
-	ATF_REQUIRE_EQ(nvlist_next(nvl, &type, &it), NULL);
+	ATF_REQUIRE_EQ(nvlist_next(nvl, &type, &it), static_cast<const char *>(NULL));
 
 	nvlist_destroy(nvl);
 }
@@ -85,7 +85,7 @@ ATF_TEST_CASE_BODY(nvlist_add_null__single_insert)
 	it = NULL;
 	ATF_REQUIRE_EQ(strcmp(nvlist_next(nvl, &type, &it), key), 0);
 	ATF_REQUIRE_EQ(type, NV_TYPE_NULL);
-	ATF_REQUIRE_EQ(nvlist_next(nvl, &type,&it), NULL);
+	ATF_REQUIRE_EQ(nvlist_next(nvl, &type,&it), static_cast<const char *>(NULL));
 
 	nvlist_destroy(nvl);
 }
@@ -118,7 +118,7 @@ ATF_TEST_CASE_BODY(nvlist_add_bool__single_insert)
 	it = NULL;
 	ATF_REQUIRE_EQ(strcmp(nvlist_next(nvl, &type, &it), key), 0);
 	ATF_REQUIRE_EQ(type, NV_TYPE_BOOL);
-	ATF_REQUIRE_EQ(nvlist_next(nvl, &type,&it), NULL);
+	ATF_REQUIRE_EQ(nvlist_next(nvl, &type,&it), static_cast<const char *>(NULL));
 
 	nvlist_destroy(nvl);
 }
@@ -153,7 +153,7 @@ ATF_TEST_CASE_BODY(nvlist_add_number__single_insert)
 	it = NULL;
 	ATF_REQUIRE_EQ(strcmp(nvlist_next(nvl, &type, &it), key), 0);
 	ATF_REQUIRE_EQ(type, NV_TYPE_NUMBER);
-	ATF_REQUIRE_EQ(nvlist_next(nvl, &type,&it), NULL);
+	ATF_REQUIRE_EQ(nvlist_next(nvl, &type,&it), static_cast<const char *>(NULL));
 
 	nvlist_destroy(nvl);
 }
@@ -191,7 +191,7 @@ ATF_TEST_CASE_BODY(nvlist_add_string__single_insert)
 	it = NULL;
 	ATF_REQUIRE_EQ(strcmp(nvlist_next(nvl, &type, &it), key), 0);
 	ATF_REQUIRE_EQ(type, NV_TYPE_STRING);
-	ATF_REQUIRE_EQ(nvlist_next(nvl, &type,&it), NULL);
+	ATF_REQUIRE_EQ(nvlist_next(nvl, &type,&it), static_cast<const char *>(NULL));
 
 	nvlist_destroy(nvl);
 }
@@ -237,7 +237,7 @@ ATF_TEST_CASE_BODY(nvlist_add_nvlist__single_insert)
 	it = NULL;
 	ATF_REQUIRE_EQ(strcmp(nvlist_next(nvl, &type, &it), key), 0);
 	ATF_REQUIRE_EQ(type, NV_TYPE_NVLIST);
-	ATF_REQUIRE_EQ(nvlist_next(nvl, &type,&it), NULL);
+	ATF_REQUIRE_EQ(nvlist_next(nvl, &type,&it), static_cast<const char *>(NULL));
 
 	nvlist_destroy(sublist);
 	nvlist_destroy(nvl);
@@ -303,7 +303,7 @@ ATF_TEST_CASE_BODY(nvlist_add_binary__single_insert)
 	it = NULL;
 	ATF_REQUIRE_EQ(strcmp(nvlist_next(nvl, &type, &it), key), 0);
 	ATF_REQUIRE_EQ(type, NV_TYPE_BINARY);
-	ATF_REQUIRE_EQ(nvlist_next(nvl, &type,&it), NULL);
+	ATF_REQUIRE_EQ(nvlist_next(nvl, &type,&it), static_cast<const char *>(NULL));
 
 	nvlist_destroy(nvl);
 	free(value);
@@ -352,7 +352,7 @@ ATF_TEST_CASE_BODY(nvlist_clone__nonempty_nvlist)
 	it = NULL;
 	ATF_REQUIRE_EQ(strcmp(nvlist_next(clone, &type, &it), key), 0);
 	ATF_REQUIRE_EQ(type, NV_TYPE_NUMBER);
-	ATF_REQUIRE_EQ(nvlist_next(clone, &type, &it), NULL);
+	ATF_REQUIRE_EQ(nvlist_next(clone, &type, &it), static_cast<const char *>(NULL));
 
 	nvlist_destroy(clone);
 	nvlist_destroy(nvl);
@@ -400,13 +400,13 @@ verify_test_nvlist(const nvlist_t *nvl)
 	ATF_REQUIRE_EQ(strcmp(nvlist_next(value, &type, &it),
 	    test_string_key), 0);
 	ATF_REQUIRE_EQ(type, NV_TYPE_STRING);
-	ATF_REQUIRE_EQ(nvlist_next(value, &type, &it), NULL);
+	ATF_REQUIRE_EQ(nvlist_next(value, &type, &it), static_cast<const char *>(NULL));
 
 	it = NULL;
 	ATF_REQUIRE_EQ(strcmp(nvlist_next(nvl, &type, &it),
 	    test_subnvlist_key), 0);
 	ATF_REQUIRE_EQ(type, NV_TYPE_NVLIST);
-	ATF_REQUIRE_EQ(nvlist_next(nvl, &type, &it), NULL);
+	ATF_REQUIRE_EQ(nvlist_next(nvl, &type, &it), static_cast<const char *>(NULL));
 }
 
 ATF_TEST_CASE_WITHOUT_HEAD(nvlist_clone__nested_nvlist);
diff --git a/lib/libpmc/libpmc.c b/lib/libpmc/libpmc.c
index 693e97711a21..17283d8f02d4 100644
--- a/lib/libpmc/libpmc.c
+++ b/lib/libpmc/libpmc.c
@@ -325,7 +325,7 @@ PMC_CLASS_TABLE_DESC(core2, IAP, core2, iap);
 PMC_CLASS_TABLE_DESC(corei7, IAP, corei7, iap);
 PMC_CLASS_TABLE_DESC(nehalem_ex, IAP, nehalem_ex, iap);
 PMC_CLASS_TABLE_DESC(haswell, IAP, haswell, iap);
-PMC_CLASS_TABLE_DESC(haswell_xeon, IAP, haswell, iap);
+PMC_CLASS_TABLE_DESC(haswell_xeon, IAP, haswell_xeon, iap);
 PMC_CLASS_TABLE_DESC(ivybridge, IAP, ivybridge, iap);
 PMC_CLASS_TABLE_DESC(ivybridge_xeon, IAP, ivybridge_xeon, iap);
 PMC_CLASS_TABLE_DESC(sandybridge, IAP, sandybridge, iap);
diff --git a/lib/libpmc/pmc.3 b/lib/libpmc/pmc.3
index 8e6db485ae37..f51285e12586 100644
--- a/lib/libpmc/pmc.3
+++ b/lib/libpmc/pmc.3
@@ -527,6 +527,7 @@ API is
 .Xr pmc.core2 3 ,
 .Xr pmc.haswell 3 ,
 .Xr pmc.haswelluc 3 ,
+.Xr pmc.haswellxeon 3 ,
 .Xr pmc.iaf 3 ,
 .Xr pmc.ivybridge 3 ,
 .Xr pmc.ivybridgexeon 3 ,
diff --git a/lib/libpmc/pmc.haswell.3 b/lib/libpmc/pmc.haswell.3
index e535d68824db..a85f7609c9df 100644
--- a/lib/libpmc/pmc.haswell.3
+++ b/lib/libpmc/pmc.haswell.3
@@ -529,73 +529,60 @@ instruction.
 .It Li ILD_STALL.IQ_FULL
 .Pq Event 87H , Umask 04H
 Stall cycles due to IQ is full.
-.It Li BR_INST_EXEC.COND
-.Pq Event 88H , Umask 01H
-Qualify conditional near branch instructions
-executed, but not necessarily retired.
+.It Li BR_INST_EXEC.NONTAKEN_COND
+.Pq Event 88H , Umask 41H
+Count conditional near branch instructions that were executed (but not
+necessarily retired) and not taken.
+.It Li BR_INST_EXEC.TAKEN_COND
+.Pq Event 88H , Umask 81H
+Count conditional near branch instructions that were executed (but not
+necessarily retired) and taken.
 .It Li BR_INST_EXEC.DIRECT_JMP
-.Pq Event 88H , Umask 02H
-Qualify all unconditional near branch instructions
-excluding calls and indirect branches.
+.Pq Event 88H , Umask 82H
+Count all unconditional near branch instructions excluding calls and
+indirect branches.
 .It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET
-.Pq Event 88H , Umask 04H
-Qualify executed indirect near branch instructions
-that are not calls nor returns.
+.Pq Event 88H , Umask 84H
+Count executed indirect near branch instructions that are not calls nor
+returns.
 .It Li BR_INST_EXEC.RETURN_NEAR
-.Pq Event 88H , Umask 08H
-Qualify indirect near branches that have a return
-mnemonic.
+.Pq Event 88H , Umask 88H
+Count indirect near branches that have a return mnemonic.
 .It Li BR_INST_EXEC.DIRECT_NEAR_CALL
-.Pq Event 88H , Umask 10H
-Qualify unconditional near call branch instructions,
-excluding non call branch, executed.
+.Pq Event 88H , Umask 90H
+Count unconditional near call branch instructions, excluding non call
+branch, executed.
 .It Li BR_INST_EXEC.INDIRECT_NEAR_CALL
-.Pq Event 88H , Umask 20H
-Qualify indirect near calls, including both register and
-memory indirect, executed.
-.It Li BR_INST_EXEC.NONTAKEN
-.Pq Event 88H , Umask 40H
-Qualify non-taken near branches executed.
-.It Li BR_INST_EXEC.TAKEN
-.Pq Event 88H , Umask 80H
-Qualify taken near branches executed. Must combine
-with 01H,02H, 04H, 08H, 10H, 20H.
+.Pq Event 88H , Umask A0H
+Count indirect near calls, including both register and memory indirect,
+executed.
 .It Li BR_INST_EXEC.ALL_BRANCHES
 .Pq Event 88H , Umask FFH
-Counts all near executed branches (not necessarily
-retired).
-.It Li BR_MISP_EXEC.COND
-.Pq Event 89H , Umask 01H
-Qualify conditional near branch instructions
-mispredicted.
+Counts all near executed branches (not necessarily retired).
+.It Li BR_MISP_EXEC.NONTAKEN_COND
+.Pq Event 89H , Umask 41H
+Count conditional near branch instructions mispredicted as nontaken.
+.It Li BR_MISP_EXEC.TAKEN_COND
+.Pq Event 89H , Umask 81H
+Count conditional near branch instructions mispredicted as taken.
 .It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET
-.Pq Event 89H , Umask 04H
-Qualify mispredicted indirect near branch
-instructions that are not calls nor returns.
+.Pq Event 89H , Umask 84H
+Count mispredicted indirect near branch instructions that are not calls
+nor returns.
 .It Li BR_MISP_EXEC.RETURN_NEAR
-.Pq Event 89H , Umask 08H
-Qualify mispredicted indirect near branches that
-have a return mnemonic.
+.Pq Event 89H , Umask 88H
+Count mispredicted indirect near branches that have a return mnemonic.
 .It Li BR_MISP_EXEC.DIRECT_NEAR_CALL
-.Pq Event 89H , Umask 10H
-Qualify mispredicted unconditional near call branch
-instructions, excluding non call branch, executed.
+.Pq Event 89H , Umask 90H
+Count mispredicted unconditional near call branch instructions, excluding
+non call branch, executed.
 .It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL
-.Pq Event 89H , Umask 20H
-Qualify mispredicted indirect near calls, including
-both register and memory indirect, executed.
-.It Li BR_MISP_EXEC.NONTAKEN
-.Pq Event 89H , Umask 40H
-Qualify mispredicted non-taken near branches
-executed.
-.It Li BR_MISP_EXEC.TAKEN
-.Pq Event 89H , Umask 80H
-Qualify mispredicted taken near branches executed.
-Must combine with 01H,02H, 04H, 08H, 10H, 20H.
+.Pq Event 89H , Umask A0H
+Count mispredicted indirect near calls, including both register and memory
+indirect, executed.
 .It Li BR_MISP_EXEC.ALL_BRANCHES
 .Pq Event 89H , Umask FFH
-Counts all near executed branches (not necessarily
-retired).
+Counts all mispredicted near executed branches (not necessarily retired).
 .It Li IDQ_UOPS_NOT_DELIVERED.CORE
 .Pq Event 9CH , Umask 01H
 Count number of non-delivered uops to RAT per
@@ -821,30 +808,24 @@ Count cases of saving new LBR records by hardware.
 Randomly sampled loads whose latency is above a
 user defined threshold. A small fraction of the overall
 loads are sampled due to randomization.
-.It Li MEM_UOP_RETIRED.LOADS
-.Pq Event D0H , Umask 01H
-Qualify retired memory uops that are loads. Combine Supports PEBS and
-with umask 10H, 20H, 40H, 80H.
-.It Li MEM_UOP_RETIRED.STORES
-.Pq Event D0H , Umask 02H
-Qualify retired memory uops that are stores.
-Combine with umask 10H, 20H, 40H, 80H.
-.It Li MEM_UOP_RETIRED.STLB_MISS
-.Pq Event D0H , Umask 10H
-Qualify retired memory uops with STLB miss. Must
-combine with umask 01H, 02H, to produce counts.
-.It Li MEM_UOP_RETIRED.LOCK
-.Pq Event D0H , Umask 20H
-Qualify retired memory uops with lock. Must combine Supports PEBS and
-with umask 01H, 02H, to produce counts.
-.It Li MEM_UOP_RETIRED.SPLIT
-.Pq Event D0H , Umask 40H
-Qualify retired memory uops with line split. Must
-combine with umask 01H, 02H, to produce counts.
-.It Li MEM_UOP_RETIRED.ALL
-.Pq Event D0H , Umask 80H
-Qualify any retired memory uops. Must combine with Supports PEBS and
-umask 01H, 02H, to produce counts.
+.It Li MEM_UOPS_RETIRED.STLB_MISS_LOADS
+.Pq Event D0H , Umask 11H
+Count retired load uops that missed the STLB.
+.It Li MEM_UOPS_RETIRED.STLB_MISS_STORES
+.Pq Event D0H , Umask 12H
+Count retired store uops that missed the STLB.
+.It Li MEM_UOPS_RETIRED.SPLIT_LOADS
+.Pq Event D0H , Umask 41H
+Count retired load uops that were split across a cache line.
+.It Li MEM_UOPS_RETIRED.SPLIT_STORES
+.Pq Event D0H , Umask 42H
+Count retired store uops that were split across a cache line.
+.It Li MEM_UOPS_RETIRED.ALL_LOADS
+.Pq Event D0H , Umask 81H
+Count all retired load uops.
+.It Li MEM_UOPS_RETIRED.ALL_STORES
+.Pq Event D0H , Umask 82H
+Count all retired store uops.
 .It Li MEM_LOAD_UOPS_RETIRED.L1_HIT
 .Pq Event D1H , Umask 01H
 Retired load uops with L1 cache hits as data sources.
diff --git a/lib/libpmc/pmc.haswellxeon.3 b/lib/libpmc/pmc.haswellxeon.3
new file mode 100644
index 000000000000..8eb5b7e8018f
--- /dev/null
+++ b/lib/libpmc/pmc.haswellxeon.3
@@ -0,0 +1,956 @@
+.\"
+.\" Copyright (c) 2013 Hiren Panchasara <hiren.panchasara@gmail.com>
+.\" All rights reserved.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\" 1. Redistributions of source code must retain the above copyright
+.\"    notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\"    notice, this list of conditions and the following disclaimer in the
+.\"    documentation and/or other materials provided with the distribution.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+.\" ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+.\" SUCH DAMAGE.
+.\"
+.\" $FreeBSD$
+.\"
+.Dd 21 November, 2014
+.Dt PMC.HASWELLXEON 3
+.Os
+.Sh NAME
+.Nm pmc.haswellxeon
+.Nd measurement events for
+.Tn Intel
+.Tn Haswell Xeon
+family CPUs
+.Sh LIBRARY
+.Lb libpmc
+.Sh SYNOPSIS
+.In pmc.h
+.Sh DESCRIPTION
+.Tn Intel
+.Tn "Haswell"
+CPUs contain PMCs conforming to version 2 of the
+.Tn Intel
+performance measurement architecture.
+These CPUs may contain up to two classes of PMCs:
+.Bl -tag -width "Li PMC_CLASS_IAP"
+.It Li PMC_CLASS_IAF
+Fixed-function counters that count only one hardware event per counter.
+.It Li PMC_CLASS_IAP
+Programmable counters that may be configured to count one of a defined
+set of hardware events.
+.El
+.Pp
+The number of PMCs available in each class and their widths need to be
+determined at run time by calling
+.Xr pmc_cpuinfo 3 .
+.Pp
+Intel Haswell Xeon PMCs are documented in
+.Rs
+.%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual"
+.%T "Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B and 3C"
+.%N "Order Number: 325462-052US"
+.%D September 2014
+.%Q "Intel Corporation"
+.Re
+.Ss HASWELL FIXED FUNCTION PMCS
+These PMCs and their supported events are documented in
+.Xr pmc.iaf 3 .
+.Ss HASWELL PROGRAMMABLE PMCS
+The programmable PMCs support the following capabilities:
+.Bl -column "PMC_CAP_INTERRUPT" "Support"
+.It Em Capability Ta Em Support
+.It PMC_CAP_CASCADE Ta \&No
+.It PMC_CAP_EDGE Ta Yes
+.It PMC_CAP_INTERRUPT Ta Yes
+.It PMC_CAP_INVERT Ta Yes
+.It PMC_CAP_READ Ta Yes
+.It PMC_CAP_PRECISE Ta \&No
+.It PMC_CAP_SYSTEM Ta Yes
+.It PMC_CAP_TAGGING Ta \&No
+.It PMC_CAP_THRESHOLD Ta Yes
+.It PMC_CAP_USER Ta Yes
+.It PMC_CAP_WRITE Ta Yes
+.El
+.Ss Event Qualifiers
+Event specifiers for these PMCs support the following common
+qualifiers:
+.Bl -tag -width indent
+.It Li rsp= Ns Ar value
+Configure the Off-core Response bits.
+.Bl -tag -width indent
+.It Li DMND_DATA_RD
+Counts the number of demand and DCU prefetch data reads of full
+and partial cachelines as well as demand data page table entry
+cacheline reads. Does not count L2 data read prefetches or
+instruction fetches.
+.It Li REQ_DMND_RFO
+Counts the number of demand and DCU prefetch reads for ownership (RFO)
+requests generated by a write to data cacheline. Does not count L2 RFO
+prefetches.
+.It Li REQ_DMND_IFETCH
+Counts the number of demand and DCU prefetch instruction cacheline reads.
+Does not count L2 code read prefetches.
+.It Li REQ_WB
+Counts the number of writeback (modified to exclusive) transactions.
+.It Li REQ_PF_DATA_RD
+Counts the number of data cacheline reads generated by L2 prefetchers.
+.It Li REQ_PF_RFO
+Counts the number of RFO requests generated by L2 prefetchers.
+.It Li REQ_PF_IFETCH
+Counts the number of code reads generated by L2 prefetchers.
+.It Li REQ_PF_LLC_DATA_RD
+L2 prefetcher to L3 for loads.
+.It Li REQ_PF_LLC_RFO
+RFO requests generated by L2 prefetcher
+.It Li REQ_PF_LLC_IFETCH
+L2 prefetcher to L3 for instruction fetches.
+.It Li REQ_BUS_LOCKS
+Bus lock and split lock requests.
+.It Li REQ_STRM_ST
+Streaming store requests.
+.It Li REQ_OTHER
+Any other request that crosses IDI, including I/O.
+.It Li RES_ANY
+Catch all value for any response types.
+.It Li RES_SUPPLIER_NO_SUPP
+No Supplier Information available.
+.It Li RES_SUPPLIER_LLC_HITM
+M-state initial lookup stat in L3.
+.It Li RES_SUPPLIER_LLC_HITE
+E-state.
+.It Li RES_SUPPLIER_LLC_HITS
+S-state.
+.It Li RES_SUPPLIER_LLC_HITF
+F-state.
+.It Li RES_SUPPLIER_LOCAL
+Local DRAM Controller.
+.It Li RES_SNOOP_SNP_NONE
+No details on snoop-related information.
+.It Li RES_SNOOP_SNP_NO_NEEDED
+No snoop was needed to satisfy the request.
+.It Li RES_SNOOP_SNP_MISS
+A snoop was needed and it missed all snooped caches:
+-For LLC Hit, ReslHitl was returned by all cores
+-For LLC Miss, Rspl was returned by all sockets and data was returned from
+DRAM.
+.It Li RES_SNOOP_HIT_NO_FWD
+A snoop was needed and it hits in at least one snooped cache. Hit denotes a
+cache-line was valid before snoop effect. This includes:
+-Snoop Hit w/ Invalidation (LLC Hit, RFO)
+-Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD)
+-Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S)
+In the LLC Miss case, data is returned from DRAM.
+.It Li RES_SNOOP_HIT_FWD
+A snoop was needed and data was forwarded from a remote socket.
+This includes:
+-Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT).
+.It Li RES_SNOOP_HITM
+A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a
+cache-line was in modified state before effect as a results of snoop. This
+includes:
+-Snoop HitM w/ WB (LLC miss, IFetch/Data_RD)
+-Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO)
+-Snoop MtoS (LLC Hit, IFetch/Data_RD).
+.It Li RES_NON_DRAM
+Target was non-DRAM system address. This includes MMIO transactions.
+.El
+.It Li cmask= Ns Ar value
+Configure the PMC to increment only if the number of configured
+events measured in a cycle is greater than or equal to
+.Ar value .
+.It Li edge
+Configure the PMC to count the number of de-asserted to asserted
+transitions of the conditions expressed by the other qualifiers.
+If specified, the counter will increment only once whenever a
+condition becomes true, irrespective of the number of clocks during
+which the condition remains true.
+.It Li inv
+Invert the sense of comparison when the
+.Dq Li cmask
+qualifier is present, making the counter increment when the number of
+events per cycle is less than the value specified by the
+.Dq Li cmask
+qualifier.
+.It Li os
+Configure the PMC to count events happening at processor privilege
+level 0.
+.It Li usr
+Configure the PMC to count events occurring at privilege levels 1, 2
+or 3.
+.El
+.Pp
+If neither of the
+.Dq Li os
+or
+.Dq Li usr
+qualifiers are specified, the default is to enable both.
+.Ss Event Specifiers (Programmable PMCs)
+Haswell programmable PMCs support the following events:
+.Bl -tag -width indent
+.It Li LD_BLOCKS.STORE_FORWARD
+.Pq Event 03H , Umask 02H
+Loads blocked by overlapping with store buffer that
+cannot be forwarded.
+.It Li MISALIGN_MEM_REF.LOADS
+.Pq Event 05H , Umask 01H
+Speculative cache-line split load uops dispatched to
+L1D.
+.It Li MISALIGN_MEM_REF.STORES
+.Pq Event 05H , Umask 02H
+Speculative cache-line split Store-address uops
+dispatched to L1D.
+.It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS
+.Pq Event 07H , Umask 01H
+False dependencies in MOB due to partial compare
+on address.
+.It Li DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK
+.Pq Event 08H , Umask 01H
+Misses in all TLB levels that cause a page walk of any
+page size.
+.It Li DTLB_LOAD_MISSES.WALK_COMPLETED_4K
+.Pq Event 08H , Umask 02H
+Completed page walks due to demand load misses
+that caused 4K page walks in any TLB levels.
+.It Li DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4K
+.Pq Event 08H , Umask 02H
+Completed page walks due to demand load misses
+that caused 2M/4M page walks in any TLB levels.
+.It Li DTLB_LOAD_MISSES.WALK_COMPLETED
+.Pq Event 08H , Umask 0EH
+Completed page walks in any TLB of any page size
+due to demand load misses
+.It Li DTLB_LOAD_MISSES.WALK_DURATION
+.Pq Event 08H , Umask 10H
+Cycle PMH is busy with a walk.
+.It Li DTLB_LOAD_MISSES.STLB_HIT_4K
+.Pq Event 08H , Umask 20H
+Load misses that missed DTLB but hit STLB (4K).
+.It Li DTLB_LOAD_MISSES.STLB_HIT_2M
+.Pq Event 08H , Umask 40H
+Load misses that missed DTLB but hit STLB (2M).
+.It Li DTLB_LOAD_MISSES.STLB_HIT
+.Pq Event 08H , Umask 60H
+Number of cache load STLB hits. No page walk.
+.It Li DTLB_LOAD_MISSES.PDE_CACHE_MISS
+.Pq Event 08H , Umask 80H
+DTLB demand load misses with low part of linear-to-
+physical address translation missed
+.It Li INT_MISC.RECOVERY_CYCLES
+.Pq Event 0DH , Umask 03H
+Cycles waiting to recover after Machine Clears
+except JEClear. Set Cmask= 1.
+.It Li UOPS_ISSUED.ANY
+.Pq Event 0EH , Umask 01H
+ncrements each cycle the # of Uops issued by the
+RAT to RS.
+Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles
+of this core.
+.It Li UOPS_ISSUED.FLAGS_MERGE
+.Pq Event 0EH , Umask 10H
+Number of flags-merge uops allocated. Such uops
+adds delay.
+.It Li UOPS_ISSUED.SLOW_LEA
+.Pq Event 0EH , Umask 20H
+Number of slow LEA or similar uops allocated. Such
+uop has 3 sources (e.g. 2 sources + immediate)
+regardless if as a result of LEA instruction or not.
+.It Li UOPS_ISSUED.SiNGLE_MUL
+.Pq Event 0EH , Umask 40H
+Number of multiply packed/scalar single precision
+uops allocated.
+.It Li L2_RQSTS.DEMAND_DATA_RD_MISS
+.Pq Event 24H , Umask 21H
+Demand Data Read requests that missed L2, no
+rejects.
+.It Li L2_RQSTS.DEMAND_DATA_RD_HIT
+.Pq Event 24H , Umask 41H
+Demand Data Read requests that hit L2 cache.
+.It Li L2_RQSTS.ALL_DEMAND_DATA_RD
+.Pq Event 24H , Umask E1H	
+Counts any demand and L1 HW prefetch data load
+requests to L2.
+.It Li L2_RQSTS.RFO_HIT
+.Pq Event 24H , Umask 42H
+Counts the number of store RFO requests that hit
+the L2 cache.
+.It Li L2_RQSTS.RFO_MISS
+.Pq Event 24H , Umask 22H
+Counts the number of store RFO requests that miss
+the L2 cache.
+.It Li L2_RQSTS.ALL_RFO
+.Pq Event 24H , Umask E2H
+Counts all L2 store RFO requests.
+.It Li L2_RQSTS.CODE_RD_HIT
+.Pq Event 24H , Umask 44H
+Number of instruction fetches that hit the L2 cache.
+.It Li L2_RQSTS.CODE_RD_MISS
+.Pq Event 24H , Umask 24H
+Number of instruction fetches that missed the L2
+cache.
+.It Li L2_RQSTS.ALL_DEMAND_MISS
+.Pq Event 24H , Umask 27H
+Demand requests that miss L2 cache.
+.It Li L2_RQSTS.ALL_DEMAND_REFERENCES
+.Pq Event 24H , Umask E7H
+Demand requests to L2 cache.
+.It Li L2_RQSTS.ALL_CODE_RD
+.Pq Event 24H , Umask E4H
+Counts all L2 code requests.
+.It Li L2_RQSTS.L2_PF_HIT
+.Pq Event 24H , Umask 50H
+Counts all L2 HW prefetcher requests that hit L2.
+.It Li L2_RQSTS.L2_PF_MISS
+.Pq Event 24H , Umask 30H
+Counts all L2 HW prefetcher requests that missed
+L2.
+.It Li L2_RQSTS.ALL_PF
+.Pq Event 24H , Umask F8H
+Counts all L2 HW prefetcher requests.
+.It Li L2_RQSTS.MISS
+.Pq Event 24H , Umask 3FH
+All requests that missed L2.
+.It Li L2_RQSTS.REFERENCES
+.Pq Event 24H , Umask FFH
+All requests to L2 cache.
+.It Li L2_DEMAND_RQSTS.WB_HIT
+.Pq Event 27H , Umask 50H
+Not rejected writebacks that hit L2 cache
+.It Li LONGEST_LAT_CACHE.REFERENCE
+.Pq Event 2EH , Umask 4FH
+This event counts requests originating from the core
+that reference a cache line in the last level cache.
+.It Li LONGEST_LAT_CACHE.MISS
+.Pq Event 2EH , Umask 41H
+This event counts each cache miss condition for
+references to the last level cache.
+.It Li CPU_CLK_UNHALTED.THREAD_P
+.Pq Event 3CH , Umask 00H
+Counts the number of thread cycles while the thread
+is not in a halt state. The thread enters the halt state
+when it is running the HLT instruction. The core
+frequency may change from time to time due to
+power or thermal throttling.
+.It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK
+.Pq Event 3CH , Umask 01H
+Increments at the frequency of XCLK (100 MHz)
+when not halted.
+.It Li L1D_PEND_MISS.PENDING
+.Pq Event 48H , Umask 01H
+Increments the number of outstanding L1D misses
+every cycle. Set Cmaks = 1 and Edge =1 to count
+occurrences.
+.It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK
+.Pq Event 49H , Umask 01H
+Miss in all TLB levels causes an page walk of any
+page size (4K/2M/4M/1G).
+.It Li DTLB_STORE_MISSES.WALK_COMPLETED_4K
+.Pq Event 49H , Umask 02H
+Completed page walks due to store misses in one or
+more TLB levels of 4K page structure.
+.It Li DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M
+.Pq Event 49H , Umask 04H
+Completed page walks due to store misses in one or
+more TLB levels of 2M/4M page structure.
+.It Li DTLB_STORE_MISSES.WALK_COMPLETED
+.Pq Event 49H , Umask 0EH
+Completed page walks due to store miss in any TLB
+levels of any page size (4K/2M/4M/1G).
+.It Li DTLB_STORE_MISSES.WALK_DURATION
+.Pq Event 49H , Umask 10H
+Cycles PMH is busy with this walk.
+.It Li DTLB_STORE_MISSES.STLB_HIT_4K
+.Pq Event 49H , Umask 20H
+Store misses that missed DTLB but hit STLB (4K).
+.It Li DTLB_STORE_MISSES.STLB_HIT_2M
+.Pq Event 49H , Umask 40H
+Store misses that missed DTLB but hit STLB (2M).
+.It Li DTLB_STORE_MISSES.STLB_HIT
+.Pq Event 49H , Umask 60H
+Store operations that miss the first TLB level but hit
+the second and do not cause page walks.
+.It Li DTLB_STORE_MISSES.PDE_CACHE_MISS
+.Pq Event 49H , Umask 80H
+DTLB store misses with low part of linear-to-physical
+address translation missed.
+.It Li LOAD_HIT_PRE.SW_PF
+.Pq Event 4CH , Umask 01H
+Non-SW-prefetch load dispatches that hit fill buffer
+allocated for S/W prefetch.
+.It Li LOAD_HIT_PRE.HW_PF
+.Pq Event 4CH , Umask 02H
+Non-SW-prefetch load dispatches that hit fill buffer
+allocated for H/W prefetch.
+.It Li L1D.REPLACEMENT
+.Pq Event 51H , Umask 01H
+Counts the number of lines brought into the L1 data
+cache.
+.It Li MOVE_ELIMINATION.INT_NOT_ELIMINATED
+.Pq Event 58H , Umask 04H
+Number of integer Move Elimination candidate uops
+that were not eliminated.
+.It Li MOVE_ELIMINATION.SMID_NOT_ELIMINATED
+.Pq Event 58H , Umask 08H
+Number of SIMD Move Elimination candidate uops
+that were not eliminated.
+.It Li MOVE_ELIMINATION.INT_ELIMINATED
+.Pq Event 58H , Umask 01H
+Unhalted core cycles when the thread is in ring 0.
+.It Li MOVE_ELIMINATION.SMID_ELIMINATED
+.Pq Event 58H , Umask 02H
+Number of SIMD Move Elimination candidate uops
+that were eliminated.
+.It Li CPL_CYCLES.RING0
+.Pq Event 5CH , Umask 02H
+Unhalted core cycles when the thread is in ring 0.
+.It Li CPL_CYCLES.RING123
+.Pq Event 5CH , Umask 01H
+Unhalted core cycles when the thread is not in ring 0.
+.It Li RS_EVENTS.EMPTY_CYCLES
+.Pq Event 5EH , Umask 01H
+Cycles the RS is empty for the thread.
+.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD
+.Pq Event 60H , Umask 01H
+Offcore outstanding Demand Data Read transactions
+in SQ to uncore. Set Cmask=1 to count cycles.
+.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CORE_RD
+.Pq Event 60H , Umask 02H
+Offcore outstanding Demand code Read transactions
+in SQ to uncore. Set Cmask=1 to count cycles.
+.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO
+.Pq Event 60H , Umask 04H
+Offcore outstanding RFO store transactions in SQ to
+uncore. Set Cmask=1 to count cycles.
+.It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD
+.Pq Event 60H , Umask 08H
+Offcore outstanding cacheable data read
+transactions in SQ to uncore. Set Cmask=1 to count
+cycles.
+.It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION
+.Pq Event 63H , Umask 01H
+Cycles in which the L1D and L2 are locked, due to a
+UC lock or split lock.
+.It Li LOCK_CYCLES.CACHE_LOCK_DURATION
+.Pq Event 63H , Umask 02H
+Cycles in which the L1D is locked.
+.It Li IDQ.EMPTY
+.Pq Event 79H , Umask 02H
+Counts cycles the IDQ is empty.
+.It Li IDQ.MITE_UOPS
+.Pq Event 79H , Umask 04H
+Increment each cycle # of uops delivered to IDQ from
+MITE path.
+Set Cmask = 1 to count cycles.
+.It Li IDQ.DSB_UOPS
+.Pq Event 79H , Umask 08H
+Increment each cycle. # of uops delivered to IDQ
+from DSB path.
+Set Cmask = 1 to count cycles.
+.It Li IDQ.MS_DSB_UOPS
+.Pq Event 79H , Umask 10H
+Increment each cycle # of uops delivered to IDQ
+when MS_busy by DSB. Set Cmask = 1 to count
+cycles. Add Edge=1 to count # of delivery.
+.It Li IDQ.MS_MITE_UOPS
+.Pq Event 79H , Umask 20H
+ncrement each cycle # of uops delivered to IDQ
+when MS_busy by MITE. Set Cmask = 1 to count
+cycles.
+.It Li IDQ.MS_UOPS
+.Pq Event 79H , Umask 30H
+Increment each cycle # of uops delivered to IDQ from
+MS by either DSB or MITE. Set Cmask = 1 to count
+cycles.
+.It Li IDQ.ALL_DSB_CYCLES_ANY_UOPS
+.Pq Event 79H , Umask 18H
+Counts cycles DSB is delivered at least one uops. Set
+Cmask = 1.
+.It Li IDQ.ALL_DSB_CYCLES_4_UOPS
+.Pq Event 79H , Umask 18H
+Counts cycles DSB is delivered four uops. Set Cmask
+=4.
+.It Li IDQ.ALL_MITE_CYCLES_ANY_UOPS
+.Pq Event 79H , Umask 24H
+Counts cycles MITE is delivered at least one uops. Set
+Cmask = 1.
+.It Li IDQ.ALL_MITE_CYCLES_4_UOPS
+.Pq Event 79H , Umask 24H
+Counts cycles MITE is delivered four uops. Set Cmask
+=4.
+.It Li IDQ.MITE_ALL_UOPS
+.Pq Event 79H , Umask 3CH
+# of uops delivered to IDQ from any path.
+.It Li ICACHE.MISSES
+.Pq Event 80H , Umask 02H
+Number of Instruction Cache, Streaming Buffer and
+Victim Cache Misses. Includes UC accesses.
+.It Li ITLB_MISSES.MISS_CAUSES_A_WALK
+.Pq Event 85H , Umask 01H
+Misses in ITLB that causes a page walk of any page
+size.
+.It Li ITLB_MISSES.WALK_COMPLETED_4K
+.Pq Event 85H , Umask 02H
+Completed page walks due to misses in ITLB 4K page
+entries.
+.It Li TLB_MISSES.WALK_COMPLETED_2M_4M
+.Pq Event 85H , Umask 04H
+Completed page walks due to misses in ITLB 2M/4M
+page entries.
+.It Li ITLB_MISSES.WALK_COMPLETED
+.Pq Event 85H , Umask 0EH
+Completed page walks in ITLB of any page size.
+.It Li ITLB_MISSES.WALK_DURATION
+.Pq Event 85H , Umask 10H
+Cycle PMH is busy with a walk.
+.It Li ITLB_MISSES.STLB_HIT_4K
+.Pq Event 85H , Umask 20H
+ITLB misses that hit STLB (4K).
+.It Li ITLB_MISSES.STLB_HIT_2M
+.Pq Event 85H , Umask 40H
+ITLB misses that hit STLB (2K).
+.It Li ITLB_MISSES.STLB_HIT
+.Pq Event 85H , Umask 60H
+TLB misses that hit STLB. No page walk.
+.It Li ILD_STALL.LCP
+.Pq Event 87H , Umask 01H
+Stalls caused by changing prefix length of the
+instruction.
+.It Li ILD_STALL.IQ_FULL
+.Pq Event 87H , Umask 04H
+Stall cycles due to IQ is full.
+.It Li BR_INST_EXEC.NONTAKEN_COND
+.Pq Event 88H , Umask 41H
+Count conditional near branch instructions that were executed (but not
+necessarily retired) and not taken.
+.It Li BR_INST_EXEC.TAKEN_COND
+.Pq Event 88H , Umask 81H
+Count conditional near branch instructions that were executed (but not
+necessarily retired) and taken.
+.It Li BR_INST_EXEC.DIRECT_JMP
+.Pq Event 88H , Umask 82H
+Count all unconditional near branch instructions excluding calls and
+indirect branches.
+.It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET
+.Pq Event 88H , Umask 84H
+Count executed indirect near branch instructions that are not calls nor
+returns.
+.It Li BR_INST_EXEC.RETURN_NEAR
+.Pq Event 88H , Umask 88H
+Count indirect near branches that have a return mnemonic.
+.It Li BR_INST_EXEC.DIRECT_NEAR_CALL
+.Pq Event 88H , Umask 90H
+Count unconditional near call branch instructions, excluding non call
+branch, executed.
+.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL
+.Pq Event 88H , Umask A0H
+Count indirect near calls, including both register and memory indirect,
+executed.
+.It Li BR_INST_EXEC.ALL_BRANCHES
+.Pq Event 88H , Umask FFH
+Counts all near executed branches (not necessarily retired).
+.It Li BR_MISP_EXEC.NONTAKEN_COND
+.Pq Event 89H , Umask 41H
+Count conditional near branch instructions mispredicted as nontaken.
+.It Li BR_MISP_EXEC.TAKEN_COND
+.Pq Event 89H , Umask 81H
+Count conditional near branch instructions mispredicted as taken.
+.It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET
+.Pq Event 89H , Umask 84H
+Count mispredicted indirect near branch instructions that are not calls
+nor returns.
+.It Li BR_MISP_EXEC.RETURN_NEAR
+.Pq Event 89H , Umask 88H
+Count mispredicted indirect near branches that have a return mnemonic.
+.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL
+.Pq Event 89H , Umask 90H
+Count mispredicted unconditional near call branch instructions, excluding
+non call branch, executed.
+.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL
+.Pq Event 89H , Umask A0H
+Count mispredicted indirect near calls, including both register and memory
+indirect, executed.
+.It Li BR_MISP_EXEC.ALL_BRANCHES
+.Pq Event 89H , Umask FFH
+Counts all mispredicted near executed branches (not necessarily retired).
+.It Li IDQ_UOPS_NOT_DELIVERED.CORE
+.Pq Event 9CH , Umask 01H
+Count number of non-delivered uops to RAT per
+thread.
+.It Li UOPS_EXECUTED_PORT.PORT_0
+.Pq Event A1H , Umask 01H
+Cycles which a Uop is dispatched on port 0 in this
+thread.
+.It Li UOPS_EXECUTED_PORT.PORT_1
+.Pq Event A1H , Umask 02H
+Cycles which a Uop is dispatched on port 1 in this
+thread.
+.It Li UOPS_EXECUTED_PORT.PORT_2
+.Pq Event A1H , Umask 04H
+Cycles which a Uop is dispatched on port 2 in this
+thread.
+.It Li UOPS_EXECUTED_PORT.PORT_3
+.Pq Event A1H , Umask 08H
+Cycles which a Uop is dispatched on port 3 in this
+thread.
+.It Li UOPS_EXECUTED_PORT.PORT_4
+.Pq Event A1H , Umask 10H
+Cycles which a Uop is dispatched on port 4 in this
+thread.
+.It Li UOPS_EXECUTED_PORT.PORT_5
+.Pq Event A1H , Umask 20H
+Cycles which a Uop is dispatched on port 5 in this
+thread.
+.It Li UOPS_EXECUTED_PORT.PORT_6
+.Pq Event A1H , Umask 40H
+Cycles which a Uop is dispatched on port 6 in this
+thread.
+.It Li UOPS_EXECUTED_PORT.PORT_7
+.Pq Event A1H , Umask 80H
+Cycles which a Uop is dispatched on port 7 in this
+thread.
+.It Li RESOURCE_STALLS.ANY
+.Pq Event A2H , Umask 01H
+Cycles Allocation is stalled due to Resource Related
+reason.
+.It Li RESOURCE_STALLS.RS
+.Pq Event A2H , Umask 04H
+Cycles stalled due to no eligible RS entry available.
+.It Li RESOURCE_STALLS.SB
+.Pq Event A2H , Umask 08H
+Cycles stalled due to no store buffers available (not
+including draining form sync).
+.It Li RESOURCE_STALLS.ROB
+.Pq Event A2H , Umask 10H
+Cycles stalled due to re-order buffer full.
+.It Li CYCLE_ACTIVITY.CYCLES_L2_PENDING
+.Pq Event A3H , Umask 01H
+Cycles with pending L2 miss loads. Set Cmask=2 to
+count cycle.
+.It Li CYCLE_ACTIVITY.CYCLES_LDM_PENDING
+.Pq Event A3H , Umask 02H
+Cycles with pending memory loads. Set Cmask=2 to
+count cycle.
+.It Li CYCLE_ACTIVITY.STALLS_L2_PENDING
+.Pq Event A3H , Umask 05H
+Number of loads missed L2.
+.It Li CYCLE_ACTIVITY.CYCLES_L1D_PENDING
+.Pq Event A3H , Umask 08H
+Cycles with pending L1 cache miss loads. Set
+Cmask=8 to count cycle.
+.It Li ITLB.ITLB_FLUSH
+.Pq Event AEH , Umask 01H
+Counts the number of ITLB flushes, includes
+4k/2M/4M pages.
+.It Li OFFCORE_REQUESTS.DEMAND_DATA_RD
+.Pq Event B0H , Umask 01H
+Demand data read requests sent to uncore.
+.It Li OFFCORE_REQUESTS.DEMAND_CODE_RD
+.Pq Event B0H , Umask 02H
+Demand code read requests sent to uncore.
+.It Li OFFCORE_REQUESTS.DEMAND_RFO
+.Pq Event B0H , Umask 04H
+Demand RFO read requests sent to uncore, including
+regular RFOs, locks, ItoM.
+.It Li OFFCORE_REQUESTS.ALL_DATA_RD
+.Pq Event B0H , Umask 08H
+Data read requests sent to uncore (demand and
+prefetch).
+.It Li UOPS_EXECUTED.CORE
+.Pq Event B1H , Umask 02H
+Counts total number of uops to be executed per-core
+each cycle.
+.It Li OFF_CORE_RESPONSE_0
+.Pq Event B7H , Umask 01H
+Requires MSR 01A6H
+.It Li OFF_CORE_RESPONSE_1
+.Pq Event BBH , Umask 01H
+Requires MSR 01A7H
+.It Li PAGE_WALKER_LOADS.DTLB_L1
+.Pq Event BCH , Umask 11H
+Number of DTLB page walker loads that hit in the
+L1+FB.
+.It Li PAGE_WALKER_LOADS.ITLB_L1
+.Pq Event BCH , Umask 21H
+Number of ITLB page walker loads that hit in the
+L1+FB.
+.It Li PAGE_WALKER_LOADS.DTLB_L2
+.Pq Event BCH , Umask 12H
+Number of DTLB page walker loads that hit in the L2.
+.It Li PAGE_WALKER_LOADS.ITLB_L2
+.Pq Event BCH , Umask 22H
+Number of ITLB page walker loads that hit in the L2.
+.It Li PAGE_WALKER_LOADS.DTLB_L3
+.Pq Event BCH , Umask 14H
+Number of DTLB page walker loads that hit in the L3.
+.It Li PAGE_WALKER_LOADS.ITLB_L3
+.Pq Event BCH , Umask 24H
+Number of ITLB page walker loads that hit in the L3.
+.It Li PAGE_WALKER_LOADS.DTLB_MEMORY
+.Pq Event BCH , Umask 18H
+Number of DTLB page walker loads from memory.
+.It Li PAGE_WALKER_LOADS.ITLB_MEMORY
+.Pq Event BCH , Umask 28H
+Number of ITLB page walker loads from memory.
+.It Li TLB_FLUSH.DTLB_THREAD
+.Pq Event BDH , Umask 01H
+DTLB flush attempts of the thread-specific entries.
+.It Li TLB_FLUSH.STLB_ANY
+.Pq Event BDH , Umask 20H
+Count number of STLB flush attempts.
+.It Li INST_RETIRED.ANY_P
+.Pq Event C0H , Umask 00H
+Number of instructions at retirement.
+.It Li INST_RETIRED.ALL
+.Pq Event C0H , Umask 01H
+Precise instruction retired event with HW to reduce
+effect of PEBS shadow in IP distribution.
+.It Li OTHER_ASSISTS.AVX_TO_SSE
+.Pq Event C1H , Umask 08H
+Number of transitions from AVX-256 to legacy SSE
+when penalty applicable.
+.It Li OTHER_ASSISTS.SSE_TO_AVX
+.Pq Event C1H , Umask 10H
+Number of transitions from SSE to AVX-256 when
+penalty applicable.
+.It Li OTHER_ASSISTS.ANY_WB_ASSIST
+.Pq Event C1H , Umask 40H
+Number of microcode assists invoked by HW upon
+uop writeback.
+.It Li UOPS_RETIRED.ALL
+.Pq Event C2H , Umask 01H
+Counts the number of micro-ops retired, Use
+cmask=1 and invert to count active cycles or stalled
+cycles.
+.It Li UOPS_RETIRED.RETIRE_SLOTS
+.Pq Event C2H , Umask 02H
+Counts the number of retirement slots used each
+cycle.
+.It Li MACHINE_CLEARS.MEMORY_ORDERING
+.Pq Event C3H , Umask 02H
+Counts the number of machine clears due to memory
+order conflicts.
+.It Li MACHINE_CLEARS.SMC
+.Pq Event C3H , Umask 04H
+Number of self-modifying-code machine clears
+detected.
+.It Li MACHINE_CLEARS.MASKMOV
+.Pq Event C3H , Umask 20H
+Counts the number of executed AVX masked load
+operations that refer to an illegal address range with
+the mask bits set to 0.
+.It Li BR_INST_RETIRED.ALL_BRANCHES
+.Pq Event C4H , Umask 00H
+Branch instructions at retirement.
+.It Li BR_INST_RETIRED.CONDITIONAL
+.Pq Event C4H , Umask 01H
+Counts the number of conditional branch instructions Supports PEBS
+retired.
+.It Li BR_INST_RETIRED.NEAR_CALL
+.Pq Event C4H , Umask 02H
+Direct and indirect near call instructions retired.
+.It Li BR_INST_RETIRED.ALL_BRANCHES
+.Pq Event C4H , Umask 04H
+Counts the number of branch instructions retired.
+.It Li BR_INST_RETIRED.NEAR_RETURN
+.Pq Event C4H , Umask 08H
+Counts the number of near return instructions
+retired.
+.It Li BR_INST_RETIRED.NOT_TAKEN
+.Pq Event C4H , Umask 10H
+Counts the number of not taken branch instructions
+retired.
+ It Li BR_INST_RETIRED.NEAR_TAKEN
+.Pq Event C4H , Umask 20H
+Number of near taken branches retired.
+.It Li BR_INST_RETIRED.FAR_BRANCH
+.Pq Event C4H , Umask 40H
+Number of far branches retired.
+.It Li BR_MISP_RETIRED.ALL_BRANCHES
+.Pq Event C5H , Umask 00H
+Mispredicted branch instructions at retirement
+.It Li BR_MISP_RETIRED.CONDITIONAL
+.Pq Event C5H , Umask 01H
+Mispredicted conditional branch instructions retired.
+.It Li BR_MISP_RETIRED.CONDITIONAL
+.Pq Event C5H , Umask 04H
+Mispredicted macro branch instructions retired.
+.It Li FP_ASSIST.X87_OUTPUT
+.Pq Event CAH , Umask 02H
+Number of X87 FP assists due to Output values.
+.It Li FP_ASSIST.X87_INPUT
+.Pq Event CAH , Umask 04H
+Number of X87 FP assists due to input values.
+.It Li FP_ASSIST.SIMD_OUTPUT
+.Pq Event CAH , Umask 08H
+Number of SIMD FP assists due to Output values.
+.It Li FP_ASSIST.SIMD_INPUT
+.Pq Event CAH , Umask 10H
+Number of SIMD FP assists due to input values.
+.It Li FP_ASSIST.ANY
+.Pq Event CAH , Umask 1EH
+Cycles with any input/output SSE* or FP assists.
+.It Li ROB_MISC_EVENTS.LBR_INSERTS
+.Pq Event CCH , Umask 20H
+Count cases of saving new LBR records by hardware.
+.It Li MEM_TRANS_RETIRED.LOAD_LATENCY
+.Pq Event CDH , Umask 01H
+Randomly sampled loads whose latency is above a
+user defined threshold. A small fraction of the overall
+loads are sampled due to randomization.
+.It Li MEM_UOPS_RETIRED.STLB_MISS_LOADS
+.Pq Event D0H , Umask 11H
+Count retired load uops that missed the STLB.
+.It Li MEM_UOPS_RETIRED.STLB_MISS_STORES
+.Pq Event D0H , Umask 12H
+Count retired store uops that missed the STLB.
+.It Li MEM_UOPS_RETIRED.SPLIT_LOADS
+.Pq Event D0H , Umask 41H
+Count retired load uops that were split across a cache line.
+.It Li MEM_UOPS_RETIRED.SPLIT_STORES
+.Pq Event D0H , Umask 42H
+Count retired store uops that were split across a cache line.
+.It Li MEM_UOPS_RETIRED.ALL_LOADS
+.Pq Event D0H , Umask 81H
+Count all retired load uops.
+.It Li MEM_UOPS_RETIRED.ALL_STORES
+.Pq Event D0H , Umask 82H
+Count all retired store uops.
+.It Li MEM_LOAD_UOPS_RETIRED.L1_HIT
+.Pq Event D1H , Umask 01H
+Retired load uops with L1 cache hits as data sources.
+.It Li MEM_LOAD_UOPS_RETIRED.L2_HIT
+.Pq Event D1H , Umask 02H
+Retired load uops with L2 cache hits as data sources.
+.It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT
+.Pq Event D1H , Umask 04H
+Retired load uops with LLC cache hits as data
+sources.
+.It Li MEM_LOAD_UOPS_RETIRED.L2_MISS
+.Pq Event D1H , Umask 10H
+Retired load uops missed L2. Unknown data source
+excluded.
+.It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB
+.Pq Event D1H , Umask 40H
+Retired load uops which data sources were load uops
+missed L1 but hit FB due to preceding miss to the
+same cache line with data not ready.
+.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS
+.Pq Event D2H , Umask 01H
+Retired load uops which data sources were LLC hit
+and cross-core snoop missed in on-pkg core cache.
+.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT
+.Pq Event D2H , Umask 02H
+Retired load uops which data sources were LLC and
+cross-core snoop hits in on-pkg core cache.
+.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM
+.Pq Event D2H , Umask 04H
+Retired load uops which data sources were HitM
+responses from shared LLC.
+.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE
+.Pq Event D2H , Umask 08H
+Retired load uops which data sources were hits in
+LLC without snoops required.
+.It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM
+.Pq Event D3H , Umask 01H
+Retired load uops which data sources missed LLC but
+serviced from local dram.
+.It Li BACLEARS.ANY
+.Pq Event E6H , Umask 1FH
+Number of front end re-steers due to BPU
+misprediction.
+.It Li L2_TRANS.DEMAND_DATA_RD
+.Pq Event F0H , Umask 01H
+Demand Data Read requests that access L2 cache.
+.It Li L2_TRANS.RFO
+.Pq Event F0H , Umask 02H
+RFO requests that access L2 cache.
+.It Li L2_TRANS.CODE_RD
+.Pq Event F0H , Umask 04H
+L2 cache accesses when fetching instructions.
+.It Li L2_TRANS.ALL_PF
+.Pq Event F0H , Umask 08H
+Any MLC or LLC HW prefetch accessing L2, including
+rejects.
+.It Li L2_TRANS.L1D_WB
+.Pq Event F0H , Umask 10H
+L1D writebacks that access L2 cache.
+.It Li L2_TRANS.L2_FILL
+.Pq Event F0H , Umask 20H
+L2 fill requests that access L2 cache.
+.It Li L2_TRANS.L2_WB
+.Pq Event F0H , Umask 40H
+L2 writebacks that access L2 cache.
+.It Li L2_TRANS.ALL_REQUESTS
+.Pq Event F0H , Umask 80H
+Transactions accessing L2 pipe.
+.It Li L2_LINES_IN.I
+.Pq Event F1H , Umask 01H
+L2 cache lines in I state filling L2.
+.It Li L2_LINES_IN.S
+.Pq Event F1H , Umask 02H
+L2 cache lines in S state filling L2.
+.It Li L2_LINES_IN.E
+.Pq Event F1H , Umask 04H
+L2 cache lines in E state filling L2.
+.It Li L2_LINES_IN.ALL
+.Pq Event F1H , Umask 07H
+L2 cache lines filling L2.
+.It Li L2_LINES_OUT.DEMAND_CLEAN
+.Pq Event F2H , Umask 05H
+Clean L2 cache lines evicted by demand.
+.It Li L2_LINES_OUT.DEMAND_DIRTY
+.Pq Event F2H , Umask 06H
+Dirty L2 cache lines evicted by demand.
+.El
+.Sh SEE ALSO
+.Xr pmc 3 ,
+.Xr pmc.atom 3 ,
+.Xr pmc.core 3 ,
+.Xr pmc.iaf 3 ,
+.Xr pmc.ucf 3 ,
+.Xr pmc.k7 3 ,
+.Xr pmc.k8 3 ,
+.Xr pmc.p4 3 ,
+.Xr pmc.p5 3 ,
+.Xr pmc.p6 3 ,
+.Xr pmc.corei7 3 ,
+.Xr pmc.corei7uc 3 ,
+.Xr pmc.haswell 3 ,
+.Xr pmc.haswelluc 3 ,
+.Xr pmc.ivybridge 3 ,
+.Xr pmc.ivybridgexeon 3 ,
+.Xr pmc.sandybridge 3 ,
+.Xr pmc.sandybridgeuc 3 ,
+.Xr pmc.sandybridgexeon 3 ,
+.Xr pmc.westmere 3 ,
+.Xr pmc.westmereuc 3 ,
+.Xr pmc.soft 3 ,
+.Xr pmc.tsc 3 ,
+.Xr pmc_cpuinfo 3 ,
+.Xr pmclog 3 ,
+.Xr hwpmc 4
+.Sh HISTORY
+Support for the Haswell Xeon microarchitecture first appeared in
+.Fx 10.2 .
+.Sh AUTHORS
+The
+.Lb libpmc
+library was written by
+.An "Joseph Koshy"
+.Aq jkoshy@FreeBSD.org .
+The support for the Haswell Xeon
+microarchitecture was written by
+.An "Randall Stewart"
+.Aq rrs@FreeBSD.org .
diff --git a/lib/libpmc/pmc.ivybridge.3 b/lib/libpmc/pmc.ivybridge.3
index a4d9f949845b..b693b30ca73b 100644
--- a/lib/libpmc/pmc.ivybridge.3
+++ b/lib/libpmc/pmc.ivybridge.3
@@ -449,80 +449,60 @@ Stalls caused by changing prefix length of the instruction.
 .It Li ILD_STALL.IQ_FULL
 .Pq Event 87H , Umask 04H
 Stall cycles due to IQ is full.
-.It Li BR_INST_EXEC.COND
-.Pq Event 88H , Umask 01H
-Qualify conditional near branch instructions executed, but not necessarily
-retired.
-Must combine with umask 40H, 80H.
+.It Li BR_INST_EXEC.NONTAKEN_COND
+.Pq Event 88H , Umask 41H
+Count conditional near branch instructions that were executed (but not
+necessarily retired) and not taken.
+.It Li BR_INST_EXEC.TAKEN_COND
+.Pq Event 88H , Umask 81H
+Count conditional near branch instructions that were executed (but not
+necessarily retired) and taken.
 .It Li BR_INST_EXEC.DIRECT_JMP
-.Pq Event 88H , Umask 02H
-Qualify all unconditional near branch instructions excluding calls and
+.Pq Event 88H , Umask 82H
+Count all unconditional near branch instructions excluding calls and
 indirect branches.
-Must combine with umask 80H.
 .It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET
-.Pq Event 88H , Umask 04H
-Qualify executed indirect near branch instructions that are not calls nor
+.Pq Event 88H , Umask 84H
+Count executed indirect near branch instructions that are not calls nor
 returns.
-Must combine with umask 80H.
 .It Li BR_INST_EXEC.RETURN_NEAR
-.Pq Event 88H , Umask 08H
-Qualify indirect near branches that have a return mnemonic.
-Must combine with umask 80H.
+.Pq Event 88H , Umask 88H
+Count indirect near branches that have a return mnemonic.
 .It Li BR_INST_EXEC.DIRECT_NEAR_CALL
-.Pq Event 88H , Umask 10H
-Qualify unconditional near call branch instructions, excluding non call
+.Pq Event 88H , Umask 90H
+Count unconditional near call branch instructions, excluding non call
 branch, executed.
-Must combine with umask 80H.
 .It Li BR_INST_EXEC.INDIRECT_NEAR_CALL
-.Pq Event 88H , Umask 20H
-Qualify indirect near calls, including both register and memory indirect,
+.Pq Event 88H , Umask A0H
+Count indirect near calls, including both register and memory indirect,
 executed.
-Must combine with umask 80H.
-.It Li BR_INST_EXEC.NONTAKEN
-.Pq Event 88H , Umask 40H
-Qualify non-taken near branches executed.
-Applicable to umask 01H only.
-.It Li BR_INST_EXEC.TAKEN
-.Pq Event 88H , Umask 80H
-Qualify taken near branches executed. Must combine with 01H,02H, 04H, 08H,
-10H, 20H.
 .It Li BR_INST_EXEC.ALL_BRANCHES
 .Pq Event 88H , Umask FFH
 Counts all near executed branches (not necessarily retired).
-.It Li BR_MISP_EXEC.COND
-.Pq Event 89H , Umask 01H
-Qualify conditional near branch instructions mispredicted.
-Must combine with umask 40H, 80H.
+.It Li BR_MISP_EXEC.NONTAKEN_COND
+.Pq Event 89H , Umask 41H
+Count conditional near branch instructions mispredicted as nontaken.
+.It Li BR_MISP_EXEC.TAKEN_COND
+.Pq Event 89H , Umask 81H
+Count conditional near branch instructions mispredicted as taken.
 .It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET
-.Pq Event 89H , Umask 04H
-Qualify mispredicted indirect near branch instructions that are not calls
+.Pq Event 89H , Umask 84H
+Count mispredicted indirect near branch instructions that are not calls
 nor returns.
-Must combine with umask 80H.
 .It Li BR_MISP_EXEC.RETURN_NEAR
-.Pq Event 89H , Umask 08H
-Qualify mispredicted indirect near branches that have a return mnemonic.
-Must combine with umask 80H.
+.Pq Event 89H , Umask 88H
+Count mispredicted indirect near branches that have a return mnemonic.
 .It Li BR_MISP_EXEC.DIRECT_NEAR_CALL
-.Pq Event 89H , Umask 10H
-Qualify mispredicted unconditional near call branch instructions, excluding
+.Pq Event 89H , Umask 90H
+Count mispredicted unconditional near call branch instructions, excluding
 non call branch, executed.
-Must combine with umask 80H.
 .It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL
-.Pq Event 89H , Umask 20H
-Qualify mispredicted indirect near calls, including both register and memory
+.Pq Event 89H , Umask A0H
+Count mispredicted indirect near calls, including both register and memory
 indirect, executed.
-Must combine with umask 80H.
-.It Li BR_MISP_EXEC.NONTAKEN
-.Pq Event 89H , Umask 40H
-Qualify mispredicted non-taken near branches executed.
-Applicable to umask 01H only.
-.It Li BR_MISP_EXEC.TAKEN
-.Pq Event 89H , Umask 80H
-Qualify mispredicted taken near branches executed. Must combine with
-01H,02H, 04H, 08H, 10H, 20H.
 .It Li BR_MISP_EXEC.ALL_BRANCHES
 .Pq Event 89H , Umask FFH
-Counts all near executed branches (not necessarily retired).
+Counts all mispredicted near executed branches (not necessarily retired).
 .It Li IDQ_UOPS_NOT_DELIVERED.CORE
 .Pq Event 9CH , Umask 01H
 Count number of non-delivered uops to RAT per thread.
@@ -726,31 +706,24 @@ Specify threshold in MSR 0x3F6.
 .Pq Event CDH , Umask 02H
 Sample stores and collect precise store operation via PEBS record.
 PMC3 only.
-.It Li MEM_UOP_RETIRED.LOADS
-.Pq Event D0H , Umask 01H
-Qualify retired memory uops that are loads. Combine with umask 10H, 20H,
-40H, 80H.
-Supports PEBS.
-.It Li MEM_UOP_RETIRED.STORES
-.Pq Event D0H , Umask 02H
-Qualify retired memory uops that are stores. Combine with umask 10H, 20H,
-40H, 80H.
-.It Li MEM_UOP_RETIRED.STLB_MISS
-.Pq Event D0H , Umask 10H
-Qualify retired memory uops with STLB miss. Must combine with umask 01H,
-02H, to produce counts.
-.It Li MEM_UOP_RETIRED.LOCK
-.Pq Event D0H , Umask 20H
-Qualify retired memory uops with lock. Must combine with umask 01H, 02H, to
-produce counts.
-.It Li MEM_UOP_RETIRED.SPLIT
-.Pq Event D0H , Umask 40H
-Qualify retired memory uops with line split. Must combine with umask 01H,
-02H, to produce counts.
-.It Li MEM_UOP_RETIRED.ALL
-.Pq Event D0H , Umask 80H
-Qualify any retired memory uops. Must combine with umask 01H, 02H, to
-produce counts.
+.It Li MEM_UOPS_RETIRED.STLB_MISS_LOADS
+.Pq Event D0H , Umask 11H
+Count retired load uops that missed the STLB.
+.It Li MEM_UOPS_RETIRED.STLB_MISS_STORES
+.Pq Event D0H , Umask 12H
+Count retired store uops that missed the STLB.
+.It Li MEM_UOPS_RETIRED.SPLIT_LOADS
+.Pq Event D0H , Umask 41H
+Count retired load uops that were split across a cache line.
+.It Li MEM_UOPS_RETIRED.SPLIT_STORES
+.Pq Event D0H , Umask 42H
+Count retired store uops that were split across a cache line.
+.It Li MEM_UOPS_RETIRED.ALL_LOADS
+.Pq Event D0H , Umask 81H
+Count all retired load uops.
+.It Li MEM_UOPS_RETIRED.ALL_STORES
+.Pq Event D0H , Umask 82H
+Count all retired store uops.
 .It Li MEM_LOAD_UOPS_RETIRED.L1_HIT
 .Pq Event D1H , Umask 01H
 Retired load uops with L1 cache hits as data sources.
diff --git a/lib/libpmc/pmc.ivybridgexeon.3 b/lib/libpmc/pmc.ivybridgexeon.3
index 31a4caa6e342..2ee5b782cc42 100644
--- a/lib/libpmc/pmc.ivybridgexeon.3
+++ b/lib/libpmc/pmc.ivybridgexeon.3
@@ -449,80 +449,60 @@ Stalls caused by changing prefix length of the instruction.
 .It Li ILD_STALL.IQ_FULL
 .Pq Event 87H , Umask 04H
 Stall cycles due to IQ is full.
-.It Li BR_INST_EXEC.COND
-.Pq Event 88H , Umask 01H
-Qualify conditional near branch instructions executed, but not necessarily
-retired.
-Must combine with umask 40H, 80H.
+.It Li BR_INST_EXEC.NONTAKEN_COND
+.Pq Event 88H , Umask 41H
+Count conditional near branch instructions that were executed (but not
+necessarily retired) and not taken.
+.It Li BR_INST_EXEC.TAKEN_COND
+.Pq Event 88H , Umask 81H
+Count conditional near branch instructions that were executed (but not
+necessarily retired) and taken.
 .It Li BR_INST_EXEC.DIRECT_JMP
-.Pq Event 88H , Umask 02H
-Qualify all unconditional near branch instructions excluding calls and
+.Pq Event 88H , Umask 82H
+Count all unconditional near branch instructions excluding calls and
 indirect branches.
-Must combine with umask 80H.
 .It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET
-.Pq Event 88H , Umask 04H
-Qualify executed indirect near branch instructions that are not calls nor
+.Pq Event 88H , Umask 84H
+Count executed indirect near branch instructions that are not calls nor
 returns.
-Must combine with umask 80H.
 .It Li BR_INST_EXEC.RETURN_NEAR
-.Pq Event 88H , Umask 08H
-Qualify indirect near branches that have a return mnemonic.
-Must combine with umask 80H.
+.Pq Event 88H , Umask 88H
+Count indirect near branches that have a return mnemonic.
 .It Li BR_INST_EXEC.DIRECT_NEAR_CALL
-.Pq Event 88H , Umask 10H
-Qualify unconditional near call branch instructions, excluding non call
+.Pq Event 88H , Umask 90H
+Count unconditional near call branch instructions, excluding non call
 branch, executed.
-Must combine with umask 80H.
 .It Li BR_INST_EXEC.INDIRECT_NEAR_CALL
-.Pq Event 88H , Umask 20H
-Qualify indirect near calls, including both register and memory indirect,
+.Pq Event 88H , Umask A0H
+Count indirect near calls, including both register and memory indirect,
 executed.
-Must combine with umask 80H.
-.It Li BR_INST_EXEC.NONTAKEN
-.Pq Event 88H , Umask 40H
-Qualify non-taken near branches executed.
-Applicable to umask 01H only.
-.It Li BR_INST_EXEC.TAKEN
-.Pq Event 88H , Umask 80H
-Qualify taken near branches executed. Must combine with 01H,02H, 04H, 08H,
-10H, 20H.
 .It Li BR_INST_EXEC.ALL_BRANCHES
 .Pq Event 88H , Umask FFH
 Counts all near executed branches (not necessarily retired).
-.It Li BR_MISP_EXEC.COND
-.Pq Event 89H , Umask 01H
-Qualify conditional near branch instructions mispredicted.
-Must combine with umask 40H, 80H.
+.It Li BR_MISP_EXEC.NONTAKEN_COND
+.Pq Event 89H , Umask 41H
+Count conditional near branch instructions mispredicted as nontaken.
+.It Li BR_MISP_EXEC.TAKEN_COND
+.Pq Event 89H , Umask 81H
+Count conditional near branch instructions mispredicted as taken.
 .It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET
-.Pq Event 89H , Umask 04H
-Qualify mispredicted indirect near branch instructions that are not calls
+.Pq Event 89H , Umask 84H
+Count mispredicted indirect near branch instructions that are not calls
 nor returns.
-Must combine with umask 80H.
 .It Li BR_MISP_EXEC.RETURN_NEAR
-.Pq Event 89H , Umask 08H
-Qualify mispredicted indirect near branches that have a return mnemonic.
-Must combine with umask 80H.
+.Pq Event 89H , Umask 88H
+Count mispredicted indirect near branches that have a return mnemonic.
 .It Li BR_MISP_EXEC.DIRECT_NEAR_CALL
-.Pq Event 89H , Umask 10H
-Qualify mispredicted unconditional near call branch instructions, excluding
+.Pq Event 89H , Umask 90H
+Count mispredicted unconditional near call branch instructions, excluding
 non call branch, executed.
-Must combine with umask 80H.
 .It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL
-.Pq Event 89H , Umask 20H
-Qualify mispredicted indirect near calls, including both register and memory
+.Pq Event 89H , Umask A0H
+Count mispredicted indirect near calls, including both register and memory
 indirect, executed.
-Must combine with umask 80H.
-.It Li BR_MISP_EXEC.NONTAKEN
-.Pq Event 89H , Umask 40H
-Qualify mispredicted non-taken near branches executed.
-Applicable to umask 01H only.
-.It Li BR_MISP_EXEC.TAKEN
-.Pq Event 89H , Umask 80H
-Qualify mispredicted taken near branches executed. Must combine with
-01H,02H, 04H, 08H, 10H, 20H.
 .It Li BR_MISP_EXEC.ALL_BRANCHES
 .Pq Event 89H , Umask FFH
-Counts all near executed branches (not necessarily retired).
+Counts all mispredicted near executed branches (not necessarily retired).
 .It Li IDQ_UOPS_NOT_DELIVERED.CORE
 .Pq Event 9CH , Umask 01H
 Count number of non-delivered uops to RAT per thread.
@@ -738,31 +718,24 @@ Specify threshold in MSR 0x3F6.
 .Pq Event CDH , Umask 02H
 Sample stores and collect precise store operation via PEBS record.
 PMC3 only.
-.It Li MEM_UOP_RETIRED.LOADS
-.Pq Event D0H , Umask 01H
-Qualify retired memory uops that are loads. Combine with umask 10H, 20H,
-40H, 80H.
-Supports PEBS.
-.It Li MEM_UOP_RETIRED.STORES
-.Pq Event D0H , Umask 02H
-Qualify retired memory uops that are stores. Combine with umask 10H, 20H,
-40H, 80H.
-.It Li MEM_UOP_RETIRED.STLB_MISS
-.Pq Event D0H , Umask 10H
-Qualify retired memory uops with STLB miss. Must combine with umask 01H,
-02H, to produce counts.
-.It Li MEM_UOP_RETIRED.LOCK
-.Pq Event D0H , Umask 20H
-Qualify retired memory uops with lock. Must combine with umask 01H, 02H, to
-produce counts.
-.It Li MEM_UOP_RETIRED.SPLIT
-.Pq Event D0H , Umask 40H
-Qualify retired memory uops with line split. Must combine with umask 01H,
-02H, to produce counts.
-.It Li MEM_UOP_RETIRED.ALL
-.Pq Event D0H , Umask 80H
-Qualify any retired memory uops. Must combine with umask 01H, 02H, to
-produce counts.
+.It Li MEM_UOPS_RETIRED.STLB_MISS_LOADS
+.Pq Event D0H , Umask 11H
+Count retired load uops that missed the STLB.
+.It Li MEM_UOPS_RETIRED.STLB_MISS_STORES
+.Pq Event D0H , Umask 12H
+Count retired store uops that missed the STLB.
+.It Li MEM_UOPS_RETIRED.SPLIT_LOADS
+.Pq Event D0H , Umask 41H
+Count retired load uops that were split across a cache line.
+.It Li MEM_UOPS_RETIRED.SPLIT_STORES
+.Pq Event D0H , Umask 42H
+Count retired store uops that were split across a cache line.
+.It Li MEM_UOPS_RETIRED.ALL_LOADS
+.Pq Event D0H , Umask 81H
+Count all retired load uops.
+.It Li MEM_UOPS_RETIRED.ALL_STORES
+.Pq Event D0H , Umask 82H
+Count all retired store uops.
 .It Li MEM_LOAD_UOPS_RETIRED.L1_HIT
 .Pq Event D1H , Umask 01H
 Retired load uops with L1 cache hits as data sources.
diff --git a/lib/libpmc/pmc.sandybridge.3 b/lib/libpmc/pmc.sandybridge.3
index 0b8f6b2f09a9..0e219ae3aeaa 100644
--- a/lib/libpmc/pmc.sandybridge.3
+++ b/lib/libpmc/pmc.sandybridge.3
@@ -497,80 +497,60 @@ Stalls caused by changing prefix length of the instruction.
 .It Li ILD_STALL.IQ_FULL
 .Pq Event 87H, Umask 04H
 Stall cycles due to IQ is full.
-.It Li BR_INST_EXEC.COND
-.Pq Event 88H, Umask 01H
-Qualify conditional near branch instructions executed, but not necessarily
-retired.
-Must combine with umask 40H, 80H
+.It Li BR_INST_EXEC.NONTAKEN_COND
+.Pq Event 88H , Umask 41H
+Count conditional near branch instructions that were executed (but not
+necessarily retired) and not taken.
+.It Li BR_INST_EXEC.TAKEN_COND
+.Pq Event 88H , Umask 81H
+Count conditional near branch instructions that were executed (but not
+necessarily retired) and taken.
 .It Li BR_INST_EXEC.DIRECT_JMP
-.Pq Event 88H, Umask 02H
-Qualify all unconditional near branch instructions excluding calls and indirect
-branches.
-Must combine with umask 80H
+.Pq Event 88H , Umask 82H
+Count all unconditional near branch instructions excluding calls and
+indirect branches.
 .It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET
-.Pq Event 88H, Umask 04H
-Qualify executed indirect near branch instructions that are not calls nor
+.Pq Event 88H , Umask 84H
+Count executed indirect near branch instructions that are not calls nor
 returns.
-Must combine with umask 80H
 .It Li BR_INST_EXEC.RETURN_NEAR
-.Pq Event 88H, Umask 08H
-Qualify indirect near branches that have a return mnemonic.
-Must combine with umask 80H
+.Pq Event 88H , Umask 88H
+Count indirect near branches that have a return mnemonic.
 .It Li BR_INST_EXEC.DIRECT_NEAR_CALL
-.Pq Event 88H, Umask 10H
-Qualify unconditional near call branch instructions, excluding non call branch,
-executed.
-Must combine with umask 80H
+.Pq Event 88H , Umask 90H
+Count unconditional near call branch instructions, excluding non call
+branch, executed.
 .It Li BR_INST_EXEC.INDIRECT_NEAR_CALL
-.Pq Event 88H, Umask 20H
-Qualify indirect near calls, including both register and memory indirect,
+.Pq Event 88H , Umask A0H
+Count indirect near calls, including both register and memory indirect,
 executed.
-Must combine with umask 80H
-.It Li BR_INST_EXEC.NONTAKEN
-.Pq Event 88H, Umask 40H
-Qualify non-taken near branches executed.
-Applicable to umask 01H only
-.It Li BR_INST_EXEC.TAKEN
-.Pq Event 88H, Umask 80H
-Qualify taken near branches executed.
-Must combine with 01H,02H, 04H, 08H, 10H, 20H
-.It Li BR_INST_EXE.ALL_BRANCHES
-.Pq Event 88H, Umask FFH
+.It Li BR_INST_EXEC.ALL_BRANCHES
+.Pq Event 88H , Umask FFH
 Counts all near executed branches (not necessarily retired).
-.It Li BR_MISP_EXEC.COND
-.Pq Event 89H, Umask 01H
-Qualify conditional near branch instructions mispredicted.
-Must combine with umask 40H, 80H
+.It Li BR_MISP_EXEC.NONTAKEN_COND
+.Pq Event 89H , Umask 41H
+Count conditional near branch instructions mispredicted as nontaken.
+.It Li BR_MISP_EXEC.TAKEN_COND
+.Pq Event 89H , Umask 81H
+Count conditional near branch instructions mispredicted as taken.
 .It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET
-.Pq Event 89H, Umask 04H
-Qualify mispredicted indirect near branch instructions that are not calls nor
-returns.
-Must combine with umask 80H
+.Pq Event 89H , Umask 84H
+Count mispredicted indirect near branch instructions that are not calls
+nor returns.
 .It Li BR_MISP_EXEC.RETURN_NEAR
-.Pq Event 89H, Umask 08H
-Qualify mispredicted indirect near branches that have a return mnemonic.
-Must combine with umask 80H
+.Pq Event 89H , Umask 88H
+Count mispredicted indirect near branches that have a return mnemonic.
 .It Li BR_MISP_EXEC.DIRECT_NEAR_CALL
-.Pq Event 89H, Umask 10H
-Qualify mispredicted unconditional near call branch instructions, excluding non
-call branch, executed.
-Must combine with umask 80H
+.Pq Event 89H , Umask 90H
+Count mispredicted unconditional near call branch instructions, excluding
+non call branch, executed.
 .It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL
-.Pq Event 89H, Umask 20H
-Qualify mispredicted indirect near calls, including both register and memory
+.Pq Event 89H , Umask A0H
+Count mispredicted indirect near calls, including both register and memory
 indirect, executed.
-Must combine with umask 80H
-.It Li BR_MISP_EXEC.NONTAKEN
-.Pq Event 89H, Umask 40H
-Qualify mispredicted non-taken near branches executed.
-Applicable to umask 01H only
-.It Li BR_MISP_EXEC.TAKEN
-.Pq Event 89H, Umask 80H
-Qualify mispredicted taken near branches executed.
-Must combine with 01H,02H, 04H, 08H, 10H, 20H
 .It Li BR_MISP_EXEC.ALL_BRANCHES
-.Pq Event 89H, Umask FFH
-Counts all near executed branches (not necessarily retired).
+.Pq Event 89H , Umask FFH
+Counts all mispredicted near executed branches (not necessarily retired).
 .It Li IDQ_UOPS_NOT_DELIVERED.CORE
 .Pq Event 9CH, Umask 01H
 Count number of non-delivered uops to RAT per thread.
diff --git a/lib/libpmc/pmc.sandybridgexeon.3 b/lib/libpmc/pmc.sandybridgexeon.3
index 17a1bf9fcd67..b334c16265fa 100644
--- a/lib/libpmc/pmc.sandybridgexeon.3
+++ b/lib/libpmc/pmc.sandybridgexeon.3
@@ -543,73 +543,60 @@ instruction.
 .It Li ILD_STALL.IQ_FULL
 .Pq Event 87H , Umask 04H
 Stall cycles due to IQ is full.
-.It Li BR_INST_EXEC.COND
-.Pq Event 88H , Umask 01H
-Qualify conditional near branch instructions
-executed, but not necessarily retired.
+.It Li BR_INST_EXEC.NONTAKEN_COND
+.Pq Event 88H , Umask 41H
+Count conditional near branch instructions that were executed (but not
+necessarily retired) and not taken.
+.It Li BR_INST_EXEC.TAKEN_COND
+.Pq Event 88H , Umask 81H
+Count conditional near branch instructions that were executed (but not
+necessarily retired) and taken.
 .It Li BR_INST_EXEC.DIRECT_JMP
-.Pq Event 88H , Umask 02H
-Qualify all unconditional near branch instructions
-excluding calls and indirect branches.
+.Pq Event 88H , Umask 82H
+Count all unconditional near branch instructions excluding calls and
+indirect branches.
 .It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET
-.Pq Event 88H , Umask 04H
-Qualify executed indirect near branch instructions
-that are not calls nor returns.
+.Pq Event 88H , Umask 84H
+Count executed indirect near branch instructions that are not calls nor
+returns.
 .It Li BR_INST_EXEC.RETURN_NEAR
-.Pq Event 88H , Umask 08H
-Qualify indirect near branches that have a return
-mnemonic.
+.Pq Event 88H , Umask 88H
+Count indirect near branches that have a return mnemonic.
 .It Li BR_INST_EXEC.DIRECT_NEAR_CALL
-.Pq Event 88H , Umask 10H
-Qualify unconditional near call branch instructions,
-excluding non call branch, executed.
+.Pq Event 88H , Umask 90H
+Count unconditional near call branch instructions, excluding non call
+branch, executed.
 .It Li BR_INST_EXEC.INDIRECT_NEAR_CALL
-.Pq Event 88H , Umask 20H
-Qualify indirect near calls, including both register
-and memory indirect, executed.
-.It Li BR_INST_EXEC.NONTAKEN
-.Pq Event 88H , Umask 40H
-Qualify non-taken near branches executed.
-.It Li BR_INST_EXEC.TAKEN
-.Pq Event 88H , Umask 80H
-Qualify taken near branches executed. Must
-combine with 01H,02H, 04H, 08H, 10H, 20H.
-.It Li BR_INST_EXE.ALL_BRANCHES
+.Pq Event 88H , Umask A0H
+Count indirect near calls, including both register and memory indirect,
+executed.
+.It Li BR_INST_EXEC.ALL_BRANCHES
 .Pq Event 88H , Umask FFH
-Counts all near executed branches (not necessarily
-retired).
-.It Li BR_MISP_EXEC.COND
-.Pq Event 89H , Umask 01H
-Qualify conditional near branch instructions
-mispredicted.
+Counts all near executed branches (not necessarily retired).
+.It Li BR_MISP_EXEC.NONTAKEN_COND
+.Pq Event 89H , Umask 41H
+Count conditional near branch instructions mispredicted as nontaken.
+.It Li BR_MISP_EXEC.TAKEN_COND
+.Pq Event 89H , Umask 81H
+Count conditional near branch instructions mispredicted as taken.
 .It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET
-.Pq Event 89H , Umask 04H
-Qualify mispredicted indirect near branch
-instructions that are not calls nor returns.
+.Pq Event 89H , Umask 84H
+Count mispredicted indirect near branch instructions that are not calls
+nor returns.
 .It Li BR_MISP_EXEC.RETURN_NEAR
-.Pq Event 89H , Umask 08H
-Qualify mispredicted indirect near branches that
-have a return mnemonic.
+.Pq Event 89H , Umask 88H
+Count mispredicted indirect near branches that have a return mnemonic.
 .It Li BR_MISP_EXEC.DIRECT_NEAR_CALL
-.Pq Event 89H , Umask 10H
-Qualify mispredicted unconditional near call branch
-instructions, excluding non call branch, executed.
+.Pq Event 89H , Umask 90H
+Count mispredicted unconditional near call branch instructions, excluding
+non call branch, executed.
 .It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL
-.Pq Event 89H , Umask 20H
-Qualify mispredicted indirect near calls, including
-both register and memory indirect, executed.
-.It Li BR_MISP_EXEC.NONTAKEN
-.Pq Event 89H , Umask 40H
-Qualify mispredicted non-taken near branches
-executed,.
-.It Li BR_MISP_EXEC.TAKEN
-.Pq Event 89H , Umask 80H
-Qualify mispredicted taken near branches executed.
-Must combine with 01H,02H, 04H, 08H, 10H, 20H
+.Pq Event 89H , Umask A0H
+Count mispredicted indirect near calls, including both register and memory
+indirect, executed.
 .It Li BR_MISP_EXEC.ALL_BRANCHES
 .Pq Event 89H , Umask FFH
-Counts all near executed branches (not necessarily
-retired).
+Counts all mispredicted near executed branches (not necessarily retired).
 .It Li IDQ_UOPS_NOT_DELIVERED.CORE
 .Pq Event 9CH , Umask 01H
 Count number of non-delivered uops to RAT per
diff --git a/lib/libstand/Makefile b/lib/libstand/Makefile
index fad9aa603c45..4a1fa2cca729 100644
--- a/lib/libstand/Makefile
+++ b/lib/libstand/Makefile
@@ -80,7 +80,6 @@ SRCS+=	aeabi_memcmp.S aeabi_memcpy.S aeabi_memmove.S aeabi_memset.S
 .if ${MACHINE_CPUARCH} == "powerpc"
 .PATH: ${.CURDIR}/../libc/quad
 SRCS+=	ashldi3.c ashrdi3.c
-.PATH: ${.CURDIR}/../libc/powerpc/gen
 SRCS+=	syncicache.c
 .endif
 
@@ -89,11 +88,7 @@ SRCS+=	syncicache.c
 SRCS+= uuid_equal.c uuid_is_nil.c
 
 # _setjmp/_longjmp
-.if ${MACHINE_ARCH} == "powerpc64"
-.PATH: ${.CURDIR}/powerpc
-.else
 .PATH: ${.CURDIR}/${MACHINE_CPUARCH}
-.endif
 SRCS+=	_setjmp.S
 
 # decompression functionality from libbz2
diff --git a/lib/libstand/powerpc/_setjmp.S b/lib/libstand/powerpc/_setjmp.S
index 3884b114274c..7c7c24b1237c 100644
--- a/lib/libstand/powerpc/_setjmp.S
+++ b/lib/libstand/powerpc/_setjmp.S
@@ -42,7 +42,7 @@
 #define JMP_xer	24*REGWIDTH
 #define JMP_sig	25*REGWIDTH
 
-ASENTRY_NOPROF(setjmp)
+ASENTRY_NOPROF(_setjmp)
 	ST_REG 31, JMP_r31(3)
 	/* r1, r2, r14-r30 */
 	ST_REG 1,  JMP_r1 (3)
@@ -79,7 +79,7 @@ ASENTRY_NOPROF(setjmp)
 
 
 .extern sigsetmask
-ASENTRY_NOPROF(longjmp)
+ASENTRY_NOPROF(_longjmp)
 	LD_REG 31, JMP_r31(3)
 	/* r1, r2, r14-r30 */
 	LD_REG 1,  JMP_r1 (3)
diff --git a/lib/libstand/powerpc/syncicache.c b/lib/libstand/powerpc/syncicache.c
new file mode 100644
index 000000000000..434dcec63416
--- /dev/null
+++ b/lib/libstand/powerpc/syncicache.c
@@ -0,0 +1,103 @@
+/*-
+ * Copyright (C) 1995-1997, 1999 Wolfgang Solfrank.
+ * Copyright (C) 1995-1997, 1999 TooLs GmbH.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by TooLs GmbH.
+ * 4. The name of TooLs GmbH may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $NetBSD: syncicache.c,v 1.2 1999/05/05 12:36:40 tsubai Exp $
+ */
+
+#ifndef lint
+static const char rcsid[] =
+  "$FreeBSD$";
+#endif /* not lint */
+
+#include <sys/param.h>
+#if	defined(_KERNEL) || defined(_STANDALONE)
+#include <sys/time.h>
+#include <sys/proc.h>
+#include <vm/vm.h>
+#endif
+#include <sys/sysctl.h>
+
+#include <machine/cpu.h>
+#include <machine/md_var.h>
+
+#ifdef _STANDALONE
+int cacheline_size = 32;
+#endif
+
+#if	!defined(_KERNEL) && !defined(_STANDALONE)
+#include <stdlib.h>
+
+int cacheline_size = 0;
+
+static void getcachelinesize(void);
+
+static void
+getcachelinesize()
+{
+	static int	cachemib[] = { CTL_MACHDEP, CPU_CACHELINE };
+	int		clen;
+
+	clen = sizeof(cacheline_size);
+
+	if (sysctl(cachemib, sizeof(cachemib) / sizeof(cachemib[0]),
+	    &cacheline_size, &clen, NULL, 0) < 0 || !cacheline_size) {
+		abort();
+	}
+}
+#endif
+
+void
+__syncicache(void *from, int len)
+{
+	int	l, off;
+	char	*p;
+
+#if	!defined(_KERNEL) && !defined(_STANDALONE)
+	if (!cacheline_size)
+		getcachelinesize();
+#endif	
+
+	off = (u_int)from & (cacheline_size - 1);
+	l = len += off;
+	p = (char *)from - off;
+
+	do {
+		__asm __volatile ("dcbst 0,%0" :: "r"(p));
+		p += cacheline_size;
+	} while ((l -= cacheline_size) > 0);
+	__asm __volatile ("sync");
+	p = (char *)from - off;
+	do {
+		__asm __volatile ("icbi 0,%0" :: "r"(p));
+		p += cacheline_size;
+	} while ((len -= cacheline_size) > 0);
+	__asm __volatile ("sync; isync");
+}
+
diff --git a/lib/libthr/thread/thr_private.h b/lib/libthr/thread/thr_private.h
index 3cfbc6333dc6..ed24c3899123 100644
--- a/lib/libthr/thread/thr_private.h
+++ b/lib/libthr/thread/thr_private.h
@@ -337,7 +337,7 @@ struct pthread_key {
 
 /*
  * lwpid_t is 32bit but kernel thr API exports tid as long type
- * in very earily date.
+ * to preserve the ABI for M:N model in very early date (r131431).
  */
 #define TID(thread)	((uint32_t) ((thread)->tid))
 
diff --git a/lib/msun/man/j0.3 b/lib/msun/man/j0.3
index 91849da47a2f..7e1b79058e2e 100644
--- a/lib/msun/man/j0.3
+++ b/lib/msun/man/j0.3
@@ -28,7 +28,7 @@
 .\"     from: @(#)j0.3	6.7 (Berkeley) 4/19/91
 .\" $FreeBSD$
 .\"
-.Dd February 18, 2008
+.Dd March 10, 2015
 .Dt J0 3
 .Os
 .Sh NAME
@@ -77,24 +77,17 @@
 The functions
 .Fn j0 ,
 .Fn j0f ,
-.Fn j1
+.Fn j1 ,
 and
 .Fn j1f
-compute the
-.Em Bessel function of the first kind of the order
-0 and the
-.Em order
-1, respectively,
-for the
-real value
+compute the Bessel function of the first kind of orders
+0 and 1 for the real value
 .Fa x ;
 the functions
 .Fn jn
 and
 .Fn jnf
-compute the
-.Em Bessel function of the first kind of the integer
-.Em order
+compute the Bessel function of the first kind of the integer order
 .Fa n
 for the real value
 .Fa x .
@@ -105,13 +98,8 @@ The functions
 .Fn y1 ,
 and
 .Fn y1f
-compute the linearly independent
-.Em Bessel function of the second kind of the order
-0 and the
-.Em order
-1, respectively,
-for the
-positive
+compute the linearly independent Bessel function of the second kind 
+of orders 0 and 1 for the positive
 .Em real
 value
 .Fa x ;
@@ -119,9 +107,7 @@ the functions
 .Fn yn
 and
 .Fn ynf
-compute the
-.Em Bessel function of the second kind for the integer
-.Em order
+compute the Bessel function of the second kind for the integer order
 .Fa n
 for the positive
 .Em real
@@ -141,11 +127,20 @@ and
 .Fn ynf .
 If
 .Fa x
-is negative, these routines will generate an invalid exception and
-return \*(Na.
+is negative, including -\*(If, these routines will generate an invalid
+exception and return \*(Na.
+If
+.Fa x
+is \*(Pm0, these routines
+will generate a divide-by-zero exception and return -\*(If.
 If
 .Fa x
-is 0 or a sufficiently small positive number, these routines
+is a sufficiently small positive number, then 
+.Fn y1 ,
+.Fn y1f ,
+.Fn yn ,
+and
+.Fn ynf 
 will generate an overflow exception and return -\*(If.
 .Sh SEE ALSO
 .Xr math 3
diff --git a/lib/msun/src/e_j0.c b/lib/msun/src/e_j0.c
index 9e269e79cf1c..365ffe5ee4bb 100644
--- a/lib/msun/src/e_j0.c
+++ b/lib/msun/src/e_j0.c
@@ -64,6 +64,8 @@ __FBSDID("$FreeBSD$");
 
 static double pzero(double), qzero(double);
 
+static const volatile double vone = 1, vzero = 0;
+
 static const double
 huge 	= 1e300,
 one	= 1.0,
@@ -150,10 +152,16 @@ __ieee754_y0(double x)
 
 	EXTRACT_WORDS(hx,lx,x);
         ix = 0x7fffffff&hx;
-    /* Y0(NaN) is NaN, y0(-inf) is Nan, y0(inf) is 0  */
-	if(ix>=0x7ff00000) return  one/(x+x*x); 
-        if((ix|lx)==0) return -one/zero;
-        if(hx<0) return zero/zero;
+	/*
+	 * y0(NaN) = NaN.
+	 * y0(Inf) = 0.
+	 * y0(-Inf) = NaN and raise invalid exception.
+	 */
+	if(ix>=0x7ff00000) return vone/(x+x*x); 
+	/* y0(+-0) = -inf and raise divide-by-zero exception. */
+	if((ix|lx)==0) return -one/vzero;
+	/* y0(x<0) = NaN and raise invalid exception. */
+	if(hx<0) return vzero/vzero;
         if(ix >= 0x40000000) {  /* |x| >= 2.0 */
         /* y0(x) = sqrt(2/(pi*x))*(p0(x)*sin(x0)+q0(x)*cos(x0))
          * where x0 = x-pi/4
diff --git a/lib/msun/src/e_j0f.c b/lib/msun/src/e_j0f.c
index 0479957c9dbf..e86ed640b3c4 100644
--- a/lib/msun/src/e_j0f.c
+++ b/lib/msun/src/e_j0f.c
@@ -16,11 +16,17 @@
 #include <sys/cdefs.h>
 __FBSDID("$FreeBSD$");
 
+/*
+ * See e_j0.c for complete comments.
+ */
+
 #include "math.h"
 #include "math_private.h"
 
 static float pzerof(float), qzerof(float);
 
+static const volatile float vone = 1,  vzero = 0;
+
 static const float
 huge 	= 1e30,
 one	= 1.0,
@@ -107,10 +113,9 @@ __ieee754_y0f(float x)
 
 	GET_FLOAT_WORD(hx,x);
         ix = 0x7fffffff&hx;
-    /* Y0(NaN) is NaN, y0(-inf) is Nan, y0(inf) is 0  */
-	if(ix>=0x7f800000) return  one/(x+x*x);
-        if(ix==0) return -one/zero;
-        if(hx<0) return zero/zero;
+	if(ix>=0x7f800000) return  vone/(x+x*x);
+	if(ix==0) return -one/vzero;
+	if(hx<0) return vzero/vzero;
         if(ix >= 0x40000000) {  /* |x| >= 2.0 */
         /* y0(x) = sqrt(2/(pi*x))*(p0(x)*sin(x0)+q0(x)*cos(x0))
          * where x0 = x-pi/4
diff --git a/lib/msun/src/e_j1.c b/lib/msun/src/e_j1.c
index 2dc0ba1c7f2b..49220586122c 100644
--- a/lib/msun/src/e_j1.c
+++ b/lib/msun/src/e_j1.c
@@ -64,6 +64,8 @@ __FBSDID("$FreeBSD$");
 
 static double pone(double), qone(double);
 
+static const volatile double vone = 1, vzero = 0;
+
 static const double
 huge    = 1e300,
 one	= 1.0,
@@ -147,10 +149,16 @@ __ieee754_y1(double x)
 
 	EXTRACT_WORDS(hx,lx,x);
         ix = 0x7fffffff&hx;
-    /* if Y1(NaN) is NaN, Y1(-inf) is NaN, Y1(inf) is 0 */
-	if(ix>=0x7ff00000) return  one/(x+x*x); 
-        if((ix|lx)==0) return -one/zero;
-        if(hx<0) return zero/zero;
+	/*
+	 * y1(NaN) = NaN.
+	 * y1(Inf) = 0.
+	 * y1(-Inf) = NaN and raise invalid exception.
+	 */
+	if(ix>=0x7ff00000) return  vone/(x+x*x); 
+	/* y1(+-0) = -inf and raise divide-by-zero exception. */
+        if((ix|lx)==0) return -one/vzero;
+	/* y1(x<0) = NaN and raise invalid exception. */
+        if(hx<0) return vzero/vzero;
         if(ix >= 0x40000000) {  /* |x| >= 2.0 */
                 s = sin(x);
                 c = cos(x);
diff --git a/lib/msun/src/e_j1f.c b/lib/msun/src/e_j1f.c
index 6077a6924d39..c39c548a0a2b 100644
--- a/lib/msun/src/e_j1f.c
+++ b/lib/msun/src/e_j1f.c
@@ -16,11 +16,17 @@
 #include <sys/cdefs.h>
 __FBSDID("$FreeBSD$");
 
+/*
+ * See e_j1.c for complete comments.
+ */
+
 #include "math.h"
 #include "math_private.h"
 
 static float ponef(float), qonef(float);
 
+static const volatile float vone = 1, vzero = 0;
+
 static const float
 huge    = 1e30,
 one	= 1.0,
@@ -104,10 +110,9 @@ __ieee754_y1f(float x)
 
 	GET_FLOAT_WORD(hx,x);
         ix = 0x7fffffff&hx;
-    /* if Y1(NaN) is NaN, Y1(-inf) is NaN, Y1(inf) is 0 */
-	if(ix>=0x7f800000) return  one/(x+x*x);
-        if(ix==0) return -one/zero;
-        if(hx<0) return zero/zero;
+	if(ix>=0x7f800000) return  vone/(x+x*x);
+	if(ix==0) return -one/vzero;
+	if(hx<0) return vzero/vzero;
         if(ix >= 0x40000000) {  /* |x| >= 2.0 */
                 s = sinf(x);
                 c = cosf(x);
diff --git a/lib/msun/src/e_jn.c b/lib/msun/src/e_jn.c
index 8b0bc62efc2c..eefd4ff751d0 100644
--- a/lib/msun/src/e_jn.c
+++ b/lib/msun/src/e_jn.c
@@ -43,6 +43,8 @@ __FBSDID("$FreeBSD$");
 #include "math.h"
 #include "math_private.h"
 
+static const volatile double vone = 1, vzero = 0;
+
 static const double
 invsqrtpi=  5.64189583547756279280e-01, /* 0x3FE20DD7, 0x50429B6D */
 two   =  2.00000000000000000000e+00, /* 0x40000000, 0x00000000 */
@@ -220,10 +222,12 @@ __ieee754_yn(int n, double x)
 
 	EXTRACT_WORDS(hx,lx,x);
 	ix = 0x7fffffff&hx;
-    /* if Y(n,NaN) is NaN */
+	/* yn(n,NaN) = NaN */
 	if((ix|((u_int32_t)(lx|-lx))>>31)>0x7ff00000) return x+x;
-	if((ix|lx)==0) return -one/zero;
-	if(hx<0) return zero/zero;
+	/* yn(n,+-0) = -inf and raise divide-by-zero exception. */
+	if((ix|lx)==0) return -one/vzero;
+	/* yn(n,x<0) = NaN and raise invalid exception. */
+	if(hx<0) return vzero/vzero;
 	sign = 1;
 	if(n<0){
 		n = -n;
diff --git a/lib/msun/src/e_jnf.c b/lib/msun/src/e_jnf.c
index f564aeccd655..965feeb666d4 100644
--- a/lib/msun/src/e_jnf.c
+++ b/lib/msun/src/e_jnf.c
@@ -16,9 +16,15 @@
 #include <sys/cdefs.h>
 __FBSDID("$FreeBSD$");
 
+/*
+ * See e_jn.c for complete comments.
+ */
+
 #include "math.h"
 #include "math_private.h"
 
+static const volatile float vone = 1, vzero = 0;
+
 static const float
 two   =  2.0000000000e+00, /* 0x40000000 */
 one   =  1.0000000000e+00; /* 0x3F800000 */
@@ -172,10 +178,9 @@ __ieee754_ynf(int n, float x)
 
 	GET_FLOAT_WORD(hx,x);
 	ix = 0x7fffffff&hx;
-    /* if Y(n,NaN) is NaN */
 	if(ix>0x7f800000) return x+x;
-	if(ix==0) return -one/zero;
-	if(hx<0) return zero/zero;
+	if(ix==0) return -one/vzero;
+	if(hx<0) return vzero/vzero;
 	sign = 1;
 	if(n<0){
 		n = -n;