diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2015-12-30 11:55:28 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2015-12-30 11:55:28 +0000 |
| commit | e81d9d49145e432d917eea3a70d2ae74dcad1d89 (patch) | |
| tree | 9ed5e1a91f242e2cb5911577356e487a55c01b78 /source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp | |
| parent | 85d8ef8f1f0e0e063a8571944302be2d2026f823 (diff) | |
| download | src-e81d9d49145e432d917eea3a70d2ae74dcad1d89.tar.gz src-e81d9d49145e432d917eea3a70d2ae74dcad1d89.zip | |
Vendor import of stripped lldb trunk r256633:
Notes
Notes:
svn path=/vendor/lldb/dist/; revision=292932
Diffstat (limited to 'source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp')
| -rw-r--r-- | source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp | 1119 |
1 files changed, 725 insertions, 394 deletions
diff --git a/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp b/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp index a574e7d348e1..28eba093f317 100644 --- a/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp +++ b/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp @@ -221,41 +221,76 @@ EmulateInstructionMIPS64::GetRegisterName (unsigned reg_num, bool alternate_name { switch (reg_num) { - case gcc_dwarf_sp_mips64: return "r29"; - case gcc_dwarf_r30_mips64: return "r30"; - case gcc_dwarf_ra_mips64: return "r31"; - case gcc_dwarf_f0_mips64: return "f0"; - case gcc_dwarf_f1_mips64: return "f1"; - case gcc_dwarf_f2_mips64: return "f2"; - case gcc_dwarf_f3_mips64: return "f3"; - case gcc_dwarf_f4_mips64: return "f4"; - case gcc_dwarf_f5_mips64: return "f5"; - case gcc_dwarf_f6_mips64: return "f6"; - case gcc_dwarf_f7_mips64: return "f7"; - case gcc_dwarf_f8_mips64: return "f8"; - case gcc_dwarf_f9_mips64: return "f9"; - case gcc_dwarf_f10_mips64: return "f10"; - case gcc_dwarf_f11_mips64: return "f11"; - case gcc_dwarf_f12_mips64: return "f12"; - case gcc_dwarf_f13_mips64: return "f13"; - case gcc_dwarf_f14_mips64: return "f14"; - case gcc_dwarf_f15_mips64: return "f15"; - case gcc_dwarf_f16_mips64: return "f16"; - case gcc_dwarf_f17_mips64: return "f17"; - case gcc_dwarf_f18_mips64: return "f18"; - case gcc_dwarf_f19_mips64: return "f19"; - case gcc_dwarf_f20_mips64: return "f20"; - case gcc_dwarf_f21_mips64: return "f21"; - case gcc_dwarf_f22_mips64: return "f22"; - case gcc_dwarf_f23_mips64: return "f23"; - case gcc_dwarf_f24_mips64: return "f24"; - case gcc_dwarf_f25_mips64: return "f25"; - case gcc_dwarf_f26_mips64: return "f26"; - case gcc_dwarf_f27_mips64: return "f27"; - case gcc_dwarf_f28_mips64: return "f28"; - case gcc_dwarf_f29_mips64: return "f29"; - case gcc_dwarf_f30_mips64: return "f30"; - case gcc_dwarf_f31_mips64: return "f31"; + case dwarf_sp_mips64: return "r29"; + case dwarf_r30_mips64: return "r30"; + case dwarf_ra_mips64: return "r31"; + case dwarf_f0_mips64: return "f0"; + case dwarf_f1_mips64: return "f1"; + case dwarf_f2_mips64: return "f2"; + case dwarf_f3_mips64: return "f3"; + case dwarf_f4_mips64: return "f4"; + case dwarf_f5_mips64: return "f5"; + case dwarf_f6_mips64: return "f6"; + case dwarf_f7_mips64: return "f7"; + case dwarf_f8_mips64: return "f8"; + case dwarf_f9_mips64: return "f9"; + case dwarf_f10_mips64: return "f10"; + case dwarf_f11_mips64: return "f11"; + case dwarf_f12_mips64: return "f12"; + case dwarf_f13_mips64: return "f13"; + case dwarf_f14_mips64: return "f14"; + case dwarf_f15_mips64: return "f15"; + case dwarf_f16_mips64: return "f16"; + case dwarf_f17_mips64: return "f17"; + case dwarf_f18_mips64: return "f18"; + case dwarf_f19_mips64: return "f19"; + case dwarf_f20_mips64: return "f20"; + case dwarf_f21_mips64: return "f21"; + case dwarf_f22_mips64: return "f22"; + case dwarf_f23_mips64: return "f23"; + case dwarf_f24_mips64: return "f24"; + case dwarf_f25_mips64: return "f25"; + case dwarf_f26_mips64: return "f26"; + case dwarf_f27_mips64: return "f27"; + case dwarf_f28_mips64: return "f28"; + case dwarf_f29_mips64: return "f29"; + case dwarf_f30_mips64: return "f30"; + case dwarf_f31_mips64: return "f31"; + case dwarf_w0_mips64: return "w0"; + case dwarf_w1_mips64: return "w1"; + case dwarf_w2_mips64: return "w2"; + case dwarf_w3_mips64: return "w3"; + case dwarf_w4_mips64: return "w4"; + case dwarf_w5_mips64: return "w5"; + case dwarf_w6_mips64: return "w6"; + case dwarf_w7_mips64: return "w7"; + case dwarf_w8_mips64: return "w8"; + case dwarf_w9_mips64: return "w9"; + case dwarf_w10_mips64: return "w10"; + case dwarf_w11_mips64: return "w11"; + case dwarf_w12_mips64: return "w12"; + case dwarf_w13_mips64: return "w13"; + case dwarf_w14_mips64: return "w14"; + case dwarf_w15_mips64: return "w15"; + case dwarf_w16_mips64: return "w16"; + case dwarf_w17_mips64: return "w17"; + case dwarf_w18_mips64: return "w18"; + case dwarf_w19_mips64: return "w19"; + case dwarf_w20_mips64: return "w20"; + case dwarf_w21_mips64: return "w21"; + case dwarf_w22_mips64: return "w22"; + case dwarf_w23_mips64: return "w23"; + case dwarf_w24_mips64: return "w24"; + case dwarf_w25_mips64: return "w25"; + case dwarf_w26_mips64: return "w26"; + case dwarf_w27_mips64: return "w27"; + case dwarf_w28_mips64: return "w28"; + case dwarf_w29_mips64: return "w29"; + case dwarf_w30_mips64: return "w30"; + case dwarf_w31_mips64: return "w31"; + case dwarf_mir_mips64: return "mir"; + case dwarf_mcsr_mips64: return "mcsr"; + case dwarf_config5_mips64: return "config5"; default: break; } @@ -264,78 +299,113 @@ EmulateInstructionMIPS64::GetRegisterName (unsigned reg_num, bool alternate_name switch (reg_num) { - case gcc_dwarf_zero_mips64: return "r0"; - case gcc_dwarf_r1_mips64: return "r1"; - case gcc_dwarf_r2_mips64: return "r2"; - case gcc_dwarf_r3_mips64: return "r3"; - case gcc_dwarf_r4_mips64: return "r4"; - case gcc_dwarf_r5_mips64: return "r5"; - case gcc_dwarf_r6_mips64: return "r6"; - case gcc_dwarf_r7_mips64: return "r7"; - case gcc_dwarf_r8_mips64: return "r8"; - case gcc_dwarf_r9_mips64: return "r9"; - case gcc_dwarf_r10_mips64: return "r10"; - case gcc_dwarf_r11_mips64: return "r11"; - case gcc_dwarf_r12_mips64: return "r12"; - case gcc_dwarf_r13_mips64: return "r13"; - case gcc_dwarf_r14_mips64: return "r14"; - case gcc_dwarf_r15_mips64: return "r15"; - case gcc_dwarf_r16_mips64: return "r16"; - case gcc_dwarf_r17_mips64: return "r17"; - case gcc_dwarf_r18_mips64: return "r18"; - case gcc_dwarf_r19_mips64: return "r19"; - case gcc_dwarf_r20_mips64: return "r20"; - case gcc_dwarf_r21_mips64: return "r21"; - case gcc_dwarf_r22_mips64: return "r22"; - case gcc_dwarf_r23_mips64: return "r23"; - case gcc_dwarf_r24_mips64: return "r24"; - case gcc_dwarf_r25_mips64: return "r25"; - case gcc_dwarf_r26_mips64: return "r26"; - case gcc_dwarf_r27_mips64: return "r27"; - case gcc_dwarf_gp_mips64: return "gp"; - case gcc_dwarf_sp_mips64: return "sp"; - case gcc_dwarf_r30_mips64: return "fp"; - case gcc_dwarf_ra_mips64: return "ra"; - case gcc_dwarf_sr_mips64: return "sr"; - case gcc_dwarf_lo_mips64: return "lo"; - case gcc_dwarf_hi_mips64: return "hi"; - case gcc_dwarf_bad_mips64: return "bad"; - case gcc_dwarf_cause_mips64: return "cause"; - case gcc_dwarf_pc_mips64: return "pc"; - case gcc_dwarf_f0_mips64: return "f0"; - case gcc_dwarf_f1_mips64: return "f1"; - case gcc_dwarf_f2_mips64: return "f2"; - case gcc_dwarf_f3_mips64: return "f3"; - case gcc_dwarf_f4_mips64: return "f4"; - case gcc_dwarf_f5_mips64: return "f5"; - case gcc_dwarf_f6_mips64: return "f6"; - case gcc_dwarf_f7_mips64: return "f7"; - case gcc_dwarf_f8_mips64: return "f8"; - case gcc_dwarf_f9_mips64: return "f9"; - case gcc_dwarf_f10_mips64: return "f10"; - case gcc_dwarf_f11_mips64: return "f11"; - case gcc_dwarf_f12_mips64: return "f12"; - case gcc_dwarf_f13_mips64: return "f13"; - case gcc_dwarf_f14_mips64: return "f14"; - case gcc_dwarf_f15_mips64: return "f15"; - case gcc_dwarf_f16_mips64: return "f16"; - case gcc_dwarf_f17_mips64: return "f17"; - case gcc_dwarf_f18_mips64: return "f18"; - case gcc_dwarf_f19_mips64: return "f19"; - case gcc_dwarf_f20_mips64: return "f20"; - case gcc_dwarf_f21_mips64: return "f21"; - case gcc_dwarf_f22_mips64: return "f22"; - case gcc_dwarf_f23_mips64: return "f23"; - case gcc_dwarf_f24_mips64: return "f24"; - case gcc_dwarf_f25_mips64: return "f25"; - case gcc_dwarf_f26_mips64: return "f26"; - case gcc_dwarf_f27_mips64: return "f27"; - case gcc_dwarf_f28_mips64: return "f28"; - case gcc_dwarf_f29_mips64: return "f29"; - case gcc_dwarf_f30_mips64: return "f30"; - case gcc_dwarf_f31_mips64: return "f31"; - case gcc_dwarf_fcsr_mips64: return "fcsr"; - case gcc_dwarf_fir_mips64: return "fir"; + case dwarf_zero_mips64: return "r0"; + case dwarf_r1_mips64: return "r1"; + case dwarf_r2_mips64: return "r2"; + case dwarf_r3_mips64: return "r3"; + case dwarf_r4_mips64: return "r4"; + case dwarf_r5_mips64: return "r5"; + case dwarf_r6_mips64: return "r6"; + case dwarf_r7_mips64: return "r7"; + case dwarf_r8_mips64: return "r8"; + case dwarf_r9_mips64: return "r9"; + case dwarf_r10_mips64: return "r10"; + case dwarf_r11_mips64: return "r11"; + case dwarf_r12_mips64: return "r12"; + case dwarf_r13_mips64: return "r13"; + case dwarf_r14_mips64: return "r14"; + case dwarf_r15_mips64: return "r15"; + case dwarf_r16_mips64: return "r16"; + case dwarf_r17_mips64: return "r17"; + case dwarf_r18_mips64: return "r18"; + case dwarf_r19_mips64: return "r19"; + case dwarf_r20_mips64: return "r20"; + case dwarf_r21_mips64: return "r21"; + case dwarf_r22_mips64: return "r22"; + case dwarf_r23_mips64: return "r23"; + case dwarf_r24_mips64: return "r24"; + case dwarf_r25_mips64: return "r25"; + case dwarf_r26_mips64: return "r26"; + case dwarf_r27_mips64: return "r27"; + case dwarf_gp_mips64: return "gp"; + case dwarf_sp_mips64: return "sp"; + case dwarf_r30_mips64: return "fp"; + case dwarf_ra_mips64: return "ra"; + case dwarf_sr_mips64: return "sr"; + case dwarf_lo_mips64: return "lo"; + case dwarf_hi_mips64: return "hi"; + case dwarf_bad_mips64: return "bad"; + case dwarf_cause_mips64: return "cause"; + case dwarf_pc_mips64: return "pc"; + case dwarf_f0_mips64: return "f0"; + case dwarf_f1_mips64: return "f1"; + case dwarf_f2_mips64: return "f2"; + case dwarf_f3_mips64: return "f3"; + case dwarf_f4_mips64: return "f4"; + case dwarf_f5_mips64: return "f5"; + case dwarf_f6_mips64: return "f6"; + case dwarf_f7_mips64: return "f7"; + case dwarf_f8_mips64: return "f8"; + case dwarf_f9_mips64: return "f9"; + case dwarf_f10_mips64: return "f10"; + case dwarf_f11_mips64: return "f11"; + case dwarf_f12_mips64: return "f12"; + case dwarf_f13_mips64: return "f13"; + case dwarf_f14_mips64: return "f14"; + case dwarf_f15_mips64: return "f15"; + case dwarf_f16_mips64: return "f16"; + case dwarf_f17_mips64: return "f17"; + case dwarf_f18_mips64: return "f18"; + case dwarf_f19_mips64: return "f19"; + case dwarf_f20_mips64: return "f20"; + case dwarf_f21_mips64: return "f21"; + case dwarf_f22_mips64: return "f22"; + case dwarf_f23_mips64: return "f23"; + case dwarf_f24_mips64: return "f24"; + case dwarf_f25_mips64: return "f25"; + case dwarf_f26_mips64: return "f26"; + case dwarf_f27_mips64: return "f27"; + case dwarf_f28_mips64: return "f28"; + case dwarf_f29_mips64: return "f29"; + case dwarf_f30_mips64: return "f30"; + case dwarf_f31_mips64: return "f31"; + case dwarf_fcsr_mips64: return "fcsr"; + case dwarf_fir_mips64: return "fir"; + case dwarf_w0_mips64: return "w0"; + case dwarf_w1_mips64: return "w1"; + case dwarf_w2_mips64: return "w2"; + case dwarf_w3_mips64: return "w3"; + case dwarf_w4_mips64: return "w4"; + case dwarf_w5_mips64: return "w5"; + case dwarf_w6_mips64: return "w6"; + case dwarf_w7_mips64: return "w7"; + case dwarf_w8_mips64: return "w8"; + case dwarf_w9_mips64: return "w9"; + case dwarf_w10_mips64: return "w10"; + case dwarf_w11_mips64: return "w11"; + case dwarf_w12_mips64: return "w12"; + case dwarf_w13_mips64: return "w13"; + case dwarf_w14_mips64: return "w14"; + case dwarf_w15_mips64: return "w15"; + case dwarf_w16_mips64: return "w16"; + case dwarf_w17_mips64: return "w17"; + case dwarf_w18_mips64: return "w18"; + case dwarf_w19_mips64: return "w19"; + case dwarf_w20_mips64: return "w20"; + case dwarf_w21_mips64: return "w21"; + case dwarf_w22_mips64: return "w22"; + case dwarf_w23_mips64: return "w23"; + case dwarf_w24_mips64: return "w24"; + case dwarf_w25_mips64: return "w25"; + case dwarf_w26_mips64: return "w26"; + case dwarf_w27_mips64: return "w27"; + case dwarf_w28_mips64: return "w28"; + case dwarf_w29_mips64: return "w29"; + case dwarf_w30_mips64: return "w30"; + case dwarf_w31_mips64: return "w31"; + case dwarf_mcsr_mips64: return "mcsr"; + case dwarf_mir_mips64: return "mir"; + case dwarf_config5_mips64: return "config5"; } return nullptr; } @@ -347,11 +417,11 @@ EmulateInstructionMIPS64::GetRegisterInfo (RegisterKind reg_kind, uint32_t reg_n { switch (reg_num) { - case LLDB_REGNUM_GENERIC_PC: reg_kind = eRegisterKindDWARF; reg_num = gcc_dwarf_pc_mips64; break; - case LLDB_REGNUM_GENERIC_SP: reg_kind = eRegisterKindDWARF; reg_num = gcc_dwarf_sp_mips64; break; - case LLDB_REGNUM_GENERIC_FP: reg_kind = eRegisterKindDWARF; reg_num = gcc_dwarf_r30_mips64; break; - case LLDB_REGNUM_GENERIC_RA: reg_kind = eRegisterKindDWARF; reg_num = gcc_dwarf_ra_mips64; break; - case LLDB_REGNUM_GENERIC_FLAGS: reg_kind = eRegisterKindDWARF; reg_num = gcc_dwarf_sr_mips64; break; + case LLDB_REGNUM_GENERIC_PC: reg_kind = eRegisterKindDWARF; reg_num = dwarf_pc_mips64; break; + case LLDB_REGNUM_GENERIC_SP: reg_kind = eRegisterKindDWARF; reg_num = dwarf_sp_mips64; break; + case LLDB_REGNUM_GENERIC_FP: reg_kind = eRegisterKindDWARF; reg_num = dwarf_r30_mips64; break; + case LLDB_REGNUM_GENERIC_RA: reg_kind = eRegisterKindDWARF; reg_num = dwarf_ra_mips64; break; + case LLDB_REGNUM_GENERIC_FLAGS: reg_kind = eRegisterKindDWARF; reg_num = dwarf_sr_mips64; break; default: return false; } @@ -362,18 +432,24 @@ EmulateInstructionMIPS64::GetRegisterInfo (RegisterKind reg_kind, uint32_t reg_n ::memset (®_info, 0, sizeof(RegisterInfo)); ::memset (reg_info.kinds, LLDB_INVALID_REGNUM, sizeof(reg_info.kinds)); - if (reg_num == gcc_dwarf_sr_mips64 || reg_num == gcc_dwarf_fcsr_mips64 || reg_num == gcc_dwarf_fir_mips64) + if (reg_num == dwarf_sr_mips64 || reg_num == dwarf_fcsr_mips64 || reg_num == dwarf_fir_mips64 || reg_num == dwarf_mcsr_mips64 || reg_num == dwarf_mir_mips64 || reg_num == dwarf_config5_mips64) { reg_info.byte_size = 4; reg_info.format = eFormatHex; reg_info.encoding = eEncodingUint; } - else if ((int)reg_num >= gcc_dwarf_zero_mips64 && (int)reg_num <= gcc_dwarf_f31_mips64) + else if ((int)reg_num >= dwarf_zero_mips64 && (int)reg_num <= dwarf_f31_mips64) { reg_info.byte_size = 8; reg_info.format = eFormatHex; reg_info.encoding = eEncodingUint; } + else if ((int)reg_num >= dwarf_w0_mips64 && (int)reg_num <= dwarf_w31_mips64) + { + reg_info.byte_size = 16; + reg_info.format = eFormatVectorOfUInt8; + reg_info.encoding = eEncodingVector; + } else { return false; @@ -385,11 +461,11 @@ EmulateInstructionMIPS64::GetRegisterInfo (RegisterKind reg_kind, uint32_t reg_n switch (reg_num) { - case gcc_dwarf_r30_mips64: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FP; break; - case gcc_dwarf_ra_mips64: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_RA; break; - case gcc_dwarf_sp_mips64: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_SP; break; - case gcc_dwarf_pc_mips64: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_PC; break; - case gcc_dwarf_sr_mips64: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FLAGS; break; + case dwarf_r30_mips64: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FP; break; + case dwarf_ra_mips64: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_RA; break; + case dwarf_sp_mips64: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_SP; break; + case dwarf_pc_mips64: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_PC; break; + case dwarf_sr_mips64: reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FLAGS; break; default: break; } return true; @@ -410,8 +486,65 @@ EmulateInstructionMIPS64::GetOpcodeForInstruction (const char *op_name) { "SD", &EmulateInstructionMIPS64::Emulate_SD, "SD rt,offset(rs)" }, { "LD", &EmulateInstructionMIPS64::Emulate_LD, "LD rt,offset(base)" }, - { "SW", &EmulateInstructionMIPS64::Emulate_SW, "SW rt,offset(rs)" }, - { "LW", &EmulateInstructionMIPS64::Emulate_LW, "LW rt,offset(rs)" }, + + + + //---------------------------------------------------------------------- + // Load/Store instructions + //---------------------------------------------------------------------- + /* Following list of emulated instructions are required by implementation of hardware watchpoint + for MIPS in lldb. As we just need the address accessed by instructions, we have generalised + all these instructions in 2 functions depending on their addressing modes */ + + { "LB", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LB rt, offset(base)" }, + { "LBE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LBE rt, offset(base)" }, + { "LBU", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LBU rt, offset(base)" }, + { "LBUE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LBUE rt, offset(base)" }, + { "LDC1", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LDC1 ft, offset(base)" }, + { "LDL", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LDL rt, offset(base)" }, + { "LDR", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LDR rt, offset(base)" }, + { "LLD", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LLD rt, offset(base)" }, + { "LDC2", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LDC2 rt, offset(base)" }, + { "LDXC1", &EmulateInstructionMIPS64::Emulate_LDST_Reg, "LDXC1 fd, index (base)" }, + { "LH", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LH rt, offset(base)" }, + { "LHE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LHE rt, offset(base)" }, + { "LHU", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LHU rt, offset(base)" }, + { "LHUE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LHUE rt, offset(base)" }, + { "LL", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LL rt, offset(base)" }, + { "LLE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LLE rt, offset(base)" }, + { "LUXC1", &EmulateInstructionMIPS64::Emulate_LDST_Reg, "LUXC1 fd, index (base)" }, + { "LW", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LW rt, offset(rs)" }, + { "LWC1", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LWC1 ft, offset(base)" }, + { "LWC2", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LWC2 rt, offset(base)" }, + { "LWE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LWE rt, offset(base)" }, + { "LWL", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LWL rt, offset(base)" }, + { "LWLE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LWLE rt, offset(base)" }, + { "LWR", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LWR rt, offset(base)" }, + { "LWRE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "LWRE rt, offset(base)" }, + { "LWXC1", &EmulateInstructionMIPS64::Emulate_LDST_Reg, "LWXC1 fd, index (base)" }, + + { "SB", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SB rt, offset(base)" }, + { "SBE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SBE rt, offset(base)" }, + { "SC", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SC rt, offset(base)" }, + { "SCE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SCE rt, offset(base)" }, + { "SCD", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SCD rt, offset(base)" }, + { "SDL", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SDL rt, offset(base)" }, + { "SDR", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SDR rt, offset(base)" }, + { "SDC1", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SDC1 ft, offset(base)" }, + { "SDC2", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SDC2 rt, offset(base)" }, + { "SDXC1", &EmulateInstructionMIPS64::Emulate_LDST_Reg, "SDXC1 fs, index (base)" }, + { "SH", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SH rt, offset(base)" }, + { "SHE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SHE rt, offset(base)" }, + { "SUXC1", &EmulateInstructionMIPS64::Emulate_LDST_Reg, "SUXC1 fs, index (base)" }, + { "SW", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SW rt, offset(rs)" }, + { "SWC1", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SWC1 ft, offset(base)" }, + { "SWC2", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SWC2 rt, offset(base)" }, + { "SWE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SWE rt, offset(base)" }, + { "SWL", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SWL rt, offset(base)" }, + { "SWLE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SWLE rt, offset(base)" }, + { "SWR", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SWR rt, offset(base)" }, + { "SWRE", &EmulateInstructionMIPS64::Emulate_LDST_Imm, "SWRE rt, offset(base)" }, + { "SWXC1", &EmulateInstructionMIPS64::Emulate_LDST_Reg, "SWXC1 fs, index (base)" }, //---------------------------------------------------------------------- // Branch instructions @@ -474,6 +607,16 @@ EmulateInstructionMIPS64::GetOpcodeForInstruction (const char *op_name) { "BC1ANY2T", &EmulateInstructionMIPS64::Emulate_BC1ANY2T, "BC1ANY2T cc, offset" }, { "BC1ANY4F", &EmulateInstructionMIPS64::Emulate_BC1ANY4F, "BC1ANY4F cc, offset" }, { "BC1ANY4T", &EmulateInstructionMIPS64::Emulate_BC1ANY4T, "BC1ANY4T cc, offset" }, + { "BNZ_B", &EmulateInstructionMIPS64::Emulate_BNZB, "BNZ.b wt,s16" }, + { "BNZ_H", &EmulateInstructionMIPS64::Emulate_BNZH, "BNZ.h wt,s16" }, + { "BNZ_W", &EmulateInstructionMIPS64::Emulate_BNZW, "BNZ.w wt,s16" }, + { "BNZ_D", &EmulateInstructionMIPS64::Emulate_BNZD, "BNZ.d wt,s16" }, + { "BZ_B", &EmulateInstructionMIPS64::Emulate_BZB, "BZ.b wt,s16" }, + { "BZ_H", &EmulateInstructionMIPS64::Emulate_BZH, "BZ.h wt,s16" }, + { "BZ_W", &EmulateInstructionMIPS64::Emulate_BZW, "BZ.w wt,s16" }, + { "BZ_D", &EmulateInstructionMIPS64::Emulate_BZD, "BZ.d wt,s16" }, + { "BNZ_V", &EmulateInstructionMIPS64::Emulate_BNZV, "BNZ.V wt,s16" }, + { "BZ_V", &EmulateInstructionMIPS64::Emulate_BZV, "BZ.V wt,s16" }, }; static const size_t k_num_mips_opcodes = llvm::array_lengthof(g_opcodes); @@ -545,7 +688,7 @@ EmulateInstructionMIPS64::EvaluateInstruction (uint32_t evaluate_options) if (auto_advance_pc) { - old_pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + old_pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; } @@ -557,7 +700,7 @@ EmulateInstructionMIPS64::EvaluateInstruction (uint32_t evaluate_options) if (auto_advance_pc) { - new_pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + new_pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; @@ -566,7 +709,7 @@ EmulateInstructionMIPS64::EvaluateInstruction (uint32_t evaluate_options) { new_pc += 4; Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, new_pc)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, new_pc)) return false; } } @@ -584,10 +727,10 @@ EmulateInstructionMIPS64::CreateFunctionEntryUnwind (UnwindPlan &unwind_plan) const bool can_replace = false; // Our previous Call Frame Address is the stack pointer - row->GetCFAValue().SetIsRegisterPlusOffset(gcc_dwarf_sp_mips64, 0); + row->GetCFAValue().SetIsRegisterPlusOffset(dwarf_sp_mips64, 0); // Our previous PC is in the RA - row->SetRegisterLocationToRegister(gcc_dwarf_pc_mips64, gcc_dwarf_ra_mips64, can_replace); + row->SetRegisterLocationToRegister(dwarf_pc_mips64, dwarf_ra_mips64, can_replace); unwind_plan.AppendRow (row); @@ -595,6 +738,7 @@ EmulateInstructionMIPS64::CreateFunctionEntryUnwind (UnwindPlan &unwind_plan) unwind_plan.SetSourceName ("EmulateInstructionMIPS64"); unwind_plan.SetSourcedFromCompiler (eLazyBoolNo); unwind_plan.SetUnwindPlanValidAtAllInstructions (eLazyBoolYes); + unwind_plan.SetReturnAddressRegister (dwarf_ra_mips64); return true; } @@ -604,18 +748,18 @@ EmulateInstructionMIPS64::nonvolatile_reg_p (uint64_t regnum) { switch (regnum) { - case gcc_dwarf_r16_mips64: - case gcc_dwarf_r17_mips64: - case gcc_dwarf_r18_mips64: - case gcc_dwarf_r19_mips64: - case gcc_dwarf_r20_mips64: - case gcc_dwarf_r21_mips64: - case gcc_dwarf_r22_mips64: - case gcc_dwarf_r23_mips64: - case gcc_dwarf_gp_mips64: - case gcc_dwarf_sp_mips64: - case gcc_dwarf_r30_mips64: - case gcc_dwarf_ra_mips64: + case dwarf_r16_mips64: + case dwarf_r17_mips64: + case dwarf_r18_mips64: + case dwarf_r19_mips64: + case dwarf_r20_mips64: + case dwarf_r21_mips64: + case dwarf_r22_mips64: + case dwarf_r23_mips64: + case dwarf_gp_mips64: + case dwarf_sp_mips64: + case dwarf_r30_mips64: + case dwarf_ra_mips64: return true; default: return false; @@ -636,10 +780,10 @@ EmulateInstructionMIPS64::Emulate_DADDiu (llvm::MCInst& insn) src = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); /* Check if this is daddiu sp,<src>,imm16 */ - if (dst == gcc_dwarf_sp_mips64) + if (dst == dwarf_sp_mips64) { /* read <src> register */ - uint64_t src_opd_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + src, 0, &success); + uint64_t src_opd_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + src, 0, &success); if (!success) return false; @@ -647,79 +791,19 @@ EmulateInstructionMIPS64::Emulate_DADDiu (llvm::MCInst& insn) Context context; RegisterInfo reg_info_sp; - if (GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_sp_mips64, reg_info_sp)) + if (GetRegisterInfo (eRegisterKindDWARF, dwarf_sp_mips64, reg_info_sp)) context.SetRegisterPlusOffset (reg_info_sp, imm); /* We are allocating bytes on stack */ context.type = eContextAdjustStackPointer; - WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_sp_mips64, result); + WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_sp_mips64, result); } return true; } bool -EmulateInstructionMIPS64::Emulate_SW (llvm::MCInst& insn) -{ - bool success = false; - uint32_t base; - int64_t imm, address; - Context bad_vaddr_context; - - base = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); - imm = insn.getOperand(2).getImm(); - - RegisterInfo reg_info_base; - if (!GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + base, reg_info_base)) - return false; - - /* read base register */ - address = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + base, 0, &success); - if (!success) - return false; - - /* destination address */ - address = address + imm; - - /* Set the bad_vaddr register with base address used in the instruction */ - bad_vaddr_context.type = eContextInvalid; - WriteRegisterUnsigned (bad_vaddr_context, eRegisterKindDWARF, gcc_dwarf_bad_mips64, address); - - return true; -} - -bool -EmulateInstructionMIPS64::Emulate_LW (llvm::MCInst& insn) -{ - bool success = false; - uint32_t base; - int64_t imm, address; - Context bad_vaddr_context; - - base = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); - imm = insn.getOperand(2).getImm(); - - RegisterInfo reg_info_base; - if (!GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + base, reg_info_base)) - return false; - - /* read base register */ - address = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + base, 0, &success); - if (!success) - return false; - - /* destination address */ - address = address + imm; - - /* Set the bad_vaddr register with base address used in the instruction */ - bad_vaddr_context.type = eContextInvalid; - WriteRegisterUnsigned (bad_vaddr_context, eRegisterKindDWARF, gcc_dwarf_bad_mips64, address); - - return true; -} - -bool EmulateInstructionMIPS64::Emulate_SD (llvm::MCInst& insn) { uint64_t address; @@ -734,12 +818,12 @@ EmulateInstructionMIPS64::Emulate_SD (llvm::MCInst& insn) src = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); base = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); - if (!GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + base, reg_info_base) - || !GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + src, reg_info_src)) + if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips64 + base, reg_info_base) + || !GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips64 + src, reg_info_src)) return false; /* read SP */ - address = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + base, 0, &success); + address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + base, 0, &success); if (!success) return false; @@ -747,7 +831,7 @@ EmulateInstructionMIPS64::Emulate_SD (llvm::MCInst& insn) address = address + imm; /* We look for sp based non-volatile register stores */ - if (base == gcc_dwarf_sp_mips64 && nonvolatile_reg_p (src)) + if (base == dwarf_sp_mips64 && nonvolatile_reg_p (src)) { Context context; RegisterValue data_src; @@ -769,7 +853,7 @@ EmulateInstructionMIPS64::Emulate_SD (llvm::MCInst& insn) /* Set the bad_vaddr register with base address used in the instruction */ bad_vaddr_context.type = eContextInvalid; - WriteRegisterUnsigned (bad_vaddr_context, eRegisterKindDWARF, gcc_dwarf_bad_mips64, address); + WriteRegisterUnsigned (bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips64, address); return true; } @@ -777,17 +861,38 @@ EmulateInstructionMIPS64::Emulate_SD (llvm::MCInst& insn) bool EmulateInstructionMIPS64::Emulate_LD (llvm::MCInst& insn) { + bool success =false; uint32_t src, base; + int64_t imm, address; + Context bad_vaddr_context; src = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); base = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); + imm = insn.getOperand(2).getImm(); + + RegisterInfo reg_info_base; + if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips64 + base, reg_info_base)) + return false; + + /* read base register */ + address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + base, 0, &success); + if (!success) + return false; - if (base == gcc_dwarf_sp_mips64 && nonvolatile_reg_p (src)) + /* destination address */ + address = address + imm; + + /* Set the bad_vaddr register with base address used in the instruction */ + bad_vaddr_context.type = eContextInvalid; + WriteRegisterUnsigned (bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips64, address); + + + if (base == dwarf_sp_mips64 && nonvolatile_reg_p (src)) { RegisterValue data_src; RegisterInfo reg_info_src; - if (!GetRegisterInfo (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + src, reg_info_src)) + if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips64 + src, reg_info_src)) return false; Context context; @@ -821,15 +926,15 @@ EmulateInstructionMIPS64::Emulate_BEQ (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; - rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rt, 0, &success); + rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success); if (!success) return false; @@ -841,7 +946,7 @@ EmulateInstructionMIPS64::Emulate_BEQ (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -864,15 +969,15 @@ EmulateInstructionMIPS64::Emulate_BNE (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; - rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rt, 0, &success); + rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success); if (!success) return false; @@ -884,7 +989,7 @@ EmulateInstructionMIPS64::Emulate_BNE (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -907,15 +1012,15 @@ EmulateInstructionMIPS64::Emulate_BEQL (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; - rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rt, 0, &success); + rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success); if (!success) return false; @@ -927,7 +1032,7 @@ EmulateInstructionMIPS64::Emulate_BEQL (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -950,15 +1055,15 @@ EmulateInstructionMIPS64::Emulate_BNEL (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; - rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rt, 0, &success); + rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success); if (!success) return false; @@ -970,7 +1075,7 @@ EmulateInstructionMIPS64::Emulate_BNEL (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -993,11 +1098,11 @@ EmulateInstructionMIPS64::Emulate_BGEZL (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -1009,7 +1114,7 @@ EmulateInstructionMIPS64::Emulate_BGEZL (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -1032,11 +1137,11 @@ EmulateInstructionMIPS64::Emulate_BLTZL (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -1048,7 +1153,7 @@ EmulateInstructionMIPS64::Emulate_BLTZL (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -1071,11 +1176,11 @@ EmulateInstructionMIPS64::Emulate_BGTZL (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -1087,7 +1192,7 @@ EmulateInstructionMIPS64::Emulate_BGTZL (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -1110,11 +1215,11 @@ EmulateInstructionMIPS64::Emulate_BLEZL (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -1126,7 +1231,7 @@ EmulateInstructionMIPS64::Emulate_BLEZL (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -1149,11 +1254,11 @@ EmulateInstructionMIPS64::Emulate_BGTZ (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -1165,7 +1270,7 @@ EmulateInstructionMIPS64::Emulate_BGTZ (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -1188,11 +1293,11 @@ EmulateInstructionMIPS64::Emulate_BLEZ (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -1204,7 +1309,7 @@ EmulateInstructionMIPS64::Emulate_BLEZ (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -1227,11 +1332,11 @@ EmulateInstructionMIPS64::Emulate_BLTZ (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -1243,7 +1348,7 @@ EmulateInstructionMIPS64::Emulate_BLTZ (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -1266,11 +1371,11 @@ EmulateInstructionMIPS64::Emulate_BGEZALL (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -1282,10 +1387,10 @@ EmulateInstructionMIPS64::Emulate_BGEZALL (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips64, pc + 8)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 8)) return false; return true; @@ -1305,7 +1410,7 @@ EmulateInstructionMIPS64::Emulate_BAL (llvm::MCInst& insn) */ offset = insn.getOperand(0).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; @@ -1313,10 +1418,10 @@ EmulateInstructionMIPS64::Emulate_BAL (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips64, pc + 8)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 8)) return false; return true; @@ -1336,7 +1441,7 @@ EmulateInstructionMIPS64::Emulate_BALC (llvm::MCInst& insn) */ offset = insn.getOperand(0).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; @@ -1344,10 +1449,10 @@ EmulateInstructionMIPS64::Emulate_BALC (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips64, pc + 4)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 4)) return false; return true; @@ -1372,11 +1477,11 @@ EmulateInstructionMIPS64::Emulate_BGEZAL (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -1387,10 +1492,10 @@ EmulateInstructionMIPS64::Emulate_BGEZAL (llvm::MCInst& insn) else target = pc + 8; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips64, pc + 8)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 8)) return false; return true; @@ -1415,11 +1520,11 @@ EmulateInstructionMIPS64::Emulate_BLTZAL (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -1430,10 +1535,10 @@ EmulateInstructionMIPS64::Emulate_BLTZAL (llvm::MCInst& insn) else target = pc + 8; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips64, pc + 8)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 8)) return false; return true; @@ -1458,11 +1563,11 @@ EmulateInstructionMIPS64::Emulate_BLTZALL (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -1473,10 +1578,10 @@ EmulateInstructionMIPS64::Emulate_BLTZALL (llvm::MCInst& insn) else target = pc + 8; /* skip delay slot */ - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips64, pc + 8)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 8)) return false; return true; @@ -1502,11 +1607,11 @@ EmulateInstructionMIPS64::Emulate_BLEZALC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -1517,10 +1622,10 @@ EmulateInstructionMIPS64::Emulate_BLEZALC (llvm::MCInst& insn) else target = pc + 4; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips64, pc + 4)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 4)) return false; return true; @@ -1545,11 +1650,11 @@ EmulateInstructionMIPS64::Emulate_BGEZALC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -1560,10 +1665,10 @@ EmulateInstructionMIPS64::Emulate_BGEZALC (llvm::MCInst& insn) else target = pc + 4; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips64, pc + 4)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 4)) return false; return true; @@ -1588,11 +1693,11 @@ EmulateInstructionMIPS64::Emulate_BLTZALC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -1603,10 +1708,10 @@ EmulateInstructionMIPS64::Emulate_BLTZALC (llvm::MCInst& insn) else target = pc + 4; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips64, pc + 4)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 4)) return false; return true; @@ -1631,11 +1736,11 @@ EmulateInstructionMIPS64::Emulate_BGTZALC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -1646,10 +1751,10 @@ EmulateInstructionMIPS64::Emulate_BGTZALC (llvm::MCInst& insn) else target = pc + 4; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips64, pc + 4)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 4)) return false; return true; @@ -1673,11 +1778,11 @@ EmulateInstructionMIPS64::Emulate_BEQZALC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -1688,10 +1793,10 @@ EmulateInstructionMIPS64::Emulate_BEQZALC (llvm::MCInst& insn) else target = pc + 4; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips64, pc + 4)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 4)) return false; return true; @@ -1715,11 +1820,11 @@ EmulateInstructionMIPS64::Emulate_BNEZALC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -1730,10 +1835,10 @@ EmulateInstructionMIPS64::Emulate_BNEZALC (llvm::MCInst& insn) else target = pc + 4; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips64, pc + 4)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 4)) return false; return true; @@ -1756,11 +1861,11 @@ EmulateInstructionMIPS64::Emulate_BGEZ (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -1771,7 +1876,7 @@ EmulateInstructionMIPS64::Emulate_BGEZ (llvm::MCInst& insn) else target = pc + 8; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -1790,7 +1895,7 @@ EmulateInstructionMIPS64::Emulate_BC (llvm::MCInst& insn) */ offset = insn.getOperand(0).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; @@ -1798,7 +1903,7 @@ EmulateInstructionMIPS64::Emulate_BC (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -1821,15 +1926,15 @@ EmulateInstructionMIPS64::Emulate_BEQC (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; - rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rt, 0, &success); + rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success); if (!success) return false; @@ -1841,7 +1946,7 @@ EmulateInstructionMIPS64::Emulate_BEQC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -1864,15 +1969,15 @@ EmulateInstructionMIPS64::Emulate_BNEC (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; - rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rt, 0, &success); + rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success); if (!success) return false; @@ -1884,7 +1989,7 @@ EmulateInstructionMIPS64::Emulate_BNEC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -1908,15 +2013,15 @@ EmulateInstructionMIPS64::Emulate_BLTC (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; - rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rt, 0, &success); + rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success); if (!success) return false; @@ -1928,7 +2033,7 @@ EmulateInstructionMIPS64::Emulate_BLTC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -1952,15 +2057,15 @@ EmulateInstructionMIPS64::Emulate_BGEC (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; - rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rt, 0, &success); + rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success); if (!success) return false; @@ -1972,7 +2077,7 @@ EmulateInstructionMIPS64::Emulate_BGEC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -1996,15 +2101,15 @@ EmulateInstructionMIPS64::Emulate_BLTUC (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; - rt_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rt, 0, &success); + rt_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success); if (!success) return false; @@ -2016,7 +2121,7 @@ EmulateInstructionMIPS64::Emulate_BLTUC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -2040,15 +2145,15 @@ EmulateInstructionMIPS64::Emulate_BGEUC (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; - rt_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rt, 0, &success); + rt_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success); if (!success) return false; @@ -2060,7 +2165,7 @@ EmulateInstructionMIPS64::Emulate_BGEUC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -2083,11 +2188,11 @@ EmulateInstructionMIPS64::Emulate_BLTZC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -2099,7 +2204,7 @@ EmulateInstructionMIPS64::Emulate_BLTZC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -2122,11 +2227,11 @@ EmulateInstructionMIPS64::Emulate_BLEZC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -2138,7 +2243,7 @@ EmulateInstructionMIPS64::Emulate_BLEZC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -2161,11 +2266,11 @@ EmulateInstructionMIPS64::Emulate_BGEZC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -2177,7 +2282,7 @@ EmulateInstructionMIPS64::Emulate_BGEZC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -2200,11 +2305,11 @@ EmulateInstructionMIPS64::Emulate_BGTZC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -2216,7 +2321,7 @@ EmulateInstructionMIPS64::Emulate_BGTZC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -2239,11 +2344,11 @@ EmulateInstructionMIPS64::Emulate_BEQZC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -2255,7 +2360,7 @@ EmulateInstructionMIPS64::Emulate_BEQZC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -2278,11 +2383,11 @@ EmulateInstructionMIPS64::Emulate_BNEZC (llvm::MCInst& insn) rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; @@ -2294,7 +2399,7 @@ EmulateInstructionMIPS64::Emulate_BNEZC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -2325,15 +2430,15 @@ EmulateInstructionMIPS64::Emulate_BOVC (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; - rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rt, 0, &success); + rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success); if (!success) return false; @@ -2345,7 +2450,7 @@ EmulateInstructionMIPS64::Emulate_BOVC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -2369,15 +2474,15 @@ EmulateInstructionMIPS64::Emulate_BNVC (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); offset = insn.getOperand(2).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; - rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rt, 0, &success); + rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success); if (!success) return false; @@ -2389,7 +2494,7 @@ EmulateInstructionMIPS64::Emulate_BNVC (llvm::MCInst& insn) Context context; context.type = eContextRelativeBranchImmediate; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -2408,7 +2513,7 @@ EmulateInstructionMIPS64::Emulate_J (llvm::MCInst& insn) */ offset = insn.getOperand(0).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; @@ -2417,7 +2522,7 @@ EmulateInstructionMIPS64::Emulate_J (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, pc)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, pc)) return false; return true; @@ -2436,7 +2541,7 @@ EmulateInstructionMIPS64::Emulate_JAL (llvm::MCInst& insn) */ offset = insn.getOperand(0).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; @@ -2445,10 +2550,10 @@ EmulateInstructionMIPS64::Emulate_JAL (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips64, pc + 8)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 8)) return false; return true; @@ -2469,20 +2574,20 @@ EmulateInstructionMIPS64::Emulate_JALR (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); rs = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, rs_val)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, rs_val)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rt, pc + 8)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_zero_mips64 + rt, pc + 8)) return false; return true; @@ -2504,11 +2609,11 @@ EmulateInstructionMIPS64::Emulate_JIALC (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rt, 0, &success); + rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success); if (!success) return false; @@ -2516,10 +2621,10 @@ EmulateInstructionMIPS64::Emulate_JIALC (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_ra_mips64, pc + 4)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_ra_mips64, pc + 4)) return false; return true; @@ -2540,7 +2645,7 @@ EmulateInstructionMIPS64::Emulate_JIC (llvm::MCInst& insn) rt = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rt, 0, &success); + rt_val = (int64_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rt, 0, &success); if (!success) return false; @@ -2548,7 +2653,7 @@ EmulateInstructionMIPS64::Emulate_JIC (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -2567,13 +2672,13 @@ EmulateInstructionMIPS64::Emulate_JR (llvm::MCInst& insn) */ rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); - rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + rs, 0, &success); + rs_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + rs, 0, &success); if (!success) return false; Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, rs_val)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, rs_val)) return false; return true; @@ -2596,11 +2701,11 @@ EmulateInstructionMIPS64::Emulate_BC1F (llvm::MCInst& insn) cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips64, 0, &success); + fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_fcsr_mips64, 0, &success); if (!success) return false; @@ -2614,7 +2719,7 @@ EmulateInstructionMIPS64::Emulate_BC1F (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -2637,11 +2742,11 @@ EmulateInstructionMIPS64::Emulate_BC1T (llvm::MCInst& insn) cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips64, 0, &success); + fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_fcsr_mips64, 0, &success); if (!success) return false; @@ -2655,7 +2760,7 @@ EmulateInstructionMIPS64::Emulate_BC1T (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -2678,11 +2783,11 @@ EmulateInstructionMIPS64::Emulate_BC1FL (llvm::MCInst& insn) cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips64, 0, &success); + fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_fcsr_mips64, 0, &success); if (!success) return false; @@ -2696,7 +2801,7 @@ EmulateInstructionMIPS64::Emulate_BC1FL (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -2719,11 +2824,11 @@ EmulateInstructionMIPS64::Emulate_BC1TL (llvm::MCInst& insn) cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips64, 0, &success); + fcsr = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_fcsr_mips64, 0, &success); if (!success) return false; @@ -2737,7 +2842,7 @@ EmulateInstructionMIPS64::Emulate_BC1TL (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -2761,11 +2866,11 @@ EmulateInstructionMIPS64::Emulate_BC1EQZ (llvm::MCInst& insn) ft = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - ft_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + ft, 0, &success); + ft_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + ft, 0, &success); if (!success) return false; @@ -2776,7 +2881,7 @@ EmulateInstructionMIPS64::Emulate_BC1EQZ (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -2800,11 +2905,11 @@ EmulateInstructionMIPS64::Emulate_BC1NEZ (llvm::MCInst& insn) ft = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - ft_val = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_zero_mips64 + ft, 0, &success); + ft_val = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips64 + ft, 0, &success); if (!success) return false; @@ -2815,7 +2920,7 @@ EmulateInstructionMIPS64::Emulate_BC1NEZ (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -2839,11 +2944,11 @@ EmulateInstructionMIPS64::Emulate_BC1ANY2F (llvm::MCInst& insn) cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips64, 0, &success); + fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_fcsr_mips64, 0, &success); if (!success) return false; @@ -2858,7 +2963,7 @@ EmulateInstructionMIPS64::Emulate_BC1ANY2F (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -2882,11 +2987,11 @@ EmulateInstructionMIPS64::Emulate_BC1ANY2T (llvm::MCInst& insn) cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips64, 0, &success); + fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_fcsr_mips64, 0, &success); if (!success) return false; @@ -2901,7 +3006,7 @@ EmulateInstructionMIPS64::Emulate_BC1ANY2T (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -2927,11 +3032,11 @@ EmulateInstructionMIPS64::Emulate_BC1ANY4F (llvm::MCInst& insn) cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips64, 0, &success); + fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_fcsr_mips64, 0, &success); if (!success) return false; @@ -2946,7 +3051,7 @@ EmulateInstructionMIPS64::Emulate_BC1ANY4F (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; @@ -2972,11 +3077,11 @@ EmulateInstructionMIPS64::Emulate_BC1ANY4T (llvm::MCInst& insn) cc = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); offset = insn.getOperand(1).getImm(); - pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success); + pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); if (!success) return false; - fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_fcsr_mips64, 0, &success); + fcsr = (uint32_t) ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_fcsr_mips64, 0, &success); if (!success) return false; @@ -2991,8 +3096,234 @@ EmulateInstructionMIPS64::Emulate_BC1ANY4T (llvm::MCInst& insn) Context context; - if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target)) + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) return false; return true; } + +bool +EmulateInstructionMIPS64::Emulate_BNZB (llvm::MCInst& insn) +{ + return Emulate_MSA_Branch_DF(insn, 1, true); +} + +bool +EmulateInstructionMIPS64::Emulate_BNZH (llvm::MCInst& insn) +{ + return Emulate_MSA_Branch_DF(insn, 2, true); +} + +bool +EmulateInstructionMIPS64::Emulate_BNZW (llvm::MCInst& insn) +{ + return Emulate_MSA_Branch_DF(insn, 4, true); +} + +bool +EmulateInstructionMIPS64::Emulate_BNZD (llvm::MCInst& insn) +{ + return Emulate_MSA_Branch_DF(insn, 8, true); +} + +bool +EmulateInstructionMIPS64::Emulate_BZB (llvm::MCInst& insn) +{ + return Emulate_MSA_Branch_DF(insn, 1, false); +} + +bool +EmulateInstructionMIPS64::Emulate_BZH (llvm::MCInst& insn) +{ + return Emulate_MSA_Branch_DF(insn, 2, false); +} + +bool +EmulateInstructionMIPS64::Emulate_BZW (llvm::MCInst& insn) +{ + return Emulate_MSA_Branch_DF(insn, 4, false); +} + +bool +EmulateInstructionMIPS64::Emulate_BZD (llvm::MCInst& insn) +{ + return Emulate_MSA_Branch_DF(insn, 8, false); +} + +bool +EmulateInstructionMIPS64::Emulate_MSA_Branch_DF (llvm::MCInst& insn, int element_byte_size, bool bnz) +{ + bool success = false, branch_hit = true; + int64_t target = 0; + RegisterValue reg_value; + uint8_t * ptr = NULL; + + uint32_t wt = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); + int64_t offset = insn.getOperand(1).getImm(); + + int64_t pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); + if (!success) + return false; + + if (ReadRegister (eRegisterKindDWARF, dwarf_w0_mips64 + wt, reg_value)) + ptr = (uint8_t *)reg_value.GetBytes(); + else + return false; + + for(int i = 0; i < 16 / element_byte_size; i++) + { + switch(element_byte_size) + { + case 1: + if((*ptr == 0 && bnz) || (*ptr != 0 && !bnz) ) + branch_hit = false; + break; + case 2: + if((*(uint16_t *)ptr == 0 && bnz) || (*(uint16_t *)ptr != 0 && !bnz)) + branch_hit = false; + break; + case 4: + if((*(uint32_t *)ptr == 0 && bnz) || (*(uint32_t *)ptr != 0 && !bnz)) + branch_hit = false; + break; + case 8: + if((*(uint64_t *)ptr == 0 && bnz) || (*(uint64_t *)ptr != 0 && !bnz)) + branch_hit = false; + break; + } + if(!branch_hit) + break; + ptr = ptr + element_byte_size; + } + + if(branch_hit) + target = pc + offset; + else + target = pc + 8; + + Context context; + context.type = eContextRelativeBranchImmediate; + + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) + return false; + + return true; +} + +bool +EmulateInstructionMIPS64::Emulate_BNZV (llvm::MCInst& insn) +{ + return Emulate_MSA_Branch_V (insn, true); +} + +bool +EmulateInstructionMIPS64::Emulate_BZV (llvm::MCInst& insn) +{ + return Emulate_MSA_Branch_V (insn, false); +} + +bool +EmulateInstructionMIPS64::Emulate_MSA_Branch_V (llvm::MCInst& insn, bool bnz) +{ + bool success = false; + int64_t target = 0; + llvm::APInt wr_val = llvm::APInt::getNullValue(128); + llvm::APInt fail_value = llvm::APInt::getMaxValue(128); + llvm::APInt zero_value = llvm::APInt::getNullValue(128); + RegisterValue reg_value; + + uint32_t wt = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); + int64_t offset = insn.getOperand(1).getImm(); + + int64_t pc = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_pc_mips64, 0, &success); + if (!success) + return false; + + if (ReadRegister (eRegisterKindDWARF, dwarf_w0_mips64 + wt, reg_value)) + wr_val = reg_value.GetAsUInt128(fail_value); + else + return false; + + if((llvm::APInt::isSameValue(zero_value, wr_val) && !bnz) || (!llvm::APInt::isSameValue(zero_value, wr_val) && bnz)) + target = pc + offset; + else + target = pc + 8; + + Context context; + context.type = eContextRelativeBranchImmediate; + + if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_pc_mips64, target)) + return false; + + return true; +} + +bool +EmulateInstructionMIPS64::Emulate_LDST_Imm (llvm::MCInst& insn) +{ + bool success = false; + uint32_t base; + int64_t imm, address; + Context bad_vaddr_context; + + uint32_t num_operands = insn.getNumOperands(); + base = m_reg_info->getEncodingValue (insn.getOperand(num_operands-2).getReg()); + imm = insn.getOperand(num_operands-1).getImm(); + + RegisterInfo reg_info_base; + if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips + base, reg_info_base)) + return false; + + /* read base register */ + address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + base, 0, &success); + if (!success) + return false; + + /* destination address */ + address = address + imm; + + /* Set the bad_vaddr register with base address used in the instruction */ + bad_vaddr_context.type = eContextInvalid; + WriteRegisterUnsigned (bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips, address); + + return true; +} + +bool +EmulateInstructionMIPS64::Emulate_LDST_Reg (llvm::MCInst& insn) +{ + bool success = false; + uint32_t base, index; + int64_t address, index_address; + Context bad_vaddr_context; + + uint32_t num_operands = insn.getNumOperands(); + base = m_reg_info->getEncodingValue (insn.getOperand(num_operands-2).getReg()); + index = m_reg_info->getEncodingValue (insn.getOperand(num_operands-1).getReg()); + + RegisterInfo reg_info_base, reg_info_index; + if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips + base, reg_info_base)) + return false; + + if (!GetRegisterInfo (eRegisterKindDWARF, dwarf_zero_mips + index, reg_info_index)) + return false; + + /* read base register */ + address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + base, 0, &success); + if (!success) + return false; + + /* read index register */ + index_address = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_zero_mips + index, 0, &success); + if (!success) + return false; + + /* destination address */ + address = address + index_address; + + /* Set the bad_vaddr register with base address used in the instruction */ + bad_vaddr_context.type = eContextInvalid; + WriteRegisterUnsigned (bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips, address); + + return true; +} |