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author | Emmanuel Vadot <manu@FreeBSD.org> | 2018-02-09 22:33:22 +0000 |
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committer | Emmanuel Vadot <manu@FreeBSD.org> | 2018-02-09 22:33:22 +0000 |
commit | 16ae49e2bea5badc71c2265966ec2a9b0ba541dc (patch) | |
tree | 5ff3ed27eadaf4f2d05b771bc108bd500b3d8f48 /src/arm/bcm47189-luxul-xap-810.dts | |
parent | 550370858c61e6f7fe3832de73daa9cc25ba716a (diff) | |
download | src-16ae49e2bea5badc71c2265966ec2a9b0ba541dc.tar.gz src-16ae49e2bea5badc71c2265966ec2a9b0ba541dc.zip |
Update our copies of the Device Tree Source to Linux 4.15vendor/device-tree/4.15
Notes
Notes:
svn path=/vendor/device-tree/dist/; revision=329088
svn path=/vendor/device-tree/4.15/; revision=329090; tag=vendor/device-tree/4.15
Diffstat (limited to 'src/arm/bcm47189-luxul-xap-810.dts')
-rw-r--r-- | src/arm/bcm47189-luxul-xap-810.dts | 87 |
1 files changed, 87 insertions, 0 deletions
diff --git a/src/arm/bcm47189-luxul-xap-810.dts b/src/arm/bcm47189-luxul-xap-810.dts new file mode 100644 index 000000000000..214df18f3a75 --- /dev/null +++ b/src/arm/bcm47189-luxul-xap-810.dts @@ -0,0 +1,87 @@ +/* + * Copyright 2017 Luxul Inc. + * + * Licensed under the ISC license. + */ + +/dts-v1/; + +#include "bcm53573.dtsi" + +/ { + compatible = "luxul,xap-810-v1", "brcm,bcm47189", "brcm,bcm53573"; + model = "Luxul XAP-810 V1"; + + chosen { + bootargs = "earlycon"; + }; + + memory { + reg = <0x00000000 0x08000000>; + }; + + leds { + compatible = "gpio-leds"; + + 5ghz { + label = "bcm53xx:blue:5ghz"; + gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + + system { + label = "bcm53xx:green:system"; + gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "timer"; + }; + }; + + pcie0_leds { + compatible = "gpio-leds"; + + 2ghz { + label = "bcm53xx:blue:2ghz"; + gpios = <&pcie0_chipcommon 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-off"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + restart { + label = "Reset"; + linux,code = <KEY_RESTART>; + gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&pcie0 { + ranges = <0x00000000 0 0 0 0 0x00100000>; + #address-cells = <3>; + #size-cells = <2>; + + bridge@0,0,0 { + reg = <0x0000 0 0 0 0>; + ranges = <0x00000000 0 0 0 0 0 0 0x00100000>; + #address-cells = <3>; + #size-cells = <2>; + + wifi@0,1,0 { + reg = <0x0000 0 0 0 0>; + ranges = <0x00000000 0 0 0 0x00100000>; + #address-cells = <1>; + #size-cells = <1>; + + pcie0_chipcommon: chipcommon@0 { + reg = <0 0x1000>; + + gpio-controller; + #gpio-cells = <2>; + }; + }; + }; +}; |