diff options
author | Andrew Turner <andrew@FreeBSD.org> | 2016-07-27 10:33:45 +0000 |
---|---|---|
committer | Andrew Turner <andrew@FreeBSD.org> | 2016-07-27 10:33:45 +0000 |
commit | c7716441be3a4a48aa7b7cdf69a15625c1cd8ef5 (patch) | |
tree | 2a59dacd09463974e72f84b0e05f237b0ba3f57b /src/arm/sh73a0.dtsi | |
parent | 235ad806ee815395bce54dc1b0ce1c06cd29b44a (diff) | |
download | src-c7716441be3a4a48aa7b7cdf69a15625c1cd8ef5.tar.gz src-c7716441be3a4a48aa7b7cdf69a15625c1cd8ef5.zip |
Import the updated devicetree files fromvendor/device-tree/devicetree-965f3718
Notes
Notes:
svn path=/vendor/device-tree/dist/; revision=303380
svn path=/vendor/device-tree/devicetree-965f3718/; revision=303381; tag=vendor/device-tree/devicetree-965f3718
Diffstat (limited to 'src/arm/sh73a0.dtsi')
-rw-r--r-- | src/arm/sh73a0.dtsi | 275 |
1 files changed, 123 insertions, 152 deletions
diff --git a/src/arm/sh73a0.dtsi b/src/arm/sh73a0.dtsi index 3a6056f9f0d2..c4f434cdec60 100644 --- a/src/arm/sh73a0.dtsi +++ b/src/arm/sh73a0.dtsi @@ -43,7 +43,7 @@ timer@f0000600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0xf0000600 0x20>; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; clocks = <&twd_clk>; }; @@ -58,7 +58,7 @@ L2: cache-controller { compatible = "arm,pl310-cache"; reg = <0xf0100000 0x1000>; - interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&pd_a3sm>; arm,data-latency = <3 3 3>; arm,tag-latency = <2 2 2>; @@ -70,8 +70,8 @@ sbsc2: memory-controller@fb400000 { compatible = "renesas,sbsc-sh73a0"; reg = <0xfb400000 0x400>; - interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>, - <0 38 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "sec", "temp"; power-domains = <&pd_a4bc1>; }; @@ -79,22 +79,22 @@ sbsc1: memory-controller@fe400000 { compatible = "renesas,sbsc-sh73a0"; reg = <0xfe400000 0x400>; - interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>, - <0 36 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "sec", "temp"; power-domains = <&pd_a4bc0>; }; pmu { compatible = "arm,cortex-a9-pmu"; - interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>, - <0 56 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; }; cmt1: timer@e6138000 { compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48"; reg = <0xe6138000 0x200>; - interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks SH73A0_CLK_CMT1>; clock-names = "fck"; power-domains = <&pd_c5>; @@ -113,14 +113,14 @@ <0xe6900020 1>, <0xe6900040 1>, <0xe6900060 1>; - interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH - 0 2 IRQ_TYPE_LEVEL_HIGH - 0 3 IRQ_TYPE_LEVEL_HIGH - 0 4 IRQ_TYPE_LEVEL_HIGH - 0 5 IRQ_TYPE_LEVEL_HIGH - 0 6 IRQ_TYPE_LEVEL_HIGH - 0 7 IRQ_TYPE_LEVEL_HIGH - 0 8 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; power-domains = <&pd_a4s>; control-parent; @@ -135,14 +135,14 @@ <0xe6900024 1>, <0xe6900044 1>, <0xe6900064 1>; - interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH - 0 10 IRQ_TYPE_LEVEL_HIGH - 0 11 IRQ_TYPE_LEVEL_HIGH - 0 12 IRQ_TYPE_LEVEL_HIGH - 0 13 IRQ_TYPE_LEVEL_HIGH - 0 14 IRQ_TYPE_LEVEL_HIGH - 0 15 IRQ_TYPE_LEVEL_HIGH - 0 16 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; power-domains = <&pd_a4s>; control-parent; @@ -157,14 +157,14 @@ <0xe6900028 1>, <0xe6900048 1>, <0xe6900068 1>; - interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH - 0 18 IRQ_TYPE_LEVEL_HIGH - 0 19 IRQ_TYPE_LEVEL_HIGH - 0 20 IRQ_TYPE_LEVEL_HIGH - 0 21 IRQ_TYPE_LEVEL_HIGH - 0 22 IRQ_TYPE_LEVEL_HIGH - 0 23 IRQ_TYPE_LEVEL_HIGH - 0 24 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; power-domains = <&pd_a4s>; control-parent; @@ -179,14 +179,14 @@ <0xe690002c 1>, <0xe690004c 1>, <0xe690006c 1>; - interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH - 0 26 IRQ_TYPE_LEVEL_HIGH - 0 27 IRQ_TYPE_LEVEL_HIGH - 0 28 IRQ_TYPE_LEVEL_HIGH - 0 29 IRQ_TYPE_LEVEL_HIGH - 0 30 IRQ_TYPE_LEVEL_HIGH - 0 31 IRQ_TYPE_LEVEL_HIGH - 0 32 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; power-domains = <&pd_a4s>; control-parent; @@ -197,10 +197,10 @@ #size-cells = <0>; compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; reg = <0xe6820000 0x425>; - interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH - 0 168 IRQ_TYPE_LEVEL_HIGH - 0 169 IRQ_TYPE_LEVEL_HIGH - 0 170 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp1_clks SH73A0_CLK_IIC0>; power-domains = <&pd_a3sp>; status = "disabled"; @@ -211,10 +211,10 @@ #size-cells = <0>; compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; reg = <0xe6822000 0x425>; - interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH - 0 52 IRQ_TYPE_LEVEL_HIGH - 0 53 IRQ_TYPE_LEVEL_HIGH - 0 54 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks SH73A0_CLK_IIC1>; power-domains = <&pd_a3sp>; status = "disabled"; @@ -225,10 +225,10 @@ #size-cells = <0>; compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; reg = <0xe6824000 0x425>; - interrupts = <0 171 IRQ_TYPE_LEVEL_HIGH - 0 172 IRQ_TYPE_LEVEL_HIGH - 0 173 IRQ_TYPE_LEVEL_HIGH - 0 174 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks SH73A0_CLK_IIC2>; power-domains = <&pd_a3sp>; status = "disabled"; @@ -239,10 +239,10 @@ #size-cells = <0>; compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; reg = <0xe6826000 0x425>; - interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH - 0 184 IRQ_TYPE_LEVEL_HIGH - 0 185 IRQ_TYPE_LEVEL_HIGH - 0 186 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp4_clks SH73A0_CLK_IIC3>; power-domains = <&pd_a3sp>; status = "disabled"; @@ -253,10 +253,10 @@ #size-cells = <0>; compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; reg = <0xe6828000 0x425>; - interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH - 0 188 IRQ_TYPE_LEVEL_HIGH - 0 189 IRQ_TYPE_LEVEL_HIGH - 0 190 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp4_clks SH73A0_CLK_IIC4>; power-domains = <&pd_c5>; status = "disabled"; @@ -265,8 +265,8 @@ mmcif: mmc@e6bd0000 { compatible = "renesas,sh-mmcif"; reg = <0xe6bd0000 0x100>; - interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH - 0 141 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>; power-domains = <&pd_a3sp>; reg-io-width = <4>; @@ -276,7 +276,7 @@ msiof0: spi@e6e20000 { compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof"; reg = <0xe6e20000 0x0064>; - interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks SH73A0_CLK_MSIOF0>; power-domains = <&pd_a3sp>; #address-cells = <1>; @@ -287,7 +287,7 @@ msiof1: spi@e6e10000 { compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof"; reg = <0xe6e10000 0x0064>; - interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks SH73A0_CLK_MSIOF1>; power-domains = <&pd_a3sp>; #address-cells = <1>; @@ -298,7 +298,7 @@ msiof2: spi@e6e00000 { compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof"; reg = <0xe6e00000 0x0064>; - interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks SH73A0_CLK_MSIOF2>; power-domains = <&pd_a3sp>; #address-cells = <1>; @@ -309,7 +309,7 @@ msiof3: spi@e6c90000 { compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof"; reg = <0xe6c90000 0x0064>; - interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks SH73A0_CLK_MSIOF3>; power-domains = <&pd_a3sp>; #address-cells = <1>; @@ -320,9 +320,9 @@ sdhi0: sd@ee100000 { compatible = "renesas,sdhi-sh73a0"; reg = <0xee100000 0x100>; - interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH - 0 84 IRQ_TYPE_LEVEL_HIGH - 0 85 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks SH73A0_CLK_SDHI0>; power-domains = <&pd_a3sp>; cap-sd-highspeed; @@ -333,8 +333,8 @@ sdhi1: sd@ee120000 { compatible = "renesas,sdhi-sh73a0"; reg = <0xee120000 0x100>; - interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH - 0 89 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks SH73A0_CLK_SDHI1>; power-domains = <&pd_a3sp>; toshiba,mmc-wrprotect-disable; @@ -345,8 +345,8 @@ sdhi2: sd@ee140000 { compatible = "renesas,sdhi-sh73a0"; reg = <0xee140000 0x100>; - interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH - 0 105 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks SH73A0_CLK_SDHI2>; power-domains = <&pd_a3sp>; toshiba,mmc-wrprotect-disable; @@ -357,9 +357,9 @@ scifa0: serial@e6c40000 { compatible = "renesas,scifa-sh73a0", "renesas,scifa"; reg = <0xe6c40000 0x100>; - interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>; - clock-names = "sci_ick"; + clock-names = "fck"; power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -367,9 +367,9 @@ scifa1: serial@e6c50000 { compatible = "renesas,scifa-sh73a0", "renesas,scifa"; reg = <0xe6c50000 0x100>; - interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>; - clock-names = "sci_ick"; + clock-names = "fck"; power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -377,9 +377,9 @@ scifa2: serial@e6c60000 { compatible = "renesas,scifa-sh73a0", "renesas,scifa"; reg = <0xe6c60000 0x100>; - interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>; - clock-names = "sci_ick"; + clock-names = "fck"; power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -387,9 +387,9 @@ scifa3: serial@e6c70000 { compatible = "renesas,scifa-sh73a0", "renesas,scifa"; reg = <0xe6c70000 0x100>; - interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>; - clock-names = "sci_ick"; + clock-names = "fck"; power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -397,9 +397,9 @@ scifa4: serial@e6c80000 { compatible = "renesas,scifa-sh73a0", "renesas,scifa"; reg = <0xe6c80000 0x100>; - interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>; - clock-names = "sci_ick"; + clock-names = "fck"; power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -407,9 +407,9 @@ scifa5: serial@e6cb0000 { compatible = "renesas,scifa-sh73a0", "renesas,scifa"; reg = <0xe6cb0000 0x100>; - interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>; - clock-names = "sci_ick"; + clock-names = "fck"; power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -417,9 +417,9 @@ scifa6: serial@e6cc0000 { compatible = "renesas,scifa-sh73a0", "renesas,scifa"; reg = <0xe6cc0000 0x100>; - interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>; - clock-names = "sci_ick"; + clock-names = "fck"; power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -427,9 +427,9 @@ scifa7: serial@e6cd0000 { compatible = "renesas,scifa-sh73a0", "renesas,scifa"; reg = <0xe6cd0000 0x100>; - interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>; - clock-names = "sci_ick"; + clock-names = "fck"; power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -437,9 +437,9 @@ scifb: serial@e6c30000 { compatible = "renesas,scifb-sh73a0", "renesas,scifb"; reg = <0xe6c30000 0x100>; - interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks SH73A0_CLK_SCIFB>; - clock-names = "sci_ick"; + clock-names = "fck"; power-domains = <&pd_a3sp>; status = "disabled"; }; @@ -579,7 +579,7 @@ #sound-dai-cells = <1>; compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2"; reg = <0xec230000 0x400>; - interrupts = <0 146 0x4>; + interrupts = <GIC_SPI 146 0x4>; power-domains = <&pd_a4mp>; status = "disabled"; }; @@ -591,7 +591,7 @@ #size-cells = <1>; ranges = <0 0 0x20000000>; reg = <0xfec10000 0x400>; - interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; clocks = <&zb_clk>; power-domains = <&pd_a4s>; }; @@ -602,39 +602,33 @@ ranges; /* External root clocks */ - extalr_clk: extalr_clk { + extalr_clk: extalr { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; - clock-output-names = "extalr"; }; - extal1_clk: extal1_clk { + extal1_clk: extal1 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; - clock-output-names = "extal1"; }; - extal2_clk: extal2_clk { + extal2_clk: extal2 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-output-names = "extal2"; }; - extcki_clk: extcki_clk { + extcki_clk: extcki { compatible = "fixed-clock"; #clock-cells = <0>; - clock-output-names = "extcki"; }; - fsiack_clk: fsiack_clk { + fsiack_clk: fsiack { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; - clock-output-names = "fsiack"; }; - fsibck_clk: fsibck_clk { + fsibck_clk: fsibck { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; - clock-output-names = "fsibck"; }; /* Special CPG clocks */ @@ -650,7 +644,7 @@ }; /* Variable factor clocks (DIV6) */ - vclk1_clk: vclk1_clk@e6150008 { + vclk1_clk: vclk1@e6150008 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150008 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, @@ -658,9 +652,8 @@ <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>, <0>; #clock-cells = <0>; - clock-output-names = "vclk1"; }; - vclk2_clk: vclk2_clk@e615000c { + vclk2_clk: vclk2@e615000c { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe615000c 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, @@ -668,9 +661,8 @@ <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>, <0>; #clock-cells = <0>; - clock-output-names = "vclk2"; }; - vclk3_clk: vclk3_clk@e615001c { + vclk3_clk: vclk3@e615001c { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe615001c 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, @@ -678,7 +670,6 @@ <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>, <0>; #clock-cells = <0>; - clock-output-names = "vclk3"; }; zb_clk: zb_clk@e6150010 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; @@ -688,168 +679,148 @@ #clock-cells = <0>; clock-output-names = "zb"; }; - flctl_clk: flctl_clk@e6150014 { + flctl_clk: flctlck@e6150014 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150014 4>; clocks = <&pll1_div2_clk>, <0>, <&cpg_clocks SH73A0_CLK_PLL2>, <0>; #clock-cells = <0>; - clock-output-names = "flctlck"; }; - sdhi0_clk: sdhi0_clk@e6150074 { + sdhi0_clk: sdhi0ck@e6150074 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150074 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, <&pll1_div13_clk>, <0>; #clock-cells = <0>; - clock-output-names = "sdhi0ck"; }; - sdhi1_clk: sdhi1_clk@e6150078 { + sdhi1_clk: sdhi1ck@e6150078 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150078 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, <&pll1_div13_clk>, <0>; #clock-cells = <0>; - clock-output-names = "sdhi1ck"; }; - sdhi2_clk: sdhi2_clk@e615007c { + sdhi2_clk: sdhi2ck@e615007c { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe615007c 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, <&pll1_div13_clk>, <0>; #clock-cells = <0>; - clock-output-names = "sdhi2ck"; }; - fsia_clk: fsia_clk@e6150018 { + fsia_clk: fsia@e6150018 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150018 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, <&fsiack_clk>, <&fsiack_clk>; #clock-cells = <0>; - clock-output-names = "fsia"; }; - fsib_clk: fsib_clk@e6150090 { + fsib_clk: fsib@e6150090 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150090 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, <&fsibck_clk>, <&fsibck_clk>; #clock-cells = <0>; - clock-output-names = "fsib"; }; - sub_clk: sub_clk@e6150080 { + sub_clk: sub@e6150080 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150080 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, <&extal2_clk>, <&extal2_clk>; #clock-cells = <0>; - clock-output-names = "sub"; }; - spua_clk: spua_clk@e6150084 { + spua_clk: spua@e6150084 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150084 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, <&extal2_clk>, <&extal2_clk>; #clock-cells = <0>; - clock-output-names = "spua"; }; - spuv_clk: spuv_clk@e6150094 { + spuv_clk: spuv@e6150094 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150094 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, <&extal2_clk>, <&extal2_clk>; #clock-cells = <0>; - clock-output-names = "spuv"; }; - msu_clk: msu_clk@e6150088 { + msu_clk: msu@e6150088 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150088 4>; clocks = <&pll1_div2_clk>, <0>, <&cpg_clocks SH73A0_CLK_PLL2>, <0>; #clock-cells = <0>; - clock-output-names = "msu"; }; - hsi_clk: hsi_clk@e615008c { + hsi_clk: hsi@e615008c { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe615008c 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, <&pll1_div7_clk>, <0>; #clock-cells = <0>; - clock-output-names = "hsi"; }; - mfg1_clk: mfg1_clk@e6150098 { + mfg1_clk: mfg1@e6150098 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150098 4>; clocks = <&pll1_div2_clk>, <0>, <&cpg_clocks SH73A0_CLK_PLL2>, <0>; #clock-cells = <0>; - clock-output-names = "mfg1"; }; - mfg2_clk: mfg2_clk@e615009c { + mfg2_clk: mfg2@e615009c { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe615009c 4>; clocks = <&pll1_div2_clk>, <0>, <&cpg_clocks SH73A0_CLK_PLL2>, <0>; #clock-cells = <0>; - clock-output-names = "mfg2"; }; - dsit_clk: dsit_clk@e6150060 { + dsit_clk: dsit@e6150060 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150060 4>; clocks = <&pll1_div2_clk>, <0>, <&cpg_clocks SH73A0_CLK_PLL2>, <0>; #clock-cells = <0>; - clock-output-names = "dsit"; }; - dsi0p_clk: dsi0p_clk@e6150064 { + dsi0p_clk: dsi0pck@e6150064 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150064 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, <&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>, <&extcki_clk>, <0>, <0>, <0>; #clock-cells = <0>; - clock-output-names = "dsi0pck"; }; /* Fixed factor clocks */ - main_div2_clk: main_div2_clk { + main_div2_clk: main_div2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks SH73A0_CLK_MAIN>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "main_div2"; }; - pll1_div2_clk: pll1_div2_clk { + pll1_div2_clk: pll1_div2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks SH73A0_CLK_PLL1>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "pll1_div2"; }; - pll1_div7_clk: pll1_div7_clk { + pll1_div7_clk: pll1_div7 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks SH73A0_CLK_PLL1>; #clock-cells = <0>; clock-div = <7>; clock-mult = <1>; - clock-output-names = "pll1_div7"; }; - pll1_div13_clk: pll1_div13_clk { + pll1_div13_clk: pll1_div13 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks SH73A0_CLK_PLL1>; #clock-cells = <0>; clock-div = <13>; clock-mult = <1>; - clock-output-names = "pll1_div13"; }; - twd_clk: twd_clk { + twd_clk: twd { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks SH73A0_CLK_Z>; #clock-cells = <0>; clock-div = <4>; clock-mult = <1>; - clock-output-names = "twd"; }; /* Gate clocks */ |