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authorRui Paulo <rpaulo@FreeBSD.org>2014-04-08 04:05:04 +0000
committerRui Paulo <rpaulo@FreeBSD.org>2014-04-08 04:05:04 +0000
commit9e63671c57a3a18134bd37350349edf113faa51d (patch)
tree9fb10a436cc78e5e7d58c6115352931abf12a20e /sys/arm/freescale/imx/imx51_ipuv3_fbd.c
parent0d4700544fc7b619ba3ba3e6da35c0cc31a4700a (diff)
downloadsrc-9e63671c57a3a18134bd37350349edf113faa51d.tar.gz
src-9e63671c57a3a18134bd37350349edf113faa51d.zip
Updates to i.MX53:
* Define support for the SDHCI driver, although it doesn't work yet * Fix the memory mappings for IPU [1] Reviewed by: ray [1]
Notes
Notes: svn path=/head/; revision=264251
Diffstat (limited to 'sys/arm/freescale/imx/imx51_ipuv3_fbd.c')
-rw-r--r--sys/arm/freescale/imx/imx51_ipuv3_fbd.c47
1 files changed, 32 insertions, 15 deletions
diff --git a/sys/arm/freescale/imx/imx51_ipuv3_fbd.c b/sys/arm/freescale/imx/imx51_ipuv3_fbd.c
index 3bb72183bd79..25d17c7aa180 100644
--- a/sys/arm/freescale/imx/imx51_ipuv3_fbd.c
+++ b/sys/arm/freescale/imx/imx51_ipuv3_fbd.c
@@ -190,7 +190,7 @@ ipu3_fb_probe(device_t dev)
if (!ofw_bus_is_compatible(dev, "fsl,ipu3"))
return (ENXIO);
- device_set_desc(dev, "i.MX515 Image Processing Unit (FB)");
+ device_set_desc(dev, "i.MX5x Image Processing Unit v3 (FB)");
return (BUS_PROBE_DEFAULT);
}
@@ -201,70 +201,87 @@ ipu3_fb_attach(device_t dev)
struct ipu3sc_softc *sc = device_get_softc(dev);
bus_space_tag_t iot;
bus_space_handle_t ioh;
- int err;
+ phandle_t node;
+ pcell_t reg;
+ int err;
+ uintptr_t base;
ipu3sc_softc = sc;
- device_printf(dev, "\tclock gate status is %d\n",
- imx51_get_clk_gating(IMX51CLK_IPU_HSP_CLK_ROOT));
+ if (bootverbose)
+ device_printf(dev, "clock gate status is %d\n",
+ imx51_get_clk_gating(IMX51CLK_IPU_HSP_CLK_ROOT));
sc->dev = dev;
sc = device_get_softc(dev);
sc->iot = iot = fdtbus_bs_tag;
- device_printf(sc->dev, ": i.MX51 IPUV3 controller\n");
-
+ /*
+ * Retrieve the device address based on the start address in the
+ * DTS. The DTS for i.MX51 specifies 0x5e000000 as the first register
+ * address, so we just subtract IPU_CM_BASE to get the offset at which
+ * the IPU device was memory mapped.
+ * On i.MX53, the offset is 0.
+ */
+ node = ofw_bus_get_node(dev);
+ if ((OF_getprop(node, "reg", &reg, sizeof(reg))) <= 0)
+ base = 0;
+ else
+ base = fdt32_to_cpu(reg) - IPU_CM_BASE(0);
/* map controller registers */
- err = bus_space_map(iot, IPU_CM_BASE, IPU_CM_SIZE, 0, &ioh);
+ err = bus_space_map(iot, IPU_CM_BASE(base), IPU_CM_SIZE, 0, &ioh);
if (err)
goto fail_retarn_cm;
sc->cm_ioh = ioh;
/* map Display Multi FIFO Controller registers */
- err = bus_space_map(iot, IPU_DMFC_BASE, IPU_DMFC_SIZE, 0, &ioh);
+ err = bus_space_map(iot, IPU_DMFC_BASE(base), IPU_DMFC_SIZE, 0, &ioh);
if (err)
goto fail_retarn_dmfc;
sc->dmfc_ioh = ioh;
/* map Display Interface 0 registers */
- err = bus_space_map(iot, IPU_DI0_BASE, IPU_DI0_SIZE, 0, &ioh);
+ err = bus_space_map(iot, IPU_DI0_BASE(base), IPU_DI0_SIZE, 0, &ioh);
if (err)
goto fail_retarn_di0;
sc->di0_ioh = ioh;
/* map Display Interface 1 registers */
- err = bus_space_map(iot, IPU_DI1_BASE, IPU_DI0_SIZE, 0, &ioh);
+ err = bus_space_map(iot, IPU_DI1_BASE(base), IPU_DI0_SIZE, 0, &ioh);
if (err)
goto fail_retarn_di1;
sc->di1_ioh = ioh;
/* map Display Processor registers */
- err = bus_space_map(iot, IPU_DP_BASE, IPU_DP_SIZE, 0, &ioh);
+ err = bus_space_map(iot, IPU_DP_BASE(base), IPU_DP_SIZE, 0, &ioh);
if (err)
goto fail_retarn_dp;
sc->dp_ioh = ioh;
/* map Display Controller registers */
- err = bus_space_map(iot, IPU_DC_BASE, IPU_DC_SIZE, 0, &ioh);
+ err = bus_space_map(iot, IPU_DC_BASE(base), IPU_DC_SIZE, 0, &ioh);
if (err)
goto fail_retarn_dc;
sc->dc_ioh = ioh;
/* map Image DMA Controller registers */
- err = bus_space_map(iot, IPU_IDMAC_BASE, IPU_IDMAC_SIZE, 0, &ioh);
+ err = bus_space_map(iot, IPU_IDMAC_BASE(base), IPU_IDMAC_SIZE, 0,
+ &ioh);
if (err)
goto fail_retarn_idmac;
sc->idmac_ioh = ioh;
/* map CPMEM registers */
- err = bus_space_map(iot, IPU_CPMEM_BASE, IPU_CPMEM_SIZE, 0, &ioh);
+ err = bus_space_map(iot, IPU_CPMEM_BASE(base), IPU_CPMEM_SIZE, 0,
+ &ioh);
if (err)
goto fail_retarn_cpmem;
sc->cpmem_ioh = ioh;
/* map DCTEMPL registers */
- err = bus_space_map(iot, IPU_DCTMPL_BASE, IPU_DCTMPL_SIZE, 0, &ioh);
+ err = bus_space_map(iot, IPU_DCTMPL_BASE(base), IPU_DCTMPL_SIZE, 0,
+ &ioh);
if (err)
goto fail_retarn_dctmpl;
sc->dctmpl_ioh = ioh;