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authorAndrew Turner <andrew@FreeBSD.org>2021-05-02 07:43:34 +0000
committerAndrew Turner <andrew@FreeBSD.org>2021-05-02 07:43:34 +0000
commit2420f6aed9e355ff65377152ba977b3a5ac441d1 (patch)
treee31aeed6036ab86fb4df95d0f5f9a0818020f611 /sys/arm64/arm64/mp_machdep.c
parentfe3822497726ab84a1e3753be41e43e4d51aab0b (diff)
downloadsrc-2420f6aed9e355ff65377152ba977b3a5ac441d1.tar.gz
src-2420f6aed9e355ff65377152ba977b3a5ac441d1.zip
Enable IPIs on CPU 0 on arm and arm64
Not all interrupt controllers enable IPIs by default as the Arm GIC specs make it an implementation defined option. As at least two hypervisors have also previously masked the IPIs on boot. As we already enable these IPIs on the non-boot CPUs it is expected this is a safe operation. Differential Revision: https://reviews.freebsd.org/D26975
Diffstat (limited to 'sys/arm64/arm64/mp_machdep.c')
-rw-r--r--sys/arm64/arm64/mp_machdep.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/sys/arm64/arm64/mp_machdep.c b/sys/arm64/arm64/mp_machdep.c
index 8d5d82879571..3b1a8cc89cab 100644
--- a/sys/arm64/arm64/mp_machdep.c
+++ b/sys/arm64/arm64/mp_machdep.c
@@ -364,6 +364,8 @@ intr_pic_ipi_setup(u_int ipi, const char *name, intr_ipi_handler_t *hand,
ii->ii_send_arg = isrc;
strlcpy(ii->ii_name, name, INTR_IPI_NAMELEN);
ii->ii_count = intr_ipi_setup_counters(name);
+
+ PIC_ENABLE_INTR(intr_irq_root_dev, isrc);
}
static void