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authorAndrew Turner <andrew@FreeBSD.org>2017-10-02 14:22:35 +0000
committerAndrew Turner <andrew@FreeBSD.org>2017-10-02 14:22:35 +0000
commit5cf1f313c42465fab211ec7b8beecb47541e5326 (patch)
treee0c44e2a367ffb096c60359fdc9bb43f8e5b62bb /sys/arm64/arm64/mp_machdep.c
parentf78bd12d6dd612d76f9019fb5f94e614f78a7e7e (diff)
downloadsrc-5cf1f313c42465fab211ec7b8beecb47541e5326.tar.gz
src-5cf1f313c42465fab211ec7b8beecb47541e5326.zip
Add a memory barrier to ensure the atomic write is visible to the other
CPUs before waking them up. Sponsored by: DARPA, AFRL
Notes
Notes: svn path=/head/; revision=324207
Diffstat (limited to 'sys/arm64/arm64/mp_machdep.c')
-rw-r--r--sys/arm64/arm64/mp_machdep.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/sys/arm64/arm64/mp_machdep.c b/sys/arm64/arm64/mp_machdep.c
index 99c0a745eaaf..2b2d7f8fbe2c 100644
--- a/sys/arm64/arm64/mp_machdep.c
+++ b/sys/arm64/arm64/mp_machdep.c
@@ -236,7 +236,10 @@ release_aps(void *dummy __unused)
atomic_store_rel_int(&aps_ready, 1);
/* Wake up the other CPUs */
- __asm __volatile("sev");
+ __asm __volatile(
+ "dsb ishst \n"
+ "sev \n"
+ ::: "memory");
printf("Release APs\n");