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authorMateusz Guzik <mjg@FreeBSD.org>2020-09-01 21:18:06 +0000
committerMateusz Guzik <mjg@FreeBSD.org>2020-09-01 21:18:06 +0000
commit50cedfede3d21824ec6023324b3ad41a435e1815 (patch)
tree28defb08b0557b3214d2f1f454dc45788d823488 /sys/arm64/rockchip/rk_pcie.c
parent654548838bebbda54247e122f932b01c3d5c51b3 (diff)
downloadsrc-50cedfede3d21824ec6023324b3ad41a435e1815.tar.gz
src-50cedfede3d21824ec6023324b3ad41a435e1815.zip
arm64: clean up empty lines in .c and .h files
Notes
Notes: svn path=/head/; revision=365069
Diffstat (limited to 'sys/arm64/rockchip/rk_pcie.c')
-rw-r--r--sys/arm64/rockchip/rk_pcie.c9
1 files changed, 0 insertions, 9 deletions
diff --git a/sys/arm64/rockchip/rk_pcie.c b/sys/arm64/rockchip/rk_pcie.c
index a92766747d90..9c1e6b04d8e2 100644
--- a/sys/arm64/rockchip/rk_pcie.c
+++ b/sys/arm64/rockchip/rk_pcie.c
@@ -203,7 +203,6 @@ struct rk_pcie_softc {
phandle_t node;
struct mtx mtx;
-
struct ofw_pci_range mem_range;
struct ofw_pci_range pref_mem_range;
struct ofw_pci_range io_range;
@@ -245,7 +244,6 @@ static struct ofw_compat_data compat_data[] = {
{NULL, 0},
};
-
static uint32_t
rk_pcie_local_cfg_read(struct rk_pcie_softc *sc, bool priv, u_int reg,
int bytes)
@@ -305,7 +303,6 @@ rk_pcie_local_cfg_write(struct rk_pcie_softc *sc, bool priv, u_int reg,
}
}
-
static bool
rk_pcie_check_dev(struct rk_pcie_softc *sc, u_int bus, u_int slot, u_int func,
u_int reg)
@@ -334,7 +331,6 @@ rk_pcie_check_dev(struct rk_pcie_softc *sc, u_int bus, u_int slot, u_int func,
return (true);
}
-
static void
rk_pcie_map_out_atu(struct rk_pcie_softc *sc, int idx, int type,
int num_bits, uint64_t pa)
@@ -342,7 +338,6 @@ rk_pcie_map_out_atu(struct rk_pcie_softc *sc, int idx, int type,
uint32_t addr0;
uint64_t max_size;
-
/* Check HW constrains */
max_size = idx == 0 ? ATU_OB_REGION_0_SIZE: ATU_OB_REGION_SIZE;
KASSERT(idx < ATU_OB_REGIONS, ("Invalid region index: %d\n", idx));
@@ -1027,7 +1022,6 @@ rk_pcie_setup_sw(struct rk_pcie_softc *sc)
pcib_bridge_init(sc->dev);
-
/* Setup config registers */
APB_WR4(sc, PCIE_CORE_CONFIG_VENDOR, 0x1D87); /* Rockchip vendor ID*/
PRIV_CFG_WR1(sc, PCIR_CLASS, PCIC_BRIDGE);
@@ -1137,7 +1131,6 @@ rk_pcie_legacy_irq(void *arg)
return (FILTER_STRAY);
}
-
static bus_dma_tag_t
rk_pcie_get_dma_tag(device_t dev, device_t child)
{
@@ -1147,7 +1140,6 @@ rk_pcie_get_dma_tag(device_t dev, device_t child)
return (sc->dmat);
}
-
static int
rk_pcie_probe(device_t dev)
{
@@ -1370,7 +1362,6 @@ out:
return (rv);
}
-
static device_method_t rk_pcie_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, rk_pcie_probe),