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authorConrad Meyer <cem@FreeBSD.org>2015-10-24 23:46:32 +0000
committerConrad Meyer <cem@FreeBSD.org>2015-10-24 23:46:32 +0000
commitcea5b880c3c01ef13b42d79081602c7c0ffa1f59 (patch)
treed14aef530f33cdfb2a2a9895bad8c24f67d9eff6 /sys/dev/ioat/ioat_hw.h
parente88e14b9f01d29616ccff4d3bbd84c71657d56f5 (diff)
downloadsrc-cea5b880c3c01ef13b42d79081602c7c0ffa1f59.tar.gz
src-cea5b880c3c01ef13b42d79081602c7c0ffa1f59.zip
ioat: Actually bring the hardware back online after reset
We need to reset the chancmp and chainaddr MMIO registers to bring the device back to a working state. Name the chanerr bits while we're here. Sponsored by: EMC / Isilon Storage Division
Notes
Notes: svn path=/head/; revision=289912
Diffstat (limited to 'sys/dev/ioat/ioat_hw.h')
-rw-r--r--sys/dev/ioat/ioat_hw.h29
1 files changed, 29 insertions, 0 deletions
diff --git a/sys/dev/ioat/ioat_hw.h b/sys/dev/ioat/ioat_hw.h
index f248a18fc842..d2bba62a6a20 100644
--- a/sys/dev/ioat/ioat_hw.h
+++ b/sys/dev/ioat/ioat_hw.h
@@ -97,6 +97,35 @@ __FBSDID("$FreeBSD$");
#define IOAT_CHANERR_OFFSET 0xA8
+#define IOAT_CHANERR_XSADDERR (1 << 0)
+#define IOAT_CHANERR_XDADDERR (1 << 1)
+#define IOAT_CHANERR_NDADDERR (1 << 2)
+#define IOAT_CHANERR_DERR (1 << 3)
+#define IOAT_CHANERR_CHADDERR (1 << 4)
+#define IOAT_CHANERR_CCMDERR (1 << 5)
+#define IOAT_CHANERR_CUNCORERR (1 << 6)
+#define IOAT_CHANERR_DUNCORERR (1 << 7)
+#define IOAT_CHANERR_RDERR (1 << 8)
+#define IOAT_CHANERR_WDERR (1 << 9)
+#define IOAT_CHANERR_DCERR (1 << 10)
+#define IOAT_CHANERR_DXSERR (1 << 11)
+#define IOAT_CHANERR_CMPADDERR (1 << 12)
+#define IOAT_CHANERR_INTCFGERR (1 << 13)
+#define IOAT_CHANERR_SEDERR (1 << 14)
+#define IOAT_CHANERR_UNAFFERR (1 << 15)
+#define IOAT_CHANERR_CXPERR (1 << 16)
+/* Reserved. (1 << 17) */
+#define IOAT_CHANERR_DCNTERR (1 << 18)
+#define IOAT_CHANERR_DIFFERR (1 << 19)
+#define IOAT_CHANERR_GTVERR (1 << 20)
+#define IOAT_CHANERR_ATVERR (1 << 21)
+#define IOAT_CHANERR_RTVERR (1 << 22)
+#define IOAT_CHANERR_BBERR (1 << 23)
+#define IOAT_CHANERR_RDIFFERR (1 << 24)
+#define IOAT_CHANERR_RGTVERR (1 << 25)
+#define IOAT_CHANERR_RATVERR (1 << 26)
+#define IOAT_CHANERR_RRTVERR (1 << 27)
+
#define IOAT_CFG_CHANERR_INT_OFFSET 0x180
#define IOAT_CFG_CHANERRMASK_INT_OFFSET 0x184