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authorAndrew Rybchenko <arybchik@FreeBSD.org>2016-01-12 15:28:59 +0000
committerAndrew Rybchenko <arybchik@FreeBSD.org>2016-01-12 15:28:59 +0000
commit0c24a07e20875fba412e4a4937efbfb3dfa8fa57 (patch)
tree4042a855cc4d7159ed05146bad88850d8204e84e /sys/dev/sfxge/common/efx_intr.c
parentf5969609b9417dbf50b02057d73d3561dfac6dbb (diff)
downloadsrc-0c24a07e20875fba412e4a4937efbfb3dfa8fa57.tar.gz
src-0c24a07e20875fba412e4a4937efbfb3dfa8fa57.zip
sfxge: fix interrupt handling for Medford
Submitted by: Andy Moreton <amoreton at solarflare.com> Reviewed by: gnn Sponsored by: Solarflare Communications, Inc. MFC after: 2 days Differential Revision: https://reviews.freebsd.org/D4886
Notes
Notes: svn path=/head/; revision=293769
Diffstat (limited to 'sys/dev/sfxge/common/efx_intr.c')
-rw-r--r--sys/dev/sfxge/common/efx_intr.c125
1 files changed, 77 insertions, 48 deletions
diff --git a/sys/dev/sfxge/common/efx_intr.c b/sys/dev/sfxge/common/efx_intr.c
index b0eebe877d25..92eb7352d219 100644
--- a/sys/dev/sfxge/common/efx_intr.c
+++ b/sys/dev/sfxge/common/efx_intr.c
@@ -67,15 +67,27 @@ static void
falconsiena_intr_fini(
__in efx_nic_t *enp);
+static void
+falconsiena_intr_status_line(
+ __in efx_nic_t *enp,
+ __out boolean_t *fatalp,
+ __out uint32_t *qmaskp);
-static __checkReturn boolean_t
-falconsiena_intr_check_fatal(
- __in efx_nic_t *enp);
+static void
+falconsiena_intr_status_message(
+ __in efx_nic_t *enp,
+ __in unsigned int message,
+ __out boolean_t *fatalp);
static void
falconsiena_intr_fatal(
__in efx_nic_t *enp);
+static __checkReturn boolean_t
+falconsiena_intr_check_fatal(
+ __in efx_nic_t *enp);
+
+
#endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */
@@ -86,6 +98,9 @@ static efx_intr_ops_t __efx_intr_falcon_ops = {
falconsiena_intr_disable, /* eio_disable */
falconsiena_intr_disable_unlocked, /* eio_disable_unlocked */
falconsiena_intr_trigger, /* eio_trigger */
+ falconsiena_intr_status_line, /* eio_status_line */
+ falconsiena_intr_status_message, /* eio_status_message */
+ falconsiena_intr_fatal, /* eio_fatal */
falconsiena_intr_fini, /* eio_fini */
};
#endif /* EFSYS_OPT_FALCON */
@@ -97,6 +112,9 @@ static efx_intr_ops_t __efx_intr_siena_ops = {
falconsiena_intr_disable, /* eio_disable */
falconsiena_intr_disable_unlocked, /* eio_disable_unlocked */
falconsiena_intr_trigger, /* eio_trigger */
+ falconsiena_intr_status_line, /* eio_status_line */
+ falconsiena_intr_status_message, /* eio_status_message */
+ falconsiena_intr_fatal, /* eio_fatal */
falconsiena_intr_fini, /* eio_fini */
};
#endif /* EFSYS_OPT_SIENA */
@@ -108,6 +126,9 @@ static efx_intr_ops_t __efx_intr_ef10_ops = {
ef10_intr_disable, /* eio_disable */
ef10_intr_disable_unlocked, /* eio_disable_unlocked */
ef10_intr_trigger, /* eio_trigger */
+ ef10_intr_status_line, /* eio_status_line */
+ ef10_intr_status_message, /* eio_status_message */
+ ef10_intr_fatal, /* eio_fatal */
ef10_intr_fini, /* eio_fini */
};
#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
@@ -261,35 +282,12 @@ efx_intr_status_line(
__out uint32_t *qmaskp)
{
efx_intr_t *eip = &(enp->en_intr);
- efx_dword_t dword;
+ efx_intr_ops_t *eiop = eip->ei_eiop;
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
- /* Ensure Huntington and Falcon/Siena ISR at same location */
- EFX_STATIC_ASSERT(FR_BZ_INT_ISR0_REG_OFST ==
- ER_DZ_BIU_INT_ISR_REG_OFST);
-
- /*
- * Read the queue mask and implicitly acknowledge the
- * interrupt.
- */
- EFX_BAR_READD(enp, FR_BZ_INT_ISR0_REG, &dword, B_FALSE);
- *qmaskp = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
-
- EFSYS_PROBE1(qmask, uint32_t, *qmaskp);
-
-#if EFSYS_OPT_HUNTINGTON
- if (enp->en_family == EFX_FAMILY_HUNTINGTON) {
- /* Huntington reports fatal errors via events */
- *fatalp = B_FALSE;
- return;
- }
-#endif
- if (*qmaskp & (1U << eip->ei_level))
- *fatalp = falconsiena_intr_check_fatal(enp);
- else
- *fatalp = B_FALSE;
+ eiop->eio_status_line(enp, fatalp, qmaskp);
}
void
@@ -299,39 +297,25 @@ efx_intr_status_message(
__out boolean_t *fatalp)
{
efx_intr_t *eip = &(enp->en_intr);
+ efx_intr_ops_t *eiop = eip->ei_eiop;
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
-#if EFSYS_OPT_HUNTINGTON
- if (enp->en_family == EFX_FAMILY_HUNTINGTON) {
- /* Huntington reports fatal errors via events */
- *fatalp = B_FALSE;
- return;
- }
-#endif
- if (message == eip->ei_level)
- *fatalp = falconsiena_intr_check_fatal(enp);
- else
- *fatalp = B_FALSE;
+ eiop->eio_status_message(enp, message, fatalp);
}
void
efx_intr_fatal(
__in efx_nic_t *enp)
{
+ efx_intr_t *eip = &(enp->en_intr);
+ efx_intr_ops_t *eiop = eip->ei_eiop;
+
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
-#if EFSYS_OPT_HUNTINGTON
- if (enp->en_family == EFX_FAMILY_HUNTINGTON) {
- /* Huntington reports fatal errors via events */
- return;
- }
-#endif
-#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA
- falconsiena_intr_fatal(enp);
-#endif
+ eiop->eio_fatal(enp);
}
@@ -514,6 +498,51 @@ falconsiena_intr_check_fatal(
return (B_FALSE);
}
+static void
+falconsiena_intr_status_line(
+ __in efx_nic_t *enp,
+ __out boolean_t *fatalp,
+ __out uint32_t *qmaskp)
+{
+ efx_intr_t *eip = &(enp->en_intr);
+ efx_dword_t dword;
+
+ EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
+ EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
+
+ /*
+ * Read the queue mask and implicitly acknowledge the
+ * interrupt.
+ */
+ EFX_BAR_READD(enp, FR_BZ_INT_ISR0_REG, &dword, B_FALSE);
+ *qmaskp = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
+
+ EFSYS_PROBE1(qmask, uint32_t, *qmaskp);
+
+ if (*qmaskp & (1U << eip->ei_level))
+ *fatalp = falconsiena_intr_check_fatal(enp);
+ else
+ *fatalp = B_FALSE;
+}
+
+static void
+falconsiena_intr_status_message(
+ __in efx_nic_t *enp,
+ __in unsigned int message,
+ __out boolean_t *fatalp)
+{
+ efx_intr_t *eip = &(enp->en_intr);
+
+ EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
+ EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
+
+ if (message == eip->ei_level)
+ *fatalp = falconsiena_intr_check_fatal(enp);
+ else
+ *fatalp = B_FALSE;
+}
+
+
static void
falconsiena_intr_fatal(
__in efx_nic_t *enp)