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authorJayachandran C. <jchandra@FreeBSD.org>2010-09-09 17:45:48 +0000
committerJayachandran C. <jchandra@FreeBSD.org>2010-09-09 17:45:48 +0000
commit2e4e56742ee27fc31553283cf143372eb01efb7d (patch)
tree37e0ff1e725c5798d2fd5f59767cd29cdb78881f /sys/mips/rmi/xlr_machdep.c
parent01f6f5fcd47d0d492451a0291e19b1e656329baa (diff)
downloadsrc-2e4e56742ee27fc31553283cf143372eb01efb7d.tar.gz
src-2e4e56742ee27fc31553283cf143372eb01efb7d.zip
Clean up and update sys/mips/rmi/rmi_mips_exts.h
- Provide 64 bit implementations for some macros. On n64 and n32, don't split 64 bit values. - No need for 32 bit ops for control registers. - Fix few bugs (write control reg, write_c0_register64). - Re-write EIRR/EIMR/CPUID operations using read_c0_registerXX, no need of inline assembly. - rename control reg access functions to avoid phnx, update callers. - stlye/whitespace fixes.
Notes
Notes: svn path=/head/; revision=212366
Diffstat (limited to 'sys/mips/rmi/xlr_machdep.c')
-rw-r--r--sys/mips/rmi/xlr_machdep.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/sys/mips/rmi/xlr_machdep.c b/sys/mips/rmi/xlr_machdep.c
index bc3dd77e3d70..87285553e518 100644
--- a/sys/mips/rmi/xlr_machdep.c
+++ b/sys/mips/rmi/xlr_machdep.c
@@ -105,7 +105,7 @@ int xlr_hwtid_to_cpuid[MAXCPU];
static void
xlr_setup_mmu_split(void)
{
- int mmu_setup;
+ uint64_t mmu_setup;
int val = 0;
if (xlr_threads_per_core == 4 && xlr_shtlb_enabled == 0)
@@ -120,7 +120,7 @@ xlr_setup_mmu_split(void)
val = 3; break;
}
- mmu_setup = read_32bit_phnx_ctrl_reg(4, 0);
+ mmu_setup = read_xlr_ctrl_register(4, 0);
mmu_setup = mmu_setup & ~0x06;
mmu_setup |= (val << 1);
@@ -128,7 +128,7 @@ xlr_setup_mmu_split(void)
if (xlr_shtlb_enabled)
mmu_setup |= 0x01;
- write_32bit_phnx_ctrl_reg(4, 0, mmu_setup);
+ write_xlr_ctrl_register(4, 0, mmu_setup);
}
static void