path: root/sys/sys/sbuf.h
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authorAndriy Gapon <avg@FreeBSD.org>2017-02-28 18:48:12 +0000
committerAndriy Gapon <avg@FreeBSD.org>2017-02-28 18:48:12 +0000
commitbc1e6499245f93ac61532a66e21a691ad3059511 (patch)
tree3975a1ec44d16c978eb5bb101174f1b381e53bd7 /sys/sys/sbuf.h
parent388f3ce6c3fb0c2eeeeebe1e0af6d72f840de7fc (diff)
Local APIC: add support for extended LVT entries found in AMD processors
The extended LVT entries can be used to configure interrupt delivery for various events that are internal to a processor and can use this feature. All current processors that support the feature have four of such entries. The entries are all masked upon the processor reset, but it's possible that firmware may use some of them. BIOS and Kernel Developer's Guides for some processor models do not assign any particular names to the extended LVTs, while other BKDGs provide names and suggested usage for them. However, there is no fixed mapping between the LVTs and the processor events in any processor model that supports the feature. Any entry can be assigned to any event. The assignment is done by programming an offset of an entry into configuration bits corresponding to an event. This change does not expose the flexibility that the feature offers. The change adds just a single method to configure a hardcoded extended LVT entry to deliver APIC_CMC_INT. The method is designed to be used with Machine Check Error Thresholding mechanism on supported processor models. For references please see BKDGs for families 10h - 16h and specifically descriptions of APIC30, APIC400, APIC[530:500] registers. For a description of the Error Thresholding mechanism see, for example, BKDG for family 10h, section http://developer.amd.com/resources/developer-guides-manuals/ Thanks to jhb and kib for their suggestions. Reviewed by: kib Discussed with: jhb MFC after: 5 weeks Relnotes: maybe Differential Revision: https://reviews.freebsd.org/D9612
Notes: svn path=/head/; revision=314398
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