|author||Marius Strobl <marius@FreeBSD.org>||2011-07-02 12:56:03 +0000|
|committer||Marius Strobl <marius@FreeBSD.org>||2011-07-02 12:56:03 +0000|
UltraSPARC-IV CPUs seem to be affected by a not publicly documented
erratum causing them to trigger stray vector interrupts accompanied by a state in which they even fault on locked TLB entries. Just retrying the instruction in that case gets the CPU back on track though. OpenSolaris also just ignores a certain number of stray vector interrupts. While at it, implement the stray vector interrupt handling for SPARC64-VI which use these for indicating uncorrectable errors in interrupt packets.
Notes: svn path=/head/; revision=223721
Diffstat (limited to 'sys/sys/ttydevsw.h')
0 files changed, 0 insertions, 0 deletions