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authorMichal Meloun <mmel@FreeBSD.org>2021-02-09 10:36:36 +0000
committerMichal Meloun <mmel@FreeBSD.org>2021-02-09 11:53:09 +0000
commitec090f4a67654fa541e6d97fd5f74d3f66c1c0d0 (patch)
tree0a72f385dfe0ac2346951c546e4e959035da0f7a /sys
parenta26f7358583174f2fe0df3e979f7b8b02069278c (diff)
downloadsrc-ec090f4a67654fa541e6d97fd5f74d3f66c1c0d0.tar.gz
src-ec090f4a67654fa541e6d97fd5f74d3f66c1c0d0.zip
arm32: Align arguments of sync_icache() syscall to cacheline size.
Otherwise, we may miss synchronization of the last cacheline. MFC after: 3 days
Diffstat (limited to 'sys')
-rw-r--r--sys/arm/arm/sys_machdep.c9
1 files changed, 3 insertions, 6 deletions
diff --git a/sys/arm/arm/sys_machdep.c b/sys/arm/arm/sys_machdep.c
index d33ac75ad73b..fc424d0fad39 100644
--- a/sys/arm/arm/sys_machdep.c
+++ b/sys/arm/arm/sys_machdep.c
@@ -68,12 +68,9 @@ sync_icache(uintptr_t addr, size_t len)
size_t size;
vm_offset_t rv;
- /*
- * Align starting address to even number because value of "1"
- * is used as return value for success.
- */
- len += addr & 1;
- addr &= ~1;
+ /* Align starting address to cacheline size */
+ len += addr & cpuinfo.dcache_line_mask;
+ addr &= ~cpuinfo.dcache_line_mask;
/* Break whole range to pages. */
do {