diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2018-08-02 17:32:43 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2018-08-02 17:32:43 +0000 |
| commit | b7eb8e35e481a74962664b63dfb09483b200209a (patch) | |
| tree | 1937fb4a348458ce2d02ade03ac3bb0aa18d2fcd /test/CodeGen/AArch64/machine-outliner-regsave.mir | |
| parent | eb11fae6d08f479c0799db45860a98af528fa6e7 (diff) | |
| download | src-b7eb8e35e481a74962664b63dfb09483b200209a.tar.gz src-b7eb8e35e481a74962664b63dfb09483b200209a.zip | |
Vendor import of llvm trunk r338536:vendor/llvm/llvm-trunk-r338536
Notes
Notes:
svn path=/vendor/llvm/dist/; revision=337137
svn path=/vendor/llvm/llvm-trunk-r338536/; revision=337138; tag=vendor/llvm/llvm-trunk-r338536
Diffstat (limited to 'test/CodeGen/AArch64/machine-outliner-regsave.mir')
| -rw-r--r-- | test/CodeGen/AArch64/machine-outliner-regsave.mir | 112 |
1 files changed, 112 insertions, 0 deletions
diff --git a/test/CodeGen/AArch64/machine-outliner-regsave.mir b/test/CodeGen/AArch64/machine-outliner-regsave.mir new file mode 100644 index 000000000000..6d00bd39cde7 --- /dev/null +++ b/test/CodeGen/AArch64/machine-outliner-regsave.mir @@ -0,0 +1,112 @@ +# RUN: llc -mtriple=aarch64-apple-darwin -run-pass=prologepilog \ +# RUN: -run-pass=machine-outliner -verify-machineinstrs %s -o - | FileCheck %s +# Check that we save LR to a callee-saved register when possible. +# foo() should use a callee-saved register. However, bar() should not. +--- | + + define void @foo() #0 { + ret void + } + + define void @bar() #0 { + ret void + } + + attributes #0 = { minsize noinline noredzone "no-frame-pointer-elim"="true" } +... +--- +# Make sure that when we outline and a register is available, we +# use it to save + restore LR instead of SP. +# CHECK: name: foo +# CHECK-DAG: bb.0 +# CHECK-DAG: $x[[REG:[0-9]+]] = ORRXrs $xzr, $lr, 0 +# CHECK-NEXT: BL +# CHECK-NEXT: $lr = ORRXrs $xzr, $x[[REG]], 0 +# CHECK-DAG: bb.1 +# CHECK-DAG: $x[[REG]] = ORRXrs $xzr, $lr, 0 +# CHECK-NEXT: BL +# CHECK-NEXT: $lr = ORRXrs $xzr, $x[[REG]], 0 +# CHECK-DAG: bb.2 +# CHECK-DAG: $x[[REG]] = ORRXrs $xzr, $lr, 0 +# CHECK-NEXT: BL +# CHECK-NEXT: $lr = ORRXrs $xzr, $x[[REG]], 0 +name: foo +tracksRegLiveness: true +fixedStack: +body: | + bb.0: + liveins: $lr, $w9 + $x25 = ORRXri $xzr, 1 + $w9 = ORRWri $wzr, 1 + $w9 = ORRWri $wzr, 1 + $w9 = ORRWri $wzr, 1 + $w9 = ORRWri $wzr, 1 + $w9 = ORRWri $wzr, 1 + $w9 = ORRWri $wzr, 2 + bb.1: + liveins: $lr, $w9 + $w9 = ORRWri $wzr, 1 + $w9 = ORRWri $wzr, 1 + $w9 = ORRWri $wzr, 1 + $w9 = ORRWri $wzr, 1 + $w9 = ORRWri $wzr, 1 + $w9 = ORRWri $wzr, 2 + bb.2: + liveins: $lr, $w9 + $w9 = ORRWri $wzr, 1 + $w9 = ORRWri $wzr, 1 + $w9 = ORRWri $wzr, 1 + $w9 = ORRWri $wzr, 1 + $w9 = ORRWri $wzr, 1 + $w9 = ORRWri $wzr, 2 + RET undef $lr + +... +--- +# Convoluted case that shows that we'll still save to the stack when there are +# no approprate registers available. +# The live-in lists do not contain x16 or x17 since including them would cause +# nothing to be outlined. +# They also deliberately don't contain x18 to show that on Darwin we won't store +# to that. +# CHECK-LABEL: name: bar +# CHECK: early-clobber $sp = STRXpre $lr, $sp, -16 +# CHECK-NEXT: BL +# CHECK-DAG: early-clobber $sp, $lr = LDRXpost $sp, 16 +# CHECK: early-clobber $sp = STRXpre $lr, $sp, -16 +# CHECK-NEXT: BL +# CHECK-DAG: early-clobber $sp, $lr = LDRXpost $sp, 16 +# CHECK: early-clobber $sp = STRXpre $lr, $sp, -16 +# CHECK-NEXT: BL +# CHECK-NEXT: early-clobber $sp, $lr = LDRXpost $sp, 16 +name: bar +tracksRegLiveness: true +body: | + bb.0: + liveins: $lr, $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x19, $x20, $x21, $x22, $x23, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28 + $w10 = ORRWri $wzr, 1 + $w10 = ORRWri $wzr, 1 + $w10 = ORRWri $wzr, 1 + $w10 = ORRWri $wzr, 1 + $w10 = ORRWri $wzr, 1 + $w12 = ORRWri $wzr, 2 + bb.1: + liveins: $lr, $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x19, $x20, $x21, $x22, $x23, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28 + $w10 = ORRWri $wzr, 1 + $w10 = ORRWri $wzr, 1 + $w10 = ORRWri $wzr, 1 + $w10 = ORRWri $wzr, 1 + $w10 = ORRWri $wzr, 1 + $w12 = ORRWri $wzr, 2 + bb.2: + liveins: $lr, $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x19, $x20, $x21, $x22, $x23, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28 + $w10 = ORRWri $wzr, 1 + $w10 = ORRWri $wzr, 1 + $w10 = ORRWri $wzr, 1 + $w10 = ORRWri $wzr, 1 + $w10 = ORRWri $wzr, 1 + $w12 = ORRWri $wzr, 2 + bb.3: + liveins: $lr, $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10, $x11, $x12, $x13, $x14, $x15, $x19, $x20, $x21, $x22, $x23, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28 + RET undef $lr + |