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author | Dimitry Andric <dim@FreeBSD.org> | 2018-08-02 17:32:43 +0000 |
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committer | Dimitry Andric <dim@FreeBSD.org> | 2018-08-02 17:32:43 +0000 |
commit | b7eb8e35e481a74962664b63dfb09483b200209a (patch) | |
tree | 1937fb4a348458ce2d02ade03ac3bb0aa18d2fcd /test/CodeGen/AMDGPU/llvm.amdgcn.sdot8.ll | |
parent | eb11fae6d08f479c0799db45860a98af528fa6e7 (diff) | |
download | src-b7eb8e35e481a74962664b63dfb09483b200209a.tar.gz src-b7eb8e35e481a74962664b63dfb09483b200209a.zip |
Vendor import of llvm trunk r338536:vendor/llvm/llvm-trunk-r338536
Notes
Notes:
svn path=/vendor/llvm/dist/; revision=337137
svn path=/vendor/llvm/llvm-trunk-r338536/; revision=337138; tag=vendor/llvm/llvm-trunk-r338536
Diffstat (limited to 'test/CodeGen/AMDGPU/llvm.amdgcn.sdot8.ll')
-rw-r--r-- | test/CodeGen/AMDGPU/llvm.amdgcn.sdot8.ll | 28 |
1 files changed, 23 insertions, 5 deletions
diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.sdot8.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.sdot8.ll index e2466eae5394..456421c4984a 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.sdot8.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.sdot8.ll @@ -1,10 +1,10 @@ ; RUN: llc -march=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck %s --check-prefix=GCN --check-prefix=GFX906 -declare i32 @llvm.amdgcn.sdot8(i32 %a, i32 %b, i32 %c) +declare i32 @llvm.amdgcn.sdot8(i32 %a, i32 %b, i32 %c, i1 %clamp) -; GCN-LABEL: {{^}}test_llvm_amdgcn_sdot8 -; GFX906: v_dot8_i32_i4 -define amdgpu_kernel void @test_llvm_amdgcn_sdot8( +; GCN-LABEL: {{^}}test_llvm_amdgcn_sdot8_clamp +; GFX906: v_dot8_i32_i4 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} clamp{{$}} +define amdgpu_kernel void @test_llvm_amdgcn_sdot8_clamp( i32 addrspace(1)* %r, <8 x i4> addrspace(1)* %a, <8 x i4> addrspace(1)* %b, @@ -15,7 +15,25 @@ entry: %a.val.cast = bitcast <8 x i4> %a.val to i32 %b.val.cast = bitcast <8 x i4> %b.val to i32 %c.val = load i32, i32 addrspace(1)* %c - %r.val = call i32 @llvm.amdgcn.sdot8(i32 %a.val.cast, i32 %b.val.cast, i32 %c.val) + %r.val = call i32 @llvm.amdgcn.sdot8(i32 %a.val.cast, i32 %b.val.cast, i32 %c.val, i1 1) + store i32 %r.val, i32 addrspace(1)* %r + ret void +} + +; GCN-LABEL: {{^}}test_llvm_amdgcn_sdot8_no_clamp +; GFX906: v_dot8_i32_i4 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}{{$}} +define amdgpu_kernel void @test_llvm_amdgcn_sdot8_no_clamp( + i32 addrspace(1)* %r, + <8 x i4> addrspace(1)* %a, + <8 x i4> addrspace(1)* %b, + i32 addrspace(1)* %c) { +entry: + %a.val = load <8 x i4>, <8 x i4> addrspace(1)* %a + %b.val = load <8 x i4>, <8 x i4> addrspace(1)* %b + %a.val.cast = bitcast <8 x i4> %a.val to i32 + %b.val.cast = bitcast <8 x i4> %b.val to i32 + %c.val = load i32, i32 addrspace(1)* %c + %r.val = call i32 @llvm.amdgcn.sdot8(i32 %a.val.cast, i32 %b.val.cast, i32 %c.val, i1 0) store i32 %r.val, i32 addrspace(1)* %r ret void } |