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authorDimitry Andric <dim@FreeBSD.org>2011-07-17 15:36:56 +0000
committerDimitry Andric <dim@FreeBSD.org>2011-07-17 15:36:56 +0000
commit411bd29eea3c360d5b48a18a17b5e87f5671af0e (patch)
treec8086addb211fa670a9d2b1038d8c2e453229755 /test/CodeGen/Mips
parent56fe8f14099930935e3870e3e823c322a85c1c89 (diff)
downloadsrc-411bd29eea3c360d5b48a18a17b5e87f5671af0e.tar.gz
src-411bd29eea3c360d5b48a18a17b5e87f5671af0e.zip
Vendor import of llvm trunk r135360:vendor/llvm/llvm-r135360
Notes
Notes: svn path=/vendor/llvm/dist/; revision=224133 svn path=/vendor/llvm/llvm-r135360/; revision=224134; tag=vendor/llvm/llvm-r135360
Diffstat (limited to 'test/CodeGen/Mips')
-rw-r--r--test/CodeGen/Mips/2008-07-15-SmallSection.ll2
-rw-r--r--test/CodeGen/Mips/2008-07-16-SignExtInReg.ll4
-rw-r--r--test/CodeGen/Mips/alloca.ll85
-rw-r--r--test/CodeGen/Mips/i64arg.ll4
-rw-r--r--test/CodeGen/Mips/inlineasmmemop.ll23
-rw-r--r--test/CodeGen/Mips/internalfunc.ll6
-rw-r--r--test/CodeGen/Mips/largeimmprinting.ll2
-rw-r--r--test/CodeGen/Mips/o32_cc_byval.ll2
-rw-r--r--test/CodeGen/Mips/private.ll2
9 files changed, 109 insertions, 21 deletions
diff --git a/test/CodeGen/Mips/2008-07-15-SmallSection.ll b/test/CodeGen/Mips/2008-07-15-SmallSection.ll
index 91efd68622a2..4795e478f761 100644
--- a/test/CodeGen/Mips/2008-07-15-SmallSection.ll
+++ b/test/CodeGen/Mips/2008-07-15-SmallSection.ll
@@ -7,7 +7,7 @@
; RUN: not grep {sbss} %t1
; RUN: not grep {gp_rel} %t1
; RUN: grep {\%hi} %t1 | count 2
-; RUN: grep {\%lo} %t1 | count 2
+; RUN: grep {\%lo} %t1 | count 3
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "mipsallegrexel-unknown-psp-elf"
diff --git a/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll b/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll
index 41ae5dd65f51..855194aa077e 100644
--- a/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll
+++ b/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll
@@ -5,13 +5,13 @@
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "mipsallegrexel-unknown-psp-elf"
-define i8 @A(i8 %e.0, i8 signext %sum) signext nounwind {
+define signext i8 @A(i8 %e.0, i8 signext %sum) nounwind {
entry:
add i8 %sum, %e.0 ; <i8>:0 [#uses=1]
ret i8 %0
}
-define i16 @B(i16 %e.0, i16 signext %sum) signext nounwind {
+define signext i16 @B(i16 %e.0, i16 signext %sum) nounwind {
entry:
add i16 %sum, %e.0 ; <i16>:0 [#uses=1]
ret i16 %0
diff --git a/test/CodeGen/Mips/alloca.ll b/test/CodeGen/Mips/alloca.ll
index 50eeecf991fb..fb4f56cb5720 100644
--- a/test/CodeGen/Mips/alloca.ll
+++ b/test/CodeGen/Mips/alloca.ll
@@ -4,15 +4,13 @@ define i32 @twoalloca(i32 %size) nounwind {
entry:
; CHECK: subu $[[T0:[0-9]+]], $sp, $[[SZ:[0-9]+]]
; CHECK: addu $sp, $zero, $[[T0]]
-; CHECK: addu $[[SP1:[0-9]+]], $zero, $sp
-; CHECK: subu $[[T1:[0-9]+]], $sp, $[[SZ]]
-; CHECK: addu $sp, $zero, $[[T1]]
-; CHECK: addu $[[SP2:[0-9]+]], $zero, $sp
-; CHECK: lw $25, %call16(foo)($gp)
-; CHECK: addiu $4, $[[SP1]], 24
-; CHECK: jalr $25
-; CHECK: lw $25, %call16(foo)($gp)
-; CHECK: addiu $4, $[[SP2]], 24
+; CHECK: addiu $[[T1:[0-9]+]], $sp, [[OFF:[0-9]+]]
+; CHECK: subu $[[T2:[0-9]+]], $sp, $[[SZ]]
+; CHECK: addu $sp, $zero, $[[T2]]
+; CHECK: addiu $[[T3:[0-9]+]], $sp, [[OFF]]
+; CHECK: lw $[[T4:[0-9]+]], %call16(foo)($gp)
+; CHECK: addu $25, $zero, $[[T4]]
+; CHECK: addu $4, $zero, $[[T1]]
; CHECK: jalr $25
%tmp1 = alloca i8, i32 %size, align 4
%add.ptr = getelementptr inbounds i8* %tmp1, i32 5
@@ -29,3 +27,72 @@ declare void @foo2(double, double, i32)
declare i32 @foo(i8*)
+@.str = private unnamed_addr constant [22 x i8] c"%d %d %d %d %d %d %d\0A\00", align 1
+
+define i32 @alloca2(i32 %size) nounwind {
+entry:
+; dynamic allocated stack area and $gp restore slot have the same offsets
+; relative to $sp.
+;
+; CHECK: alloca2
+; CHECK: .cprestore [[OFF:[0-9]+]]
+; CHECK: subu $[[T0:[0-9]+]], $sp, $[[SZ:[0-9]+]]
+; CHECK: addu $sp, $zero, $[[T0]]
+; CHECK: addiu $[[T1:[0-9]+]], $sp, [[OFF]]
+
+ %tmp1 = alloca i8, i32 %size, align 4
+ %0 = bitcast i8* %tmp1 to i32*
+ %cmp = icmp sgt i32 %size, 10
+ br i1 %cmp, label %if.then, label %if.else
+
+if.then: ; preds = %entry
+; CHECK: addiu $4, $[[T1]], 40
+
+ %add.ptr = getelementptr inbounds i8* %tmp1, i32 40
+ %1 = bitcast i8* %add.ptr to i32*
+ call void @foo3(i32* %1) nounwind
+ %arrayidx15.pre = getelementptr inbounds i8* %tmp1, i32 12
+ %.pre = bitcast i8* %arrayidx15.pre to i32*
+ br label %if.end
+
+if.else: ; preds = %entry
+; CHECK: addiu $4, $[[T1]], 12
+
+ %add.ptr5 = getelementptr inbounds i8* %tmp1, i32 12
+ %2 = bitcast i8* %add.ptr5 to i32*
+ call void @foo3(i32* %2) nounwind
+ br label %if.end
+
+if.end: ; preds = %if.else, %if.then
+; CHECK: lw $5, 0($[[T1]])
+; CHECK: lw $25, %call16(printf)
+
+ %.pre-phi = phi i32* [ %2, %if.else ], [ %.pre, %if.then ]
+ %tmp7 = load i32* %0, align 4, !tbaa !0
+ %arrayidx9 = getelementptr inbounds i8* %tmp1, i32 4
+ %3 = bitcast i8* %arrayidx9 to i32*
+ %tmp10 = load i32* %3, align 4, !tbaa !0
+ %arrayidx12 = getelementptr inbounds i8* %tmp1, i32 8
+ %4 = bitcast i8* %arrayidx12 to i32*
+ %tmp13 = load i32* %4, align 4, !tbaa !0
+ %tmp16 = load i32* %.pre-phi, align 4, !tbaa !0
+ %arrayidx18 = getelementptr inbounds i8* %tmp1, i32 16
+ %5 = bitcast i8* %arrayidx18 to i32*
+ %tmp19 = load i32* %5, align 4, !tbaa !0
+ %arrayidx21 = getelementptr inbounds i8* %tmp1, i32 20
+ %6 = bitcast i8* %arrayidx21 to i32*
+ %tmp22 = load i32* %6, align 4, !tbaa !0
+ %arrayidx24 = getelementptr inbounds i8* %tmp1, i32 24
+ %7 = bitcast i8* %arrayidx24 to i32*
+ %tmp25 = load i32* %7, align 4, !tbaa !0
+ %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([22 x i8]* @.str, i32 0, i32 0), i32 %tmp7, i32 %tmp10, i32 %tmp13, i32 %tmp16, i32 %tmp19, i32 %tmp22, i32 %tmp25) nounwind
+ ret i32 0
+}
+
+declare void @foo3(i32*)
+
+declare i32 @printf(i8* nocapture, ...) nounwind
+
+!0 = metadata !{metadata !"int", metadata !1}
+!1 = metadata !{metadata !"omnipotent char", metadata !2}
+!2 = metadata !{metadata !"Simple C/C++ TBAA", null}
diff --git a/test/CodeGen/Mips/i64arg.ll b/test/CodeGen/Mips/i64arg.ll
index 9a30453a51fc..560f2e9b0874 100644
--- a/test/CodeGen/Mips/i64arg.ll
+++ b/test/CodeGen/Mips/i64arg.ll
@@ -10,8 +10,8 @@ entry:
; CHECK: jalr
tail call void @ff1(i32 %i, i64 1085102592623924856) nounwind
; CHECK: lw $25, %call16(ff2)
-; CHECK: lw $[[R2:[0-9]+]], 80($sp)
-; CHECK: lw $[[R3:[0-9]+]], 84($sp)
+; CHECK: lw $[[R2:[0-9]+]], 88($sp)
+; CHECK: lw $[[R3:[0-9]+]], 92($sp)
; CHECK: addu $4, $zero, $[[R2]]
; CHECK: addu $5, $zero, $[[R3]]
; CHECK: jalr $25
diff --git a/test/CodeGen/Mips/inlineasmmemop.ll b/test/CodeGen/Mips/inlineasmmemop.ll
new file mode 100644
index 000000000000..c5658923dcc6
--- /dev/null
+++ b/test/CodeGen/Mips/inlineasmmemop.ll
@@ -0,0 +1,23 @@
+; RUN: llc -march=mipsel -mcpu=4ke < %s | FileCheck %s
+
+@g1 = external global i32
+
+define i32 @f1(i32 %x) nounwind {
+entry:
+; CHECK: addiu $[[T0:[0-9]+]], $sp
+; CHECK: #APP
+; CHECK: sw $4, 0($[[T0]])
+; CHECK: #NO_APP
+; CHECK: lw $[[T1:[0-9]+]], %got(g1)($gp)
+; CHECK: #APP
+; CHECK: lw $[[T3:[0-9]+]], 0($[[T0]])
+; CHECK: #NO_APP
+; CHECK: sw $[[T3]], 0($[[T1]])
+
+ %l1 = alloca i32, align 4
+ call void asm "sw $1, $0", "=*m,r"(i32* %l1, i32 %x) nounwind
+ %0 = call i32 asm "lw $0, $1", "=r,*m"(i32* %l1) nounwind
+ store i32 %0, i32* @g1, align 4
+ ret i32 %0
+}
+
diff --git a/test/CodeGen/Mips/internalfunc.ll b/test/CodeGen/Mips/internalfunc.ll
index 50d099385a6e..c2a4e5cfc24f 100644
--- a/test/CodeGen/Mips/internalfunc.ll
+++ b/test/CodeGen/Mips/internalfunc.ll
@@ -15,7 +15,7 @@ entry:
define void @caller(i32 %a0, i32 %a1) nounwind {
entry:
; CHECK: lw $[[R1:[0-9]+]], %got(caller.sf1)($gp)
-; CHECK: addiu ${{[0-9]+}}, $[[R1]], %lo(caller.sf1)
+; CHECK: lw $25, %lo(caller.sf1)($[[R1]])
%tobool = icmp eq i32 %a1, 0
br i1 %tobool, label %if.end, label %if.then
@@ -26,9 +26,9 @@ if.then: ; preds = %entry
if.end: ; preds = %entry, %if.then
; CHECK: lw $[[R2:[0-9]+]], %got(sf2)($gp)
-; CHECK: lw $[[R3:[0-9]+]], %got(caller.sf1)($gp)
; CHECK: addiu ${{[0-9]+}}, $[[R2]], %lo(sf2)
-; CHECK: addiu ${{[0-9]+}}, $[[R3]], %lo(caller.sf1)
+; CHECK: lw $[[R3:[0-9]+]], %got(caller.sf1)($gp)
+; CHECK: sw ${{[0-9]+}}, %lo(caller.sf1)($[[R3]])
%tobool3 = icmp ne i32 %a0, 0
%tmp4 = load void (...)** @gf1, align 4
%cond = select i1 %tobool3, void (...)* %tmp4, void (...)* bitcast (void ()* @sf2 to void (...)*)
diff --git a/test/CodeGen/Mips/largeimmprinting.ll b/test/CodeGen/Mips/largeimmprinting.ll
index fd7ae9e0ac20..fcc20f799440 100644
--- a/test/CodeGen/Mips/largeimmprinting.ll
+++ b/test/CodeGen/Mips/largeimmprinting.ll
@@ -8,7 +8,7 @@ define void @f() nounwind {
entry:
; CHECK: lui $at, 65534
; CHECK: addu $at, $sp, $at
-; CHECK: addiu $sp, $at, -16
+; CHECK: addiu $sp, $at, -24
; CHECK: .cprestore 65536
%agg.tmp = alloca %struct.S1, align 1
diff --git a/test/CodeGen/Mips/o32_cc_byval.ll b/test/CodeGen/Mips/o32_cc_byval.ll
index b78c393498c4..f5e1a878dcfa 100644
--- a/test/CodeGen/Mips/o32_cc_byval.ll
+++ b/test/CodeGen/Mips/o32_cc_byval.ll
@@ -24,7 +24,7 @@ entry:
; CHECK: sw $[[R4]], 28($sp)
; CHECK: sw $[[R5]], 32($sp)
; CHECK: sw $[[R6]], 36($sp)
-; CHECK: lw $6, 0($[[R0]])
+; CHECK: lw $6, %lo(f1.s1)($[[R1]])
; CHECK: lw $7, 4($[[R0]])
%agg.tmp10 = alloca %struct.S3, align 4
call void @callee1(float 2.000000e+01, %struct.S1* byval bitcast (%0* @f1.s1 to %struct.S1*)) nounwind
diff --git a/test/CodeGen/Mips/private.ll b/test/CodeGen/Mips/private.ll
index 34b75477b689..4cc48f098a9e 100644
--- a/test/CodeGen/Mips/private.ll
+++ b/test/CodeGen/Mips/private.ll
@@ -6,8 +6,6 @@
; RUN: grep \\\$baz: %t
; RUN: grep lw.*\\\$baz %t
-declare void @foo()
-
define private void @foo() {
ret void
}