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author	Dimitry Andric <dim@FreeBSD.org>	2014-11-24 09:08:18 +0000
committer	Dimitry Andric <dim@FreeBSD.org>	2014-11-24 09:08:18 +0000
commit	5ca98fd98791947eba83a1ed3f2c8191ef7afa6c (patch)
tree	f5944309621cee4fe0976be6f9ac619b7ebfc4c2 /test/CodeGen/R600/sra.ll
parent	68bcb7db193e4bc81430063148253d30a791023e (diff)
download	src-5ca98fd98791947eba83a1ed3f2c8191ef7afa6c.tar.gz src-5ca98fd98791947eba83a1ed3f2c8191ef7afa6c.zip

Vendor import of llvm RELEASE_350/final tag r216957 (effectively, 3.5.0 release):vendor/llvm/llvm-release_350-r216957

https://llvm.org/svn/llvm-project/llvm/tags/RELEASE_350/final@216957

Notes

Notes: svn path=/vendor/llvm/dist/; revision=274955 svn path=/vendor/llvm/llvm-release_35-r216957/; revision=274956; tag=vendor/llvm/llvm-release_350-r216957

Diffstat (limited to 'test/CodeGen/R600/sra.ll')

-rw-r--r--

test/CodeGen/R600/sra.ll

130

1 files changed, 130 insertions, 0 deletions

diff --git a/test/CodeGen/R600/sra.ll b/test/CodeGen/R600/sra.ll
index fe9df104ae11..9eb3dc544074 100644
--- a/test/CodeGen/R600/sra.ll
+++ b/test/CodeGen/R600/sra.ll

@@ -52,3 +52,133 @@ entry:

ret void

}

+;EG-CHECK-LABEL: @ashr_i64_2

+;EG-CHECK: SUB_INT {{\*? *}}[[COMPSH:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHIFT:T[0-9]+\.[XYZW]]]

+;EG-CHECK: LSHL {{\* *}}[[TEMP:T[0-9]+\.[XYZW]]], [[OPHI:T[0-9]+\.[XYZW]]], {{[[COMPSH]]|PV.[XYZW]}}

+;EG-CHECK: LSHL {{\*? *}}[[OVERF:T[0-9]+\.[XYZW]]], {{[[TEMP]]|PV.[XYZW]}}, 1

+;EG_CHECK-DAG: ADD_INT {{\*? *}}[[BIGSH:T[0-9]+\.[XYZW]]], [[SHIFT]], literal

+;EG-CHECK-DAG: LSHR {{\*? *}}[[LOSMTMP:T[0-9]+\.[XYZW]]], [[OPLO:T[0-9]+\.[XYZW]]], [[SHIFT]]

+;EG-CHECK-DAG: OR_INT {{\*? *}}[[LOSM:T[0-9]+\.[XYZW]]], {{[[LOSMTMP]]|PV.[XYZW]}}, {{[[OVERF]]|PV.[XYZW]}}

+;EG-CHECK-DAG: ASHR {{\*? *}}[[HISM:T[0-9]+\.[XYZW]]], [[OPHI]], {{PS|[[SHIFT]]}}

+;EG-CHECK-DAG: ASHR {{\*? *}}[[LOBIG:T[0-9]+\.[XYZW]]], [[OPHI]], literal

+;EG-CHECK-DAG: ASHR {{\*? *}}[[HIBIG:T[0-9]+\.[XYZW]]], [[OPHI]], literal

+;EG-CHECK-DAG: SETGT_UINT {{\*? *}}[[RESC:T[0-9]+\.[XYZW]]], [[SHIFT]], literal

+;EG-CHECK-DAG: CNDE_INT {{\*? *}}[[RESLO:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}}

+;EG-CHECK-DAG: CNDE_INT {{\*? *}}[[RESHI:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}}

+;SI-CHECK-LABEL: @ashr_i64_2

+;SI-CHECK: V_ASHR_I64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}

+define void @ashr_i64_2(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {

+entry:

+ %b_ptr = getelementptr i64 addrspace(1)* %in, i64 1

+ %a = load i64 addrspace(1) * %in

+ %b = load i64 addrspace(1) * %b_ptr

+ %result = ashr i64 %a, %b

+ store i64 %result, i64 addrspace(1)* %out

+ ret void

+;EG-CHECK-LABEL: @ashr_v2i64

+;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]]

+;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]]

+;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHA]]

+;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHB]]

+;EG-CHECK-DAG: LSHL {{.*}}, 1

+;EG-CHECK-DAG: ASHR {{.*}}, [[SHA]]

+;EG-CHECK-DAG: ASHR {{.*}}, [[SHB]]

+;EG-CHECK-DAG: LSHR {{.*}}, [[SHA]]

+;EG-CHECK-DAG: LSHR {{.*}}, [[SHB]]

+;EG-CHECK-DAG: OR_INT

+;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal

+;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal

+;EG-CHECK-DAG: ASHR

+;EG-CHECK-DAG: ASHR {{.*}}, literal

+;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal

+;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal

+;EG-CHECK-DAG: CNDE_INT

+;SI-CHECK-LABEL: @ashr_v2i64

+;SI-CHECK: V_ASHR_I64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}

+define void @ashr_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) {

+ %b_ptr = getelementptr <2 x i64> addrspace(1)* %in, i64 1

+ %a = load <2 x i64> addrspace(1) * %in

+ %b = load <2 x i64> addrspace(1) * %b_ptr

+ %result = ashr <2 x i64> %a, %b

+ store <2 x i64> %result, <2 x i64> addrspace(1)* %out

+ ret void

+;EG-CHECK-LABEL: @ashr_v4i64

+;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]]

+;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]]

+;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHC:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHC:T[0-9]+\.[XYZW]]]

+;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHD:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHD:T[0-9]+\.[XYZW]]]

+;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHA]]

+;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHB]]

+;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHC]]

+;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHD]]

+;EG-CHECK-DAG: LSHL {{.*}}, 1

+;EG-CHECK-DAG: ASHR {{.*}}, [[SHA]]

+;EG-CHECK-DAG: ASHR {{.*}}, [[SHB]]

+;EG-CHECK-DAG: ASHR {{.*}}, [[SHC]]

+;EG-CHECK-DAG: ASHR {{.*}}, [[SHD]]

+;EG-CHECK-DAG: LSHR {{.*}}, [[SHA]]

+;EG-CHECK-DAG: LSHR {{.*}}, [[SHB]]

+;EG-CHECK-DAG: LSHR {{.*}}, [[SHA]]

+;EG-CHECK-DAG: LSHR {{.*}}, [[SHB]]

+;EG-CHECK-DAG: OR_INT

+;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal

+;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal

+;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHC:T[0-9]+\.[XYZW]]]{{.*}}, literal

+;EG-CHECK-DAG: ADD_INT {{\*? *}}[[BIGSHD:T[0-9]+\.[XYZW]]]{{.*}}, literal

+;EG-CHECK-DAG: ASHR

+;EG-CHECK-DAG: ASHR {{.*}}, literal

+;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal

+;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal

+;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHC]], literal

+;EG-CHECK-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHD]], literal

+;EG-CHECK-DAG: CNDE_INT

+;SI-CHECK-LABEL: @ashr_v4i64

+;SI-CHECK: V_ASHR_I64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}

+define void @ashr_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) {

+ %b_ptr = getelementptr <4 x i64> addrspace(1)* %in, i64 1

+ %a = load <4 x i64> addrspace(1) * %in

+ %b = load <4 x i64> addrspace(1) * %b_ptr

+ %result = ashr <4 x i64> %a, %b

+ store <4 x i64> %result, <4 x i64> addrspace(1)* %out

+ ret void