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author	Dimitry Andric <dim@FreeBSD.org>	2015-01-18 16:17:27 +0000
committer	Dimitry Andric <dim@FreeBSD.org>	2015-01-18 16:17:27 +0000
commit	67c32a98315f785a9ec9d531c1f571a0196c7463 (patch)
tree	4abb9cbeecc7901726dd0b4a37369596c852e9ef /test/CodeGen/R600/sra.ll
parent	9f61947910e6ab40de38e6b4034751ef1513200f (diff)
download	src-67c32a98315f785a9ec9d531c1f571a0196c7463.tar.gz src-67c32a98315f785a9ec9d531c1f571a0196c7463.zip

Vendor import of llvm RELEASE_360/rc1 tag r226102 (effectively, 3.6.0 RC1):vendor/llvm/llvm-release_360-r226102

https://llvm.org/svn/llvm-project/llvm/tags/RELEASE_360/rc1@226102

Notes

Notes: svn path=/vendor/llvm/dist/; revision=277323 svn path=/vendor/llvm/llvm-release_360-r226102/; revision=277324; tag=vendor/llvm/llvm-release_360-r226102

Diffstat (limited to 'test/CodeGen/R600/sra.ll')

-rw-r--r--

test/CodeGen/R600/sra.ll

1 files changed, 27 insertions, 27 deletions

diff --git a/test/CodeGen/R600/sra.ll b/test/CodeGen/R600/sra.ll
index 9eb3dc544074..d463fc20b9c5 100644
--- a/test/CodeGen/R600/sra.ll
+++ b/test/CodeGen/R600/sra.ll

@@ -1,13 +1,13 @@

;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s

-;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s

+;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s

-;EG-CHECK-LABEL: @ashr_v2i32

+;EG-CHECK-LABEL: {{^}}ashr_v2i32:

;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}

-;SI-CHECK-LABEL: @ashr_v2i32

-;SI-CHECK: V_ASHR_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}

+;SI-CHECK-LABEL: {{^}}ashr_v2i32:

+;SI-CHECK: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}

define void @ashr_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {

%b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1

@@ -18,17 +18,17 @@ define void @ashr_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %i

ret void

}

-;EG-CHECK-LABEL: @ashr_v4i32

+;EG-CHECK-LABEL: {{^}}ashr_v4i32:

;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}

-;SI-CHECK-LABEL: @ashr_v4i32

-;SI-CHECK: V_ASHR_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}

+;SI-CHECK-LABEL: {{^}}ashr_v4i32:

+;SI-CHECK: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}

define void @ashr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {

%b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1

@@ -39,11 +39,11 @@ define void @ashr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %i

ret void

}

-;EG-CHECK-LABEL: @ashr_i64

+;EG-CHECK-LABEL: {{^}}ashr_i64:

;EG-CHECK: ASHR

-;SI-CHECK-LABEL: @ashr_i64

-;SI-CHECK: S_ASHR_I64 s[{{[0-9]}}:{{[0-9]}}], s[{{[0-9]}}:{{[0-9]}}], 8

+;SI-CHECK-LABEL: {{^}}ashr_i64:

+;SI-CHECK: s_ashr_i64 s[{{[0-9]}}:{{[0-9]}}], s[{{[0-9]}}:{{[0-9]}}], 8

define void @ashr_i64(i64 addrspace(1)* %out, i32 %in) {

entry:

%0 = sext i32 %in to i64

@@ -52,7 +52,7 @@ entry:

ret void

}

-;EG-CHECK-LABEL: @ashr_i64_2

+;EG-CHECK-LABEL: {{^}}ashr_i64_2:

;EG-CHECK: SUB_INT {{\*? *}}[[COMPSH:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHIFT:T[0-9]+\.[XYZW]]]

;EG-CHECK: LSHL {{\* *}}[[TEMP:T[0-9]+\.[XYZW]]], [[OPHI:T[0-9]+\.[XYZW]]], {{[[COMPSH]]|PV.[XYZW]}}

;EG-CHECK: LSHL {{\*? *}}[[OVERF:T[0-9]+\.[XYZW]]], {{[[TEMP]]|PV.[XYZW]}}, 1

@@ -66,8 +66,8 @@ entry:

;EG-CHECK-DAG: CNDE_INT {{\*? *}}[[RESLO:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}}

;EG-CHECK-DAG: CNDE_INT {{\*? *}}[[RESHI:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}}

-;SI-CHECK-LABEL: @ashr_i64_2

-;SI-CHECK: V_ASHR_I64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}

+;SI-CHECK-LABEL: {{^}}ashr_i64_2:

+;SI-CHECK: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}

define void @ashr_i64_2(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {

entry:

%b_ptr = getelementptr i64 addrspace(1)* %in, i64 1

@@ -78,7 +78,7 @@ entry:

ret void

}

-;EG-CHECK-LABEL: @ashr_v2i64

+;EG-CHECK-LABEL: {{^}}ashr_v2i64:

;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]]

;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]]

;EG-CHECK-DAG: LSHL {{\*? *}}[[COMPSHA]]

@@ -104,9 +104,9 @@ entry:

;EG-CHECK-DAG: CNDE_INT

-;SI-CHECK-LABEL: @ashr_v2i64

-;SI-CHECK: V_ASHR_I64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}

+;SI-CHECK-LABEL: {{^}}ashr_v2i64:

+;SI-CHECK: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}

define void @ashr_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) {

%b_ptr = getelementptr <2 x i64> addrspace(1)* %in, i64 1

@@ -117,7 +117,7 @@ define void @ashr_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %i

ret void

}

-;EG-CHECK-LABEL: @ashr_v4i64

+;EG-CHECK-LABEL: {{^}}ashr_v4i64:

;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]]

;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]]

;EG-CHECK-DAG: SUB_INT {{\*? *}}[[COMPSHC:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHC:T[0-9]+\.[XYZW]]]

@@ -167,11 +167,11 @@ define void @ashr_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %i

;EG-CHECK-DAG: CNDE_INT

-;SI-CHECK-LABEL: @ashr_v4i64

-;SI-CHECK: V_ASHR_I64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}

+;SI-CHECK-LABEL: {{^}}ashr_v4i64:

+;SI-CHECK: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}

define void @ashr_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) {

%b_ptr = getelementptr <4 x i64> addrspace(1)* %in, i64 1