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| author | Dimitry Andric <dim@FreeBSD.org> | 2017-12-18 20:10:56 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2017-12-18 20:10:56 +0000 |
| commit | 044eb2f6afba375a914ac9d8024f8f5142bb912e (patch) | |
| tree | 1475247dc9f9fe5be155ebd4c9069c75aadf8c20 /test/CodeGen/X86/GlobalISel/legalize-insert-vec512.mir | |
| parent | eb70dddbd77e120e5d490bd8fbe7ff3f8fa81c6b (diff) | |
| download | src-044eb2f6afba375a914ac9d8024f8f5142bb912e.tar.gz src-044eb2f6afba375a914ac9d8024f8f5142bb912e.zip | |
Vendor import of llvm trunk r321017:vendor/llvm/llvm-trunk-r321017
Notes
Notes:
svn path=/vendor/llvm/dist/; revision=326938
svn path=/vendor/llvm/llvm-trunk-r321017/; revision=326939; tag=vendor/llvm/llvm-trunk-r321017
Diffstat (limited to 'test/CodeGen/X86/GlobalISel/legalize-insert-vec512.mir')
| -rw-r--r-- | test/CodeGen/X86/GlobalISel/legalize-insert-vec512.mir | 29 |
1 files changed, 15 insertions, 14 deletions
diff --git a/test/CodeGen/X86/GlobalISel/legalize-insert-vec512.mir b/test/CodeGen/X86/GlobalISel/legalize-insert-vec512.mir index 777531da4d93..d9fb35e44dc3 100644 --- a/test/CodeGen/X86/GlobalISel/legalize-insert-vec512.mir +++ b/test/CodeGen/X86/GlobalISel/legalize-insert-vec512.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --- | @@ -11,7 +12,6 @@ ... --- name: test_insert_128 -# ALL-LABEL: name: test_insert_128 alignment: 4 legalized: false regBankSelected: false @@ -19,25 +19,25 @@ registers: - { id: 0, class: _ } - { id: 1, class: _ } - { id: 2, class: _ } -# ALL: %0(<16 x s32>) = COPY %zmm0 -# ALL-NEXT: %1(<4 x s32>) = COPY %xmm1 -# ALL-NEXT: %2(<16 x s32>) = G_INSERT %0, %1(<4 x s32>), 0 -# ALL-NEXT: %ymm0 = COPY %2(<16 x s32>) -# ALL-NEXT: RET 0, implicit %ymm0 body: | bb.1 (%ir-block.0): liveins: %zmm0, %ymm1 + ; ALL-LABEL: name: test_insert_128 + ; ALL: [[COPY:%[0-9]+]]:_(<16 x s32>) = COPY %zmm0 + ; ALL: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY %xmm1 + ; ALL: [[INSERT:%[0-9]+]]:_(<16 x s32>) = G_INSERT [[COPY]], [[COPY1]](<4 x s32>), 0 + ; ALL: %zmm0 = COPY [[INSERT]](<16 x s32>) + ; ALL: RET 0, implicit %ymm0 %0(<16 x s32>) = COPY %zmm0 %1(<4 x s32>) = COPY %xmm1 %2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<4 x s32>), 0 - %ymm0 = COPY %2(<16 x s32>) + %zmm0 = COPY %2(<16 x s32>) RET 0, implicit %ymm0 ... --- name: test_insert_256 -# ALL-LABEL: name: test_insert_256 alignment: 4 legalized: false regBankSelected: false @@ -45,19 +45,20 @@ registers: - { id: 0, class: _ } - { id: 1, class: _ } - { id: 2, class: _ } -# ALL: %0(<16 x s32>) = COPY %zmm0 -# ALL-NEXT: %1(<8 x s32>) = COPY %ymm1 -# ALL-NEXT: %2(<16 x s32>) = G_INSERT %0, %1(<8 x s32>), 0 -# ALL-NEXT: %ymm0 = COPY %2(<16 x s32>) -# ALL-NEXT: RET 0, implicit %ymm0 body: | bb.1 (%ir-block.0): liveins: %zmm0, %ymm1 + ; ALL-LABEL: name: test_insert_256 + ; ALL: [[COPY:%[0-9]+]]:_(<16 x s32>) = COPY %zmm0 + ; ALL: [[COPY1:%[0-9]+]]:_(<8 x s32>) = COPY %ymm1 + ; ALL: [[INSERT:%[0-9]+]]:_(<16 x s32>) = G_INSERT [[COPY]], [[COPY1]](<8 x s32>), 0 + ; ALL: %zmm0 = COPY [[INSERT]](<16 x s32>) + ; ALL: RET 0, implicit %ymm0 %0(<16 x s32>) = COPY %zmm0 %1(<8 x s32>) = COPY %ymm1 %2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<8 x s32>), 0 - %ymm0 = COPY %2(<16 x s32>) + %zmm0 = COPY %2(<16 x s32>) RET 0, implicit %ymm0 ... |