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| author | Dimitry Andric <dim@FreeBSD.org> | 2012-04-14 13:54:10 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2012-04-14 13:54:10 +0000 |
| commit | 63faed5b8e4f2755f127fcb8aa440480c0649327 (patch) | |
| tree | 19c69a04768629f2d440944b71cbe90adae0b615 /test/CodeGen/X86/SwizzleShuff.ll | |
| parent | d4c8b5d2e851b0e8a063c6bf8543a4823a26c15a (diff) | |
| download | src-63faed5b8e4f2755f127fcb8aa440480c0649327.tar.gz src-63faed5b8e4f2755f127fcb8aa440480c0649327.zip | |
Vendor import of llvm trunk r154661:vendor/llvm/llvm-trunk-r154661
Notes
Notes:
svn path=/vendor/llvm/dist/; revision=234285
svn path=/vendor/llvm/llvm-trunk-r154661/; revision=234286; tag=vendor/llvm/llvm-trunk-r154661
Diffstat (limited to 'test/CodeGen/X86/SwizzleShuff.ll')
| -rw-r--r-- | test/CodeGen/X86/SwizzleShuff.ll | 68 |
1 files changed, 68 insertions, 0 deletions
diff --git a/test/CodeGen/X86/SwizzleShuff.ll b/test/CodeGen/X86/SwizzleShuff.ll new file mode 100644 index 000000000000..100817a676e8 --- /dev/null +++ b/test/CodeGen/X86/SwizzleShuff.ll @@ -0,0 +1,68 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s + +; Check that we perform a scalar XOR on i32. + +; CHECK: pull_bitcast +; CHECK: xorl +; CHECK: ret +define void @pull_bitcast (<4 x i8>* %pA, <4 x i8>* %pB) { + %A = load <4 x i8>* %pA + %B = load <4 x i8>* %pB + %C = xor <4 x i8> %A, %B + store <4 x i8> %C, <4 x i8>* %pA + ret void +} + +; CHECK: multi_use_swizzle +; CHECK: mov +; CHECK-NEXT: shuf +; CHECK-NEXT: shuf +; CHECK-NEXT: shuf +; CHECK-NEXT: xor +; CHECK-NEXT: ret +define <4 x i32> @multi_use_swizzle (<4 x i32>* %pA, <4 x i32>* %pB) { + %A = load <4 x i32>* %pA + %B = load <4 x i32>* %pB + %S = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 1, i32 5, i32 6> + %S1 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 1, i32 3, i32 2, i32 2> + %S2 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 2> + %R = xor <4 x i32> %S1, %S2 + ret <4 x i32> %R +} + +; CHECK: pull_bitcast2 +; CHECK: xorl +; CHECK: ret +define <4 x i8> @pull_bitcast2 (<4 x i8>* %pA, <4 x i8>* %pB, <4 x i8>* %pC) { + %A = load <4 x i8>* %pA + store <4 x i8> %A, <4 x i8>* %pC + %B = load <4 x i8>* %pB + %C = xor <4 x i8> %A, %B + store <4 x i8> %C, <4 x i8>* %pA + ret <4 x i8> %C +} + + + +; CHECK: reverse_1 +; CHECK-NOT: shuf +; CHECK: ret +define <4 x i32> @reverse_1 (<4 x i32>* %pA, <4 x i32>* %pB) { + %A = load <4 x i32>* %pA + %B = load <4 x i32>* %pB + %S = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 0, i32 3, i32 2> + %S1 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> + ret <4 x i32> %S1 +} + + +; CHECK: no_reverse_shuff +; CHECK: shuf +; CHECK: ret +define <4 x i32> @no_reverse_shuff (<4 x i32>* %pA, <4 x i32>* %pB) { + %A = load <4 x i32>* %pA + %B = load <4 x i32>* %pB + %S = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 0, i32 3, i32 2> + %S1 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 3, i32 2> + ret <4 x i32> %S1 +} |