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authorDimitry Andric <dim@FreeBSD.org>2018-07-28 10:51:19 +0000
committerDimitry Andric <dim@FreeBSD.org>2018-07-28 10:51:19 +0000
commiteb11fae6d08f479c0799db45860a98af528fa6e7 (patch)
tree44d492a50c8c1a7eb8e2d17ea3360ec4d066f042 /test/CodeGen/X86/fixup-bw-inst.mir
parentb8a2042aa938069e862750553db0e4d82d25822c (diff)
downloadsrc-eb11fae6d08f479c0799db45860a98af528fa6e7.tar.gz
src-eb11fae6d08f479c0799db45860a98af528fa6e7.zip
Vendor import of llvm trunk r338150:vendor/llvm/llvm-trunk-r338150
Notes
Notes: svn path=/vendor/llvm/dist/; revision=336809 svn path=/vendor/llvm/llvm-trunk-r338150/; revision=336814; tag=vendor/llvm/llvm-trunk-r338150
Diffstat (limited to 'test/CodeGen/X86/fixup-bw-inst.mir')
-rw-r--r--test/CodeGen/X86/fixup-bw-inst.mir143
1 files changed, 72 insertions, 71 deletions
diff --git a/test/CodeGen/X86/fixup-bw-inst.mir b/test/CodeGen/X86/fixup-bw-inst.mir
index cea483e1b9bc..c5ccaa46f37b 100644
--- a/test/CodeGen/X86/fixup-bw-inst.mir
+++ b/test/CodeGen/X86/fixup-bw-inst.mir
@@ -26,103 +26,67 @@
ret i16 %i.0
}
+ define i16 @test4() {
+ entry:
+ %t1 = zext i1 undef to i16
+ %t2 = or i16 undef, %t1
+ ret i16 %t2
+ }
+
+ define void @test5() {ret void}
+
...
---
# CHECK-LABEL: name: test1
name: test1
alignment: 4
-exposesReturnsTwice: false
-legalized: false
-regBankSelected: false
-selected: false
tracksRegLiveness: true
-registers:
liveins:
- - { reg: '%rax' }
-frameInfo:
- stackSize: 0
-fixedStack:
-stack:
-constants:
-# Verify that "movw (%rax), %ax" is changed to "movzwl (%rax), %rax".
+ - { reg: '$rax' }
+# Verify that "movw ($rax), $ax" is changed to "movzwl ($rax), $rax".
#
# For that to happen, the liveness information after the MOV16rm
-# instruction should be used, not before it because %rax is live
+# instruction should be used, not before it because $rax is live
# before the MOV and is killed by it.
body: |
bb.0:
- liveins: %rax
+ liveins: $rax
- %ax = MOV16rm killed %rax, 1, %noreg, 0, %noreg
- ; CHECK: %eax = MOVZX32rm16 killed %rax
+ $ax = MOV16rm killed $rax, 1, $noreg, 0, $noreg
+ ; CHECK: $eax = MOVZX32rm16 killed $rax
- RETQ %ax
+ RETQ $ax
...
---
# CHECK-LABEL: name: test2
name: test2
alignment: 4
-exposesReturnsTwice: false
-legalized: false
-regBankSelected: false
-selected: false
tracksRegLiveness: true
-registers:
liveins:
- - { reg: '%rax' }
-frameInfo:
- stackSize: 0
-fixedStack:
-stack:
-constants:
+ - { reg: '$rax' }
# Imp-use of any super-register means the register is live before the MOV
body: |
bb.0:
- liveins: %dl, %rbx, %rcx, %r14
+ liveins: $dl, $rbx, $rcx, $r14
- %cl = MOV8rr killed %dl, implicit killed %rcx, implicit-def %rcx
- ; CHECK: %cl = MOV8rr killed %dl, implicit killed %rcx, implicit-def %rcx
+ $cl = MOV8rr killed $dl, implicit killed $rcx, implicit-def $rcx
+ ; CHECK: $cl = MOV8rr killed $dl, implicit killed $rcx, implicit-def $rcx
JMP_1 %bb.1
bb.1:
- liveins: %rcx
+ liveins: $rcx
- RETQ %cl
+ RETQ $cl
...
---
# CHECK-LABEL: name: test3
name: test3
alignment: 4
-exposesReturnsTwice: false
-legalized: false
-regBankSelected: false
-selected: false
tracksRegLiveness: true
-registers:
liveins:
- - { reg: '%rdi', virtual-reg: '' }
-frameInfo:
- isFrameAddressTaken: false
- isReturnAddressTaken: false
- hasStackMap: false
- hasPatchPoint: false
- stackSize: 0
- offsetAdjustment: 0
- maxAlignment: 0
- adjustsStack: false
- hasCalls: false
- stackProtector: ''
- maxCallFrameSize: 0
- hasOpaqueSPAdjustment: false
- hasVAStart: false
- hasMustTailInVarArgFunc: false
- savePoint: ''
- restorePoint: ''
-fixedStack:
-stack:
-constants:
-# After MOV16rm the whole %eax is not *really* live, as can be seen by
+ - { reg: '$rdi' }
+# After MOV16rm the whole $eax is not *really* live, as can be seen by
# missing implicit-uses of it in that MOV. Make sure that MOV is
# transformed into MOVZX.
# See the comment near the original IR on what preceding decisions can
@@ -130,22 +94,59 @@ constants:
body: |
bb.0.entry:
successors: %bb.1(0x30000000), %bb.2.if.then(0x50000000)
- liveins: %rdi
+ liveins: $rdi
- TEST64rr %rdi, %rdi, implicit-def %eflags
- JE_1 %bb.1, implicit %eflags
+ TEST64rr $rdi, $rdi, implicit-def $eflags
+ JE_1 %bb.1, implicit $eflags
bb.2.if.then:
- liveins: %rdi
+ liveins: $rdi
- %ax = MOV16rm killed %rdi, 1, %noreg, 0, %noreg, implicit-def %eax :: (load 2 from %ir.p)
- ; CHECK: %eax = MOVZX32rm16 killed %rdi, 1, %noreg, 0, %noreg, implicit-def %eax :: (load 2 from %ir.p)
- %ax = KILL %ax, implicit killed %eax
- RETQ %ax
+ $ax = MOV16rm killed $rdi, 1, $noreg, 0, $noreg, implicit-def $eax :: (load 2 from %ir.p)
+ ; CHECK: $eax = MOVZX32rm16 killed $rdi, 1, $noreg, 0, $noreg, implicit-def $eax :: (load 2 from %ir.p)
+ $ax = KILL $ax, implicit killed $eax
+ RETQ $ax
bb.1:
- %eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags
- %ax = KILL %ax, implicit killed %eax
- RETQ %ax
+ $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags
+ $ax = KILL $ax, implicit killed $eax
+ RETQ $ax
+
+...
+---
+# CHECK-LABEL: name: test4
+name: test4
+alignment: 4
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r9d' }
+# This code copies r10b into r9b and then uses r9w. We would like to promote
+# the copy to a 32-bit copy, but because r9w is used this is not acceptable.
+body: |
+ bb.0.entry:
+ liveins: $r9d
+
+ $r9b = MOV8rr undef $r10b, implicit-def $r9d, implicit killed $r9d, implicit-def $eflags
+ ; CHECK: $r9b = MOV8rr undef $r10b, implicit-def $r9d, implicit killed $r9d, implicit-def $eflags
+
+ $ax = OR16rr undef $ax, $r9w, implicit-def $eflags
+ RETQ $ax
+
+...
+---
+# CHECK-LABEL: name: test5
+name: test5
+alignment: 4
+tracksRegLiveness: true
+liveins:
+ - { reg: '$ch', reg: '$bl' }
+body: |
+ bb.0:
+ liveins: $ch, $bl
+
+ $cl = MOV8rr $bl, implicit-def $cx, implicit killed $ch, implicit-def $eflags
+ ; CHECK: $cl = MOV8rr $bl, implicit-def $cx, implicit killed $ch, implicit-def $eflags
+
+ RETQ $cx
...