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| author | Dimitry Andric <dim@FreeBSD.org> | 2018-07-28 10:51:19 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2018-07-28 10:51:19 +0000 |
| commit | eb11fae6d08f479c0799db45860a98af528fa6e7 (patch) | |
| tree | 44d492a50c8c1a7eb8e2d17ea3360ec4d066f042 /test/MC/AArch64/SVE/sqdech-diagnostics.s | |
| parent | b8a2042aa938069e862750553db0e4d82d25822c (diff) | |
| download | src-eb11fae6d08f479c0799db45860a98af528fa6e7.tar.gz src-eb11fae6d08f479c0799db45860a98af528fa6e7.zip | |
Vendor import of llvm trunk r338150:vendor/llvm/llvm-trunk-r338150
Notes
Notes:
svn path=/vendor/llvm/dist/; revision=336809
svn path=/vendor/llvm/llvm-trunk-r338150/; revision=336814; tag=vendor/llvm/llvm-trunk-r338150
Diffstat (limited to 'test/MC/AArch64/SVE/sqdech-diagnostics.s')
| -rw-r--r-- | test/MC/AArch64/SVE/sqdech-diagnostics.s | 81 |
1 files changed, 81 insertions, 0 deletions
diff --git a/test/MC/AArch64/SVE/sqdech-diagnostics.s b/test/MC/AArch64/SVE/sqdech-diagnostics.s new file mode 100644 index 000000000000..dd68b9d08f09 --- /dev/null +++ b/test/MC/AArch64/SVE/sqdech-diagnostics.s @@ -0,0 +1,81 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + +// ------------------------------------------------------------------------- // +// Invalid result register + +sqdech w0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: sqdech w0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdech wsp +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: sqdech wsp +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdech sp +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: sqdech sp +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdech z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqdech z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Operands not matching up + +sqdech x0, w1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be 32-bit form of destination register +// CHECK-NEXT: sqdech x0, w1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdech x0, x1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: sqdech x0, x1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Immediate not compatible with encode/decode function. + +sqdech x0, all, mul #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: sqdech x0, all, mul #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdech x0, all, mul #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: sqdech x0, all, mul #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdech x0, all, mul #17 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16] +// CHECK-NEXT: sqdech x0, all, mul #17 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + + +// ------------------------------------------------------------------------- // +// Invalid predicate patterns + +sqdech x0, vl512 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: sqdech x0, vl512 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdech x0, vl9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand +// CHECK-NEXT: sqdech x0, vl9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdech x0, #-1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern +// CHECK-NEXT: sqdech x0, #-1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqdech x0, #32 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate pattern +// CHECK-NEXT: sqdech x0, #32 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |