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| author | Dimitry Andric <dim@FreeBSD.org> | 2015-12-30 11:46:15 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2015-12-30 11:46:15 +0000 |
| commit | dd58ef019b700900793a1eb48b52123db01b654e (patch) | |
| tree | fcfbb4df56a744f4ddc6122c50521dd3f1c5e196 /test/MC/Mips/mips32r6/invalid.s | |
| parent | 2fe5752e3a7c345cdb59e869278d36af33c13fa4 (diff) | |
| download | src-dd58ef019b700900793a1eb48b52123db01b654e.tar.gz src-dd58ef019b700900793a1eb48b52123db01b654e.zip | |
Vendor import of llvm trunk r256633:
Notes
Notes:
svn path=/vendor/llvm/dist/; revision=292915
Diffstat (limited to 'test/MC/Mips/mips32r6/invalid.s')
| -rw-r--r-- | test/MC/Mips/mips32r6/invalid.s | 43 |
1 files changed, 33 insertions, 10 deletions
diff --git a/test/MC/Mips/mips32r6/invalid.s b/test/MC/Mips/mips32r6/invalid.s index 0ce75e6143c2..1656ac1da350 100644 --- a/test/MC/Mips/mips32r6/invalid.s +++ b/test/MC/Mips/mips32r6/invalid.s @@ -2,17 +2,40 @@ # the assembler (e.g. invalid set of operands or operand's restrictions not met). # RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r6 2>%t1 -# RUN: FileCheck %s < %t1 -check-prefix=ASM +# RUN: FileCheck %s < %t1 .text +local_label: .set noreorder .set noat - jalr.hb $31 # ASM: :[[@LINE]]:9: error: source and destination must be different - jalr.hb $31, $31 # ASM: :[[@LINE]]:9: error: source and destination must be different - ldc2 $8,-21181($at) # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - sdc2 $20,23157($s2) # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - swc2 $25,24880($s0) # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - break 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - break 1024, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - break 7, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - break 1024, 1024 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + align $4, $2, $3, -1 # CHECK: :[[@LINE]]:29: error: expected 2-bit unsigned immediate + align $4, $2, $3, 4 # CHECK: :[[@LINE]]:29: error: expected 2-bit unsigned immediate + jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different + jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different + ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + swc2 $25,24880($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + break -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + break 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + break -1, 5 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + break 1024, 5 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + break 7, -1 # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate + break 7, 1024 # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate + break 1024, 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + // FIXME: Following tests are temporarely disabled, until "PredicateControl not in hierarchy" problem is resolved + bltl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bltul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + blel $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bleul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgel $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgeul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgtl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgtul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + cache -1, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate + jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different + jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different + lsa $2, $3, $4, 0 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4 + lsa $2, $3, $4, 5 # CHECK: :[[@LINE]]:25: error: expected immediate in range 1 .. 4 + pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate + pref 32, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate |