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| -rw-r--r-- | docs/ReleaseNotes.rst | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/docs/ReleaseNotes.rst b/docs/ReleaseNotes.rst index 70d31a625abb..8209c08889ed 100644 --- a/docs/ReleaseNotes.rst +++ b/docs/ReleaseNotes.rst @@ -95,6 +95,22 @@ Changes to the LLVM IR <SpeculativeLoadHardening.html>`_ must be enabled for the function body. +Changes to the JIT APIs +----------------------- + +The ORC (On Request Compilation) JIT APIs have been updated to support +concurrent compilation. The existing (non-concurrent) ORC layer classes and +related APIs are deprecated, have been renamed with a "Legacy" prefix (e.g. +LegacyIRCompileLayer). The deprecated clasess will be removed in LLVM 9. + +An example JIT stack using the concurrent ORC APIs, called LLJIT, has been +added (see include/llvm/ExecutionEngine/Orc/LLJIT.h). The lli tool has been +updated to use LLJIT. + +MCJIT and ExecutionEngine continue to be supported, though ORC should be +preferred for new projects. + + Changes to the AArch64 Target ----------------------------- @@ -173,6 +189,26 @@ Changes to the PowerPC Target * Enabled llvm-exegesis latency mode for PPC +Changes to the SystemZ Target +----------------------------- + +* A number of bugs related to C/C++ language vector extension support were + fixed: the ``-mzvector`` option now actually enables the ``__vector`` and + ``__bool`` keywords, the ``vec_step`` intrinsic now works, and the + ``vec_insert_and_zero`` and ``vec_orc`` intrinsics now generate correct code. + +* The ``__float128`` keyword, which had been accidentally enabled in some + earlier releases, is now no longer supported. On SystemZ, the ``long double`` + data type itself already uses the IEEE 128-bit floating-point format. + +* When the compiler inlines ``strcmp`` or ``memcmp``, the generated code no + longer returns ``INT_MIN`` as the negative result value under any + circumstances. + +* Various code-gen improvements, in particular related to improved + auto-vectorization, inlining, and instruction scheduling. + + Changes to the X86 Target ------------------------- |