diff options
26 files changed, 503 insertions, 45 deletions
diff --git a/include/llvm/CodeGen/GlobalISel/IRTranslator.h b/include/llvm/CodeGen/GlobalISel/IRTranslator.h index f3553966fcdf..2498ee933210 100644 --- a/include/llvm/CodeGen/GlobalISel/IRTranslator.h +++ b/include/llvm/CodeGen/GlobalISel/IRTranslator.h @@ -232,6 +232,7 @@ private: /// Returns true if the value should be split into multiple LLTs. /// If \p Offsets is given then the split type's offsets will be stored in it. + /// If \p Offsets is not empty it will be cleared first. bool valueIsSplit(const Value &V, SmallVectorImpl<uint64_t> *Offsets = nullptr); diff --git a/include/llvm/IR/Function.h b/include/llvm/IR/Function.h index c8d6b0776fbf..02e3ecc8e27f 100644 --- a/include/llvm/IR/Function.h +++ b/include/llvm/IR/Function.h @@ -557,7 +557,7 @@ public: /// True if this function needs an unwind table. bool needsUnwindTableEntry() const { - return hasUWTable() || !doesNotThrow(); + return hasUWTable() || !doesNotThrow() || hasPersonalityFn(); } /// Determine if the function returns a structure through first diff --git a/include/llvm/MC/MCExpr.h b/include/llvm/MC/MCExpr.h index c4dfbe949078..3fd58a169d4b 100644 --- a/include/llvm/MC/MCExpr.h +++ b/include/llvm/MC/MCExpr.h @@ -588,6 +588,8 @@ public: virtual bool evaluateAsRelocatableImpl(MCValue &Res, const MCAsmLayout *Layout, const MCFixup *Fixup) const = 0; + // allow Target Expressions to be checked for equality + virtual bool isEqualTo(const MCExpr *x) const { return false; } // This should be set when assigned expressions are not valid ".set" // expressions, e.g. registers, and must be inlined. virtual bool inlineAssignedExpr() const { return false; } diff --git a/include/llvm/MC/MCParser/MCAsmParserUtils.h b/include/llvm/MC/MCParser/MCAsmParserUtils.h index 259113bc3860..84173bb9cb8e 100644 --- a/include/llvm/MC/MCParser/MCAsmParserUtils.h +++ b/include/llvm/MC/MCParser/MCAsmParserUtils.h @@ -25,7 +25,7 @@ namespace MCParserUtils { /// On success, returns false and sets the Symbol and Value output parameters. bool parseAssignmentExpression(StringRef Name, bool allow_redef, MCAsmParser &Parser, MCSymbol *&Symbol, - const MCExpr *&Value, bool AllowExtendedExpr = false); + const MCExpr *&Value); } // namespace MCParserUtils diff --git a/include/llvm/MC/MCParser/MCTargetAsmParser.h b/include/llvm/MC/MCParser/MCTargetAsmParser.h index 2d188a6755e1..135b5fab07ce 100644 --- a/include/llvm/MC/MCParser/MCTargetAsmParser.h +++ b/include/llvm/MC/MCParser/MCTargetAsmParser.h @@ -372,9 +372,9 @@ public: SemaCallback = Callback; } - // Target-specific parsing of assembler-level variable assignment. - virtual bool parseAssignmentExpression(const MCExpr *&Res, SMLoc &EndLoc) { - return getParser().parseExpression(Res, EndLoc); + // Target-specific parsing of expression. + virtual bool parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) { + return getParser().parsePrimaryExpr(Res, EndLoc); } virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, diff --git a/lib/CodeGen/CodeGenPrepare.cpp b/lib/CodeGen/CodeGenPrepare.cpp index c41beb094604..be685b26a9ea 100644 --- a/lib/CodeGen/CodeGenPrepare.cpp +++ b/lib/CodeGen/CodeGenPrepare.cpp @@ -223,8 +223,17 @@ static cl::opt<bool> namespace { +enum ExtType { + ZeroExtension, // Zero extension has been seen. + SignExtension, // Sign extension has been seen. + BothExtension // This extension type is used if we saw sext after + // ZeroExtension had been set, or if we saw zext after + // SignExtension had been set. It makes the type + // information of a promoted instruction invalid. +}; + using SetOfInstrs = SmallPtrSet<Instruction *, 16>; -using TypeIsSExt = PointerIntPair<Type *, 1, bool>; +using TypeIsSExt = PointerIntPair<Type *, 2, ExtType>; using InstrToOrigTy = DenseMap<Instruction *, TypeIsSExt>; using SExts = SmallVector<Instruction *, 16>; using ValueToSExts = DenseMap<Value *, SExts>; @@ -3277,6 +3286,41 @@ namespace { /// Hepler class to perform type promotion. class TypePromotionHelper { + /// Utility function to add a promoted instruction \p ExtOpnd to + /// \p PromotedInsts and record the type of extension we have seen. + static void addPromotedInst(InstrToOrigTy &PromotedInsts, + Instruction *ExtOpnd, + bool IsSExt) { + ExtType ExtTy = IsSExt ? SignExtension : ZeroExtension; + InstrToOrigTy::iterator It = PromotedInsts.find(ExtOpnd); + if (It != PromotedInsts.end()) { + // If the new extension is same as original, the information in + // PromotedInsts[ExtOpnd] is still correct. + if (It->second.getInt() == ExtTy) + return; + + // Now the new extension is different from old extension, we make + // the type information invalid by setting extension type to + // BothExtension. + ExtTy = BothExtension; + } + PromotedInsts[ExtOpnd] = TypeIsSExt(ExtOpnd->getType(), ExtTy); + } + + /// Utility function to query the original type of instruction \p Opnd + /// with a matched extension type. If the extension doesn't match, we + /// cannot use the information we had on the original type. + /// BothExtension doesn't match any extension type. + static const Type *getOrigType(const InstrToOrigTy &PromotedInsts, + Instruction *Opnd, + bool IsSExt) { + ExtType ExtTy = IsSExt ? SignExtension : ZeroExtension; + InstrToOrigTy::const_iterator It = PromotedInsts.find(Opnd); + if (It != PromotedInsts.end() && It->second.getInt() == ExtTy) + return It->second.getPointer(); + return nullptr; + } + /// Utility function to check whether or not a sign or zero extension /// of \p Inst with \p ConsideredExtType can be moved through \p Inst by /// either using the operands of \p Inst or promoting \p Inst. @@ -3465,10 +3509,9 @@ bool TypePromotionHelper::canGetThrough(const Instruction *Inst, // I.e., check that trunc just drops extended bits of the same kind of // the extension. // #1 get the type of the operand and check the kind of the extended bits. - const Type *OpndType; - InstrToOrigTy::const_iterator It = PromotedInsts.find(Opnd); - if (It != PromotedInsts.end() && It->second.getInt() == IsSExt) - OpndType = It->second.getPointer(); + const Type *OpndType = getOrigType(PromotedInsts, Opnd, IsSExt); + if (OpndType) + ; else if ((IsSExt && isa<SExtInst>(Opnd)) || (!IsSExt && isa<ZExtInst>(Opnd))) OpndType = Opnd->getOperand(0)->getType(); else @@ -3596,8 +3639,7 @@ Value *TypePromotionHelper::promoteOperandForOther( // Remember the original type of the instruction before promotion. // This is useful to know that the high bits are sign extended bits. - PromotedInsts.insert(std::pair<Instruction *, TypeIsSExt>( - ExtOpnd, TypeIsSExt(ExtOpnd->getType(), IsSExt))); + addPromotedInst(PromotedInsts, ExtOpnd, IsSExt); // Step #1. TPT.mutateType(ExtOpnd, Ext->getType()); // Step #2. diff --git a/lib/CodeGen/GlobalISel/IRTranslator.cpp b/lib/CodeGen/GlobalISel/IRTranslator.cpp index 80da50562d32..75496fba0449 100644 --- a/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -1435,6 +1435,8 @@ void IRTranslator::finishPendingPhis() { bool IRTranslator::valueIsSplit(const Value &V, SmallVectorImpl<uint64_t> *Offsets) { SmallVector<LLT, 4> SplitTys; + if (Offsets && !Offsets->empty()) + Offsets->clear(); computeValueLLTs(*DL, *V.getType(), SplitTys, Offsets); return SplitTys.size() > 1; } diff --git a/lib/IR/DebugInfo.cpp b/lib/IR/DebugInfo.cpp index 77585ee30cd8..165c881c13e7 100644 --- a/lib/IR/DebugInfo.cpp +++ b/lib/IR/DebugInfo.cpp @@ -1329,7 +1329,7 @@ LLVMMetadataRef LLVMDIBuilderCreateParameterVariable( size_t NameLen, unsigned ArgNo, LLVMMetadataRef File, unsigned LineNo, LLVMMetadataRef Ty, LLVMBool AlwaysPreserve, LLVMDIFlags Flags) { return wrap(unwrap(Builder)->createParameterVariable( - unwrap<DIScope>(Scope), Name, ArgNo, unwrap<DIFile>(File), + unwrap<DIScope>(Scope), {Name, NameLen}, ArgNo, unwrap<DIFile>(File), LineNo, unwrap<DIType>(Ty), AlwaysPreserve, map_from_llvmDIFlags(Flags))); } diff --git a/lib/MC/MCExpr.cpp b/lib/MC/MCExpr.cpp index 0694a8fa620e..a4c99a0c1c15 100644 --- a/lib/MC/MCExpr.cpp +++ b/lib/MC/MCExpr.cpp @@ -750,8 +750,22 @@ bool MCExpr::evaluateAsRelocatableImpl(MCValue &Res, const MCAssembler *Asm, if (!ABE->getLHS()->evaluateAsRelocatableImpl(LHSValue, Asm, Layout, Fixup, Addrs, InSet) || !ABE->getRHS()->evaluateAsRelocatableImpl(RHSValue, Asm, Layout, Fixup, - Addrs, InSet)) + Addrs, InSet)) { + // Check if both are Target Expressions, see if we can compare them. + if (const MCTargetExpr *L = dyn_cast<MCTargetExpr>(ABE->getLHS())) + if (const MCTargetExpr *R = cast<MCTargetExpr>(ABE->getRHS())) { + switch (ABE->getOpcode()) { + case MCBinaryExpr::EQ: + Res = MCValue::get((L->isEqualTo(R)) ? -1 : 0); + return true; + case MCBinaryExpr::NE: + Res = MCValue::get((R->isEqualTo(R)) ? 0 : -1); + return true; + default: {} + } + } return false; + } // We only support a few operations on non-constant expressions, handle // those first. diff --git a/lib/MC/MCParser/AsmParser.cpp b/lib/MC/MCParser/AsmParser.cpp index 39a760826d96..501a1cccf60e 100644 --- a/lib/MC/MCParser/AsmParser.cpp +++ b/lib/MC/MCParser/AsmParser.cpp @@ -337,7 +337,7 @@ private: StringRef parseStringToComma(); bool parseAssignment(StringRef Name, bool allow_redef, - bool NoDeadStrip = false, bool AllowExtendedExpr = false); + bool NoDeadStrip = false); unsigned getBinOpPrecedence(AsmToken::TokenKind K, MCBinaryExpr::Opcode &Kind); @@ -1363,7 +1363,8 @@ void AsmParser::altMacroString(StringRef AltMacroStr,std::string &Res) { bool AsmParser::parseExpression(const MCExpr *&Res, SMLoc &EndLoc) { // Parse the expression. Res = nullptr; - if (parsePrimaryExpr(Res, EndLoc) || parseBinOpRHS(1, Res, EndLoc)) + if (getTargetParser().parsePrimaryExpr(Res, EndLoc) || + parseBinOpRHS(1, Res, EndLoc)) return true; // As a special case, we support 'a op b @ modifier' by rewriting the @@ -1617,7 +1618,7 @@ bool AsmParser::parseBinOpRHS(unsigned Precedence, const MCExpr *&Res, // Eat the next primary expression. const MCExpr *RHS; - if (parsePrimaryExpr(RHS, EndLoc)) + if (getTargetParser().parsePrimaryExpr(RHS, EndLoc)) return true; // If BinOp binds less tightly with RHS than the operator after RHS, let @@ -1826,7 +1827,7 @@ bool AsmParser::parseStatement(ParseStatementInfo &Info, // identifier '=' ... -> assignment statement Lex(); - return parseAssignment(IDVal, true, /*NoDeadStrip*/ false, /*AllowExtendedExpr*/true); + return parseAssignment(IDVal, true); default: // Normal instruction or directive. break; @@ -2766,11 +2767,11 @@ void AsmParser::handleMacroExit() { } bool AsmParser::parseAssignment(StringRef Name, bool allow_redef, - bool NoDeadStrip, bool AllowExtendedExpr) { + bool NoDeadStrip) { MCSymbol *Sym; const MCExpr *Value; if (MCParserUtils::parseAssignmentExpression(Name, allow_redef, *this, Sym, - Value, AllowExtendedExpr)) + Value)) return true; if (!Sym) { @@ -5839,17 +5840,12 @@ static bool isSymbolUsedInExpression(const MCSymbol *Sym, const MCExpr *Value) { bool parseAssignmentExpression(StringRef Name, bool allow_redef, MCAsmParser &Parser, MCSymbol *&Sym, - const MCExpr *&Value, bool AllowExtendedExpr) { + const MCExpr *&Value) { // FIXME: Use better location, we should use proper tokens. SMLoc EqualLoc = Parser.getTok().getLoc(); - SMLoc EndLoc; - if (AllowExtendedExpr) { - if (Parser.getTargetParser().parseAssignmentExpression(Value, EndLoc)) { - return Parser.TokError("missing expression"); - } - } else if (Parser.parseExpression(Value, EndLoc)) - return Parser.TokError("missing expression"); + if (Parser.parseExpression(Value)) + return Parser.TokError("missing expression"); // Note: we don't count b as used in "a = b". This is to allow // a = b diff --git a/lib/Support/Path.cpp b/lib/Support/Path.cpp index 098230290ed2..768a819c8d05 100644 --- a/lib/Support/Path.cpp +++ b/lib/Support/Path.cpp @@ -1150,8 +1150,16 @@ Error TempFile::keep(const Twine &Name) { // If we can't cancel the delete don't rename. auto H = reinterpret_cast<HANDLE>(_get_osfhandle(FD)); std::error_code RenameEC = setDeleteDisposition(H, false); - if (!RenameEC) + if (!RenameEC) { RenameEC = rename_fd(FD, Name); + // If rename failed because it's cross-device, copy instead + if (RenameEC == + std::error_code(ERROR_NOT_SAME_DEVICE, std::system_category())) { + RenameEC = copy_file(TmpName, Name); + setDeleteDisposition(H, true); + } + } + // If we can't rename, discard the temporary file. if (RenameEC) setDeleteDisposition(H, true); diff --git a/lib/Support/Windows/Path.inc b/lib/Support/Windows/Path.inc index b64b013d7407..f425d607af47 100644 --- a/lib/Support/Windows/Path.inc +++ b/lib/Support/Windows/Path.inc @@ -450,7 +450,7 @@ static std::error_code rename_handle(HANDLE FromHandle, const Twine &To) { if (std::error_code EC2 = realPathFromHandle(FromHandle, WideFrom)) return EC2; if (::MoveFileExW(WideFrom.begin(), WideTo.begin(), - MOVEFILE_REPLACE_EXISTING | MOVEFILE_COPY_ALLOWED)) + MOVEFILE_REPLACE_EXISTING)) return std::error_code(); return mapWindowsError(GetLastError()); } diff --git a/lib/Target/AArch64/AArch64SystemOperands.td b/lib/Target/AArch64/AArch64SystemOperands.td index 8acd32533eea..dbc4deaf3f9f 100644 --- a/lib/Target/AArch64/AArch64SystemOperands.td +++ b/lib/Target/AArch64/AArch64SystemOperands.td @@ -576,6 +576,12 @@ def : ROSysReg<"ICH_VTR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b001>; def : ROSysReg<"ICH_EISR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b011>; def : ROSysReg<"ICH_ELRSR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b101>; +// SVE control registers +// Op0 Op1 CRn CRm Op2 +let Requires = [{ {AArch64::FeatureSVE} }] in { +def : ROSysReg<"ID_AA64ZFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b100>; +} + // v8.1a "Limited Ordering Regions" extension-specific system register // Op0 Op1 CRn CRm Op2 let Requires = [{ {AArch64::HasV8_1aOps} }] in @@ -1311,6 +1317,15 @@ def : RWSysReg<"VNCR_EL2", 0b11, 0b100, 0b0010, 0b0010, 0b000>; } // HasV8_4aOps +// SVE control registers +// Op0 Op1 CRn CRm Op2 +let Requires = [{ {AArch64::FeatureSVE} }] in { +def : RWSysReg<"ZCR_EL1", 0b11, 0b000, 0b0001, 0b0010, 0b000>; +def : RWSysReg<"ZCR_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b000>; +def : RWSysReg<"ZCR_EL3", 0b11, 0b110, 0b0001, 0b0010, 0b000>; +def : RWSysReg<"ZCR_EL12", 0b11, 0b101, 0b0001, 0b0010, 0b000>; +} + // Cyclone specific system registers // Op0 Op1 CRn CRm Op2 let Requires = [{ {AArch64::ProcCyclone} }] in diff --git a/lib/Target/X86/AsmParser/X86AsmParser.cpp b/lib/Target/X86/AsmParser/X86AsmParser.cpp index fafbed0bd935..b02e4d80fbba 100644 --- a/lib/Target/X86/AsmParser/X86AsmParser.cpp +++ b/lib/Target/X86/AsmParser/X86AsmParser.cpp @@ -955,7 +955,7 @@ public: void SetFrameRegister(unsigned RegNo) override; - bool parseAssignmentExpression(const MCExpr *&Res, SMLoc &EndLoc) override; + bool parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) override; bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) override; @@ -2260,15 +2260,17 @@ std::unique_ptr<X86Operand> X86AsmParser::ParseMemOperand(unsigned SegReg, return X86Operand::CreateMem(getPointerWidth(), Disp, MemStart, MemEnd); } -// Parse either a standard expression or a register. -bool X86AsmParser::parseAssignmentExpression(const MCExpr *&Res, - SMLoc &EndLoc) { +// Parse either a standard primary expression or a register. +bool X86AsmParser::parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) { MCAsmParser &Parser = getParser(); - if (Parser.parseExpression(Res, EndLoc)) { + if (Parser.parsePrimaryExpr(Res, EndLoc)) { SMLoc StartLoc = Parser.getTok().getLoc(); // Normal Expression parse fails, check if it could be a register. unsigned RegNo; - if (Parser.getTargetParser().ParseRegister(RegNo, StartLoc, EndLoc)) + bool TryRegParse = + getTok().is(AsmToken::Percent) || + (isParsingIntelSyntax() && getTok().is(AsmToken::Identifier)); + if (!TryRegParse || ParseRegister(RegNo, StartLoc, EndLoc)) return true; // Clear previous parse error and return correct expression. Parser.clearPendingErrors(); diff --git a/lib/Target/X86/MCTargetDesc/X86MCExpr.h b/lib/Target/X86/MCTargetDesc/X86MCExpr.h index f1438cd24960..1070f70468fa 100644 --- a/lib/Target/X86/MCTargetDesc/X86MCExpr.h +++ b/lib/Target/X86/MCTargetDesc/X86MCExpr.h @@ -48,7 +48,7 @@ public: /// @} void printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const override { - if (MAI->getAssemblerDialect() == 0) + if (!MAI || MAI->getAssemblerDialect() == 0) OS << '%'; OS << X86ATTInstPrinter::getRegisterName(RegNo); } @@ -59,6 +59,11 @@ public: } // Register values should be inlined as they are not valid .set expressions. bool inlineAssignedExpr() const override { return true; } + bool isEqualTo(const MCExpr *X) const override { + if (auto *E = dyn_cast<X86MCExpr>(X)) + return getRegNo() == E->getRegNo(); + return false; + } void visitUsedExpr(MCStreamer &Streamer) const override{}; MCFragment *findAssociatedFragment() const override { return nullptr; } diff --git a/lib/Transforms/Utils/BypassSlowDivision.cpp b/lib/Transforms/Utils/BypassSlowDivision.cpp index 05512a6dff3e..e7828af648a9 100644 --- a/lib/Transforms/Utils/BypassSlowDivision.cpp +++ b/lib/Transforms/Utils/BypassSlowDivision.cpp @@ -388,6 +388,15 @@ Optional<QuotRemPair> FastDivInsertionTask::insertFastDivAndRem() { return None; } + // After Constant Hoisting pass, long constants may be represented as + // bitcast instructions. As a result, some constants may look like an + // instruction at first, and an additional check is necessary to find out if + // an operand is actually a constant. + if (auto *BCI = dyn_cast<BitCastInst>(Divisor)) + if (BCI->getParent() == SlowDivOrRem->getParent() && + isa<ConstantInt>(BCI->getOperand(0))) + return None; + if (DividendShort && !isSignedOp()) { // If the division is unsigned and Dividend is known to be short, then // either diff --git a/test/CodeGen/AArch64/GlobalISel/irtranslator-duplicate-types-param.ll b/test/CodeGen/AArch64/GlobalISel/irtranslator-duplicate-types-param.ll new file mode 100644 index 000000000000..c20b855c8e7a --- /dev/null +++ b/test/CodeGen/AArch64/GlobalISel/irtranslator-duplicate-types-param.ll @@ -0,0 +1,15 @@ +; RUN: llc -O0 -o - -verify-machineinstrs %s | FileCheck %s +target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" +target triple = "aarch64-unknown-linux-gnu" + +; Check we don't crash due to encountering the same struct param type twice. +; CHECK-LABEL: param_two_struct +; CHECK: add +; CHECK: ret +define i64 @param_two_struct([2 x i64] %t.coerce, [2 x i64] %s.coerce) { +entry: + %t.coerce.fca.0.extract = extractvalue [2 x i64] %t.coerce, 0 + %s.coerce.fca.1.extract = extractvalue [2 x i64] %s.coerce, 1 + %add = add nsw i64 %s.coerce.fca.1.extract, %t.coerce.fca.0.extract + ret i64 %add +} diff --git a/test/CodeGen/PowerPC/uwtables.ll b/test/CodeGen/PowerPC/uwtables.ll new file mode 100644 index 000000000000..1968b715a1b3 --- /dev/null +++ b/test/CodeGen/PowerPC/uwtables.ll @@ -0,0 +1,51 @@ +; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \ +; RUN: -verify-machineinstrs -ppc-asm-full-reg-names \ +; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s +; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \ +; RUN: -verify-machineinstrs -ppc-asm-full-reg-names \ +; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s +; RUN: llc -mtriple=powerpc64-unknown-unknown \ +; RUN: -verify-machineinstrs -ppc-asm-full-reg-names \ +; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s + + +@_ZTIi = external constant i8* + +; Function is marked as nounwind but it still throws with __cxa_throw and +; calls __cxa_call_unexpected. +; Need to make sure that we do not only have a debug frame. +; Function Attrs: noreturn nounwind +define void @_Z4funcv() local_unnamed_addr #0 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +entry: + %exception = tail call i8* @__cxa_allocate_exception(i64 4) + %0 = bitcast i8* %exception to i32* + store i32 100, i32* %0, align 16 + invoke void @__cxa_throw(i8* %exception, i8* bitcast (i8** @_ZTIi to i8*), i8* null) + to label %unreachable unwind label %lpad + +lpad: ; preds = %entry + %1 = landingpad { i8*, i32 } + filter [0 x i8*] zeroinitializer + %2 = extractvalue { i8*, i32 } %1, 0 + tail call void @__cxa_call_unexpected(i8* %2) + unreachable + +unreachable: ; preds = %entry + unreachable +; CHECK-LABEL: _Z4funcv +; CHECK-NOT: .debug_frame +; CHECK: .cfi_personality +; CHECK: .cfi_endproc +} + +declare i8* @__cxa_allocate_exception(i64) local_unnamed_addr + +declare void @__cxa_throw(i8*, i8*, i8*) local_unnamed_addr + +declare i32 @__gxx_personality_v0(...) + +declare void @__cxa_call_unexpected(i8*) local_unnamed_addr + + +attributes #0 = { noreturn nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" } + diff --git a/test/CodeGen/X86/divide-by-constant.ll b/test/CodeGen/X86/divide-by-constant.ll index cc2dc1b1d094..0dbb215a1bff 100644 --- a/test/CodeGen/X86/divide-by-constant.ll +++ b/test/CodeGen/X86/divide-by-constant.ll @@ -330,3 +330,113 @@ entry: %div = udiv i64 %rem, 7 ret i64 %div } + +define { i64, i32 } @PR38622(i64) nounwind { +; X32-LABEL: PR38622: +; X32: # %bb.0: +; X32-NEXT: pushl %ebp +; X32-NEXT: pushl %ebx +; X32-NEXT: pushl %edi +; X32-NEXT: pushl %esi +; X32-NEXT: subl $12, %esp +; X32-NEXT: movl {{[0-9]+}}(%esp), %ebx +; X32-NEXT: movl {{[0-9]+}}(%esp), %ebp +; X32-NEXT: pushl $0 +; X32-NEXT: pushl $-294967296 # imm = 0xEE6B2800 +; X32-NEXT: pushl %ebp +; X32-NEXT: pushl %ebx +; X32-NEXT: calll __udivdi3 +; X32-NEXT: addl $16, %esp +; X32-NEXT: movl %eax, %esi +; X32-NEXT: movl %edx, %edi +; X32-NEXT: pushl $0 +; X32-NEXT: pushl $-294967296 # imm = 0xEE6B2800 +; X32-NEXT: pushl %ebp +; X32-NEXT: pushl %ebx +; X32-NEXT: calll __umoddi3 +; X32-NEXT: addl $16, %esp +; X32-NEXT: movl %eax, %ecx +; X32-NEXT: movl %esi, %eax +; X32-NEXT: movl %edi, %edx +; X32-NEXT: addl $12, %esp +; X32-NEXT: popl %esi +; X32-NEXT: popl %edi +; X32-NEXT: popl %ebx +; X32-NEXT: popl %ebp +; X32-NEXT: retl +; +; X64-LABEL: PR38622: +; X64: # %bb.0: +; X64-NEXT: movq %rdi, %rax +; X64-NEXT: shrq $11, %rax +; X64-NEXT: movabsq $4835703278458517, %rcx # imm = 0x112E0BE826D695 +; X64-NEXT: mulq %rcx +; X64-NEXT: shrq $9, %rdx +; X64-NEXT: imull $-294967296, %edx, %eax # imm = 0xEE6B2800 +; X64-NEXT: subl %eax, %edi +; X64-NEXT: movq %rdx, %rax +; X64-NEXT: movl %edi, %edx +; X64-NEXT: retq + %2 = udiv i64 %0, 4000000000 + %3 = urem i64 %0, 4000000000 + %4 = trunc i64 %3 to i32 + %5 = insertvalue { i64, i32 } undef, i64 %2, 0 + %6 = insertvalue { i64, i32 } %5, i32 %4, 1 + ret { i64, i32 } %6 +} + +define { i64, i32 } @PR38622_signed(i64) nounwind { +; X32-LABEL: PR38622_signed: +; X32: # %bb.0: +; X32-NEXT: pushl %ebp +; X32-NEXT: pushl %ebx +; X32-NEXT: pushl %edi +; X32-NEXT: pushl %esi +; X32-NEXT: subl $12, %esp +; X32-NEXT: movl {{[0-9]+}}(%esp), %ebx +; X32-NEXT: movl {{[0-9]+}}(%esp), %ebp +; X32-NEXT: pushl $0 +; X32-NEXT: pushl $-294967296 # imm = 0xEE6B2800 +; X32-NEXT: pushl %ebp +; X32-NEXT: pushl %ebx +; X32-NEXT: calll __divdi3 +; X32-NEXT: addl $16, %esp +; X32-NEXT: movl %eax, %esi +; X32-NEXT: movl %edx, %edi +; X32-NEXT: pushl $0 +; X32-NEXT: pushl $-294967296 # imm = 0xEE6B2800 +; X32-NEXT: pushl %ebp +; X32-NEXT: pushl %ebx +; X32-NEXT: calll __moddi3 +; X32-NEXT: addl $16, %esp +; X32-NEXT: movl %eax, %ecx +; X32-NEXT: movl %esi, %eax +; X32-NEXT: movl %edi, %edx +; X32-NEXT: addl $12, %esp +; X32-NEXT: popl %esi +; X32-NEXT: popl %edi +; X32-NEXT: popl %ebx +; X32-NEXT: popl %ebp +; X32-NEXT: retl +; +; X64-LABEL: PR38622_signed: +; X64: # %bb.0: +; X64-NEXT: movabsq $1237940039285380275, %rcx # imm = 0x112E0BE826D694B3 +; X64-NEXT: movq %rdi, %rax +; X64-NEXT: imulq %rcx +; X64-NEXT: movq %rdx, %rcx +; X64-NEXT: shrq $63, %rcx +; X64-NEXT: sarq $28, %rdx +; X64-NEXT: leaq (%rdx,%rcx), %rax +; X64-NEXT: addl %ecx, %edx +; X64-NEXT: imull $-294967296, %edx, %ecx # imm = 0xEE6B2800 +; X64-NEXT: subl %ecx, %edi +; X64-NEXT: movl %edi, %edx +; X64-NEXT: retq + %2 = sdiv i64 %0, 4000000000 + %3 = srem i64 %0, 4000000000 + %4 = trunc i64 %3 to i32 + %5 = insertvalue { i64, i32 } undef, i64 %2, 0 + %6 = insertvalue { i64, i32 } %5, i32 %4, 1 + ret { i64, i32 } %6 +} diff --git a/test/CodeGen/X86/uwtables.ll b/test/CodeGen/X86/uwtables.ll new file mode 100644 index 000000000000..d25492dfe5f1 --- /dev/null +++ b/test/CodeGen/X86/uwtables.ll @@ -0,0 +1,43 @@ +; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s + + +@_ZTIi = external constant i8* + +; Function is marked as nounwind but it still throws with __cxa_throw and +; calls __cxa_call_unexpected. +; Need to make sure that we do not only have a debug frame. +; Function Attrs: noreturn nounwind +define void @_Z4funcv() local_unnamed_addr #0 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +entry: + %exception = tail call i8* @__cxa_allocate_exception(i64 4) + %0 = bitcast i8* %exception to i32* + store i32 100, i32* %0, align 16 + invoke void @__cxa_throw(i8* %exception, i8* bitcast (i8** @_ZTIi to i8*), i8* null) + to label %unreachable unwind label %lpad + +lpad: ; preds = %entry + %1 = landingpad { i8*, i32 } + filter [0 x i8*] zeroinitializer + %2 = extractvalue { i8*, i32 } %1, 0 + tail call void @__cxa_call_unexpected(i8* %2) + unreachable + +unreachable: ; preds = %entry + unreachable +; CHECK-LABEL: _Z4funcv +; CHECK-NOT: .debug_frame +; CHECK: .cfi_personality +; CHECK: .cfi_endproc +} + +declare i8* @__cxa_allocate_exception(i64) local_unnamed_addr + +declare void @__cxa_throw(i8*, i8*, i8*) local_unnamed_addr + +declare i32 @__gxx_personality_v0(...) + +declare void @__cxa_call_unexpected(i8*) local_unnamed_addr + + +attributes #0 = { noreturn nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+vsx,-power9-vector,-qpx" "unsafe-fp-math"="false" "use-soft-float"="false" } + diff --git a/test/CodeGen/X86/x86-shrink-wrap-unwind.ll b/test/CodeGen/X86/x86-shrink-wrap-unwind.ll index bac8393b3ec0..f1f81da926de 100644 --- a/test/CodeGen/X86/x86-shrink-wrap-unwind.ll +++ b/test/CodeGen/X86/x86-shrink-wrap-unwind.ll @@ -237,6 +237,7 @@ attributes #5 = { nounwind readonly ssp uwtable "split-stack" } ; CHECK: push ; ; Jump to throw_exception: +; CHECK-NEXT: .cfi_def_cfa_offset ; CHECK-NEXT: testb $1, %dil ; CHECK-NEXT: jne [[THROW_LABEL:LBB[0-9_]+]] ; Else return exit diff --git a/test/MC/AArch64/SVE/system-regs-diagnostics.s b/test/MC/AArch64/SVE/system-regs-diagnostics.s new file mode 100644 index 000000000000..4fd83f78071f --- /dev/null +++ b/test/MC/AArch64/SVE/system-regs-diagnostics.s @@ -0,0 +1,51 @@ +// RUN: not llvm-mc -triple aarch64 -mattr=+sve -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-SVE +// RUN: not llvm-mc -triple aarch64 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NOSVE + + +// --------------------------------------------------------------------------// +// ID_AA64ZFR0_EL1 is read-only + +msr ID_AA64ZFR0_EL1, x3 +// CHECK-SVE: error: expected writable system register or pstate +// CHECK-SVE-NEXT: msr ID_AA64ZFR0_EL1, x3 + + +// --------------------------------------------------------------------------// +// Check that the other SVE registers are only readable/writable when +// the +sve attribute is set. + +mrs x3, ID_AA64ZFR0_EL1 +// CHECK-NOSVE: error: expected readable system register +// CHECK-NOSVE: mrs x3, ID_AA64ZFR0_EL1 + +mrs x3, ZCR_EL1 +// CHECK-NOSVE: error: expected readable system register +// CHECK-NOSVE-NEXT: mrs x3, ZCR_EL1 + +mrs x3, ZCR_EL2 +// CHECK-NOSVE: error: expected readable system register +// CHECK-NOSVE-NEXT: mrs x3, ZCR_EL2 + +mrs x3, ZCR_EL3 +// CHECK-NOSVE: error: expected readable system register +// CHECK-NOSVE-NEXT: mrs x3, ZCR_EL3 + +mrs x3, ZCR_EL12 +// CHECK-NOSVE: error: expected readable system register +// CHECK-NOSVE-NEXT: mrs x3, ZCR_EL12 + +msr ZCR_EL1, x3 +// CHECK-NOSVE: error: expected writable system register or pstate +// CHECK-NOSVE-NEXT: msr ZCR_EL1, x3 + +msr ZCR_EL2, x3 +// CHECK-NOSVE: error: expected writable system register or pstate +// CHECK-NOSVE-NEXT: msr ZCR_EL2, x3 + +msr ZCR_EL3, x3 +// CHECK-NOSVE: error: expected writable system register or pstate +// CHECK-NOSVE-NEXT: msr ZCR_EL3, x3 + +msr ZCR_EL12, x3 +// CHECK-NOSVE: error: expected writable system register or pstate +// CHECK-NOSVE-NEXT: msr ZCR_EL12, x3 diff --git a/test/MC/AArch64/SVE/system-regs.s b/test/MC/AArch64/SVE/system-regs.s new file mode 100644 index 000000000000..17829ebdaaca --- /dev/null +++ b/test/MC/AArch64/SVE/system-regs.s @@ -0,0 +1,62 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +mrs x3, ID_AA64ZFR0_EL1 +// CHECK-INST: mrs x3, ID_AA64ZFR0_EL1 +// CHECK-ENCODING: [0x83,0x04,0x38,0xd5] +// CHECK-ERROR: expected readable system register +// CHECK-UNKNOWN: 83 04 38 d5 mrs x3, S3_0_C0_C4_4 + +mrs x3, ZCR_EL1 +// CHECK-INST: mrs x3, ZCR_EL1 +// CHECK-ENCODING: [0x03,0x12,0x38,0xd5] +// CHECK-ERROR: expected readable system register +// CHECK-UNKNOWN: 03 12 38 d5 mrs x3, S3_0_C1_C2_0 + +mrs x3, ZCR_EL2 +// CHECK-INST: mrs x3, ZCR_EL2 +// CHECK-ENCODING: [0x03,0x12,0x3c,0xd5] +// CHECK-ERROR: expected readable system register +// CHECK-UNKNOWN: 03 12 3c d5 mrs x3, S3_4_C1_C2_0 + +mrs x3, ZCR_EL3 +// CHECK-INST: mrs x3, ZCR_EL3 +// CHECK-ENCODING: [0x03,0x12,0x3e,0xd5] +// CHECK-ERROR: expected readable system register +// CHECK-UNKNOWN: 03 12 3e d5 mrs x3, S3_6_C1_C2_0 + +mrs x3, ZCR_EL12 +// CHECK-INST: mrs x3, ZCR_EL12 +// CHECK-ENCODING: [0x03,0x12,0x3d,0xd5] +// CHECK-ERROR: expected readable system register +// CHECK-UNKNOWN: 03 12 3d d5 mrs x3, S3_5_C1_C2_0 + +msr ZCR_EL1, x3 +// CHECK-INST: msr ZCR_EL1, x3 +// CHECK-ENCODING: [0x03,0x12,0x18,0xd5] +// CHECK-ERROR: expected writable system register or pstate +// CHECK-UNKNOWN: 03 12 18 d5 msr S3_0_C1_C2_0, x3 + +msr ZCR_EL2, x3 +// CHECK-INST: msr ZCR_EL2, x3 +// CHECK-ENCODING: [0x03,0x12,0x1c,0xd5] +// CHECK-ERROR: expected writable system register or pstate +// CHECK-UNKNOWN: 03 12 1c d5 msr S3_4_C1_C2_0, x3 + +msr ZCR_EL3, x3 +// CHECK-INST: msr ZCR_EL3, x3 +// CHECK-ENCODING: [0x03,0x12,0x1e,0xd5] +// CHECK-ERROR: expected writable system register or pstate +// CHECK-UNKNOWN: 03 12 1e d5 msr S3_6_C1_C2_0, x3 + +msr ZCR_EL12, x3 +// CHECK-INST: msr ZCR_EL12, x3 +// CHECK-ENCODING: [0x03,0x12,0x1d,0xd5] +// CHECK-ERROR: expected writable system register or pstate +// CHECK-UNKNOWN: 03 12 1d d5 msr S3_5_C1_C2_0, x3 diff --git a/test/MC/X86/pr37425.s b/test/MC/X86/pr37425.s index 965d56ea1c5f..2cfa5e98a392 100644 --- a/test/MC/X86/pr37425.s +++ b/test/MC/X86/pr37425.s @@ -1,5 +1,4 @@ -// RUN: llvm-mc -triple x86_64-unknown-unknown -defsym=ERR=0 %s -o - | FileCheck %s -// RUN: not llvm-mc -triple x86_64-unknown-unknown -defsym=ERR=1 %s -o - 2>&1 | FileCheck --check-prefix=ERR %s +// RUN: llvm-mc -triple x86_64-unknown-unknown %s -o - | FileCheck %s // CHECK-NOT: .set var_xdata var_xdata = %rcx @@ -7,10 +6,15 @@ var_xdata = %rcx // CHECK: xorq %rcx, %rcx xorq var_xdata, var_xdata -.if (ERR==1) -// ERR: [[@LINE+2]]:15: error: unknown token in expression in '.set' directive -// ERR: [[@LINE+1]]:15: error: missing expression in '.set' directive -.set err_var, %rcx -.endif +// CHECK: .data +// CHECK-NEXT: .byte 1 +.data +.if var_xdata == %rax + .byte 0 +.elseif var_xdata == %rcx + .byte 1 +.else + .byte 2 +.endif diff --git a/test/Transforms/CodeGenPrepare/X86/multi-extension.ll b/test/Transforms/CodeGenPrepare/X86/multi-extension.ll new file mode 100644 index 000000000000..950f9f2e04ab --- /dev/null +++ b/test/Transforms/CodeGenPrepare/X86/multi-extension.ll @@ -0,0 +1,25 @@ +; RUN: opt < %s -codegenprepare -S -mtriple=x86_64-unknown-unknown | FileCheck %s +target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.13.0" + +declare void @bar(i64) + +@b = global i16 0, align 2 + +; This test case is extracted from PR38125. +; %or is reachable by both a sext and zext that are going to be promoted. +; It ensures correct operation on PromotedInsts. + +; CHECK: %promoted = trunc i32 %or to i16 +; CHECK-NEXT: %c = sext i16 %promoted to i64 +define i32 @foo(i16 %kkk) { +entry: + %t4 = load i16, i16* @b, align 2 + %conv4 = zext i16 %t4 to i32 + %or = or i16 %kkk, %t4 + %c = sext i16 %or to i64 + call void @bar(i64 %c) + %t5 = and i16 %or, 5 + %z = zext i16 %t5 to i32 + ret i32 %z +} diff --git a/utils/lit/tests/Inputs/shtest-format/lit.cfg b/utils/lit/tests/Inputs/shtest-format/lit.cfg index 607538e901a2..38c3da3d3cd9 100644 --- a/utils/lit/tests/Inputs/shtest-format/lit.cfg +++ b/utils/lit/tests/Inputs/shtest-format/lit.cfg @@ -6,4 +6,4 @@ config.test_source_root = None config.test_exec_root = None config.target_triple = 'x86_64-unknown-unknown' config.available_features.add('a-present-feature') -config.substitutions.append(('%{python}', "'%s'" % (sys.executable))) +config.substitutions.append(('%{python}', '"%s"' % (sys.executable))) |