diff options
40 files changed, 1765 insertions, 562 deletions
@@ -31,6 +31,11 @@ NOTE TO PEOPLE WHO THINK THAT FreeBSD 11.x IS SLOW: disable the most expensive debugging functionality run "ln -s 'abort:false,junk:false' /etc/malloc.conf".) +20160113: + With the addition of ypldap(8), a new _ypldap user is now required + during installworld. "mergemaster -p" can be used to add the user + prior to installworld, as documented in the handbook. + 20151216: The tftp loader (pxeboot) now uses the option root-path directive. As a consequence it no longer looks for a pxeboot.4th file on the tftp diff --git a/etc/master.passwd b/etc/master.passwd index f2a4523131c1..fc7fef59438b 100644 --- a/etc/master.passwd +++ b/etc/master.passwd @@ -22,5 +22,6 @@ uucp:*:66:66::0:0:UUCP pseudo-user:/var/spool/uucppublic:/usr/local/libexec/uucp pop:*:68:6::0:0:Post Office Owner:/nonexistent:/usr/sbin/nologin auditdistd:*:78:77::0:0:Auditdistd unprivileged user:/var/empty:/usr/sbin/nologin www:*:80:80::0:0:World Wide Web Owner:/nonexistent:/usr/sbin/nologin +_ypldap:*:93:93::0:0:YP Ldap unprivileged user:/var/empty:/usr/sbin/nologin hast:*:845:845::0:0:HAST unprivileged user:/var/empty:/usr/sbin/nologin nobody:*:65534:65534::0:0:Unprivileged user:/nonexistent:/usr/sbin/nologin diff --git a/lib/libc/sys/futimens.c b/lib/libc/sys/futimens.c index 2014cc5cecf3..59fb37f5249a 100644 --- a/lib/libc/sys/futimens.c +++ b/lib/libc/sys/futimens.c @@ -42,8 +42,11 @@ futimens(int fd, const struct timespec times[2]) { struct timeval now, tv[2], *tvp; struct stat sb; + int osreldate; - if (__getosreldate() >= 1100056) + osreldate = __getosreldate(); + if (osreldate >= 1100056 || + (osreldate >= 1002506 && osreldate < 1100000)) return (__sys_futimens(fd, times)); if (times == NULL || (times[0].tv_nsec == UTIME_NOW && diff --git a/lib/libc/sys/utimensat.2 b/lib/libc/sys/utimensat.2 index 0f397c6a99aa..57ad904206ed 100644 --- a/lib/libc/sys/utimensat.2 +++ b/lib/libc/sys/utimensat.2 @@ -31,7 +31,7 @@ .\" @(#)utimes.2 8.1 (Berkeley) 6/4/93 .\" $FreeBSD$ .\" -.Dd January 23, 2015 +.Dd January 12, 2016 .Dt UTIMENSAT 2 .Os .Sh NAME @@ -289,4 +289,4 @@ The and .Fn utimensat system calls appeared in -.Fx 11.0 . +.Fx 10.3 . diff --git a/lib/libc/sys/utimensat.c b/lib/libc/sys/utimensat.c index 67d19cb2f9ba..a1c3c211fe95 100644 --- a/lib/libc/sys/utimensat.c +++ b/lib/libc/sys/utimensat.c @@ -42,8 +42,11 @@ utimensat(int fd, const char *path, const struct timespec times[2], int flag) { struct timeval now, tv[2], *tvp; struct stat sb; + int osreldate; - if (__getosreldate() >= 1100056) + osreldate = __getosreldate(); + if (osreldate >= 1100056 || + (osreldate >= 1002506 && osreldate < 1100000)) return (__sys_utimensat(fd, path, times, flag)); if ((flag & ~AT_SYMLINK_NOFOLLOW) != 0) { diff --git a/share/examples/ypldap/ypldap.conf b/share/examples/ypldap/ypldap.conf new file mode 100644 index 000000000000..83d25ac60ba8 --- /dev/null +++ b/share/examples/ypldap/ypldap.conf @@ -0,0 +1,40 @@ +$FreeBSD$ +domain "freebsd.org" +interval 60 +provide map "passwd.byname" +provide map "passwd.byuid" +provide map "group.byname" +provide map "group.bygid" +provide map "netid.byname" + +directory "127.0.0.1" { + # directory options + binddn "cn=ldap,dc=freebsd,dc=org" + bindcred "secret" + basedn "dc=freebsd.,dc=org" + # starting point for groups directory search, default to basedn + groupdn "ou=Groups,dc=freebsd,dc=org" + + # passwd maps configuration (RFC 2307 posixAccount object class) + passwd filter "(objectClass=posixAccount)" + + attribute name maps to "uid" + fixed attribute passwd "*" + attribute uid maps to "uidNumber" + attribute gid maps to "gidNumber" + attribute gecos maps to "cn" + attribute home maps to "homeDirectory" + attribute shell maps to "loginShell" + fixed attribute change "0" + fixed attribute expire "0" + fixed attribute class "" + + # group maps configuration (RFC 2307 posixGroup object class) + group filter "(objectClass=posixGroup)" + + attribute groupname maps to "cn" + fixed attribute grouppasswd "*" + attribute groupgid maps to "gidNumber" + # memberUid returns multiple group members + list groupmembers maps to "memberUid" +} diff --git a/share/man/man4/uart.4 b/share/man/man4/uart.4 index 3fca2f89de8b..138e04924196 100644 --- a/share/man/man4/uart.4 +++ b/share/man/man4/uart.4 @@ -25,7 +25,7 @@ .\" .\" $FreeBSD$ .\" -.Dd August 10, 2015 +.Dd December 9, 2015 .Dt UART 4 .Os .Sh NAME @@ -160,7 +160,9 @@ The API, accessed via is available on the tty device. To use the PPS capture feature with .Xr ntpd 8 , -symlink the tty device to +symlink the tty callout device +.Va /dev/cuau? +to .Va /dev/pps0. .Pp The @@ -175,15 +177,54 @@ it can be set in .Xr loader.conf 5 or .Xr sysctl.conf 5 . +.Pp The following capture modes are available: .Bl -tag -compact -offset "mmmm" -width "mmmm" -.It 0 +.It 0x00 Capture disabled. -.It 1 +.It 0x01 Capture pulses on the CTS line. -.It 2 -Capture pulses on the DCD line (default). +.It 0x02 +Capture pulses on the DCD line. +.El +.Pp +The following values may be ORed with the capture mode to configure +capture processing options: +.Bl -tag -compact -offset "mmmm" -width "mmmm" +.It 0x10 +Invert the pulse (RS-232 logic low = ASSERT, high = CLEAR). +.It 0x20 +Attempt to capture narrow pulses. .El +.Pp +Add the narrow pulse option when the incoming PPS pulse width is small +enough to prevent reliable capture in normal mode. +In narrow mode the driver uses the hardware's ability to latch a line +state change; not all hardware has this capability. +The hardware latch provides a reliable indication that a pulse occurred, +but prevents distinguishing between the CLEAR and ASSERT edges of the pulse. +For each detected pulse, the driver synthesizes both an ASSERT and a CLEAR +event, using the same timestamp for each. +To prevent spurious events when the hardware is intermittently able to +see both edges of a pulse, the driver will not generate a new pair of +events within a half second of the prior pair. +Both normal and narrow pulse modes work with +.Xr ntpd 8 . +.Pp +Add the invert option when the connection to the uart device uses TTL +level signals, or when the PPS source emits inverted pulses. +RFC 2783 defines an ASSERT event as a higher-voltage line level, and a CLEAR +event as a lower-voltage line level, in the context of the RS-232 protocol. +The modem control signals on a TTL-level connection are typically +inverted from the RS-232 levels. +For example, carrier presence is indicated by a high signal on an RS-232 +DCD line, and by a low signal on a TTL DCD line. +This is due to the use of inverting line driver buffers to convert between +TTL and RS-232 line levels in most hardware designs. +Generally speaking, a connection to a DB-9 style connector is an RS-232 +level signal at up to 12 volts. +A connection to header pins or an edge-connector on an embedded board +is typically a TTL signal at 3.3 or 5 volts. .Sh FILES .Bl -tag -width ".Pa /dev/ttyu?.init" -compact .It Pa /dev/ttyu? diff --git a/sys/arm/arm/pmap-v6-new.c b/sys/arm/arm/pmap-v6-new.c index 5d7e5711d05c..9a756cfd94ab 100644 --- a/sys/arm/arm/pmap-v6-new.c +++ b/sys/arm/arm/pmap-v6-new.c @@ -1109,7 +1109,7 @@ pmap_bootstrap(vm_offset_t firstaddr) * mapping of pages. */ #define SYSMAP(c, p, v, n) do { \ - v = (c)pmap_preboot_reserve_pages(1); \ + v = (c)pmap_preboot_reserve_pages(n); \ p = pt2map_entry((vm_offset_t)v); \ } while (0) diff --git a/sys/boot/efi/libefi/libefi.c b/sys/boot/efi/libefi/libefi.c index 0c24c6d64a72..f87b89acb2bc 100644 --- a/sys/boot/efi/libefi/libefi.c +++ b/sys/boot/efi/libefi/libefi.c @@ -179,7 +179,7 @@ efi_main(EFI_HANDLE image_handle, EFI_SYSTEM_TABLE *system_table) argv = malloc((argc + 1) * sizeof(CHAR16*)); argc = 0; if (addprog) - argv[argc++] = (CHAR16 *)"loader.efi"; + argv[argc++] = (CHAR16 *)L"loader.efi"; argp = args; while (argp != NULL && *argp != 0) { argp = arg_skipsep(argp); diff --git a/sys/boot/uboot/lib/copy.c b/sys/boot/uboot/lib/copy.c index c0e8b81290bc..131b88d85861 100644 --- a/sys/boot/uboot/lib/copy.c +++ b/sys/boot/uboot/lib/copy.c @@ -100,7 +100,7 @@ uboot_loadaddr(u_int type, void *data, uint64_t addr) biggest_block = 0; biggest_size = 0; - subldr = rounddown2((uint64_t)(uintptr_t)_start, KERN_ALIGN); + subldr = rounddown2((uintptr_t)_start, KERN_ALIGN); eubldr = roundup2((uint64_t)uboot_heap_end, KERN_ALIGN); for (i = 0; i < si->mr_no; i++) { if (si->mr[i].flags != MR_ATTR_DRAM) diff --git a/sys/dev/sfxge/common/efx.h b/sys/dev/sfxge/common/efx.h index 7eee1c3bc1d8..f7ff65d49317 100644 --- a/sys/dev/sfxge/common/efx.h +++ b/sys/dev/sfxge/common/efx.h @@ -505,13 +505,6 @@ efx_mac_fcntl_get( __out unsigned int *fcntl_wantedp, __out unsigned int *fcntl_linkp); -#define EFX_MAC_HASH_BITS (1 << 8) - -extern __checkReturn efx_rc_t -efx_mac_hash_set( - __in efx_nic_t *enp, - __in_ecount(EFX_MAC_HASH_BITS) unsigned int const *bucket); - #if EFSYS_OPT_MAC_STATS @@ -1923,8 +1916,6 @@ efx_psuedo_hdr_pkt_length_get( typedef enum efx_rxq_type_e { EFX_RXQ_TYPE_DEFAULT, - EFX_RXQ_TYPE_SPLIT_HEADER, - EFX_RXQ_TYPE_SPLIT_PAYLOAD, EFX_RXQ_TYPE_SCATTER, EFX_RXQ_NTYPES } efx_rxq_type_t; diff --git a/sys/dev/sfxge/common/efx_check.h b/sys/dev/sfxge/common/efx_check.h index 80119c5cf451..eab4f4b191d2 100644 --- a/sys/dev/sfxge/common/efx_check.h +++ b/sys/dev/sfxge/common/efx_check.h @@ -61,9 +61,6 @@ /* Decode fatal errors */ #if EFSYS_OPT_DECODE_INTR_FATAL # if !(EFSYS_OPT_FALCON || EFSYS_OPT_SIENA) -# if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) -# error "INTR_FATAL not supported on HUNTINGTON or MEDFORD" -# endif # error "INTR_FATAL requires FALCON or SIENA" # endif #endif /* EFSYS_OPT_DECODE_INTR_FATAL */ @@ -138,9 +135,6 @@ /* Support management controller messages */ #if EFSYS_OPT_MCDI # if !(EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) -# if EFSYS_OPT_FALCON -# error "MCDI not supported on FALCON" -# endif # error "MCDI requires SIENA or HUNTINGTON or MEDFORD" # endif #endif /* EFSYS_OPT_MCDI */ @@ -186,14 +180,14 @@ # endif #endif /* EFSYS_OPT_MON_NULL */ -/* Support Siena monitor */ +/* Obsolete option */ #ifdef EFSYS_OPT_MON_SIENA -# error "MON_SIENA is obsolete use MON_MCDI" +# error "MON_SIENA is obsolete (replaced by MON_MCDI)." #endif /* EFSYS_OPT_MON_SIENA*/ -/* Support Huntington monitor */ +/* Obsolete option */ #ifdef EFSYS_OPT_MON_HUNTINGTON -# error "MON_HUNTINGTON is obsolete use MON_MCDI" +# error "MON_HUNTINGTON is obsolete (replaced by MON_MCDI)." #endif /* EFSYS_OPT_MON_HUNTINGTON*/ /* Support monitor statistics (voltage/temperature) */ @@ -265,9 +259,9 @@ # endif #endif /* EFSYS_OPT_PCIE_TUNE */ -/* Support PHY BIST diagnostics */ +/* Obsolete option */ #if EFSYS_OPT_PHY_BIST -# error "PHY_BIST is obsolete. It has been replaced by the BIST option." +# error "PHY_BIST is obsolete (replaced by BIST)." #endif /* EFSYS_OPT_PHY_BIST */ /* Support PHY flags */ @@ -379,7 +373,7 @@ /* Obsolete option */ #ifdef EFSYS_OPT_STAT_NAME -# error "EFSYS_OPT_STAT_NAME is obsolete (replaced by EFSYS_OPT_NAMES)." +# error "STAT_NAME is obsolete (replaced by NAMES)." #endif /* Support PCI Vital Product Data (VPD) */ @@ -399,7 +393,7 @@ /* Obsolete option */ #ifdef EFSYS_OPT_MCAST_FILTER_LIST -# error "MCAST_FILTER_LIST is obsolete and not supported" +# error "MCAST_FILTER_LIST is obsolete and is not supported" #endif /* EFSYS_OPT_MCAST_FILTER_LIST */ /* Support BIST */ diff --git a/sys/dev/sfxge/common/efx_filter.c b/sys/dev/sfxge/common/efx_filter.c index 9841715e317e..93cf540539bc 100644 --- a/sys/dev/sfxge/common/efx_filter.c +++ b/sys/dev/sfxge/common/efx_filter.c @@ -97,17 +97,17 @@ static efx_filter_ops_t __efx_filter_siena_ops = { }; #endif /* EFSYS_OPT_SIENA */ -#if EFSYS_OPT_HUNTINGTON -static efx_filter_ops_t __efx_filter_hunt_ops = { - hunt_filter_init, /* efo_init */ - hunt_filter_fini, /* efo_fini */ - hunt_filter_restore, /* efo_restore */ - hunt_filter_add, /* efo_add */ - hunt_filter_delete, /* efo_delete */ - hunt_filter_supported_filters, /* efo_supported_filters */ - hunt_filter_reconfigure, /* efo_reconfigure */ +#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD +static efx_filter_ops_t __efx_filter_ef10_ops = { + ef10_filter_init, /* efo_init */ + ef10_filter_fini, /* efo_fini */ + ef10_filter_restore, /* efo_restore */ + ef10_filter_add, /* efo_add */ + ef10_filter_delete, /* efo_delete */ + ef10_filter_supported_filters, /* efo_supported_filters */ + ef10_filter_reconfigure, /* efo_reconfigure */ }; -#endif /* EFSYS_OPT_HUNTINGTON */ +#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */ __checkReturn efx_rc_t efx_filter_insert( @@ -189,10 +189,16 @@ efx_filter_init( #if EFSYS_OPT_HUNTINGTON case EFX_FAMILY_HUNTINGTON: - efop = (efx_filter_ops_t *)&__efx_filter_hunt_ops; + efop = (efx_filter_ops_t *)&__efx_filter_ef10_ops; break; #endif /* EFSYS_OPT_HUNTINGTON */ +#if EFSYS_OPT_MEDFORD + case EFX_FAMILY_MEDFORD: + efop = (efx_filter_ops_t *)&__efx_filter_ef10_ops; + break; +#endif /* EFSYS_OPT_MEDFORD */ + default: EFSYS_ASSERT(0); rc = ENOTSUP; diff --git a/sys/dev/sfxge/common/efx_impl.h b/sys/dev/sfxge/common/efx_impl.h index 0aba6f6e0f44..023479daa15a 100644 --- a/sys/dev/sfxge/common/efx_impl.h +++ b/sys/dev/sfxge/common/efx_impl.h @@ -342,6 +342,10 @@ typedef struct efx_intr_ops_s { void (*eio_disable)(efx_nic_t *); void (*eio_disable_unlocked)(efx_nic_t *); efx_rc_t (*eio_trigger)(efx_nic_t *, unsigned int); + void (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *); + void (*eio_status_message)(efx_nic_t *, unsigned int, + boolean_t *); + void (*eio_fatal)(efx_nic_t *); void (*eio_fini)(efx_nic_t *); } efx_intr_ops_t; @@ -436,9 +440,9 @@ typedef struct efx_filter_s { #if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA falconsiena_filter_t *ef_falconsiena_filter; #endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */ -#if EFSYS_OPT_HUNTINGTON - hunt_filter_table_t *ef_hunt_filter_table; -#endif /* EFSYS_OPT_HUNTINGTON */ +#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD + ef10_filter_table_t *ef_ef10_filter_table; +#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */ } efx_filter_t; extern void diff --git a/sys/dev/sfxge/common/efx_intr.c b/sys/dev/sfxge/common/efx_intr.c index b0eebe877d25..92eb7352d219 100644 --- a/sys/dev/sfxge/common/efx_intr.c +++ b/sys/dev/sfxge/common/efx_intr.c @@ -67,15 +67,27 @@ static void falconsiena_intr_fini( __in efx_nic_t *enp); +static void +falconsiena_intr_status_line( + __in efx_nic_t *enp, + __out boolean_t *fatalp, + __out uint32_t *qmaskp); -static __checkReturn boolean_t -falconsiena_intr_check_fatal( - __in efx_nic_t *enp); +static void +falconsiena_intr_status_message( + __in efx_nic_t *enp, + __in unsigned int message, + __out boolean_t *fatalp); static void falconsiena_intr_fatal( __in efx_nic_t *enp); +static __checkReturn boolean_t +falconsiena_intr_check_fatal( + __in efx_nic_t *enp); + + #endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */ @@ -86,6 +98,9 @@ static efx_intr_ops_t __efx_intr_falcon_ops = { falconsiena_intr_disable, /* eio_disable */ falconsiena_intr_disable_unlocked, /* eio_disable_unlocked */ falconsiena_intr_trigger, /* eio_trigger */ + falconsiena_intr_status_line, /* eio_status_line */ + falconsiena_intr_status_message, /* eio_status_message */ + falconsiena_intr_fatal, /* eio_fatal */ falconsiena_intr_fini, /* eio_fini */ }; #endif /* EFSYS_OPT_FALCON */ @@ -97,6 +112,9 @@ static efx_intr_ops_t __efx_intr_siena_ops = { falconsiena_intr_disable, /* eio_disable */ falconsiena_intr_disable_unlocked, /* eio_disable_unlocked */ falconsiena_intr_trigger, /* eio_trigger */ + falconsiena_intr_status_line, /* eio_status_line */ + falconsiena_intr_status_message, /* eio_status_message */ + falconsiena_intr_fatal, /* eio_fatal */ falconsiena_intr_fini, /* eio_fini */ }; #endif /* EFSYS_OPT_SIENA */ @@ -108,6 +126,9 @@ static efx_intr_ops_t __efx_intr_ef10_ops = { ef10_intr_disable, /* eio_disable */ ef10_intr_disable_unlocked, /* eio_disable_unlocked */ ef10_intr_trigger, /* eio_trigger */ + ef10_intr_status_line, /* eio_status_line */ + ef10_intr_status_message, /* eio_status_message */ + ef10_intr_fatal, /* eio_fatal */ ef10_intr_fini, /* eio_fini */ }; #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */ @@ -261,35 +282,12 @@ efx_intr_status_line( __out uint32_t *qmaskp) { efx_intr_t *eip = &(enp->en_intr); - efx_dword_t dword; + efx_intr_ops_t *eiop = eip->ei_eiop; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); - /* Ensure Huntington and Falcon/Siena ISR at same location */ - EFX_STATIC_ASSERT(FR_BZ_INT_ISR0_REG_OFST == - ER_DZ_BIU_INT_ISR_REG_OFST); - - /* - * Read the queue mask and implicitly acknowledge the - * interrupt. - */ - EFX_BAR_READD(enp, FR_BZ_INT_ISR0_REG, &dword, B_FALSE); - *qmaskp = EFX_DWORD_FIELD(dword, EFX_DWORD_0); - - EFSYS_PROBE1(qmask, uint32_t, *qmaskp); - -#if EFSYS_OPT_HUNTINGTON - if (enp->en_family == EFX_FAMILY_HUNTINGTON) { - /* Huntington reports fatal errors via events */ - *fatalp = B_FALSE; - return; - } -#endif - if (*qmaskp & (1U << eip->ei_level)) - *fatalp = falconsiena_intr_check_fatal(enp); - else - *fatalp = B_FALSE; + eiop->eio_status_line(enp, fatalp, qmaskp); } void @@ -299,39 +297,25 @@ efx_intr_status_message( __out boolean_t *fatalp) { efx_intr_t *eip = &(enp->en_intr); + efx_intr_ops_t *eiop = eip->ei_eiop; EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); -#if EFSYS_OPT_HUNTINGTON - if (enp->en_family == EFX_FAMILY_HUNTINGTON) { - /* Huntington reports fatal errors via events */ - *fatalp = B_FALSE; - return; - } -#endif - if (message == eip->ei_level) - *fatalp = falconsiena_intr_check_fatal(enp); - else - *fatalp = B_FALSE; + eiop->eio_status_message(enp, message, fatalp); } void efx_intr_fatal( __in efx_nic_t *enp) { + efx_intr_t *eip = &(enp->en_intr); + efx_intr_ops_t *eiop = eip->ei_eiop; + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); -#if EFSYS_OPT_HUNTINGTON - if (enp->en_family == EFX_FAMILY_HUNTINGTON) { - /* Huntington reports fatal errors via events */ - return; - } -#endif -#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA - falconsiena_intr_fatal(enp); -#endif + eiop->eio_fatal(enp); } @@ -514,6 +498,51 @@ falconsiena_intr_check_fatal( return (B_FALSE); } +static void +falconsiena_intr_status_line( + __in efx_nic_t *enp, + __out boolean_t *fatalp, + __out uint32_t *qmaskp) +{ + efx_intr_t *eip = &(enp->en_intr); + efx_dword_t dword; + + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); + + /* + * Read the queue mask and implicitly acknowledge the + * interrupt. + */ + EFX_BAR_READD(enp, FR_BZ_INT_ISR0_REG, &dword, B_FALSE); + *qmaskp = EFX_DWORD_FIELD(dword, EFX_DWORD_0); + + EFSYS_PROBE1(qmask, uint32_t, *qmaskp); + + if (*qmaskp & (1U << eip->ei_level)) + *fatalp = falconsiena_intr_check_fatal(enp); + else + *fatalp = B_FALSE; +} + +static void +falconsiena_intr_status_message( + __in efx_nic_t *enp, + __in unsigned int message, + __out boolean_t *fatalp) +{ + efx_intr_t *eip = &(enp->en_intr); + + EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); + EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); + + if (message == eip->ei_level) + *fatalp = falconsiena_intr_check_fatal(enp); + else + *fatalp = B_FALSE; +} + + static void falconsiena_intr_fatal( __in efx_nic_t *enp) diff --git a/sys/dev/sfxge/common/efx_mac.c b/sys/dev/sfxge/common/efx_mac.c index 50f9333ae274..79f8516efd91 100644 --- a/sys/dev/sfxge/common/efx_mac.c +++ b/sys/dev/sfxge/common/efx_mac.c @@ -462,55 +462,6 @@ efx_mac_fcntl_get( *fcntl_wantedp = wanted; } -/* - * FIXME: efx_mac_hash_set() should be deleted once all its callers have been - * updated to use efx_mac_multicast_list_set(). - * Then efx_port_t.ep_multicst_hash could be made Falcon/Siena specific as - * well. - */ - __checkReturn efx_rc_t -efx_mac_hash_set( - __in efx_nic_t *enp, - __in_ecount(EFX_MAC_HASH_BITS) unsigned int const *bucket) -{ - efx_port_t *epp = &(enp->en_port); - efx_mac_ops_t *emop = epp->ep_emop; - efx_oword_t old_hash[2]; - unsigned int index; - efx_rc_t rc; - - EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); - EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT); - - memcpy(old_hash, epp->ep_multicst_hash, sizeof (old_hash)); - - /* Set the lower 128 bits of the hash */ - EFX_ZERO_OWORD(epp->ep_multicst_hash[0]); - for (index = 0; index < 128; index++) { - if (bucket[index] != 0) - EFX_SET_OWORD_BIT(epp->ep_multicst_hash[0], index); - } - - /* Set the upper 128 bits of the hash */ - EFX_ZERO_OWORD(epp->ep_multicst_hash[1]); - for (index = 0; index < 128; index++) { - if (bucket[index + 128] != 0) - EFX_SET_OWORD_BIT(epp->ep_multicst_hash[1], index); - } - - if ((rc = emop->emo_reconfigure(enp)) != 0) - goto fail1; - - return (0); - -fail1: - EFSYS_PROBE1(fail1, efx_rc_t, rc); - - memcpy(epp->ep_multicst_hash, old_hash, sizeof (old_hash)); - - return (rc); -} - __checkReturn efx_rc_t efx_mac_multicast_list_set( __in efx_nic_t *enp, @@ -912,6 +863,8 @@ fail1: #if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA +#define EFX_MAC_HASH_BITS (1 << 8) + /* Compute the multicast hash as used on Falcon and Siena. */ static void falconsiena_mac_multicast_hash_compute( diff --git a/sys/dev/sfxge/common/efx_mcdi.c b/sys/dev/sfxge/common/efx_mcdi.c index e9912d7af957..600da9aeb1a5 100644 --- a/sys/dev/sfxge/common/efx_mcdi.c +++ b/sys/dev/sfxge/common/efx_mcdi.c @@ -643,7 +643,6 @@ efx_mcdi_ev_cpl( efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); const efx_mcdi_transport_t *emtp = enp->en_mcdi.em_emtp; efx_mcdi_ops_t *emcop = enp->en_mcdi.em_emcop; - efx_nic_cfg_t *encp = &enp->en_nic_cfg; efx_mcdi_req_t *emrp; int state; @@ -668,7 +667,7 @@ efx_mcdi_ev_cpl( emip->emi_pending_req = NULL; EFSYS_UNLOCK(enp->en_eslp, state); - if (encp->enc_mcdi_max_payload_length > MCDI_CTL_SDU_LEN_MAX_V1) { + if (emip->emi_max_version >= 2) { /* MCDIv2 response details do not fit into an event. */ efx_mcdi_read_response_header(enp, emrp); } else { diff --git a/sys/dev/sfxge/common/efx_mcdi.h b/sys/dev/sfxge/common/efx_mcdi.h index a9a5c0917745..53f76b32d91c 100644 --- a/sys/dev/sfxge/common/efx_mcdi.h +++ b/sys/dev/sfxge/common/efx_mcdi.h @@ -69,6 +69,7 @@ struct efx_mcdi_req_s { typedef struct efx_mcdi_iface_s { unsigned int emi_port; + unsigned int emi_max_version; unsigned int emi_seq; efx_mcdi_req_t *emi_pending_req; boolean_t emi_ev_cpl; diff --git a/sys/dev/sfxge/common/efx_regs_mcdi.h b/sys/dev/sfxge/common/efx_regs_mcdi.h index db8651e24164..a1d76abe4e0b 100644 --- a/sys/dev/sfxge/common/efx_regs_mcdi.h +++ b/sys/dev/sfxge/common/efx_regs_mcdi.h @@ -299,6 +299,9 @@ * have already installed filters. See the comment at * MC_CMD_WORKAROUND_BUG26807. */ #define MC_CMD_ERR_FILTERS_PRESENT 0x1014 +/* The clock whose frequency you've attempted to set set + * doesn't exist on this NIC */ +#define MC_CMD_ERR_NO_CLOCK 0x1015 #define MC_CMD_ERR_CODE_OFST 0 @@ -318,9 +321,11 @@ /* Point to the copycode entry point. */ #define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4) #define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4) +#define MEDFORD_MC_BOOTROM_COPYCODE_VEC (0x10000 - 3 * 0x4) /* Points to the recovery mode entry point. */ #define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4) #define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4) +#define MEDFORD_MC_BOOTROM_NOFLASH_VEC (0x10000 - 2 * 0x4) /* The command set exported by the boot ROM (MCDI v0) */ #define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS { \ @@ -1456,9 +1461,11 @@ #define MC_CMD_FC_IN_DDR_TEST_START_B1_WIDTH 1 /* MC_CMD_FC_IN_DDR_TEST_POLL msgrequest */ -#define MC_CMD_FC_IN_DDR_TEST_POLL_LEN 8 +#define MC_CMD_FC_IN_DDR_TEST_POLL_LEN 12 #define MC_CMD_FC_IN_DDR_TEST_CMD_OFST 0 /* MC_CMD_FC_IN_DDR_TEST_HEADER_OFST 4 */ +/* Clear previous test result and prepare for restarting DDR test */ +#define MC_CMD_FC_IN_DDR_TEST_POLL_CLEAR_RESULT_FOR_DDR_TEST_OFST 8 /* MC_CMD_FC_IN_GET_ASSERT msgrequest */ #define MC_CMD_FC_IN_GET_ASSERT_LEN 4 @@ -1475,6 +1482,10 @@ #define MC_CMD_FC_IN_FPGA_BUILD_SERVICES 0x2 /* enum: Get the BSP version */ #define MC_CMD_FC_IN_FPGA_BUILD_BSP_VERSION 0x3 +/* enum: Get build register for V2 (SFA974X) */ +#define MC_CMD_FC_IN_FPGA_BUILD_BUILD_V2 0x4 +/* enum: GEt the services register for V2 (SFA974X) */ +#define MC_CMD_FC_IN_FPGA_BUILD_SERVICES_V2 0x5 /* MC_CMD_FC_IN_READ_MAP msgrequest */ #define MC_CMD_FC_IN_READ_MAP_LEN 8 @@ -1832,6 +1843,7 @@ #define MC_CMD_FC_IN_DDR_OP_OFST 4 #define MC_CMD_FC_IN_DDR_SET_SPD 0x0 /* enum */ #define MC_CMD_FC_IN_DDR_GET_STATUS 0x1 /* enum */ +#define MC_CMD_FC_IN_DDR_SET_INFO 0x2 /* enum */ #define MC_CMD_FC_IN_DDR_BANK_OFST 8 #define MC_CMD_FC_IN_DDR_BANK_B0 0x0 /* enum */ #define MC_CMD_FC_IN_DDR_BANK_B1 0x1 /* enum */ @@ -1855,6 +1867,15 @@ /* Page index of the spd data copied into MC_CMD_FC_IN_DDR_SPD */ #define MC_CMD_FC_IN_DDR_SPD_PAGE_ID_OFST 144 +/* MC_CMD_FC_IN_DDR_SET_INFO msgrequest */ +#define MC_CMD_FC_IN_DDR_SET_INFO_LEN 16 +/* MC_CMD_FC_IN_CMD_OFST 0 */ +/* MC_CMD_FC_IN_DDR_OP_OFST 4 */ +/* Affected bank */ +/* MC_CMD_FC_IN_DDR_BANK_OFST 8 */ +/* Size of DDR */ +#define MC_CMD_FC_IN_DDR_SIZE_OFST 12 + /* MC_CMD_FC_IN_DDR_GET_STATUS msgrequest */ #define MC_CMD_FC_IN_DDR_GET_STATUS_LEN 12 /* MC_CMD_FC_IN_CMD_OFST 0 */ @@ -2387,6 +2408,116 @@ #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_LBN 0 #define MC_CMD_FC_OUT_FPGA_BUILD_REVISION_HIGH_WIDTH 16 +/* MC_CMD_FC_OUT_FPGA_BUILD_V2 msgresponse */ +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_LEN 32 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_INFO_OFST 0 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_LBN 31 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_APPLICATION_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_LBN 30 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_IS_LICENSED_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_LBN 16 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_COMPONENT_ID_WIDTH 14 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_LBN 12 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MAJOR_WIDTH 4 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_LBN 4 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_MINOR_WIDTH 8 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_LBN 0 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_NUM_WIDTH 4 +/* Build timestamp (seconds since epoch) */ +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_TIMESTAMP_OFST 4 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_PARAMETERS_OFST 8 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_LBN 31 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_PMA_PASSTHROUGH_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_LBN 29 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_QDR_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_LBN 28 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_QDR_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_LBN 27 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DDR3_ECC_ENABLED_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_LBN 26 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_DDR3_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_LBN 25 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_DDR3_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_LBN 24 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_TO_DDR3_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_LBN 23 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_T0_DDR3_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_LBN 22 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE2_RLDRAM_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_LBN 21 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DISCRETE1_RLDRAM_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_LBN 20 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM2_RLDRAM_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_LBN 19 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SODIMM1_RLDRAM_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_LBN 18 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_10G 0x0 /* enum */ +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_3_SPEED_40G 0x1 /* enum */ +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_LBN 17 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_10G 0x0 /* enum */ +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_7_SPEED_40G 0x1 /* enum */ +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_LBN 16 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_10G 0x0 /* enum */ +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_3_SPEED_40G 0x1 /* enum */ +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_LBN 15 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP7_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_LBN 14 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP6_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_LBN 13 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP5_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_LBN 12 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP4_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_LBN 11 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP3_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_LBN 10 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP2_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_LBN 9 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP1_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_LBN 8 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_SFP0_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_LBN 7 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC3_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_LBN 6 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC2_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_LBN 5 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC1_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_LBN 4 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_NIC0_DEF_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_LBN 0 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_FPGA_TYPE_WIDTH 4 +#define MC_CMD_FC_FPGA_V2_TYPE_A3 0x0 /* enum */ +#define MC_CMD_FC_FPGA_V2_TYPE_A4 0x1 /* enum */ +#define MC_CMD_FC_FPGA_V2_TYPE_A5 0x2 /* enum */ +#define MC_CMD_FC_FPGA_V2_TYPE_A7 0x3 /* enum */ +#define MC_CMD_FC_FPGA_V2_TYPE_D3 0x8 /* enum */ +#define MC_CMD_FC_FPGA_V2_TYPE_D4 0x9 /* enum */ +#define MC_CMD_FC_FPGA_V2_TYPE_D5 0xa /* enum */ +#define MC_CMD_FC_FPGA_V2_TYPE_D7 0xb /* enum */ +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_IDENTIFIER_OFST 12 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_LBN 0 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_CHANGESET_WIDTH 16 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_LBN 16 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_BUILD_FLAG_WIDTH 1 +/* MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 */ +/* MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 */ +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_HI_OFST 16 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_LBN 0 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MINOR_WIDTH 16 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_LBN 16 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MAJOR_WIDTH 16 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_VERSION_LO_OFST 20 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_LBN 0 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_BUILD_WIDTH 16 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_LBN 16 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_DEPLOYMENT_VERSION_MICRO_WIDTH 16 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_LO_OFST 24 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HI_OFST 28 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_LBN 0 +#define MC_CMD_FC_OUT_FPGA_BUILD_V2_REVISION_HIGH_WIDTH 16 + /* MC_CMD_FC_OUT_FPGA_SERVICES msgresponse */ #define MC_CMD_FC_OUT_FPGA_SERVICES_LEN 32 #define MC_CMD_FC_OUT_FPGA_SERVICES_COMPONENT_INFO_OFST 0 @@ -2437,6 +2568,40 @@ #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_LBN 0 #define MC_CMD_FC_OUT_FPGA_SERVICES_REVISION_HIGH_WIDTH 16 +/* MC_CMD_FC_OUT_FPGA_SERVICES_V2 msgresponse */ +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_LEN 32 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_INFO_OFST 0 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_LBN 31 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_APPLICATION_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_LBN 30 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IS_LICENSED_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_LBN 16 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_COMPONENT_ID_WIDTH 14 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_LBN 12 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MAJOR_WIDTH 4 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_LBN 4 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_VERSION_MINOR_WIDTH 8 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_LBN 0 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_NUM_WIDTH 4 +/* Build timestamp (seconds since epoch) */ +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_TIMESTAMP_OFST 4 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PARAMETERS_OFST 8 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_LBN 0 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_PTP_ENABLED_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_LBN 8 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_FC_FLASH_BOOTED_WIDTH 1 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_IDENTIFIER_OFST 12 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_LBN 0 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_CHANGESET_WIDTH 16 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_LBN 16 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_BUILD_FLAG_WIDTH 1 +/* MC_CMD_FC_FPGA_BUILD_FLAG_INTERNAL 0x0 */ +/* MC_CMD_FC_FPGA_BUILD_FLAG_RELEASE 0x1 */ +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_LO_OFST 24 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HI_OFST 28 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_LBN 0 +#define MC_CMD_FC_OUT_FPGA_SERVICES_V2_REVISION_HIGH_WIDTH 16 + /* MC_CMD_FC_OUT_BSP_VERSION msgresponse */ #define MC_CMD_FC_OUT_BSP_VERSION_LEN 4 /* Qsys system ID */ @@ -2718,6 +2883,9 @@ /* MC_CMD_FC_OUT_DDR_SET_SPD msgresponse */ #define MC_CMD_FC_OUT_DDR_SET_SPD_LEN 0 +/* MC_CMD_FC_OUT_DDR_SET_INFO msgresponse */ +#define MC_CMD_FC_OUT_DDR_SET_INFO_LEN 0 + /* MC_CMD_FC_OUT_DDR_GET_STATUS msgresponse */ #define MC_CMD_FC_OUT_DDR_GET_STATUS_LEN 4 #define MC_CMD_FC_OUT_DDR_GET_STATUS_FLAGS_OFST 0 @@ -3131,6 +3299,8 @@ #define MC_CMD_AOE_OUT_INFO_FPGA_VERSION_OFST 12 /* FPGA type - read from CPLD straps */ #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_OFST 16 +#define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_A5_C2 0x1 /* enum */ +#define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_A7_C2 0x2 /* enum */ /* FPGA state (debug) */ #define MC_CMD_AOE_OUT_INFO_FPGA_STATE_OFST 20 /* FPGA image - partition from which loaded */ @@ -3144,23 +3314,28 @@ /* Random pieces of information */ #define MC_CMD_AOE_OUT_INFO_FLAGS_OFST 32 /* enum: Power to FPGA supplied by PEG connector, not PCIe bus */ -#define MC_CMD_AOE_OUT_INFO_PEG_POWER 0x1 +#define MC_CMD_AOE_OUT_INFO_PEG_POWER 0x1 /* enum: CPLD apparently good */ -#define MC_CMD_AOE_OUT_INFO_CPLD_GOOD 0x2 +#define MC_CMD_AOE_OUT_INFO_CPLD_GOOD 0x2 /* enum: FPGA working normally */ -#define MC_CMD_AOE_OUT_INFO_FPGA_GOOD 0x4 +#define MC_CMD_AOE_OUT_INFO_FPGA_GOOD 0x4 /* enum: FPGA is powered */ -#define MC_CMD_AOE_OUT_INFO_FPGA_POWER 0x8 +#define MC_CMD_AOE_OUT_INFO_FPGA_POWER 0x8 /* enum: Board has incompatible SODIMMs fitted */ -#define MC_CMD_AOE_OUT_INFO_BAD_SODIMM 0x10 +#define MC_CMD_AOE_OUT_INFO_BAD_SODIMM 0x10 /* enum: Board has ByteBlaster connected */ -#define MC_CMD_AOE_OUT_INFO_HAS_BYTEBLASTER 0x20 -/* Revision of Modena board */ +#define MC_CMD_AOE_OUT_INFO_HAS_BYTEBLASTER 0x20 +/* enum: FPGA Boot flash has an invalid header. */ +#define MC_CMD_AOE_OUT_INFO_FPGA_BAD_BOOT_HDR 0x40 +/* enum: FPGA Application flash is accessible. */ +#define MC_CMD_AOE_OUT_INFO_FPGA_APP_FLASH_GOOD 0x80 +/* Revision of Modena and Sorrento boards. Sorrento can be R1_2 or R1_3. */ #define MC_CMD_AOE_OUT_INFO_BOARD_REVISION_OFST 36 #define MC_CMD_AOE_OUT_INFO_UNKNOWN 0x0 /* enum */ #define MC_CMD_AOE_OUT_INFO_R1_0 0x10 /* enum */ #define MC_CMD_AOE_OUT_INFO_R1_1 0x11 /* enum */ #define MC_CMD_AOE_OUT_INFO_R1_2 0x12 /* enum */ +#define MC_CMD_AOE_OUT_INFO_R1_3 0x13 /* enum */ /* Result of FC booting - not valid while a ByteBlaster is connected. */ #define MC_CMD_AOE_OUT_INFO_FC_BOOT_RESULT_OFST 40 /* enum: No error */ @@ -3931,15 +4106,30 @@ /* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS msgresponse */ #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_LEN 16 -/* Uncorrected error on transmit timestamps in NIC clock format */ +/* Uncorrected error on PTP transmit timestamps in NIC clock format */ #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_OFST 0 -/* Uncorrected error on receive timestamps in NIC clock format */ +/* Uncorrected error on PTP receive timestamps in NIC clock format */ #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_OFST 4 /* Uncorrected error on PPS output in NIC clock format */ #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_OFST 8 /* Uncorrected error on PPS input in NIC clock format */ #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_OFST 12 +/* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2 msgresponse */ +#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_LEN 24 +/* Uncorrected error on PTP transmit timestamps in NIC clock format */ +#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_OFST 0 +/* Uncorrected error on PTP receive timestamps in NIC clock format */ +#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_OFST 4 +/* Uncorrected error on PPS output in NIC clock format */ +#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_OFST 8 +/* Uncorrected error on PPS input in NIC clock format */ +#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_OFST 12 +/* Uncorrected error on non-PTP transmit timestamps in NIC clock format */ +#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_OFST 16 +/* Uncorrected error on non-PTP receive timestamps in NIC clock format */ +#define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_OFST 20 + /* MC_CMD_PTP_OUT_MANFTEST_PPS msgresponse */ #define MC_CMD_PTP_OUT_MANFTEST_PPS_LEN 4 /* Results of testing */ @@ -5203,7 +5393,7 @@ #define MC_CMD_SET_MAC 0x2c #undef MC_CMD_0x2c_PRIVILEGE_CTG -#define MC_CMD_0x2c_PRIVILEGE_CTG SRIOV_CTG_LINK +#define MC_CMD_0x2c_PRIVILEGE_CTG SRIOV_CTG_GENERAL /* MC_CMD_SET_MAC_IN msgrequest */ #define MC_CMD_SET_MAC_IN_LEN 28 @@ -5950,6 +6140,37 @@ /* amount to read in bytes */ #define MC_CMD_NVRAM_READ_IN_LENGTH_OFST 8 +/* MC_CMD_NVRAM_READ_IN_V2 msgrequest */ +#define MC_CMD_NVRAM_READ_IN_V2_LEN 16 +#define MC_CMD_NVRAM_READ_IN_V2_TYPE_OFST 0 +/* Enum values, see field(s): */ +/* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ +#define MC_CMD_NVRAM_READ_IN_V2_OFFSET_OFST 4 +/* amount to read in bytes */ +#define MC_CMD_NVRAM_READ_IN_V2_LENGTH_OFST 8 +/* Optional control info. If a partition is stored with an A/B versioning + * scheme (i.e. in more than one physical partition in NVRAM) the host can set + * this to control which underlying physical partition is used to read data + * from. This allows it to perform a read-modify-write-verify with the write + * lock continuously held by calling NVRAM_UPDATE_START, reading the old + * contents using MODE=TARGET_CURRENT, overwriting the old partition and then + * verifying by reading with MODE=TARGET_BACKUP. + */ +#define MC_CMD_NVRAM_READ_IN_V2_MODE_OFST 12 +/* enum: Same as omitting MODE: caller sees data in current partition unless it + * holds the write lock in which case it sees data in the partition it is + * updating. + */ +#define MC_CMD_NVRAM_READ_IN_V2_DEFAULT 0x0 +/* enum: Read from the current partition of an A/B pair, even if holding the + * write lock. + */ +#define MC_CMD_NVRAM_READ_IN_V2_TARGET_CURRENT 0x1 +/* enum: Read from the non-current (i.e. to be updated) partition of an A/B + * pair + */ +#define MC_CMD_NVRAM_READ_IN_V2_TARGET_BACKUP 0x2 + /* MC_CMD_NVRAM_READ_OUT msgresponse */ #define MC_CMD_NVRAM_READ_OUT_LENMIN 1 #define MC_CMD_NVRAM_READ_OUT_LENMAX 252 @@ -6329,6 +6550,8 @@ #define MC_CMD_SENSOR_PHY0_VCC 0x4c /* enum: Voltage supplied to the QSFP #1 from their power supply: mV */ #define MC_CMD_SENSOR_PHY1_VCC 0x4d +/* enum: Controller die temperature (TDIODE): degC */ +#define MC_CMD_SENSOR_CONTROLLER_TDIODE_TEMP 0x4e /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ #define MC_CMD_SENSOR_ENTRY_OFST 4 #define MC_CMD_SENSOR_ENTRY_LEN 8 @@ -6406,7 +6629,7 @@ /* MC_CMD_READ_SENSORS_EXT_IN msgrequest */ #define MC_CMD_READ_SENSORS_EXT_IN_LEN 12 -/* DMA address of host buffer for sensor readings */ +/* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */ #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LEN 8 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0 @@ -7656,6 +7879,88 @@ #define LICENSED_APP_ID_ID_LBN 0 #define LICENSED_APP_ID_ID_WIDTH 32 +/* LICENSED_FEATURES structuredef */ +#define LICENSED_FEATURES_LEN 8 +/* Bitmask of licensed firmware features */ +#define LICENSED_FEATURES_MASK_OFST 0 +#define LICENSED_FEATURES_MASK_LEN 8 +#define LICENSED_FEATURES_MASK_LO_OFST 0 +#define LICENSED_FEATURES_MASK_HI_OFST 4 +#define LICENSED_FEATURES_RX_CUT_THROUGH_LBN 0 +#define LICENSED_FEATURES_RX_CUT_THROUGH_WIDTH 1 +#define LICENSED_FEATURES_PIO_LBN 1 +#define LICENSED_FEATURES_PIO_WIDTH 1 +#define LICENSED_FEATURES_EVQ_TIMER_LBN 2 +#define LICENSED_FEATURES_EVQ_TIMER_WIDTH 1 +#define LICENSED_FEATURES_CLOCK_LBN 3 +#define LICENSED_FEATURES_CLOCK_WIDTH 1 +#define LICENSED_FEATURES_RX_TIMESTAMPS_LBN 4 +#define LICENSED_FEATURES_RX_TIMESTAMPS_WIDTH 1 +#define LICENSED_FEATURES_TX_TIMESTAMPS_LBN 5 +#define LICENSED_FEATURES_TX_TIMESTAMPS_WIDTH 1 +#define LICENSED_FEATURES_RX_SNIFF_LBN 6 +#define LICENSED_FEATURES_RX_SNIFF_WIDTH 1 +#define LICENSED_FEATURES_TX_SNIFF_LBN 7 +#define LICENSED_FEATURES_TX_SNIFF_WIDTH 1 +#define LICENSED_FEATURES_PROXY_FILTER_OPS_LBN 8 +#define LICENSED_FEATURES_PROXY_FILTER_OPS_WIDTH 1 +#define LICENSED_FEATURES_MASK_LBN 0 +#define LICENSED_FEATURES_MASK_WIDTH 64 + +/* LICENSED_V3_APPS structuredef */ +#define LICENSED_V3_APPS_LEN 8 +/* Bitmask of licensed applications */ +#define LICENSED_V3_APPS_MASK_OFST 0 +#define LICENSED_V3_APPS_MASK_LEN 8 +#define LICENSED_V3_APPS_MASK_LO_OFST 0 +#define LICENSED_V3_APPS_MASK_HI_OFST 4 +#define LICENSED_V3_APPS_ONLOAD_LBN 0 +#define LICENSED_V3_APPS_ONLOAD_WIDTH 1 +#define LICENSED_V3_APPS_PTP_LBN 1 +#define LICENSED_V3_APPS_PTP_WIDTH 1 +#define LICENSED_V3_APPS_SOLARCAPTURE_PRO_LBN 2 +#define LICENSED_V3_APPS_SOLARCAPTURE_PRO_WIDTH 1 +#define LICENSED_V3_APPS_SOLARSECURE_LBN 3 +#define LICENSED_V3_APPS_SOLARSECURE_WIDTH 1 +#define LICENSED_V3_APPS_PERF_MONITOR_LBN 4 +#define LICENSED_V3_APPS_PERF_MONITOR_WIDTH 1 +#define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_LBN 5 +#define LICENSED_V3_APPS_SOLARCAPTURE_LIVE_WIDTH 1 +#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_LBN 6 +#define LICENSED_V3_APPS_CAPTURE_SOLARSYSTEM_WIDTH 1 +#define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_LBN 7 +#define LICENSED_V3_APPS_NETWORK_ACCESS_CONTROL_WIDTH 1 +#define LICENSED_V3_APPS_MASK_LBN 0 +#define LICENSED_V3_APPS_MASK_WIDTH 64 + +/* LICENSED_V3_FEATURES structuredef */ +#define LICENSED_V3_FEATURES_LEN 8 +/* Bitmask of licensed firmware features */ +#define LICENSED_V3_FEATURES_MASK_OFST 0 +#define LICENSED_V3_FEATURES_MASK_LEN 8 +#define LICENSED_V3_FEATURES_MASK_LO_OFST 0 +#define LICENSED_V3_FEATURES_MASK_HI_OFST 4 +#define LICENSED_V3_FEATURES_RX_CUT_THROUGH_LBN 0 +#define LICENSED_V3_FEATURES_RX_CUT_THROUGH_WIDTH 1 +#define LICENSED_V3_FEATURES_PIO_LBN 1 +#define LICENSED_V3_FEATURES_PIO_WIDTH 1 +#define LICENSED_V3_FEATURES_EVQ_TIMER_LBN 2 +#define LICENSED_V3_FEATURES_EVQ_TIMER_WIDTH 1 +#define LICENSED_V3_FEATURES_CLOCK_LBN 3 +#define LICENSED_V3_FEATURES_CLOCK_WIDTH 1 +#define LICENSED_V3_FEATURES_RX_TIMESTAMPS_LBN 4 +#define LICENSED_V3_FEATURES_RX_TIMESTAMPS_WIDTH 1 +#define LICENSED_V3_FEATURES_TX_TIMESTAMPS_LBN 5 +#define LICENSED_V3_FEATURES_TX_TIMESTAMPS_WIDTH 1 +#define LICENSED_V3_FEATURES_RX_SNIFF_LBN 6 +#define LICENSED_V3_FEATURES_RX_SNIFF_WIDTH 1 +#define LICENSED_V3_FEATURES_TX_SNIFF_LBN 7 +#define LICENSED_V3_FEATURES_TX_SNIFF_WIDTH 1 +#define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_LBN 8 +#define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_WIDTH 1 +#define LICENSED_V3_FEATURES_MASK_LBN 0 +#define LICENSED_V3_FEATURES_MASK_WIDTH 64 + /* TX_TIMESTAMP_EVENT structuredef */ #define TX_TIMESTAMP_EVENT_LEN 6 /* lower 16 bits of timestamp data */ @@ -8050,6 +8355,8 @@ #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_IP_CSUM_EN_WIDTH 1 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_LBN 11 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_INNER_TCP_CSUM_EN_WIDTH 1 +#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_LBN 12 +#define MC_CMD_INIT_TXQ_EXT_IN_FLAG_TSOV2_EN_WIDTH 1 /* Owner ID to use if in buffer mode (zero if physical) */ #define MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_OFST 20 /* The port ID associated with the v-adaptor which should contain this DMAQ. */ @@ -8923,7 +9230,10 @@ /***********************************/ /* MC_CMD_PARSER_DISP_RW - * Direct read/write of parser-dispatcher state (DICPUs and LUE) for debugging + * Direct read/write of parser-dispatcher state (DICPUs and LUE) for debugging. + * Please note that this interface is only of use to debug tools which have + * knowledge of firmware and hardware data structures; nothing here is intended + * for use by normal driver code. */ #define MC_CMD_PARSER_DISP_RW 0xe5 #undef MC_CMD_0xe5_PRIVILEGE_CTG @@ -8942,6 +9252,12 @@ #define MC_CMD_PARSER_DISP_RW_IN_LUE 0x2 /* enum: Lookup engine (with requested metadata format) */ #define MC_CMD_PARSER_DISP_RW_IN_LUE_VERSIONED_METADATA 0x3 +/* enum: RX0 dispatcher CPU (alias for RX_DICPU; Medford has 2 RX DICPUs) */ +#define MC_CMD_PARSER_DISP_RW_IN_RX0_DICPU 0x0 +/* enum: RX1 dispatcher CPU (only valid for Medford) */ +#define MC_CMD_PARSER_DISP_RW_IN_RX1_DICPU 0x4 +/* enum: Miscellaneous other state (only valid for Medford) */ +#define MC_CMD_PARSER_DISP_RW_IN_MISC_STATE 0x5 /* identifies the type of operation requested */ #define MC_CMD_PARSER_DISP_RW_IN_OP_OFST 4 /* enum: read a word of DICPU DMEM or a LUE entry */ @@ -8950,8 +9266,12 @@ #define MC_CMD_PARSER_DISP_RW_IN_WRITE 0x1 /* enum: read-modify-write a word of DICPU DMEM (not valid for LUE) */ #define MC_CMD_PARSER_DISP_RW_IN_RMW 0x2 -/* data memory address or LUE index */ +/* data memory address (DICPU targets) or LUE index (LUE targets) */ #define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_OFST 8 +/* selector (for MISC_STATE target) */ +#define MC_CMD_PARSER_DISP_RW_IN_SELECTOR_OFST 8 +/* enum: Port to datapath mapping */ +#define MC_CMD_PARSER_DISP_RW_IN_PORT_DP_MAPPING 0x1 /* value to write (for DMEM writes) */ #define MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_OFST 12 /* XOR value (for DMEM read-modify-writes: new = (old & mask) ^ value) */ @@ -8976,6 +9296,12 @@ */ #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_OFST 20 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_LEN 32 +/* datapath(s) used for each port (for MISC_STATE PORT_DP_MAPPING selector) */ +#define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_OFST 0 +#define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_LEN 4 +#define MC_CMD_PARSER_DISP_RW_OUT_PORT_DP_MAPPING_NUM 4 +#define MC_CMD_PARSER_DISP_RW_OUT_DP0 0x1 /* enum */ +#define MC_CMD_PARSER_DISP_RW_OUT_DP1 0x2 /* enum */ /***********************************/ @@ -9656,6 +9982,14 @@ #define MC_CMD_GET_CAPABILITIES_OUT_LEN 20 /* First word of flags. */ #define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_OFST 0 +#define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_LBN 3 +#define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_LBN 4 +#define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_LBN 5 +#define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 +#define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 #define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_LBN 7 #define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 #define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_LBN 8 @@ -9824,6 +10158,200 @@ /* Licensed capabilities */ #define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_OFST 16 +/* MC_CMD_GET_CAPABILITIES_V2_IN msgrequest */ +#define MC_CMD_GET_CAPABILITIES_V2_IN_LEN 0 + +/* MC_CMD_GET_CAPABILITIES_V2_OUT msgresponse */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_LEN 26 +/* First word of flags. */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_OFST 0 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_LBN 3 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_LBN 4 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_LBN 5 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_LBN 6 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_LBN 7 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_LBN 8 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_LBN 9 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_LBN 10 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_LBN 11 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_LBN 12 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_LBN 13 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_LBN 14 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_LBN 15 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_LBN 16 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_LBN 17 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_LBN 18 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_LBN 19 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_LBN 20 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_LBN 21 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_LBN 22 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_LBN 23 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_LBN 24 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_LBN 25 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_LBN 26 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_LBN 27 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_LBN 28 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_LBN 29 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_LBN 30 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_LBN 31 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_WIDTH 1 +/* RxDPCPU firmware id. */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_OFST 4 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_LEN 2 +/* enum: Standard RXDP firmware */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP 0x0 +/* enum: Low latency RXDP firmware */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_LOW_LATENCY 0x1 +/* enum: Packed stream RXDP firmware */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_PACKED_STREAM 0x2 +/* enum: BIST RXDP firmware */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_BIST 0x10a +/* enum: RXDP Test firmware image 1 */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101 +/* enum: RXDP Test firmware image 2 */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102 +/* enum: RXDP Test firmware image 3 */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103 +/* enum: RXDP Test firmware image 4 */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104 +/* enum: RXDP Test firmware image 5 */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_BACKPRESSURE 0x105 +/* enum: RXDP Test firmware image 6 */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106 +/* enum: RXDP Test firmware image 7 */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107 +/* enum: RXDP Test firmware image 8 */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DISABLE_DL 0x108 +/* enum: RXDP Test firmware image 9 */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b +/* TxDPCPU firmware id. */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_OFST 6 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_DPCPU_FW_ID_LEN 2 +/* enum: Standard TXDP firmware */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP 0x0 +/* enum: Low latency TXDP firmware */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_LOW_LATENCY 0x1 +/* enum: High packet rate TXDP firmware */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_HIGH_PACKET_RATE 0x3 +/* enum: BIST TXDP firmware */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_BIST 0x12d +/* enum: TXDP Test firmware image 1 */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_TSO_EDIT 0x101 +/* enum: TXDP Test firmware image 2 */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_OFST 8 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_LEN 2 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_LBN 0 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_WIDTH 12 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_LBN 12 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4 +/* enum: reserved value - do not use (may indicate alternative interpretation + * of REV field in future) + */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RESERVED 0x0 +/* enum: Trivial RX PD firmware for early Huntington development (Huntington + * development only) + */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 +/* enum: RX PD firmware with approximately Siena-compatible behaviour + * (Huntington development only) + */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 +/* enum: Virtual switching (full feature) RX PD production firmware */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_VSWITCH 0x3 +/* enum: siena_compat variant RX PD firmware using PM rather than MAC + * (Huntington development only) + */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 +/* enum: Low latency RX PD production firmware */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 +/* enum: Packed stream RX PD production firmware */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6 +/* enum: RX PD firmware handling layer 2 only for high packet rate performance + * tests (Medford development only) + */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7 +/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe +/* enum: RX PD firmware parsing but not filtering network overlay tunnel + * encapsulations (Medford development only) + */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_OFST 10 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_LEN 2 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_LBN 0 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_WIDTH 12 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_LBN 12 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4 +/* enum: reserved value - do not use (may indicate alternative interpretation + * of REV field in future) + */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RESERVED 0x0 +/* enum: Trivial TX PD firmware for early Huntington development (Huntington + * development only) + */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 +/* enum: TX PD firmware with approximately Siena-compatible behaviour + * (Huntington development only) + */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 +/* enum: Virtual switching (full feature) TX PD production firmware */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_VSWITCH 0x3 +/* enum: siena_compat variant TX PD firmware using PM rather than MAC + * (Huntington development only) + */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */ +/* enum: TX PD firmware handling layer 2 only for high packet rate performance + * tests (Medford development only) + */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7 +/* enum: RX PD firmware for GUE parsing prototype (Medford development only) */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe +/* Hardware capabilities of NIC */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_OFST 12 +/* Licensed capabilities */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_OFST 16 +/* Second word of flags. Not present on older firmware (check the length). */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_OFST 20 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN 0 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_WIDTH 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_LBN 1 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_ENCAP_WIDTH 1 +/* Number of FATSOv2 contexts per datapath supported by this NIC. Not present + * on older firmware (check the length). + */ +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_OFST 24 +#define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_N_CONTEXTS_LEN 2 + /***********************************/ /* MC_CMD_V2_EXTN @@ -10545,10 +11073,17 @@ #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN 8 /* The handle of the RSS context */ #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0 -/* Hash control flags. The _EN bits are always supported. The _MODE bits only - * work when the firmware reports ADDITIONAL_RSS_MODES in - * MC_CMD_GET_CAPABILITIES and override the _EN bits if any of them are not 0. - * See the RSS_MODE structure for the meaning of the mode bits. +/* Hash control flags. The _EN bits are always supported, but new modes are + * available when ADDITIONAL_RSS_MODES is reported by MC_CMD_GET_CAPABILITIES: + * in this case, the MODE fields may be set to non-zero values, and will take + * effect regardless of the settings of the _EN flags. See the RSS_MODE + * structure for the meaning of the mode bits. Drivers must check the + * capability before trying to set any _MODE fields, as older firmware will + * reject any attempt to set the FLAGS field to a value > 0xff with EINVAL. In + * the case where all the _MODE flags are zero, the _EN flags take effect, + * providing backward compatibility for existing drivers. (Setting all _MODE + * *and* all _EN flags to zero is valid, to disable RSS spreading for that + * particular packet type.) */ #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_OFST 4 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_LBN 0 @@ -10594,11 +11129,18 @@ /* MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT msgresponse */ #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN 8 -/* Hash control flags. If any _MODE bits are non-zero (which will only be true - * when the firmware reports ADDITIONAL_RSS_MODES) then the _EN bits should be - * disregarded (but are guaranteed to be consistent with the _MODE bits if - * RSS_CONTEXT_SET_FLAGS has never been called for this context since it was - * allocated). +/* Hash control flags. If all _MODE bits are zero (which will always be true + * for older firmware which does not report the ADDITIONAL_RSS_MODES + * capability), the _EN bits report the state. If any _MODE bits are non-zero + * (which will only be true when the firmware reports ADDITIONAL_RSS_MODES) + * then the _EN bits should be disregarded, although the _MODE flags are + * guaranteed to be consistent with the _EN flags for a freshly-allocated RSS + * context and in the case where the _EN flags were used in the SET. This + * provides backward compatibility: old drivers will not be attempting to + * derive any meaning from the _MODE bits (and can never set them to any value + * not representable by the _EN bits); new drivers can always determine the + * mode by looking only at the _MODE bits; the value returned by a GET can + * always be used for a SET regardless of old/new driver vs. old/new firmware. */ #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST 4 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN 0 @@ -11568,32 +12110,38 @@ #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8 -/* enum: Attenuation (0-15, TBD for Medford) */ +/* enum: Attenuation (0-15, Huntington) */ #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_ATT 0x0 -/* enum: CTLE Boost (0-15, TBD for Medford) */ +/* enum: CTLE Boost (0-15, Huntington) */ #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST 0x1 -/* enum: Edge DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive, TBD - * for Medford) +/* enum: Edge DFE Tap1 (Huntington - 0 - max negative, 64 - zero, 127 - max + * positive, Medford - 0-31) */ #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP1 0x2 -/* enum: Edge DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive, TBD for - * Medford) +/* enum: Edge DFE Tap2 (Huntington - 0 - max negative, 32 - zero, 63 - max + * positive, Medford - 0-31) */ #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP2 0x3 -/* enum: Edge DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive, TBD for - * Medford) +/* enum: Edge DFE Tap3 (Huntington - 0 - max negative, 32 - zero, 63 - max + * positive, Medford - 0-16) */ #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP3 0x4 -/* enum: Edge DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive, TBD for - * Medford) +/* enum: Edge DFE Tap4 (Huntington - 0 - max negative, 32 - zero, 63 - max + * positive, Medford - 0-16) */ #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP4 0x5 -/* enum: Edge DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive, TBD for - * Medford) +/* enum: Edge DFE Tap5 (Huntington - 0 - max negative, 32 - zero, 63 - max + * positive, Medford - 0-16) */ #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP5 0x6 -/* enum: Edge DFE DLEV (TBD for Medford) */ +/* enum: Edge DFE DLEV (0-128 for Medford) */ #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_DLEV 0x7 +/* enum: Variable Gain Amplifier (0-15, Medford) */ +#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_VGA 0x8 +/* enum: CTLE EQ Capacitor (0-15, Medford) */ +#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9 +/* enum: CTLE EQ Resistor (0-7, Medford) */ +#define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 3 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ @@ -11665,26 +12213,32 @@ #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8 -/* enum: TX Amplitude */ +/* enum: TX Amplitude (Huntington, Medford) */ #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV 0x0 -/* enum: De-Emphasis Tap1 Magnitude (0-7) */ +/* enum: De-Emphasis Tap1 Magnitude (0-7) (Huntington) */ #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_MODE 0x1 /* enum: De-Emphasis Tap1 Fine */ #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_DTLEV 0x2 -/* enum: De-Emphasis Tap2 Magnitude (0-6) */ +/* enum: De-Emphasis Tap2 Magnitude (0-6) (Huntington) */ #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2 0x3 -/* enum: De-Emphasis Tap2 Fine */ +/* enum: De-Emphasis Tap2 Fine (Huntington) */ #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2TLEV 0x4 -/* enum: Pre-Emphasis Magnitude */ +/* enum: Pre-Emphasis Magnitude (Huntington) */ #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_E 0x5 -/* enum: Pre-Emphasis Fine */ +/* enum: Pre-Emphasis Fine (Huntington) */ #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_ETLEV 0x6 -/* enum: TX Slew Rate Coarse control */ +/* enum: TX Slew Rate Coarse control (Huntington) */ #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_PREDRV_DLY 0x7 -/* enum: TX Slew Rate Fine control */ +/* enum: TX Slew Rate Fine control (Huntington) */ #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_SR_SET 0x8 -/* enum: TX Termination Impedance control */ +/* enum: TX Termination Impedance control (Huntington) */ #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_RT_SET 0x9 +/* enum: TX Amplitude Fine control (Medford) */ +#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_FINE 0xa +/* enum: Pre-shoot Tap (Medford) */ +#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV 0xb +/* enum: De-emphasis Tap (Medford) */ +#define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY 0xc #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 3 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_0 0x0 /* enum */ @@ -11871,8 +12425,12 @@ #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_DLEV 0x7 /* enum: Figure of Merit */ #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_FOM 0x8 +/* enum: CTLE EQ Capacitor (HF Gain) */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9 +/* enum: CTLE EQ Resistor (DC Gain) */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8 -#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 4 +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 5 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */ #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */ #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */ @@ -11881,12 +12439,57 @@ #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_5 0x5 /* enum */ #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_6 0x6 /* enum */ #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_7 0x7 /* enum */ -#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_ALL 0x8 /* enum */ -#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_LBN 12 -#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 12 +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_8 0x8 /* enum */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_9 0x9 /* enum */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_10 0xa /* enum */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_11 0xb /* enum */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_12 0xc /* enum */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_13 0xd /* enum */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_14 0xe /* enum */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_15 0xf /* enum */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_ALL 0x10 /* enum */ +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 13 +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1 +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_LBN 14 +#define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 10 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8 +/* MC_CMD_PCIE_TUNE_RXEQ_SET_IN msgrequest */ +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMIN 8 +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LENMAX 252 +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num)) +/* Requested operation */ +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_OFST 0 +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_OP_LEN 1 +/* Align the arguments to 32 bits */ +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_OFST 1 +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PCIE_TUNE_RSVD_LEN 3 +/* RXEQ Parameter */ +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_OFST 4 +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LEN 4 +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1 +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62 +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0 +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8 +/* Enum values, see field(s): */ +/* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_ID */ +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8 +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 5 +/* Enum values, see field(s): */ +/* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */ +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 13 +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1 +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_LBN 14 +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 2 +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16 +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8 +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24 +#define MC_CMD_PCIE_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8 + +/* MC_CMD_PCIE_TUNE_RXEQ_SET_OUT msgresponse */ +#define MC_CMD_PCIE_TUNE_RXEQ_SET_OUT_LEN 0 + /* MC_CMD_PCIE_TUNE_TXEQ_GET_IN msgrequest */ #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_LEN 4 /* Requested operation */ @@ -11961,6 +12564,7 @@ /***********************************/ /* MC_CMD_LICENSING * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition + * - not used for V3 licensing */ #define MC_CMD_LICENSING 0xf3 #undef MC_CMD_0xf3_PRIVILEGE_CTG @@ -12006,6 +12610,95 @@ /***********************************/ +/* MC_CMD_LICENSING_V3 + * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition + * - V3 licensing (Medford) + */ +#define MC_CMD_LICENSING_V3 0xd0 +#undef MC_CMD_0xd0_PRIVILEGE_CTG + +#define MC_CMD_0xd0_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_LICENSING_V3_IN msgrequest */ +#define MC_CMD_LICENSING_V3_IN_LEN 4 +/* identifies the type of operation requested */ +#define MC_CMD_LICENSING_V3_IN_OP_OFST 0 +/* enum: re-read and apply licenses after a license key partition update; note + * that this operation returns a zero-length response + */ +#define MC_CMD_LICENSING_V3_IN_OP_UPDATE_LICENSE 0x0 +/* enum: report counts of installed licenses */ +#define MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE 0x1 + +/* MC_CMD_LICENSING_V3_OUT msgresponse */ +#define MC_CMD_LICENSING_V3_OUT_LEN 88 +/* count of keys which are valid */ +#define MC_CMD_LICENSING_V3_OUT_VALID_KEYS_OFST 0 +/* sum of UNVERIFIABLE_KEYS + WRONG_NODE_KEYS (for compatibility with + * MC_CMD_FC_OP_LICENSE) + */ +#define MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_OFST 4 +/* count of keys which are invalid due to being unverifiable */ +#define MC_CMD_LICENSING_V3_OUT_UNVERIFIABLE_KEYS_OFST 8 +/* count of keys which are invalid due to being for the wrong node */ +#define MC_CMD_LICENSING_V3_OUT_WRONG_NODE_KEYS_OFST 12 +/* licensing state (for diagnostics; the exact meaning of the bits in this + * field are private to the firmware) + */ +#define MC_CMD_LICENSING_V3_OUT_LICENSING_STATE_OFST 16 +/* licensing subsystem self-test report (for manftest) */ +#define MC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_OFST 20 +/* enum: licensing subsystem self-test failed */ +#define MC_CMD_LICENSING_V3_OUT_SELF_TEST_FAIL 0x0 +/* enum: licensing subsystem self-test passed */ +#define MC_CMD_LICENSING_V3_OUT_SELF_TEST_PASS 0x1 +/* bitmask of licensed applications */ +#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_OFST 24 +#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LEN 8 +#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_OFST 24 +#define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_OFST 28 +/* reserved for future use */ +#define MC_CMD_LICENSING_V3_OUT_RESERVED_0_OFST 32 +#define MC_CMD_LICENSING_V3_OUT_RESERVED_0_LEN 24 +/* bitmask of licensed features */ +#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_OFST 56 +#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LEN 8 +#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_OFST 56 +#define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_OFST 60 +/* reserved for future use */ +#define MC_CMD_LICENSING_V3_OUT_RESERVED_1_OFST 64 +#define MC_CMD_LICENSING_V3_OUT_RESERVED_1_LEN 24 + + +/***********************************/ +/* MC_CMD_LICENSING_GET_ID_V3 + * Get ID and type from the NVRAM_PARTITION_TYPE_LICENSE application license + * partition - V3 licensing (Medford) + */ +#define MC_CMD_LICENSING_GET_ID_V3 0xd1 +#undef MC_CMD_0xd1_PRIVILEGE_CTG + +#define MC_CMD_0xd1_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_LICENSING_GET_ID_V3_IN msgrequest */ +#define MC_CMD_LICENSING_GET_ID_V3_IN_LEN 0 + +/* MC_CMD_LICENSING_GET_ID_V3_OUT msgresponse */ +#define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMIN 8 +#define MC_CMD_LICENSING_GET_ID_V3_OUT_LENMAX 252 +#define MC_CMD_LICENSING_GET_ID_V3_OUT_LEN(num) (8+1*(num)) +/* type of license (eg 3) */ +#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_TYPE_OFST 0 +/* length of the license ID (in bytes) */ +#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LENGTH_OFST 4 +/* the unique license ID of the adapter */ +#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_OFST 8 +#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_LEN 1 +#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MINNUM 0 +#define MC_CMD_LICENSING_GET_ID_V3_OUT_LICENSE_ID_MAXNUM 244 + + +/***********************************/ /* MC_CMD_MC2MC_PROXY * Execute an arbitrary MCDI command on the slave MC of a dual-core device. * This will fail on a single-core system. @@ -12026,7 +12719,7 @@ /* MC_CMD_GET_LICENSED_APP_STATE * Query the state of an individual licensed application. (Note that the actual * state may be invalidated by the MC_CMD_LICENSING OP_UPDATE_LICENSE operation - * or a reboot of the MC.) + * or a reboot of the MC.) Not used for V3 licensing */ #define MC_CMD_GET_LICENSED_APP_STATE 0xf5 #undef MC_CMD_0xf5_PRIVILEGE_CTG @@ -12049,8 +12742,70 @@ /***********************************/ +/* MC_CMD_GET_LICENSED_V3_APP_STATE + * Query the state of an individual licensed application. (Note that the actual + * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE + * operation or a reboot of the MC.) Used for V3 licensing (Medford) + */ +#define MC_CMD_GET_LICENSED_V3_APP_STATE 0xd2 +#undef MC_CMD_0xd2_PRIVILEGE_CTG + +#define MC_CMD_0xd2_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_GET_LICENSED_V3_APP_STATE_IN msgrequest */ +#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_LEN 8 +/* application ID to query (LICENSED_V3_APPS_xxx) expressed as a single bit + * mask + */ +#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_OFST 0 +#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LEN 8 +#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_LO_OFST 0 +#define MC_CMD_GET_LICENSED_V3_APP_STATE_IN_APP_ID_HI_OFST 4 + +/* MC_CMD_GET_LICENSED_V3_APP_STATE_OUT msgresponse */ +#define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LEN 4 +/* state of this application */ +#define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_STATE_OFST 0 +/* enum: no (or invalid) license is present for the application */ +#define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_NOT_LICENSED 0x0 +/* enum: a valid license is present for the application */ +#define MC_CMD_GET_LICENSED_V3_APP_STATE_OUT_LICENSED 0x1 + + +/***********************************/ +/* MC_CMD_GET_LICENSED_V3_FEATURE_STATES + * Query the state of an one or more licensed features. (Note that the actual + * state may be invalidated by the MC_CMD_LICENSING_V3 OP_UPDATE_LICENSE + * operation or a reboot of the MC.) Used for V3 licensing (Medford) + */ +#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES 0xd3 +#undef MC_CMD_0xd3_PRIVILEGE_CTG + +#define MC_CMD_0xd3_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN msgrequest */ +#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_LEN 8 +/* features to query (LICENSED_V3_FEATURES_xxx) expressed as a mask with one or + * more bits set + */ +#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_OFST 0 +#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LEN 8 +#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_LO_OFST 0 +#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_IN_FEATURES_HI_OFST 4 + +/* MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT msgresponse */ +#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_LEN 8 +/* states of these features - bit set for licensed, clear for not licensed */ +#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_OFST 0 +#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LEN 8 +#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_LO_OFST 0 +#define MC_CMD_GET_LICENSED_V3_FEATURE_STATES_OUT_STATES_HI_OFST 4 + + +/***********************************/ /* MC_CMD_LICENSED_APP_OP - * Perform an action for an individual licensed application. + * Perform an action for an individual licensed application - not used for V3 + * licensing. */ #define MC_CMD_LICENSED_APP_OP 0xf6 #undef MC_CMD_0xf6_PRIVILEGE_CTG @@ -12117,6 +12872,69 @@ /***********************************/ +/* MC_CMD_LICENSED_V3_VALIDATE_APP + * Perform validation for an individual licensed application - V3 licensing + * (Medford) + */ +#define MC_CMD_LICENSED_V3_VALIDATE_APP 0xd4 +#undef MC_CMD_0xd4_PRIVILEGE_CTG + +#define MC_CMD_0xd4_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_LICENSED_V3_VALIDATE_APP_IN msgrequest */ +#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_LEN 72 +/* application ID expressed as a single bit mask */ +#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_OFST 0 +#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LEN 8 +#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_LO_OFST 0 +#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_APP_ID_HI_OFST 4 +/* challenge for validation */ +#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_OFST 8 +#define MC_CMD_LICENSED_V3_VALIDATE_APP_IN_CHALLENGE_LEN 64 + +/* MC_CMD_LICENSED_V3_VALIDATE_APP_OUT msgresponse */ +#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_LEN 72 +/* application expiry time */ +#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_TIME_OFST 0 +/* application expiry units */ +#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNITS_OFST 4 +/* enum: expiry units are accounting units */ +#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_ACC 0x0 +/* enum: expiry units are calendar days */ +#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_EXPIRY_UNIT_DAYS 0x1 +/* validation response to challenge */ +#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_OFST 8 +#define MC_CMD_LICENSED_V3_VALIDATE_APP_OUT_RESPONSE_LEN 64 + + +/***********************************/ +/* MC_CMD_LICENSED_V3_MASK_FEATURES + * Mask features - V3 licensing (Medford) + */ +#define MC_CMD_LICENSED_V3_MASK_FEATURES 0xd5 +#undef MC_CMD_0xd5_PRIVILEGE_CTG + +#define MC_CMD_0xd5_PRIVILEGE_CTG SRIOV_CTG_GENERAL + +/* MC_CMD_LICENSED_V3_MASK_FEATURES_IN msgrequest */ +#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_LEN 12 +/* mask to be applied to features to be changed */ +#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_OFST 0 +#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LEN 8 +#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_LO_OFST 0 +#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_MASK_HI_OFST 4 +/* whether to turn on or turn off the masked features */ +#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_FLAG_OFST 8 +/* enum: turn the features off */ +#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_OFF 0x0 +/* enum: turn the features back on */ +#define MC_CMD_LICENSED_V3_MASK_FEATURES_IN_ON 0x1 + +/* MC_CMD_LICENSED_V3_MASK_FEATURES_OUT msgresponse */ +#define MC_CMD_LICENSED_V3_MASK_FEATURES_OUT_LEN 0 + + +/***********************************/ /* MC_CMD_SET_PORT_SNIFF_CONFIG * Configure RX port sniffing for the physical port associated with the calling * function. Only a privileged function may change the port sniffing diff --git a/sys/dev/sfxge/common/efx_rx.c b/sys/dev/sfxge/common/efx_rx.c index 48e6328b3d40..c017e3f510cf 100644 --- a/sys/dev/sfxge/common/efx_rx.c +++ b/sys/dev/sfxge/common/efx_rx.c @@ -1246,7 +1246,6 @@ falconsiena_rx_qcreate( efx_nic_cfg_t *encp = &(enp->en_nic_cfg); efx_oword_t oword; uint32_t size; - boolean_t split; boolean_t jumbo; efx_rc_t rc; @@ -1277,7 +1276,6 @@ falconsiena_rx_qcreate( switch (type) { case EFX_RXQ_TYPE_DEFAULT: - split = B_FALSE; jumbo = B_FALSE; break; @@ -1307,7 +1305,6 @@ falconsiena_rx_qcreate( rc = EINVAL; goto fail4; } - split = B_FALSE; jumbo = B_TRUE; break; #endif /* EFSYS_OPT_RX_SCATTER */ @@ -1318,10 +1315,7 @@ falconsiena_rx_qcreate( } /* Set up the new descriptor queue */ - EFX_POPULATE_OWORD_10(oword, - FRF_CZ_RX_HDR_SPLIT, split, - FRF_AZ_RX_ISCSI_DDIG_EN, 0, - FRF_AZ_RX_ISCSI_HDIG_EN, 0, + EFX_POPULATE_OWORD_7(oword, FRF_AZ_RX_DESCQ_BUF_BASE_ID, id, FRF_AZ_RX_DESCQ_EVQ_ID, eep->ee_index, FRF_AZ_RX_DESCQ_OWNER_ID, 0, diff --git a/sys/dev/sfxge/common/hunt_ev.c b/sys/dev/sfxge/common/hunt_ev.c index c0a5b4f448e5..4742cbf61384 100644 --- a/sys/dev/sfxge/common/hunt_ev.c +++ b/sys/dev/sfxge/common/hunt_ev.c @@ -499,7 +499,6 @@ ef10_ev_rx( uint32_t l3_class; uint32_t l4_class; uint32_t next_read_lbits; - boolean_t soft1, soft2; uint16_t flags; boolean_t should_abort; efx_evq_rxq_state_t *eersp; @@ -561,10 +560,6 @@ ef10_ev_rx( flags |= EFX_DISCARD; } - /* FIXME: do we need soft bits from RXDP firmware ? */ - soft1 = (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_EV_SOFT1) != 0); - soft2 = (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_EV_SOFT2) != 0); - mcast = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_MAC_CLASS); if (mcast == ESE_DZ_MAC_CLASS_UCAST) flags |= EFX_PKT_UNICAST; diff --git a/sys/dev/sfxge/common/hunt_filter.c b/sys/dev/sfxge/common/hunt_filter.c index 846687db7f52..49ed0142ed06 100644 --- a/sys/dev/sfxge/common/hunt_filter.c +++ b/sys/dev/sfxge/common/hunt_filter.c @@ -41,90 +41,91 @@ __FBSDID("$FreeBSD$"); #if EFSYS_OPT_FILTER -#define HFE_SPEC(hftp, index) ((hftp)->hft_entry[(index)].hfe_spec) +#define EFE_SPEC(eftp, index) ((eftp)->eft_entry[(index)].efe_spec) static efx_filter_spec_t * -hunt_filter_entry_spec( - __in const hunt_filter_table_t *hftp, +ef10_filter_entry_spec( + __in const ef10_filter_table_t *eftp, __in unsigned int index) { - return ((efx_filter_spec_t *)(HFE_SPEC(hftp, index) & - ~(uintptr_t)EFX_HUNT_FILTER_FLAGS)); + return ((efx_filter_spec_t *)(EFE_SPEC(eftp, index) & + ~(uintptr_t)EFX_EF10_FILTER_FLAGS)); } static boolean_t -hunt_filter_entry_is_busy( - __in const hunt_filter_table_t *hftp, +ef10_filter_entry_is_busy( + __in const ef10_filter_table_t *eftp, __in unsigned int index) { - if (HFE_SPEC(hftp, index) & EFX_HUNT_FILTER_FLAG_BUSY) + if (EFE_SPEC(eftp, index) & EFX_EF10_FILTER_FLAG_BUSY) return (B_TRUE); else return (B_FALSE); } static boolean_t -hunt_filter_entry_is_auto_old( - __in const hunt_filter_table_t *hftp, +ef10_filter_entry_is_auto_old( + __in const ef10_filter_table_t *eftp, __in unsigned int index) { - if (HFE_SPEC(hftp, index) & EFX_HUNT_FILTER_FLAG_AUTO_OLD) + if (EFE_SPEC(eftp, index) & EFX_EF10_FILTER_FLAG_AUTO_OLD) return (B_TRUE); else return (B_FALSE); } static void -hunt_filter_set_entry( - __inout hunt_filter_table_t *hftp, +ef10_filter_set_entry( + __inout ef10_filter_table_t *eftp, __in unsigned int index, __in_opt const efx_filter_spec_t *efsp) { - HFE_SPEC(hftp, index) = (uintptr_t)efsp; + EFE_SPEC(eftp, index) = (uintptr_t)efsp; } static void -hunt_filter_set_entry_busy( - __inout hunt_filter_table_t *hftp, +ef10_filter_set_entry_busy( + __inout ef10_filter_table_t *eftp, __in unsigned int index) { - HFE_SPEC(hftp, index) |= (uintptr_t)EFX_HUNT_FILTER_FLAG_BUSY; + EFE_SPEC(eftp, index) |= (uintptr_t)EFX_EF10_FILTER_FLAG_BUSY; } static void -hunt_filter_set_entry_not_busy( - __inout hunt_filter_table_t *hftp, +ef10_filter_set_entry_not_busy( + __inout ef10_filter_table_t *eftp, __in unsigned int index) { - HFE_SPEC(hftp, index) &= ~(uintptr_t)EFX_HUNT_FILTER_FLAG_BUSY; + EFE_SPEC(eftp, index) &= ~(uintptr_t)EFX_EF10_FILTER_FLAG_BUSY; } static void -hunt_filter_set_entry_auto_old( - __inout hunt_filter_table_t *hftp, +ef10_filter_set_entry_auto_old( + __inout ef10_filter_table_t *eftp, __in unsigned int index) { - EFSYS_ASSERT(hunt_filter_entry_spec(hftp, index) != NULL); - HFE_SPEC(hftp, index) |= (uintptr_t)EFX_HUNT_FILTER_FLAG_AUTO_OLD; + EFSYS_ASSERT(ef10_filter_entry_spec(eftp, index) != NULL); + EFE_SPEC(eftp, index) |= (uintptr_t)EFX_EF10_FILTER_FLAG_AUTO_OLD; } static void -hunt_filter_set_entry_not_auto_old( - __inout hunt_filter_table_t *hftp, +ef10_filter_set_entry_not_auto_old( + __inout ef10_filter_table_t *eftp, __in unsigned int index) { - HFE_SPEC(hftp, index) &= ~(uintptr_t)EFX_HUNT_FILTER_FLAG_AUTO_OLD; - EFSYS_ASSERT(hunt_filter_entry_spec(hftp, index) != NULL); + EFE_SPEC(eftp, index) &= ~(uintptr_t)EFX_EF10_FILTER_FLAG_AUTO_OLD; + EFSYS_ASSERT(ef10_filter_entry_spec(eftp, index) != NULL); } __checkReturn efx_rc_t -hunt_filter_init( +ef10_filter_init( __in efx_nic_t *enp) { efx_rc_t rc; - hunt_filter_table_t *hftp; + ef10_filter_table_t *eftp; - EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || + enp->en_family == EFX_FAMILY_MEDFORD); #define MATCH_MASK(match) (EFX_MASK32(match) << EFX_LOW_BIT(match)) EFX_STATIC_ASSERT(EFX_FILTER_MATCH_REM_HOST == @@ -149,14 +150,14 @@ hunt_filter_init( MATCH_MASK(MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO)); #undef MATCH_MASK - EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (hunt_filter_table_t), hftp); + EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (ef10_filter_table_t), eftp); - if (!hftp) { + if (!eftp) { rc = ENOMEM; goto fail1; } - enp->en_filter.ef_hunt_filter_table = hftp; + enp->en_filter.ef_ef10_filter_table = eftp; return (0); @@ -167,14 +168,15 @@ fail1: } void -hunt_filter_fini( +ef10_filter_fini( __in efx_nic_t *enp) { - EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || + enp->en_family == EFX_FAMILY_MEDFORD); - if (enp->en_filter.ef_hunt_filter_table != NULL) { - EFSYS_KMEM_FREE(enp->en_esip, sizeof (hunt_filter_table_t), - enp->en_filter.ef_hunt_filter_table); + if (enp->en_filter.ef_ef10_filter_table != NULL) { + EFSYS_KMEM_FREE(enp->en_esip, sizeof (ef10_filter_table_t), + enp->en_filter.ef_ef10_filter_table); } } @@ -183,7 +185,7 @@ efx_mcdi_filter_op_add( __in efx_nic_t *enp, __in efx_filter_spec_t *spec, __in unsigned int filter_op, - __inout hunt_filter_handle_t *handle) + __inout ef10_filter_handle_t *handle) { efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_FILTER_OP_IN_LEN, @@ -201,9 +203,9 @@ efx_mcdi_filter_op_add( switch (filter_op) { case MC_CMD_FILTER_OP_IN_OP_REPLACE: MCDI_IN_SET_DWORD(req, FILTER_OP_IN_HANDLE_LO, - handle->hfh_lo); + handle->efh_lo); MCDI_IN_SET_DWORD(req, FILTER_OP_IN_HANDLE_HI, - handle->hfh_hi); + handle->efh_hi); /* Fall through */ case MC_CMD_FILTER_OP_IN_OP_INSERT: case MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE: @@ -302,8 +304,8 @@ efx_mcdi_filter_op_add( goto fail3; } - handle->hfh_lo = MCDI_OUT_DWORD(req, FILTER_OP_OUT_HANDLE_LO); - handle->hfh_hi = MCDI_OUT_DWORD(req, FILTER_OP_OUT_HANDLE_HI); + handle->efh_lo = MCDI_OUT_DWORD(req, FILTER_OP_OUT_HANDLE_LO); + handle->efh_hi = MCDI_OUT_DWORD(req, FILTER_OP_OUT_HANDLE_HI); return (0); @@ -322,7 +324,7 @@ static __checkReturn efx_rc_t efx_mcdi_filter_op_delete( __in efx_nic_t *enp, __in unsigned int filter_op, - __inout hunt_filter_handle_t *handle) + __inout ef10_filter_handle_t *handle) { efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_FILTER_OP_IN_LEN, @@ -351,8 +353,8 @@ efx_mcdi_filter_op_delete( goto fail1; } - MCDI_IN_SET_DWORD(req, FILTER_OP_IN_HANDLE_LO, handle->hfh_lo); - MCDI_IN_SET_DWORD(req, FILTER_OP_IN_HANDLE_HI, handle->hfh_hi); + MCDI_IN_SET_DWORD(req, FILTER_OP_IN_HANDLE_LO, handle->efh_lo); + MCDI_IN_SET_DWORD(req, FILTER_OP_IN_HANDLE_HI, handle->efh_hi); efx_mcdi_execute(enp, &req); @@ -380,7 +382,7 @@ fail1: } static __checkReturn boolean_t -hunt_filter_equal( +ef10_filter_equal( __in const efx_filter_spec_t *left, __in const efx_filter_spec_t *right) { @@ -413,7 +415,7 @@ hunt_filter_equal( } static __checkReturn boolean_t -hunt_filter_same_dest( +ef10_filter_same_dest( __in const efx_filter_spec_t *left, __in const efx_filter_spec_t *right) { @@ -430,7 +432,7 @@ hunt_filter_same_dest( } static __checkReturn uint32_t -hunt_filter_hash( +ef10_filter_hash( __in efx_filter_spec_t *spec) { EFX_STATIC_ASSERT((sizeof (efx_filter_spec_t) % sizeof (uint32_t)) @@ -456,7 +458,7 @@ hunt_filter_hash( * exclusive. */ static __checkReturn boolean_t -hunt_filter_is_exclusive( +ef10_filter_is_exclusive( __in efx_filter_spec_t *spec) { if ((spec->efs_match_flags & EFX_FILTER_MATCH_LOC_MAC) && @@ -478,30 +480,31 @@ hunt_filter_is_exclusive( } __checkReturn efx_rc_t -hunt_filter_restore( +ef10_filter_restore( __in efx_nic_t *enp) { int tbl_id; efx_filter_spec_t *spec; - hunt_filter_table_t *hftp = enp->en_filter.ef_hunt_filter_table; + ef10_filter_table_t *eftp = enp->en_filter.ef_ef10_filter_table; boolean_t restoring; int state; efx_rc_t rc; - EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || + enp->en_family == EFX_FAMILY_MEDFORD); - for (tbl_id = 0; tbl_id < EFX_HUNT_FILTER_TBL_ROWS; tbl_id++) { + for (tbl_id = 0; tbl_id < EFX_EF10_FILTER_TBL_ROWS; tbl_id++) { EFSYS_LOCK(enp->en_eslp, state); - spec = hunt_filter_entry_spec(hftp, tbl_id); + spec = ef10_filter_entry_spec(eftp, tbl_id); if (spec == NULL) { restoring = B_FALSE; - } else if (hunt_filter_entry_is_busy(hftp, tbl_id)) { + } else if (ef10_filter_entry_is_busy(eftp, tbl_id)) { /* Ignore busy entries. */ restoring = B_FALSE; } else { - hunt_filter_set_entry_busy(hftp, tbl_id); + ef10_filter_set_entry_busy(eftp, tbl_id); restoring = B_TRUE; } @@ -510,14 +513,14 @@ hunt_filter_restore( if (restoring == B_FALSE) continue; - if (hunt_filter_is_exclusive(spec)) { + if (ef10_filter_is_exclusive(spec)) { rc = efx_mcdi_filter_op_add(enp, spec, MC_CMD_FILTER_OP_IN_OP_INSERT, - &hftp->hft_entry[tbl_id].hfe_handle); + &eftp->eft_entry[tbl_id].efe_handle); } else { rc = efx_mcdi_filter_op_add(enp, spec, MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE, - &hftp->hft_entry[tbl_id].hfe_handle); + &eftp->eft_entry[tbl_id].efe_handle); } if (rc != 0) @@ -525,7 +528,7 @@ hunt_filter_restore( EFSYS_LOCK(enp->en_eslp, state); - hunt_filter_set_entry_not_busy(hftp, tbl_id); + ef10_filter_set_entry_not_busy(eftp, tbl_id); EFSYS_UNLOCK(enp->en_eslp, state); } @@ -542,17 +545,17 @@ fail1: * An arbitrary search limit for the software hash table. As per the linux net * driver. */ -#define EFX_HUNT_FILTER_SEARCH_LIMIT 200 +#define EF10_FILTER_SEARCH_LIMIT 200 static __checkReturn efx_rc_t -hunt_filter_add_internal( +ef10_filter_add_internal( __in efx_nic_t *enp, __inout efx_filter_spec_t *spec, __in boolean_t may_replace, __out_opt uint32_t *filter_id) { efx_rc_t rc; - hunt_filter_table_t *hftp = enp->en_filter.ef_hunt_filter_table; + ef10_filter_table_t *eftp = enp->en_filter.ef_ef10_filter_table; efx_filter_spec_t *saved_spec; uint32_t hash; unsigned int depth; @@ -562,13 +565,14 @@ hunt_filter_add_internal( int state; boolean_t locked = B_FALSE; - EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || + enp->en_family == EFX_FAMILY_MEDFORD); #if EFSYS_OPT_RX_SCALE spec->efs_rss_context = enp->en_rss_context; #endif - hash = hunt_filter_hash(spec); + hash = ef10_filter_hash(spec); /* * FIXME: Add support for inserting filters of different priorities @@ -587,21 +591,21 @@ hunt_filter_add_internal( locked = B_TRUE; for (;;) { - i = (hash + depth) & (EFX_HUNT_FILTER_TBL_ROWS - 1); - saved_spec = hunt_filter_entry_spec(hftp, i); + i = (hash + depth) & (EFX_EF10_FILTER_TBL_ROWS - 1); + saved_spec = ef10_filter_entry_spec(eftp, i); if (!saved_spec) { if (ins_index < 0) { ins_index = i; } - } else if (hunt_filter_equal(spec, saved_spec)) { - if (hunt_filter_entry_is_busy(hftp, i)) + } else if (ef10_filter_equal(spec, saved_spec)) { + if (ef10_filter_entry_is_busy(eftp, i)) break; if (saved_spec->efs_priority == EFX_FILTER_PRI_AUTO) { ins_index = i; goto found; - } else if (hunt_filter_is_exclusive(spec)) { + } else if (ef10_filter_is_exclusive(spec)) { if (may_replace) { ins_index = i; goto found; @@ -619,7 +623,7 @@ hunt_filter_add_internal( * the first suitable slot or return EBUSY if * there was none. */ - if (depth == EFX_HUNT_FILTER_SEARCH_LIMIT) { + if (depth == EF10_FILTER_SEARCH_LIMIT) { if (ins_index < 0) { rc = EBUSY; goto fail2; @@ -639,11 +643,11 @@ found: * insert a conflicting filter while we're waiting for the * firmware must find the busy entry. */ - saved_spec = hunt_filter_entry_spec(hftp, ins_index); + saved_spec = ef10_filter_entry_spec(eftp, ins_index); if (saved_spec) { if (saved_spec->efs_priority == EFX_FILTER_PRI_AUTO) { /* This is a filter we are refreshing */ - hunt_filter_set_entry_not_auto_old(hftp, ins_index); + ef10_filter_set_entry_not_auto_old(eftp, ins_index); goto out_unlock; } @@ -655,9 +659,9 @@ found: goto fail3; } *saved_spec = *spec; - hunt_filter_set_entry(hftp, ins_index, saved_spec); + ef10_filter_set_entry(eftp, ins_index, saved_spec); } - hunt_filter_set_entry_busy(hftp, ins_index); + ef10_filter_set_entry_busy(eftp, ins_index); EFSYS_UNLOCK(enp->en_eslp, state); locked = B_FALSE; @@ -669,15 +673,15 @@ found: if (replacing) { rc = efx_mcdi_filter_op_add(enp, spec, MC_CMD_FILTER_OP_IN_OP_REPLACE, - &hftp->hft_entry[ins_index].hfe_handle); - } else if (hunt_filter_is_exclusive(spec)) { + &eftp->eft_entry[ins_index].efe_handle); + } else if (ef10_filter_is_exclusive(spec)) { rc = efx_mcdi_filter_op_add(enp, spec, MC_CMD_FILTER_OP_IN_OP_INSERT, - &hftp->hft_entry[ins_index].hfe_handle); + &eftp->eft_entry[ins_index].efe_handle); } else { rc = efx_mcdi_filter_op_add(enp, spec, MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE, - &hftp->hft_entry[ins_index].hfe_handle); + &eftp->eft_entry[ins_index].efe_handle); } if (rc != 0) @@ -694,7 +698,7 @@ found: saved_spec->efs_dmaq_id = spec->efs_dmaq_id; } - hunt_filter_set_entry_not_busy(hftp, ins_index); + ef10_filter_set_entry_not_busy(eftp, ins_index); out_unlock: @@ -713,8 +717,8 @@ fail4: EFSYS_KMEM_FREE(enp->en_esip, sizeof (*spec), saved_spec); saved_spec = NULL; } - hunt_filter_set_entry_not_busy(hftp, ins_index); - hunt_filter_set_entry(hftp, ins_index, NULL); + ef10_filter_set_entry_not_busy(eftp, ins_index); + ef10_filter_set_entry(eftp, ins_index, NULL); fail3: EFSYS_PROBE(fail3); @@ -732,14 +736,14 @@ fail1: } __checkReturn efx_rc_t -hunt_filter_add( +ef10_filter_add( __in efx_nic_t *enp, __inout efx_filter_spec_t *spec, __in boolean_t may_replace) { efx_rc_t rc; - rc = hunt_filter_add_internal(enp, spec, may_replace, NULL); + rc = ef10_filter_add_internal(enp, spec, may_replace, NULL); if (rc != 0) goto fail1; @@ -753,15 +757,15 @@ fail1: static __checkReturn efx_rc_t -hunt_filter_delete_internal( +ef10_filter_delete_internal( __in efx_nic_t *enp, __in uint32_t filter_id) { efx_rc_t rc; - hunt_filter_table_t *table = enp->en_filter.ef_hunt_filter_table; + ef10_filter_table_t *table = enp->en_filter.ef_ef10_filter_table; efx_filter_spec_t *spec; int state; - uint32_t filter_idx = filter_id % EFX_HUNT_FILTER_TBL_ROWS; + uint32_t filter_idx = filter_id % EFX_EF10_FILTER_TBL_ROWS; /* * Find the software table entry and mark it busy. Don't @@ -771,13 +775,13 @@ hunt_filter_delete_internal( * FIXME: What if the busy flag is never cleared? */ EFSYS_LOCK(enp->en_eslp, state); - while (hunt_filter_entry_is_busy(table, filter_idx)) { + while (ef10_filter_entry_is_busy(table, filter_idx)) { EFSYS_UNLOCK(enp->en_eslp, state); EFSYS_SPIN(1); EFSYS_LOCK(enp->en_eslp, state); } - if ((spec = hunt_filter_entry_spec(table, filter_idx)) != NULL) { - hunt_filter_set_entry_busy(table, filter_idx); + if ((spec = ef10_filter_entry_spec(table, filter_idx)) != NULL) { + ef10_filter_set_entry_busy(table, filter_idx); } EFSYS_UNLOCK(enp->en_eslp, state); @@ -790,20 +794,20 @@ hunt_filter_delete_internal( * Try to remove the hardware filter. This may fail if the MC has * rebooted (which frees all hardware filter resources). */ - if (hunt_filter_is_exclusive(spec)) { + if (ef10_filter_is_exclusive(spec)) { rc = efx_mcdi_filter_op_delete(enp, MC_CMD_FILTER_OP_IN_OP_REMOVE, - &table->hft_entry[filter_idx].hfe_handle); + &table->eft_entry[filter_idx].efe_handle); } else { rc = efx_mcdi_filter_op_delete(enp, MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE, - &table->hft_entry[filter_idx].hfe_handle); + &table->eft_entry[filter_idx].efe_handle); } /* Free the software table entry */ EFSYS_LOCK(enp->en_eslp, state); - hunt_filter_set_entry_not_busy(table, filter_idx); - hunt_filter_set_entry(table, filter_idx, NULL); + ef10_filter_set_entry_not_busy(table, filter_idx); + ef10_filter_set_entry(table, filter_idx, NULL); EFSYS_UNLOCK(enp->en_eslp, state); EFSYS_KMEM_FREE(enp->en_esip, sizeof (*spec), spec); @@ -824,12 +828,12 @@ fail1: } __checkReturn efx_rc_t -hunt_filter_delete( +ef10_filter_delete( __in efx_nic_t *enp, __inout efx_filter_spec_t *spec) { efx_rc_t rc; - hunt_filter_table_t *table = enp->en_filter.ef_hunt_filter_table; + ef10_filter_table_t *table = enp->en_filter.ef_ef10_filter_table; efx_filter_spec_t *saved_spec; unsigned int hash; unsigned int depth; @@ -837,22 +841,23 @@ hunt_filter_delete( int state; boolean_t locked = B_FALSE; - EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON); + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || + enp->en_family == EFX_FAMILY_MEDFORD); - hash = hunt_filter_hash(spec); + hash = ef10_filter_hash(spec); EFSYS_LOCK(enp->en_eslp, state); locked = B_TRUE; depth = 1; for (;;) { - i = (hash + depth) & (EFX_HUNT_FILTER_TBL_ROWS - 1); - saved_spec = hunt_filter_entry_spec(table, i); - if (saved_spec && hunt_filter_equal(spec, saved_spec) && - hunt_filter_same_dest(spec, saved_spec)) { + i = (hash + depth) & (EFX_EF10_FILTER_TBL_ROWS - 1); + saved_spec = ef10_filter_entry_spec(table, i); + if (saved_spec && ef10_filter_equal(spec, saved_spec) && + ef10_filter_same_dest(spec, saved_spec)) { break; } - if (depth == EFX_HUNT_FILTER_SEARCH_LIMIT) { + if (depth == EF10_FILTER_SEARCH_LIMIT) { rc = ENOENT; goto fail1; } @@ -862,7 +867,7 @@ hunt_filter_delete( EFSYS_UNLOCK(enp->en_eslp, state); locked = B_FALSE; - rc = hunt_filter_delete_internal(enp, i); + rc = ef10_filter_delete_internal(enp, i); if (rc != 0) goto fail2; @@ -961,7 +966,7 @@ fail1: } __checkReturn efx_rc_t -hunt_filter_supported_filters( +ef10_filter_supported_filters( __in efx_nic_t *enp, __out uint32_t *list, __out size_t *length) @@ -980,13 +985,13 @@ fail1: } static __checkReturn efx_rc_t -hunt_filter_unicast_refresh( +ef10_filter_unicast_refresh( __in efx_nic_t *enp, __in_ecount(6) uint8_t const *addr, __in boolean_t all_unicst, __in efx_filter_flag_t filter_flags) { - hunt_filter_table_t *hftp = enp->en_filter.ef_hunt_filter_table; + ef10_filter_table_t *eftp = enp->en_filter.ef_ef10_filter_table; efx_filter_spec_t spec; efx_rc_t rc; @@ -996,11 +1001,11 @@ hunt_filter_unicast_refresh( /* Insert the filter for the local station address */ efx_filter_spec_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, - hftp->hft_default_rxq); + eftp->eft_default_rxq); efx_filter_spec_set_eth_local(&spec, EFX_FILTER_SPEC_VID_UNSPEC, addr); - rc = hunt_filter_add_internal(enp, &spec, B_TRUE, - &hftp->hft_unicst_filter_index); + rc = ef10_filter_add_internal(enp, &spec, B_TRUE, + &eftp->eft_unicst_filter_index); if (rc != 0) { /* * Fall back to an unknown filter. We may be able to subscribe @@ -1008,7 +1013,7 @@ hunt_filter_unicast_refresh( */ goto use_uc_def; } - hftp->hft_unicst_filter_set = B_TRUE; + eftp->eft_unicst_filter_set = B_TRUE; return (0); @@ -1016,32 +1021,32 @@ use_uc_def: /* Insert the unknown unicast filter */ efx_filter_spec_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, - hftp->hft_default_rxq); + eftp->eft_default_rxq); efx_filter_spec_set_uc_def(&spec); - rc = hunt_filter_add_internal(enp, &spec, B_TRUE, - &hftp->hft_unicst_filter_index); + rc = ef10_filter_add_internal(enp, &spec, B_TRUE, + &eftp->eft_unicst_filter_index); if (rc != 0) goto fail1; - hftp->hft_unicst_filter_set = B_TRUE; + eftp->eft_unicst_filter_set = B_TRUE; return (0); fail1: EFSYS_PROBE1(fail1, efx_rc_t, rc); - if (hftp->hft_unicst_filter_set != B_FALSE) { - (void) hunt_filter_delete_internal(enp, - hftp->hft_unicst_filter_index); + if (eftp->eft_unicst_filter_set != B_FALSE) { + (void) ef10_filter_delete_internal(enp, + eftp->eft_unicst_filter_index); - hftp->hft_unicst_filter_set = B_FALSE; + eftp->eft_unicst_filter_set = B_FALSE; } return (rc); } static __checkReturn efx_rc_t -hunt_filter_multicast_refresh( +ef10_filter_multicast_refresh( __in efx_nic_t *enp, __in boolean_t mulcst, __in boolean_t all_mulcst, @@ -1050,7 +1055,7 @@ hunt_filter_multicast_refresh( __in int count, __in efx_filter_flag_t filter_flags) { - hunt_filter_table_t *hftp = enp->en_filter.ef_hunt_filter_table; + ef10_filter_table_t *eftp = enp->en_filter.ef_ef10_filter_table; efx_filter_spec_t spec; uint8_t addr[6]; unsigned i; @@ -1063,25 +1068,25 @@ hunt_filter_multicast_refresh( count = 0; if (count + (brdcst ? 1 : 0) > - EFX_ARRAY_SIZE(hftp->hft_mulcst_filter_indexes)) { + EFX_ARRAY_SIZE(eftp->eft_mulcst_filter_indexes)) { /* Too many MAC addresses; use unknown multicast filter */ goto use_mc_def; } /* Insert/renew multicast address list filters */ - hftp->hft_mulcst_filter_count = count; - for (i = 0; i < hftp->hft_mulcst_filter_count; i++) { + eftp->eft_mulcst_filter_count = count; + for (i = 0; i < eftp->eft_mulcst_filter_count; i++) { efx_filter_spec_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, - hftp->hft_default_rxq); + eftp->eft_default_rxq); efx_filter_spec_set_eth_local(&spec, EFX_FILTER_SPEC_VID_UNSPEC, &addrs[i * EFX_MAC_ADDR_LEN]); - rc = hunt_filter_add_internal(enp, &spec, B_TRUE, - &hftp->hft_mulcst_filter_indexes[i]); + rc = ef10_filter_add_internal(enp, &spec, B_TRUE, + &eftp->eft_mulcst_filter_indexes[i]); if (rc != 0) { /* Rollback, then use unknown multicast filter */ goto rollback; @@ -1090,18 +1095,18 @@ hunt_filter_multicast_refresh( if (brdcst == B_TRUE) { /* Insert/renew broadcast address filter */ - hftp->hft_mulcst_filter_count++; + eftp->eft_mulcst_filter_count++; efx_filter_spec_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, - hftp->hft_default_rxq); + eftp->eft_default_rxq); EFX_MAC_BROADCAST_ADDR_SET(addr); efx_filter_spec_set_eth_local(&spec, EFX_FILTER_SPEC_VID_UNSPEC, addr); - rc = hunt_filter_add_internal(enp, &spec, B_TRUE, - &hftp->hft_mulcst_filter_indexes[ - hftp->hft_mulcst_filter_count - 1]); + rc = ef10_filter_add_internal(enp, &spec, B_TRUE, + &eftp->eft_mulcst_filter_indexes[ + eftp->eft_mulcst_filter_count - 1]); if (rc != 0) { /* Rollback, then use unknown multicast filter */ goto rollback; @@ -1116,24 +1121,24 @@ rollback: * before inserting the unknown multicast filter. */ while (i--) { - (void) hunt_filter_delete_internal(enp, - hftp->hft_mulcst_filter_indexes[i]); + (void) ef10_filter_delete_internal(enp, + eftp->eft_mulcst_filter_indexes[i]); } - hftp->hft_mulcst_filter_count = 0; + eftp->eft_mulcst_filter_count = 0; use_mc_def: /* Insert the unknown multicast filter */ efx_filter_spec_init_rx(&spec, EFX_FILTER_PRI_AUTO, filter_flags, - hftp->hft_default_rxq); + eftp->eft_default_rxq); efx_filter_spec_set_mc_def(&spec); - rc = hunt_filter_add_internal(enp, &spec, B_TRUE, - &hftp->hft_mulcst_filter_indexes[0]); + rc = ef10_filter_add_internal(enp, &spec, B_TRUE, + &eftp->eft_mulcst_filter_indexes[0]); if (rc != 0) goto fail1; - hftp->hft_mulcst_filter_count = 1; + eftp->eft_mulcst_filter_count = 1; /* * FIXME: If brdcst == B_FALSE, add a filter to drop broadcast traffic. @@ -1192,7 +1197,7 @@ fail1: * still applied in this case). */ __checkReturn efx_rc_t -hunt_filter_reconfigure( +ef10_filter_reconfigure( __in efx_nic_t *enp, __in_ecount(6) uint8_t const *mac_addr, __in boolean_t all_unicst, @@ -1202,58 +1207,58 @@ hunt_filter_reconfigure( __in_ecount(6*count) uint8_t const *addrs, __in int count) { - hunt_filter_table_t *table = enp->en_filter.ef_hunt_filter_table; + ef10_filter_table_t *table = enp->en_filter.ef_ef10_filter_table; efx_filter_flag_t filter_flags; unsigned i; int all_unicst_rc; int all_mulcst_rc; efx_rc_t rc; - if (table->hft_default_rxq == NULL) { + if (table->eft_default_rxq == NULL) { /* * Filters direct traffic to the default RXQ, and so cannot be * inserted until it is available. Any currently configured * filters must be removed (ignore errors in case the MC * has rebooted, which removes hardware filters). */ - if (table->hft_unicst_filter_set != B_FALSE) { - (void) hunt_filter_delete_internal(enp, - table->hft_unicst_filter_index); - table->hft_unicst_filter_set = B_FALSE; + if (table->eft_unicst_filter_set != B_FALSE) { + (void) ef10_filter_delete_internal(enp, + table->eft_unicst_filter_index); + table->eft_unicst_filter_set = B_FALSE; } - for (i = 0; i < table->hft_mulcst_filter_count; i++) { - (void) hunt_filter_delete_internal(enp, - table->hft_mulcst_filter_indexes[i]); + for (i = 0; i < table->eft_mulcst_filter_count; i++) { + (void) ef10_filter_delete_internal(enp, + table->eft_mulcst_filter_indexes[i]); } - table->hft_mulcst_filter_count = 0; + table->eft_mulcst_filter_count = 0; return (0); } - if (table->hft_using_rss) + if (table->eft_using_rss) filter_flags = EFX_FILTER_FLAG_RX_RSS; else filter_flags = 0; /* Mark old filters which may need to be removed */ - if (table->hft_unicst_filter_set != B_FALSE) { - hunt_filter_set_entry_auto_old(table, - table->hft_unicst_filter_index); + if (table->eft_unicst_filter_set != B_FALSE) { + ef10_filter_set_entry_auto_old(table, + table->eft_unicst_filter_index); } - for (i = 0; i < table->hft_mulcst_filter_count; i++) { - hunt_filter_set_entry_auto_old(table, - table->hft_mulcst_filter_indexes[i]); + for (i = 0; i < table->eft_mulcst_filter_count; i++) { + ef10_filter_set_entry_auto_old(table, + table->eft_mulcst_filter_indexes[i]); } /* Insert or renew unicast filters */ - if ((all_unicst_rc = hunt_filter_unicast_refresh(enp, mac_addr, + if ((all_unicst_rc = ef10_filter_unicast_refresh(enp, mac_addr, all_unicst, filter_flags)) != 0) { if (all_unicst == B_FALSE) { rc = all_unicst_rc; goto fail1; } /* Retry without all_unicast flag */ - rc = hunt_filter_unicast_refresh(enp, mac_addr, + rc = ef10_filter_unicast_refresh(enp, mac_addr, B_FALSE, filter_flags); if (rc != 0) goto fail2; @@ -1272,12 +1277,14 @@ hunt_filter_reconfigure( * filters. This ensures that encp->enc_workaround_bug26807 matches the * firmware state, and that later changes to enable/disable the * workaround will result in this function seeing a reset (FLR). + * + * FIXME: On Medford mulicast chaining should always be on. */ if ((rc = hunt_filter_get_workarounds(enp)) != 0) goto fail3; /* Insert or renew multicast filters */ - if ((all_mulcst_rc = hunt_filter_multicast_refresh(enp, mulcst, + if ((all_mulcst_rc = ef10_filter_multicast_refresh(enp, mulcst, all_mulcst, brdcst, addrs, count, filter_flags)) != 0) { if (all_mulcst == B_FALSE) { @@ -1285,7 +1292,7 @@ hunt_filter_reconfigure( goto fail4; } /* Retry without all_mulcast flag */ - rc = hunt_filter_multicast_refresh(enp, mulcst, + rc = ef10_filter_multicast_refresh(enp, mulcst, B_FALSE, brdcst, addrs, count, filter_flags); if (rc != 0) @@ -1293,9 +1300,9 @@ hunt_filter_reconfigure( } /* Remove old filters which were not renewed */ - for (i = 0; i < EFX_ARRAY_SIZE(table->hft_entry); i++) { - if (hunt_filter_entry_is_auto_old(table, i)) { - (void) hunt_filter_delete_internal(enp, i); + for (i = 0; i < EFX_ARRAY_SIZE(table->eft_entry); i++) { + if (ef10_filter_entry_is_auto_old(table, i)) { + (void) ef10_filter_delete_internal(enp, i); } } @@ -1319,9 +1326,9 @@ fail1: EFSYS_PROBE1(fail1, efx_rc_t, rc); /* Clear auto old flags */ - for (i = 0; i < EFX_ARRAY_SIZE(table->hft_entry); i++) { - if (hunt_filter_entry_is_auto_old(table, i)) { - hunt_filter_set_entry_not_auto_old(table, i); + for (i = 0; i < EFX_ARRAY_SIZE(table->eft_entry); i++) { + if (ef10_filter_entry_is_auto_old(table, i)) { + ef10_filter_set_entry_not_auto_old(table, i); } } @@ -1329,45 +1336,45 @@ fail1: } void -hunt_filter_get_default_rxq( +ef10_filter_get_default_rxq( __in efx_nic_t *enp, __out efx_rxq_t **erpp, __out boolean_t *using_rss) { - hunt_filter_table_t *table = enp->en_filter.ef_hunt_filter_table; + ef10_filter_table_t *table = enp->en_filter.ef_ef10_filter_table; - *erpp = table->hft_default_rxq; - *using_rss = table->hft_using_rss; + *erpp = table->eft_default_rxq; + *using_rss = table->eft_using_rss; } void -hunt_filter_default_rxq_set( +ef10_filter_default_rxq_set( __in efx_nic_t *enp, __in efx_rxq_t *erp, __in boolean_t using_rss) { - hunt_filter_table_t *table = enp->en_filter.ef_hunt_filter_table; + ef10_filter_table_t *table = enp->en_filter.ef_ef10_filter_table; #if EFSYS_OPT_RX_SCALE EFSYS_ASSERT((using_rss == B_FALSE) || (enp->en_rss_context != EF10_RSS_CONTEXT_INVALID)); - table->hft_using_rss = using_rss; + table->eft_using_rss = using_rss; #else EFSYS_ASSERT(using_rss == B_FALSE); - table->hft_using_rss = B_FALSE; + table->eft_using_rss = B_FALSE; #endif - table->hft_default_rxq = erp; + table->eft_default_rxq = erp; } void -hunt_filter_default_rxq_clear( +ef10_filter_default_rxq_clear( __in efx_nic_t *enp) { - hunt_filter_table_t *table = enp->en_filter.ef_hunt_filter_table; + ef10_filter_table_t *table = enp->en_filter.ef_ef10_filter_table; - table->hft_default_rxq = NULL; - table->hft_using_rss = B_FALSE; + table->eft_default_rxq = NULL; + table->eft_using_rss = B_FALSE; } diff --git a/sys/dev/sfxge/common/hunt_impl.h b/sys/dev/sfxge/common/hunt_impl.h index cb5f3b4d4931..c76d36efbca4 100644 --- a/sys/dev/sfxge/common/hunt_impl.h +++ b/sys/dev/sfxge/common/hunt_impl.h @@ -140,6 +140,21 @@ ef10_intr_trigger( __in unsigned int level); void +ef10_intr_status_line( + __in efx_nic_t *enp, + __out boolean_t *fatalp, + __out uint32_t *qmaskp); + + void +ef10_intr_status_message( + __in efx_nic_t *enp, + __in unsigned int message, + __out boolean_t *fatalp); + + void +ef10_intr_fatal( + __in efx_nic_t *enp); + void ef10_intr_fini( __in efx_nic_t *enp); @@ -346,18 +361,18 @@ ef10_nvram_partn_write_segment_tlv( extern __checkReturn efx_rc_t ef10_nvram_partn_size( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __out size_t *sizep); extern __checkReturn efx_rc_t ef10_nvram_partn_lock( __in efx_nic_t *enp, - __in unsigned int partn); + __in uint32_t partn); extern __checkReturn efx_rc_t ef10_nvram_partn_read( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __in unsigned int offset, __out_bcount(size) caddr_t data, __in size_t size); @@ -365,14 +380,14 @@ ef10_nvram_partn_read( extern __checkReturn efx_rc_t ef10_nvram_partn_erase( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __in unsigned int offset, __in size_t size); extern __checkReturn efx_rc_t ef10_nvram_partn_write( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __in unsigned int offset, __out_bcount(size) caddr_t data, __in size_t size); @@ -380,7 +395,7 @@ ef10_nvram_partn_write( extern void ef10_nvram_partn_unlock( __in efx_nic_t *enp, - __in unsigned int partn); + __in uint32_t partn); #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */ @@ -442,7 +457,7 @@ ef10_nvram_rw_finish( extern __checkReturn efx_rc_t ef10_nvram_partn_set_version( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __in_ecount(4) uint16_t version[4]); extern __checkReturn efx_rc_t @@ -914,71 +929,75 @@ ef10_rx_fini( #if EFSYS_OPT_FILTER -typedef struct hunt_filter_handle_s { - uint32_t hfh_lo; - uint32_t hfh_hi; -} hunt_filter_handle_t; +typedef struct ef10_filter_handle_s { + uint32_t efh_lo; + uint32_t efh_hi; +} ef10_filter_handle_t; -typedef struct hunt_filter_entry_s { - uintptr_t hfe_spec; /* pointer to filter spec plus busy bit */ - hunt_filter_handle_t hfe_handle; -} hunt_filter_entry_t; +typedef struct ef10_filter_entry_s { + uintptr_t efe_spec; /* pointer to filter spec plus busy bit */ + ef10_filter_handle_t efe_handle; +} ef10_filter_entry_t; /* * BUSY flag indicates that an update is in progress. * AUTO_OLD flag is used to mark and sweep MAC packet filters. */ -#define EFX_HUNT_FILTER_FLAG_BUSY 1U -#define EFX_HUNT_FILTER_FLAG_AUTO_OLD 2U -#define EFX_HUNT_FILTER_FLAGS 3U +#define EFX_EF10_FILTER_FLAG_BUSY 1U +#define EFX_EF10_FILTER_FLAG_AUTO_OLD 2U +#define EFX_EF10_FILTER_FLAGS 3U -#define EFX_HUNT_FILTER_TBL_ROWS 8192 +/* + * Size of the hash table used by the driver. Doesn't need to be the + * same size as the hardware's table. + */ +#define EFX_EF10_FILTER_TBL_ROWS 8192 /* Allow for the broadcast address to be added to the multicast list */ -#define EFX_HUNT_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1) - -typedef struct hunt_filter_table_s { - hunt_filter_entry_t hft_entry[EFX_HUNT_FILTER_TBL_ROWS]; - efx_rxq_t * hft_default_rxq; - boolean_t hft_using_rss; - uint32_t hft_unicst_filter_index; - boolean_t hft_unicst_filter_set; - uint32_t hft_mulcst_filter_indexes[ - EFX_HUNT_FILTER_MULTICAST_FILTERS_MAX]; - uint32_t hft_mulcst_filter_count; -} hunt_filter_table_t; +#define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1) + +typedef struct ef10_filter_table_s { + ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS]; + efx_rxq_t * eft_default_rxq; + boolean_t eft_using_rss; + uint32_t eft_unicst_filter_index; + boolean_t eft_unicst_filter_set; + uint32_t eft_mulcst_filter_indexes[ + EFX_EF10_FILTER_MULTICAST_FILTERS_MAX]; + uint32_t eft_mulcst_filter_count; +} ef10_filter_table_t; __checkReturn efx_rc_t -hunt_filter_init( +ef10_filter_init( __in efx_nic_t *enp); void -hunt_filter_fini( +ef10_filter_fini( __in efx_nic_t *enp); __checkReturn efx_rc_t -hunt_filter_restore( +ef10_filter_restore( __in efx_nic_t *enp); __checkReturn efx_rc_t -hunt_filter_add( +ef10_filter_add( __in efx_nic_t *enp, __inout efx_filter_spec_t *spec, __in boolean_t may_replace); __checkReturn efx_rc_t -hunt_filter_delete( +ef10_filter_delete( __in efx_nic_t *enp, __inout efx_filter_spec_t *spec); extern __checkReturn efx_rc_t -hunt_filter_supported_filters( +ef10_filter_supported_filters( __in efx_nic_t *enp, __out uint32_t *list, __out size_t *length); extern __checkReturn efx_rc_t -hunt_filter_reconfigure( +ef10_filter_reconfigure( __in efx_nic_t *enp, __in_ecount(6) uint8_t const *mac_addr, __in boolean_t all_unicst, @@ -989,19 +1008,19 @@ hunt_filter_reconfigure( __in int count); extern void -hunt_filter_get_default_rxq( +ef10_filter_get_default_rxq( __in efx_nic_t *enp, __out efx_rxq_t **erpp, __out boolean_t *using_rss); extern void -hunt_filter_default_rxq_set( +ef10_filter_default_rxq_set( __in efx_nic_t *enp, __in efx_rxq_t *erp, __in boolean_t using_rss); extern void -hunt_filter_default_rxq_clear( +ef10_filter_default_rxq_clear( __in efx_nic_t *enp); diff --git a/sys/dev/sfxge/common/hunt_intr.c b/sys/dev/sfxge/common/hunt_intr.c index 2033398f9ba7..6f9789f96d39 100644 --- a/sys/dev/sfxge/common/hunt_intr.c +++ b/sys/dev/sfxge/common/hunt_intr.c @@ -148,6 +148,48 @@ fail1: return (rc); } + void +ef10_intr_status_line( + __in efx_nic_t *enp, + __out boolean_t *fatalp, + __out uint32_t *qmaskp) +{ + efx_dword_t dword; + + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || + enp->en_family == EFX_FAMILY_MEDFORD); + + /* Read the queue mask and implicitly acknowledge the interrupt. */ + EFX_BAR_READD(enp, ER_DZ_BIU_INT_ISR_REG, &dword, B_FALSE); + *qmaskp = EFX_DWORD_FIELD(dword, EFX_DWORD_0); + + EFSYS_PROBE1(qmask, uint32_t, *qmaskp); + + *fatalp = B_FALSE; +} + + void +ef10_intr_status_message( + __in efx_nic_t *enp, + __in unsigned int message, + __out boolean_t *fatalp) +{ + EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON || + enp->en_family == EFX_FAMILY_MEDFORD); + + _NOTE(ARGUNUSED(enp, message)) + + /* EF10 fatal errors are reported via events */ + *fatalp = B_FALSE; +} + + void +ef10_intr_fatal( + __in efx_nic_t *enp) +{ + /* EF10 fatal errors are reported via events */ + _NOTE(ARGUNUSED(enp)) +} void ef10_intr_fini( diff --git a/sys/dev/sfxge/common/hunt_mac.c b/sys/dev/sfxge/common/hunt_mac.c index 5d5d26fb33a9..e93919a038a3 100644 --- a/sys/dev/sfxge/common/hunt_mac.c +++ b/sys/dev/sfxge/common/hunt_mac.c @@ -281,9 +281,9 @@ hunt_mac_filter_default_rxq_set( boolean_t old_using_rss; efx_rc_t rc; - hunt_filter_get_default_rxq(enp, &old_rxq, &old_using_rss); + ef10_filter_get_default_rxq(enp, &old_rxq, &old_using_rss); - hunt_filter_default_rxq_set(enp, erp, using_rss); + ef10_filter_default_rxq_set(enp, erp, using_rss); rc = efx_filter_reconfigure(enp, epp->ep_mac_addr, epp->ep_all_unicst, epp->ep_mulcst, @@ -299,7 +299,7 @@ hunt_mac_filter_default_rxq_set( fail1: EFSYS_PROBE1(fail1, efx_rc_t, rc); - hunt_filter_default_rxq_set(enp, old_rxq, old_using_rss); + ef10_filter_default_rxq_set(enp, old_rxq, old_using_rss); return (rc); } @@ -310,7 +310,7 @@ hunt_mac_filter_default_rxq_clear( { efx_port_t *epp = &(enp->en_port); - hunt_filter_default_rxq_clear(enp); + ef10_filter_default_rxq_clear(enp); efx_filter_reconfigure(enp, epp->ep_mac_addr, epp->ep_all_unicst, epp->ep_mulcst, diff --git a/sys/dev/sfxge/common/hunt_mcdi.c b/sys/dev/sfxge/common/hunt_mcdi.c index 590456e7b789..d23259e70060 100644 --- a/sys/dev/sfxge/common/hunt_mcdi.c +++ b/sys/dev/sfxge/common/hunt_mcdi.c @@ -81,6 +81,7 @@ ef10_mcdi_init( __in efx_nic_t *enp, __in const efx_mcdi_transport_t *emtp) { + efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); efsys_mem_t *esmp = emtp->emt_dma_mem; efx_dword_t dword; efx_rc_t rc; @@ -89,6 +90,13 @@ ef10_mcdi_init( enp->en_family == EFX_FAMILY_MEDFORD); EFSYS_ASSERT(enp->en_features & EFX_FEATURE_MCDI_DMA); + /* + * All EF10 firmware supports MCDIv2 and MCDIv1. + * Medford BootROM supports MCDIv2 and MCDIv1. + * Huntington BootROM supports MCDIv1 only. + */ + emip->emi_max_version = 2; + /* A host DMA buffer is required for EF10 MCDI */ if (esmp == NULL) { rc = EINVAL; diff --git a/sys/dev/sfxge/common/hunt_nvram.c b/sys/dev/sfxge/common/hunt_nvram.c index 38db912bb29f..0248221adbe2 100644 --- a/sys/dev/sfxge/common/hunt_nvram.c +++ b/sys/dev/sfxge/common/hunt_nvram.c @@ -1288,7 +1288,7 @@ fail1: __checkReturn efx_rc_t ef10_nvram_partn_size( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __out size_t *sizep) { efx_rc_t rc; @@ -1308,7 +1308,7 @@ fail1: __checkReturn efx_rc_t ef10_nvram_partn_lock( __in efx_nic_t *enp, - __in unsigned int partn) + __in uint32_t partn) { efx_rc_t rc; @@ -1326,7 +1326,7 @@ fail1: __checkReturn efx_rc_t ef10_nvram_partn_read( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __in unsigned int offset, __out_bcount(size) caddr_t data, __in size_t size) @@ -1358,7 +1358,7 @@ fail1: __checkReturn efx_rc_t ef10_nvram_partn_erase( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __in unsigned int offset, __in size_t size) { @@ -1403,7 +1403,7 @@ fail1: __checkReturn efx_rc_t ef10_nvram_partn_write( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __in unsigned int offset, __out_bcount(size) caddr_t data, __in size_t size) @@ -1457,7 +1457,7 @@ fail1: void ef10_nvram_partn_unlock( __in efx_nic_t *enp, - __in unsigned int partn) + __in uint32_t partn) { boolean_t reboot; efx_rc_t rc; @@ -1475,7 +1475,7 @@ fail1: __checkReturn efx_rc_t ef10_nvram_partn_set_version( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __in_ecount(4) uint16_t version[4]) { struct tlv_partition_version partn_version; @@ -1509,8 +1509,6 @@ fail1: #if EFSYS_OPT_NVRAM -/* FIXME: Update partition table for Medford */ - typedef struct ef10_parttbl_entry_s { unsigned int partn; unsigned int port; @@ -1518,7 +1516,7 @@ typedef struct ef10_parttbl_entry_s { } ef10_parttbl_entry_t; /* Translate EFX NVRAM types to firmware partition types */ -static ef10_parttbl_entry_t ef10_parttbl[] = { +static ef10_parttbl_entry_t hunt_parttbl[] = { {NVRAM_PARTITION_TYPE_MC_FIRMWARE, 1, EFX_NVRAM_MC_FIRMWARE}, {NVRAM_PARTITION_TYPE_MC_FIRMWARE, 2, EFX_NVRAM_MC_FIRMWARE}, {NVRAM_PARTITION_TYPE_MC_FIRMWARE, 3, EFX_NVRAM_MC_FIRMWARE}, @@ -1549,6 +1547,37 @@ static ef10_parttbl_entry_t ef10_parttbl[] = { {NVRAM_PARTITION_TYPE_FPGA_BACKUP, 4, EFX_NVRAM_FPGA_BACKUP} }; +static ef10_parttbl_entry_t medford_parttbl[] = { + {NVRAM_PARTITION_TYPE_MC_FIRMWARE, 1, EFX_NVRAM_MC_FIRMWARE}, + {NVRAM_PARTITION_TYPE_MC_FIRMWARE, 2, EFX_NVRAM_MC_FIRMWARE}, + {NVRAM_PARTITION_TYPE_MC_FIRMWARE, 3, EFX_NVRAM_MC_FIRMWARE}, + {NVRAM_PARTITION_TYPE_MC_FIRMWARE, 4, EFX_NVRAM_MC_FIRMWARE}, + {NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 1, EFX_NVRAM_MC_GOLDEN}, + {NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 2, EFX_NVRAM_MC_GOLDEN}, + {NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 3, EFX_NVRAM_MC_GOLDEN}, + {NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 4, EFX_NVRAM_MC_GOLDEN}, + {NVRAM_PARTITION_TYPE_EXPANSION_ROM, 1, EFX_NVRAM_BOOTROM}, + {NVRAM_PARTITION_TYPE_EXPANSION_ROM, 2, EFX_NVRAM_BOOTROM}, + {NVRAM_PARTITION_TYPE_EXPANSION_ROM, 3, EFX_NVRAM_BOOTROM}, + {NVRAM_PARTITION_TYPE_EXPANSION_ROM, 4, EFX_NVRAM_BOOTROM}, + {NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 1, EFX_NVRAM_BOOTROM_CFG}, + {NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 2, EFX_NVRAM_BOOTROM_CFG}, + {NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 3, EFX_NVRAM_BOOTROM_CFG}, + {NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 4, EFX_NVRAM_BOOTROM_CFG}, + {NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 1, EFX_NVRAM_DYNAMIC_CFG}, + {NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 2, EFX_NVRAM_DYNAMIC_CFG}, + {NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 3, EFX_NVRAM_DYNAMIC_CFG}, + {NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 4, EFX_NVRAM_DYNAMIC_CFG}, + {NVRAM_PARTITION_TYPE_FPGA, 1, EFX_NVRAM_FPGA}, + {NVRAM_PARTITION_TYPE_FPGA, 2, EFX_NVRAM_FPGA}, + {NVRAM_PARTITION_TYPE_FPGA, 3, EFX_NVRAM_FPGA}, + {NVRAM_PARTITION_TYPE_FPGA, 4, EFX_NVRAM_FPGA}, + {NVRAM_PARTITION_TYPE_FPGA_BACKUP, 1, EFX_NVRAM_FPGA_BACKUP}, + {NVRAM_PARTITION_TYPE_FPGA_BACKUP, 2, EFX_NVRAM_FPGA_BACKUP}, + {NVRAM_PARTITION_TYPE_FPGA_BACKUP, 3, EFX_NVRAM_FPGA_BACKUP}, + {NVRAM_PARTITION_TYPE_FPGA_BACKUP, 4, EFX_NVRAM_FPGA_BACKUP} +}; + static __checkReturn ef10_parttbl_entry_t * ef10_parttbl_entry( __in efx_nic_t *enp, @@ -1556,17 +1585,39 @@ ef10_parttbl_entry( { efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); ef10_parttbl_entry_t *entry; - int i; + ef10_parttbl_entry_t *parttbl; + size_t parttbl_size = 0; + unsigned int i; EFSYS_ASSERT3U(type, <, EFX_NVRAM_NTYPES); - for (i = 0; i < EFX_ARRAY_SIZE(ef10_parttbl); i++) { - entry = &ef10_parttbl[i]; + switch (enp->en_family) { + case EFX_FAMILY_HUNTINGTON: + parttbl = hunt_parttbl; + parttbl_size = EFX_ARRAY_SIZE(hunt_parttbl); + break; - if (entry->port == emip->emi_port && entry->nvtype == type) - return (entry); + case EFX_FAMILY_MEDFORD: + parttbl = medford_parttbl; + parttbl_size = EFX_ARRAY_SIZE(medford_parttbl); + break; + + default: + EFSYS_ASSERT(B_FALSE); + goto not_found; } + if (parttbl != NULL) { + for (i = 0; i < parttbl_size; i++) { + entry = &parttbl[i]; + + if (entry->port == emip->emi_port && + entry->nvtype == type) { + return (entry); + } + } + } +not_found: return (NULL); } @@ -1579,10 +1630,12 @@ ef10_nvram_test( { efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); ef10_parttbl_entry_t *entry; + ef10_parttbl_entry_t *parttbl; + size_t parttbl_size = 0; unsigned int npartns = 0; uint32_t *partns = NULL; size_t size; - int i; + unsigned int i; unsigned int j; efx_rc_t rc; @@ -1603,8 +1656,24 @@ ef10_nvram_test( * Iterate over the list of supported partition types * applicable to *this* port */ - for (i = 0; i < EFX_ARRAY_SIZE(ef10_parttbl); i++) { - entry = &ef10_parttbl[i]; + switch (enp->en_family) { + case EFX_FAMILY_HUNTINGTON: + parttbl = hunt_parttbl; + parttbl_size = EFX_ARRAY_SIZE(hunt_parttbl); + break; + + case EFX_FAMILY_MEDFORD: + parttbl = medford_parttbl; + parttbl_size = EFX_ARRAY_SIZE(medford_parttbl); + break; + + default: + EFSYS_ASSERT(B_FALSE); + goto fail3; + } + + for (i = 0; i < parttbl_size; i++) { + entry = &parttbl[i]; if (entry->port != emip->emi_port) continue; @@ -1613,7 +1682,7 @@ ef10_nvram_test( if (entry->partn == partns[j]) { rc = efx_mcdi_nvram_test(enp, entry->partn); if (rc != 0) - goto fail3; + goto fail4; } } } @@ -1621,6 +1690,8 @@ ef10_nvram_test( EFSYS_KMEM_FREE(enp->en_esip, size, partns); return (0); +fail4: + EFSYS_PROBE(fail3); fail3: EFSYS_PROBE(fail3); fail2: @@ -1840,7 +1911,7 @@ ef10_nvram_set_version( __in_ecount(4) uint16_t version[4]) { ef10_parttbl_entry_t *entry; - unsigned int partn; + uint32_t partn; efx_rc_t rc; if ((entry = ef10_parttbl_entry(enp, type)) == NULL) { diff --git a/sys/dev/sfxge/common/hunt_rx.c b/sys/dev/sfxge/common/hunt_rx.c index d5a38159fbd4..57b0c3d63991 100644 --- a/sys/dev/sfxge/common/hunt_rx.c +++ b/sys/dev/sfxge/common/hunt_rx.c @@ -147,14 +147,34 @@ fail1: static __checkReturn efx_rc_t efx_mcdi_rss_context_alloc( __in efx_nic_t *enp, + __in efx_rx_scale_support_t scale_support, + __in uint32_t num_queues, __out uint32_t *rss_contextp) { efx_mcdi_req_t req; uint8_t payload[MAX(MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN)]; uint32_t rss_context; + uint32_t context_type; efx_rc_t rc; + if (num_queues > EFX_MAXRSS) { + rc = EINVAL; + goto fail1; + } + + switch (scale_support) { + case EFX_RX_SCALE_EXCLUSIVE: + context_type = MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE; + break; + case EFX_RX_SCALE_SHARED: + context_type = MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED; + break; + default: + rc = EINVAL; + goto fail2; + } + (void) memset(payload, 0, sizeof (payload)); req.emr_cmd = MC_CMD_RSS_CONTEXT_ALLOC; req.emr_in_buf = payload; @@ -164,33 +184,36 @@ efx_mcdi_rss_context_alloc( MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID, EVB_PORT_ID_ASSIGNED); - MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_TYPE, - MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE); + MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_TYPE, context_type); /* NUM_QUEUES is only used to validate indirection table offsets */ - MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, 64); + MCDI_IN_SET_DWORD(req, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, num_queues); efx_mcdi_execute(enp, &req); if (req.emr_rc != 0) { rc = req.emr_rc; - goto fail1; + goto fail3; } if (req.emr_out_length_used < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN) { rc = EMSGSIZE; - goto fail2; + goto fail4; } rss_context = MCDI_OUT_DWORD(req, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID); if (rss_context == EF10_RSS_CONTEXT_INVALID) { rc = ENOENT; - goto fail3; + goto fail5; } *rss_contextp = rss_context; return (0); +fail5: + EFSYS_PROBE(fail5); +fail4: + EFSYS_PROBE(fail4); fail3: EFSYS_PROBE(fail3); fail2: @@ -420,7 +443,8 @@ ef10_rx_init( { #if EFSYS_OPT_RX_SCALE - if (efx_mcdi_rss_context_alloc(enp, &enp->en_rss_context) == 0) { + if (efx_mcdi_rss_context_alloc(enp, EFX_RX_SCALE_EXCLUSIVE, EFX_MAXRSS, + &enp->en_rss_context) == 0) { /* * Allocated an exclusive RSS context, which allows both the * indirection table and key to be modified. @@ -715,11 +739,6 @@ ef10_rx_qcreate( disable_scatter = B_FALSE; } - /* - * Note: EFX_RXQ_TYPE_SPLIT_HEADER and EFX_RXQ_TYPE_SPLIT_PAYLOAD are - * not supported here. - */ - if ((rc = efx_mcdi_init_rxq(enp, n, eep->ee_index, label, index, esmp, disable_scatter)) != 0) goto fail3; diff --git a/sys/dev/sfxge/common/mcdi_mon.c b/sys/dev/sfxge/common/mcdi_mon.c index e2105cdcef01..d443cbadaa8c 100644 --- a/sys/dev/sfxge/common/mcdi_mon.c +++ b/sys/dev/sfxge/common/mcdi_mon.c @@ -149,6 +149,13 @@ static const struct mcdi_sensor_map_s { STAT(Px, CONTROLLER_SLAVE_VPTAT_EXT_ADC), /* 0x46 SLAVE_VPTAT_EXT_ADC */ STAT(Px, CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC), /* 0x47 SLAVE_INTERNAL_TEMP_EXT_ADC */ + STAT_NO_SENSOR(), /* 0x48 (no sensor) */ + STAT(Px, SODIMM_VOUT), /* 0x49 SODIMM_VOUT */ + STAT(Px, SODIMM_0_TEMP), /* 0x4a SODIMM_0_TEMP */ + STAT(Px, SODIMM_1_TEMP), /* 0x4b SODIMM_1_TEMP */ + STAT(Px, PHY0_VCC), /* 0x4c PHY0_VCC */ + STAT(Px, PHY1_VCC), /* 0x4d PHY1_VCC */ + STAT(Px, CONTROLLER_TDIODE_TEMP), /* 0x4e CONTROLLER_TDIODE_TEMP */ }; #define MCDI_STATIC_SENSOR_ASSERT(_field) \ diff --git a/sys/dev/sfxge/common/siena_flash.h b/sys/dev/sfxge/common/siena_flash.h index 51e29e71f7e4..48ddfac11b7b 100644 --- a/sys/dev/sfxge/common/siena_flash.h +++ b/sys/dev/sfxge/common/siena_flash.h @@ -91,6 +91,19 @@ typedef struct blob_hdr_s { /* GENERATED BY scripts/genfwdef */ #define BLOB_CPU_TYPE_RXDI_VTBL1 (14) #define BLOB_CPU_TYPE_TXDI_VTBL1 (15) #define BLOB_CPU_TYPE_DUMPSPEC (32) +#define BLOB_CPU_TYPE_MC_XIP (33) + +#define BLOB_CPU_TYPE_INVALID (31) + +/* + * The upper four bits of the CPU type field specify the compression + * algorithm used for this blob. + */ +#define BLOB_COMPRESSION_MASK (0xf0000000) +#define BLOB_CPU_TYPE_MASK (0x0fffffff) + +#define BLOB_COMPRESSION_NONE (0x00000000) /* Stored as is */ +#define BLOB_COMPRESSION_LZ (0x10000000) /* see lib/lzdecoder.c */ typedef struct siena_mc_boot_hdr_s { /* GENERATED BY scripts/genfwdef */ efx_dword_t magic; /* = SIENA_MC_BOOT_MAGIC */ diff --git a/sys/dev/sfxge/common/siena_impl.h b/sys/dev/sfxge/common/siena_impl.h index 0433edbda922..a6afcf85a859 100644 --- a/sys/dev/sfxge/common/siena_impl.h +++ b/sys/dev/sfxge/common/siena_impl.h @@ -158,18 +158,18 @@ siena_mcdi_feature_supported( extern __checkReturn efx_rc_t siena_nvram_partn_size( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __out size_t *sizep); extern __checkReturn efx_rc_t siena_nvram_partn_lock( __in efx_nic_t *enp, - __in unsigned int partn); + __in uint32_t partn); extern __checkReturn efx_rc_t siena_nvram_partn_read( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __in unsigned int offset, __out_bcount(size) caddr_t data, __in size_t size); @@ -177,14 +177,14 @@ siena_nvram_partn_read( extern __checkReturn efx_rc_t siena_nvram_partn_erase( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __in unsigned int offset, __in size_t size); extern __checkReturn efx_rc_t siena_nvram_partn_write( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __in unsigned int offset, __out_bcount(size) caddr_t data, __in size_t size); @@ -192,12 +192,12 @@ siena_nvram_partn_write( extern void siena_nvram_partn_unlock( __in efx_nic_t *enp, - __in unsigned int partn); + __in uint32_t partn); extern __checkReturn efx_rc_t siena_nvram_get_dynamic_cfg( __in efx_nic_t *enp, - __in unsigned int index, + __in uint32_t partn, __in boolean_t vpd, __out siena_mc_dynamic_config_hdr_t **dcfgp, __out size_t *sizep); @@ -223,7 +223,7 @@ siena_nvram_size( extern __checkReturn efx_rc_t siena_nvram_get_subtype( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __out uint32_t *subtypep); extern __checkReturn efx_rc_t diff --git a/sys/dev/sfxge/common/siena_mcdi.c b/sys/dev/sfxge/common/siena_mcdi.c index a3505989d068..cb62f6dee3a4 100644 --- a/sys/dev/sfxge/common/siena_mcdi.c +++ b/sys/dev/sfxge/common/siena_mcdi.c @@ -244,6 +244,9 @@ siena_mcdi_init( goto fail1; } + /* Siena BootROM and firmware only support MCDIv1 */ + emip->emi_max_version = 1; + /* * Wipe the atomic reboot status so subsequent MCDI requests succeed. * BOOT_STATUS is preserved so eno_nic_probe() can boot out of the diff --git a/sys/dev/sfxge/common/siena_nvram.c b/sys/dev/sfxge/common/siena_nvram.c index ecc51952ea53..b1406ddbb57f 100644 --- a/sys/dev/sfxge/common/siena_nvram.c +++ b/sys/dev/sfxge/common/siena_nvram.c @@ -44,7 +44,7 @@ __FBSDID("$FreeBSD$"); __checkReturn efx_rc_t siena_nvram_partn_size( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __out size_t *sizep) { efx_rc_t rc; @@ -72,7 +72,7 @@ fail1: __checkReturn efx_rc_t siena_nvram_partn_lock( __in efx_nic_t *enp, - __in unsigned int partn) + __in uint32_t partn) { efx_rc_t rc; @@ -91,7 +91,7 @@ fail1: __checkReturn efx_rc_t siena_nvram_partn_read( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __in unsigned int offset, __out_bcount(size) caddr_t data, __in size_t size) @@ -123,7 +123,7 @@ fail1: __checkReturn efx_rc_t siena_nvram_partn_erase( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __in unsigned int offset, __in size_t size) { @@ -144,7 +144,7 @@ fail1: __checkReturn efx_rc_t siena_nvram_partn_write( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __in unsigned int offset, __out_bcount(size) caddr_t data, __in size_t size) @@ -176,7 +176,7 @@ fail1: void siena_nvram_partn_unlock( __in efx_nic_t *enp, - __in unsigned int partn) + __in uint32_t partn) { boolean_t reboot; efx_rc_t rc; @@ -326,7 +326,7 @@ fail1: __checkReturn efx_rc_t siena_nvram_get_dynamic_cfg( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __in boolean_t vpd, __out siena_mc_dynamic_config_hdr_t **dcfgp, __out size_t *sizep) @@ -455,7 +455,7 @@ fail1: __checkReturn efx_rc_t siena_nvram_get_subtype( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __out uint32_t *subtypep) { efx_mcdi_req_t req; @@ -515,8 +515,8 @@ siena_nvram_get_version( { siena_mc_dynamic_config_hdr_t *dcfg; siena_parttbl_entry_t *entry; - unsigned int dcfg_partn; - unsigned int partn; + uint32_t dcfg_partn; + uint32_t partn; unsigned int i; efx_rc_t rc; diff --git a/sys/dev/sfxge/common/siena_vpd.c b/sys/dev/sfxge/common/siena_vpd.c index df6797d2fbae..6498fdfcd341 100644 --- a/sys/dev/sfxge/common/siena_vpd.c +++ b/sys/dev/sfxge/common/siena_vpd.c @@ -44,7 +44,7 @@ __FBSDID("$FreeBSD$"); static __checkReturn efx_rc_t siena_vpd_get_static( __in efx_nic_t *enp, - __in unsigned int partn, + __in uint32_t partn, __deref_out_bcount_opt(*sizep) caddr_t *svpdp, __out size_t *sizep) { @@ -207,7 +207,7 @@ siena_vpd_size( __out size_t *sizep) { efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip); - unsigned int partn; + uint32_t partn; efx_rc_t rc; EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA); diff --git a/sys/dev/uart/uart_bus.h b/sys/dev/uart/uart_bus.h index 11d599e670fe..d46c28dd4e53 100644 --- a/sys/dev/uart/uart_bus.h +++ b/sys/dev/uart/uart_bus.h @@ -113,6 +113,7 @@ struct uart_softc { /* Pulse capturing support (PPS). */ struct pps_state sc_pps; int sc_pps_mode; + sbintime_t sc_pps_captime; /* Upper layer data. */ void *sc_softih; diff --git a/sys/dev/uart/uart_core.c b/sys/dev/uart/uart_core.c index 96b45299a18a..9650dd501e68 100644 --- a/sys/dev/uart/uart_core.c +++ b/sys/dev/uart/uart_core.c @@ -48,6 +48,7 @@ __FBSDID("$FreeBSD$"); #include <dev/uart/uart.h> #include <dev/uart/uart_bus.h> #include <dev/uart/uart_cpu.h> +#include <dev/uart/uart_ppstypes.h> #include "uart_if.h" @@ -70,47 +71,47 @@ static int uart_force_poll; SYSCTL_INT(_debug, OID_AUTO, uart_force_poll, CTLFLAG_RDTUN, &uart_force_poll, 0, "Force UART polling"); -#define PPS_MODE_DISABLED 0 -#define PPS_MODE_CTS 1 -#define PPS_MODE_DCD 2 - -static inline int -uart_pps_signal(int pps_mode) -{ - - switch(pps_mode) { - case PPS_MODE_CTS: - return (SER_CTS); - case PPS_MODE_DCD: - return (SER_DCD); - } - return (0); -} static inline int uart_pps_mode_valid(int pps_mode) { - - switch(pps_mode) { - case PPS_MODE_DISABLED: - case PPS_MODE_CTS: - case PPS_MODE_DCD: - return (true); + int opt; + + switch(pps_mode & UART_PPS_SIGNAL_MASK) { + case UART_PPS_DISABLED: + case UART_PPS_CTS: + case UART_PPS_DCD: + break; + default: + return (false); } - return (false); + + opt = pps_mode & UART_PPS_OPTION_MASK; + if ((opt & ~(UART_PPS_INVERT_PULSE | UART_PPS_NARROW_PULSE)) != 0) + return (false); + + return (true); } -static const char * -uart_pps_mode_name(int pps_mode) +static void +uart_pps_print_mode(struct uart_softc *sc) { - switch(pps_mode) { - case PPS_MODE_DISABLED: - return ("disabled"); - case PPS_MODE_CTS: - return ("CTS"); - case PPS_MODE_DCD: - return ("DCD"); + + device_printf(sc->sc_dev, "PPS capture mode: "); + switch(sc->sc_pps_mode) { + case UART_PPS_DISABLED: + printf("disabled"); + case UART_PPS_CTS: + printf("CTS"); + case UART_PPS_DCD: + printf("DCD"); + default: + printf("invalid"); } - return ("invalid"); + if (sc->sc_pps_mode & UART_PPS_INVERT_PULSE) + printf("-Inverted"); + if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) + printf("-NarrowPulse"); + printf("\n"); } static int @@ -131,6 +132,55 @@ uart_pps_mode_sysctl(SYSCTL_HANDLER_ARGS) } static void +uart_pps_process(struct uart_softc *sc, int ser_sig) +{ + sbintime_t now; + int is_assert, pps_sig; + + /* Which signal is configured as PPS? Early out if none. */ + switch(sc->sc_pps_mode & UART_PPS_SIGNAL_MASK) { + case UART_PPS_CTS: + pps_sig = SER_CTS; + break; + case UART_PPS_DCD: + pps_sig = SER_DCD; + break; + default: + return; + } + + /* Early out if there is no change in the signal configured as PPS. */ + if ((ser_sig & SER_DELTA(pps_sig)) == 0) + return; + + /* + * In narrow-pulse mode we need to synthesize both capture and clear + * events from a single "delta occurred" indication from the uart + * hardware because the pulse width is too narrow to reliably detect + * both edges. However, when the pulse width is close to our interrupt + * processing latency we might intermittantly catch both edges. To + * guard against generating spurious events when that happens, we use a + * separate timer to ensure at least half a second elapses before we + * generate another event. + */ + pps_capture(&sc->sc_pps); + if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) { + now = getsbinuptime(); + if (now > sc->sc_pps_captime + 500 * SBT_1MS) { + sc->sc_pps_captime = now; + pps_event(&sc->sc_pps, PPS_CAPTUREASSERT); + pps_event(&sc->sc_pps, PPS_CAPTURECLEAR); + } + } else { + is_assert = ser_sig & pps_sig; + if (sc->sc_pps_mode & UART_PPS_INVERT_PULSE) + is_assert = !is_assert; + pps_event(&sc->sc_pps, is_assert ? PPS_CAPTUREASSERT : + PPS_CAPTURECLEAR); + } +} + +static void uart_pps_init(struct uart_softc *sc) { struct sysctl_ctx_list *ctx; @@ -147,23 +197,23 @@ uart_pps_init(struct uart_softc *sc) * for one specific device. */ #ifdef UART_PPS_ON_CTS - sc->sc_pps_mode = PPS_MODE_CTS; + sc->sc_pps_mode = UART_PPS_CTS; #else - sc->sc_pps_mode = PPS_MODE_DCD; + sc->sc_pps_mode = UART_PPS_DCD; #endif TUNABLE_INT_FETCH("hw.uart.pps_mode", &sc->sc_pps_mode); SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "pps_mode", CTLTYPE_INT | CTLFLAG_RWTUN, sc, 0, uart_pps_mode_sysctl, "I", - "pulse capturing mode - 0/1/2 - disabled/CTS/DCD"); + "pulse mode: 0/1/2=disabled/CTS/DCD; " + "add 0x10 to invert, 0x20 for narrow pulse"); if (!uart_pps_mode_valid(sc->sc_pps_mode)) { device_printf(sc->sc_dev, - "Invalid pps_mode %d configured; disabling PPS capture\n", + "Invalid pps_mode 0x%02x configured; disabling PPS capture\n", sc->sc_pps_mode); - sc->sc_pps_mode = PPS_MODE_DISABLED; + sc->sc_pps_mode = UART_PPS_DISABLED; } else if (bootverbose) { - device_printf(sc->sc_dev, "PPS capture mode %d (%s)\n", - sc->sc_pps_mode, uart_pps_mode_name(sc->sc_pps_mode)); + uart_pps_print_mode(sc); } sc->sc_pps.ppscap = PPS_CAPTUREBOTH; @@ -313,23 +363,16 @@ static __inline int uart_intr_sigchg(void *arg) { struct uart_softc *sc = arg; - int new, old, pps_sig, sig; + int new, old, sig; sig = UART_GETSIG(sc); /* - * Time pulse counting support. Note that both CTS and DCD are - * active-low signals. The status bit is high to indicate that - * the signal on the line is low, which corresponds to a PPS - * clear event. + * Time pulse counting support, invoked whenever the PPS parameters are + * currently set to capture either edge of the signal. */ if (sc->sc_pps.ppsparam.mode & PPS_CAPTUREBOTH) { - pps_sig = uart_pps_signal(sc->sc_pps_mode); - if (sig & SER_DELTA(pps_sig)) { - pps_capture(&sc->sc_pps); - pps_event(&sc->sc_pps, (sig & pps_sig) ? - PPS_CAPTURECLEAR : PPS_CAPTUREASSERT); - } + uart_pps_process(sc, sig); } /* diff --git a/sys/dev/uart/uart_dev_ns8250.c b/sys/dev/uart/uart_dev_ns8250.c index ee0b37badb08..ee21f43aa6cf 100644 --- a/sys/dev/uart/uart_dev_ns8250.c +++ b/sys/dev/uart/uart_dev_ns8250.c @@ -51,6 +51,7 @@ __FBSDID("$FreeBSD$"); #endif #include <dev/uart/uart_bus.h> #include <dev/uart/uart_dev_ns8250.h> +#include <dev/uart/uart_ppstypes.h> #include <dev/ic/ns16550.h> @@ -401,11 +402,40 @@ static struct ofw_compat_data compat_data[] = { UART_FDT_CLASS_AND_DEVICE(compat_data); #endif -#define SIGCHG(c, i, s, d) \ - if (c) { \ - i |= (i & s) ? s : s | d; \ - } else { \ - i = (i & s) ? (i & ~s) | d : i; \ +/* Use token-pasting to form SER_ and MSR_ named constants. */ +#define SER(sig) SER_##sig +#define SERD(sig) SER_D##sig +#define MSR(sig) MSR_##sig +#define MSRD(sig) MSR_D##sig + +/* + * Detect signal changes using software delta detection. The previous state of + * the signals is in 'var' the new hardware state is in 'msr', and 'sig' is the + * short name (DCD, CTS, etc) of the signal bit being processed; 'var' gets the + * new state of both the signal and the delta bits. + */ +#define SIGCHGSW(var, msr, sig) \ + if ((msr) & MSR(sig)) { \ + if ((var & SER(sig)) == 0) \ + var |= SERD(sig) | SER(sig); \ + } else { \ + if ((var & SER(sig)) != 0) \ + var = SERD(sig) | (var & ~SER(sig)); \ + } + +/* + * Detect signal changes using the hardware msr delta bits. This is currently + * used only when PPS timing information is being captured using the "narrow + * pulse" option. With a narrow PPS pulse the signal may not still be asserted + * by time the interrupt handler is invoked. The hardware will latch the fact + * that it changed in the delta bits. + */ +#define SIGCHGHW(var, msr, sig) \ + if ((msr) & MSRD(sig)) { \ + if (((msr) & MSR(sig)) != 0) \ + var |= SERD(sig) | SER(sig); \ + else \ + var = SERD(sig) | (var & ~SER(sig)); \ } int @@ -532,21 +562,37 @@ ns8250_bus_flush(struct uart_softc *sc, int what) int ns8250_bus_getsig(struct uart_softc *sc) { - uint32_t new, old, sig; + uint32_t old, sig; uint8_t msr; + /* + * The delta bits are reputed to be broken on some hardware, so use + * software delta detection by default. Use the hardware delta bits + * when capturing PPS pulses which are too narrow for software detection + * to see the edges. Hardware delta for RI doesn't work like the + * others, so always use software for it. Other threads may be changing + * other (non-MSR) bits in sc_hwsig, so loop until it can succesfully + * update without other changes happening. Note that the SIGCHGxx() + * macros carefully preserve the delta bits when we have to loop several + * times and a signal transitions between iterations. + */ do { old = sc->sc_hwsig; sig = old; uart_lock(sc->sc_hwmtx); msr = uart_getreg(&sc->sc_bas, REG_MSR); uart_unlock(sc->sc_hwmtx); - SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR); - SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS); - SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD); - SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI); - new = sig & ~SER_MASK_DELTA; - } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); + if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) { + SIGCHGHW(sig, msr, DSR); + SIGCHGHW(sig, msr, CTS); + SIGCHGHW(sig, msr, DCD); + } else { + SIGCHGSW(sig, msr, DSR); + SIGCHGSW(sig, msr, CTS); + SIGCHGSW(sig, msr, DCD); + } + SIGCHGSW(sig, msr, RI); + } while (!atomic_cmpset_32(&sc->sc_hwsig, old, sig & ~SER_MASK_DELTA)); return (sig); } @@ -900,12 +946,10 @@ ns8250_bus_setsig(struct uart_softc *sc, int sig) old = sc->sc_hwsig; new = old; if (sig & SER_DDTR) { - SIGCHG(sig & SER_DTR, new, SER_DTR, - SER_DDTR); + new = (new & ~SER_DTR) | (sig & (SER_DTR | SER_DDTR)); } if (sig & SER_DRTS) { - SIGCHG(sig & SER_RTS, new, SER_RTS, - SER_DRTS); + new = (new & ~SER_RTS) | (sig & (SER_RTS | SER_DRTS)); } } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); uart_lock(sc->sc_hwmtx); diff --git a/sys/dev/uart/uart_ppstypes.h b/sys/dev/uart/uart_ppstypes.h new file mode 100644 index 000000000000..142d0f19c992 --- /dev/null +++ b/sys/dev/uart/uart_ppstypes.h @@ -0,0 +1,46 @@ +/*- + * Copyright (c) 2015 Ian Lepore + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _DEV_UART_PPSTYPES_H_ +#define _DEV_UART_PPSTYPES_H_ + +/* + * These constants are shared by several drivers including uart and usb_serial. + */ + +#define UART_PPS_SIGNAL_MASK 0x0f +#define UART_PPS_OPTION_MASK 0xf0 + +#define UART_PPS_DISABLED 0x00 +#define UART_PPS_CTS 0x01 +#define UART_PPS_DCD 0x02 + +#define UART_PPS_INVERT_PULSE 0x10 +#define UART_PPS_NARROW_PULSE 0x20 + +#endif /* _DEV_UART_PPSTYPES_H_ */ diff --git a/usr.sbin/ypldap/yp.c b/usr.sbin/ypldap/yp.c index e46113636d44..367624574cea 100644 --- a/usr.sbin/ypldap/yp.c +++ b/usr.sbin/ypldap/yp.c @@ -83,10 +83,10 @@ void yp_enable_events(void) { int i; - extern fd_set svc_fdset; + extern fd_set svc_fdset; struct yp_event *ye; - for (i = 0; i < getdtablesize(); i++) { + for (i = 0; i < FD_SETSIZE; i++) { if (FD_ISSET(i, &svc_fdset)) { if ((ye = calloc(1, sizeof(*ye))) == NULL) fatal(NULL); diff --git a/usr.sbin/ypldap/ypldap.conf.5 b/usr.sbin/ypldap/ypldap.conf.5 index 5c22b3ba51cc..5c936a95e741 100644 --- a/usr.sbin/ypldap/ypldap.conf.5 +++ b/usr.sbin/ypldap/ypldap.conf.5 @@ -15,7 +15,7 @@ .\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF .\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. .\" -.Dd $Mdocdate: April 30 2012 $ +.Dd $Mdocdate: January 13 2016 $ .Dt YPLDAP.CONF 5 .Os .Sh NAME @@ -155,6 +155,9 @@ Use the supplied LDAP filter to retrieve password entries. .It Pa /etc/ypldap.conf .Xr ypldap 8 configuration file. +.It Pa /usr/share/example/ypldap/ypldap.conf +.Xr ypldap 8 +configuration file example. .El .Sh SEE ALSO .Xr ypbind 8 , |