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-rw-r--r--share/man/man9/atomic.913
-rw-r--r--sys/sys/atomic_common.h2
2 files changed, 14 insertions, 1 deletions
diff --git a/share/man/man9/atomic.9 b/share/man/man9/atomic.9
index 39a4fa9c6f96..397a8fcd6b18 100644
--- a/share/man/man9/atomic.9
+++ b/share/man/man9/atomic.9
@@ -22,7 +22,7 @@
.\"
.\" $FreeBSD$
.\"
-.Dd August 18, 2019
+.Dd February 24, 2021
.Dt ATOMIC 9
.Os
.Sh NAME
@@ -31,6 +31,7 @@
.Nm atomic_cmpset ,
.Nm atomic_fcmpset ,
.Nm atomic_fetchadd ,
+.Nm atomic_interrupt_fence ,
.Nm atomic_load ,
.Nm atomic_readandclear ,
.Nm atomic_set ,
@@ -59,6 +60,8 @@
.Fc
.Ft <type>
.Fn atomic_fetchadd_<type> "volatile <type> *p" "<type> v"
+.Ft void
+.Fn atomic_interrupt_fence "void"
.Ft <type>
.Fn atomic_load_[acq_]<type> "volatile <type> *p"
.Ft <type>
@@ -292,6 +295,14 @@ release stores, by separating access from ordering, they can sometimes
facilitate more efficient implementations of synchronization primitives.
For example, they can be used to avoid executing a memory barrier until a
memory access shows that some condition is satisfied.
+.Ss Interrupt Fence Operations
+The
+.Fn atomic_interrupt_fence()
+function establishes ordering between its call location and any interrupt
+handler executing on the same CPU.
+It is modeled after the similar C11 function
+.Fn atomic_signal_fence() ,
+and adapted for the kernel environment.
.Ss Multiple Processors
In multiprocessor systems, the atomicity of the atomic operations on memory
depends on support for cache coherence in the underlying architecture.
diff --git a/sys/sys/atomic_common.h b/sys/sys/atomic_common.h
index 48f0a8b8939c..403b3de8a092 100644
--- a/sys/sys/atomic_common.h
+++ b/sys/sys/atomic_common.h
@@ -78,4 +78,6 @@
#define atomic_load_consume_ptr(p) \
((__typeof(*p)) atomic_load_acq_ptr((uintptr_t *)p))
+#define atomic_interrupt_fence() __compiler_membar()
+
#endif