diff options
Diffstat (limited to 'Bindings/interrupt-controller')
34 files changed, 115 insertions, 59 deletions
diff --git a/Bindings/interrupt-controller/abilis,tb10x-ictl.txt b/Bindings/interrupt-controller/abilis,tb10x-ictl.txt index 9d52d5afe3e9..5a4dd263fc12 100644 --- a/Bindings/interrupt-controller/abilis,tb10x-ictl.txt +++ b/Bindings/interrupt-controller/abilis,tb10x-ictl.txt @@ -13,7 +13,6 @@ Required properties - interrupt-congroller: Identifies the node as an interrupt controller. - #interrupt cells: Specifies the number of cells used to encode an interrupt source connected to this controller. The value shall be 2. -- interrupt-parent: Specifies the parent interrupt controller. - interrupts: Specifies the list of interrupt lines which are handled by the interrupt controller in the parent controller's notation. Interrupts are mapped one-to-one to parent interrupts. diff --git a/Bindings/interrupt-controller/al,alpine-msix.txt b/Bindings/interrupt-controller/al,alpine-msix.txt index f6f1c14bf99b..5669764f9cc9 100644 --- a/Bindings/interrupt-controller/al,alpine-msix.txt +++ b/Bindings/interrupt-controller/al,alpine-msix.txt @@ -6,7 +6,6 @@ Required properties: - compatible: should be "al,alpine-msix" - reg: physical base address and size of the registers -- interrupt-parent: specifies the parent interrupt controller. - interrupt-controller: identifies the node as an interrupt controller - msi-controller: identifies the node as an PCI Message Signaled Interrupt controller diff --git a/Bindings/interrupt-controller/allwinner,sunxi-nmi.txt b/Bindings/interrupt-controller/allwinner,sunxi-nmi.txt index 4903fb72d883..24beadf7ba83 100644 --- a/Bindings/interrupt-controller/allwinner,sunxi-nmi.txt +++ b/Bindings/interrupt-controller/allwinner,sunxi-nmi.txt @@ -13,7 +13,6 @@ Required properties: - #interrupt-cells : Specifies the number of cells needed to encode an interrupt source. The value shall be 2. The first cell is the IRQ number, the second cell the trigger type as defined in interrupt.txt in this directory. -- interrupt-parent: Specifies the parent interrupt controller. - interrupts: Specifies the interrupt line (NMI) which is handled by the interrupt controller in the parent controller's notation. This value shall be the NMI. diff --git a/Bindings/interrupt-controller/amlogic,meson-gpio-intc.txt b/Bindings/interrupt-controller/amlogic,meson-gpio-intc.txt index 89674ad8a097..1502a51548bb 100644 --- a/Bindings/interrupt-controller/amlogic,meson-gpio-intc.txt +++ b/Bindings/interrupt-controller/amlogic,meson-gpio-intc.txt @@ -15,9 +15,6 @@ Required properties: "amlogic,meson-gxbb-gpio-intc" for GXBB SoCs (S905) or "amlogic,meson-gxl-gpio-intc" for GXL SoCs (S905X, S912) "amlogic,meson-axg-gpio-intc" for AXG SoCs (A113D, A113X) -- interrupt-parent : a phandle to the GIC the interrupts are routed to. - Usually this is provided at the root level of the device tree as it is - common to most of the SoC. - reg : Specifies base physical address and size of the registers. - interrupt-controller : Identifies the node as an interrupt controller. - #interrupt-cells : Specifies the number of cells needed to encode an diff --git a/Bindings/interrupt-controller/atmel,aic.txt b/Bindings/interrupt-controller/atmel,aic.txt index 0e9f09a6a2fe..f4c5d34c4111 100644 --- a/Bindings/interrupt-controller/atmel,aic.txt +++ b/Bindings/interrupt-controller/atmel,aic.txt @@ -4,7 +4,6 @@ Required properties: - compatible: Should be "atmel,<chip>-aic" <chip> can be "at91rm9200", "sama5d2", "sama5d3" or "sama5d4" - interrupt-controller: Identifies the node as an interrupt controller. -- interrupt-parent: For single AIC system, it is an empty property. - #interrupt-cells: The number of cells to define the interrupts. It should be 3. The first cell is the IRQ number (aka "Peripheral IDentifier" on datasheet). The second cell is used to specify flags: @@ -27,7 +26,6 @@ Examples: aic: interrupt-controller@fffff000 { compatible = "atmel,at91rm9200-aic"; interrupt-controller; - interrupt-parent; #interrupt-cells = <3>; reg = <0xfffff000 0x200>; }; diff --git a/Bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt b/Bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt index 6428a6ba9f4a..0f1af5a1c12e 100644 --- a/Bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt +++ b/Bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt @@ -26,8 +26,6 @@ Required properties: are 0..7 for bank 0, and 0..31 for bank 1. Additional required properties for brcm,bcm2836-armctrl-ic: -- interrupt-parent : Specifies the parent interrupt controller when this - controller is the second level. - interrupts : Specifies the interrupt on the parent for this interrupt controller to handle. diff --git a/Bindings/interrupt-controller/brcm,bcm3380-l2-intc.txt b/Bindings/interrupt-controller/brcm,bcm3380-l2-intc.txt index 8f48aad50868..37aea40d5430 100644 --- a/Bindings/interrupt-controller/brcm,bcm3380-l2-intc.txt +++ b/Bindings/interrupt-controller/brcm,bcm3380-l2-intc.txt @@ -18,8 +18,6 @@ Required properties: - interrupt-controller: identifies the node as an interrupt controller - #interrupt-cells: specifies the number of cells needed to encode an interrupt source, should be 1. -- interrupt-parent: specifies the phandle to the parent interrupt controller - this one is cascaded from - interrupts: specifies the interrupt line in the interrupt-parent controller node, valid values depend on the type of parent interrupt controller diff --git a/Bindings/interrupt-controller/brcm,bcm6345-l1-intc.txt b/Bindings/interrupt-controller/brcm,bcm6345-l1-intc.txt index 4040905388d9..2bc19b1ac877 100644 --- a/Bindings/interrupt-controller/brcm,bcm6345-l1-intc.txt +++ b/Bindings/interrupt-controller/brcm,bcm6345-l1-intc.txt @@ -29,8 +29,6 @@ Required properties: - interrupt-controller: identifies the node as an interrupt controller - #interrupt-cells: specifies the number of cells needed to encode an interrupt source, should be 1. -- interrupt-parent: specifies the phandle to the parent interrupt controller(s) - this one is cascaded from - interrupts: specifies the interrupt line(s) in the interrupt-parent controller node; valid values depend on the type of parent interrupt controller diff --git a/Bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt b/Bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt index cc217b22dccd..2117d4ac1ae5 100644 --- a/Bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt +++ b/Bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt @@ -28,8 +28,6 @@ Required properties: - interrupt-controller: identifies the node as an interrupt controller - #interrupt-cells: specifies the number of cells needed to encode an interrupt source, should be 1. -- interrupt-parent: specifies the phandle to the parent interrupt controller(s) - this one is cascaded from - interrupts: specifies the interrupt line(s) in the interrupt-parent controller node; valid values depend on the type of parent interrupt controller diff --git a/Bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt b/Bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt index 44a9bb15dd56..addd86b6ca2f 100644 --- a/Bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt +++ b/Bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt @@ -56,8 +56,6 @@ Required properties: - interrupt-controller: identifies the node as an interrupt controller - #interrupt-cells: specifies the number of cells needed to encode an interrupt source, should be 1. -- interrupt-parent: specifies the phandle to the parent interrupt controller - this one is cascaded from - interrupts: specifies the interrupt line(s) in the interrupt-parent controller node, valid values depend on the type of parent interrupt controller - brcm,int-map-mask: 32-bits bit mask describing how many and which interrupts diff --git a/Bindings/interrupt-controller/brcm,l2-intc.txt b/Bindings/interrupt-controller/brcm,l2-intc.txt index 36df06c5c567..d514ec060a4a 100644 --- a/Bindings/interrupt-controller/brcm,l2-intc.txt +++ b/Bindings/interrupt-controller/brcm,l2-intc.txt @@ -8,8 +8,6 @@ Required properties: - interrupt-controller: identifies the node as an interrupt controller - #interrupt-cells: specifies the number of cells needed to encode an interrupt source. Should be 1. -- interrupt-parent: specifies the phandle to the parent interrupt controller - this controller is cacaded from - interrupts: specifies the interrupt line in the interrupt-parent irq space to be used for cascading diff --git a/Bindings/interrupt-controller/fsl,ls-scfg-msi.txt b/Bindings/interrupt-controller/fsl,ls-scfg-msi.txt index a4ff93d6b7f3..454ce04d6787 100644 --- a/Bindings/interrupt-controller/fsl,ls-scfg-msi.txt +++ b/Bindings/interrupt-controller/fsl,ls-scfg-msi.txt @@ -13,9 +13,6 @@ Required properties: - reg: physical base address of the controller and length of memory mapped. - interrupts: an interrupt to the parent interrupt controller. -Optional properties: -- interrupt-parent: the phandle to the parent interrupt controller. - This interrupt controller hardware is a second level interrupt controller that is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based platforms. If interrupt-parent is not provided, the default parent interrupt diff --git a/Bindings/interrupt-controller/hisilicon,mbigen-v2.txt b/Bindings/interrupt-controller/hisilicon,mbigen-v2.txt index 3b2f4c43ad8d..a6813a071f15 100644 --- a/Bindings/interrupt-controller/hisilicon,mbigen-v2.txt +++ b/Bindings/interrupt-controller/hisilicon,mbigen-v2.txt @@ -68,8 +68,6 @@ Examples: Devices connect to mbigen required properties: ---------------------------------------------------- --interrupt-parent: Specifies the mbigen device node which device connected. - -interrupts:Specifies the interrupt source. For the specific information of each cell in this property,please refer to the "interrupt-cells" description mentioned above. diff --git a/Bindings/interrupt-controller/ingenic,intc.txt b/Bindings/interrupt-controller/ingenic,intc.txt index 5f89fb635a1b..d4373d0f7121 100644 --- a/Bindings/interrupt-controller/ingenic,intc.txt +++ b/Bindings/interrupt-controller/ingenic,intc.txt @@ -4,6 +4,7 @@ Required properties: - compatible : should be "ingenic,<socname>-intc". Valid strings are: ingenic,jz4740-intc + ingenic,jz4725b-intc ingenic,jz4770-intc ingenic,jz4775-intc ingenic,jz4780-intc @@ -11,7 +12,6 @@ Required properties: - interrupt-controller : Identifies the node as an interrupt controller - #interrupt-cells : Specifies the number of cells needed to encode an interrupt source. The value shall be 1. -- interrupt-parent : phandle of the CPU interrupt controller. - interrupts : Specifies the CPU interrupt the controller is connected to. Example: diff --git a/Bindings/interrupt-controller/marvell,odmi-controller.txt b/Bindings/interrupt-controller/marvell,odmi-controller.txt index 3f6442c7f867..930fb462fd9f 100644 --- a/Bindings/interrupt-controller/marvell,odmi-controller.txt +++ b/Bindings/interrupt-controller/marvell,odmi-controller.txt @@ -26,8 +26,6 @@ Required properties: See Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt for details about the GIC Device Tree binding. -- interrupt-parent : Reference to the parent interrupt controller. - Example: odmi: odmi@300000 { diff --git a/Bindings/interrupt-controller/mediatek,cirq.txt b/Bindings/interrupt-controller/mediatek,cirq.txt index a7efdbc3de5b..5865f4f2c69d 100644 --- a/Bindings/interrupt-controller/mediatek,cirq.txt +++ b/Bindings/interrupt-controller/mediatek,cirq.txt @@ -16,8 +16,6 @@ Required properties: and "mediatek,cirq" as a fallback. - interrupt-controller : Identifies the node as an interrupt controller. - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt. -- interrupt-parent: phandle of irq parent for cirq. The parent must - use the same interrupt-cells format as GIC. - reg: Physical base address of the cirq registers and length of memory mapped region. - mediatek,ext-irq-range: Identifies external irq number range in different diff --git a/Bindings/interrupt-controller/mediatek,sysirq.txt b/Bindings/interrupt-controller/mediatek,sysirq.txt index 07bf0b9a5139..33a98eb44949 100644 --- a/Bindings/interrupt-controller/mediatek,sysirq.txt +++ b/Bindings/interrupt-controller/mediatek,sysirq.txt @@ -11,6 +11,7 @@ Required properties: "mediatek,mt7622-sysirq", "mediatek,mt6577-sysirq": for MT7622 "mediatek,mt6795-sysirq", "mediatek,mt6577-sysirq": for MT6795 "mediatek,mt6797-sysirq", "mediatek,mt6577-sysirq": for MT6797 + "mediatek,mt6765-sysirq", "mediatek,mt6577-sysirq": for MT6765 "mediatek,mt6755-sysirq", "mediatek,mt6577-sysirq": for MT6755 "mediatek,mt6592-sysirq", "mediatek,mt6577-sysirq": for MT6592 "mediatek,mt6589-sysirq", "mediatek,mt6577-sysirq": for MT6589 @@ -21,8 +22,6 @@ Required properties: "mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq": for MT2701 - interrupt-controller : Identifies the node as an interrupt controller - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt. -- interrupt-parent: phandle of irq parent for sysirq. The parent must - use the same interrupt-cells format as GIC. - reg: Physical base address of the intpol registers and length of memory mapped region. Could be multiple bases here. Ex: mt6797 needs 2 reg, others need 1. diff --git a/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt b/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt index b47a8a02b17b..f5baeccb689f 100644 --- a/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt +++ b/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt @@ -7,7 +7,6 @@ Required properties: - interrupt-controller : Identifies the node as an interrupt controller - #interrupt-cells : Specifies the number of cells needed to encode an interrupt source. The value shall be 1. -- interrupt-parent : phandle of the CPU interrupt controller. - interrupts : Specifies the CPU interrupt the controller is connected to. Example: diff --git a/Bindings/interrupt-controller/nvidia,tegra20-ictlr.txt b/Bindings/interrupt-controller/nvidia,tegra20-ictlr.txt index f246ccbf8838..2ff356640100 100644 --- a/Bindings/interrupt-controller/nvidia,tegra20-ictlr.txt +++ b/Bindings/interrupt-controller/nvidia,tegra20-ictlr.txt @@ -19,8 +19,6 @@ Required properties: - interrupt-controller : Identifies the node as an interrupt controller. - #interrupt-cells : Specifies the number of cells needed to encode an interrupt source. The value must be 3. -- interrupt-parent : a phandle to the GIC these interrupts are routed - to. Notes: diff --git a/Bindings/interrupt-controller/nxp,lpc3220-mic.txt b/Bindings/interrupt-controller/nxp,lpc3220-mic.txt index 38211f344dc8..0bfb3ba55f4c 100644 --- a/Bindings/interrupt-controller/nxp,lpc3220-mic.txt +++ b/Bindings/interrupt-controller/nxp,lpc3220-mic.txt @@ -14,8 +14,6 @@ Required properties: Reset value is IRQ_TYPE_LEVEL_LOW. Optional properties: -- interrupt-parent: empty for MIC interrupt controller, link to parent - MIC interrupt controller for SIC1 and SIC2 - interrupts: empty for MIC interrupt controller, cascaded MIC hardware interrupts for SIC1 and SIC2 diff --git a/Bindings/interrupt-controller/qca,ath79-misc-intc.txt b/Bindings/interrupt-controller/qca,ath79-misc-intc.txt index 475ae9bd562b..ad70006c1848 100644 --- a/Bindings/interrupt-controller/qca,ath79-misc-intc.txt +++ b/Bindings/interrupt-controller/qca,ath79-misc-intc.txt @@ -7,7 +7,6 @@ Required Properties: - compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc" or "qca,<soctype>-cpu-intc", "qca,ar7240-misc-intc" - reg: Base address and size of the controllers memory area -- interrupt-parent: phandle of the parent interrupt controller. - interrupts: Interrupt specifier for the controllers interrupt. - interrupt-controller : Identifies the node as an interrupt controller - #interrupt-cells : Specifies the number of cells needed to encode interrupt diff --git a/Bindings/interrupt-controller/qcom,pdc.txt b/Bindings/interrupt-controller/qcom,pdc.txt index 0b2c97ddb520..8e0797cb1487 100644 --- a/Bindings/interrupt-controller/qcom,pdc.txt +++ b/Bindings/interrupt-controller/qcom,pdc.txt @@ -35,12 +35,6 @@ Properties: interrupt. The second element is the trigger type. -- interrupt-parent: - Usage: required - Value type: <phandle> - Definition: Specifies the interrupt parent necessary for hierarchical - domain to operate. - - interrupt-controller: Usage: required Value type: <bool> diff --git a/Bindings/interrupt-controller/renesas,irqc.txt b/Bindings/interrupt-controller/renesas,irqc.txt index 20f121daa910..a046ed374d80 100644 --- a/Bindings/interrupt-controller/renesas,irqc.txt +++ b/Bindings/interrupt-controller/renesas,irqc.txt @@ -7,15 +7,18 @@ Required properties: - "renesas,irqc-r8a73a4" (R-Mobile APE6) - "renesas,irqc-r8a7743" (RZ/G1M) - "renesas,irqc-r8a7745" (RZ/G1E) + - "renesas,irqc-r8a77470" (RZ/G1C) - "renesas,irqc-r8a7790" (R-Car H2) - "renesas,irqc-r8a7791" (R-Car M2-W) - "renesas,irqc-r8a7792" (R-Car V2H) - "renesas,irqc-r8a7793" (R-Car M2-N) - "renesas,irqc-r8a7794" (R-Car E2) + - "renesas,intc-ex-r8a774a1" (RZ/G2M) - "renesas,intc-ex-r8a7795" (R-Car H3) - "renesas,intc-ex-r8a7796" (R-Car M3-W) - "renesas,intc-ex-r8a77965" (R-Car M3-N) - "renesas,intc-ex-r8a77970" (R-Car V3M) + - "renesas,intc-ex-r8a77980" (R-Car V3H) - "renesas,intc-ex-r8a77995" (R-Car D3) - #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in interrupts.txt in this directory diff --git a/Bindings/interrupt-controller/riscv,cpu-intc.txt b/Bindings/interrupt-controller/riscv,cpu-intc.txt new file mode 100644 index 000000000000..265b223cd978 --- /dev/null +++ b/Bindings/interrupt-controller/riscv,cpu-intc.txt @@ -0,0 +1,52 @@ +RISC-V Hart-Level Interrupt Controller (HLIC) +--------------------------------------------- + +RISC-V cores include Control Status Registers (CSRs) which are local to each +CPU core (HART in RISC-V terminology) and can be read or written by software. +Some of these CSRs are used to control local interrupts connected to the core. +Every interrupt is ultimately routed through a hart's HLIC before it +interrupts that hart. + +The RISC-V supervisor ISA manual specifies three interrupt sources that are +attached to every HLIC: software interrupts, the timer interrupt, and external +interrupts. Software interrupts are used to send IPIs between cores. The +timer interrupt comes from an architecturally mandated real-time timer that is +controlled via Supervisor Binary Interface (SBI) calls and CSR reads. External +interrupts connect all other device interrupts to the HLIC, which are routed +via the platform-level interrupt controller (PLIC). + +All RISC-V systems that conform to the supervisor ISA specification are +required to have a HLIC with these three interrupt sources present. Since the +interrupt map is defined by the ISA it's not listed in the HLIC's device tree +entry, though external interrupt controllers (like the PLIC, for example) will +need to define how their interrupts map to the relevant HLICs. This means +a PLIC interrupt property will typically list the HLICs for all present HARTs +in the system. + +Required properties: +- compatible : "riscv,cpu-intc" +- #interrupt-cells : should be <1>. The interrupt sources are defined by the + RISC-V supervisor ISA manual, with only the following three interrupts being + defined for supervisor mode: + - Source 1 is the supervisor software interrupt, which can be sent by an SBI + call and is reserved for use by software. + - Source 5 is the supervisor timer interrupt, which can be configured by + SBI calls and implements a one-shot timer. + - Source 9 is the supervisor external interrupt, which chains to all other + device interrupts. +- interrupt-controller : Identifies the node as an interrupt controller + +Furthermore, this interrupt-controller MUST be embedded inside the cpu +definition of the hart whose CSRs control these local interrupts. + +An example device tree entry for a HLIC is show below. + + cpu1: cpu@1 { + compatible = "riscv"; + ... + cpu1-intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "sifive,fu540-c000-cpu-intc", "riscv,cpu-intc"; + interrupt-controller; + }; + }; diff --git a/Bindings/interrupt-controller/samsung,exynos4210-combiner.txt b/Bindings/interrupt-controller/samsung,exynos4210-combiner.txt index 9e5f73412cd7..19af687858a1 100644 --- a/Bindings/interrupt-controller/samsung,exynos4210-combiner.txt +++ b/Bindings/interrupt-controller/samsung,exynos4210-combiner.txt @@ -32,8 +32,6 @@ Optional properties: - samsung,combiner-nr: The number of interrupt combiners supported. If this property is not specified, the default number of combiners is assumed to be 16. -- interrupt-parent: pHandle of the parent interrupt controller, if not - inherited from the parent node. Example: diff --git a/Bindings/interrupt-controller/sifive,plic-1.0.0.txt b/Bindings/interrupt-controller/sifive,plic-1.0.0.txt new file mode 100644 index 000000000000..6adf7a6e8825 --- /dev/null +++ b/Bindings/interrupt-controller/sifive,plic-1.0.0.txt @@ -0,0 +1,58 @@ +SiFive Platform-Level Interrupt Controller (PLIC) +------------------------------------------------- + +SiFive SOCs include an implementation of the Platform-Level Interrupt Controller +(PLIC) high-level specification in the RISC-V Privileged Architecture +specification. The PLIC connects all external interrupts in the system to all +hart contexts in the system, via the external interrupt source in each hart. + +A hart context is a privilege mode in a hardware execution thread. For example, +in an 4 core system with 2-way SMT, you have 8 harts and probably at least two +privilege modes per hart; machine mode and supervisor mode. + +Each interrupt can be enabled on per-context basis. Any context can claim +a pending enabled interrupt and then release it once it has been handled. + +Each interrupt has a configurable priority. Higher priority interrupts are +serviced first. Each context can specify a priority threshold. Interrupts +with priority below this threshold will not cause the PLIC to raise its +interrupt line leading to the context. + +While the PLIC supports both edge-triggered and level-triggered interrupts, +interrupt handlers are oblivious to this distinction and therefore it is not +specified in the PLIC device-tree binding. + +While the RISC-V ISA doesn't specify a memory layout for the PLIC, the +"sifive,plic-1.0.0" device is a concrete implementation of the PLIC that +contains a specific memory layout, which is documented in chapter 8 of the +SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>. + +Required properties: +- compatible : "sifive,plic-1.0.0" and a string identifying the actual + detailed implementation in case that specific bugs need to be worked around. +- #address-cells : should be <0> or more. +- #interrupt-cells : should be <1> or more. +- interrupt-controller : Identifies the node as an interrupt controller. +- reg : Should contain 1 register range (address and length). +- interrupts-extended : Specifies which contexts are connected to the PLIC, + with "-1" specifying that a context is not present. Each node pointed + to should be a riscv,cpu-intc node, which has a riscv node as parent. +- riscv,ndev: Specifies how many external interrupts are supported by + this controller. + +Example: + + plic: interrupt-controller@c000000 { + #address-cells = <0>; + #interrupt-cells = <1>; + compatible = "sifive,plic-1.0.0", "sifive,fu540-c000-plic"; + interrupt-controller; + interrupts-extended = < + &cpu0-intc 11 + &cpu1-intc 11 &cpu1-intc 9 + &cpu2-intc 11 &cpu2-intc 9 + &cpu3-intc 11 &cpu3-intc 9 + &cpu4-intc 11 &cpu4-intc 9>; + reg = <0xc000000 0x4000000>; + riscv,ndev = <10>; + }; diff --git a/Bindings/interrupt-controller/sigma,smp8642-intc.txt b/Bindings/interrupt-controller/sigma,smp8642-intc.txt index 1f441fa0ad40..355c18a3a4d3 100644 --- a/Bindings/interrupt-controller/sigma,smp8642-intc.txt +++ b/Bindings/interrupt-controller/sigma,smp8642-intc.txt @@ -4,7 +4,6 @@ Required properties: - compatible: should be "sigma,smp8642-intc" - reg: physical address of MMIO region - ranges: address space mapping of child nodes -- interrupt-parent: phandle of parent interrupt controller - interrupt-controller: boolean - #address-cells: should be <1> - #size-cells: should be <1> diff --git a/Bindings/interrupt-controller/snps,archs-idu-intc.txt b/Bindings/interrupt-controller/snps,archs-idu-intc.txt index 8b46a34e05f1..09fc02b99845 100644 --- a/Bindings/interrupt-controller/snps,archs-idu-intc.txt +++ b/Bindings/interrupt-controller/snps,archs-idu-intc.txt @@ -7,7 +7,6 @@ Properties: - compatible: "snps,archs-idu-intc" - interrupt-controller: This is an interrupt controller. -- interrupt-parent: <reference to parent core intc> - #interrupt-cells: Must be <1>. Value of the cell specifies the "common" IRQ from peripheral to IDU. Number N diff --git a/Bindings/interrupt-controller/snps,dw-apb-ictl.txt b/Bindings/interrupt-controller/snps,dw-apb-ictl.txt index 492911744ca3..086ff08322db 100644 --- a/Bindings/interrupt-controller/snps,dw-apb-ictl.txt +++ b/Bindings/interrupt-controller/snps,dw-apb-ictl.txt @@ -11,7 +11,6 @@ Required properties: - interrupt-controller: identifies the node as an interrupt controller - #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1 - interrupts: interrupt reference to primary interrupt controller -- interrupt-parent: (optional) reference specific primary interrupt controller The interrupt sources map to the corresponding bits in the interrupt registers, i.e. diff --git a/Bindings/interrupt-controller/socionext,synquacer-exiu.txt b/Bindings/interrupt-controller/socionext,synquacer-exiu.txt index 8b2faefe29ca..dac0846fe789 100644 --- a/Bindings/interrupt-controller/socionext,synquacer-exiu.txt +++ b/Bindings/interrupt-controller/socionext,synquacer-exiu.txt @@ -12,7 +12,6 @@ Required properties: - interrupt-controller : Identifies the node as an interrupt controller. - #interrupt-cells : Specifies the number of cells needed to encode an interrupt source. The value must be 3. -- interrupt-parent : phandle of the GIC these interrupts are routed to. - socionext,spi-base : The SPI number of the first SPI of the 32 adjacent ones the EXIU forwards its interrups to. diff --git a/Bindings/interrupt-controller/st,spear3xx-shirq.txt b/Bindings/interrupt-controller/st,spear3xx-shirq.txt index 2ab0ea39867b..a407c499b3cc 100644 --- a/Bindings/interrupt-controller/st,spear3xx-shirq.txt +++ b/Bindings/interrupt-controller/st,spear3xx-shirq.txt @@ -31,10 +31,6 @@ Required properties: parent) is equal to number of groups. The format of the interrupt specifier depends in the interrupt parent controller. - Optional properties: - - interrupt-parent: pHandle of the parent interrupt controller, if not - inherited from the parent node. - Example: The following is an example from the SPEAr320 SoC dtsi file. diff --git a/Bindings/interrupt-controller/technologic,ts4800.txt b/Bindings/interrupt-controller/technologic,ts4800.txt index 7f15f1b0325b..341ae5909333 100644 --- a/Bindings/interrupt-controller/technologic,ts4800.txt +++ b/Bindings/interrupt-controller/technologic,ts4800.txt @@ -11,6 +11,4 @@ Required properties: region - #interrupt-cells: specifies the number of cells needed to encode an interrupt source, should be 1. -- interrupt-parent: phandle to the parent interrupt controller this one is - cascaded from - interrupts: specifies the interrupt line in the interrupt-parent controller diff --git a/Bindings/interrupt-controller/ti,c64x+megamod-pic.txt b/Bindings/interrupt-controller/ti,c64x+megamod-pic.txt index 42bb796cc4ad..ee3f9c351501 100644 --- a/Bindings/interrupt-controller/ti,c64x+megamod-pic.txt +++ b/Bindings/interrupt-controller/ti,c64x+megamod-pic.txt @@ -46,7 +46,6 @@ C6X Interrupt Chips - interrupt-controller - #interrupt-cells: <1> - reg: base address and size of register area - - interrupt-parent: must be core interrupt controller - interrupts: This should have four cells; one for each interrupt combiner. The cells contain the core priority interrupt to which the corresponding combiner output is wired. diff --git a/Bindings/interrupt-controller/ti,omap4-wugen-mpu b/Bindings/interrupt-controller/ti,omap4-wugen-mpu index 18d4f407bf0e..422d6908f8b2 100644 --- a/Bindings/interrupt-controller/ti,omap4-wugen-mpu +++ b/Bindings/interrupt-controller/ti,omap4-wugen-mpu @@ -12,8 +12,6 @@ Required properties: - interrupt-controller : Identifies the node as an interrupt controller. - #interrupt-cells : Specifies the number of cells needed to encode an interrupt source. The value must be 3. -- interrupt-parent : a phandle to the GIC these interrupts are routed - to. Notes: |