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-rw-r--r--Bindings/spi/amlogic,meson-gx-spicc.yaml4
-rw-r--r--Bindings/spi/brcm,spi-bcm-qspi.yaml198
-rw-r--r--Bindings/spi/cdns,qspi-nor.yaml143
-rw-r--r--Bindings/spi/fsl,spi-fsl-qspi.yaml96
-rw-r--r--Bindings/spi/mediatek,spi-mtk-nor.yaml1
-rw-r--r--Bindings/spi/spi-controller.yaml21
-rw-r--r--Bindings/spi/spi-mt65xx.txt2
-rw-r--r--Bindings/spi/spi-mux.yaml10
-rw-r--r--Bindings/spi/spi-nxp-fspi.txt2
-rw-r--r--Bindings/spi/spi-slave-mt27xx.txt1
-rw-r--r--Bindings/spi/st,stm32-spi.yaml6
11 files changed, 459 insertions, 25 deletions
diff --git a/Bindings/spi/amlogic,meson-gx-spicc.yaml b/Bindings/spi/amlogic,meson-gx-spicc.yaml
index 667dedefd69f..e3fb553d9180 100644
--- a/Bindings/spi/amlogic,meson-gx-spicc.yaml
+++ b/Bindings/spi/amlogic,meson-gx-spicc.yaml
@@ -90,8 +90,8 @@ examples:
#address-cells = <1>;
#size-cells = <0>;
- ethernet-switch@0 {
- compatible = "micrel,ks8995m";
+ display@0 {
+ compatible = "lg,lg4573";
spi-max-frequency = <1000000>;
reg = <0>;
};
diff --git a/Bindings/spi/brcm,spi-bcm-qspi.yaml b/Bindings/spi/brcm,spi-bcm-qspi.yaml
new file mode 100644
index 000000000000..6ee19d49fd3c
--- /dev/null
+++ b/Bindings/spi/brcm,spi-bcm-qspi.yaml
@@ -0,0 +1,198 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/brcm,spi-bcm-qspi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom SPI controller
+
+maintainers:
+ - Kamal Dasu <kdasu.kdev@gmail.com>
+ - Rafał Miłecki <rafal@milecki.pl>
+
+description: |
+ The Broadcom SPI controller is a SPI master found on various SOCs, including
+ BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consits
+ of:
+ MSPI : SPI master controller can read and write to a SPI slave device
+ BSPI : Broadcom SPI in combination with the MSPI hw IP provides acceleration
+ for flash reads and be configured to do single, double, quad lane
+ io with 3-byte and 4-byte addressing support.
+
+ Supported Broadcom SoCs have one instance of MSPI+BSPI controller IP.
+ MSPI master can be used wihout BSPI. BRCMSTB SoCs have an additional instance
+ of a MSPI master without the BSPI to use with non flash slave devices that
+ use SPI protocol.
+
+allOf:
+ - $ref: spi-controller.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - description: Second Instance of MSPI BRCMSTB SoCs
+ items:
+ - enum:
+ - brcm,spi-bcm7425-qspi
+ - brcm,spi-bcm7429-qspi
+ - brcm,spi-bcm7435-qspi
+ - brcm,spi-bcm7445-qspi
+ - brcm,spi-bcm7216-qspi
+ - brcm,spi-bcm7278-qspi
+ - const: brcm,spi-bcm-qspi
+ - const: brcm,spi-brcmstb-mspi
+ - description: Second Instance of MSPI BRCMSTB SoCs
+ items:
+ - enum:
+ - brcm,spi-brcmstb-qspi
+ - brcm,spi-brcmstb-mspi
+ - brcm,spi-nsp-qspi
+ - brcm,spi-ns2-qspi
+ - const: brcm,spi-bcm-qspi
+
+ reg:
+ minItems: 1
+ maxItems: 5
+
+ reg-names:
+ minItems: 1
+ maxItems: 5
+ items:
+ - const: mspi
+ - const: bspi
+ - enum: [ intr_regs, intr_status_reg, cs_reg ]
+ - enum: [ intr_regs, intr_status_reg, cs_reg ]
+ - enum: [ intr_regs, intr_status_reg, cs_reg ]
+
+ interrupts:
+ minItems: 1
+ maxItems: 7
+
+ interrupt-names:
+ oneOf:
+ - minItems: 1
+ maxItems: 7
+ items:
+ - const: mspi_done
+ - const: mspi_halted
+ - const: spi_lr_fullness_reached
+ - const: spi_lr_session_aborted
+ - const: spi_lr_impatient
+ - const: spi_lr_session_done
+ - const: spi_lr_overread
+ - const: spi_l1_intr
+
+ clocks:
+ maxItems: 1
+ description: reference clock for this block
+
+ native-endian:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: Defined when using BE SoC and device uses BE register read/write
+
+unevaluatedProperties: false
+
+required:
+ - reg
+ - reg-names
+ - interrupts
+ - interrupt-names
+
+examples:
+ - | # BRCMSTB SoC: SPI Master (MSPI+BSPI) for SPI-NOR access
+ spi@f03e3400 {
+ compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi";
+ reg = <0xf03e3400 0x188>, <0xf03e3200 0x50>, <0xf03e0920 0x4>;
+ reg-names = "mspi", "bspi", "cs_reg";
+ interrupts = <0x5>, <0x6>, <0x1>, <0x2>, <0x3>, <0x4>, <0x0>;
+ interrupt-parent = <&gic>;
+ interrupt-names = "mspi_done",
+ "mspi_halted",
+ "spi_lr_fullness_reached",
+ "spi_lr_session_aborted",
+ "spi_lr_impatient",
+ "spi_lr_session_done",
+ "spi_lr_overread";
+ clocks = <&hif_spi>;
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+
+ flash@0 {
+ #size-cells = <0x2>;
+ #address-cells = <0x2>;
+ compatible = "m25p80";
+ reg = <0x0>;
+ spi-max-frequency = <0x2625a00>;
+ spi-cpol;
+ spi-cpha;
+ };
+ };
+ - | # BRCMSTB SoC: MSPI master for any SPI device
+ spi@f0416000 {
+ clocks = <&upg_fixed>;
+ compatible = "brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi";
+ reg = <0xf0416000 0x180>;
+ reg-names = "mspi";
+ interrupts = <0x14>;
+ interrupt-parent = <&irq0_aon_intc>;
+ interrupt-names = "mspi_done";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ - | # iProc SoC
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ spi@18027200 {
+ compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
+ reg = <0x18027200 0x184>,
+ <0x18027000 0x124>,
+ <0x1811c408 0x004>,
+ <0x180273a0 0x01c>;
+ reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg";
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mspi_done",
+ "mspi_halted",
+ "spi_lr_fullness_reached",
+ "spi_lr_session_aborted",
+ "spi_lr_impatient",
+ "spi_lr_session_done";
+ clocks = <&iprocmed>;
+ num-cs = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ - | # NS2 SoC
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ spi@66470200 {
+ compatible = "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi";
+ reg = <0x66470200 0x184>,
+ <0x66470000 0x124>,
+ <0x67017408 0x004>,
+ <0x664703a0 0x01c>;
+ reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg";
+ interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "spi_l1_intr";
+ clocks = <&iprocmed>;
+ num-cs = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "m25p80";
+ reg = <0x0>;
+ spi-max-frequency = <12500000>;
+ spi-cpol;
+ spi-cpha;
+ };
+ };
diff --git a/Bindings/spi/cdns,qspi-nor.yaml b/Bindings/spi/cdns,qspi-nor.yaml
new file mode 100644
index 000000000000..0e7087cc8bf9
--- /dev/null
+++ b/Bindings/spi/cdns,qspi-nor.yaml
@@ -0,0 +1,143 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence Quad SPI controller
+
+maintainers:
+ - Pratyush Yadav <p.yadav@ti.com>
+
+allOf:
+ - $ref: spi-controller.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - ti,k2g-qspi
+ - ti,am654-ospi
+ - intel,lgm-qspi
+ - const: cdns,qspi-nor
+ - const: cdns,qspi-nor
+
+ reg:
+ items:
+ - description: the controller register set
+ - description: the controller data area
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ cdns,fifo-depth:
+ description:
+ Size of the data FIFO in words.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ enum: [ 128, 256 ]
+ default: 128
+
+ cdns,fifo-width:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Bus width of the data FIFO in bytes.
+ default: 4
+
+ cdns,trigger-address:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ 32-bit indirect AHB trigger address.
+
+ cdns,is-decoded-cs:
+ type: boolean
+ description:
+ Flag to indicate whether decoder is used to select different chip select
+ for different memory regions.
+
+ cdns,rclk-en:
+ type: boolean
+ description:
+ Flag to indicate that QSPI return clock is used to latch the read
+ data rather than the QSPI clock. Make sure that QSPI return clock
+ is populated on the board before using this property.
+
+ resets:
+ maxItems: 2
+
+ reset-names:
+ minItems: 1
+ maxItems: 2
+ items:
+ enum: [ qspi, qspi-ocp ]
+
+# subnode's properties
+patternProperties:
+ "@[0-9a-f]+$":
+ type: object
+ description:
+ Flash device uses the below defined properties in the subnode.
+
+ properties:
+ cdns,read-delay:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Delay for read capture logic, in clock cycles.
+
+ cdns,tshsl-ns:
+ description:
+ Delay in nanoseconds for the length that the master mode chip select
+ outputs are de-asserted between transactions.
+
+ cdns,tsd2d-ns:
+ description:
+ Delay in nanoseconds between one chip select being de-activated
+ and the activation of another.
+
+ cdns,tchsh-ns:
+ description:
+ Delay in nanoseconds between last bit of current transaction and
+ deasserting the device chip select (qspi_n_ss_out).
+
+ cdns,tslch-ns:
+ description:
+ Delay in nanoseconds between setting qspi_n_ss_out low and
+ first bit transfer.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - cdns,fifo-depth
+ - cdns,fifo-width
+ - cdns,trigger-address
+ - '#address-cells'
+ - '#size-cells'
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ qspi: spi@ff705000 {
+ compatible = "cdns,qspi-nor";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xff705000 0x1000>,
+ <0xffa00000 0x1000>;
+ interrupts = <0 151 4>;
+ clocks = <&qspi_clk>;
+ cdns,fifo-depth = <128>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x00000000>;
+ resets = <&rst 0x1>, <&rst 0x2>;
+ reset-names = "qspi", "qspi-ocp";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ };
+ };
diff --git a/Bindings/spi/fsl,spi-fsl-qspi.yaml b/Bindings/spi/fsl,spi-fsl-qspi.yaml
new file mode 100644
index 000000000000..e58644558412
--- /dev/null
+++ b/Bindings/spi/fsl,spi-fsl-qspi.yaml
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/fsl,spi-fsl-qspi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale Quad Serial Peripheral Interface (QuadSPI)
+
+maintainers:
+ - Han Xu <han.xu@nxp.com>
+
+allOf:
+ - $ref: "spi-controller.yaml#"
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - fsl,vf610-qspi
+ - fsl,imx6sx-qspi
+ - fsl,imx7d-qspi
+ - fsl,imx6ul-qspi
+ - fsl,ls1021a-qspi
+ - fsl,ls2080a-qspi
+ - items:
+ - enum:
+ - fsl,ls1043a-qspi
+ - const: fsl,ls1021a-qspi
+ - items:
+ - enum:
+ - fsl,imx8mq-qspi
+ - const: fsl,imx7d-qspi
+
+ reg:
+ items:
+ - description: registers
+ - description: memory mapping
+
+ reg-names:
+ items:
+ - const: QuadSPI
+ - const: QuadSPI-memory
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: SoC SPI qspi_en clock
+ - description: SoC SPI qspi clock
+
+ clock-names:
+ items:
+ - const: qspi_en
+ - const: qspi
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ spi@1550000 {
+ compatible = "fsl,ls1021a-qspi";
+ reg = <0x0 0x1550000 0x0 0x100000>,
+ <0x0 0x40000000 0x0 0x10000000>;
+ reg-names = "QuadSPI", "QuadSPI-memory";
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(2)>,
+ <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(2)>;
+ clock-names = "qspi_en", "qspi";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ };
+ };
+ };
diff --git a/Bindings/spi/mediatek,spi-mtk-nor.yaml b/Bindings/spi/mediatek,spi-mtk-nor.yaml
index 55c239446a5b..7393f30535df 100644
--- a/Bindings/spi/mediatek,spi-mtk-nor.yaml
+++ b/Bindings/spi/mediatek,spi-mtk-nor.yaml
@@ -31,6 +31,7 @@ properties:
- mediatek,mt7623-nor
- mediatek,mt7629-nor
- mediatek,mt8192-nor
+ - mediatek,mt8195-nor
- enum:
- mediatek,mt8173-nor
- items:
diff --git a/Bindings/spi/spi-controller.yaml b/Bindings/spi/spi-controller.yaml
index 06786f1b43d2..0477396e4945 100644
--- a/Bindings/spi/spi-controller.yaml
+++ b/Bindings/spi/spi-controller.yaml
@@ -181,22 +181,23 @@ additionalProperties: true
examples:
- |
- spi@f00 {
+ spi@80010000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
- reg = <0xf00 0x20>;
- interrupts = <2 13 0 2 14 0>;
- interrupt-parent = <&mpc5200_pic>;
-
- ethernet-switch@0 {
- compatible = "micrel,ks8995m";
+ compatible = "fsl,imx28-spi";
+ reg = <0x80010000 0x2000>;
+ interrupts = <96>;
+ dmas = <&dma_apbh 0>;
+ dma-names = "rx-tx";
+
+ display@0 {
+ compatible = "lg,lg4573";
spi-max-frequency = <1000000>;
reg = <0>;
};
- codec@1 {
- compatible = "ti,tlv320aic26";
+ sensor@1 {
+ compatible = "bosch,bme680";
spi-max-frequency = <100000>;
reg = <1>;
};
diff --git a/Bindings/spi/spi-mt65xx.txt b/Bindings/spi/spi-mt65xx.txt
index 9e43721fa7d6..4d0e4c15c4ea 100644
--- a/Bindings/spi/spi-mt65xx.txt
+++ b/Bindings/spi/spi-mt65xx.txt
@@ -12,7 +12,9 @@ Required properties:
- mediatek,mt8173-spi: for mt8173 platforms
- mediatek,mt8183-spi: for mt8183 platforms
- "mediatek,mt8192-spi", "mediatek,mt6765-spi": for mt8192 platforms
+ - "mediatek,mt8195-spi", "mediatek,mt6765-spi": for mt8195 platforms
- "mediatek,mt8516-spi", "mediatek,mt2712-spi": for mt8516 platforms
+ - "mediatek,mt6779-spi", "mediatek,mt6765-spi": for mt6779 platforms
- #address-cells: should be 1.
diff --git a/Bindings/spi/spi-mux.yaml b/Bindings/spi/spi-mux.yaml
index 6c21a132b51f..51c7622dc20b 100644
--- a/Bindings/spi/spi-mux.yaml
+++ b/Bindings/spi/spi-mux.yaml
@@ -72,19 +72,15 @@ examples:
mux-controls = <&mux>;
- spi-flash@0 {
+ flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
spi-max-frequency = <40000000>;
};
- spi-device@1 {
- compatible = "lineartechnology,ltc2488";
+ sensor@1 {
+ compatible = "bosch,bme680";
reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
spi-max-frequency = <10000000>;
};
};
diff --git a/Bindings/spi/spi-nxp-fspi.txt b/Bindings/spi/spi-nxp-fspi.txt
index 7ac60d9fe357..8f34a7c7d8b8 100644
--- a/Bindings/spi/spi-nxp-fspi.txt
+++ b/Bindings/spi/spi-nxp-fspi.txt
@@ -4,6 +4,8 @@ Required properties:
- compatible : Should be "nxp,lx2160a-fspi"
"nxp,imx8qxp-fspi"
"nxp,imx8mm-fspi"
+ "nxp,imx8mp-fspi"
+ "nxp,imx8dxl-fspi"
- reg : First contains the register location and length,
Second contains the memory mapping address and length
diff --git a/Bindings/spi/spi-slave-mt27xx.txt b/Bindings/spi/spi-slave-mt27xx.txt
index c37e5a179b21..9192724540fd 100644
--- a/Bindings/spi/spi-slave-mt27xx.txt
+++ b/Bindings/spi/spi-slave-mt27xx.txt
@@ -3,6 +3,7 @@ Binding for MTK SPI Slave controller
Required properties:
- compatible: should be one of the following.
- mediatek,mt2712-spi-slave: for mt2712 platforms
+ - mediatek,mt8195-spi-slave: for mt8195 platforms
- reg: Address and length of the register set for the device.
- interrupts: Should contain spi interrupt.
- clocks: phandles to input clocks.
diff --git a/Bindings/spi/st,stm32-spi.yaml b/Bindings/spi/st,stm32-spi.yaml
index d11806b1ede3..2d9af4c506bb 100644
--- a/Bindings/spi/st,stm32-spi.yaml
+++ b/Bindings/spi/st,stm32-spi.yaml
@@ -96,12 +96,6 @@ examples:
dma-names = "rx", "tx";
cs-gpios = <&gpioa 11 0>;
- aardvark@0 {
- compatible = "totalphase,aardvark";
- reg = <0>;
- spi-max-frequency = <4000000>;
- st,spi-midi-ns = <4000>;
- };
};
...
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 20:26:08 +0000