564 files changed, 91446 insertions, 21525 deletions

diff --git a/MdePkg/Include/AArch64/ProcessorBind.h b/MdePkg/Include/AArch64/ProcessorBind.h
index 3fc678c756b3..9603c32d9339 100644
--- a/MdePkg/Include/AArch64/ProcessorBind.h
+++ b/MdePkg/Include/AArch64/ProcessorBind.h
@@ -1,17 +1,11 @@
 /** @file
   Processor or Compiler specific defines and types for AArch64.
 
-  Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
   Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
 
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -26,11 +20,57 @@
 //
 // Make sure we are using the correct packing rules per EFI specification
 //
-#ifndef __GNUC__
+#if !defined(__GNUC__) && !defined(__ASSEMBLER__)
 #pragma pack()
 #endif
 
-#if _MSC_EXTENSIONS
+#if defined(_MSC_EXTENSIONS)
+
+//
+// Disable some level 4 compilation warnings (same as IA32 and X64)
+//
+
+//
+// Disabling bitfield type checking warnings.
+//
+#pragma warning ( disable : 4214 )
+
+//
+// Disabling the unreferenced formal parameter warnings.
+//
+#pragma warning ( disable : 4100 )
+
+//
+// Disable slightly different base types warning as CHAR8 * can not be set
+// to a constant string.
+//
+#pragma warning ( disable : 4057 )
+
+//
+// ASSERT(FALSE) or while (TRUE) are legal constructs so suppress this warning
+//
+#pragma warning ( disable : 4127 )
+
+//
+// This warning is caused by functions defined but not used. For precompiled header only.
+//
+#pragma warning ( disable : 4505 )
+
+//
+// This warning is caused by empty (after preprocessing) source file. For precompiled header only.
+//
+#pragma warning ( disable : 4206 )
+
+//
+// Disable 'potentially uninitialized local variable X used' warnings
+//
+#pragma warning ( disable : 4701 )
+
+//
+// Disable 'potentially uninitialized local pointer variable X used' warnings
+//
+#pragma warning ( disable : 4703 )
+
   //
   // use Microsoft* C compiler dependent integer width types
   //
@@ -45,7 +85,9 @@
   typedef unsigned char       UINT8;
   typedef char                CHAR8;
   typedef signed char         INT8;
+
 #else
+
   //
   // Assume standard AARCH64 alignment.
   //
@@ -60,6 +102,7 @@
   typedef unsigned char       UINT8;
   typedef char                CHAR8;
   typedef signed char         INT8;
+
 #endif
 
 ///
@@ -94,12 +137,22 @@ typedef INT64   INTN;
 #define MAX_ADDRESS   0xFFFFFFFFFFFFFFFFULL
 
 ///
+/// Maximum usable address at boot time (48 bits using 4 KB pages)
+///
+#define MAX_ALLOC_ADDRESS   0xFFFFFFFFFFFFULL
+
+///
 /// Maximum legal AArch64 INTN and UINTN values.
 ///
 #define MAX_INTN   ((INTN)0x7FFFFFFFFFFFFFFFULL)
 #define MAX_UINTN  ((UINTN)0xFFFFFFFFFFFFFFFFULL)
 
 ///
+/// Minimum legal AArch64 INTN value.
+///
+#define MIN_INTN   (((INTN)-9223372036854775807LL) - 1)
+
+///
 /// The stack alignment required for AARCH64
 ///
 #define CPU_STACK_ALIGNMENT  16
diff --git a/MdePkg/Include/Arm/ProcessorBind.h b/MdePkg/Include/Arm/ProcessorBind.h
index ba024c072d71..8794f07cf3d1 100644
--- a/MdePkg/Include/Arm/ProcessorBind.h
+++ b/MdePkg/Include/Arm/ProcessorBind.h
@@ -1,15 +1,9 @@
 /** @file
   Processor or Compiler specific defines and types for ARM.
 
-  Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
   Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -24,18 +18,67 @@
 //
 // Make sure we are using the correct packing rules per EFI specification
 //
-#ifndef __GNUC__
+#if !defined(__GNUC__) && !defined(__ASSEMBLER__)
 #pragma pack()
 #endif
 
+#if defined(_MSC_EXTENSIONS)
+
+//
+// Disable some level 4 compilation warnings (same as IA32 and X64)
+//
+
+//
+// Disabling bitfield type checking warnings.
+//
+#pragma warning ( disable : 4214 )
+
+//
+// Disabling the unreferenced formal parameter warnings.
+//
+#pragma warning ( disable : 4100 )
+
 //
-// RVCT does not support the __builtin_unreachable() macro
+// Disable slightly different base types warning as CHAR8 * can not be set
+// to a constant string.
+//
+#pragma warning ( disable : 4057 )
+
+//
+// ASSERT(FALSE) or while (TRUE) are legal constructs so suppress this warning
+//
+#pragma warning ( disable : 4127 )
+
+//
+// This warning is caused by functions defined but not used. For precompiled header only.
+//
+#pragma warning ( disable : 4505 )
+
+//
+// This warning is caused by empty (after preprocessing) source file. For precompiled header only.
+//
+#pragma warning ( disable : 4206 )
+
 //
-#ifdef __ARMCC_VERSION
+// Disable 'potentially uninitialized local variable X used' warnings
+//
+#pragma warning ( disable : 4701 )
+
+//
+// Disable 'potentially uninitialized local pointer variable X used' warnings
+//
+#pragma warning ( disable : 4703 )
+
+#endif
+
+//
+// RVCT and MSFT don't support the __builtin_unreachable() macro
+//
+#if defined(__ARMCC_VERSION) || defined(_MSC_EXTENSIONS)
 #define UNREACHABLE()
 #endif
 
-#if _MSC_EXTENSIONS 
+#if defined(_MSC_EXTENSIONS)
   //
   // use Microsoft* C compiler dependent integer width types
   //
@@ -52,7 +95,7 @@
   typedef signed char         INT8;
 #else
   //
-  // Assume standard ARM alignment. 
+  // Assume standard ARM alignment.
   // Need to check portability of long long
   //
   typedef unsigned long long  UINT64;
@@ -100,12 +143,22 @@ typedef INT32   INTN;
 #define MAX_ADDRESS  0xFFFFFFFF
 
 ///
+/// Maximum usable address at boot time
+///
+#define MAX_ALLOC_ADDRESS   MAX_ADDRESS
+
+///
 /// Maximum legal ARM INTN and UINTN values.
 ///
 #define MAX_INTN   ((INTN)0x7FFFFFFF)
 #define MAX_UINTN  ((UINTN)0xFFFFFFFF)
 
 ///
+/// Minimum legal ARM INTN value.
+///
+#define MIN_INTN   (((INTN)-2147483647) - 1)
+
+///
 /// The stack alignment required for ARM
 ///
 #define CPU_STACK_ALIGNMENT  sizeof(UINT64)
@@ -121,7 +174,7 @@ typedef INT32   INTN;
 // use the correct C calling convention. All protocol member functions and
 // EFI intrinsics are required to modify their member functions with EFIAPI.
 //
-#define EFIAPI    
+#define EFIAPI
 
 // When compiling with Clang, we still use GNU as for the assembler, so we still
 // need to define the GCC_ASM* macros.
@@ -142,34 +195,39 @@ typedef INT32   INTN;
 
     #define GCC_ASM_EXPORT(func__)  \
              .global  _CONCATENATE (__USER_LABEL_PREFIX__, func__)    ;\
-             .type ASM_PFX(func__), %function  
+             .type ASM_PFX(func__), %function
 
     #define GCC_ASM_IMPORT(func__)  \
              .extern  _CONCATENATE (__USER_LABEL_PREFIX__, func__)
-             
+
   #else
     //
-    // .type not supported by Apple Xcode tools 
+    // .type not supported by Apple Xcode tools
     //
-    #define INTERWORK_FUNC(func__)  
+    #define INTERWORK_FUNC(func__)
 
     #define GCC_ASM_EXPORT(func__)  \
              .globl  _CONCATENATE (__USER_LABEL_PREFIX__, func__)    \
-  
-    #define GCC_ASM_IMPORT(name)  
+
+    #define GCC_ASM_IMPORT(name)
 
   #endif
+#elif defined(_MSC_EXTENSIONS)
+  //
+  // PRESERVE8 is not supported by the MSFT assembler.
+  //
+  #define PRESERVE8
 #endif
 
 /**
   Return the pointer to the first instruction of a function given a function pointer.
-  On ARM CPU architectures, these two pointer values are the same, 
+  On ARM CPU architectures, these two pointer values are the same,
   so the implementation of this macro is very simple.
-  
+
   @param  FunctionPointer   A pointer to a function.
 
   @return The pointer to the first instruction of a function given a function pointer.
-  
+
 **/
 #define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)
 
diff --git a/MdePkg/Include/Base.h b/MdePkg/Include/Base.h
index 70cb9992a6fd..60c2e085d5cc 100644
--- a/MdePkg/Include/Base.h
+++ b/MdePkg/Include/Base.h
@@ -6,15 +6,9 @@
   environment. There are a set of base libraries in the Mde Package that can
   be used to implement base modules.
 
-Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
 Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -34,64 +28,12 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #pragma warning ( disable : 4200 )
 #endif
 
-/**
-  Verifies the storage size of a given data type.
-
-  This macro generates a divide by zero error or a zero size array declaration in
-  the preprocessor if the size is incorrect.  These are declared as "extern" so
-  the space for these arrays will not be in the modules.
-
-  @param  TYPE  The date type to determine the size of.
-  @param  Size  The expected size for the TYPE.
-
-**/
-#define VERIFY_SIZE_OF(TYPE, Size) extern UINT8 _VerifySizeof##TYPE[(sizeof(TYPE) == (Size)) / (sizeof(TYPE) == (Size))]
-
-//
-// Verify that ProcessorBind.h produced UEFI Data Types that are compliant with
-// Section 2.3.1 of the UEFI 2.3 Specification.
-//
-VERIFY_SIZE_OF (BOOLEAN, 1);
-VERIFY_SIZE_OF (INT8, 1);
-VERIFY_SIZE_OF (UINT8, 1);
-VERIFY_SIZE_OF (INT16, 2);
-VERIFY_SIZE_OF (UINT16, 2);
-VERIFY_SIZE_OF (INT32, 4);
-VERIFY_SIZE_OF (UINT32, 4);
-VERIFY_SIZE_OF (INT64, 8);
-VERIFY_SIZE_OF (UINT64, 8);
-VERIFY_SIZE_OF (CHAR8, 1);
-VERIFY_SIZE_OF (CHAR16, 2);
-
-//
-// The following three enum types are used to verify that the compiler
-// configuration for enum types is compliant with Section 2.3.1 of the 
-// UEFI 2.3 Specification. These enum types and enum values are not 
-// intended to be used. A prefix of '__' is used avoid conflicts with
-// other types.
-//
-typedef enum {
-  __VerifyUint8EnumValue = 0xff
-} __VERIFY_UINT8_ENUM_SIZE;
-
-typedef enum {
-  __VerifyUint16EnumValue = 0xffff
-} __VERIFY_UINT16_ENUM_SIZE;
-
-typedef enum {
-  __VerifyUint32EnumValue = 0xffffffff
-} __VERIFY_UINT32_ENUM_SIZE;
-
-VERIFY_SIZE_OF (__VERIFY_UINT8_ENUM_SIZE, 4);
-VERIFY_SIZE_OF (__VERIFY_UINT16_ENUM_SIZE, 4);
-VERIFY_SIZE_OF (__VERIFY_UINT32_ENUM_SIZE, 4);
-
 //
 // The Microsoft* C compiler can removed references to unreferenced data items
 //  if the /OPT:REF linker option is used. We defined a macro as this is a
 //  a non standard extension
 //
-#if defined(_MSC_EXTENSIONS) && !defined (MDE_CPU_EBC)
+#if defined(_MSC_VER) && _MSC_VER < 1800 && !defined (MDE_CPU_EBC)
   ///
   /// Remove global variable from the linked image if there are no references to
   /// it after all compiler and linker optimizations have been performed.
@@ -112,11 +54,10 @@ VERIFY_SIZE_OF (__VERIFY_UINT32_ENUM_SIZE, 4);
 // warnings.
 //
 #ifndef UNREACHABLE
-  #if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ > 4)
+  #ifdef __GNUC__
     ///
     /// Signal compilers and analyzers that this call is not reachable.  It is
     /// up to the compiler to remove any code past that point.
-    /// Not implemented by GCC 4.4 or earlier.
     ///
     #define UNREACHABLE()  __builtin_unreachable ()
   #elif defined (__has_feature)
@@ -218,6 +159,26 @@ VERIFY_SIZE_OF (__VERIFY_UINT32_ENUM_SIZE, 4);
   #endif
 #endif
 
+///
+/// Tell the code optimizer that the function will return twice.
+/// This prevents wrong optimizations which can cause bugs.
+///
+#ifndef RETURNS_TWICE
+  #if defined (__GNUC__) || defined (__clang__)
+    ///
+    /// Tell the code optimizer that the function will return twice.
+    /// This prevents wrong optimizations which can cause bugs.
+    ///
+    #define RETURNS_TWICE  __attribute__((returns_twice))
+  #else
+    ///
+    /// Tell the code optimizer that the function will return twice.
+    /// This prevents wrong optimizations which can cause bugs.
+    ///
+    #define RETURNS_TWICE
+  #endif
+#endif
+
 //
 // For symbol name in assembly code, an extra "_" is sometimes necessary
 //
@@ -234,7 +195,7 @@ VERIFY_SIZE_OF (__VERIFY_UINT32_ENUM_SIZE, 4);
 ///
 #define ASM_PFX(name) _CONCATENATE (__USER_LABEL_PREFIX__, name)
 
-#if __APPLE__
+#ifdef __APPLE__
   //
   // Apple extension that is used by the linker to optimize code size
   // with assembly functions. Put at the end of your .S files
@@ -376,6 +337,14 @@ struct _LIST_ENTRY {
 #define MAX_INT64   ((INT64)0x7FFFFFFFFFFFFFFFULL)
 #define MAX_UINT64  ((UINT64)0xFFFFFFFFFFFFFFFFULL)
 
+///
+/// Minimum values for the signed UEFI Data Types
+///
+#define MIN_INT8   (((INT8)  -127) - 1)
+#define MIN_INT16  (((INT16) -32767) - 1)
+#define MIN_INT32  (((INT32) -2147483647) - 1)
+#define MIN_INT64  (((INT64) -9223372036854775807LL) - 1)
+
 #define  BIT0     0x00000001
 #define  BIT1     0x00000002
 #define  BIT2     0x00000004
@@ -552,21 +521,24 @@ struct _LIST_ENTRY {
 #define  BASE_8EB    0x8000000000000000ULL
 
 //
-//  Support for variable length argument lists using the ANSI standard.
+//  Support for variable argument lists in freestanding edk2 modules.
 //
-//  Since we are using the ANSI standard we used the standard naming and
-//  did not follow the coding convention
+//  For modules that use the ISO C library interfaces for variable
+//  argument lists, refer to "StdLib/Include/stdarg.h".
 //
 //  VA_LIST  - typedef for argument list.
 //  VA_START (VA_LIST Marker, argument before the ...) - Init Marker for use.
 //  VA_END (VA_LIST Marker) - Clear Marker
-//  VA_ARG (VA_LIST Marker, var arg size) - Use Marker to get an argument from
-//    the ... list. You must know the size and pass it in this macro.
+//  VA_ARG (VA_LIST Marker, var arg type) - Use Marker to get an argument from
+//    the ... list. You must know the type and pass it in this macro.  Type
+//    must be compatible with the type of the actual next argument (as promoted
+//    according to the default argument promotions.)
 //  VA_COPY (VA_LIST Dest, VA_LIST Start) - Initialize Dest as a copy of Start.
 //
-//  example:
+//  Example:
 //
 //  UINTN
+//  EFIAPI
 //  ExampleVarArg (
 //    IN UINTN  NumberOfArgs,
 //    ...
@@ -582,15 +554,21 @@ struct _LIST_ENTRY {
 //    VA_START (Marker, NumberOfArgs);
 //    for (Index = 0, Result = 0; Index < NumberOfArgs; Index++) {
 //      //
-//      // The ... list is a series of UINTN values, so average them up.
+//      // The ... list is a series of UINTN values, so sum them up.
 //      //
 //      Result += VA_ARG (Marker, UINTN);
 //    }
 //
 //    VA_END (Marker);
-//    return Result
+//    return Result;
 //  }
 //
+//  Notes:
+//  - Functions that call VA_START() / VA_END() must have a variable
+//    argument list and must be declared EFIAPI.
+//  - Functions that call VA_COPY() / VA_END() must be declared EFIAPI.
+//  - Functions that only use VA_LIST and VA_ARG() need not be EFIAPI.
+//
 
 /**
   Return the size of argument that has been aligned to sizeof (UINTN).
@@ -631,7 +609,19 @@ struct _LIST_ENTRY {
 
 #define VA_COPY(Dest, Start)          __va_copy (Dest, Start)
 
-#elif defined(__GNUC__)
+#elif defined(_M_ARM) || defined(_M_ARM64)
+//
+// MSFT ARM variable argument list support.
+//
+
+typedef char* VA_LIST;
+
+#define VA_START(Marker, Parameter)     __va_start (&Marker, &Parameter, _INT_SIZE_OF (Parameter), __alignof(Parameter), &Parameter)
+#define VA_ARG(Marker, TYPE)            (*(TYPE *) ((Marker += _INT_SIZE_OF (TYPE) + ((-(INTN)Marker) & (sizeof(TYPE) - 1))) - _INT_SIZE_OF (TYPE)))
+#define VA_END(Marker)                  (Marker = (VA_LIST) 0)
+#define VA_COPY(Dest, Start)            ((void)((Dest) = (Start)))
+
+#elif defined(__GNUC__) || defined(__clang__)
 
 #if defined(MDE_CPU_X64) && !defined(NO_MSABI_VA_FUNCS)
 //
@@ -736,7 +726,7 @@ typedef CHAR8 *VA_LIST;
 
   This macro initializes Dest as a copy of Start, as if the VA_START macro had been applied to Dest
   followed by the same sequence of uses of the VA_ARG macro as had previously been used to reach
-  the present state of Start. 
+  the present state of Start.
 
   @param   Dest   VA_LIST used to traverse the list of arguments.
   @param   Start  VA_LIST used to traverse the list of arguments.
@@ -791,17 +781,71 @@ typedef UINTN  *BASE_LIST;
   @return  Offset, in bytes, of field.
 
 **/
-#ifdef __GNUC__
-#if __GNUC__ >= 4
+#if (defined(__GNUC__) && __GNUC__ >= 4) || defined(__clang__)
 #define OFFSET_OF(TYPE, Field) ((UINTN) __builtin_offsetof(TYPE, Field))
 #endif
-#endif
 
 #ifndef OFFSET_OF
 #define OFFSET_OF(TYPE, Field) ((UINTN) &(((TYPE *)0)->Field))
 #endif
 
 /**
+  Portable definition for compile time assertions.
+  Equivalent to C11 static_assert macro from assert.h.
+
+  @param  Expression  Boolean expression.
+  @param  Message     Raised compiler diagnostic message when expression is false.
+
+**/
+#ifdef MDE_CPU_EBC
+  #define STATIC_ASSERT(Expression, Message)
+#elif defined(_MSC_EXTENSIONS)
+  #define STATIC_ASSERT static_assert
+#else
+  #define STATIC_ASSERT _Static_assert
+#endif
+
+//
+// Verify that ProcessorBind.h produced UEFI Data Types that are compliant with
+// Section 2.3.1 of the UEFI 2.3 Specification.
+//
+
+STATIC_ASSERT (sizeof (BOOLEAN) == 1, "sizeof (BOOLEAN) does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (sizeof (INT8)    == 1, "sizeof (INT8) does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (sizeof (UINT8)   == 1, "sizeof (UINT8) does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (sizeof (INT16)   == 2, "sizeof (INT16) does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (sizeof (UINT16)  == 2, "sizeof (UINT16) does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (sizeof (INT32)   == 4, "sizeof (INT32) does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (sizeof (UINT32)  == 4, "sizeof (UINT32) does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (sizeof (INT64)   == 8, "sizeof (INT64) does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (sizeof (UINT64)  == 8, "sizeof (UINT64) does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (sizeof (CHAR8)   == 1, "sizeof (CHAR8) does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (sizeof (CHAR16)  == 2, "sizeof (CHAR16) does not meet UEFI Specification Data Type requirements");
+
+//
+// The following three enum types are used to verify that the compiler
+// configuration for enum types is compliant with Section 2.3.1 of the
+// UEFI 2.3 Specification. These enum types and enum values are not
+// intended to be used. A prefix of '__' is used avoid conflicts with
+// other types.
+//
+typedef enum {
+  __VerifyUint8EnumValue = 0xff
+} __VERIFY_UINT8_ENUM_SIZE;
+
+typedef enum {
+  __VerifyUint16EnumValue = 0xffff
+} __VERIFY_UINT16_ENUM_SIZE;
+
+typedef enum {
+  __VerifyUint32EnumValue = 0xffffffff
+} __VERIFY_UINT32_ENUM_SIZE;
+
+STATIC_ASSERT (sizeof (__VERIFY_UINT8_ENUM_SIZE) == 4, "Size of enum does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (sizeof (__VERIFY_UINT16_ENUM_SIZE) == 4, "Size of enum does not meet UEFI Specification Data Type requirements");
+STATIC_ASSERT (sizeof (__VERIFY_UINT32_ENUM_SIZE) == 4, "Size of enum does not meet UEFI Specification Data Type requirements");
+
+/**
   Macro that returns a pointer to the data structure that contains a specified field of
   that data structure.  This is a lightweight method to hide information by placing a
   public data structure inside a larger private data structure and using a pointer to
@@ -820,7 +864,7 @@ typedef UINTN  *BASE_LIST;
   @return  A pointer to the structure from one of it's elements.
 
 **/
-#define BASE_CR(Record, TYPE, Field)  ((TYPE *) ((CHAR8 *) (Record) - (CHAR8 *) &(((TYPE *) 0)->Field)))
+#define BASE_CR(Record, TYPE, Field)  ((TYPE *) ((CHAR8 *) (Record) - OFFSET_OF (TYPE, Field)))
 
 /**
   Rounds a value up to the next boundary using a specified alignment.
@@ -1213,6 +1257,7 @@ typedef UINTN RETURN_STATUS;
     (SIGNATURE_32 (A, B, C, D) | ((UINT64) (SIGNATURE_32 (E, F, G, H)) << 32))
 
 #if defined(_MSC_EXTENSIONS) && !defined (__INTEL_COMPILER) && !defined (MDE_CPU_EBC)
+  void * _ReturnAddress(void);
   #pragma intrinsic(_ReturnAddress)
   /**
     Get the return address of the calling function.
@@ -1227,7 +1272,7 @@ typedef UINTN RETURN_STATUS;
 
   **/
   #define RETURN_ADDRESS(L)     ((L == 0) ? _ReturnAddress() : (VOID *) 0)
-#elif defined(__GNUC__)
+#elif defined (__GNUC__) || defined (__clang__)
   void * __builtin_return_address (unsigned int level);
   /**
     Get the return address of the calling function.
diff --git a/MdePkg/Include/Ebc/ProcessorBind.h b/MdePkg/Include/Ebc/ProcessorBind.h
index ca46b80561ab..f747e8da2c1f 100644
--- a/MdePkg/Include/Ebc/ProcessorBind.h
+++ b/MdePkg/Include/Ebc/ProcessorBind.h
@@ -4,14 +4,8 @@
   We currently only have one EBC compiler so there may be some Intel compiler
   specific functions in this file.
 
-Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -91,23 +85,33 @@ typedef unsigned long         UINTN;
 /// A value of native width with the highest bit set.
 /// Scalable macro to set the most significant bit in a natural number.
 ///
-#define MAX_BIT     (1ULL << (sizeof (INTN) * 8 - 1)) 
+#define MAX_BIT     ((UINTN)((1ULL << (sizeof (INTN) * 8 - 1))))
 ///
 /// A value of native width with the two highest bits set.
 /// Scalable macro to set the most 2 significant bits in a natural number.
 ///
-#define MAX_2_BITS  (3ULL << (sizeof (INTN) * 8 - 2))
+#define MAX_2_BITS  ((UINTN)(3ULL << (sizeof (INTN) * 8 - 2)))
 
 ///
 /// Maximum legal EBC address
 ///
-#define MAX_ADDRESS   ((UINTN) ~0)
+#define MAX_ADDRESS   ((UINTN)(~0ULL >> (64 - sizeof (INTN) * 8)))
+
+///
+/// Maximum usable address at boot time (48 bits using 4 KB pages)
+///
+#define MAX_ALLOC_ADDRESS   MAX_ADDRESS
 
 ///
 /// Maximum legal EBC INTN and UINTN values.
 ///
-#define MAX_UINTN  ((UINTN) ~0)
-#define MAX_INTN   ((INTN)~MAX_BIT)
+#define MAX_UINTN  ((UINTN)(~0ULL >> (64 - sizeof (INTN) * 8)))
+#define MAX_INTN   ((INTN)(~0ULL >> (65 - sizeof (INTN) * 8)))
+
+///
+/// Minimum legal EBC INTN value.
+///
+#define MIN_INTN   (((INTN)-MAX_INTN) - 1)
 
 ///
 /// The stack alignment required for EBC
@@ -130,14 +134,14 @@ typedef unsigned long         UINTN;
   /// If EFIAPI is already defined, then we use that definition.
   ///
 #else
-#define EFIAPI    
+#define EFIAPI
 #endif
 
 /**
   Return the pointer to the first instruction of a function given a function pointer.
-  On EBC architectures, these two pointer values are the same, 
+  On EBC architectures, these two pointer values are the same,
   so the implementation of this macro is very simple.
-  
+
   @param  FunctionPointer   A pointer to a function.
 
   @return The pointer to the first instruction of a function given a function pointer.
@@ -148,5 +152,5 @@ typedef unsigned long         UINTN;
 #define __USER_LABEL_PREFIX__
 #endif
 
-#endif 
+#endif
 
diff --git a/MdePkg/Include/Guid/Acpi.h b/MdePkg/Include/Guid/Acpi.h
index 3897ae62ff30..7aa5ab5a2826 100644
--- a/MdePkg/Include/Guid/Acpi.h
+++ b/MdePkg/Include/Guid/Acpi.h
@@ -2,17 +2,11 @@
   GUIDs used for ACPI entries in the EFI system table
 
   These GUIDs point the ACPI tables as defined in the ACPI specifications.
-  ACPI 2.0 specification defines the ACPI 2.0 GUID. UEFI 2.0 defines the 
+  ACPI 2.0 specification defines the ACPI 2.0 GUID. UEFI 2.0 defines the
   ACPI 2.0 Table GUID and ACPI Table GUID.
 
-  Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   GUIDs defined in UEFI 2.0 spec.
diff --git a/MdePkg/Include/Guid/Apriori.h b/MdePkg/Include/Guid/Apriori.h
index 6d4fc74d406b..2a30fd52e24b 100644
--- a/MdePkg/Include/Guid/Apriori.h
+++ b/MdePkg/Include/Guid/Apriori.h
@@ -3,14 +3,8 @@
   list of FV filenames that the DXE dispatcher will schedule reguardless of
   the dependency grammar.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   GUID introduced in PI Version 1.0.
diff --git a/MdePkg/Include/Guid/AprioriFileName.h b/MdePkg/Include/Guid/AprioriFileName.h
index d99893887d1b..ab34b17ea8b5 100644
--- a/MdePkg/Include/Guid/AprioriFileName.h
+++ b/MdePkg/Include/Guid/AprioriFileName.h
@@ -3,14 +3,8 @@
   name of the PEI a priori file that is stored in a firmware
   volume.
 
-  Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   GUID introduced in PI Version 1.0.
@@ -24,7 +18,7 @@
   { 0x1b45cc0a, 0x156a, 0x428a, { 0x62, 0XAF, 0x49, 0x86, 0x4d, 0xa0, 0xe6, 0xe6 } }
 
 
-///   
+///
 ///  This file must be of type EFI_FV_FILETYPE_FREEFORM and must
 ///  contain a single section of type EFI_SECTION_RAW. For details on
 ///  firmware volumes, firmware file types, and firmware file section
@@ -33,7 +27,7 @@
 typedef struct {
   ///
   /// An array of zero or more EFI_GUID type entries that match the file names of PEIM
-  /// modules in the same Firmware Volume. The maximum number of entries. 
+  /// modules in the same Firmware Volume. The maximum number of entries.
   ///
   EFI_GUID  FileNamesWithinVolume[1];
 } PEI_APRIORI_FILE_CONTENTS;
diff --git a/MdePkg/Include/Guid/Btt.h b/MdePkg/Include/Guid/Btt.h
new file mode 100644
index 000000000000..93a79782b5ca
--- /dev/null
+++ b/MdePkg/Include/Guid/Btt.h
@@ -0,0 +1,222 @@
+/** @file
+  Block Translation Table (BTT) metadata layout definition.
+
+  BTT is a layout and set of rules for doing block I/O that provide powerfail
+  write atomicity of a single block.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  This metadata layout definition was introduced in UEFI Specification 2.7.
+
+**/
+
+#ifndef _BTT_H_
+#define _BTT_H_
+
+///
+/// The BTT layout and behavior is described by the GUID as below.
+///
+#define EFI_BTT_ABSTRACTION_GUID \
+  { \
+    0x18633bfc, 0x1735, 0x4217, { 0x8a, 0xc9, 0x17, 0x23, 0x92, 0x82, 0xd3, 0xf8 } \
+  }
+
+//
+// Alignment of all BTT structures
+//
+#define EFI_BTT_ALIGNMENT                4096
+
+#define EFI_BTT_INFO_UNUSED_LEN          3968
+
+#define EFI_BTT_INFO_BLOCK_SIG_LEN       16
+
+///
+/// Indicate inconsistent metadata or lost metadata due to unrecoverable media errors.
+///
+#define EFI_BTT_INFO_BLOCK_FLAGS_ERROR   0x00000001
+
+#define EFI_BTT_INFO_BLOCK_MAJOR_VERSION 2
+#define EFI_BTT_INFO_BLOCK_MINOR_VERSION 0
+
+///
+/// Block Translation Table (BTT) Info Block
+///
+typedef struct _EFI_BTT_INFO_BLOCK {
+  ///
+  /// Signature of the BTT Index Block data structure.
+  /// Shall be "BTT_ARENA_INFO\0\0".
+  ///
+  CHAR8    Sig[EFI_BTT_INFO_BLOCK_SIG_LEN];
+
+  ///
+  /// UUID identifying this BTT instance.
+  ///
+  GUID Uuid;
+
+  ///
+  /// UUID of containing namespace.
+  ///
+  GUID ParentUuid;
+
+  ///
+  /// Attributes of this BTT Info Block.
+  ///
+  UINT32   Flags;
+
+  ///
+  /// Major version number. Currently at version 2.
+  ///
+  UINT16   Major;
+
+  ///
+  /// Minor version number. Currently at version 0.
+  ///
+  UINT16   Minor;
+
+  ///
+  /// Advertised LBA size in bytes. I/O requests shall be in this size chunk.
+  ///
+  UINT32   ExternalLbaSize;
+
+  ///
+  /// Advertised number of LBAs in this arena.
+  ///
+  UINT32   ExternalNLba;
+
+  ///
+  /// Internal LBA size shall be greater than or equal to ExternalLbaSize and shall not be smaller than 512 bytes.
+  ///
+  UINT32   InternalLbaSize;
+
+  ///
+  /// Number of internal blocks in the arena data area.
+  ///
+  UINT32   InternalNLba;
+
+  ///
+  /// Number of free blocks maintained for writes to this arena.
+  ///
+  UINT32   NFree;
+
+  ///
+  /// The size of this info block in bytes.
+  ///
+  UINT32   InfoSize;
+
+  ///
+  /// Offset of next arena, relative to the beginning of this arena.
+  ///
+  UINT64   NextOff;
+
+  ///
+  /// Offset of the data area for this arena, relative to the beginning of this arena.
+  ///
+  UINT64   DataOff;
+
+  ///
+  /// Offset of the map for this arena, relative to the beginning of this arena.
+  ///
+  UINT64   MapOff;
+
+  ///
+  /// Offset of the flog for this arena, relative to the beginning of this arena.
+  ///
+  UINT64   FlogOff;
+
+  ///
+  /// Offset of the backup copy of this arena's info block, relative to the beginning of this arena.
+  ///
+  UINT64   InfoOff;
+
+  ///
+  /// Shall be zero.
+  ///
+  CHAR8    Unused[EFI_BTT_INFO_UNUSED_LEN];
+
+  ///
+  /// 64-bit Fletcher64 checksum of all fields.
+  ///
+  UINT64   Checksum;
+} EFI_BTT_INFO_BLOCK;
+
+///
+/// BTT Map entry maps an LBA that indexes into the arena, to its actual location.
+///
+typedef struct _EFI_BTT_MAP_ENTRY {
+  ///
+  /// Post-map LBA number (block number in this arena's data area)
+  ///
+  UINT32 PostMapLba : 30;
+
+  ///
+  /// When set and Zero is not set, reads on this block return an error.
+  /// When set and Zero is set, indicate a map entry in its normal, non-error state.
+  ///
+  UINT32 Error : 1;
+
+  ///
+  /// When set and Error is not set, reads on this block return a full block of zeros.
+  /// When set and Error is set, indicate a map entry in its normal, non-error state.
+  ///
+  UINT32 Zero : 1;
+} EFI_BTT_MAP_ENTRY;
+
+///
+/// Alignment of each flog structure
+///
+#define EFI_BTT_FLOG_ENTRY_ALIGNMENT 64
+
+///
+/// The BTT Flog is both a free list and a log.
+/// The Flog size is determined by the EFI_BTT_INFO_BLOCK.NFree which determines how many of these flog
+/// entries there are.
+/// The Flog location is the highest aligned address in the arena after space for the backup info block.
+///
+typedef struct _EFI_BTT_FLOG {
+  ///
+  /// Last pre-map LBA written using this flog entry.
+  ///
+  UINT32 Lba0;
+
+  ///
+  /// Old post-map LBA.
+  ///
+  UINT32 OldMap0;
+
+  ///
+  /// New post-map LBA.
+  ///
+  UINT32 NewMap0;
+
+  ///
+  /// The Seq0 field in each flog entry is used to determine which set of fields is newer between the two sets
+  /// (Lba0, OldMap0, NewMpa0, Seq0 vs Lba1, Oldmap1, NewMap1, Seq1).
+  ///
+  UINT32 Seq0;
+
+  ///
+  /// Alternate lba entry.
+  ///
+  UINT32 Lba1;
+
+  ///
+  /// Alternate old entry.
+  ///
+  UINT32 OldMap1;
+
+  ///
+  /// Alternate new entry.
+  ///
+  UINT32 NewMap1;
+
+  ///
+  /// Alternate Seq entry.
+  ///
+  UINT32 Seq1;
+} EFI_BTT_FLOG;
+
+extern GUID gEfiBttAbstractionGuid;
+
+#endif //_BTT_H_
diff --git a/MdePkg/Include/Guid/CapsuleReport.h b/MdePkg/Include/Guid/CapsuleReport.h
index 051a41bde9f3..8228f937d014 100644
--- a/MdePkg/Include/Guid/CapsuleReport.h
+++ b/MdePkg/Include/Guid/CapsuleReport.h
@@ -1,14 +1,8 @@
 /** @file
   Guid & data structure used for Capsule process result variables
-  
-  Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   GUIDs defined in UEFI 2.4 spec.
@@ -84,14 +78,14 @@ typedef struct {
 
   ///
   /// In case of capsule loaded from disk, the zero-terminated array containing file name of capsule that was processed.
-  /// In case of capsule submitted directly to UpdateCapsule() there is no file name, and this field is required to contain a single 16-bit zero character 
+  /// In case of capsule submitted directly to UpdateCapsule() there is no file name, and this field is required to contain a single 16-bit zero character
   ///  which is included in VariableTotalSize.
   ///
   /// CHAR16 CapsuleFileName[];
   ///
 
   ///
-  /// This field will contain a zero-terminated CHAR16 string containing the text representation of the device path of device publishing Firmware Management Protocol  
+  /// This field will contain a zero-terminated CHAR16 string containing the text representation of the device path of device publishing Firmware Management Protocol
   /// (if present). In case where device path is not present and the target is not otherwise known to firmware, or when payload was blocked by policy, or skipped,
   /// this field is required to contain a single 16-bit zero character which is included in VariableTotalSize.
   ///
@@ -99,6 +93,35 @@ typedef struct {
   ///
 } EFI_CAPSULE_RESULT_VARIABLE_FMP;
 
+typedef struct {
+
+  ///
+  /// Version of this structure, currently 0x00000001
+  ///
+  UINT32    Version;
+
+  ///
+  /// The unique identifier of the capsule whose processing result is recorded in this variable.
+  /// 0x00000000 - 0xEFFFFFFF - Implementation Reserved
+  /// 0xF0000000 - 0xFFFFFFFF - Specification Reserved
+  /// #define REDFISH_DEFINED_JSON_SCHEMA 0xF000000
+  /// The JSON payload shall conform to a Redfish-defined JSON schema, see DMTF-Redfish
+  /// Specification.
+  ///
+  UINT32 CapsuleId;
+
+  ///
+  /// The length of Resp in bytes.
+  ///
+  UINT32 RespLength;
+
+  ///
+  /// Variable length buffer containing the replied JSON payload to the caller who delivered JSON
+  /// capsule to system. The definition of the JSON schema used in the replied payload is beyond
+  /// the scope of this specification.
+  ///
+  UINT8 Resp[];
+ } EFI_CAPSULE_RESULT_VARIABLE_JSON;
 
 extern EFI_GUID gEfiCapsuleReportGuid;
 
diff --git a/MdePkg/Include/Guid/Cper.h b/MdePkg/Include/Guid/Cper.h
index f6f5bc2df8fb..06e06c4eab7d 100644
--- a/MdePkg/Include/Guid/Cper.h
+++ b/MdePkg/Include/Guid/Cper.h
@@ -1,18 +1,12 @@
 /** @file
   GUIDs and definitions used for Common Platform Error Record.
 
-  Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.<BR>
   (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
-  GUIDs defined in UEFI 2.6 Specification.
+  GUIDs defined in UEFI 2.7 Specification.
 
 **/
 
@@ -101,6 +95,18 @@ typedef struct {
   { \
     0x667DD791, 0xC6B3, 0x4c27, { 0x8A, 0x6B, 0x0F, 0x8E, 0x72, 0x2D, 0xEB, 0x41 } \
   }
+#define EFI_EVENT_NOTIFICATION_TYPE_DMAR_SEA \
+  { \
+    0x9A78788A, 0xBBE8, 0x11E4, { 0x80, 0x9E, 0x67, 0x61, 0x1E, 0x5D, 0x46, 0xB0 } \
+  }
+#define EFI_EVENT_NOTIFICATION_TYPE_DMAR_SEI \
+  { \
+    0x5C284C81, 0xB0AE, 0x4E87, { 0xA3, 0x22, 0xB0, 0x4C, 0x85, 0x62, 0x43, 0x23 } \
+  }
+#define EFI_EVENT_NOTIFICATION_TYPE_DMAR_PEI \
+  { \
+    0x09A9D5AC, 0x5204, 0x4214, { 0x96, 0xE5, 0x94, 0x99, 0x2E, 0x75, 0x2B, 0xCD } \
+  }
 ///@}
 
 ///
@@ -256,6 +262,7 @@ typedef struct {
 ///@{
 #define EFI_GENERIC_ERROR_PROC_TYPE_IA32_X64         0x00
 #define EFI_GENERIC_ERROR_PROC_TYPE_IA64             0x01
+#define EFI_GENERIC_ERROR_PROC_TYPE_ARM              0x02
 ///@}
 
 ///
@@ -265,6 +272,8 @@ typedef struct {
 #define EFI_GENERIC_ERROR_PROC_ISA_IA32              0x00
 #define EFI_GENERIC_ERROR_PROC_ISA_IA64              0x01
 #define EFI_GENERIC_ERROR_PROC_ISA_X64               0x02
+#define EFI_GENERIC_ERROR_PROC_ISA_ARM_A32_T32       0x03
+#define EFI_GENERIC_ERROR_PROC_ISA_ARM_A64           0x04
 ///@}
 
 ///
@@ -1088,16 +1097,21 @@ typedef struct {
 
 ///
 /// Identifies the type of firmware error record
-///
+///@{
 #define EFI_FIRMWARE_ERROR_TYPE_IPF_SAL              0x00
+#define EFI_FIRMWARE_ERROR_TYPE_SOC_TYPE1            0x01
+#define EFI_FIRMWARE_ERROR_TYPE_SOC_TYPE2            0x02
+///@}
 
 ///
 /// Firmware Error Record Section
 ///
 typedef struct {
   UINT8       ErrorType;
-  UINT8       Resv1[7];
+  UINT8       Revision;
+  UINT8       Resv1[6];
   UINT64      RecordId;
+  EFI_GUID    RecordIdGuid;
 } EFI_FIRMWARE_ERROR_DATA;
 
 ///
@@ -1205,6 +1219,9 @@ extern EFI_GUID gEfiEventNotificationTypeInitGuid;
 extern EFI_GUID gEfiEventNotificationTypeNmiGuid;
 extern EFI_GUID gEfiEventNotificationTypeBootGuid;
 extern EFI_GUID gEfiEventNotificationTypeDmarGuid;
+extern EFI_GUID gEfiEventNotificationTypeSeaGuid;
+extern EFI_GUID gEfiEventNotificationTypeSeiGuid;
+extern EFI_GUID gEfiEventNotificationTypePeiGuid;
 
 extern EFI_GUID gEfiProcessorGenericErrorSectionGuid;
 extern EFI_GUID gEfiProcessorSpecificErrorSectionGuid;
diff --git a/MdePkg/Include/Guid/DebugImageInfoTable.h b/MdePkg/Include/Guid/DebugImageInfoTable.h
index 553ebd258854..7940f8d6fd9e 100644
--- a/MdePkg/Include/Guid/DebugImageInfoTable.h
+++ b/MdePkg/Include/Guid/DebugImageInfoTable.h
@@ -1,14 +1,8 @@
 /** @file
   GUID and related data structures used with the Debug Image Info Table.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   GUID defined in UEFI 2.0 spec.
@@ -35,7 +29,7 @@
 
 typedef struct {
   UINT64                Signature;          ///< A constant UINT64 that has the value EFI_SYSTEM_TABLE_SIGNATURE
-  EFI_PHYSICAL_ADDRESS  EfiSystemTableBase; ///< The physical address of the EFI system table. 
+  EFI_PHYSICAL_ADDRESS  EfiSystemTableBase; ///< The physical address of the EFI system table.
   UINT32                Crc32;              ///< A 32-bit CRC value that is used to verify the EFI_SYSTEM_TABLE_POINTER structure is valid.
 } EFI_SYSTEM_TABLE_POINTER;
 
diff --git a/MdePkg/Include/Guid/DxeServices.h b/MdePkg/Include/Guid/DxeServices.h
index be2b5b3e96d0..8c5f7e927b4c 100644
--- a/MdePkg/Include/Guid/DxeServices.h
+++ b/MdePkg/Include/Guid/DxeServices.h
@@ -1,14 +1,8 @@
 /** @file
   GUID used to identify the DXE Services Table
 
-  Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   GUID introduced in PI Version 1.0.
diff --git a/MdePkg/Include/Guid/EventGroup.h b/MdePkg/Include/Guid/EventGroup.h
index 04ee0e0fdaad..1614c542bf89 100644
--- a/MdePkg/Include/Guid/EventGroup.h
+++ b/MdePkg/Include/Guid/EventGroup.h
@@ -1,21 +1,15 @@
 /** @file
   GUIDs for gBS->CreateEventEx Event Groups. Defined in UEFI spec 2.0 and PI 1.2.1.
 
-Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
 #ifndef __EVENT_GROUP_GUID__
 #define __EVENT_GROUP_GUID__
 
-                                             
+
 #define EFI_EVENT_GROUP_EXIT_BOOT_SERVICES \
   { 0x27abf055, 0xb1b8, 0x4c26, { 0x80, 0x48, 0x74, 0x8f, 0x37, 0xba, 0xa2, 0xdf } }
 
diff --git a/MdePkg/Include/Guid/EventLegacyBios.h b/MdePkg/Include/Guid/EventLegacyBios.h
index f69aa18f9a21..038259bf20be 100644
--- a/MdePkg/Include/Guid/EventLegacyBios.h
+++ b/MdePkg/Include/Guid/EventLegacyBios.h
@@ -1,16 +1,10 @@
 /** @file
-  GUID is the name of events used with CreateEventEx in order to be notified 
+  GUID is the name of events used with CreateEventEx in order to be notified
   when the EFI boot manager is about to boot a legacy boot option.
-  Events of this type are notificated just before Int19h is invoked. 
+  Events of this type are notificated just before Int19h is invoked.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   GUID introduced in PI Version 1.0.
diff --git a/MdePkg/Include/Guid/FileInfo.h b/MdePkg/Include/Guid/FileInfo.h
index 5a2e081b4672..db359799ad67 100644
--- a/MdePkg/Include/Guid/FileInfo.h
+++ b/MdePkg/Include/Guid/FileInfo.h
@@ -3,14 +3,8 @@
   and EFI_FILE_PROTOCOL.GetInfo() to set or get generic file information.
   This GUID is defined in UEFI specification.
 
-Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/Guid/FileSystemInfo.h b/MdePkg/Include/Guid/FileSystemInfo.h
index f666ae5571ab..3a0aa9d66be5 100644
--- a/MdePkg/Include/Guid/FileSystemInfo.h
+++ b/MdePkg/Include/Guid/FileSystemInfo.h
@@ -3,14 +3,8 @@
   or EFI_FILE_PROTOCOL.SetInfo() to get or set information about the system's volume.
   This GUID is defined in UEFI specification.
 
-Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.                                                        
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/Guid/FileSystemVolumeLabelInfo.h b/MdePkg/Include/Guid/FileSystemVolumeLabelInfo.h
index 0f41f9a34e03..9be7a7c33fce 100644
--- a/MdePkg/Include/Guid/FileSystemVolumeLabelInfo.h
+++ b/MdePkg/Include/Guid/FileSystemVolumeLabelInfo.h
@@ -3,14 +3,8 @@
   or EFI_FILE_PROTOCOL.SetInfo() to get or set the system's volume label.
   This GUID is defined in UEFI specification.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/Guid/FirmwareContentsSigned.h b/MdePkg/Include/Guid/FirmwareContentsSigned.h
index c13a21eb1356..1748da8f5601 100644
--- a/MdePkg/Include/Guid/FirmwareContentsSigned.h
+++ b/MdePkg/Include/Guid/FirmwareContentsSigned.h
@@ -1,14 +1,8 @@
 /** @file
   GUID is used to define the signed section.
 
-  Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   GUID introduced in PI Version 1.2.1.
diff --git a/MdePkg/Include/Guid/FirmwareFileSystem2.h b/MdePkg/Include/Guid/FirmwareFileSystem2.h
index 9e12fd608444..1d4cfd3cf08a 100644
--- a/MdePkg/Include/Guid/FirmwareFileSystem2.h
+++ b/MdePkg/Include/Guid/FirmwareFileSystem2.h
@@ -1,14 +1,8 @@
 /** @file
   Guid used to define the Firmware File System 2.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   GUIDs introduced in PI Version 1.0.
@@ -18,18 +12,18 @@
 #ifndef __FIRMWARE_FILE_SYSTEM2_GUID_H__
 #define __FIRMWARE_FILE_SYSTEM2_GUID_H__
 
-/// 
-/// The firmware volume header contains a data field for 
+///
+/// The firmware volume header contains a data field for
 /// the file system GUID
-/// 
+///
 #define EFI_FIRMWARE_FILE_SYSTEM2_GUID \
   { 0x8c8ce578, 0x8a3d, 0x4f1c, { 0x99, 0x35, 0x89, 0x61, 0x85, 0xc3, 0x2d, 0xd3 } }
 
 ///
-/// A Volume Top File (VTF) is a file that must be 
-/// located such that the last byte of the file is 
+/// A Volume Top File (VTF) is a file that must be
+/// located such that the last byte of the file is
 /// also the last byte of the firmware volume
-/// 
+///
 #define EFI_FFS_VOLUME_TOP_FILE_GUID \
   { 0x1BA0062E, 0xC779, 0x4582, { 0x85, 0x66, 0x33, 0x6A, 0xE8, 0xF7, 0x8F, 0x9 } }
 
diff --git a/MdePkg/Include/Guid/FirmwareFileSystem3.h b/MdePkg/Include/Guid/FirmwareFileSystem3.h
index 37ee56a97afd..a9c7fb9f203c 100644
--- a/MdePkg/Include/Guid/FirmwareFileSystem3.h
+++ b/MdePkg/Include/Guid/FirmwareFileSystem3.h
@@ -1,14 +1,8 @@
 /** @file
   Guid used to define the Firmware File System 3.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   GUIDs introduced in PI Version 1.0.
@@ -18,7 +12,7 @@
 #ifndef __FIRMWARE_FILE_SYSTEM3_GUID_H__
 #define __FIRMWARE_FILE_SYSTEM3_GUID_H__
 
-/// 
+///
 /// The firmware volume header contains a data field for the file system GUID
 /// {5473C07A-3DCB-4dca-BD6F-1E9689E7349A}
 ///
diff --git a/MdePkg/Include/Guid/FmpCapsule.h b/MdePkg/Include/Guid/FmpCapsule.h
index 2d97b109d093..c19671e8456d 100644
--- a/MdePkg/Include/Guid/FmpCapsule.h
+++ b/MdePkg/Include/Guid/FmpCapsule.h
@@ -3,13 +3,7 @@
   Management Protocol
 
   Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   GUIDs defined in UEFI 2.4 spec.
@@ -85,13 +79,22 @@ typedef struct {
   /// therefore can be modified without changing the Auth data.
   ///
   UINT64   UpdateHardwareInstance;
+
+  ///
+  /// A 64-bit bitmask that determines what sections are added to the payload.
+  /// #define CAPSULE_SUPPORT_AUTHENTICATION 0x0000000000000001
+  /// #define CAPSULE_SUPPORT_DEPENDENCY 0x0000000000000002
+  ///
+  UINT64   ImageCapsuleSupport;
 } EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER;
 
 #pragma pack()
 
 
 #define EFI_FIRMWARE_MANAGEMENT_CAPSULE_HEADER_INIT_VERSION       0x00000001
-#define EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER_INIT_VERSION 0x00000002
+#define EFI_FIRMWARE_MANAGEMENT_CAPSULE_IMAGE_HEADER_INIT_VERSION 0x00000003
+#define CAPSULE_SUPPORT_AUTHENTICATION    0x0000000000000001
+#define CAPSULE_SUPPORT_DEPENDENCY        0x0000000000000002
 
 extern EFI_GUID gEfiFmpCapsuleGuid;
 
diff --git a/MdePkg/Include/Guid/GlobalVariable.h b/MdePkg/Include/Guid/GlobalVariable.h
index a0be1a94c604..b1e07ff543c1 100644
--- a/MdePkg/Include/Guid/GlobalVariable.h
+++ b/MdePkg/Include/Guid/GlobalVariable.h
@@ -1,14 +1,8 @@
 /** @file
   GUID for EFI (NVRAM) Variables.
 
-  Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   GUID defined in UEFI 2.1
diff --git a/MdePkg/Include/Guid/Gpt.h b/MdePkg/Include/Guid/Gpt.h
index af2b1a12f82c..8c45490c865b 100644
--- a/MdePkg/Include/Guid/Gpt.h
+++ b/MdePkg/Include/Guid/Gpt.h
@@ -1,17 +1,11 @@
 /** @file
   Guids used for the GPT (GUID Partition Table)
 
-  GPT defines a new disk partitioning scheme and also describes 
-  usage of the legacy Master Boot Record (MBR) partitioning scheme. 
+  GPT defines a new disk partitioning scheme and also describes
+  usage of the legacy Master Boot Record (MBR) partitioning scheme.
 
-  Copyright (c) 2006 - 2007, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   GUIDs defined in UEFI 2.1 spec.
diff --git a/MdePkg/Include/Guid/GraphicsInfoHob.h b/MdePkg/Include/Guid/GraphicsInfoHob.h
index 46dd29ddb2d2..cd1965c38532 100644
--- a/MdePkg/Include/Guid/GraphicsInfoHob.h
+++ b/MdePkg/Include/Guid/GraphicsInfoHob.h
@@ -2,13 +2,7 @@
   Hob guid for Information about the graphics mode.
 
   Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution. The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This HOB is introduced in in PI Version 1.4.
diff --git a/MdePkg/Include/Guid/HardwareErrorVariable.h b/MdePkg/Include/Guid/HardwareErrorVariable.h
index 4f644155a1da..4385f5f7a216 100644
--- a/MdePkg/Include/Guid/HardwareErrorVariable.h
+++ b/MdePkg/Include/Guid/HardwareErrorVariable.h
@@ -2,13 +2,7 @@
   GUID for hardware error record variables.
 
   Copyright (c) 2007 - 2009, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   GUID defined in UEFI 2.1.
diff --git a/MdePkg/Include/Guid/HiiFormMapMethodGuid.h b/MdePkg/Include/Guid/HiiFormMapMethodGuid.h
index 8b37807f3d24..6fff5b606f95 100644
--- a/MdePkg/Include/Guid/HiiFormMapMethodGuid.h
+++ b/MdePkg/Include/Guid/HiiFormMapMethodGuid.h
@@ -1,14 +1,8 @@
 /** @file
   Guid used to identify HII FormMap configuration method.
 
-  Copyright (c) 2009, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   GUID defined in UEFI 2.2 spec.
diff --git a/MdePkg/Include/Guid/HiiKeyBoardLayout.h b/MdePkg/Include/Guid/HiiKeyBoardLayout.h
index c2619713ed27..8f584b0930ff 100644
--- a/MdePkg/Include/Guid/HiiKeyBoardLayout.h
+++ b/MdePkg/Include/Guid/HiiKeyBoardLayout.h
@@ -1,15 +1,9 @@
 /** @file
 
   HII keyboard layout GUID as defined in UEFI2.1 specification
-  
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   GUIDs defined in UEFI 2.1 spec.
diff --git a/MdePkg/Include/Guid/HiiPlatformSetupFormset.h b/MdePkg/Include/Guid/HiiPlatformSetupFormset.h
index 2503879a4c7a..e0a38a2aa8ad 100644
--- a/MdePkg/Include/Guid/HiiPlatformSetupFormset.h
+++ b/MdePkg/Include/Guid/HiiPlatformSetupFormset.h
@@ -1,15 +1,9 @@
 /** @file
-  GUID indicates that the form set contains forms designed to be used 
+  GUID indicates that the form set contains forms designed to be used
   for platform configuration and this form set will be displayed.
 
-Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   GUID defined in UEFI 2.1.
@@ -28,8 +22,12 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #define EFI_HII_USER_CREDENTIAL_FORMSET_GUID \
   { 0x337f4407, 0x5aee, 0x4b83, { 0xb2, 0xa7, 0x4e, 0xad, 0xca, 0x30, 0x88, 0xcd } }
 
+#define EFI_HII_REST_STYLE_FORMSET_GUID \
+  { 0x790217bd, 0xbecf, 0x485b, { 0x91, 0x70, 0x5f, 0xf7, 0x11, 0x31, 0x8b, 0x27 } }
+
 extern EFI_GUID gEfiHiiPlatformSetupFormsetGuid;
 extern EFI_GUID gEfiHiiDriverHealthFormsetGuid;
 extern EFI_GUID gEfiHiiUserCredentialFormsetGuid;
+extern EFI_GUID gEfiHiiRestStyleFormsetGuid;
 
 #endif
diff --git a/MdePkg/Include/Guid/HobList.h b/MdePkg/Include/Guid/HobList.h
index 94c1a58e0f03..e44faedc171b 100644
--- a/MdePkg/Include/Guid/HobList.h
+++ b/MdePkg/Include/Guid/HobList.h
@@ -3,14 +3,8 @@
 
   These GUIDs point the HOB List passed from PEI to DXE.
 
-  Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   GUID introduced in PI Version 1.0.
diff --git a/MdePkg/Include/Guid/ImageAuthentication.h b/MdePkg/Include/Guid/ImageAuthentication.h
index a81b79b83850..84b52b969510 100644
--- a/MdePkg/Include/Guid/ImageAuthentication.h
+++ b/MdePkg/Include/Guid/ImageAuthentication.h
@@ -1,14 +1,8 @@
 /** @file
   Image signature database are defined for the signed image validation.
 
-  Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   GUIDs defined in UEFI 2.5 spec.
@@ -319,7 +313,7 @@ typedef struct {
   /// Zero or more image signatures. If the image contained no signatures,
   /// then this field is empty.
   /// EFI_SIGNATURE_LIST            Signature;
-  /// 
+  ///
 } EFI_IMAGE_EXECUTION_INFO;
 
 
diff --git a/MdePkg/Include/Guid/JsonCapsule.h b/MdePkg/Include/Guid/JsonCapsule.h
new file mode 100644
index 000000000000..d54c50694f5c
--- /dev/null
+++ b/MdePkg/Include/Guid/JsonCapsule.h
@@ -0,0 +1,98 @@
+/** @file
+Guid & data structure for tables defined for reporting firmware configuration data to EFI
+Configuration Tables and also for processing JSON payload capsule.
+
+
+Copyright (c) 2020, American Megatrends International LLC. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __JSON_CAPSULE_GUID_H__
+#define __JSON_CAPSULE_GUID_H__
+
+//
+// The address reported in the table entry identified by EFI_JSON_CAPSULE_DATA_TABLE_GUID will be
+// referenced as physical and will not be fixed up when transition from preboot to runtime phase. The
+// addresses reported in these table entries identified by EFI_JSON_CONFIG_DATA_TABLE_GUID and
+// EFI_JSON_CAPSULE_RESULT_TABLE_GUID will be referenced as virtual and will be fixed up when
+// transition from preboot to runtime phase.
+//
+#define EFI_JSON_CONFIG_DATA_TABLE_GUID \
+    {0x87367f87, 0x1119, 0x41ce, \
+    {0xaa, 0xec, 0x8b, 0xe0, 0x11, 0x1f, 0x55, 0x8a }}
+#define EFI_JSON_CAPSULE_DATA_TABLE_GUID \
+    {0x35e7a725, 0x8dd2, 0x4cac, \
+    {0x80, 0x11, 0x33, 0xcd, 0xa8, 0x10, 0x90, 0x56 }}
+#define EFI_JSON_CAPSULE_RESULT_TABLE_GUID \
+    {0xdbc461c3, 0xb3de, 0x422a,\
+    {0xb9, 0xb4, 0x98, 0x86, 0xfd, 0x49, 0xa1, 0xe5 }}
+#define EFI_JSON_CAPSULE_ID_GUID \
+    {0x67d6f4cd, 0xd6b8,  0x4573, \
+    {0xbf, 0x4a, 0xde, 0x5e, 0x25, 0x2d, 0x61, 0xae }}
+
+
+#pragma pack(1)
+
+typedef struct {
+  ///
+  /// Version of the structure, initially 0x00000001.
+  ///
+  UINT32 Version;
+
+  ///
+  /// The unique identifier of this capsule.
+  ///
+  UINT32 CapsuleId;
+
+  ///
+  /// The length of the JSON payload immediately following this header, in bytes.
+  ///
+  UINT32 PayloadLength;
+
+  ///
+  /// Variable length buffer containing the JSON payload that should be parsed and applied to the system. The
+  /// definition of the JSON schema used in the payload is beyond the scope of this specification.
+  ///
+  UINT8 Payload[];
+} EFI_JSON_CAPSULE_HEADER;
+
+typedef struct {
+  ///
+  /// The length of the following ConfigData, in bytes.
+  ///
+  UINT32 ConfigDataLength;
+
+  ///
+  /// Variable length buffer containing the JSON payload that describes one group of configuration data within
+  /// current system. The definition of the JSON schema used in this payload is beyond the scope of this specification.
+  ///
+  UINT8 ConfigData[];
+} EFI_JSON_CONFIG_DATA_ITEM;
+
+typedef struct {
+  ///
+  /// Version of the structure, initially 0x00000001.
+  ///
+  UINT32 Version;
+
+  ///
+  ////The total length of EFI_JSON_CAPSULE_CONFIG_DATA, in bytes.
+  ///
+  UINT32 TotalLength;
+
+  ///
+  /// Array of configuration data groups.
+  ///
+  EFI_JSON_CONFIG_DATA_ITEM ConfigDataList[];
+} EFI_JSON_CAPSULE_CONFIG_DATA;
+
+#pragma pack()
+
+extern EFI_GUID gEfiJsonConfigDataTableGuid;
+extern EFI_GUID gEfiJsonCapsuleDataTableGuid;
+extern EFI_GUID gEfiJsonCapsuleResultTableGuid;
+extern EFI_GUID gEfiJsonCapsuleIdGuid;
+
+
+#endif
diff --git a/MdePkg/Include/Guid/MdePkgTokenSpace.h b/MdePkg/Include/Guid/MdePkgTokenSpace.h
index 70896ef67da1..f20370e7062b 100644
--- a/MdePkg/Include/Guid/MdePkgTokenSpace.h
+++ b/MdePkg/Include/Guid/MdePkgTokenSpace.h
@@ -1,14 +1,8 @@
 /** @file
-  GUID for MdePkg PCD Token Space 
+  GUID for MdePkg PCD Token Space
 
-  Copyright (c) 2009, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/Guid/MemoryAllocationHob.h b/MdePkg/Include/Guid/MemoryAllocationHob.h
index 788920c4801c..1985abc04950 100644
--- a/MdePkg/Include/Guid/MemoryAllocationHob.h
+++ b/MdePkg/Include/Guid/MemoryAllocationHob.h
@@ -1,14 +1,8 @@
 /** @file
   GUIDs for HOBs used in memory allcation
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   GUIDs introduced in PI Version 1.0.
diff --git a/MdePkg/Include/Guid/MemoryAttributesTable.h b/MdePkg/Include/Guid/MemoryAttributesTable.h
index 1292771c2201..2b4e2aa7e649 100644
--- a/MdePkg/Include/Guid/MemoryAttributesTable.h
+++ b/MdePkg/Include/Guid/MemoryAttributesTable.h
@@ -2,13 +2,7 @@
   GUIDs used for UEFI Memory Attributes Table in the UEFI 2.6 specification.
 
   Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/Guid/MemoryOverwriteControl.h b/MdePkg/Include/Guid/MemoryOverwriteControl.h
index d6869a121a6f..9fba7eaf3a55 100644
--- a/MdePkg/Include/Guid/MemoryOverwriteControl.h
+++ b/MdePkg/Include/Guid/MemoryOverwriteControl.h
@@ -1,20 +1,14 @@
 /** @file
-  GUID used for MemoryOverwriteRequestControl UEFI variable defined in 
+  GUID used for MemoryOverwriteRequestControl UEFI variable defined in
   TCG Platform Reset Attack Mitigation Specification 1.00.
   See http://trustedcomputinggroup.org for the latest specification
 
-  The purpose of the MemoryOverwriteRequestControl UEFI variable is to give users (e.g., OS, loader) the ability to 
-  indicate to the platform that secrets are present in memory and that the platform firmware must clear memory upon 
-  a restart. The OS loader should not create the variable. Rather, the  firmware is required to create it. 
+  The purpose of the MemoryOverwriteRequestControl UEFI variable is to give users (e.g., OS, loader) the ability to
+  indicate to the platform that secrets are present in memory and that the platform firmware must clear memory upon
+  a restart. The OS loader should not create the variable. Rather, the  firmware is required to create it.
 
-  Copyright (c) 2009, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -27,17 +21,17 @@
   }
 
 ///
-///  Variable name is "MemoryOverwriteRequestControl" and it is a 1 byte unsigned value. 
-///  The attributes should be: 
-///  EFI_VARIABLE_NON_VOLATILE | 
-///  EFI_VARIABLE_BOOTSERVICE_ACCESS | 
-///  EFI_VARIABLE_RUNTIME_ACCESS 
+///  Variable name is "MemoryOverwriteRequestControl" and it is a 1 byte unsigned value.
+///  The attributes should be:
+///  EFI_VARIABLE_NON_VOLATILE |
+///  EFI_VARIABLE_BOOTSERVICE_ACCESS |
+///  EFI_VARIABLE_RUNTIME_ACCESS
 ///
 #define MEMORY_OVERWRITE_REQUEST_VARIABLE_NAME L"MemoryOverwriteRequestControl"
 
 ///
-/// 0 = Firmware MUST clear the MOR bi
-/// 1 = Firmware MUST set the MOR bit 
+/// 0 = Firmware MUST clear the MOR bit
+/// 1 = Firmware MUST set the MOR bit
 ///
 #define MOR_CLEAR_MEMORY_BIT_MASK        0x01
 
diff --git a/MdePkg/Include/Guid/Mps.h b/MdePkg/Include/Guid/Mps.h
index 4d4692e3be22..48f52b0e2bf0 100644
--- a/MdePkg/Include/Guid/Mps.h
+++ b/MdePkg/Include/Guid/Mps.h
@@ -3,14 +3,8 @@
   ACPI is the primary means of exporting MPS information to the OS. MPS only was
   included to support Itanium-based platform power on. So don't use it if you don't have too.
 
-  Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   GUIDs defined in UEFI 2.0 spec.
diff --git a/MdePkg/Include/Guid/PcAnsi.h b/MdePkg/Include/Guid/PcAnsi.h
index 7ff878d7f19e..312df6bd304f 100644
--- a/MdePkg/Include/Guid/PcAnsi.h
+++ b/MdePkg/Include/Guid/PcAnsi.h
@@ -1,14 +1,8 @@
 /** @file
   Terminal Device Path Vendor Guid.
 
-  Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   GUIDs defined in UEFI 2.0 spec.
@@ -42,7 +36,7 @@
   { \
     0x37499a9d, 0x542f, 0x4c89, {0xa0, 0x26, 0x35, 0xda, 0x14, 0x20, 0x94, 0xe4 } \
   }
-  
+
 #define EFI_SAS_DEVICE_PATH_GUID \
   { \
     0xd487ddb4, 0x008b, 0x11d9, {0xaf, 0xdc, 0x00, 0x10, 0x83, 0xff, 0xca, 0x4d } \
diff --git a/MdePkg/Include/Guid/PropertiesTable.h b/MdePkg/Include/Guid/PropertiesTable.h
deleted file mode 100644
index 7fa382686044..000000000000
--- a/MdePkg/Include/Guid/PropertiesTable.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/** @file
-  GUIDs used for UEFI Properties Table in the UEFI 2.5 specification.
-
-  Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __EFI_PROPERTIES_TABLE_H__
-#define __EFI_PROPERTIES_TABLE_H__
-
-#define EFI_PROPERTIES_TABLE_GUID {\
-  0x880aaca3, 0x4adc, 0x4a04, {0x90, 0x79, 0xb7, 0x47, 0x34, 0x8, 0x25, 0xe5} \
-}
-
-typedef struct {
-  UINT32    Version;
-  UINT32    Length;
-  UINT64    MemoryProtectionAttribute;
-} EFI_PROPERTIES_TABLE;
-
-#define EFI_PROPERTIES_TABLE_VERSION  0x00010000
-
-//
-// Memory attribute (Not defined bit is reserved)
-//
-#define EFI_PROPERTIES_RUNTIME_MEMORY_PROTECTION_NON_EXECUTABLE_PE_DATA        0x1
-
-extern EFI_GUID gEfiPropertiesTableGuid;
-
-#endif
diff --git a/MdePkg/Include/Guid/RtPropertiesTable.h b/MdePkg/Include/Guid/RtPropertiesTable.h
new file mode 100644
index 000000000000..9bad51f2cf0d
--- /dev/null
+++ b/MdePkg/Include/Guid/RtPropertiesTable.h
@@ -0,0 +1,69 @@
+/** @file
+Guid & data structure for EFI_RT _PROPERTIES_TABLE, designed to be published by a
+platform if it no longer  supports all EFI runtime services once ExitBootServices()
+has been called by the OS. Introduced in UEFI 2.8a.
+
+
+Copyright (c) 2020, American Megatrends International LLC. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __RT_PROPERTIES_TABLE_GUID_H__
+#define __RT_PROPERTIES_TABLE_GUID_H__
+
+//
+// Table, defined here, should be published by a platform if it no longer supports all EFI runtime
+// services once ExitBootServices() has been called by the OS. Note that this is merely a hint
+// to the OS, which it is free to ignore, and so the platform is still required to provide callable
+// implementations of unsupported runtime services that simply return EFI_UNSUPPORTED.
+//
+#define EFI_RT_PROPERTIES_TABLE_GUID \
+    { 0xeb66918a, 0x7eef, 0x402a, \
+    { 0x84, 0x2e, 0x93, 0x1d, 0x21, 0xc3, 0x8a, 0xe9 }}
+
+
+
+
+#pragma pack(1)
+
+typedef struct {
+  ///
+  /// Version of the structure, must be 0x1.
+  ///
+  UINT16 Version;
+
+  ///
+  /// Size in bytes of the entire EFI_RT_PROPERTIES_TABLE, must be 8.
+  ///
+  UINT16 Length;
+
+  ///
+  /// Bitmask of which calls are or are not supported, where a bit set to 1 indicates
+  /// that the call is supported, and 0 indicates that it is not.
+  ///
+  UINT32 RuntimeServicesSupported;
+} EFI_RT_PROPERTIES_TABLE;
+
+#pragma pack()
+
+#define EFI_RT_PROPERTIES_TABLE_VERSION 0x1
+
+#define EFI_RT_SUPPORTED_GET_TIME                       0x0001
+#define EFI_RT_SUPPORTED_SET_TIME                       0x0002
+#define EFI_RT_SUPPORTED_GET_WAKEUP_TIME                0x0004
+#define EFI_RT_SUPPORTED_SET_WAKEUP_TIME                0x0008
+#define EFI_RT_SUPPORTED_GET_VARIABLE                   0x0010
+#define EFI_RT_SUPPORTED_GET_NEXT_VARIABLE_NAME         0x0020
+#define EFI_RT_SUPPORTED_SET_VARIABLE                   0x0040
+#define EFI_RT_SUPPORTED_SET_VIRTUAL_ADDRESS_MAP        0x0080
+#define EFI_RT_SUPPORTED_CONVERT_POINTER                0x0100
+#define EFI_RT_SUPPORTED_GET_NEXT_HIGH_MONOTONIC_COUNT  0x0200
+#define EFI_RT_SUPPORTED_RESET_SYSTEM                   0x0400
+#define EFI_RT_SUPPORTED_UPDATE_CAPSULE                 0x0800
+#define EFI_RT_SUPPORTED_QUERY_CAPSULE_CAPABILITIES     0x1000
+#define EFI_RT_SUPPORTED_QUERY_VARIABLE_INFO            0x2000
+
+extern EFI_GUID gEfiRtPropertiesTableGuid;
+
+#endif
diff --git a/MdePkg/Include/Guid/SalSystemTable.h b/MdePkg/Include/Guid/SalSystemTable.h
deleted file mode 100644
index 8994ee7bdf3f..000000000000
--- a/MdePkg/Include/Guid/SalSystemTable.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/** @file
-  GUIDs used for SAL system table entries in the EFI system table.
-
-  SAL System Table contains Itanium-based processor centric information about
-  the system.
-
-  Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
-
-  @par Revision Reference:
-  GUIDs defined in UEFI 2.0 spec.
-
-**/
-
-#ifndef __SAL_SYSTEM_TABLE_GUID_H__
-#define __SAL_SYSTEM_TABLE_GUID_H__
-
-#define SAL_SYSTEM_TABLE_GUID \
-  { \
-    0xeb9d2d32, 0x2d88, 0x11d3, {0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \
-  }
-
-extern EFI_GUID gEfiSalSystemTableGuid;
-
-#endif
diff --git a/MdePkg/Include/Guid/SmBios.h b/MdePkg/Include/Guid/SmBios.h
index 05e11b7b63da..9040e3b5adab 100644
--- a/MdePkg/Include/Guid/SmBios.h
+++ b/MdePkg/Include/Guid/SmBios.h
@@ -5,14 +5,8 @@
   locate the SMBIOS tables. Do not search the 0xF0000 segment to find SMBIOS
   tables.
 
-  Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   GUIDs defined in UEFI 2.5 spec.
diff --git a/MdePkg/Include/Guid/SmramMemoryReserve.h b/MdePkg/Include/Guid/SmramMemoryReserve.h
new file mode 100644
index 000000000000..955b2fb0fec5
--- /dev/null
+++ b/MdePkg/Include/Guid/SmramMemoryReserve.h
@@ -0,0 +1,45 @@
+/** @file
+  This is a special GUID extension Hob to describe SMRAM memory regions.
+
+  This file defines:
+  * the GUID used to identify the GUID HOB for reserving SMRAM regions.
+  * the data structure of SMRAM descriptor to describe SMRAM candidate regions
+  * values of state of SMRAM candidate regions
+  * the GUID specific data structure of HOB for reserving SMRAM regions.
+
+  Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  GUIDs defined in PI SPEC version 1.5.
+
+**/
+
+#ifndef _SMRAM_MEMORY_RESERVE_H_
+#define _SMRAM_MEMORY_RESERVE_H_
+
+#define EFI_SMM_SMRAM_MEMORY_GUID \
+  { \
+    0x6dadf1d1, 0xd4cc, 0x4910, {0xbb, 0x6e, 0x82, 0xb1, 0xfd, 0x80, 0xff, 0x3d } \
+  }
+
+/**
+* The GUID extension hob is to describe SMRAM memory regions supported by the platform.
+**/
+typedef struct {
+  ///
+  /// Designates the number of possible regions in the system
+  /// that can be usable for SMRAM.
+  ///
+  UINT32                NumberOfSmmReservedRegions;
+  ///
+  /// Used throughout this protocol to describe the candidate
+  /// regions for SMRAM that are supported by this platform.
+  ///
+  EFI_SMRAM_DESCRIPTOR  Descriptor[1];
+} EFI_SMRAM_HOB_DESCRIPTOR_BLOCK;
+
+extern EFI_GUID gEfiSmmSmramMemoryGuid;
+
+#endif
+
diff --git a/MdePkg/Include/Guid/StatusCodeDataTypeId.h b/MdePkg/Include/Guid/StatusCodeDataTypeId.h
index 8bbc3315bc62..60114dffa489 100644
--- a/MdePkg/Include/Guid/StatusCodeDataTypeId.h
+++ b/MdePkg/Include/Guid/StatusCodeDataTypeId.h
@@ -1,17 +1,11 @@
 /** @file
   GUID used to identify id for the caller who is initiating the Status Code.
 
-  Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
-  These GUIDs and structures are defined in UEFI Platform Initialization Specification 1.2 
+  These GUIDs and structures are defined in UEFI Platform Initialization Specification 1.2
   Volume 3: Shared Architectural Elements
 
 **/
@@ -38,12 +32,12 @@ typedef enum {
   ///
   EfiStringUnicode,
   ///
-  /// An EFI_STATUS_CODE_STRING_TOKEN representing the string.  The actual 
+  /// An EFI_STATUS_CODE_STRING_TOKEN representing the string.  The actual
   /// string can be obtained by querying the HII Database
   ///
   EfiStringToken
 } EFI_STRING_TYPE;
- 
+
 ///
 /// Specifies the format of the data in EFI_STATUS_CODE_STRING_DATA.String.
 ///
@@ -60,7 +54,7 @@ typedef struct {
   ///
   EFI_STRING_ID   Token;
 } EFI_STATUS_CODE_STRING_TOKEN;
- 
+
 typedef union {
   ///
   /// ASCII formatted string.
@@ -75,11 +69,11 @@ typedef union {
   ///
   EFI_STATUS_CODE_STRING_TOKEN  Hii;
 } EFI_STATUS_CODE_STRING;
- 
+
 ///
-/// This data type defines a string type of extended data. A string can accompany 
-/// any status code. The string can provide additional information about the 
-/// status code. The string can be ASCII, Unicode, or a Human Interface Infrastructure 
+/// This data type defines a string type of extended data. A string can accompany
+/// any status code. The string can provide additional information about the
+/// status code. The string can be ASCII, Unicode, or a Human Interface Infrastructure
 /// (HII) token/GUID pair.
 ///
 typedef struct {
@@ -89,14 +83,14 @@ typedef struct {
   /// sizeof (EFI_STATUS_CODE_STRING_DATA) - HeaderSize, and
   /// DataHeader.Type should be
   /// EFI_STATUS_CODE_DATA_TYPE_STRING_GUID.
-  /// 
-  EFI_STATUS_CODE_DATA           DataHeader; 
+  ///
+  EFI_STATUS_CODE_DATA           DataHeader;
   ///
   /// Specifies the format of the data in String.
   ///
   EFI_STRING_TYPE                StringType;
   ///
-  /// A pointer to the extended data. The data follows the format specified by 
+  /// A pointer to the extended data. The data follows the format specified by
   /// StringType.
   ///
   EFI_STATUS_CODE_STRING         String;
@@ -118,12 +112,13 @@ extern EFI_GUID gEfiStatusCodeDataTypeStringGuid;
 ///   - EFI_STATUS_CODE_EXCEP_EXTENDED_DATA
 ///   - EFI_STATUS_CODE_START_EXTENDED_DATA
 ///   - EFI_LEGACY_OPROM_EXTENDED_DATA
+///   - EFI_RETURN_STATUS_EXTENDED_DATA
 ///
 #define EFI_STATUS_CODE_SPECIFIC_DATA_GUID \
   { 0x335984bd, 0xe805, 0x409a, { 0xb8, 0xf8, 0xd2, 0x7e, 0xce, 0x5f, 0xf7, 0xa6 } }
 
 ///
-/// Extended data about the device path, which is used for many errors and 
+/// Extended data about the device path, which is used for many errors and
 /// progress codes to point to the device.
 ///
 /// The device path is used to point to the physical device in case there is more than one device
@@ -148,7 +143,7 @@ typedef struct {
   ///
   EFI_STATUS_CODE_DATA                 DataHeader;
   ///
-  /// The device path to the controller or the hardware device. Note that this parameter is a 
+  /// The device path to the controller or the hardware device. Note that this parameter is a
   /// variable-length device path structure and not a pointer to such a structure. This structure is
   /// populated only if it is a physical device. For virtual devices, the Size field in DataHeader
   /// is set to zero and this field is not populated.
@@ -183,7 +178,7 @@ typedef struct {
 ///
 /// This structure defines extended data describing a PCI resource allocation error.
 ///
-/// @par Note: 
+/// @par Note:
 ///   The following structure contains variable-length fields and cannot be defined as a C-style
 ///   structure.
 ///
@@ -209,7 +204,7 @@ typedef struct {
   ///
   /// DevicePathSize should be zero if it is a virtual device that is not associated with
   /// a device path. Otherwise, this parameter is the length of the variable-length
-  /// DevicePath. 
+  /// DevicePath.
   ///
   UINT16                             DevicePathSize;
   ///
@@ -223,9 +218,9 @@ typedef struct {
   ///
   UINT16                             AllocResSize;
   ///
-  /// The device path to the controller or the hardware device that did not get the requested 
-  /// resources. Note that this parameter is the variable-length device path structure and not 
-  /// a pointer to this structure. 
+  /// The device path to the controller or the hardware device that did not get the requested
+  /// resources. Note that this parameter is the variable-length device path structure and not
+  /// a pointer to this structure.
   ///
   //  EFI_DEVICE_PATH_PROTOCOL       DevicePath;
   ///
@@ -234,7 +229,7 @@ typedef struct {
   ///
   //  UINT8                          ReqRes[];
   ///
-  /// The allocated resources in the format of an ACPI 2.0 resource descriptor. This 
+  /// The allocated resources in the format of an ACPI 2.0 resource descriptor. This
   /// parameter is not a pointer; it is the complete resource descriptor.
   ///
   //  UINT8                          AllocRes[];
@@ -244,7 +239,7 @@ typedef struct {
 /// This structure provides a calculation for base-10 representations.
 ///
 /// Not consistent with PI 1.2 Specification.
-/// This data type is not defined in the PI 1.2 Specification, but is 
+/// This data type is not defined in the PI 1.2 Specification, but is
 /// required by several of the other data structures in this file.
 ///
 typedef struct {
@@ -253,16 +248,16 @@ typedef struct {
   ///
   INT16                            Value;
   ///
-  /// The INT16 number by which to raise the base-2 calculation. 
+  /// The INT16 number by which to raise the base-2 calculation.
   ///
   INT16                            Exponent;
 } EFI_EXP_BASE10_DATA;
 
 ///
-/// This structure provides the voltage at the time of error. It also provides 
-/// the threshold value indicating the minimum or maximum voltage that is considered 
-/// an error. If the voltage is less then the threshold, the error indicates that the 
-/// voltage fell below the minimum acceptable value. If the voltage is greater then the threshold, 
+/// This structure provides the voltage at the time of error. It also provides
+/// the threshold value indicating the minimum or maximum voltage that is considered
+/// an error. If the voltage is less then the threshold, the error indicates that the
+/// voltage fell below the minimum acceptable value. If the voltage is greater then the threshold,
 /// the error indicates that the voltage rose above the maximum acceptable value.
 ///
 typedef struct {
@@ -312,7 +307,7 @@ typedef struct {
   /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
   /// sizeof (EFI_COMPUTING_UNIT_TIMER_EXPIRED_ERROR_DATA) -
   /// HeaderSize, and DataHeader.Type should be
-  /// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.  
+  /// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
   ///
   EFI_STATUS_CODE_DATA  DataHeader;
   ///
@@ -341,11 +336,11 @@ typedef struct {
 ///
 /// This structure defines extended data for processor mismatch errors.
 ///
-/// This provides information to indicate which processors mismatch, and how they mismatch. The 
-/// status code contains the instance number of the processor that is in error. This structure's 
-/// Instance indicates the second processor that does not match. This differentiation allows the 
-/// consumer to determine which two processors do not match. The Attributes indicate what 
-/// mismatch is being reported. Because Attributes is a bit field, more than one mismatch can be 
+/// This provides information to indicate which processors mismatch, and how they mismatch. The
+/// status code contains the instance number of the processor that is in error. This structure's
+/// Instance indicates the second processor that does not match. This differentiation allows the
+/// consumer to determine which two processors do not match. The Attributes indicate what
+/// mismatch is being reported. Because Attributes is a bit field, more than one mismatch can be
 /// reported with one error code.
 ///
 typedef struct {
@@ -354,23 +349,23 @@ typedef struct {
   /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
   /// sizeof (EFI_ HOST_PROCESSOR_MISMATCH_ERROR_DATA) -
   /// HeaderSize , and DataHeader.Type should be
-  /// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.  
+  /// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
   ///
   EFI_STATUS_CODE_DATA  DataHeader;
   ///
   /// The unit number of the computing unit that does not match.
-  ///  
+  ///
   UINT32                Instance;
-  /// 
-  /// The attributes describing the failure. 
-  ///  
+  ///
+  /// The attributes describing the failure.
+  ///
   UINT16                Attributes;
 } EFI_HOST_PROCESSOR_MISMATCH_ERROR_DATA;
 
 ///
 /// This structure provides details about the computing unit thermal failure.
 ///
-/// This structure provides the temperature at the time of error. It also provides the threshold value 
+/// This structure provides the temperature at the time of error. It also provides the threshold value
 /// indicating the minimum temperature that is considered an error.
 ///
 typedef struct {
@@ -379,7 +374,7 @@ typedef struct {
   /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
   /// sizeof (EFI_COMPUTING_UNIT_THERMAL_ERROR_DATA) -
   /// HeaderSize , and DataHeader.Type should be
-  /// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.  
+  /// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
   ///
   EFI_STATUS_CODE_DATA  DataHeader;
   ///
@@ -429,7 +424,7 @@ typedef struct {
 typedef UINT32  EFI_CPU_STATE_CHANGE_CAUSE;
 
 ///
-/// The reasons that the processor is disabled.  
+/// The reasons that the processor is disabled.
 /// Used to fill in EFI_COMPUTING_UNIT_CPU_DISABLED_ERROR_DATA.Cause.
 ///
 ///@{
@@ -447,8 +442,8 @@ typedef UINT32  EFI_CPU_STATE_CHANGE_CAUSE;
 ///
 /// This structure provides information about the disabled computing unit.
 ///
-/// This structure provides details as to why and how the computing unit was disabled. The causes 
-/// should cover the typical reasons a processor would be disabled. How the processor was disabled is 
+/// This structure provides details as to why and how the computing unit was disabled. The causes
+/// should cover the typical reasons a processor would be disabled. How the processor was disabled is
 /// important because there are distinct differences between hardware and software disabling.
 ///
 typedef struct {
@@ -461,12 +456,12 @@ typedef struct {
   ///
   EFI_STATUS_CODE_DATA  DataHeader;
   ///
-  /// The reason for disabling the processor. 
-  /// 
+  /// The reason for disabling the processor.
+  ///
   UINT32                Cause;
   ///
-  /// TRUE if the processor is disabled via software means such as not listing it in the ACPI tables. 
-  /// Such a processor will respond to Interprocessor Interrupts (IPIs). FALSE if the processor is hardware 
+  /// TRUE if the processor is disabled via software means such as not listing it in the ACPI tables.
+  /// Such a processor will respond to Interprocessor Interrupts (IPIs). FALSE if the processor is hardware
   /// disabled, which means it is invisible to software and will not respond to IPIs.
   ///
   BOOLEAN               SoftwareDisabled;
@@ -504,8 +499,8 @@ typedef UINT8 EFI_MEMORY_ERROR_OPERATION;
 ///@}
 
 ///
-/// This structure provides specific details about the memory error that was detected. It provides 
-/// enough information so that consumers can identify the exact failure and provides enough 
+/// This structure provides specific details about the memory error that was detected. It provides
+/// enough information so that consumers can identify the exact failure and provides enough
 /// information to enable corrective action if necessary.
 ///
 typedef struct {
@@ -513,7 +508,7 @@ typedef struct {
   /// The data header identifying the data. DataHeader.HeaderSize should be
   /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
   /// sizeof (EFI_MEMORY_EXTENDED_ERROR_DATA) - HeaderSize, and
-  /// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.  
+  /// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
   ///
   EFI_STATUS_CODE_DATA          DataHeader;
   ///
@@ -521,18 +516,18 @@ typedef struct {
   ///
   EFI_MEMORY_ERROR_GRANULARITY  Granularity;
   ///
-  /// The operation that resulted in the error being detected. 
+  /// The operation that resulted in the error being detected.
   ///
   EFI_MEMORY_ERROR_OPERATION    Operation;
   ///
-  /// The error syndrome, vendor-specific ECC syndrome, or CRC data associated with 
+  /// The error syndrome, vendor-specific ECC syndrome, or CRC data associated with
   /// the error.  If unknown, should be initialized to 0.
-  /// Inconsistent with specification here:  
+  /// Inconsistent with specification here:
   /// This field in StatusCodes spec0.9 is defined as UINT32, keep code unchanged.
   ///
   UINTN                         Syndrome;
   ///
-  /// The physical address of the error. 
+  /// The physical address of the error.
   ///
   EFI_PHYSICAL_ADDRESS          Address;
   ///
@@ -543,31 +538,31 @@ typedef struct {
 
 ///
 /// A definition to describe that the operation is performed on multiple devices within the array.
-/// May be used for EFI_STATUS_CODE_DIMM_NUMBER.Array and EFI_STATUS_CODE_DIMM_NUMBER.Device. 
+/// May be used for EFI_STATUS_CODE_DIMM_NUMBER.Array and EFI_STATUS_CODE_DIMM_NUMBER.Device.
 ///
 #define EFI_MULTIPLE_MEMORY_DEVICE_OPERATION 0xfffe
 
 ///
 /// A definition to describe that the operation is performed on all devices within the array.
-/// May be used for EFI_STATUS_CODE_DIMM_NUMBER.Array and EFI_STATUS_CODE_DIMM_NUMBER.Device. 
+/// May be used for EFI_STATUS_CODE_DIMM_NUMBER.Array and EFI_STATUS_CODE_DIMM_NUMBER.Device.
 ///
 #define EFI_ALL_MEMORY_DEVICE_OPERATION 0xffff
 
 ///
 /// A definition to describe that the operation is performed on multiple arrays.
-/// May be used for EFI_STATUS_CODE_DIMM_NUMBER.Array and EFI_STATUS_CODE_DIMM_NUMBER.Device. 
+/// May be used for EFI_STATUS_CODE_DIMM_NUMBER.Array and EFI_STATUS_CODE_DIMM_NUMBER.Device.
 ///
 #define EFI_MULTIPLE_MEMORY_ARRAY_OPERATION 0xfffe
 
 ///
 /// A definition to describe that the operation is performed on all the arrays.
-/// May be used for EFI_STATUS_CODE_DIMM_NUMBER.Array and EFI_STATUS_CODE_DIMM_NUMBER.Device. 
+/// May be used for EFI_STATUS_CODE_DIMM_NUMBER.Array and EFI_STATUS_CODE_DIMM_NUMBER.Device.
 ///
 #define EFI_ALL_MEMORY_ARRAY_OPERATION 0xffff
 
 ///
-/// This extended data provides some context that consumers can use to locate a DIMM within the 
-/// overall memory scheme.  
+/// This extended data provides some context that consumers can use to locate a DIMM within the
+/// overall memory scheme.
 ///
 /// This extended data provides some context that consumers can use to locate a DIMM within the
 /// overall memory scheme. The Array and Device numbers may indicate a specific DIMM, or they
@@ -595,7 +590,7 @@ typedef struct {
 /// This structure defines extended data describing memory modules that do not match.
 ///
 /// This extended data may be used to convey the specifics of memory modules that do not match.
-/// 
+///
 typedef struct {
   ///
   /// The data header identifying the data. DataHeader.HeaderSize should be
@@ -606,7 +601,7 @@ typedef struct {
   ///
   EFI_STATUS_CODE_DATA         DataHeader;
   ///
-  /// The instance number of the memory module that does not match. 
+  /// The instance number of the memory module that does not match.
   ///
   EFI_STATUS_CODE_DIMM_NUMBER  Instance;
 } EFI_MEMORY_MODULE_MISMATCH_ERROR_DATA;
@@ -614,7 +609,7 @@ typedef struct {
 ///
 /// This structure defines extended data describing a memory range.
 ///
-/// This extended data may be used to convey the specifics of a memory range.  Ranges are specified 
+/// This extended data may be used to convey the specifics of a memory range.  Ranges are specified
 /// with a start address and a length.
 ///
 typedef struct {
@@ -622,11 +617,11 @@ typedef struct {
   /// The data header identifying the data. DataHeader.HeaderSize should be
   /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
   /// sizeof (EFI_MEMORY_RANGE_EXTENDED_DATA) - HeaderSize, and
-  /// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.  
+  /// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
   ///
   EFI_STATUS_CODE_DATA  DataHeader;
   ///
-  /// The starting address of the memory range. 
+  /// The starting address of the memory range.
   ///
   EFI_PHYSICAL_ADDRESS  Start;
   ///
@@ -647,7 +642,7 @@ typedef struct {
   /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
   /// sizeof (EFI_DEBUG_ASSERT_DATA) - HeaderSize , and
   /// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
-  /// 
+  ///
   EFI_STATUS_CODE_DATA         DataHeader;
   ///
   /// The line number of the source file where the fault was generated.
@@ -658,7 +653,7 @@ typedef struct {
   ///
   UINT32                       FileNameSize;
   ///
-  /// A pointer to a NULL-terminated ASCII or Unicode string that represents 
+  /// A pointer to a NULL-terminated ASCII or Unicode string that represents
   /// the file name of the source file where the fault was generated.
   ///
   EFI_STATUS_CODE_STRING_DATA  *FileName;
@@ -691,7 +686,7 @@ typedef union {
   /// EFI_SYSTEM_CONTEXT_X64 is defined in the
   /// EFI_DEBUG_SUPPORT_PROTOCOL in the UEFI Specification.
   ///
-  EFI_SYSTEM_CONTEXT_X64  SystemContextX64; 
+  EFI_SYSTEM_CONTEXT_X64  SystemContextX64;
   ///
   /// The context of the ARM processor when the exception was generated. Type
   /// EFI_SYSTEM_CONTEXT_ARM is defined in the
@@ -713,11 +708,11 @@ typedef struct {
   /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
   /// sizeof (EFI_STATUS_CODE_EXCEP_EXTENDED_DATA) - HeaderSize,
   /// and DataHeader.Type should be
-  /// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.  
+  /// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
   ///
   EFI_STATUS_CODE_DATA                  DataHeader;
   ///
-  /// The system context. 
+  /// The system context.
   ///
   EFI_STATUS_CODE_EXCEP_SYSTEM_CONTEXT  Context;
 } EFI_STATUS_CODE_EXCEP_EXTENDED_DATA;
@@ -729,33 +724,33 @@ typedef struct {
 /// the UEFI Driver Binding Protocol.
 ///
 typedef struct {
-  /// 
+  ///
   /// The data header identifying the data. DataHeader.HeaderSize should be
   /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
   /// sizeof (EFI_STATUS_CODE_START_EXTENDED_DATA) - HeaderSize,
   /// and DataHeader.Type should be
-  /// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.  
+  /// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
   ///
   EFI_STATUS_CODE_DATA           DataHeader;
   ///
-  /// The controller handle. 
+  /// The controller handle.
   ///
   EFI_HANDLE                     ControllerHandle;
   ///
   /// The driver binding handle.
   ///
   EFI_HANDLE                     DriverBindingHandle;
-  /// 
-  /// The size of the RemainingDevicePath. It is zero if the Start() function is 
+  ///
+  /// The size of the RemainingDevicePath. It is zero if the Start() function is
   /// called with RemainingDevicePath = NULL.  The UEFI Specification allows
   /// that the Start() function of bus drivers can be called in this way.
   ///
   UINT16                         DevicePathSize;
   ///
-  /// Matches the RemainingDevicePath parameter being passed to the Start() function. 
-  /// Note that this parameter is the variable-length device path and not a pointer 
+  /// Matches the RemainingDevicePath parameter being passed to the Start() function.
+  /// Note that this parameter is the variable-length device path and not a pointer
   /// to the device path.
-  ///  
+  ///
   //  EFI_DEVICE_PATH_PROTOCOL   RemainingDevicePath;
 } EFI_STATUS_CODE_START_EXTENDED_DATA;
 
@@ -771,7 +766,7 @@ typedef struct {
   /// The data header identifying the data. DataHeader.HeaderSize should be
   /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
   /// sizeof (EFI_LEGACY_OPROM_EXTENDED_DATA) - HeaderSize, and
-  /// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.  
+  /// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
   ///
   EFI_STATUS_CODE_DATA  DataHeader;
   ///
@@ -779,11 +774,30 @@ typedef struct {
   ///
   EFI_HANDLE            DeviceHandle;
   ///
-  /// The base address of the shadowed legacy ROM image.  May or may not point to the shadow RAM area. 
+  /// The base address of the shadowed legacy ROM image.  May or may not point to the shadow RAM area.
   ///
   EFI_PHYSICAL_ADDRESS  RomImageBase;
 } EFI_LEGACY_OPROM_EXTENDED_DATA;
 
+///
+/// This structure defines extended data describing an EFI_STATUS return value that stands for a
+/// failed function call (such as a UEFI boot service).
+///
+typedef struct {
+  ///
+  /// The data header identifying the data:
+  /// DataHeader.HeaderSize should be sizeof(EFI_STATUS_CODE_DATA),
+  /// DataHeader.Size should be sizeof(EFI_RETURN_STATUS_EXTENDED_DATA) - HeaderSize,
+  /// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
+  ///
+  EFI_STATUS_CODE_DATA DataHeader;
+  ///
+  /// The EFI_STATUS return value of the service or function whose failure triggered the
+  /// reporting of the status code (generally an error code or a debug code).
+  ///
+  EFI_STATUS           ReturnStatus;
+} EFI_RETURN_STATUS_EXTENDED_DATA;
+
 extern EFI_GUID gEfiStatusCodeSpecificDataGuid;
 
 #endif
diff --git a/MdePkg/Include/Guid/SystemResourceTable.h b/MdePkg/Include/Guid/SystemResourceTable.h
index dc7e16bd241f..4b6ecc2b06b7 100644
--- a/MdePkg/Include/Guid/SystemResourceTable.h
+++ b/MdePkg/Include/Guid/SystemResourceTable.h
@@ -1,14 +1,8 @@
 /** @file
   Guid & data structure used for EFI System Resource Table (ESRT)
 
-  Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution. The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   GUIDs defined in UEFI 2.5 spec.
@@ -40,14 +34,15 @@
 ///
 /// Last Attempt Status Values
 ///
-#define LAST_ATTEMPT_STATUS_SUCCESS                       0x00000000
-#define LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL            0x00000001
-#define LAST_ATTEMPT_STATUS_ERROR_INSUFFICIENT_RESOURCES  0x00000002
-#define LAST_ATTEMPT_STATUS_ERROR_INCORRECT_VERSION       0x00000003
-#define LAST_ATTEMPT_STATUS_ERROR_INVALID_FORMAT          0x00000004
-#define LAST_ATTEMPT_STATUS_ERROR_AUTH_ERROR              0x00000005
-#define LAST_ATTEMPT_STATUS_ERROR_PWR_EVT_AC              0x00000006
-#define LAST_ATTEMPT_STATUS_ERROR_PWR_EVT_BATT            0x00000007
+#define LAST_ATTEMPT_STATUS_SUCCESS                         0x00000000
+#define LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL              0x00000001
+#define LAST_ATTEMPT_STATUS_ERROR_INSUFFICIENT_RESOURCES    0x00000002
+#define LAST_ATTEMPT_STATUS_ERROR_INCORRECT_VERSION         0x00000003
+#define LAST_ATTEMPT_STATUS_ERROR_INVALID_FORMAT            0x00000004
+#define LAST_ATTEMPT_STATUS_ERROR_AUTH_ERROR                0x00000005
+#define LAST_ATTEMPT_STATUS_ERROR_PWR_EVT_AC                0x00000006
+#define LAST_ATTEMPT_STATUS_ERROR_PWR_EVT_BATT              0x00000007
+#define LAST_ATTEMPT_STATUS_ERROR_UNSATISFIED_DEPENDENCIES  0x00000008
 
 typedef struct {
   ///
diff --git a/MdePkg/Include/Guid/VectorHandoffTable.h b/MdePkg/Include/Guid/VectorHandoffTable.h
index 256b34550f4b..874f9f62c7ba 100644
--- a/MdePkg/Include/Guid/VectorHandoffTable.h
+++ b/MdePkg/Include/Guid/VectorHandoffTable.h
@@ -1,15 +1,9 @@
 /** @file
   GUID for system configuration table entry that points to the table
-  in case an entity in DXE wishes to update/change the vector table contents. 
+  in case an entity in DXE wishes to update/change the vector table contents.
 
-  Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   GUID defined in PI 1.2.1 spec.
diff --git a/MdePkg/Include/Guid/WinCertificate.h b/MdePkg/Include/Guid/WinCertificate.h
index 6dea446ba060..c44bb388cccc 100644
--- a/MdePkg/Include/Guid/WinCertificate.h
+++ b/MdePkg/Include/Guid/WinCertificate.h
@@ -2,13 +2,7 @@
   GUID for UEFI WIN_CERTIFICATE structure.
 
   Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   GUID defined in UEFI 2.0 spec.
diff --git a/MdePkg/Include/Ia32/Nasm.inc b/MdePkg/Include/Ia32/Nasm.inc
new file mode 100644
index 000000000000..dbfcb740800d
--- /dev/null
+++ b/MdePkg/Include/Ia32/Nasm.inc
@@ -0,0 +1,22 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Abstract:
+;
+;   This file provides macro definitions for NASM files.
+;
+;------------------------------------------------------------------------------
+
+%macro SETSSBSY        0
+    DB 0xF3, 0x0F, 0x01, 0xE8
+%endmacro
+
+%macro READSSP_EAX     0
+    DB 0xF3, 0x0F, 0x1E, 0xC8
+%endmacro
+
+%macro INCSSP_EAX      0
+    DB 0xF3, 0x0F, 0xAE, 0xE8
+%endmacro
diff --git a/MdePkg/Include/Ia32/ProcessorBind.h b/MdePkg/Include/Ia32/ProcessorBind.h
index 9eb6954706d7..b10c641efdd9 100644
--- a/MdePkg/Include/Ia32/ProcessorBind.h
+++ b/MdePkg/Include/Ia32/ProcessorBind.h
@@ -1,14 +1,8 @@
 /** @file
   Processor or Compiler specific defines and types for IA-32 architecture.
 
-Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -93,24 +87,24 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 //
 #pragma warning ( disable : 4206 )
 
-#if _MSC_VER == 1800 || _MSC_VER == 1900
+#if defined(_MSC_VER) && _MSC_VER >= 1800
 
 //
 // Disable these warnings for VS2013.
 //
 
 //
-// This warning is for potentially uninitialized local variable, and it may cause false 
+// This warning is for potentially uninitialized local variable, and it may cause false
 // positive issues in VS2013 and VS2015 build
 //
 #pragma warning ( disable : 4701 )
-  
+
 //
-// This warning is for potentially uninitialized local pointer variable, and it may cause 
+// This warning is for potentially uninitialized local pointer variable, and it may cause
 // false positive issues in VS2013 and VS2015 build
 //
 #pragma warning ( disable : 4703 )
-  
+
 #endif
 
 #endif
@@ -168,7 +162,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   /// 1-byte signed value.
   ///
   typedef signed char         INT8;
-#else  
+#else
   ///
   /// 8-byte unsigned value.
   ///
@@ -247,12 +241,22 @@ typedef INT32   INTN;
 #define MAX_ADDRESS   0xFFFFFFFF
 
 ///
+/// Maximum usable address at boot time
+///
+#define MAX_ALLOC_ADDRESS   MAX_ADDRESS
+
+///
 /// Maximum legal IA-32 INTN and UINTN values.
 ///
 #define MAX_INTN   ((INTN)0x7FFFFFFF)
 #define MAX_UINTN  ((UINTN)0xFFFFFFFF)
 
 ///
+/// Minimum legal IA-32 INTN value.
+///
+#define MIN_INTN   (((INTN)-2147483647) - 1)
+
+///
 /// The stack alignment required for IA-32.
 ///
 #define CPU_STACK_ALIGNMENT   sizeof(UINTN)
@@ -275,22 +279,22 @@ typedef INT32   INTN;
 #elif defined(_MSC_EXTENSIONS)
   ///
   /// Microsoft* compiler specific method for EFIAPI calling convention.
-  /// 
-  #define EFIAPI __cdecl  
-#elif defined(__GNUC__)
+  ///
+  #define EFIAPI __cdecl
+#elif defined(__GNUC__) || defined(__clang__)
   ///
   /// GCC specific method for EFIAPI calling convention.
-  /// 
-  #define EFIAPI __attribute__((cdecl))  
+  ///
+  #define EFIAPI __attribute__((cdecl))
 #else
   ///
   /// The default for a non Microsoft* or GCC compiler is to assume the EFI ABI
-  /// is the standard. 
+  /// is the standard.
   ///
   #define EFIAPI
 #endif
 
-#if defined(__GNUC__)
+#if defined(__GNUC__) || defined(__clang__)
   ///
   /// For GNU assembly code, .global or .globl can declare global symbols.
   /// Define this macro to unify the usage.
@@ -300,13 +304,13 @@ typedef INT32   INTN;
 
 /**
   Return the pointer to the first instruction of a function given a function pointer.
-  On IA-32 CPU architectures, these two pointer values are the same, 
+  On IA-32 CPU architectures, these two pointer values are the same,
   so the implementation of this macro is very simple.
-  
+
   @param  FunctionPointer   A pointer to a function.
 
   @return The pointer to the first instruction of a function given a function pointer.
-  
+
 **/
 #define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)
 
diff --git a/MdePkg/Include/IndustryStandard/Acpi.h b/MdePkg/Include/IndustryStandard/Acpi.h
index 3d35f599b4e6..a362d0f68f98 100644
--- a/MdePkg/Include/IndustryStandard/Acpi.h
+++ b/MdePkg/Include/IndustryStandard/Acpi.h
@@ -2,20 +2,15 @@
   This file contains the latest ACPI definitions that are
   consumed by drivers that do not care about ACPI versions.
 
-  Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2019, ARM Ltd. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
 #ifndef _ACPI_H_
 #define _ACPI_H_
 
-#include <IndustryStandard/Acpi61.h>
+#include <IndustryStandard/Acpi63.h>
 
 #endif
diff --git a/MdePkg/Include/IndustryStandard/Acpi10.h b/MdePkg/Include/IndustryStandard/Acpi10.h
index 5a17db6ac570..d1398018aef9 100644
--- a/MdePkg/Include/IndustryStandard/Acpi10.h
+++ b/MdePkg/Include/IndustryStandard/Acpi10.h
@@ -1,14 +1,8 @@
-/** @file   
+/** @file
   ACPI 1.0b definitions from the ACPI Specification, revision 1.0b
 
-Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
 #ifndef _ACPI_1_0_H_
@@ -43,7 +37,7 @@ typedef struct {
 #pragma pack()
 
 //
-// Define for Desriptor
+// Define for Descriptor
 //
 #define ACPI_SMALL_ITEM_FLAG                   0x00
 #define ACPI_LARGE_ITEM_FLAG                   0x01
@@ -115,7 +109,7 @@ typedef struct {
 #pragma pack(1)
 
 ///
-/// The commond definition of QWORD, DWORD, and WORD
+/// The common definition of QWORD, DWORD, and WORD
 /// Address Space Descriptors.
 ///
 typedef PACKED struct {
@@ -357,7 +351,7 @@ typedef struct {
 #define   EFI_ACPI_DMA_SPEED_TYPE_A                     0x20
 #define   EFI_ACPI_DMA_SPEED_TYPE_B                     0x40
 #define   EFI_ACPI_DMA_SPEED_TYPE_F                     0x60
-                                               
+
 #define EFI_ACPI_DMA_BUS_MASTER_MASK                    0x04
 #define   EFI_ACPI_DMA_BUS_MASTER                       0x04
 
@@ -403,7 +397,7 @@ typedef struct {
 
 //
 // Root System Description Table
-// No definition needed as it is a common description table header, the same with 
+// No definition needed as it is a common description table header, the same with
 // EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
 //
 
diff --git a/MdePkg/Include/IndustryStandard/Acpi20.h b/MdePkg/Include/IndustryStandard/Acpi20.h
index d84b7db7b7da..b4e19ae56ea6 100644
--- a/MdePkg/Include/IndustryStandard/Acpi20.h
+++ b/MdePkg/Include/IndustryStandard/Acpi20.h
@@ -1,14 +1,8 @@
-/** @file   
+/** @file
   ACPI 2.0 definitions from the ACPI Specification, revision 2.0
 
-  Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
 #ifndef _ACPI_2_0_H_
@@ -17,7 +11,7 @@
 #include <IndustryStandard/Acpi10.h>
 
 //
-// Define for Desriptor
+// Define for Descriptor
 //
 #define ACPI_LARGE_GENERIC_REGISTER_DESCRIPTOR_NAME          0x02
 
@@ -103,7 +97,7 @@ typedef struct {
 
 //
 // Root System Description Table
-// No definition needed as it is a common description table header, the same with 
+// No definition needed as it is a common description table header, the same with
 // EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
 //
 
@@ -114,7 +108,7 @@ typedef struct {
 
 //
 // Extended System Description Table
-// No definition needed as it is a common description table header, the same with 
+// No definition needed as it is a common description table header, the same with
 // EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
 //
 
@@ -511,7 +505,7 @@ typedef struct {
 #define EFI_ACPI_2_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE  SIGNATURE_32('S', 'L', 'I', 'T')
 
 ///
-/// "SPCR" Serial Port Concole Redirection Table
+/// "SPCR" Serial Port Console Redirection Table
 ///
 #define EFI_ACPI_2_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE  SIGNATURE_32('S', 'P', 'C', 'R')
 
diff --git a/MdePkg/Include/IndustryStandard/Acpi30.h b/MdePkg/Include/IndustryStandard/Acpi30.h
index d510d8b93469..4ef7bec7a5b4 100644
--- a/MdePkg/Include/IndustryStandard/Acpi30.h
+++ b/MdePkg/Include/IndustryStandard/Acpi30.h
@@ -1,14 +1,8 @@
-/** @file   
+/** @file
   ACPI 3.0 definitions from the ACPI Specification Revision 3.0b October 10, 2006
 
-  Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
 #ifndef _ACPI_3_0_H_
@@ -17,7 +11,7 @@
 #include <IndustryStandard/Acpi20.h>
 
 //
-// Define for Desriptor
+// Define for Descriptor
 //
 #define ACPI_LARGE_EXTENDED_ADDRESS_SPACE_DESCRIPTOR_NAME    0x0B
 
@@ -128,7 +122,7 @@ typedef struct {
 
 //
 // Root System Description Table
-// No definition needed as it is a common description table header, the same with 
+// No definition needed as it is a common description table header, the same with
 // EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
 //
 
@@ -139,7 +133,7 @@ typedef struct {
 
 //
 // Extended System Description Table
-// No definition needed as it is a common description table header, the same with 
+// No definition needed as it is a common description table header, the same with
 // EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
 //
 
@@ -597,7 +591,7 @@ typedef struct {
 ///
 /// "RSD PTR " Root System Description Pointer
 ///
-#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE  SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ') 
+#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE  SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
 
 ///
 /// "APIC" Multiple APIC Description Table
@@ -690,7 +684,7 @@ typedef struct {
 #define EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('M', 'C', 'F', 'G')
 
 ///
-/// "SPCR" Serial Port Concole Redirection Table
+/// "SPCR" Serial Port Console Redirection Table
 ///
 #define EFI_ACPI_3_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE  SIGNATURE_32('S', 'P', 'C', 'R')
 
diff --git a/MdePkg/Include/IndustryStandard/Acpi40.h b/MdePkg/Include/IndustryStandard/Acpi40.h
index 94ae5fc56727..cfd491d45de5 100644
--- a/MdePkg/Include/IndustryStandard/Acpi40.h
+++ b/MdePkg/Include/IndustryStandard/Acpi40.h
@@ -1,14 +1,8 @@
-/** @file   
+/** @file
   ACPI 4.0 definitions from the ACPI Specification Revision 4.0a April 5, 2010
 
-  Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
 #ifndef _ACPI_4_0_H_
@@ -86,7 +80,7 @@ typedef struct {
 
 //
 // Root System Description Table
-// No definition needed as it is a common description table header, the same with 
+// No definition needed as it is a common description table header, the same with
 // EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
 //
 
@@ -97,7 +91,7 @@ typedef struct {
 
 //
 // Extended System Description Table
-// No definition needed as it is a common description table header, the same with 
+// No definition needed as it is a common description table header, the same with
 // EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
 //
 
@@ -1132,7 +1126,7 @@ typedef struct {
 ///
 /// "RSD PTR " Root System Description Pointer
 ///
-#define EFI_ACPI_4_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE  SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ') 
+#define EFI_ACPI_4_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE  SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
 
 ///
 /// "APIC" Multiple APIC Description Table
@@ -1270,7 +1264,7 @@ typedef struct {
 #define EFI_ACPI_4_0_MANAGEMENT_CONTROLLER_HOST_INTERFACE_TABLE_SIGNATURE  SIGNATURE_32('M', 'C', 'H', 'I')
 
 ///
-/// "SPCR" Serial Port Concole Redirection Table
+/// "SPCR" Serial Port Console Redirection Table
 ///
 #define EFI_ACPI_4_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE  SIGNATURE_32('S', 'P', 'C', 'R')
 
diff --git a/MdePkg/Include/IndustryStandard/Acpi50.h b/MdePkg/Include/IndustryStandard/Acpi50.h
index a371c9ade1b1..a9f0912e2d6a 100644
--- a/MdePkg/Include/IndustryStandard/Acpi50.h
+++ b/MdePkg/Include/IndustryStandard/Acpi50.h
@@ -1,15 +1,10 @@
-/** @file   
+/** @file
   ACPI 5.0 definitions from the ACPI Specification Revision 5.0a November 13, 2013.
 
   Copyright (c) 2014 Hewlett-Packard Development Company, L.P.<BR>
-  Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2020, ARM Ltd. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
 #ifndef _ACPI_5_0_H_
@@ -18,7 +13,7 @@
 #include <IndustryStandard/Acpi40.h>
 
 //
-// Define for Desriptor
+// Define for Descriptor
 //
 #define ACPI_SMALL_FIXED_DMA_DESCRIPTOR_NAME                         0x0A
 #define ACPI_LARGE_GPIO_CONNECTION_DESCRIPTOR_NAME                   0x0C
@@ -208,7 +203,7 @@ typedef struct {
 
 //
 // Root System Description Table
-// No definition needed as it is a common description table header, the same with 
+// No definition needed as it is a common description table header, the same with
 // EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
 //
 
@@ -219,7 +214,7 @@ typedef struct {
 
 //
 // Extended System Description Table
-// No definition needed as it is a common description table header, the same with 
+// No definition needed as it is a common description table header, the same with
 // EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
 //
 
@@ -1207,7 +1202,7 @@ typedef struct {
   ///
   UINT64                                          ExitBootServicesEntry;
   ///
-  /// Timer value logged at the point just prior towhen the OS loader gaining
+  /// Timer value logged at the point just prior to when the OS loader gaining
   /// control back from calls the ExitBootServices function for UEFI compatible firmware.
   /// For non-UEFI compatible boots, this field must be zero.
   ///
@@ -1876,7 +1871,7 @@ typedef struct {
 ///
 /// "RSD PTR " Root System Description Pointer
 ///
-#define EFI_ACPI_5_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE  SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ') 
+#define EFI_ACPI_5_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE  SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
 
 ///
 /// "APIC" Multiple APIC Description Table
@@ -2064,12 +2059,17 @@ typedef struct {
 #define EFI_ACPI_5_0_DATA_MANAGEMENT_TABLE_SIGNATURE  SIGNATURE_32('M', 'S', 'D', 'M')
 
 ///
+/// "PCCT" Platform Communications Channel Table
+///
+#define EFI_ACPI_5_0_PLATFORM_COMMUNICATIONS_CHANNEL_TABLE_SIGNATURE  SIGNATURE_32('P', 'C', 'C', 'T')
+
+///
 /// "SLIC" MS Software Licensing Table Specification
 ///
 #define EFI_ACPI_5_0_SOFTWARE_LICENSING_TABLE_SIGNATURE  SIGNATURE_32('S', 'L', 'I', 'C')
 
 ///
-/// "SPCR" Serial Port Concole Redirection Table
+/// "SPCR" Serial Port Console Redirection Table
 ///
 #define EFI_ACPI_5_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE  SIGNATURE_32('S', 'P', 'C', 'R')
 
diff --git a/MdePkg/Include/IndustryStandard/Acpi51.h b/MdePkg/Include/IndustryStandard/Acpi51.h
index 457706befd82..2c027859b9a3 100644
--- a/MdePkg/Include/IndustryStandard/Acpi51.h
+++ b/MdePkg/Include/IndustryStandard/Acpi51.h
@@ -1,16 +1,11 @@
-/** @file   
+/** @file
   ACPI 5.1 definitions from the ACPI Specification Revision 5.1 Errata B January, 2016.
 
   Copyright (c) 2014 Hewlett-Packard Development Company, L.P.<BR>
-  Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
   (C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2020, ARM Ltd. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
 #ifndef _ACPI_5_1_H_
@@ -89,7 +84,7 @@ typedef struct {
 
 //
 // Root System Description Table
-// No definition needed as it is a common description table header, the same with 
+// No definition needed as it is a common description table header, the same with
 // EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
 //
 
@@ -100,7 +95,7 @@ typedef struct {
 
 //
 // Extended System Description Table
-// No definition needed as it is a common description table header, the same with 
+// No definition needed as it is a common description table header, the same with
 // EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
 //
 
@@ -1160,7 +1155,7 @@ typedef struct {
   ///
   UINT64                                          ExitBootServicesEntry;
   ///
-  /// Timer value logged at the point just prior towhen the OS loader gaining
+  /// Timer value logged at the point just prior to when the OS loader gaining
   /// control back from calls the ExitBootServices function for UEFI compatible firmware.
   /// For non-UEFI compatible boots, this field must be zero.
   ///
@@ -1874,7 +1869,7 @@ typedef struct {
   UINT8                                    CommandComplete:1;
   UINT8                                    SciDoorbell:1;
   UINT8                                    Error:1;
-  UINT8                                    PlatformNotification:1;  
+  UINT8                                    PlatformNotification:1;
   UINT8                                    Reserved:4;
   UINT8                                    Reserved1;
 } EFI_ACPI_5_1_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;
@@ -1892,7 +1887,7 @@ typedef struct {
 ///
 /// "RSD PTR " Root System Description Pointer
 ///
-#define EFI_ACPI_5_1_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE  SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ') 
+#define EFI_ACPI_5_1_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE  SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
 
 ///
 /// "APIC" Multiple APIC Description Table
@@ -2085,12 +2080,17 @@ typedef struct {
 #define EFI_ACPI_5_1_DATA_MANAGEMENT_TABLE_SIGNATURE  SIGNATURE_32('M', 'S', 'D', 'M')
 
 ///
+/// "PCCT" Platform Communications Channel Table
+///
+#define EFI_ACPI_5_1_PLATFORM_COMMUNICATIONS_CHANNEL_TABLE_SIGNATURE  SIGNATURE_32('P', 'C', 'C', 'T')
+
+///
 /// "SLIC" MS Software Licensing Table Specification
 ///
 #define EFI_ACPI_5_1_SOFTWARE_LICENSING_TABLE_SIGNATURE  SIGNATURE_32('S', 'L', 'I', 'C')
 
 ///
-/// "SPCR" Serial Port Concole Redirection Table
+/// "SPCR" Serial Port Console Redirection Table
 ///
 #define EFI_ACPI_5_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE  SIGNATURE_32('S', 'P', 'C', 'R')
 
diff --git a/MdePkg/Include/IndustryStandard/Acpi60.h b/MdePkg/Include/IndustryStandard/Acpi60.h
index 478697cceb48..35417fb39b11 100644
--- a/MdePkg/Include/IndustryStandard/Acpi60.h
+++ b/MdePkg/Include/IndustryStandard/Acpi60.h
@@ -1,15 +1,10 @@
-/** @file   
+/** @file
   ACPI 6.0 definitions from the ACPI Specification Revision 6.0 Errata A January, 2016.
 
-  Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
   (C) Copyright 2015-2016 Hewlett Packard Enterprise Development LP<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2020, ARM Ltd. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
 #ifndef _ACPI_6_0_H_
@@ -88,7 +83,7 @@ typedef struct {
 
 //
 // Root System Description Table
-// No definition needed as it is a common description table header, the same with 
+// No definition needed as it is a common description table header, the same with
 // EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
 //
 
@@ -99,7 +94,7 @@ typedef struct {
 
 //
 // Extended System Description Table
-// No definition needed as it is a common description table header, the same with 
+// No definition needed as it is a common description table header, the same with
 // EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
 //
 
@@ -1175,7 +1170,7 @@ typedef struct {
   ///
   UINT64                                          ExitBootServicesEntry;
   ///
-  /// Timer value logged at the point just prior towhen the OS loader gaining
+  /// Timer value logged at the point just prior to when the OS loader gaining
   /// control back from calls the ExitBootServices function for UEFI compatible firmware.
   /// For non-UEFI compatible boots, this field must be zero.
   ///
@@ -2020,7 +2015,9 @@ typedef struct {
 //
 // PCCT Subspace type
 //
-#define EFI_ACPI_6_0_PCCT_SUBSPACE_TYPE_GENERIC  0x00
+#define EFI_ACPI_6_0_PCCT_SUBSPACE_TYPE_GENERIC                         0x00
+#define EFI_ACPI_6_0_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS     0x01
+#define EFI_ACPI_6_0_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS     0x02
 
 ///
 /// PCC Subspace Structure Header
@@ -2061,7 +2058,7 @@ typedef struct {
   UINT8                                    CommandComplete:1;
   UINT8                                    SciDoorbell:1;
   UINT8                                    Error:1;
-  UINT8                                    PlatformNotification:1;  
+  UINT8                                    PlatformNotification:1;
   UINT8                                    Reserved:4;
   UINT8                                    Reserved1;
 } EFI_ACPI_6_0_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;
@@ -2072,6 +2069,50 @@ typedef struct {
   EFI_ACPI_6_0_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS     Status;
 } EFI_ACPI_6_0_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER;
 
+#define EFI_ACPI_6_0_PCCT_SUBSPACE_DOORBELL_INTERRUPT_FLAGS_POLARITY    BIT0
+#define EFI_ACPI_6_0_PCCT_SUBSPACE_DOORBELL_INTERRUPT_FLAGS_MODE        BIT1
+
+///
+/// Type 1 HW-Reduced Communications Subspace Structure
+///
+typedef struct {
+  UINT8                                    Type;
+  UINT8                                    Length;
+  UINT32                                   DoorbellInterrupt;
+  UINT8                                    DoorbellInterruptFlags;
+  UINT8                                    Reserved;
+  UINT64                                   BaseAddress;
+  UINT64                                   AddressLength;
+  EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE   DoorbellRegister;
+  UINT64                                   DoorbellPreserve;
+  UINT64                                   DoorbellWrite;
+  UINT32                                   NominalLatency;
+  UINT32                                   MaximumPeriodicAccessRate;
+  UINT16                                   MinimumRequestTurnaroundTime;
+} EFI_ACPI_6_0_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS;
+
+///
+/// Type 2 HW-Reduced Communications Subspace Structure
+///
+typedef struct {
+  UINT8                                    Type;
+  UINT8                                    Length;
+  UINT32                                   DoorbellInterrupt;
+  UINT8                                    DoorbellInterruptFlags;
+  UINT8                                    Reserved;
+  UINT64                                   BaseAddress;
+  UINT64                                   AddressLength;
+  EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE   DoorbellRegister;
+  UINT64                                   DoorbellPreserve;
+  UINT64                                   DoorbellWrite;
+  UINT32                                   NominalLatency;
+  UINT32                                   MaximumPeriodicAccessRate;
+  UINT16                                   MinimumRequestTurnaroundTime;
+  EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE   DoorbellAckRegister;
+  UINT64                                   DoorbellAckPreserve;
+  UINT64                                   DoorbellAckWrite;
+} EFI_ACPI_6_0_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS;
+
 //
 // Known table signatures
 //
@@ -2079,7 +2120,7 @@ typedef struct {
 ///
 /// "RSD PTR " Root System Description Pointer
 ///
-#define EFI_ACPI_6_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE  SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ') 
+#define EFI_ACPI_6_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE  SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
 
 ///
 /// "APIC" Multiple APIC Description Table
@@ -2282,12 +2323,17 @@ typedef struct {
 #define EFI_ACPI_6_0_DATA_MANAGEMENT_TABLE_SIGNATURE  SIGNATURE_32('M', 'S', 'D', 'M')
 
 ///
+/// "PCCT" Platform Communications Channel Table
+///
+#define EFI_ACPI_6_0_PLATFORM_COMMUNICATIONS_CHANNEL_TABLE_SIGNATURE  SIGNATURE_32('P', 'C', 'C', 'T')
+
+///
 /// "SLIC" MS Software Licensing Table Specification
 ///
 #define EFI_ACPI_6_0_SOFTWARE_LICENSING_TABLE_SIGNATURE  SIGNATURE_32('S', 'L', 'I', 'C')
 
 ///
-/// "SPCR" Serial Port Concole Redirection Table
+/// "SPCR" Serial Port Console Redirection Table
 ///
 #define EFI_ACPI_6_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE  SIGNATURE_32('S', 'P', 'C', 'R')
 
diff --git a/MdePkg/Include/IndustryStandard/Acpi61.h b/MdePkg/Include/IndustryStandard/Acpi61.h
index 954e61d2a19f..35351db8b072 100644
--- a/MdePkg/Include/IndustryStandard/Acpi61.h
+++ b/MdePkg/Include/IndustryStandard/Acpi61.h
@@ -1,15 +1,10 @@
-/** @file   
+/** @file
   ACPI 6.1 definitions from the ACPI Specification Revision 6.1 January, 2016.
 
-  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
  (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2020, ARM Ltd. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
 #ifndef _ACPI_6_1_H_
@@ -88,7 +83,7 @@ typedef struct {
 
 //
 // Root System Description Table
-// No definition needed as it is a common description table header, the same with 
+// No definition needed as it is a common description table header, the same with
 // EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
 //
 
@@ -99,7 +94,7 @@ typedef struct {
 
 //
 // Extended System Description Table
-// No definition needed as it is a common description table header, the same with 
+// No definition needed as it is a common description table header, the same with
 // EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
 //
 
@@ -1175,7 +1170,7 @@ typedef struct {
   ///
   UINT64                                          ExitBootServicesEntry;
   ///
-  /// Timer value logged at the point just prior towhen the OS loader gaining
+  /// Timer value logged at the point just prior to when the OS loader gaining
   /// control back from calls the ExitBootServices function for UEFI compatible firmware.
   /// For non-UEFI compatible boots, this field must be zero.
   ///
@@ -1400,7 +1395,7 @@ typedef struct {
 #define EFI_ACPI_6_1_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE   { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}
 #define EFI_ACPI_6_1_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE     { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}
 #define EFI_ACPI_6_1_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}
-#define EFI_ACPI_6_1_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT   { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D ]}
+#define EFI_ACPI_6_1_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT   { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}
 typedef struct {
   UINT16                                      Type;
   UINT16                                      Length;
@@ -2052,7 +2047,9 @@ typedef struct {
 //
 // PCCT Subspace type
 //
-#define EFI_ACPI_6_1_PCCT_SUBSPACE_TYPE_GENERIC  0x00
+#define EFI_ACPI_6_1_PCCT_SUBSPACE_TYPE_GENERIC                         0x00
+#define EFI_ACPI_6_1_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS     0x01
+#define EFI_ACPI_6_1_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS     0x02
 
 ///
 /// PCC Subspace Structure Header
@@ -2093,7 +2090,7 @@ typedef struct {
   UINT8                                    CommandComplete:1;
   UINT8                                    SciDoorbell:1;
   UINT8                                    Error:1;
-  UINT8                                    PlatformNotification:1;  
+  UINT8                                    PlatformNotification:1;
   UINT8                                    Reserved:4;
   UINT8                                    Reserved1;
 } EFI_ACPI_6_1_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;
@@ -2104,6 +2101,50 @@ typedef struct {
   EFI_ACPI_6_1_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS     Status;
 } EFI_ACPI_6_1_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER;
 
+#define EFI_ACPI_6_1_PCCT_SUBSPACE_DOORBELL_INTERRUPT_FLAGS_POLARITY    BIT0
+#define EFI_ACPI_6_1_PCCT_SUBSPACE_DOORBELL_INTERRUPT_FLAGS_MODE        BIT1
+
+///
+/// Type 1 HW-Reduced Communications Subspace Structure
+///
+typedef struct {
+  UINT8                                    Type;
+  UINT8                                    Length;
+  UINT32                                   DoorbellInterrupt;
+  UINT8                                    DoorbellInterruptFlags;
+  UINT8                                    Reserved;
+  UINT64                                   BaseAddress;
+  UINT64                                   AddressLength;
+  EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE   DoorbellRegister;
+  UINT64                                   DoorbellPreserve;
+  UINT64                                   DoorbellWrite;
+  UINT32                                   NominalLatency;
+  UINT32                                   MaximumPeriodicAccessRate;
+  UINT16                                   MinimumRequestTurnaroundTime;
+} EFI_ACPI_6_1_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS;
+
+///
+/// Type 2 HW-Reduced Communications Subspace Structure
+///
+typedef struct {
+  UINT8                                    Type;
+  UINT8                                    Length;
+  UINT32                                   DoorbellInterrupt;
+  UINT8                                    DoorbellInterruptFlags;
+  UINT8                                    Reserved;
+  UINT64                                   BaseAddress;
+  UINT64                                   AddressLength;
+  EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE   DoorbellRegister;
+  UINT64                                   DoorbellPreserve;
+  UINT64                                   DoorbellWrite;
+  UINT32                                   NominalLatency;
+  UINT32                                   MaximumPeriodicAccessRate;
+  UINT16                                   MinimumRequestTurnaroundTime;
+  EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE   DoorbellAckRegister;
+  UINT64                                   DoorbellAckPreserve;
+  UINT64                                   DoorbellAckWrite;
+} EFI_ACPI_6_1_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS;
+
 //
 // Known table signatures
 //
@@ -2111,7 +2152,7 @@ typedef struct {
 ///
 /// "RSD PTR " Root System Description Pointer
 ///
-#define EFI_ACPI_6_1_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE  SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ') 
+#define EFI_ACPI_6_1_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE  SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
 
 ///
 /// "APIC" Multiple APIC Description Table
@@ -2314,12 +2355,17 @@ typedef struct {
 #define EFI_ACPI_6_1_DATA_MANAGEMENT_TABLE_SIGNATURE  SIGNATURE_32('M', 'S', 'D', 'M')
 
 ///
+/// "PCCT" Platform Communications Channel Table
+///
+#define EFI_ACPI_6_1_PLATFORM_COMMUNICATIONS_CHANNEL_TABLE_SIGNATURE  SIGNATURE_32('P', 'C', 'C', 'T')
+
+///
 /// "SLIC" MS Software Licensing Table Specification
 ///
 #define EFI_ACPI_6_1_SOFTWARE_LICENSING_TABLE_SIGNATURE  SIGNATURE_32('S', 'L', 'I', 'C')
 
 ///
-/// "SPCR" Serial Port Concole Redirection Table
+/// "SPCR" Serial Port Console Redirection Table
 ///
 #define EFI_ACPI_6_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE  SIGNATURE_32('S', 'P', 'C', 'R')
 
diff --git a/MdePkg/Include/IndustryStandard/Acpi62.h b/MdePkg/Include/IndustryStandard/Acpi62.h
new file mode 100644
index 000000000000..7d71ac142f90
--- /dev/null
+++ b/MdePkg/Include/IndustryStandard/Acpi62.h
@@ -0,0 +1,2960 @@
+/** @file
+  ACPI 6.2 definitions from the ACPI Specification Revision 6.2 May, 2017.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2020, ARM Ltd. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _ACPI_6_2_H_
+#define _ACPI_6_2_H_
+
+#include <IndustryStandard/Acpi61.h>
+
+//
+// Large Item Descriptor Name
+//
+#define ACPI_LARGE_PIN_FUNCTION_DESCRIPTOR_NAME              0x0D
+#define ACPI_LARGE_PIN_CONFIGURATION_DESCRIPTOR_NAME         0x0F
+#define ACPI_LARGE_PIN_GROUP_DESCRIPTOR_NAME                 0x10
+#define ACPI_LARGE_PIN_GROUP_FUNCTION_DESCRIPTOR_NAME        0x11
+#define ACPI_LARGE_PIN_GROUP_CONFIGURATION_DESCRIPTOR_NAME   0x12
+
+//
+// Large Item Descriptor Value
+//
+#define ACPI_PIN_FUNCTION_DESCRIPTOR                         0x8D
+#define ACPI_PIN_CONFIGURATION_DESCRIPTOR                    0x8F
+#define ACPI_PIN_GROUP_DESCRIPTOR                            0x90
+#define ACPI_PIN_GROUP_FUNCTION_DESCRIPTOR                   0x91
+#define ACPI_PIN_GROUP_CONFIGURATION_DESCRIPTOR              0x92
+
+#pragma pack(1)
+
+///
+/// Pin Function Descriptor
+///
+typedef PACKED struct {
+  ACPI_LARGE_RESOURCE_HEADER    Header;
+  UINT8                         RevisionId;
+  UINT16                        Flags;
+  UINT8                         PinPullConfiguration;
+  UINT16                        FunctionNumber;
+  UINT16                        PinTableOffset;
+  UINT8                         ResourceSourceIndex;
+  UINT16                        ResourceSourceNameOffset;
+  UINT16                        VendorDataOffset;
+  UINT16                        VendorDataLength;
+} EFI_ACPI_PIN_FUNCTION_DESCRIPTOR;
+
+///
+/// Pin Configuration Descriptor
+///
+typedef PACKED struct {
+  ACPI_LARGE_RESOURCE_HEADER    Header;
+  UINT8                         RevisionId;
+  UINT16                        Flags;
+  UINT8                         PinConfigurationType;
+  UINT32                        PinConfigurationValue;
+  UINT16                        PinTableOffset;
+  UINT8                         ResourceSourceIndex;
+  UINT16                        ResourceSourceNameOffset;
+  UINT16                        VendorDataOffset;
+  UINT16                        VendorDataLength;
+} EFI_ACPI_PIN_CONFIGURATION_DESCRIPTOR;
+
+///
+/// Pin Group Descriptor
+///
+typedef PACKED struct {
+  ACPI_LARGE_RESOURCE_HEADER    Header;
+  UINT8                         RevisionId;
+  UINT16                        Flags;
+  UINT16                        PinTableOffset;
+  UINT16                        ResourceLabelOffset;
+  UINT16                        VendorDataOffset;
+  UINT16                        VendorDataLength;
+} EFI_ACPI_PIN_GROUP_DESCRIPTOR;
+
+///
+/// Pin Group Function Descriptor
+///
+typedef PACKED struct {
+  ACPI_LARGE_RESOURCE_HEADER    Header;
+  UINT8                         RevisionId;
+  UINT16                        Flags;
+  UINT16                        FunctionNumber;
+  UINT8                         ResourceSourceIndex;
+  UINT16                        ResourceSourceNameOffset;
+  UINT16                        ResourceSourceLabelOffset;
+  UINT16                        VendorDataOffset;
+  UINT16                        VendorDataLength;
+} EFI_ACPI_PIN_GROUP_FUNCTION_DESCRIPTOR;
+
+///
+/// Pin Group Configuration Descriptor
+///
+typedef PACKED struct {
+  ACPI_LARGE_RESOURCE_HEADER    Header;
+  UINT8                         RevisionId;
+  UINT16                        Flags;
+  UINT8                         PinConfigurationType;
+  UINT32                        PinConfigurationValue;
+  UINT8                         ResourceSourceIndex;
+  UINT16                        ResourceSourceNameOffset;
+  UINT16                        ResourceSourceLabelOffset;
+  UINT16                        VendorDataOffset;
+  UINT16                        VendorDataLength;
+} EFI_ACPI_PIN_GROUP_CONFIGURATION_DESCRIPTOR;
+
+#pragma pack()
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+///
+/// ACPI 6.2 Generic Address Space definition
+///
+typedef struct {
+  UINT8   AddressSpaceId;
+  UINT8   RegisterBitWidth;
+  UINT8   RegisterBitOffset;
+  UINT8   AccessSize;
+  UINT64  Address;
+} EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE;
+
+//
+// Generic Address Space Address IDs
+//
+#define EFI_ACPI_6_2_SYSTEM_MEMORY              0
+#define EFI_ACPI_6_2_SYSTEM_IO                  1
+#define EFI_ACPI_6_2_PCI_CONFIGURATION_SPACE    2
+#define EFI_ACPI_6_2_EMBEDDED_CONTROLLER        3
+#define EFI_ACPI_6_2_SMBUS                      4
+#define EFI_ACPI_6_2_PLATFORM_COMMUNICATION_CHANNEL  0x0A
+#define EFI_ACPI_6_2_FUNCTIONAL_FIXED_HARDWARE       0x7F
+
+//
+// Generic Address Space Access Sizes
+//
+#define EFI_ACPI_6_2_UNDEFINED  0
+#define EFI_ACPI_6_2_BYTE       1
+#define EFI_ACPI_6_2_WORD       2
+#define EFI_ACPI_6_2_DWORD      3
+#define EFI_ACPI_6_2_QWORD      4
+
+//
+// ACPI 6.2 table structures
+//
+
+///
+/// Root System Description Pointer Structure
+///
+typedef struct {
+  UINT64  Signature;
+  UINT8   Checksum;
+  UINT8   OemId[6];
+  UINT8   Revision;
+  UINT32  RsdtAddress;
+  UINT32  Length;
+  UINT64  XsdtAddress;
+  UINT8   ExtendedChecksum;
+  UINT8   Reserved[3];
+} EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_POINTER;
+
+///
+/// RSD_PTR Revision (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02  ///< ACPISpec (Revision 6.2) says current value is 2
+
+///
+/// Common table header, this prefaces all ACPI tables, including FACS, but
+/// excluding the RSD PTR structure
+///
+typedef struct {
+  UINT32  Signature;
+  UINT32  Length;
+} EFI_ACPI_6_2_COMMON_HEADER;
+
+//
+// Root System Description Table
+// No definition needed as it is a common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
+//
+
+///
+/// RSDT Revision (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Extended System Description Table
+// No definition needed as it is a common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
+//
+
+///
+/// XSDT Revision (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Fixed ACPI Description Table Structure (FADT)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER             Header;
+  UINT32                                  FirmwareCtrl;
+  UINT32                                  Dsdt;
+  UINT8                                   Reserved0;
+  UINT8                                   PreferredPmProfile;
+  UINT16                                  SciInt;
+  UINT32                                  SmiCmd;
+  UINT8                                   AcpiEnable;
+  UINT8                                   AcpiDisable;
+  UINT8                                   S4BiosReq;
+  UINT8                                   PstateCnt;
+  UINT32                                  Pm1aEvtBlk;
+  UINT32                                  Pm1bEvtBlk;
+  UINT32                                  Pm1aCntBlk;
+  UINT32                                  Pm1bCntBlk;
+  UINT32                                  Pm2CntBlk;
+  UINT32                                  PmTmrBlk;
+  UINT32                                  Gpe0Blk;
+  UINT32                                  Gpe1Blk;
+  UINT8                                   Pm1EvtLen;
+  UINT8                                   Pm1CntLen;
+  UINT8                                   Pm2CntLen;
+  UINT8                                   PmTmrLen;
+  UINT8                                   Gpe0BlkLen;
+  UINT8                                   Gpe1BlkLen;
+  UINT8                                   Gpe1Base;
+  UINT8                                   CstCnt;
+  UINT16                                  PLvl2Lat;
+  UINT16                                  PLvl3Lat;
+  UINT16                                  FlushSize;
+  UINT16                                  FlushStride;
+  UINT8                                   DutyOffset;
+  UINT8                                   DutyWidth;
+  UINT8                                   DayAlrm;
+  UINT8                                   MonAlrm;
+  UINT8                                   Century;
+  UINT16                                  IaPcBootArch;
+  UINT8                                   Reserved1;
+  UINT32                                  Flags;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  ResetReg;
+  UINT8                                   ResetValue;
+  UINT16                                  ArmBootArch;
+  UINT8                                   MinorVersion;
+  UINT64                                  XFirmwareCtrl;
+  UINT64                                  XDsdt;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  XPm1aEvtBlk;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  XPm1bEvtBlk;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  XPm1aCntBlk;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  XPm1bCntBlk;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  XPm2CntBlk;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  XPmTmrBlk;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  XGpe0Blk;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  XGpe1Blk;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  SleepControlReg;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  SleepStatusReg;
+  UINT64                                  HypervisorVendorIdentity;
+} EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE;
+
+///
+/// FADT Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_REVISION  0x06
+#define EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION  0x02
+
+//
+// Fixed ACPI Description Table Preferred Power Management Profile
+//
+#define EFI_ACPI_6_2_PM_PROFILE_UNSPECIFIED         0
+#define EFI_ACPI_6_2_PM_PROFILE_DESKTOP             1
+#define EFI_ACPI_6_2_PM_PROFILE_MOBILE              2
+#define EFI_ACPI_6_2_PM_PROFILE_WORKSTATION         3
+#define EFI_ACPI_6_2_PM_PROFILE_ENTERPRISE_SERVER   4
+#define EFI_ACPI_6_2_PM_PROFILE_SOHO_SERVER         5
+#define EFI_ACPI_6_2_PM_PROFILE_APPLIANCE_PC        6
+#define EFI_ACPI_6_2_PM_PROFILE_PERFORMANCE_SERVER  7
+#define EFI_ACPI_6_2_PM_PROFILE_TABLET              8
+
+//
+// Fixed ACPI Description Table Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_2_LEGACY_DEVICES              BIT0
+#define EFI_ACPI_6_2_8042                        BIT1
+#define EFI_ACPI_6_2_VGA_NOT_PRESENT             BIT2
+#define EFI_ACPI_6_2_MSI_NOT_SUPPORTED           BIT3
+#define EFI_ACPI_6_2_PCIE_ASPM_CONTROLS          BIT4
+#define EFI_ACPI_6_2_CMOS_RTC_NOT_PRESENT        BIT5
+
+//
+// Fixed ACPI Description Table Arm Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_2_ARM_PSCI_COMPLIANT              BIT0
+#define EFI_ACPI_6_2_ARM_PSCI_USE_HVC                BIT1
+
+//
+// Fixed ACPI Description Table Fixed Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_2_WBINVD                                 BIT0
+#define EFI_ACPI_6_2_WBINVD_FLUSH                           BIT1
+#define EFI_ACPI_6_2_PROC_C1                                BIT2
+#define EFI_ACPI_6_2_P_LVL2_UP                              BIT3
+#define EFI_ACPI_6_2_PWR_BUTTON                             BIT4
+#define EFI_ACPI_6_2_SLP_BUTTON                             BIT5
+#define EFI_ACPI_6_2_FIX_RTC                                BIT6
+#define EFI_ACPI_6_2_RTC_S4                                 BIT7
+#define EFI_ACPI_6_2_TMR_VAL_EXT                            BIT8
+#define EFI_ACPI_6_2_DCK_CAP                                BIT9
+#define EFI_ACPI_6_2_RESET_REG_SUP                          BIT10
+#define EFI_ACPI_6_2_SEALED_CASE                            BIT11
+#define EFI_ACPI_6_2_HEADLESS                               BIT12
+#define EFI_ACPI_6_2_CPU_SW_SLP                             BIT13
+#define EFI_ACPI_6_2_PCI_EXP_WAK                            BIT14
+#define EFI_ACPI_6_2_USE_PLATFORM_CLOCK                     BIT15
+#define EFI_ACPI_6_2_S4_RTC_STS_VALID                       BIT16
+#define EFI_ACPI_6_2_REMOTE_POWER_ON_CAPABLE                BIT17
+#define EFI_ACPI_6_2_FORCE_APIC_CLUSTER_MODEL               BIT18
+#define EFI_ACPI_6_2_FORCE_APIC_PHYSICAL_DESTINATION_MODE   BIT19
+#define EFI_ACPI_6_2_HW_REDUCED_ACPI                        BIT20
+#define EFI_ACPI_6_2_LOW_POWER_S0_IDLE_CAPABLE              BIT21
+
+///
+/// Firmware ACPI Control Structure
+///
+typedef struct {
+  UINT32  Signature;
+  UINT32  Length;
+  UINT32  HardwareSignature;
+  UINT32  FirmwareWakingVector;
+  UINT32  GlobalLock;
+  UINT32  Flags;
+  UINT64  XFirmwareWakingVector;
+  UINT8   Version;
+  UINT8   Reserved0[3];
+  UINT32  OspmFlags;
+  UINT8   Reserved1[24];
+} EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE;
+
+///
+/// FACS Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION  0x02
+
+///
+/// Firmware Control Structure Feature Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_2_S4BIOS_F                     BIT0
+#define EFI_ACPI_6_2_64BIT_WAKE_SUPPORTED_F       BIT1
+
+///
+/// OSPM Enabled Firmware Control Structure Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_2_OSPM_64BIT_WAKE_F            BIT0
+
+//
+// Differentiated System Description Table,
+// Secondary System Description Table
+// and Persistent System Description Table,
+// no definition needed as they are common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.
+//
+#define EFI_ACPI_6_2_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION   0x02
+#define EFI_ACPI_6_2_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION        0x02
+
+///
+/// Multiple APIC Description Table header definition.  The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      LocalApicAddress;
+  UINT32                      Flags;
+} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
+
+///
+/// MADT Revision (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x04
+
+///
+/// Multiple APIC Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_2_PCAT_COMPAT         BIT0
+
+//
+// Multiple APIC Description Table APIC structure types
+// All other values between 0x0D and 0x7F are reserved and
+// will be ignored by OSPM. 0x80 ~ 0xFF are reserved for OEM.
+//
+#define EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC           0x00
+#define EFI_ACPI_6_2_IO_APIC                        0x01
+#define EFI_ACPI_6_2_INTERRUPT_SOURCE_OVERRIDE      0x02
+#define EFI_ACPI_6_2_NON_MASKABLE_INTERRUPT_SOURCE  0x03
+#define EFI_ACPI_6_2_LOCAL_APIC_NMI                 0x04
+#define EFI_ACPI_6_2_LOCAL_APIC_ADDRESS_OVERRIDE    0x05
+#define EFI_ACPI_6_2_IO_SAPIC                       0x06
+#define EFI_ACPI_6_2_LOCAL_SAPIC                    0x07
+#define EFI_ACPI_6_2_PLATFORM_INTERRUPT_SOURCES     0x08
+#define EFI_ACPI_6_2_PROCESSOR_LOCAL_X2APIC         0x09
+#define EFI_ACPI_6_2_LOCAL_X2APIC_NMI               0x0A
+#define EFI_ACPI_6_2_GIC                            0x0B
+#define EFI_ACPI_6_2_GICD                           0x0C
+#define EFI_ACPI_6_2_GIC_MSI_FRAME                  0x0D
+#define EFI_ACPI_6_2_GICR                           0x0E
+#define EFI_ACPI_6_2_GIC_ITS                        0x0F
+
+//
+// APIC Structure Definitions
+//
+
+///
+/// Processor Local APIC Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   AcpiProcessorUid;
+  UINT8   ApicId;
+  UINT32  Flags;
+} EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC_STRUCTURE;
+
+///
+/// Local APIC Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_2_LOCAL_APIC_ENABLED        BIT0
+
+///
+/// IO APIC Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   IoApicId;
+  UINT8   Reserved;
+  UINT32  IoApicAddress;
+  UINT32  GlobalSystemInterruptBase;
+} EFI_ACPI_6_2_IO_APIC_STRUCTURE;
+
+///
+/// Interrupt Source Override Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   Bus;
+  UINT8   Source;
+  UINT32  GlobalSystemInterrupt;
+  UINT16  Flags;
+} EFI_ACPI_6_2_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT8   InterruptType;
+  UINT8   ProcessorId;
+  UINT8   ProcessorEid;
+  UINT8   IoSapicVector;
+  UINT32  GlobalSystemInterrupt;
+  UINT32  PlatformInterruptSourceFlags;
+  UINT8   CpeiProcessorOverride;
+  UINT8   Reserved[31];
+} EFI_ACPI_6_2_PLATFORM_INTERRUPT_APIC_STRUCTURE;
+
+//
+// MPS INTI flags.
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_2_POLARITY      (3 << 0)
+#define EFI_ACPI_6_2_TRIGGER_MODE  (3 << 2)
+
+///
+/// Non-Maskable Interrupt Source Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT32  GlobalSystemInterrupt;
+} EFI_ACPI_6_2_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
+
+///
+/// Local APIC NMI Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   AcpiProcessorUid;
+  UINT16  Flags;
+  UINT8   LocalApicLint;
+} EFI_ACPI_6_2_LOCAL_APIC_NMI_STRUCTURE;
+
+///
+/// Local APIC Address Override Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved;
+  UINT64  LocalApicAddress;
+} EFI_ACPI_6_2_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
+
+///
+/// IO SAPIC Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   IoApicId;
+  UINT8   Reserved;
+  UINT32  GlobalSystemInterruptBase;
+  UINT64  IoSapicAddress;
+} EFI_ACPI_6_2_IO_SAPIC_STRUCTURE;
+
+///
+/// Local SAPIC Structure
+/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   AcpiProcessorId;
+  UINT8   LocalSapicId;
+  UINT8   LocalSapicEid;
+  UINT8   Reserved[3];
+  UINT32  Flags;
+  UINT32  ACPIProcessorUIDValue;
+} EFI_ACPI_6_2_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT8   InterruptType;
+  UINT8   ProcessorId;
+  UINT8   ProcessorEid;
+  UINT8   IoSapicVector;
+  UINT32  GlobalSystemInterrupt;
+  UINT32  PlatformInterruptSourceFlags;
+} EFI_ACPI_6_2_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
+
+///
+/// Platform Interrupt Source Flags.
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_2_CPEI_PROCESSOR_OVERRIDE          BIT0
+
+///
+/// Processor Local x2APIC Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   Reserved[2];
+  UINT32  X2ApicId;
+  UINT32  Flags;
+  UINT32  AcpiProcessorUid;
+} EFI_ACPI_6_2_PROCESSOR_LOCAL_X2APIC_STRUCTURE;
+
+///
+/// Local x2APIC NMI Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT32  AcpiProcessorUid;
+  UINT8   LocalX2ApicLint;
+  UINT8   Reserved[3];
+} EFI_ACPI_6_2_LOCAL_X2APIC_NMI_STRUCTURE;
+
+///
+/// GIC Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved;
+  UINT32  CPUInterfaceNumber;
+  UINT32  AcpiProcessorUid;
+  UINT32  Flags;
+  UINT32  ParkingProtocolVersion;
+  UINT32  PerformanceInterruptGsiv;
+  UINT64  ParkedAddress;
+  UINT64  PhysicalBaseAddress;
+  UINT64  GICV;
+  UINT64  GICH;
+  UINT32  VGICMaintenanceInterrupt;
+  UINT64  GICRBaseAddress;
+  UINT64  MPIDR;
+  UINT8   ProcessorPowerEfficiencyClass;
+  UINT8   Reserved2[3];
+} EFI_ACPI_6_2_GIC_STRUCTURE;
+
+///
+/// GIC Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_2_GIC_ENABLED                              BIT0
+#define EFI_ACPI_6_2_PERFORMANCE_INTERRUPT_MODEL              BIT1
+#define EFI_ACPI_6_2_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS    BIT2
+
+///
+/// GIC Distributor Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved1;
+  UINT32  GicId;
+  UINT64  PhysicalBaseAddress;
+  UINT32  SystemVectorBase;
+  UINT8   GicVersion;
+  UINT8   Reserved2[3];
+} EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE;
+
+///
+/// GIC Version
+///
+#define EFI_ACPI_6_2_GIC_V1                                   0x01
+#define EFI_ACPI_6_2_GIC_V2                                   0x02
+#define EFI_ACPI_6_2_GIC_V3                                   0x03
+#define EFI_ACPI_6_2_GIC_V4                                   0x04
+
+///
+/// GIC MSI Frame Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved1;
+  UINT32  GicMsiFrameId;
+  UINT64  PhysicalBaseAddress;
+  UINT32  Flags;
+  UINT16  SPICount;
+  UINT16  SPIBase;
+} EFI_ACPI_6_2_GIC_MSI_FRAME_STRUCTURE;
+
+///
+/// GIC MSI Frame Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_2_SPI_COUNT_BASE_SELECT                    BIT0
+
+///
+/// GICR Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved;
+  UINT64  DiscoveryRangeBaseAddress;
+  UINT32  DiscoveryRangeLength;
+} EFI_ACPI_6_2_GICR_STRUCTURE;
+
+///
+/// GIC Interrupt Translation Service Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved;
+  UINT32  GicItsId;
+  UINT64  PhysicalBaseAddress;
+  UINT32  Reserved2;
+} EFI_ACPI_6_2_GIC_ITS_STRUCTURE;
+
+///
+/// Smart Battery Description Table (SBST)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      WarningEnergyLevel;
+  UINT32                      LowEnergyLevel;
+  UINT32                      CriticalEnergyLevel;
+} EFI_ACPI_6_2_SMART_BATTERY_DESCRIPTION_TABLE;
+
+///
+/// SBST Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Embedded Controller Boot Resources Table (ECDT)
+/// The table is followed by a null terminated ASCII string that contains
+/// a fully qualified reference to the name space object.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER             Header;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  EcControl;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  EcData;
+  UINT32                                  Uid;
+  UINT8                                   GpeBit;
+} EFI_ACPI_6_2_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
+
+///
+/// ECDT Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION  0x01
+
+///
+/// System Resource Affinity Table (SRAT).  The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      Reserved1;  ///< Must be set to 1
+  UINT64                      Reserved2;
+} EFI_ACPI_6_2_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;
+
+///
+/// SRAT Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION  0x03
+
+//
+// SRAT structure types.
+// All other values between 0x05 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY  0x00
+#define EFI_ACPI_6_2_MEMORY_AFFINITY                      0x01
+#define EFI_ACPI_6_2_PROCESSOR_LOCAL_X2APIC_AFFINITY      0x02
+#define EFI_ACPI_6_2_GICC_AFFINITY                        0x03
+#define EFI_ACPI_6_2_GIC_ITS_AFFINITY                     0x04
+
+///
+/// Processor Local APIC/SAPIC Affinity Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   ProximityDomain7To0;
+  UINT8   ApicId;
+  UINT32  Flags;
+  UINT8   LocalSapicEid;
+  UINT8   ProximityDomain31To8[3];
+  UINT32  ClockDomain;
+} EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;
+
+///
+/// Local APIC/SAPIC Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
+
+///
+/// Memory Affinity Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT32  ProximityDomain;
+  UINT16  Reserved1;
+  UINT32  AddressBaseLow;
+  UINT32  AddressBaseHigh;
+  UINT32  LengthLow;
+  UINT32  LengthHigh;
+  UINT32  Reserved2;
+  UINT32  Flags;
+  UINT64  Reserved3;
+} EFI_ACPI_6_2_MEMORY_AFFINITY_STRUCTURE;
+
+//
+// Memory Flags.  All other bits are reserved and must be 0.
+//
+#define EFI_ACPI_6_2_MEMORY_ENABLED       (1 << 0)
+#define EFI_ACPI_6_2_MEMORY_HOT_PLUGGABLE (1 << 1)
+#define EFI_ACPI_6_2_MEMORY_NONVOLATILE   (1 << 2)
+
+///
+/// Processor Local x2APIC Affinity Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   Reserved1[2];
+  UINT32  ProximityDomain;
+  UINT32  X2ApicId;
+  UINT32  Flags;
+  UINT32  ClockDomain;
+  UINT8   Reserved2[4];
+} EFI_ACPI_6_2_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;
+
+///
+/// GICC Affinity Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT32  ProximityDomain;
+  UINT32  AcpiProcessorUid;
+  UINT32  Flags;
+  UINT32  ClockDomain;
+} EFI_ACPI_6_2_GICC_AFFINITY_STRUCTURE;
+
+///
+/// GICC Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_2_GICC_ENABLED (1 << 0)
+
+///
+/// GIC Interrupt Translation Service (ITS) Affinity Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT32  ProximityDomain;
+  UINT8   Reserved[2];
+  UINT32  ItsId;
+} EFI_ACPI_6_2_GIC_ITS_AFFINITY_STRUCTURE;
+
+///
+/// System Locality Distance Information Table (SLIT).
+/// The rest of the table is a matrix.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT64                      NumberOfSystemLocalities;
+} EFI_ACPI_6_2_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;
+
+///
+/// SLIT Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION  0x01
+
+///
+/// Corrected Platform Error Polling Table (CPEP)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT8                       Reserved[8];
+} EFI_ACPI_6_2_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;
+
+///
+/// CPEP Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01
+
+//
+// CPEP processor structure types.
+//
+#define EFI_ACPI_6_2_CPEP_PROCESSOR_APIC_SAPIC  0x00
+
+///
+/// Corrected Platform Error Polling Processor Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   ProcessorId;
+  UINT8   ProcessorEid;
+  UINT32  PollingInterval;
+} EFI_ACPI_6_2_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;
+
+///
+/// Maximum System Characteristics Table (MSCT)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      OffsetProxDomInfo;
+  UINT32                      MaximumNumberOfProximityDomains;
+  UINT32                      MaximumNumberOfClockDomains;
+  UINT64                      MaximumPhysicalAddress;
+} EFI_ACPI_6_2_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;
+
+///
+/// MSCT Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01
+
+///
+/// Maximum Proximity Domain Information Structure Definition
+///
+typedef struct {
+  UINT8   Revision;
+  UINT8   Length;
+  UINT32  ProximityDomainRangeLow;
+  UINT32  ProximityDomainRangeHigh;
+  UINT32  MaximumProcessorCapacity;
+  UINT64  MaximumMemoryCapacity;
+} EFI_ACPI_6_2_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;
+
+///
+/// ACPI RAS Feature Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT8                       PlatformCommunicationChannelIdentifier[12];
+} EFI_ACPI_6_2_RAS_FEATURE_TABLE;
+
+///
+/// RASF Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_RAS_FEATURE_TABLE_REVISION 0x01
+
+///
+/// ACPI RASF Platform Communication Channel Shared Memory Region definition.
+///
+typedef struct {
+  UINT32                      Signature;
+  UINT16                      Command;
+  UINT16                      Status;
+  UINT16                      Version;
+  UINT8                       RASCapabilities[16];
+  UINT8                       SetRASCapabilities[16];
+  UINT16                      NumberOfRASFParameterBlocks;
+  UINT32                      SetRASCapabilitiesStatus;
+} EFI_ACPI_6_2_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
+
+///
+/// ACPI RASF PCC command code
+///
+#define EFI_ACPI_6_2_RASF_PCC_COMMAND_CODE_EXECUTE_RASF_COMMAND  0x01
+
+///
+/// ACPI RASF Platform RAS Capabilities
+///
+#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED                         BIT0
+#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED_AND_EXPOSED_TO_SOFTWARE BIT1
+#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS            BIT2
+#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS    BIT3
+#define EFI_ACPI_6_2_RASF_PLATFORM_RAS_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING         BIT4
+
+///
+/// ACPI RASF Parameter Block structure for PATROL_SCRUB
+///
+typedef struct {
+  UINT16                      Type;
+  UINT16                      Version;
+  UINT16                      Length;
+  UINT16                      PatrolScrubCommand;
+  UINT64                      RequestedAddressRange[2];
+  UINT64                      ActualAddressRange[2];
+  UINT16                      Flags;
+  UINT8                       RequestedSpeed;
+} EFI_ACPI_6_2_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE;
+
+///
+/// ACPI RASF Patrol Scrub command
+///
+#define EFI_ACPI_6_2_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS   0x01
+#define EFI_ACPI_6_2_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER   0x02
+#define EFI_ACPI_6_2_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER    0x03
+
+///
+/// Memory Power State Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT8                       PlatformCommunicationChannelIdentifier;
+  UINT8                       Reserved[3];
+// Memory Power Node Structure
+// Memory Power State Characteristics
+} EFI_ACPI_6_2_MEMORY_POWER_STATUS_TABLE;
+
+///
+/// MPST Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_MEMORY_POWER_STATE_TABLE_REVISION 0x01
+
+///
+/// MPST Platform Communication Channel Shared Memory Region definition.
+///
+typedef struct {
+  UINT32                      Signature;
+  UINT16                      Command;
+  UINT16                      Status;
+  UINT32                      MemoryPowerCommandRegister;
+  UINT32                      MemoryPowerStatusRegister;
+  UINT32                      PowerStateId;
+  UINT32                      MemoryPowerNodeId;
+  UINT64                      MemoryEnergyConsumed;
+  UINT64                      ExpectedAveragePowerComsuned;
+} EFI_ACPI_6_2_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
+
+///
+/// ACPI MPST PCC command code
+///
+#define EFI_ACPI_6_2_MPST_PCC_COMMAND_CODE_EXECUTE_MPST_COMMAND  0x03
+
+///
+/// ACPI MPST Memory Power command
+///
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE       0x01
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE       0x02
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED   0x03
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED   0x04
+
+///
+/// MPST Memory Power Node Table
+///
+typedef struct {
+  UINT8                                             PowerStateValue;
+  UINT8                                             PowerStateInformationIndex;
+} EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE;
+
+typedef struct {
+  UINT8                                             Flag;
+  UINT8                                             Reserved;
+  UINT16                                            MemoryPowerNodeId;
+  UINT32                                            Length;
+  UINT64                                            AddressBase;
+  UINT64                                            AddressLength;
+  UINT32                                            NumberOfPowerStates;
+  UINT32                                            NumberOfPhysicalComponents;
+//EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE              MemoryPowerState[NumberOfPowerStates];
+//UINT16                                            PhysicalComponentIdentifier[NumberOfPhysicalComponents];
+} EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE;
+
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE          0x01
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED   0x02
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE   0x04
+
+typedef struct {
+  UINT16                      MemoryPowerNodeCount;
+  UINT8                       Reserved[2];
+} EFI_ACPI_6_2_MPST_MEMORY_POWER_NODE_TABLE;
+
+///
+/// MPST Memory Power State Characteristics Table
+///
+typedef struct {
+  UINT8                                             PowerStateStructureID;
+  UINT8                                             Flag;
+  UINT16                                            Reserved;
+  UINT32                                            AveragePowerConsumedInMPS0;
+  UINT32                                            RelativePowerSavingToMPS0;
+  UINT64                                            ExitLatencyToMPS0;
+} EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE;
+
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED              0x01
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY   0x02
+#define EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT    0x04
+
+typedef struct {
+  UINT16                      MemoryPowerStateCharacteristicsCount;
+  UINT8                       Reserved[2];
+} EFI_ACPI_6_2_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE;
+
+///
+/// Memory Topology Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      Reserved;
+} EFI_ACPI_6_2_MEMORY_TOPOLOGY_TABLE;
+
+///
+/// PMTT Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_MEMORY_TOPOLOGY_TABLE_REVISION 0x01
+
+///
+/// Common Memory Aggregator Device Structure.
+///
+typedef struct {
+  UINT8                       Type;
+  UINT8                       Reserved;
+  UINT16                      Length;
+  UINT16                      Flags;
+  UINT16                      Reserved1;
+} EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// Memory Aggregator Device Type
+///
+#define EFI_ACPI_6_2_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET            0x1
+#define EFI_ACPI_6_2_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x2
+#define EFI_ACPI_6_2_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM              0x3
+
+///
+/// Socket Memory Aggregator Device Structure.
+///
+typedef struct {
+  EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE  Header;
+  UINT16                                                       SocketIdentifier;
+  UINT16                                                       Reserved;
+//EFI_ACPI_6_2_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE  MemoryController[];
+} EFI_ACPI_6_2_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// MemoryController Memory Aggregator Device Structure.
+///
+typedef struct {
+  EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE  Header;
+  UINT32                                                       ReadLatency;
+  UINT32                                                       WriteLatency;
+  UINT32                                                       ReadBandwidth;
+  UINT32                                                       WriteBandwidth;
+  UINT16                                                       OptimalAccessUnit;
+  UINT16                                                       OptimalAccessAlignment;
+  UINT16                                                       Reserved;
+  UINT16                                                       NumberOfProximityDomains;
+//UINT32                                                       ProximityDomain[NumberOfProximityDomains];
+//EFI_ACPI_6_2_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE    PhysicalComponent[];
+} EFI_ACPI_6_2_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// DIMM Memory Aggregator Device Structure.
+///
+typedef struct {
+  EFI_ACPI_6_2_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE  Header;
+  UINT16                                                       PhysicalComponentIdentifier;
+  UINT16                                                       Reserved;
+  UINT32                                                       SizeOfDimm;
+  UINT32                                                       SmbiosHandle;
+} EFI_ACPI_6_2_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// Boot Graphics Resource Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  ///
+  /// 2-bytes (16 bit) version ID. This value must be 1.
+  ///
+  UINT16                      Version;
+  ///
+  /// 1-byte status field indicating current status about the table.
+  ///     Bits[7:1] = Reserved (must be zero)
+  ///     Bit [0] = Valid. A one indicates the boot image graphic is valid.
+  ///
+  UINT8                       Status;
+  ///
+  /// 1-byte enumerated type field indicating format of the image.
+  ///     0 = Bitmap
+  ///     1 - 255  Reserved (for future use)
+  ///
+  UINT8                       ImageType;
+  ///
+  /// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy
+  /// of the image bitmap.
+  ///
+  UINT64                      ImageAddress;
+  ///
+  /// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image.
+  /// (X, Y) display offset of the top left corner of the boot image.
+  /// The top left corner of the display is at offset (0, 0).
+  ///
+  UINT32                      ImageOffsetX;
+  ///
+  /// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image.
+  /// (X, Y) display offset of the top left corner of the boot image.
+  /// The top left corner of the display is at offset (0, 0).
+  ///
+  UINT32                      ImageOffsetY;
+} EFI_ACPI_6_2_BOOT_GRAPHICS_RESOURCE_TABLE;
+
+///
+/// BGRT Revision
+///
+#define EFI_ACPI_6_2_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1
+
+///
+/// BGRT Version
+///
+#define EFI_ACPI_6_2_BGRT_VERSION         0x01
+
+///
+/// BGRT Status
+///
+#define EFI_ACPI_6_2_BGRT_STATUS_NOT_DISPLAYED 0x00
+#define EFI_ACPI_6_2_BGRT_STATUS_DISPLAYED     0x01
+
+///
+/// BGRT Image Type
+///
+#define EFI_ACPI_6_2_BGRT_IMAGE_TYPE_BMP  0x00
+
+///
+/// FPDT Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01
+
+///
+/// FPDT Performance Record Types
+///
+#define EFI_ACPI_6_2_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER      0x0000
+#define EFI_ACPI_6_2_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER     0x0001
+
+///
+/// FPDT Performance Record Revision
+///
+#define EFI_ACPI_6_2_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER  0x01
+#define EFI_ACPI_6_2_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01
+
+///
+/// FPDT Runtime Performance Record Types
+///
+#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME                0x0000
+#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND               0x0001
+#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT      0x0002
+
+///
+/// FPDT Runtime Performance Record Revision
+///
+#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_REVISION_S3_RESUME            0x01
+#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_REVISION_S3_SUSPEND           0x01
+#define EFI_ACPI_6_2_FPDT_RUNTIME_RECORD_REVISION_FIRMWARE_BASIC_BOOT  0x02
+
+///
+/// FPDT Performance Record header
+///
+typedef struct {
+  UINT16           Type;
+  UINT8            Length;
+  UINT8            Revision;
+} EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER;
+
+///
+/// FPDT Performance Table header
+///
+typedef struct {
+  UINT32  Signature;
+  UINT32  Length;
+} EFI_ACPI_6_2_FPDT_PERFORMANCE_TABLE_HEADER;
+
+///
+/// FPDT Firmware Basic Boot Performance Pointer Record Structure
+///
+typedef struct {
+  EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER     Header;
+  UINT32                                          Reserved;
+  ///
+  /// 64-bit processor-relative physical address of the Basic Boot Performance Table.
+  ///
+  UINT64                                          BootPerformanceTablePointer;
+} EFI_ACPI_6_2_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD;
+
+///
+/// FPDT S3 Performance Table Pointer Record Structure
+///
+typedef struct {
+  EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER     Header;
+  UINT32                                          Reserved;
+  ///
+  /// 64-bit processor-relative physical address of the S3 Performance Table.
+  ///
+  UINT64                                          S3PerformanceTablePointer;
+} EFI_ACPI_6_2_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD;
+
+///
+/// FPDT Firmware Basic Boot Performance Record Structure
+///
+typedef struct {
+  EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER     Header;
+  UINT32                                          Reserved;
+  ///
+  /// Timer value logged at the beginning of firmware image execution.
+  /// This may not always be zero or near zero.
+  ///
+  UINT64                                          ResetEnd;
+  ///
+  /// Timer value logged just prior to loading the OS boot loader into memory.
+  /// For non-UEFI compatible boots, this field must be zero.
+  ///
+  UINT64                                          OsLoaderLoadImageStart;
+  ///
+  /// Timer value logged just prior to launching the previously loaded OS boot loader image.
+  /// For non-UEFI compatible boots, the timer value logged will be just prior
+  /// to the INT 19h handler invocation.
+  ///
+  UINT64                                          OsLoaderStartImageStart;
+  ///
+  /// Timer value logged at the point when the OS loader calls the
+  /// ExitBootServices function for UEFI compatible firmware.
+  /// For non-UEFI compatible boots, this field must be zero.
+  ///
+  UINT64                                          ExitBootServicesEntry;
+  ///
+  /// Timer value logged at the point just prior to when the OS loader gaining
+  /// control back from calls the ExitBootServices function for UEFI compatible firmware.
+  /// For non-UEFI compatible boots, this field must be zero.
+  ///
+  UINT64                                          ExitBootServicesExit;
+} EFI_ACPI_6_2_FPDT_FIRMWARE_BASIC_BOOT_RECORD;
+
+///
+/// FPDT Firmware Basic Boot Performance Table signature
+///
+#define EFI_ACPI_6_2_FPDT_BOOT_PERFORMANCE_TABLE_SIGNATURE  SIGNATURE_32('F', 'B', 'P', 'T')
+
+//
+// FPDT Firmware Basic Boot Performance Table
+//
+typedef struct {
+  EFI_ACPI_6_2_FPDT_PERFORMANCE_TABLE_HEADER      Header;
+  //
+  // one or more Performance Records.
+  //
+} EFI_ACPI_6_2_FPDT_FIRMWARE_BASIC_BOOT_TABLE;
+
+///
+/// FPDT "S3PT" S3 Performance Table
+///
+#define EFI_ACPI_6_2_FPDT_S3_PERFORMANCE_TABLE_SIGNATURE  SIGNATURE_32('S', '3', 'P', 'T')
+
+//
+// FPDT Firmware S3 Boot Performance Table
+//
+typedef struct {
+  EFI_ACPI_6_2_FPDT_PERFORMANCE_TABLE_HEADER      Header;
+  //
+  // one or more Performance Records.
+  //
+} EFI_ACPI_6_2_FPDT_FIRMWARE_S3_BOOT_TABLE;
+
+///
+/// FPDT Basic S3 Resume Performance Record
+///
+typedef struct {
+  EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER     Header;
+  ///
+  /// A count of the number of S3 resume cycles since the last full boot sequence.
+  ///
+  UINT32                                          ResumeCount;
+  ///
+  /// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the
+  /// OS waking vector. Only the most recent resume cycle's time is retained.
+  ///
+  UINT64                                          FullResume;
+  ///
+  /// Average timer value of all resume cycles logged since the last full boot
+  /// sequence, including the most recent resume.  Note that the entire log of
+  /// timer values does not need to be retained in order to calculate this average.
+  ///
+  UINT64                                          AverageResume;
+} EFI_ACPI_6_2_FPDT_S3_RESUME_RECORD;
+
+///
+/// FPDT Basic S3 Suspend Performance Record
+///
+typedef struct {
+  EFI_ACPI_6_2_FPDT_PERFORMANCE_RECORD_HEADER     Header;
+  ///
+  /// Timer value recorded at the OS write to SLP_TYP upon entry to S3.
+  /// Only the most recent suspend cycle's timer value is retained.
+  ///
+  UINT64                                          SuspendStart;
+  ///
+  /// Timer value recorded at the final firmware write to SLP_TYP (or other
+  /// mechanism) used to trigger hardware entry to S3.
+  /// Only the most recent suspend cycle's timer value is retained.
+  ///
+  UINT64                                          SuspendEnd;
+} EFI_ACPI_6_2_FPDT_S3_SUSPEND_RECORD;
+
+///
+/// Firmware Performance Record Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+} EFI_ACPI_6_2_FIRMWARE_PERFORMANCE_RECORD_TABLE;
+
+///
+/// Generic Timer Description Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT64                      CntControlBasePhysicalAddress;
+  UINT32                      Reserved;
+  UINT32                      SecurePL1TimerGSIV;
+  UINT32                      SecurePL1TimerFlags;
+  UINT32                      NonSecurePL1TimerGSIV;
+  UINT32                      NonSecurePL1TimerFlags;
+  UINT32                      VirtualTimerGSIV;
+  UINT32                      VirtualTimerFlags;
+  UINT32                      NonSecurePL2TimerGSIV;
+  UINT32                      NonSecurePL2TimerFlags;
+  UINT64                      CntReadBasePhysicalAddress;
+  UINT32                      PlatformTimerCount;
+  UINT32                      PlatformTimerOffset;
+} EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE;
+
+///
+/// GTDT Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x02
+
+///
+/// Timer Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_2_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE          BIT0
+#define EFI_ACPI_6_2_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY      BIT1
+#define EFI_ACPI_6_2_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY          BIT2
+
+///
+/// Platform Timer Type
+///
+#define EFI_ACPI_6_2_GTDT_GT_BLOCK                       0
+#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG          1
+
+///
+/// GT Block Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT16  Length;
+  UINT8   Reserved;
+  UINT64  CntCtlBase;
+  UINT32  GTBlockTimerCount;
+  UINT32  GTBlockTimerOffset;
+} EFI_ACPI_6_2_GTDT_GT_BLOCK_STRUCTURE;
+
+///
+/// GT Block Timer Structure
+///
+typedef struct {
+  UINT8   GTFrameNumber;
+  UINT8   Reserved[3];
+  UINT64  CntBaseX;
+  UINT64  CntEL0BaseX;
+  UINT32  GTxPhysicalTimerGSIV;
+  UINT32  GTxPhysicalTimerFlags;
+  UINT32  GTxVirtualTimerGSIV;
+  UINT32  GTxVirtualTimerFlags;
+  UINT32  GTxCommonFlags;
+} EFI_ACPI_6_2_GTDT_GT_BLOCK_TIMER_STRUCTURE;
+
+///
+/// GT Block Physical Timers and Virtual Timers Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_2_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE          BIT0
+#define EFI_ACPI_6_2_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY      BIT1
+
+///
+/// Common Flags Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_2_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER              BIT0
+#define EFI_ACPI_6_2_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY      BIT1
+
+///
+/// SBSA Generic Watchdog Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT16  Length;
+  UINT8   Reserved;
+  UINT64  RefreshFramePhysicalAddress;
+  UINT64  WatchdogControlFramePhysicalAddress;
+  UINT32  WatchdogTimerGSIV;
+  UINT32  WatchdogTimerFlags;
+} EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE;
+
+///
+/// SBSA Generic Watchdog Timer Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE          BIT0
+#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY      BIT1
+#define EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER                  BIT2
+
+//
+// NVDIMM Firmware Interface Table definition.
+//
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER    Header;
+  UINT32                         Reserved;
+} EFI_ACPI_6_2_NVDIMM_FIRMWARE_INTERFACE_TABLE;
+
+//
+// NFIT Version (as defined in ACPI 6.2 spec.)
+//
+#define EFI_ACPI_6_2_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1
+
+//
+// Definition for NFIT Table Structure Types
+//
+#define EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE              0
+#define EFI_ACPI_6_2_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE_TYPE                      1
+#define EFI_ACPI_6_2_NFIT_INTERLEAVE_STRUCTURE_TYPE                                 2
+#define EFI_ACPI_6_2_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE              3
+#define EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE                      4
+#define EFI_ACPI_6_2_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE            5
+#define EFI_ACPI_6_2_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE                         6
+
+//
+// Definition for NFIT Structure Header
+//
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+} EFI_ACPI_6_2_NFIT_STRUCTURE_HEADER;
+
+//
+// Definition for System Physical Address Range Structure
+//
+#define EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT      BIT0
+#define EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID             BIT1
+#define EFI_ACPI_6_2_NFIT_GUID_VOLATILE_MEMORY_REGION                             { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }}
+#define EFI_ACPI_6_2_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION          { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}
+#define EFI_ACPI_6_2_NFIT_GUID_NVDIMM_CONTROL_REGION                              { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}
+#define EFI_ACPI_6_2_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION                    { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}
+#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE   { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}
+#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE     { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}
+#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}
+#define EFI_ACPI_6_2_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT   { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+  UINT16                                      SPARangeStructureIndex;
+  UINT16                                      Flags;
+  UINT32                                      Reserved_8;
+  UINT32                                      ProximityDomain;
+  GUID                                        AddressRangeTypeGUID;
+  UINT64                                      SystemPhysicalAddressRangeBase;
+  UINT64                                      SystemPhysicalAddressRangeLength;
+  UINT64                                      AddressRangeMemoryMappingAttribute;
+} EFI_ACPI_6_2_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE;
+
+//
+// Definition for Memory Device to System Physical Address Range Mapping Structure
+//
+typedef struct {
+  UINT32                                      DIMMNumber:4;
+  UINT32                                      MemoryChannelNumber:4;
+  UINT32                                      MemoryControllerID:4;
+  UINT32                                      SocketID:4;
+  UINT32                                      NodeControllerID:12;
+  UINT32                                      Reserved_28:4;
+} EFI_ACPI_6_2_NFIT_DEVICE_HANDLE;
+
+#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_PREVIOUS_SAVE_FAIL                                      BIT0
+#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_LAST_RESTORE_FAIL                                       BIT1
+#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_PLATFORM_FLUSH_FAIL                                     BIT2
+#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_NOT_ARMED_PRIOR_TO_OSPM_HAND_OFF                        BIT3
+#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_SMART_HEALTH_EVENTS_PRIOR_OSPM_HAND_OFF                 BIT4
+#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_ENABLED_TO_NOTIFY_OSPM_ON_SMART_HEALTH_EVENTS  BIT5
+#define EFI_ACPI_6_2_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_NOT_MAP_NVDIMM_TO_SPA                          BIT6
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+  EFI_ACPI_6_2_NFIT_DEVICE_HANDLE             NFITDeviceHandle;
+  UINT16                                      NVDIMMPhysicalID;
+  UINT16                                      NVDIMMRegionID;
+  UINT16                                      SPARangeStructureIndex ;
+  UINT16                                      NVDIMMControlRegionStructureIndex;
+  UINT64                                      NVDIMMRegionSize;
+  UINT64                                      RegionOffset;
+  UINT64                                      NVDIMMPhysicalAddressRegionBase;
+  UINT16                                      InterleaveStructureIndex;
+  UINT16                                      InterleaveWays;
+  UINT16                                      NVDIMMStateFlags;
+  UINT16                                      Reserved_46;
+} EFI_ACPI_6_2_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE;
+
+//
+// Definition for Interleave Structure
+//
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+  UINT16                                      InterleaveStructureIndex;
+  UINT16                                      Reserved_6;
+  UINT32                                      NumberOfLines;
+  UINT32                                      LineSize;
+//UINT32                                      LineOffset[NumberOfLines];
+} EFI_ACPI_6_2_NFIT_INTERLEAVE_STRUCTURE;
+
+//
+// Definition for SMBIOS Management Information Structure
+//
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+  UINT32                                      Reserved_4;
+//UINT8                                       Data[];
+} EFI_ACPI_6_2_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE;
+
+//
+// Definition for NVDIMM Control Region Structure
+//
+#define EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_VALID_FIELDS_MANUFACTURING           BIT0
+
+#define EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED    BIT0
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+  UINT16                                      NVDIMMControlRegionStructureIndex;
+  UINT16                                      VendorID;
+  UINT16                                      DeviceID;
+  UINT16                                      RevisionID;
+  UINT16                                      SubsystemVendorID;
+  UINT16                                      SubsystemDeviceID;
+  UINT16                                      SubsystemRevisionID;
+  UINT8                                       ValidFields;
+  UINT8                                       ManufacturingLocation;
+  UINT16                                      ManufacturingDate;
+  UINT8                                       Reserved_22[2];
+  UINT32                                      SerialNumber;
+  UINT16                                      RegionFormatInterfaceCode;
+  UINT16                                      NumberOfBlockControlWindows;
+  UINT64                                      SizeOfBlockControlWindow;
+  UINT64                                      CommandRegisterOffsetInBlockControlWindow;
+  UINT64                                      SizeOfCommandRegisterInBlockControlWindows;
+  UINT64                                      StatusRegisterOffsetInBlockControlWindow;
+  UINT64                                      SizeOfStatusRegisterInBlockControlWindows;
+  UINT16                                      NVDIMMControlRegionFlag;
+  UINT8                                       Reserved_74[6];
+} EFI_ACPI_6_2_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE;
+
+//
+// Definition for NVDIMM Block Data Window Region Structure
+//
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+  UINT16                                      NVDIMMControlRegionStructureIndex;
+  UINT16                                      NumberOfBlockDataWindows;
+  UINT64                                      BlockDataWindowStartOffset;
+  UINT64                                      SizeOfBlockDataWindow;
+  UINT64                                      BlockAccessibleMemoryCapacity;
+  UINT64                                      BeginningAddressOfFirstBlockInBlockAccessibleMemory;
+} EFI_ACPI_6_2_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE;
+
+//
+// Definition for Flush Hint Address Structure
+//
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+  EFI_ACPI_6_2_NFIT_DEVICE_HANDLE             NFITDeviceHandle;
+  UINT16                                      NumberOfFlushHintAddresses;
+  UINT8                                       Reserved_10[6];
+//UINT64                                      FlushHintAddress[NumberOfFlushHintAddresses];
+} EFI_ACPI_6_2_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE;
+
+///
+/// Secure DEVices Table (SDEV)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER   Header;
+} EFI_ACPI_6_2_SECURE_DEVICES_TABLE_HEADER;
+
+///
+/// SDEV Revision (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_SECURE_DEVICES_TABLE_REVISION      0x01
+
+///
+/// Secure Device types
+///
+#define EFI_ACPI_6_2_SDEV_TYPE_PCIE_ENDPOINT_DEVICE     0x01
+#define EFI_ACPI_6_2_SDEV_TYPE_ACPI_NAMESPACE_DEVICE    0x00
+
+///
+/// Secure Device flags
+///
+#define EFI_ACPI_6_2_SDEV_FLAG_ALLOW_HANDOFF            BIT0
+
+///
+/// SDEV Structure Header
+///
+typedef struct {
+  UINT8                         Type;
+  UINT8                         Flags;
+  UINT16                        Length;
+} EFI_ACPI_6_2_SDEV_STRUCTURE_HEADER;
+
+///
+/// PCIe Endpoint Device based Secure Device Structure
+///
+typedef struct {
+  UINT8                         Type;
+  UINT8                         Flags;
+  UINT16                        Length;
+  UINT16                        PciSegmentNumber;
+  UINT16                        StartBusNumber;
+  UINT16                        PciPathOffset;
+  UINT16                        PciPathLength;
+  UINT16                        VendorSpecificDataOffset;
+  UINT16                        VendorSpecificDataLength;
+} EFI_ACPI_6_2_SDEV_STRUCTURE_PCIE_ENDPOINT_DEVICE;
+
+///
+/// ACPI_NAMESPACE_DEVICE based Secure Device Structure
+///
+typedef struct {
+  UINT8                         Type;
+  UINT8                         Flags;
+  UINT16                        Length;
+  UINT16                        DeviceIdentifierOffset;
+  UINT16                        DeviceIdentifierLength;
+  UINT16                        VendorSpecificDataOffset;
+  UINT16                        VendorSpecificDataLength;
+} EFI_ACPI_6_2_SDEV_STRUCTURE_ACPI_NAMESPACE_DEVICE;
+
+///
+/// Boot Error Record Table (BERT)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      BootErrorRegionLength;
+  UINT64                      BootErrorRegion;
+} EFI_ACPI_6_2_BOOT_ERROR_RECORD_TABLE_HEADER;
+
+///
+/// BERT Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_BOOT_ERROR_RECORD_TABLE_REVISION 0x01
+
+///
+/// Boot Error Region Block Status Definition
+///
+typedef struct {
+  UINT32       UncorrectableErrorValid:1;
+  UINT32       CorrectableErrorValid:1;
+  UINT32       MultipleUncorrectableErrors:1;
+  UINT32       MultipleCorrectableErrors:1;
+  UINT32       ErrorDataEntryCount:10;
+  UINT32       Reserved:18;
+} EFI_ACPI_6_2_ERROR_BLOCK_STATUS;
+
+///
+/// Boot Error Region Definition
+///
+typedef struct {
+  EFI_ACPI_6_2_ERROR_BLOCK_STATUS              BlockStatus;
+  UINT32                                       RawDataOffset;
+  UINT32                                       RawDataLength;
+  UINT32                                       DataLength;
+  UINT32                                       ErrorSeverity;
+} EFI_ACPI_6_2_BOOT_ERROR_REGION_STRUCTURE;
+
+//
+// Boot Error Severity types
+//
+#define EFI_ACPI_6_2_ERROR_SEVERITY_CORRECTABLE  0x00
+#define EFI_ACPI_6_2_ERROR_SEVERITY_FATAL        0x01
+#define EFI_ACPI_6_2_ERROR_SEVERITY_CORRECTED    0x02
+#define EFI_ACPI_6_2_ERROR_SEVERITY_NONE         0x03
+
+///
+/// Generic Error Data Entry Definition
+///
+typedef struct {
+  UINT8    SectionType[16];
+  UINT32   ErrorSeverity;
+  UINT16   Revision;
+  UINT8    ValidationBits;
+  UINT8    Flags;
+  UINT32   ErrorDataLength;
+  UINT8    FruId[16];
+  UINT8    FruText[20];
+  UINT8    Timestamp[8];
+} EFI_ACPI_6_2_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;
+
+///
+/// Generic Error Data Entry Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_GENERIC_ERROR_DATA_ENTRY_REVISION  0x0300
+
+///
+/// HEST - Hardware Error Source Table
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      ErrorSourceCount;
+} EFI_ACPI_6_2_HARDWARE_ERROR_SOURCE_TABLE_HEADER;
+
+///
+/// HEST Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01
+
+//
+// Error Source structure types.
+//
+#define EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION  0x00
+#define EFI_ACPI_6_2_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK  0x01
+#define EFI_ACPI_6_2_IA32_ARCHITECTURE_NMI_ERROR                0x02
+#define EFI_ACPI_6_2_PCI_EXPRESS_ROOT_PORT_AER                  0x06
+#define EFI_ACPI_6_2_PCI_EXPRESS_DEVICE_AER                     0x07
+#define EFI_ACPI_6_2_PCI_EXPRESS_BRIDGE_AER                     0x08
+#define EFI_ACPI_6_2_GENERIC_HARDWARE_ERROR                     0x09
+#define EFI_ACPI_6_2_GENERIC_HARDWARE_ERROR_VERSION_2           0x0A
+#define EFI_ACPI_6_2_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK   0x0B
+
+//
+// Error Source structure flags.
+//
+#define EFI_ACPI_6_2_ERROR_SOURCE_FLAG_FIRMWARE_FIRST       (1 << 0)
+#define EFI_ACPI_6_2_ERROR_SOURCE_FLAG_GLOBAL               (1 << 1)
+#define EFI_ACPI_6_2_ERROR_SOURCE_FLAG_GHES_ASSIST          (1 << 2)
+
+///
+/// IA-32 Architecture Machine Check Exception Structure Definition
+///
+typedef struct {
+  UINT16  Type;
+  UINT16  SourceId;
+  UINT8   Reserved0[2];
+  UINT8   Flags;
+  UINT8   Enabled;
+  UINT32  NumberOfRecordsToPreAllocate;
+  UINT32  MaxSectionsPerRecord;
+  UINT64  GlobalCapabilityInitData;
+  UINT64  GlobalControlInitData;
+  UINT8   NumberOfHardwareBanks;
+  UINT8   Reserved1[7];
+} EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;
+
+///
+/// IA-32 Architecture Machine Check Bank Structure Definition
+///
+typedef struct {
+  UINT8   BankNumber;
+  UINT8   ClearStatusOnInitialization;
+  UINT8   StatusDataFormat;
+  UINT8   Reserved0;
+  UINT32  ControlRegisterMsrAddress;
+  UINT64  ControlInitData;
+  UINT32  StatusRegisterMsrAddress;
+  UINT32  AddressRegisterMsrAddress;
+  UINT32  MiscRegisterMsrAddress;
+} EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;
+
+///
+/// IA-32 Architecture Machine Check Bank Structure MCA data format
+///
+#define EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32      0x00
+#define EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64   0x01
+#define EFI_ACPI_6_2_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64     0x02
+
+//
+// Hardware Error Notification types. All other values are reserved
+//
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_POLLED                         0x00
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT             0x01
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT                0x02
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_SCI                            0x03
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_NMI                            0x04
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_CMCI                           0x05
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_MCE                            0x06
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL                    0x07
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEA                      0x08
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEI                      0x09
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_GSIV                           0x0A
+#define EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_SOFTWARE_DELEGATED_EXCEPTION   0x0B
+
+///
+/// Hardware Error Notification Configuration Write Enable Structure Definition
+///
+typedef struct {
+  UINT16    Type:1;
+  UINT16    PollInterval:1;
+  UINT16    SwitchToPollingThresholdValue:1;
+  UINT16    SwitchToPollingThresholdWindow:1;
+  UINT16    ErrorThresholdValue:1;
+  UINT16    ErrorThresholdWindow:1;
+  UINT16    Reserved:10;
+} EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;
+
+///
+/// Hardware Error Notification Structure Definition
+///
+typedef struct {
+  UINT8                                                                          Type;
+  UINT8                                                                          Length;
+  EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE  ConfigurationWriteEnable;
+  UINT32                                                                         PollInterval;
+  UINT32                                                                         Vector;
+  UINT32                                                                         SwitchToPollingThresholdValue;
+  UINT32                                                                         SwitchToPollingThresholdWindow;
+  UINT32                                                                         ErrorThresholdValue;
+  UINT32                                                                         ErrorThresholdWindow;
+} EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;
+
+///
+/// IA-32 Architecture Corrected Machine Check Structure Definition
+///
+typedef struct {
+  UINT16                                                 Type;
+  UINT16                                                 SourceId;
+  UINT8                                                  Reserved0[2];
+  UINT8                                                  Flags;
+  UINT8                                                  Enabled;
+  UINT32                                                 NumberOfRecordsToPreAllocate;
+  UINT32                                                 MaxSectionsPerRecord;
+  EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE     NotificationStructure;
+  UINT8                                                  NumberOfHardwareBanks;
+  UINT8                                                  Reserved1[3];
+} EFI_ACPI_6_2_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;
+
+///
+/// IA-32 Architecture NMI Error Structure Definition
+///
+typedef struct {
+  UINT16  Type;
+  UINT16  SourceId;
+  UINT8   Reserved0[2];
+  UINT32  NumberOfRecordsToPreAllocate;
+  UINT32  MaxSectionsPerRecord;
+  UINT32  MaxRawDataLength;
+} EFI_ACPI_6_2_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;
+
+///
+/// PCI Express Root Port AER Structure Definition
+///
+typedef struct {
+  UINT16  Type;
+  UINT16  SourceId;
+  UINT8   Reserved0[2];
+  UINT8   Flags;
+  UINT8   Enabled;
+  UINT32  NumberOfRecordsToPreAllocate;
+  UINT32  MaxSectionsPerRecord;
+  UINT32  Bus;
+  UINT16  Device;
+  UINT16  Function;
+  UINT16  DeviceControl;
+  UINT8   Reserved1[2];
+  UINT32  UncorrectableErrorMask;
+  UINT32  UncorrectableErrorSeverity;
+  UINT32  CorrectableErrorMask;
+  UINT32  AdvancedErrorCapabilitiesAndControl;
+  UINT32  RootErrorCommand;
+} EFI_ACPI_6_2_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;
+
+///
+/// PCI Express Device AER Structure Definition
+///
+typedef struct {
+  UINT16  Type;
+  UINT16  SourceId;
+  UINT8   Reserved0[2];
+  UINT8   Flags;
+  UINT8   Enabled;
+  UINT32  NumberOfRecordsToPreAllocate;
+  UINT32  MaxSectionsPerRecord;
+  UINT32  Bus;
+  UINT16  Device;
+  UINT16  Function;
+  UINT16  DeviceControl;
+  UINT8   Reserved1[2];
+  UINT32  UncorrectableErrorMask;
+  UINT32  UncorrectableErrorSeverity;
+  UINT32  CorrectableErrorMask;
+  UINT32  AdvancedErrorCapabilitiesAndControl;
+} EFI_ACPI_6_2_PCI_EXPRESS_DEVICE_AER_STRUCTURE;
+
+///
+/// PCI Express Bridge AER Structure Definition
+///
+typedef struct {
+  UINT16  Type;
+  UINT16  SourceId;
+  UINT8   Reserved0[2];
+  UINT8   Flags;
+  UINT8   Enabled;
+  UINT32  NumberOfRecordsToPreAllocate;
+  UINT32  MaxSectionsPerRecord;
+  UINT32  Bus;
+  UINT16  Device;
+  UINT16  Function;
+  UINT16  DeviceControl;
+  UINT8   Reserved1[2];
+  UINT32  UncorrectableErrorMask;
+  UINT32  UncorrectableErrorSeverity;
+  UINT32  CorrectableErrorMask;
+  UINT32  AdvancedErrorCapabilitiesAndControl;
+  UINT32  SecondaryUncorrectableErrorMask;
+  UINT32  SecondaryUncorrectableErrorSeverity;
+  UINT32  SecondaryAdvancedErrorCapabilitiesAndControl;
+} EFI_ACPI_6_2_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;
+
+///
+/// Generic Hardware Error Source Structure Definition
+///
+typedef struct {
+  UINT16                                                 Type;
+  UINT16                                                 SourceId;
+  UINT16                                                 RelatedSourceId;
+  UINT8                                                  Flags;
+  UINT8                                                  Enabled;
+  UINT32                                                 NumberOfRecordsToPreAllocate;
+  UINT32                                                 MaxSectionsPerRecord;
+  UINT32                                                 MaxRawDataLength;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE                 ErrorStatusAddress;
+  EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE     NotificationStructure;
+  UINT32                                                 ErrorStatusBlockLength;
+} EFI_ACPI_6_2_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;
+
+///
+/// Generic Hardware Error Source Version 2 Structure Definition
+///
+typedef struct {
+  UINT16                                                 Type;
+  UINT16                                                 SourceId;
+  UINT16                                                 RelatedSourceId;
+  UINT8                                                  Flags;
+  UINT8                                                  Enabled;
+  UINT32                                                 NumberOfRecordsToPreAllocate;
+  UINT32                                                 MaxSectionsPerRecord;
+  UINT32                                                 MaxRawDataLength;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE                 ErrorStatusAddress;
+  EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE     NotificationStructure;
+  UINT32                                                 ErrorStatusBlockLength;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE                 ReadAckRegister;
+  UINT64                                                 ReadAckPreserve;
+  UINT64                                                 ReadAckWrite;
+} EFI_ACPI_6_2_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE;
+
+///
+/// Generic Error Status Definition
+///
+typedef struct {
+  EFI_ACPI_6_2_ERROR_BLOCK_STATUS              BlockStatus;
+  UINT32                                       RawDataOffset;
+  UINT32                                       RawDataLength;
+  UINT32                                       DataLength;
+  UINT32                                       ErrorSeverity;
+} EFI_ACPI_6_2_GENERIC_ERROR_STATUS_STRUCTURE;
+
+///
+/// IA-32 Architecture Deferred Machine Check Structure Definition
+///
+typedef struct {
+  UINT16                                                Type;
+  UINT16                                                SourceId;
+  UINT8                                                 Reserved0[2];
+  UINT8                                                 Flags;
+  UINT8                                                 Enabled;
+  UINT32                                                NumberOfRecordsToPreAllocate;
+  UINT32                                                MaxSectionsPerRecord;
+  EFI_ACPI_6_2_HARDWARE_ERROR_NOTIFICATION_STRUCTURE    NotificationStructure;
+  UINT8                                                 NumberOfHardwareBanks;
+  UINT8                                                 Reserved1[3];
+} EFI_ACPI_6_2_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK_STRUCTURE;;
+
+///
+/// HMAT - Heterogeneous Memory Attribute Table
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT8                       Reserved[4];
+} EFI_ACPI_6_2_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER;
+
+///
+/// HMAT Revision (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION 0x01
+
+///
+/// HMAT types
+///
+#define EFI_ACPI_6_2_HMAT_TYPE_MEMORY_SUBSYSTEM_ADDRESS_RANGE               0x00
+#define EFI_ACPI_6_2_HMAT_TYPE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO   0x01
+#define EFI_ACPI_6_2_HMAT_TYPE_MEMORY_SIDE_CACHE_INFO                       0x02
+
+///
+/// HMAT Structure Header
+///
+typedef struct {
+  UINT16                        Type;
+  UINT8                         Reserved[2];
+  UINT32                        Length;
+} EFI_ACPI_6_2_HMAT_STRUCTURE_HEADER;
+
+///
+/// Memory Subsystem Address Range Structure flags
+///
+typedef struct {
+  UINT16                        ProcessorProximityDomainValid:1;
+  UINT16                        MemoryProximityDomainValid:1;
+  UINT16                        ReservationHint:1;
+  UINT16                        Reserved:13;
+} EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SUBSYSTEM_ADDRESS_RANGE_FLAGS;
+
+///
+/// Memory Subsystem Address Range Structure
+///
+typedef struct {
+  UINT16                                                            Type;
+  UINT8                                                             Reserved[2];
+  UINT32                                                            Length;
+  EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SUBSYSTEM_ADDRESS_RANGE_FLAGS  Flags;
+  UINT8                                                             Reserved1[2];
+  UINT32                                                            ProcessorProximityDomain;
+  UINT32                                                            MemoryProximityDomain;
+  UINT8                                                             Reserved2[4];
+  UINT64                                                            SystemPhysicalAddressRangeBase;
+  UINT64                                                            SystemPhysicalAddressRangeLength;
+} EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SUBSYSTEM_ADDRESS_RANGE;
+
+///
+/// System Locality Latency and Bandwidth Information Structure flags
+///
+typedef struct {
+  UINT8                         MemoryHierarchy:5;
+  UINT8                         Reserved:3;
+} EFI_ACPI_6_2_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS;
+
+///
+/// System Locality Latency and Bandwidth Information Structure
+///
+typedef struct {
+  UINT16                                                                        Type;
+  UINT8                                                                         Reserved[2];
+  UINT32                                                                        Length;
+  EFI_ACPI_6_2_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS  Flags;
+  UINT8                                                                         DataType;
+  UINT8                                                                         Reserved1[2];
+  UINT32                                                                        NumberOfInitiatorProximityDomains;
+  UINT32                                                                        NumberOfTargetProximityDomains;
+  UINT8                                                                         Reserved2[4];
+  UINT64                                                                        EntryBaseUnit;
+} EFI_ACPI_6_2_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO;
+
+///
+/// Memory Side Cache Information Structure cache attributes
+///
+typedef struct {
+  UINT32                        TotalCacheLevels:4;
+  UINT32                        CacheLevel:4;
+  UINT32                        CacheAssociativity:4;
+  UINT32                        WritePolicy:4;
+  UINT32                        CacheLineSize:16;
+} EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES;
+
+///
+/// Memory Side Cache Information Structure
+///
+typedef struct {
+  UINT16                                                                Type;
+  UINT8                                                                 Reserved[2];
+  UINT32                                                                Length;
+  UINT32                                                                MemoryProximityDomain;
+  UINT8                                                                 Reserved1[4];
+  UINT64                                                                MemorySideCacheSize;
+  EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES   CacheAttributes;
+  UINT8                                                                 Reserved2[2];
+  UINT16                                                                NumberOfSmbiosHandles;
+} EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO;
+
+///
+/// ERST - Error Record Serialization Table
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      SerializationHeaderSize;
+  UINT8                       Reserved0[4];
+  UINT32                      InstructionEntryCount;
+} EFI_ACPI_6_2_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;
+
+///
+/// ERST Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01
+
+///
+/// ERST Serialization Actions
+///
+#define EFI_ACPI_6_2_ERST_BEGIN_WRITE_OPERATION                    0x00
+#define EFI_ACPI_6_2_ERST_BEGIN_READ_OPERATION                     0x01
+#define EFI_ACPI_6_2_ERST_BEGIN_CLEAR_OPERATION                    0x02
+#define EFI_ACPI_6_2_ERST_END_OPERATION                            0x03
+#define EFI_ACPI_6_2_ERST_SET_RECORD_OFFSET                        0x04
+#define EFI_ACPI_6_2_ERST_EXECUTE_OPERATION                        0x05
+#define EFI_ACPI_6_2_ERST_CHECK_BUSY_STATUS                        0x06
+#define EFI_ACPI_6_2_ERST_GET_COMMAND_STATUS                       0x07
+#define EFI_ACPI_6_2_ERST_GET_RECORD_IDENTIFIER                    0x08
+#define EFI_ACPI_6_2_ERST_SET_RECORD_IDENTIFIER                    0x09
+#define EFI_ACPI_6_2_ERST_GET_RECORD_COUNT                         0x0A
+#define EFI_ACPI_6_2_ERST_BEGIN_DUMMY_WRITE_OPERATION              0x0B
+#define EFI_ACPI_6_2_ERST_GET_ERROR_LOG_ADDRESS_RANGE              0x0D
+#define EFI_ACPI_6_2_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH       0x0E
+#define EFI_ACPI_6_2_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES   0x0F
+#define EFI_ACPI_6_2_ERST_GET_EXECUTE_OPERATION_TIMINGS            0x10
+
+///
+/// ERST Action Command Status
+///
+#define EFI_ACPI_6_2_ERST_STATUS_SUCCESS                           0x00
+#define EFI_ACPI_6_2_ERST_STATUS_NOT_ENOUGH_SPACE                  0x01
+#define EFI_ACPI_6_2_ERST_STATUS_HARDWARE_NOT_AVAILABLE            0x02
+#define EFI_ACPI_6_2_ERST_STATUS_FAILED                            0x03
+#define EFI_ACPI_6_2_ERST_STATUS_RECORD_STORE_EMPTY                0x04
+#define EFI_ACPI_6_2_ERST_STATUS_RECORD_NOT_FOUND                  0x05
+
+///
+/// ERST Serialization Instructions
+///
+#define EFI_ACPI_6_2_ERST_READ_REGISTER                            0x00
+#define EFI_ACPI_6_2_ERST_READ_REGISTER_VALUE                      0x01
+#define EFI_ACPI_6_2_ERST_WRITE_REGISTER                           0x02
+#define EFI_ACPI_6_2_ERST_WRITE_REGISTER_VALUE                     0x03
+#define EFI_ACPI_6_2_ERST_NOOP                                     0x04
+#define EFI_ACPI_6_2_ERST_LOAD_VAR1                                0x05
+#define EFI_ACPI_6_2_ERST_LOAD_VAR2                                0x06
+#define EFI_ACPI_6_2_ERST_STORE_VAR1                               0x07
+#define EFI_ACPI_6_2_ERST_ADD                                      0x08
+#define EFI_ACPI_6_2_ERST_SUBTRACT                                 0x09
+#define EFI_ACPI_6_2_ERST_ADD_VALUE                                0x0A
+#define EFI_ACPI_6_2_ERST_SUBTRACT_VALUE                           0x0B
+#define EFI_ACPI_6_2_ERST_STALL                                    0x0C
+#define EFI_ACPI_6_2_ERST_STALL_WHILE_TRUE                         0x0D
+#define EFI_ACPI_6_2_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE            0x0E
+#define EFI_ACPI_6_2_ERST_GOTO                                     0x0F
+#define EFI_ACPI_6_2_ERST_SET_SRC_ADDRESS_BASE                     0x10
+#define EFI_ACPI_6_2_ERST_SET_DST_ADDRESS_BASE                     0x11
+#define EFI_ACPI_6_2_ERST_MOVE_DATA                                0x12
+
+///
+/// ERST Instruction Flags
+///
+#define EFI_ACPI_6_2_ERST_PRESERVE_REGISTER                        0x01
+
+///
+/// ERST Serialization Instruction Entry
+///
+typedef struct {
+  UINT8                                    SerializationAction;
+  UINT8                                    Instruction;
+  UINT8                                    Flags;
+  UINT8                                    Reserved0;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE   RegisterRegion;
+  UINT64                                   Value;
+  UINT64                                   Mask;
+} EFI_ACPI_6_2_ERST_SERIALIZATION_INSTRUCTION_ENTRY;
+
+///
+/// EINJ - Error Injection Table
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      InjectionHeaderSize;
+  UINT8                       InjectionFlags;
+  UINT8                       Reserved0[3];
+  UINT32                      InjectionEntryCount;
+} EFI_ACPI_6_2_ERROR_INJECTION_TABLE_HEADER;
+
+///
+/// EINJ Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_ERROR_INJECTION_TABLE_REVISION 0x01
+
+///
+/// EINJ Error Injection Actions
+///
+#define EFI_ACPI_6_2_EINJ_BEGIN_INJECTION_OPERATION                0x00
+#define EFI_ACPI_6_2_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE           0x01
+#define EFI_ACPI_6_2_EINJ_SET_ERROR_TYPE                           0x02
+#define EFI_ACPI_6_2_EINJ_GET_ERROR_TYPE                           0x03
+#define EFI_ACPI_6_2_EINJ_END_OPERATION                            0x04
+#define EFI_ACPI_6_2_EINJ_EXECUTE_OPERATION                        0x05
+#define EFI_ACPI_6_2_EINJ_CHECK_BUSY_STATUS                        0x06
+#define EFI_ACPI_6_2_EINJ_GET_COMMAND_STATUS                       0x07
+#define EFI_ACPI_6_2_EINJ_TRIGGER_ERROR                            0xFF
+
+///
+/// EINJ Action Command Status
+///
+#define EFI_ACPI_6_2_EINJ_STATUS_SUCCESS                           0x00
+#define EFI_ACPI_6_2_EINJ_STATUS_UNKNOWN_FAILURE                   0x01
+#define EFI_ACPI_6_2_EINJ_STATUS_INVALID_ACCESS                    0x02
+
+///
+/// EINJ Error Type Definition
+///
+#define EFI_ACPI_6_2_EINJ_ERROR_PROCESSOR_CORRECTABLE                 (1 << 0)
+#define EFI_ACPI_6_2_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL      (1 << 1)
+#define EFI_ACPI_6_2_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL         (1 << 2)
+#define EFI_ACPI_6_2_EINJ_ERROR_MEMORY_CORRECTABLE                    (1 << 3)
+#define EFI_ACPI_6_2_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL         (1 << 4)
+#define EFI_ACPI_6_2_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL            (1 << 5)
+#define EFI_ACPI_6_2_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE               (1 << 6)
+#define EFI_ACPI_6_2_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL    (1 << 7)
+#define EFI_ACPI_6_2_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL       (1 << 8)
+#define EFI_ACPI_6_2_EINJ_ERROR_PLATFORM_CORRECTABLE                  (1 << 9)
+#define EFI_ACPI_6_2_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL       (1 << 10)
+#define EFI_ACPI_6_2_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL          (1 << 11)
+
+///
+/// EINJ Injection Instructions
+///
+#define EFI_ACPI_6_2_EINJ_READ_REGISTER                            0x00
+#define EFI_ACPI_6_2_EINJ_READ_REGISTER_VALUE                      0x01
+#define EFI_ACPI_6_2_EINJ_WRITE_REGISTER                           0x02
+#define EFI_ACPI_6_2_EINJ_WRITE_REGISTER_VALUE                     0x03
+#define EFI_ACPI_6_2_EINJ_NOOP                                     0x04
+
+///
+/// EINJ Instruction Flags
+///
+#define EFI_ACPI_6_2_EINJ_PRESERVE_REGISTER                        0x01
+
+///
+/// EINJ Injection Instruction Entry
+///
+typedef struct {
+  UINT8                                    InjectionAction;
+  UINT8                                    Instruction;
+  UINT8                                    Flags;
+  UINT8                                    Reserved0;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE   RegisterRegion;
+  UINT64                                   Value;
+  UINT64                                   Mask;
+} EFI_ACPI_6_2_EINJ_INJECTION_INSTRUCTION_ENTRY;
+
+///
+/// EINJ Trigger Action Table
+///
+typedef struct {
+  UINT32  HeaderSize;
+  UINT32  Revision;
+  UINT32  TableSize;
+  UINT32  EntryCount;
+} EFI_ACPI_6_2_EINJ_TRIGGER_ACTION_TABLE;
+
+///
+/// Platform Communications Channel Table (PCCT)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      Flags;
+  UINT64                      Reserved;
+} EFI_ACPI_6_2_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER;
+
+///
+/// PCCT Version (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x02
+
+///
+/// PCCT Global Flags
+///
+#define EFI_ACPI_6_2_PCCT_FLAGS_PLATFORM_INTERRUPT  BIT0
+
+//
+// PCCT Subspace type
+//
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_GENERIC                         0x00
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS     0x01
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS     0x02
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_3_EXTENDED_PCC                  0x03
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_TYPE_4_EXTENDED_PCC                  0x04
+
+///
+/// PCC Subspace Structure Header
+///
+typedef struct {
+  UINT8        Type;
+  UINT8        Length;
+} EFI_ACPI_6_2_PCCT_SUBSPACE_HEADER;
+
+///
+/// Generic Communications Subspace Structure
+///
+typedef struct {
+  UINT8                                    Type;
+  UINT8                                    Length;
+  UINT8                                    Reserved[6];
+  UINT64                                   BaseAddress;
+  UINT64                                   AddressLength;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE   DoorbellRegister;
+  UINT64                                   DoorbellPreserve;
+  UINT64                                   DoorbellWrite;
+  UINT32                                   NominalLatency;
+  UINT32                                   MaximumPeriodicAccessRate;
+  UINT16                                   MinimumRequestTurnaroundTime;
+} EFI_ACPI_6_2_PCCT_SUBSPACE_GENERIC;
+
+///
+/// Generic Communications Channel Shared Memory Region
+///
+
+typedef struct {
+  UINT8                                    Command;
+  UINT8                                    Reserved:7;
+  UINT8                                    NotifyOnCompletion:1;
+} EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND;
+
+typedef struct {
+  UINT8                                    CommandComplete:1;
+  UINT8                                    PlatformInterrupt:1;
+  UINT8                                    Error:1;
+  UINT8                                    PlatformNotification:1;
+  UINT8                                    Reserved:4;
+  UINT8                                    Reserved1;
+} EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;
+
+typedef struct {
+  UINT32                                                    Signature;
+  EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND    Command;
+  EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS     Status;
+} EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER;
+
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_POLARITY    BIT0
+#define EFI_ACPI_6_2_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_MODE        BIT1
+
+///
+/// Type 1 HW-Reduced Communications Subspace Structure
+///
+typedef struct {
+  UINT8                                    Type;
+  UINT8                                    Length;
+  UINT32                                   PlatformInterrupt;
+  UINT8                                    PlatformInterruptFlags;
+  UINT8                                    Reserved;
+  UINT64                                   BaseAddress;
+  UINT64                                   AddressLength;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE   DoorbellRegister;
+  UINT64                                   DoorbellPreserve;
+  UINT64                                   DoorbellWrite;
+  UINT32                                   NominalLatency;
+  UINT32                                   MaximumPeriodicAccessRate;
+  UINT16                                   MinimumRequestTurnaroundTime;
+} EFI_ACPI_6_2_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS;
+
+///
+/// Type 2 HW-Reduced Communications Subspace Structure
+///
+typedef struct {
+  UINT8                                    Type;
+  UINT8                                    Length;
+  UINT32                                   PlatformInterrupt;
+  UINT8                                    PlatformInterruptFlags;
+  UINT8                                    Reserved;
+  UINT64                                   BaseAddress;
+  UINT64                                   AddressLength;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE   DoorbellRegister;
+  UINT64                                   DoorbellPreserve;
+  UINT64                                   DoorbellWrite;
+  UINT32                                   NominalLatency;
+  UINT32                                   MaximumPeriodicAccessRate;
+  UINT16                                   MinimumRequestTurnaroundTime;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE   PlatformInterruptAckRegister;
+  UINT64                                   PlatformInterruptAckPreserve;
+  UINT64                                   PlatformInterruptAckWrite;
+} EFI_ACPI_6_2_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS;
+
+///
+/// Type 3 Extended PCC Subspace Structure
+///
+typedef struct {
+  UINT8                                    Type;
+  UINT8                                    Length;
+  UINT32                                   PlatformInterrupt;
+  UINT8                                    PlatformInterruptFlags;
+  UINT8                                    Reserved;
+  UINT64                                   BaseAddress;
+  UINT32                                   AddressLength;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE   DoorbellRegister;
+  UINT64                                   DoorbellPreserve;
+  UINT64                                   DoorbellWrite;
+  UINT32                                   NominalLatency;
+  UINT32                                   MaximumPeriodicAccessRate;
+  UINT32                                   MinimumRequestTurnaroundTime;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE   PlatformInterruptAckRegister;
+  UINT64                                   PlatformInterruptAckPreserve;
+  UINT64                                   PlatformInterruptAckSet;
+  UINT8                                    Reserved1[8];
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE   CommandCompleteCheckRegister;
+  UINT64                                   CommandCompleteCheckMask;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE   CommandCompleteUpdateRegister;
+  UINT64                                   CommandCompleteUpdatePreserve;
+  UINT64                                   CommandCompleteUpdateSet;
+  EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE   ErrorStatusRegister;
+  UINT64                                   ErrorStatusMask;
+} EFI_ACPI_6_2_PCCT_SUBSPACE_3_EXTENDED_PCC;
+
+///
+/// Type 4 Extended PCC Subspace Structure
+///
+typedef EFI_ACPI_6_2_PCCT_SUBSPACE_3_EXTENDED_PCC EFI_ACPI_6_2_PCCT_SUBSPACE_4_EXTENDED_PCC;
+
+#define EFI_ACPI_6_2_PCCT_MASTER_SLAVE_COMMUNICATIONS_CHANNEL_FLAGS_NOTIFY_ON_COMPLETION BIT0
+
+typedef struct {
+  UINT32                                    Signature;
+  UINT32                                    Flags;
+  UINT32                                    Length;
+  UINT32                                    Command;
+} EFI_ACPI_6_2_PCCT_EXTENDED_PCC_SHARED_MEMORY_REGION_HEADER;
+
+///
+/// Platform Debug Trigger Table (PDTT)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER   Header;
+  UINT8                         TriggerCount;
+  UINT8                         Reserved[3];
+  UINT32                        TriggerIdentifierArrayOffset;
+} EFI_ACPI_6_2_PLATFORM_DEBUG_TRIGGER_TABLE_HEADER;
+
+///
+/// PDTT Revision (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_PLATFORM_DEBUG_TRIGGER_TABLE_REVISION 0x00
+
+///
+/// PDTT Platform Communication Channel Identifier Structure
+///
+typedef struct {
+  UINT16                        SubChannelIdentifer:8;
+  UINT16                        Runtime:1;
+  UINT16                        WaitForCompletion:1;
+  UINT16                        Reserved:6;
+} EFI_ACPI_6_2_PDTT_PCC_IDENTIFIER;
+
+///
+/// PCC Commands Codes used by Platform Debug Trigger Table
+///
+#define EFI_ACPI_6_2_PDTT_PCC_COMMAND_DOORBELL_ONLY     0x00
+#define EFI_ACPI_6_2_PDTT_PCC_COMMAND_VENDOR_SPECIFIC   0x01
+
+///
+/// PPTT Platform Communication Channel
+///
+typedef EFI_ACPI_6_2_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER EFI_ACPI_6_2_PDTT_PCC;
+
+///
+/// Processor Properties Topology Table (PPTT)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER   Header;
+} EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER;
+
+///
+/// PPTT Revision (as defined in ACPI 6.2 spec.)
+///
+#define EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION 0x01
+
+///
+/// PPTT types
+///
+#define EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR     0x00
+#define EFI_ACPI_6_2_PPTT_TYPE_CACHE         0x01
+#define EFI_ACPI_6_2_PPTT_TYPE_ID            0x02
+
+///
+/// PPTT Structure Header
+///
+typedef struct {
+  UINT8                         Type;
+  UINT8                         Length;
+  UINT8                         Reserved[2];
+} EFI_ACPI_6_2_PPTT_STRUCTURE_HEADER;
+
+///
+/// For PPTT struct processor flags
+///
+#define EFI_ACPI_6_2_PPTT_PROCESSOR_ID_INVALID 0x0
+#define EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID   0x1
+
+///
+/// Processor hierarchy node structure flags
+///
+typedef struct {
+  UINT32                        PhysicalPackage:1;
+  UINT32                        AcpiProcessorIdValid:1;
+  UINT32                        Reserved:30;
+} EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR_FLAGS;
+
+///
+/// Processor hierarchy node structure
+///
+typedef struct {
+  UINT8                                         Type;
+  UINT8                                         Length;
+  UINT8                                         Reserved[2];
+  EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR_FLAGS   Flags;
+  UINT32                                        Parent;
+  UINT32                                        AcpiProcessorId;
+  UINT32                                        NumberOfPrivateResources;
+} EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR;
+
+///
+/// Cache Type Structure flags
+///
+typedef struct {
+  UINT32                        SizePropertyValid:1;
+  UINT32                        NumberOfSetsValid:1;
+  UINT32                        AssociativityValid:1;
+  UINT32                        AllocationTypeValid:1;
+  UINT32                        CacheTypeValid:1;
+  UINT32                        WritePolicyValid:1;
+  UINT32                        LineSizeValid:1;
+  UINT32                        Reserved:25;
+} EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_FLAGS;
+
+///
+/// For cache attributes
+///
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ            0x0
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_WRITE           0x1
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE      0x2
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA            0x0
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION     0x1
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED         0x2
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK    0x0
+#define EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_THROUGH 0x1
+
+///
+/// Cache Type Structure cache attributes
+///
+typedef struct {
+  UINT8                         AllocationType:2;
+  UINT8                         CacheType:2;
+  UINT8                         WritePolicy:1;
+  UINT8                         Reserved:3;
+} EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES;
+
+///
+/// Cache Type Structure
+///
+typedef struct {
+  UINT8                                         Type;
+  UINT8                                         Length;
+  UINT8                                         Reserved[2];
+  EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_FLAGS       Flags;
+  UINT32                                        NextLevelOfCache;
+  UINT32                                        Size;
+  UINT32                                        NumberOfSets;
+  UINT8                                         Associativity;
+  EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES  Attributes;
+  UINT16                                        LineSize;
+} EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE;
+
+///
+/// ID structure
+///
+typedef struct {
+  UINT8                         Type;
+  UINT8                         Length;
+  UINT8                         Reserved[2];
+  UINT32                        VendorId;
+  UINT64                        Level1Id;
+  UINT64                        Level2Id;
+  UINT16                        MajorRev;
+  UINT16                        MinorRev;
+  UINT16                        SpinRev;
+} EFI_ACPI_6_2_PPTT_STRUCTURE_ID;
+
+//
+// Known table signatures
+//
+
+///
+/// "RSD PTR " Root System Description Pointer
+///
+#define EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE  SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
+
+///
+/// "APIC" Multiple APIC Description Table
+///
+#define EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('A', 'P', 'I', 'C')
+
+///
+/// "BERT" Boot Error Record Table
+///
+#define EFI_ACPI_6_2_BOOT_ERROR_RECORD_TABLE_SIGNATURE  SIGNATURE_32('B', 'E', 'R', 'T')
+
+///
+/// "BGRT" Boot Graphics Resource Table
+///
+#define EFI_ACPI_6_2_BOOT_GRAPHICS_RESOURCE_TABLE_SIGNATURE  SIGNATURE_32('B', 'G', 'R', 'T')
+
+///
+/// "CPEP" Corrected Platform Error Polling Table
+///
+#define EFI_ACPI_6_2_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE  SIGNATURE_32('C', 'P', 'E', 'P')
+
+///
+/// "DSDT" Differentiated System Description Table
+///
+#define EFI_ACPI_6_2_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('D', 'S', 'D', 'T')
+
+///
+/// "ECDT" Embedded Controller Boot Resources Table
+///
+#define EFI_ACPI_6_2_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE  SIGNATURE_32('E', 'C', 'D', 'T')
+
+///
+/// "EINJ" Error Injection Table
+///
+#define EFI_ACPI_6_2_ERROR_INJECTION_TABLE_SIGNATURE  SIGNATURE_32('E', 'I', 'N', 'J')
+
+///
+/// "ERST" Error Record Serialization Table
+///
+#define EFI_ACPI_6_2_ERROR_RECORD_SERIALIZATION_TABLE_SIGNATURE  SIGNATURE_32('E', 'R', 'S', 'T')
+
+///
+/// "FACP" Fixed ACPI Description Table
+///
+#define EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('F', 'A', 'C', 'P')
+
+///
+/// "FACS" Firmware ACPI Control Structure
+///
+#define EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE  SIGNATURE_32('F', 'A', 'C', 'S')
+
+///
+/// "FPDT" Firmware Performance Data Table
+///
+#define EFI_ACPI_6_2_FIRMWARE_PERFORMANCE_DATA_TABLE_SIGNATURE  SIGNATURE_32('F', 'P', 'D', 'T')
+
+///
+/// "GTDT" Generic Timer Description Table
+///
+#define EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('G', 'T', 'D', 'T')
+
+///
+/// "HEST" Hardware Error Source Table
+///
+#define EFI_ACPI_6_2_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE  SIGNATURE_32('H', 'E', 'S', 'T')
+
+///
+/// "HMAT" Heterogeneous Memory Attribute Table
+///
+#define EFI_ACPI_6_2_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE  SIGNATURE_32('H', 'M', 'A', 'T')
+
+///
+/// "MPST" Memory Power State Table
+///
+#define EFI_ACPI_6_2_MEMORY_POWER_STATE_TABLE_SIGNATURE  SIGNATURE_32('M', 'P', 'S', 'T')
+
+///
+/// "MSCT" Maximum System Characteristics Table
+///
+#define EFI_ACPI_6_2_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE  SIGNATURE_32('M', 'S', 'C', 'T')
+
+///
+/// "NFIT" NVDIMM Firmware Interface Table
+///
+#define EFI_ACPI_6_2_NVDIMM_FIRMWARE_INTERFACE_TABLE_STRUCTURE_SIGNATURE  SIGNATURE_32('N', 'F', 'I', 'T')
+
+///
+/// "PDTT" Platform Debug Trigger Table
+///
+#define EFI_ACPI_6_2_PLATFORM_DEBUG_TRIGGER_TABLE_STRUCTURE_SIGNATURE  SIGNATURE_32('P', 'D', 'T', 'T')
+
+///
+/// "PMTT" Platform Memory Topology Table
+///
+#define EFI_ACPI_6_2_PLATFORM_MEMORY_TOPOLOGY_TABLE_SIGNATURE  SIGNATURE_32('P', 'M', 'T', 'T')
+
+///
+/// "PPTT" Processor Properties Topology Table
+///
+#define EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE  SIGNATURE_32('P', 'P', 'T', 'T')
+
+///
+/// "PSDT" Persistent System Description Table
+///
+#define EFI_ACPI_6_2_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('P', 'S', 'D', 'T')
+
+///
+/// "RASF" ACPI RAS Feature Table
+///
+#define EFI_ACPI_6_2_ACPI_RAS_FEATURE_TABLE_SIGNATURE  SIGNATURE_32('R', 'A', 'S', 'F')
+
+///
+/// "RSDT" Root System Description Table
+///
+#define EFI_ACPI_6_2_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('R', 'S', 'D', 'T')
+
+///
+/// "SBST" Smart Battery Specification Table
+///
+#define EFI_ACPI_6_2_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE  SIGNATURE_32('S', 'B', 'S', 'T')
+
+///
+/// "SDEV" Secure DEVices Table
+///
+#define EFI_ACPI_6_2_SECURE_DEVICES_TABLE_SIGNATURE  SIGNATURE_32('S', 'D', 'E', 'V')
+
+///
+/// "SLIT" System Locality Information Table
+///
+#define EFI_ACPI_6_2_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE  SIGNATURE_32('S', 'L', 'I', 'T')
+
+///
+/// "SRAT" System Resource Affinity Table
+///
+#define EFI_ACPI_6_2_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE  SIGNATURE_32('S', 'R', 'A', 'T')
+
+///
+/// "SSDT" Secondary System Description Table
+///
+#define EFI_ACPI_6_2_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('S', 'S', 'D', 'T')
+
+///
+/// "XSDT" Extended System Description Table
+///
+#define EFI_ACPI_6_2_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('X', 'S', 'D', 'T')
+
+///
+/// "BOOT" MS Simple Boot Spec
+///
+#define EFI_ACPI_6_2_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE  SIGNATURE_32('B', 'O', 'O', 'T')
+
+///
+/// "CSRT" MS Core System Resource Table
+///
+#define EFI_ACPI_6_2_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE  SIGNATURE_32('C', 'S', 'R', 'T')
+
+///
+/// "DBG2" MS Debug Port 2 Spec
+///
+#define EFI_ACPI_6_2_DEBUG_PORT_2_TABLE_SIGNATURE  SIGNATURE_32('D', 'B', 'G', '2')
+
+///
+/// "DBGP" MS Debug Port Spec
+///
+#define EFI_ACPI_6_2_DEBUG_PORT_TABLE_SIGNATURE  SIGNATURE_32('D', 'B', 'G', 'P')
+
+///
+/// "DMAR" DMA Remapping Table
+///
+#define EFI_ACPI_6_2_DMA_REMAPPING_TABLE_SIGNATURE  SIGNATURE_32('D', 'M', 'A', 'R')
+
+///
+/// "DPPT" DMA Protection Policy Table
+///
+#define EFI_ACPI_6_2_DMA_PROTECTION_POLICY_TABLE_SIGNATURE  SIGNATURE_32('D', 'P', 'P', 'T')
+
+///
+/// "DRTM" Dynamic Root of Trust for Measurement Table
+///
+#define EFI_ACPI_6_2_DYNAMIC_ROOT_OF_TRUST_FOR_MEASUREMENT_TABLE_SIGNATURE  SIGNATURE_32('D', 'R', 'T', 'M')
+
+///
+/// "ETDT" Event Timer Description Table
+///
+#define EFI_ACPI_6_2_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('E', 'T', 'D', 'T')
+
+///
+/// "HPET" IA-PC High Precision Event Timer Table
+///
+#define EFI_ACPI_6_2_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE  SIGNATURE_32('H', 'P', 'E', 'T')
+
+///
+/// "iBFT" iSCSI Boot Firmware Table
+///
+#define EFI_ACPI_6_2_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE  SIGNATURE_32('i', 'B', 'F', 'T')
+
+///
+/// "IORT" I/O Remapping Table
+///
+#define EFI_ACPI_6_2_IO_REMAPPING_TABLE_SIGNATURE  SIGNATURE_32('I', 'O', 'R', 'T')
+
+///
+/// "IVRS" I/O Virtualization Reporting Structure
+///
+#define EFI_ACPI_6_2_IO_VIRTUALIZATION_REPORTING_STRUCTURE_SIGNATURE  SIGNATURE_32('I', 'V', 'R', 'S')
+
+///
+/// "LPIT" Low Power Idle Table
+///
+#define EFI_ACPI_6_2_LOW_POWER_IDLE_TABLE_STRUCTURE_SIGNATURE  SIGNATURE_32('L', 'P', 'I', 'T')
+
+///
+/// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table
+///
+#define EFI_ACPI_6_2_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('M', 'C', 'F', 'G')
+
+///
+/// "MCHI" Management Controller Host Interface Table
+///
+#define EFI_ACPI_6_2_MANAGEMENT_CONTROLLER_HOST_INTERFACE_TABLE_SIGNATURE  SIGNATURE_32('M', 'C', 'H', 'I')
+
+///
+/// "MSDM" MS Data Management Table
+///
+#define EFI_ACPI_6_2_DATA_MANAGEMENT_TABLE_SIGNATURE  SIGNATURE_32('M', 'S', 'D', 'M')
+
+///
+/// "PCCT" Platform Communications Channel Table
+///
+#define EFI_ACPI_6_2_PLATFORM_COMMUNICATIONS_CHANNEL_TABLE_SIGNATURE  SIGNATURE_32('P', 'C', 'C', 'T')
+
+///
+/// "SDEI" Software Delegated Exceptions Interface Table
+///
+#define EFI_ACPI_6_2_SOFTWARE_DELEGATED_EXCEPTIONS_INTERFACE_TABLE_SIGNATURE  SIGNATURE_32('S', 'D', 'E', 'I')
+
+///
+/// "SLIC" MS Software Licensing Table Specification
+///
+#define EFI_ACPI_6_2_SOFTWARE_LICENSING_TABLE_SIGNATURE  SIGNATURE_32('S', 'L', 'I', 'C')
+
+///
+/// "SPCR" Serial Port Console Redirection Table
+///
+#define EFI_ACPI_6_2_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE  SIGNATURE_32('S', 'P', 'C', 'R')
+
+///
+/// "SPMI" Server Platform Management Interface Table
+///
+#define EFI_ACPI_6_2_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE  SIGNATURE_32('S', 'P', 'M', 'I')
+
+///
+/// "STAO" _STA Override Table
+///
+#define EFI_ACPI_6_2_STA_OVERRIDE_TABLE_SIGNATURE  SIGNATURE_32('S', 'T', 'A', 'O')
+
+///
+/// "TCPA" Trusted Computing Platform Alliance Capabilities Table
+///
+#define EFI_ACPI_6_2_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE  SIGNATURE_32('T', 'C', 'P', 'A')
+
+///
+/// "TPM2" Trusted Computing Platform 1 Table
+///
+#define EFI_ACPI_6_2_TRUSTED_COMPUTING_PLATFORM_2_TABLE_SIGNATURE  SIGNATURE_32('T', 'P', 'M', '2')
+
+///
+/// "UEFI" UEFI ACPI Data Table
+///
+#define EFI_ACPI_6_2_UEFI_ACPI_DATA_TABLE_SIGNATURE  SIGNATURE_32('U', 'E', 'F', 'I')
+
+///
+/// "WAET" Windows ACPI Emulated Devices Table
+///
+#define EFI_ACPI_6_2_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE  SIGNATURE_32('W', 'A', 'E', 'T')
+
+///
+/// "WDAT" Watchdog Action Table
+///
+#define EFI_ACPI_6_2_WATCHDOG_ACTION_TABLE_SIGNATURE  SIGNATURE_32('W', 'D', 'A', 'T')
+
+///
+/// "WDRT" Watchdog Resource Table
+///
+#define EFI_ACPI_6_2_WATCHDOG_RESOURCE_TABLE_SIGNATURE  SIGNATURE_32('W', 'D', 'R', 'T')
+
+///
+/// "WPBT" MS Platform Binary Table
+///
+#define EFI_ACPI_6_2_PLATFORM_BINARY_TABLE_SIGNATURE  SIGNATURE_32('W', 'P', 'B', 'T')
+
+///
+/// "WSMT" Windows SMM Security Mitigation Table
+///
+#define EFI_ACPI_6_2_WINDOWS_SMM_SECURITY_MITIGATION_TABLE_SIGNATURE  SIGNATURE_32('W', 'S', 'M', 'T')
+
+///
+/// "XENV" Xen Project Table
+///
+#define EFI_ACPI_6_2_XEN_PROJECT_TABLE_SIGNATURE  SIGNATURE_32('X', 'E', 'N', 'V')
+
+#pragma pack()
+
+#endif
diff --git a/MdePkg/Include/IndustryStandard/Acpi63.h b/MdePkg/Include/IndustryStandard/Acpi63.h
new file mode 100644
index 000000000000..b365cd0cd4de
--- /dev/null
+++ b/MdePkg/Include/IndustryStandard/Acpi63.h
@@ -0,0 +1,2960 @@
+/** @file
+  ACPI 6.3 definitions from the ACPI Specification Revision 6.3 Jan, 2019.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2019 - 2020, ARM Ltd. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _ACPI_6_3_H_
+#define _ACPI_6_3_H_
+
+#include <IndustryStandard/Acpi62.h>
+
+//
+// Ensure proper structure formats
+//
+#pragma pack(1)
+
+///
+/// ACPI 6.3 Generic Address Space definition
+///
+typedef struct {
+  UINT8   AddressSpaceId;
+  UINT8   RegisterBitWidth;
+  UINT8   RegisterBitOffset;
+  UINT8   AccessSize;
+  UINT64  Address;
+} EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE;
+
+//
+// Generic Address Space Address IDs
+//
+#define EFI_ACPI_6_3_SYSTEM_MEMORY                   0x00
+#define EFI_ACPI_6_3_SYSTEM_IO                       0x01
+#define EFI_ACPI_6_3_PCI_CONFIGURATION_SPACE         0x02
+#define EFI_ACPI_6_3_EMBEDDED_CONTROLLER             0x03
+#define EFI_ACPI_6_3_SMBUS                           0x04
+#define EFI_ACPI_6_3_SYSTEM_CMOS                     0x05
+#define EFI_ACPI_6_3_PCI_BAR_TARGET                  0x06
+#define EFI_ACPI_6_3_IPMI                            0x07
+#define EFI_ACPI_6_3_GENERAL_PURPOSE_IO              0x08
+#define EFI_ACPI_6_3_GENERIC_SERIAL_BUS              0x09
+#define EFI_ACPI_6_3_PLATFORM_COMMUNICATION_CHANNEL  0x0A
+#define EFI_ACPI_6_3_FUNCTIONAL_FIXED_HARDWARE       0x7F
+
+//
+// Generic Address Space Access Sizes
+//
+#define EFI_ACPI_6_3_UNDEFINED  0
+#define EFI_ACPI_6_3_BYTE       1
+#define EFI_ACPI_6_3_WORD       2
+#define EFI_ACPI_6_3_DWORD      3
+#define EFI_ACPI_6_3_QWORD      4
+
+//
+// ACPI 6.3 table structures
+//
+
+///
+/// Root System Description Pointer Structure
+///
+typedef struct {
+  UINT64  Signature;
+  UINT8   Checksum;
+  UINT8   OemId[6];
+  UINT8   Revision;
+  UINT32  RsdtAddress;
+  UINT32  Length;
+  UINT64  XsdtAddress;
+  UINT8   ExtendedChecksum;
+  UINT8   Reserved[3];
+} EFI_ACPI_6_3_ROOT_SYSTEM_DESCRIPTION_POINTER;
+
+///
+/// RSD_PTR Revision (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_ROOT_SYSTEM_DESCRIPTION_POINTER_REVISION 0x02  ///< ACPISpec (Revision 6.3) says current value is 2
+
+///
+/// Common table header, this prefaces all ACPI tables, including FACS, but
+/// excluding the RSD PTR structure
+///
+typedef struct {
+  UINT32  Signature;
+  UINT32  Length;
+} EFI_ACPI_6_3_COMMON_HEADER;
+
+//
+// Root System Description Table
+// No definition needed as it is a common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
+//
+
+///
+/// RSDT Revision (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_ROOT_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+//
+// Extended System Description Table
+// No definition needed as it is a common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
+//
+
+///
+/// XSDT Revision (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_EXTENDED_SYSTEM_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Fixed ACPI Description Table Structure (FADT)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER             Header;
+  UINT32                                  FirmwareCtrl;
+  UINT32                                  Dsdt;
+  UINT8                                   Reserved0;
+  UINT8                                   PreferredPmProfile;
+  UINT16                                  SciInt;
+  UINT32                                  SmiCmd;
+  UINT8                                   AcpiEnable;
+  UINT8                                   AcpiDisable;
+  UINT8                                   S4BiosReq;
+  UINT8                                   PstateCnt;
+  UINT32                                  Pm1aEvtBlk;
+  UINT32                                  Pm1bEvtBlk;
+  UINT32                                  Pm1aCntBlk;
+  UINT32                                  Pm1bCntBlk;
+  UINT32                                  Pm2CntBlk;
+  UINT32                                  PmTmrBlk;
+  UINT32                                  Gpe0Blk;
+  UINT32                                  Gpe1Blk;
+  UINT8                                   Pm1EvtLen;
+  UINT8                                   Pm1CntLen;
+  UINT8                                   Pm2CntLen;
+  UINT8                                   PmTmrLen;
+  UINT8                                   Gpe0BlkLen;
+  UINT8                                   Gpe1BlkLen;
+  UINT8                                   Gpe1Base;
+  UINT8                                   CstCnt;
+  UINT16                                  PLvl2Lat;
+  UINT16                                  PLvl3Lat;
+  UINT16                                  FlushSize;
+  UINT16                                  FlushStride;
+  UINT8                                   DutyOffset;
+  UINT8                                   DutyWidth;
+  UINT8                                   DayAlrm;
+  UINT8                                   MonAlrm;
+  UINT8                                   Century;
+  UINT16                                  IaPcBootArch;
+  UINT8                                   Reserved1;
+  UINT32                                  Flags;
+  EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE  ResetReg;
+  UINT8                                   ResetValue;
+  UINT16                                  ArmBootArch;
+  UINT8                                   MinorVersion;
+  UINT64                                  XFirmwareCtrl;
+  UINT64                                  XDsdt;
+  EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE  XPm1aEvtBlk;
+  EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE  XPm1bEvtBlk;
+  EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE  XPm1aCntBlk;
+  EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE  XPm1bCntBlk;
+  EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE  XPm2CntBlk;
+  EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE  XPmTmrBlk;
+  EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE  XGpe0Blk;
+  EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE  XGpe1Blk;
+  EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE  SleepControlReg;
+  EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE  SleepStatusReg;
+  UINT64                                  HypervisorVendorIdentity;
+} EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE;
+
+///
+/// FADT Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_REVISION  0x06
+#define EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION  0x03
+
+//
+// Fixed ACPI Description Table Preferred Power Management Profile
+//
+#define EFI_ACPI_6_3_PM_PROFILE_UNSPECIFIED         0
+#define EFI_ACPI_6_3_PM_PROFILE_DESKTOP             1
+#define EFI_ACPI_6_3_PM_PROFILE_MOBILE              2
+#define EFI_ACPI_6_3_PM_PROFILE_WORKSTATION         3
+#define EFI_ACPI_6_3_PM_PROFILE_ENTERPRISE_SERVER   4
+#define EFI_ACPI_6_3_PM_PROFILE_SOHO_SERVER         5
+#define EFI_ACPI_6_3_PM_PROFILE_APPLIANCE_PC        6
+#define EFI_ACPI_6_3_PM_PROFILE_PERFORMANCE_SERVER  7
+#define EFI_ACPI_6_3_PM_PROFILE_TABLET              8
+
+//
+// Fixed ACPI Description Table Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_3_LEGACY_DEVICES              BIT0
+#define EFI_ACPI_6_3_8042                        BIT1
+#define EFI_ACPI_6_3_VGA_NOT_PRESENT             BIT2
+#define EFI_ACPI_6_3_MSI_NOT_SUPPORTED           BIT3
+#define EFI_ACPI_6_3_PCIE_ASPM_CONTROLS          BIT4
+#define EFI_ACPI_6_3_CMOS_RTC_NOT_PRESENT        BIT5
+
+//
+// Fixed ACPI Description Table Arm Boot Architecture Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_3_ARM_PSCI_COMPLIANT              BIT0
+#define EFI_ACPI_6_3_ARM_PSCI_USE_HVC                BIT1
+
+//
+// Fixed ACPI Description Table Fixed Feature Flags
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_3_WBINVD                                 BIT0
+#define EFI_ACPI_6_3_WBINVD_FLUSH                           BIT1
+#define EFI_ACPI_6_3_PROC_C1                                BIT2
+#define EFI_ACPI_6_3_P_LVL2_UP                              BIT3
+#define EFI_ACPI_6_3_PWR_BUTTON                             BIT4
+#define EFI_ACPI_6_3_SLP_BUTTON                             BIT5
+#define EFI_ACPI_6_3_FIX_RTC                                BIT6
+#define EFI_ACPI_6_3_RTC_S4                                 BIT7
+#define EFI_ACPI_6_3_TMR_VAL_EXT                            BIT8
+#define EFI_ACPI_6_3_DCK_CAP                                BIT9
+#define EFI_ACPI_6_3_RESET_REG_SUP                          BIT10
+#define EFI_ACPI_6_3_SEALED_CASE                            BIT11
+#define EFI_ACPI_6_3_HEADLESS                               BIT12
+#define EFI_ACPI_6_3_CPU_SW_SLP                             BIT13
+#define EFI_ACPI_6_3_PCI_EXP_WAK                            BIT14
+#define EFI_ACPI_6_3_USE_PLATFORM_CLOCK                     BIT15
+#define EFI_ACPI_6_3_S4_RTC_STS_VALID                       BIT16
+#define EFI_ACPI_6_3_REMOTE_POWER_ON_CAPABLE                BIT17
+#define EFI_ACPI_6_3_FORCE_APIC_CLUSTER_MODEL               BIT18
+#define EFI_ACPI_6_3_FORCE_APIC_PHYSICAL_DESTINATION_MODE   BIT19
+#define EFI_ACPI_6_3_HW_REDUCED_ACPI                        BIT20
+#define EFI_ACPI_6_3_LOW_POWER_S0_IDLE_CAPABLE              BIT21
+
+///
+/// Firmware ACPI Control Structure
+///
+typedef struct {
+  UINT32  Signature;
+  UINT32  Length;
+  UINT32  HardwareSignature;
+  UINT32  FirmwareWakingVector;
+  UINT32  GlobalLock;
+  UINT32  Flags;
+  UINT64  XFirmwareWakingVector;
+  UINT8   Version;
+  UINT8   Reserved0[3];
+  UINT32  OspmFlags;
+  UINT8   Reserved1[24];
+} EFI_ACPI_6_3_FIRMWARE_ACPI_CONTROL_STRUCTURE;
+
+///
+/// FACS Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION  0x02
+
+///
+/// Firmware Control Structure Feature Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_3_S4BIOS_F                     BIT0
+#define EFI_ACPI_6_3_64BIT_WAKE_SUPPORTED_F       BIT1
+
+///
+/// OSPM Enabled Firmware Control Structure Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_3_OSPM_64BIT_WAKE_F            BIT0
+
+//
+// Differentiated System Description Table,
+// Secondary System Description Table
+// and Persistent System Description Table,
+// no definition needed as they are common description table header, the same with
+// EFI_ACPI_DESCRIPTION_HEADER, followed by a definition block.
+//
+#define EFI_ACPI_6_3_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_REVISION   0x02
+#define EFI_ACPI_6_3_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION        0x02
+
+///
+/// Multiple APIC Description Table header definition.  The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      LocalApicAddress;
+  UINT32                      Flags;
+} EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER;
+
+///
+/// MADT Revision (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION 0x05
+
+///
+/// Multiple APIC Flags
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_3_PCAT_COMPAT         BIT0
+
+//
+// Multiple APIC Description Table APIC structure types
+// All other values between 0x0D and 0x7F are reserved and
+// will be ignored by OSPM. 0x80 ~ 0xFF are reserved for OEM.
+//
+#define EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC           0x00
+#define EFI_ACPI_6_3_IO_APIC                        0x01
+#define EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE      0x02
+#define EFI_ACPI_6_3_NON_MASKABLE_INTERRUPT_SOURCE  0x03
+#define EFI_ACPI_6_3_LOCAL_APIC_NMI                 0x04
+#define EFI_ACPI_6_3_LOCAL_APIC_ADDRESS_OVERRIDE    0x05
+#define EFI_ACPI_6_3_IO_SAPIC                       0x06
+#define EFI_ACPI_6_3_LOCAL_SAPIC                    0x07
+#define EFI_ACPI_6_3_PLATFORM_INTERRUPT_SOURCES     0x08
+#define EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC         0x09
+#define EFI_ACPI_6_3_LOCAL_X2APIC_NMI               0x0A
+#define EFI_ACPI_6_3_GIC                            0x0B
+#define EFI_ACPI_6_3_GICD                           0x0C
+#define EFI_ACPI_6_3_GIC_MSI_FRAME                  0x0D
+#define EFI_ACPI_6_3_GICR                           0x0E
+#define EFI_ACPI_6_3_GIC_ITS                        0x0F
+
+//
+// APIC Structure Definitions
+//
+
+///
+/// Processor Local APIC Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   AcpiProcessorUid;
+  UINT8   ApicId;
+  UINT32  Flags;
+} EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE;
+
+///
+/// Local APIC Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_3_LOCAL_APIC_ENABLED         BIT0
+#define EFI_ACPI_6_3_LOCAL_APIC_ONLINE_CAPABLE  BIT1
+
+///
+/// IO APIC Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   IoApicId;
+  UINT8   Reserved;
+  UINT32  IoApicAddress;
+  UINT32  GlobalSystemInterruptBase;
+} EFI_ACPI_6_3_IO_APIC_STRUCTURE;
+
+///
+/// Interrupt Source Override Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   Bus;
+  UINT8   Source;
+  UINT32  GlobalSystemInterrupt;
+  UINT16  Flags;
+} EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT8   InterruptType;
+  UINT8   ProcessorId;
+  UINT8   ProcessorEid;
+  UINT8   IoSapicVector;
+  UINT32  GlobalSystemInterrupt;
+  UINT32  PlatformInterruptSourceFlags;
+  UINT8   CpeiProcessorOverride;
+  UINT8   Reserved[31];
+} EFI_ACPI_6_3_PLATFORM_INTERRUPT_APIC_STRUCTURE;
+
+//
+// MPS INTI flags.
+// All other bits are reserved and must be set to 0.
+//
+#define EFI_ACPI_6_3_POLARITY      (3 << 0)
+#define EFI_ACPI_6_3_TRIGGER_MODE  (3 << 2)
+
+///
+/// Non-Maskable Interrupt Source Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT32  GlobalSystemInterrupt;
+} EFI_ACPI_6_3_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;
+
+///
+/// Local APIC NMI Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   AcpiProcessorUid;
+  UINT16  Flags;
+  UINT8   LocalApicLint;
+} EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE;
+
+///
+/// Local APIC Address Override Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved;
+  UINT64  LocalApicAddress;
+} EFI_ACPI_6_3_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;
+
+///
+/// IO SAPIC Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   IoApicId;
+  UINT8   Reserved;
+  UINT32  GlobalSystemInterruptBase;
+  UINT64  IoSapicAddress;
+} EFI_ACPI_6_3_IO_SAPIC_STRUCTURE;
+
+///
+/// Local SAPIC Structure
+/// This struct followed by a null-terminated ASCII string - ACPI Processor UID String
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   AcpiProcessorId;
+  UINT8   LocalSapicId;
+  UINT8   LocalSapicEid;
+  UINT8   Reserved[3];
+  UINT32  Flags;
+  UINT32  ACPIProcessorUIDValue;
+} EFI_ACPI_6_3_PROCESSOR_LOCAL_SAPIC_STRUCTURE;
+
+///
+/// Platform Interrupt Sources Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT8   InterruptType;
+  UINT8   ProcessorId;
+  UINT8   ProcessorEid;
+  UINT8   IoSapicVector;
+  UINT32  GlobalSystemInterrupt;
+  UINT32  PlatformInterruptSourceFlags;
+} EFI_ACPI_6_3_PLATFORM_INTERRUPT_SOURCES_STRUCTURE;
+
+///
+/// Platform Interrupt Source Flags.
+/// All other bits are reserved and must be set to 0.
+///
+#define EFI_ACPI_6_3_CPEI_PROCESSOR_OVERRIDE          BIT0
+
+///
+/// Processor Local x2APIC Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   Reserved[2];
+  UINT32  X2ApicId;
+  UINT32  Flags;
+  UINT32  AcpiProcessorUid;
+} EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE;
+
+///
+/// Local x2APIC NMI Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Flags;
+  UINT32  AcpiProcessorUid;
+  UINT8   LocalX2ApicLint;
+  UINT8   Reserved[3];
+} EFI_ACPI_6_3_LOCAL_X2APIC_NMI_STRUCTURE;
+
+///
+/// GIC Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved;
+  UINT32  CPUInterfaceNumber;
+  UINT32  AcpiProcessorUid;
+  UINT32  Flags;
+  UINT32  ParkingProtocolVersion;
+  UINT32  PerformanceInterruptGsiv;
+  UINT64  ParkedAddress;
+  UINT64  PhysicalBaseAddress;
+  UINT64  GICV;
+  UINT64  GICH;
+  UINT32  VGICMaintenanceInterrupt;
+  UINT64  GICRBaseAddress;
+  UINT64  MPIDR;
+  UINT8   ProcessorPowerEfficiencyClass;
+  UINT8   Reserved2;
+  UINT16  SpeOverflowInterrupt;
+} EFI_ACPI_6_3_GIC_STRUCTURE;
+
+///
+/// GIC Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_3_GIC_ENABLED                              BIT0
+#define EFI_ACPI_6_3_PERFORMANCE_INTERRUPT_MODEL              BIT1
+#define EFI_ACPI_6_3_VGIC_MAINTENANCE_INTERRUPT_MODE_FLAGS    BIT2
+
+///
+/// GIC Distributor Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved1;
+  UINT32  GicId;
+  UINT64  PhysicalBaseAddress;
+  UINT32  SystemVectorBase;
+  UINT8   GicVersion;
+  UINT8   Reserved2[3];
+} EFI_ACPI_6_3_GIC_DISTRIBUTOR_STRUCTURE;
+
+///
+/// GIC Version
+///
+#define EFI_ACPI_6_3_GIC_V1                                   0x01
+#define EFI_ACPI_6_3_GIC_V2                                   0x02
+#define EFI_ACPI_6_3_GIC_V3                                   0x03
+#define EFI_ACPI_6_3_GIC_V4                                   0x04
+
+///
+/// GIC MSI Frame Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved1;
+  UINT32  GicMsiFrameId;
+  UINT64  PhysicalBaseAddress;
+  UINT32  Flags;
+  UINT16  SPICount;
+  UINT16  SPIBase;
+} EFI_ACPI_6_3_GIC_MSI_FRAME_STRUCTURE;
+
+///
+/// GIC MSI Frame Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_3_SPI_COUNT_BASE_SELECT                    BIT0
+
+///
+/// GICR Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved;
+  UINT64  DiscoveryRangeBaseAddress;
+  UINT32  DiscoveryRangeLength;
+} EFI_ACPI_6_3_GICR_STRUCTURE;
+
+///
+/// GIC Interrupt Translation Service Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT16  Reserved;
+  UINT32  GicItsId;
+  UINT64  PhysicalBaseAddress;
+  UINT32  Reserved2;
+} EFI_ACPI_6_3_GIC_ITS_STRUCTURE;
+
+///
+/// Smart Battery Description Table (SBST)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      WarningEnergyLevel;
+  UINT32                      LowEnergyLevel;
+  UINT32                      CriticalEnergyLevel;
+} EFI_ACPI_6_3_SMART_BATTERY_DESCRIPTION_TABLE;
+
+///
+/// SBST Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_SMART_BATTERY_DESCRIPTION_TABLE_REVISION 0x01
+
+///
+/// Embedded Controller Boot Resources Table (ECDT)
+/// The table is followed by a null terminated ASCII string that contains
+/// a fully qualified reference to the name space object.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER             Header;
+  EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE  EcControl;
+  EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE  EcData;
+  UINT32                                  Uid;
+  UINT8                                   GpeBit;
+} EFI_ACPI_6_3_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE;
+
+///
+/// ECDT Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION  0x01
+
+///
+/// System Resource Affinity Table (SRAT).  The rest of the table
+/// must be defined in a platform specific manner.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      Reserved1;  ///< Must be set to 1
+  UINT64                      Reserved2;
+} EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;
+
+///
+/// SRAT Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION  0x03
+
+//
+// SRAT structure types.
+// All other values between 0x06 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY  0x00
+#define EFI_ACPI_6_3_MEMORY_AFFINITY                      0x01
+#define EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_AFFINITY      0x02
+#define EFI_ACPI_6_3_GICC_AFFINITY                        0x03
+#define EFI_ACPI_6_3_GIC_ITS_AFFINITY                     0x04
+#define EFI_ACPI_6_3_GENERIC_INITIATOR_AFFINITY           0x05
+
+///
+/// Processor Local APIC/SAPIC Affinity Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   ProximityDomain7To0;
+  UINT8   ApicId;
+  UINT32  Flags;
+  UINT8   LocalSapicEid;
+  UINT8   ProximityDomain31To8[3];
+  UINT32  ClockDomain;
+} EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY_STRUCTURE;
+
+///
+/// Local APIC/SAPIC Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)
+
+///
+/// Memory Affinity Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT32  ProximityDomain;
+  UINT16  Reserved1;
+  UINT32  AddressBaseLow;
+  UINT32  AddressBaseHigh;
+  UINT32  LengthLow;
+  UINT32  LengthHigh;
+  UINT32  Reserved2;
+  UINT32  Flags;
+  UINT64  Reserved3;
+} EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE;
+
+//
+// Memory Flags.  All other bits are reserved and must be 0.
+//
+#define EFI_ACPI_6_3_MEMORY_ENABLED       (1 << 0)
+#define EFI_ACPI_6_3_MEMORY_HOT_PLUGGABLE (1 << 1)
+#define EFI_ACPI_6_3_MEMORY_NONVOLATILE   (1 << 2)
+
+///
+/// Processor Local x2APIC Affinity Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   Reserved1[2];
+  UINT32  ProximityDomain;
+  UINT32  X2ApicId;
+  UINT32  Flags;
+  UINT32  ClockDomain;
+  UINT8   Reserved2[4];
+} EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_AFFINITY_STRUCTURE;
+
+///
+/// GICC Affinity Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT32  ProximityDomain;
+  UINT32  AcpiProcessorUid;
+  UINT32  Flags;
+  UINT32  ClockDomain;
+} EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE;
+
+///
+/// GICC Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_3_GICC_ENABLED (1 << 0)
+
+///
+/// GIC Interrupt Translation Service (ITS) Affinity Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT32  ProximityDomain;
+  UINT8   Reserved[2];
+  UINT32  ItsId;
+} EFI_ACPI_6_3_GIC_ITS_AFFINITY_STRUCTURE;
+
+//
+// Generic Initiator Affinity Structure Device Handle Types
+// All other values between 0x02 an 0xFF are reserved and
+// will be ignored by OSPM.
+//
+#define EFI_ACPI_6_3_ACPI_DEVICE_HANDLE     0x00
+#define EFI_ACPI_6_3_PCI_DEVICE_HANDLE      0x01
+
+///
+/// Device Handle - ACPI
+///
+typedef struct {
+  UINT64  AcpiHid;
+  UINT32  AcpiUid;
+  UINT8   Reserved[4];
+} EFI_ACPI_6_3_DEVICE_HANDLE_ACPI;
+
+///
+/// Device Handle - PCI
+///
+typedef struct {
+  UINT16  PciSegment;
+  UINT16  PciBdfNumber;
+  UINT8   Reserved[12];
+} EFI_ACPI_6_3_DEVICE_HANDLE_PCI;
+
+///
+/// Generic Initiator Affinity Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   Reserved1;
+  UINT8   DeviceHandleType;
+  UINT32  ProximityDomain;
+
+  union {
+    EFI_ACPI_6_3_DEVICE_HANDLE_ACPI   Acpi;
+    EFI_ACPI_6_3_DEVICE_HANDLE_PCI    Pci;
+  } DeviceHandle;
+
+  UINT32  Flags;
+  UINT8   Reserved2[4];
+} EFI_ACPI_6_3_GENERIC_INITIATOR_AFFINITY_STRUCTURE;
+
+///
+/// Generic Initiator Affinity Structure Flags. All other bits are reserved
+/// and must be 0.
+///
+#define EFI_ACPI_6_3_GENERIC_INITIATOR_AFFINITY_STRUCTURE_ENABLED (1 << 0)
+
+///
+/// System Locality Distance Information Table (SLIT).
+/// The rest of the table is a matrix.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT64                      NumberOfSystemLocalities;
+} EFI_ACPI_6_3_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER;
+
+///
+/// SLIT Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION  0x01
+
+///
+/// Corrected Platform Error Polling Table (CPEP)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT8                       Reserved[8];
+} EFI_ACPI_6_3_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_HEADER;
+
+///
+/// CPEP Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_REVISION 0x01
+
+//
+// CPEP processor structure types.
+//
+#define EFI_ACPI_6_3_CPEP_PROCESSOR_APIC_SAPIC  0x00
+
+///
+/// Corrected Platform Error Polling Processor Structure Definition
+///
+typedef struct {
+  UINT8   Type;
+  UINT8   Length;
+  UINT8   ProcessorId;
+  UINT8   ProcessorEid;
+  UINT32  PollingInterval;
+} EFI_ACPI_6_3_CPEP_PROCESSOR_APIC_SAPIC_STRUCTURE;
+
+///
+/// Maximum System Characteristics Table (MSCT)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      OffsetProxDomInfo;
+  UINT32                      MaximumNumberOfProximityDomains;
+  UINT32                      MaximumNumberOfClockDomains;
+  UINT64                      MaximumPhysicalAddress;
+} EFI_ACPI_6_3_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_HEADER;
+
+///
+/// MSCT Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_REVISION 0x01
+
+///
+/// Maximum Proximity Domain Information Structure Definition
+///
+typedef struct {
+  UINT8   Revision;
+  UINT8   Length;
+  UINT32  ProximityDomainRangeLow;
+  UINT32  ProximityDomainRangeHigh;
+  UINT32  MaximumProcessorCapacity;
+  UINT64  MaximumMemoryCapacity;
+} EFI_ACPI_6_3_MAXIMUM_PROXIMITY_DOMAIN_INFORMATION_STRUCTURE;
+
+///
+/// ACPI RAS Feature Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT8                       PlatformCommunicationChannelIdentifier[12];
+} EFI_ACPI_6_3_RAS_FEATURE_TABLE;
+
+///
+/// RASF Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_RAS_FEATURE_TABLE_REVISION 0x01
+
+///
+/// ACPI RASF Platform Communication Channel Shared Memory Region definition.
+///
+typedef struct {
+  UINT32                      Signature;
+  UINT16                      Command;
+  UINT16                      Status;
+  UINT16                      Version;
+  UINT8                       RASCapabilities[16];
+  UINT8                       SetRASCapabilities[16];
+  UINT16                      NumberOfRASFParameterBlocks;
+  UINT32                      SetRASCapabilitiesStatus;
+} EFI_ACPI_6_3_RASF_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
+
+///
+/// ACPI RASF PCC command code
+///
+#define EFI_ACPI_6_3_RASF_PCC_COMMAND_CODE_EXECUTE_RASF_COMMAND  0x01
+
+///
+/// ACPI RASF Platform RAS Capabilities
+///
+#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED                         BIT0
+#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_HARDWARE_BASED_PATROL_SCRUB_SUPPORTED_AND_EXPOSED_TO_SOFTWARE BIT1
+#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_CPU_CACHE_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS            BIT2
+#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_MEMORY_CONTROLLER_FLUSH_TO_NVDIMM_DURABILITY_ON_POWER_LOSS    BIT3
+#define EFI_ACPI_6_3_RASF_PLATFORM_RAS_CAPABILITY_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_HARDWARE_MIRRORING         BIT4
+
+///
+/// ACPI RASF Parameter Block structure for PATROL_SCRUB
+///
+typedef struct {
+  UINT16                      Type;
+  UINT16                      Version;
+  UINT16                      Length;
+  UINT16                      PatrolScrubCommand;
+  UINT64                      RequestedAddressRange[2];
+  UINT64                      ActualAddressRange[2];
+  UINT16                      Flags;
+  UINT8                       RequestedSpeed;
+} EFI_ACPI_6_3_RASF_PATROL_SCRUB_PLATFORM_BLOCK_STRUCTURE;
+
+///
+/// ACPI RASF Patrol Scrub command
+///
+#define EFI_ACPI_6_3_RASF_PATROL_SCRUB_COMMAND_GET_PATROL_PARAMETERS   0x01
+#define EFI_ACPI_6_3_RASF_PATROL_SCRUB_COMMAND_START_PATROL_SCRUBBER   0x02
+#define EFI_ACPI_6_3_RASF_PATROL_SCRUB_COMMAND_STOP_PATROL_SCRUBBER    0x03
+
+///
+/// Memory Power State Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT8                       PlatformCommunicationChannelIdentifier;
+  UINT8                       Reserved[3];
+// Memory Power Node Structure
+// Memory Power State Characteristics
+} EFI_ACPI_6_3_MEMORY_POWER_STATUS_TABLE;
+
+///
+/// MPST Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_MEMORY_POWER_STATE_TABLE_REVISION 0x01
+
+///
+/// MPST Platform Communication Channel Shared Memory Region definition.
+///
+typedef struct {
+  UINT32                      Signature;
+  UINT16                      Command;
+  UINT16                      Status;
+  UINT32                      MemoryPowerCommandRegister;
+  UINT32                      MemoryPowerStatusRegister;
+  UINT32                      PowerStateId;
+  UINT32                      MemoryPowerNodeId;
+  UINT64                      MemoryEnergyConsumed;
+  UINT64                      ExpectedAveragePowerComsuned;
+} EFI_ACPI_6_3_MPST_PLATFORM_COMMUNICATION_CHANNEL_SHARED_MEMORY_REGION;
+
+///
+/// ACPI MPST PCC command code
+///
+#define EFI_ACPI_6_3_MPST_PCC_COMMAND_CODE_EXECUTE_MPST_COMMAND  0x03
+
+///
+/// ACPI MPST Memory Power command
+///
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_POWER_STATE       0x01
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_COMMAND_SET_MEMORY_POWER_STATE       0x02
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_COMMAND_GET_AVERAGE_POWER_CONSUMED   0x03
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_COMMAND_GET_MEMORY_ENERGY_CONSUMED   0x04
+
+///
+/// MPST Memory Power Node Table
+///
+typedef struct {
+  UINT8                                             PowerStateValue;
+  UINT8                                             PowerStateInformationIndex;
+} EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE;
+
+typedef struct {
+  UINT8                                             Flag;
+  UINT8                                             Reserved;
+  UINT16                                            MemoryPowerNodeId;
+  UINT32                                            Length;
+  UINT64                                            AddressBase;
+  UINT64                                            AddressLength;
+  UINT32                                            NumberOfPowerStates;
+  UINT32                                            NumberOfPhysicalComponents;
+//EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE              MemoryPowerState[NumberOfPowerStates];
+//UINT16                                            PhysicalComponentIdentifier[NumberOfPhysicalComponents];
+} EFI_ACPI_6_3_MPST_MEMORY_POWER_STRUCTURE;
+
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STRUCTURE_FLAG_ENABLE          0x01
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STRUCTURE_FLAG_POWER_MANAGED   0x02
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STRUCTURE_FLAG_HOT_PLUGGABLE   0x04
+
+typedef struct {
+  UINT16                      MemoryPowerNodeCount;
+  UINT8                       Reserved[2];
+} EFI_ACPI_6_3_MPST_MEMORY_POWER_NODE_TABLE;
+
+///
+/// MPST Memory Power State Characteristics Table
+///
+typedef struct {
+  UINT8                                             PowerStateStructureID;
+  UINT8                                             Flag;
+  UINT16                                            Reserved;
+  UINT32                                            AveragePowerConsumedInMPS0;
+  UINT32                                            RelativePowerSavingToMPS0;
+  UINT64                                            ExitLatencyToMPS0;
+} EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE;
+
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_MEMORY_CONTENT_PRESERVED              0x01
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_ENTRY   0x02
+#define EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_STRUCTURE_FLAG_AUTONOMOUS_MEMORY_POWER_STATE_EXIT    0x04
+
+typedef struct {
+  UINT16                      MemoryPowerStateCharacteristicsCount;
+  UINT8                       Reserved[2];
+} EFI_ACPI_6_3_MPST_MEMORY_POWER_STATE_CHARACTERISTICS_TABLE;
+
+///
+/// Memory Topology Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      Reserved;
+} EFI_ACPI_6_3_MEMORY_TOPOLOGY_TABLE;
+
+///
+/// PMTT Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_MEMORY_TOPOLOGY_TABLE_REVISION 0x01
+
+///
+/// Common Memory Aggregator Device Structure.
+///
+typedef struct {
+  UINT8                       Type;
+  UINT8                       Reserved;
+  UINT16                      Length;
+  UINT16                      Flags;
+  UINT16                      Reserved1;
+} EFI_ACPI_6_3_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// Memory Aggregator Device Type
+///
+#define EFI_ACPI_6_3_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_SOCKET            0x1
+#define EFI_ACPI_6_3_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_MEMORY_CONTROLLER 0x2
+#define EFI_ACPI_6_3_PMMT_MEMORY_AGGREGATOR_DEVICE_TYPE_DIMM              0x3
+
+///
+/// Socket Memory Aggregator Device Structure.
+///
+typedef struct {
+  EFI_ACPI_6_3_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE  Header;
+  UINT16                                                       SocketIdentifier;
+  UINT16                                                       Reserved;
+//EFI_ACPI_6_3_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE  MemoryController[];
+} EFI_ACPI_6_3_PMMT_SOCKET_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// MemoryController Memory Aggregator Device Structure.
+///
+typedef struct {
+  EFI_ACPI_6_3_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE  Header;
+  UINT32                                                       ReadLatency;
+  UINT32                                                       WriteLatency;
+  UINT32                                                       ReadBandwidth;
+  UINT32                                                       WriteBandwidth;
+  UINT16                                                       OptimalAccessUnit;
+  UINT16                                                       OptimalAccessAlignment;
+  UINT16                                                       Reserved;
+  UINT16                                                       NumberOfProximityDomains;
+//UINT32                                                       ProximityDomain[NumberOfProximityDomains];
+//EFI_ACPI_6_3_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE    PhysicalComponent[];
+} EFI_ACPI_6_3_PMMT_MEMORY_CONTROLLER_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// DIMM Memory Aggregator Device Structure.
+///
+typedef struct {
+  EFI_ACPI_6_3_PMMT_COMMON_MEMORY_AGGREGATOR_DEVICE_STRUCTURE  Header;
+  UINT16                                                       PhysicalComponentIdentifier;
+  UINT16                                                       Reserved;
+  UINT32                                                       SizeOfDimm;
+  UINT32                                                       SmbiosHandle;
+} EFI_ACPI_6_3_PMMT_DIMM_MEMORY_AGGREGATOR_DEVICE_STRUCTURE;
+
+///
+/// Boot Graphics Resource Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  ///
+  /// 2-bytes (16 bit) version ID. This value must be 1.
+  ///
+  UINT16                      Version;
+  ///
+  /// 1-byte status field indicating current status about the table.
+  ///     Bits[7:1] = Reserved (must be zero)
+  ///     Bit [0] = Valid. A one indicates the boot image graphic is valid.
+  ///
+  UINT8                       Status;
+  ///
+  /// 1-byte enumerated type field indicating format of the image.
+  ///     0 = Bitmap
+  ///     1 - 255  Reserved (for future use)
+  ///
+  UINT8                       ImageType;
+  ///
+  /// 8-byte (64 bit) physical address pointing to the firmware's in-memory copy
+  /// of the image bitmap.
+  ///
+  UINT64                      ImageAddress;
+  ///
+  /// A 4-byte (32-bit) unsigned long describing the display X-offset of the boot image.
+  /// (X, Y) display offset of the top left corner of the boot image.
+  /// The top left corner of the display is at offset (0, 0).
+  ///
+  UINT32                      ImageOffsetX;
+  ///
+  /// A 4-byte (32-bit) unsigned long describing the display Y-offset of the boot image.
+  /// (X, Y) display offset of the top left corner of the boot image.
+  /// The top left corner of the display is at offset (0, 0).
+  ///
+  UINT32                      ImageOffsetY;
+} EFI_ACPI_6_3_BOOT_GRAPHICS_RESOURCE_TABLE;
+
+///
+/// BGRT Revision
+///
+#define EFI_ACPI_6_3_BOOT_GRAPHICS_RESOURCE_TABLE_REVISION 1
+
+///
+/// BGRT Version
+///
+#define EFI_ACPI_6_3_BGRT_VERSION         0x01
+
+///
+/// BGRT Status
+///
+#define EFI_ACPI_6_3_BGRT_STATUS_NOT_DISPLAYED 0x00
+#define EFI_ACPI_6_3_BGRT_STATUS_DISPLAYED     0x01
+
+///
+/// BGRT Image Type
+///
+#define EFI_ACPI_6_3_BGRT_IMAGE_TYPE_BMP  0x00
+
+///
+/// FPDT Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_FIRMWARE_PERFORMANCE_DATA_TABLE_REVISION 0x01
+
+///
+/// FPDT Performance Record Types
+///
+#define EFI_ACPI_6_3_FPDT_RECORD_TYPE_FIRMWARE_BASIC_BOOT_POINTER      0x0000
+#define EFI_ACPI_6_3_FPDT_RECORD_TYPE_S3_PERFORMANCE_TABLE_POINTER     0x0001
+
+///
+/// FPDT Performance Record Revision
+///
+#define EFI_ACPI_6_3_FPDT_RECORD_REVISION_FIRMWARE_BASIC_BOOT_POINTER  0x01
+#define EFI_ACPI_6_3_FPDT_RECORD_REVISION_S3_PERFORMANCE_TABLE_POINTER 0x01
+
+///
+/// FPDT Runtime Performance Record Types
+///
+#define EFI_ACPI_6_3_FPDT_RUNTIME_RECORD_TYPE_S3_RESUME                0x0000
+#define EFI_ACPI_6_3_FPDT_RUNTIME_RECORD_TYPE_S3_SUSPEND               0x0001
+#define EFI_ACPI_6_3_FPDT_RUNTIME_RECORD_TYPE_FIRMWARE_BASIC_BOOT      0x0002
+
+///
+/// FPDT Runtime Performance Record Revision
+///
+#define EFI_ACPI_6_3_FPDT_RUNTIME_RECORD_REVISION_S3_RESUME            0x01
+#define EFI_ACPI_6_3_FPDT_RUNTIME_RECORD_REVISION_S3_SUSPEND           0x01
+#define EFI_ACPI_6_3_FPDT_RUNTIME_RECORD_REVISION_FIRMWARE_BASIC_BOOT  0x02
+
+///
+/// FPDT Performance Record header
+///
+typedef struct {
+  UINT16           Type;
+  UINT8            Length;
+  UINT8            Revision;
+} EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER;
+
+///
+/// FPDT Performance Table header
+///
+typedef struct {
+  UINT32  Signature;
+  UINT32  Length;
+} EFI_ACPI_6_3_FPDT_PERFORMANCE_TABLE_HEADER;
+
+///
+/// FPDT Firmware Basic Boot Performance Pointer Record Structure
+///
+typedef struct {
+  EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER     Header;
+  UINT32                                          Reserved;
+  ///
+  /// 64-bit processor-relative physical address of the Basic Boot Performance Table.
+  ///
+  UINT64                                          BootPerformanceTablePointer;
+} EFI_ACPI_6_3_FPDT_BOOT_PERFORMANCE_TABLE_POINTER_RECORD;
+
+///
+/// FPDT S3 Performance Table Pointer Record Structure
+///
+typedef struct {
+  EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER     Header;
+  UINT32                                          Reserved;
+  ///
+  /// 64-bit processor-relative physical address of the S3 Performance Table.
+  ///
+  UINT64                                          S3PerformanceTablePointer;
+} EFI_ACPI_6_3_FPDT_S3_PERFORMANCE_TABLE_POINTER_RECORD;
+
+///
+/// FPDT Firmware Basic Boot Performance Record Structure
+///
+typedef struct {
+  EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER     Header;
+  UINT32                                          Reserved;
+  ///
+  /// Timer value logged at the beginning of firmware image execution.
+  /// This may not always be zero or near zero.
+  ///
+  UINT64                                          ResetEnd;
+  ///
+  /// Timer value logged just prior to loading the OS boot loader into memory.
+  /// For non-UEFI compatible boots, this field must be zero.
+  ///
+  UINT64                                          OsLoaderLoadImageStart;
+  ///
+  /// Timer value logged just prior to launching the previously loaded OS boot loader image.
+  /// For non-UEFI compatible boots, the timer value logged will be just prior
+  /// to the INT 19h handler invocation.
+  ///
+  UINT64                                          OsLoaderStartImageStart;
+  ///
+  /// Timer value logged at the point when the OS loader calls the
+  /// ExitBootServices function for UEFI compatible firmware.
+  /// For non-UEFI compatible boots, this field must be zero.
+  ///
+  UINT64                                          ExitBootServicesEntry;
+  ///
+  /// Timer value logged at the point just prior towhen the OS loader gaining
+  /// control back from calls the ExitBootServices function for UEFI compatible firmware.
+  /// For non-UEFI compatible boots, this field must be zero.
+  ///
+  UINT64                                          ExitBootServicesExit;
+} EFI_ACPI_6_3_FPDT_FIRMWARE_BASIC_BOOT_RECORD;
+
+///
+/// FPDT Firmware Basic Boot Performance Table signature
+///
+#define EFI_ACPI_6_3_FPDT_BOOT_PERFORMANCE_TABLE_SIGNATURE  SIGNATURE_32('F', 'B', 'P', 'T')
+
+//
+// FPDT Firmware Basic Boot Performance Table
+//
+typedef struct {
+  EFI_ACPI_6_3_FPDT_PERFORMANCE_TABLE_HEADER      Header;
+  //
+  // one or more Performance Records.
+  //
+} EFI_ACPI_6_3_FPDT_FIRMWARE_BASIC_BOOT_TABLE;
+
+///
+/// FPDT "S3PT" S3 Performance Table
+///
+#define EFI_ACPI_6_3_FPDT_S3_PERFORMANCE_TABLE_SIGNATURE  SIGNATURE_32('S', '3', 'P', 'T')
+
+//
+// FPDT Firmware S3 Boot Performance Table
+//
+typedef struct {
+  EFI_ACPI_6_3_FPDT_PERFORMANCE_TABLE_HEADER      Header;
+  //
+  // one or more Performance Records.
+  //
+} EFI_ACPI_6_3_FPDT_FIRMWARE_S3_BOOT_TABLE;
+
+///
+/// FPDT Basic S3 Resume Performance Record
+///
+typedef struct {
+  EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER     Header;
+  ///
+  /// A count of the number of S3 resume cycles since the last full boot sequence.
+  ///
+  UINT32                                          ResumeCount;
+  ///
+  /// Timer recorded at the end of BIOS S3 resume, just prior to handoff to the
+  /// OS waking vector. Only the most recent resume cycle's time is retained.
+  ///
+  UINT64                                          FullResume;
+  ///
+  /// Average timer value of all resume cycles logged since the last full boot
+  /// sequence, including the most recent resume.  Note that the entire log of
+  /// timer values does not need to be retained in order to calculate this average.
+  ///
+  UINT64                                          AverageResume;
+} EFI_ACPI_6_3_FPDT_S3_RESUME_RECORD;
+
+///
+/// FPDT Basic S3 Suspend Performance Record
+///
+typedef struct {
+  EFI_ACPI_6_3_FPDT_PERFORMANCE_RECORD_HEADER     Header;
+  ///
+  /// Timer value recorded at the OS write to SLP_TYP upon entry to S3.
+  /// Only the most recent suspend cycle's timer value is retained.
+  ///
+  UINT64                                          SuspendStart;
+  ///
+  /// Timer value recorded at the final firmware write to SLP_TYP (or other
+  /// mechanism) used to trigger hardware entry to S3.
+  /// Only the most recent suspend cycle's timer value is retained.
+  ///
+  UINT64                                          SuspendEnd;
+} EFI_ACPI_6_3_FPDT_S3_SUSPEND_RECORD;
+
+///
+/// Firmware Performance Record Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+} EFI_ACPI_6_3_FIRMWARE_PERFORMANCE_RECORD_TABLE;
+
+///
+/// Generic Timer Description Table definition.
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT64                      CntControlBasePhysicalAddress;
+  UINT32                      Reserved;
+  UINT32                      SecurePL1TimerGSIV;
+  UINT32                      SecurePL1TimerFlags;
+  UINT32                      NonSecurePL1TimerGSIV;
+  UINT32                      NonSecurePL1TimerFlags;
+  UINT32                      VirtualTimerGSIV;
+  UINT32                      VirtualTimerFlags;
+  UINT32                      NonSecurePL2TimerGSIV;
+  UINT32                      NonSecurePL2TimerFlags;
+  UINT64                      CntReadBasePhysicalAddress;
+  UINT32                      PlatformTimerCount;
+  UINT32                      PlatformTimerOffset;
+  UINT32                      VirtualPL2TimerGSIV;
+  UINT32                      VirtualPL2TimerFlags;
+} EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE;
+
+///
+/// GTDT Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION 0x03
+
+///
+/// Timer Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_3_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE          BIT0
+#define EFI_ACPI_6_3_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY      BIT1
+#define EFI_ACPI_6_3_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY          BIT2
+
+///
+/// Platform Timer Type
+///
+#define EFI_ACPI_6_3_GTDT_GT_BLOCK                       0
+#define EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG          1
+
+///
+/// GT Block Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT16  Length;
+  UINT8   Reserved;
+  UINT64  CntCtlBase;
+  UINT32  GTBlockTimerCount;
+  UINT32  GTBlockTimerOffset;
+} EFI_ACPI_6_3_GTDT_GT_BLOCK_STRUCTURE;
+
+///
+/// GT Block Timer Structure
+///
+typedef struct {
+  UINT8   GTFrameNumber;
+  UINT8   Reserved[3];
+  UINT64  CntBaseX;
+  UINT64  CntEL0BaseX;
+  UINT32  GTxPhysicalTimerGSIV;
+  UINT32  GTxPhysicalTimerFlags;
+  UINT32  GTxVirtualTimerGSIV;
+  UINT32  GTxVirtualTimerFlags;
+  UINT32  GTxCommonFlags;
+} EFI_ACPI_6_3_GTDT_GT_BLOCK_TIMER_STRUCTURE;
+
+///
+/// GT Block Physical Timers and Virtual Timers Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_3_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE          BIT0
+#define EFI_ACPI_6_3_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY      BIT1
+
+///
+/// Common Flags Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_3_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER              BIT0
+#define EFI_ACPI_6_3_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY      BIT1
+
+///
+/// SBSA Generic Watchdog Structure
+///
+typedef struct {
+  UINT8   Type;
+  UINT16  Length;
+  UINT8   Reserved;
+  UINT64  RefreshFramePhysicalAddress;
+  UINT64  WatchdogControlFramePhysicalAddress;
+  UINT32  WatchdogTimerGSIV;
+  UINT32  WatchdogTimerFlags;
+} EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE;
+
+///
+/// SBSA Generic Watchdog Timer Flags.  All other bits are reserved and must be 0.
+///
+#define EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE          BIT0
+#define EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY      BIT1
+#define EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER                  BIT2
+
+//
+// NVDIMM Firmware Interface Table definition.
+//
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER    Header;
+  UINT32                         Reserved;
+} EFI_ACPI_6_3_NVDIMM_FIRMWARE_INTERFACE_TABLE;
+
+//
+// NFIT Version (as defined in ACPI 6.3 spec.)
+//
+#define EFI_ACPI_6_3_NVDIMM_FIRMWARE_INTERFACE_TABLE_REVISION 0x1
+
+//
+// Definition for NFIT Table Structure Types
+//
+#define EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE_TYPE              0
+#define EFI_ACPI_6_3_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE_TYPE                      1
+#define EFI_ACPI_6_3_NFIT_INTERLEAVE_STRUCTURE_TYPE                                 2
+#define EFI_ACPI_6_3_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE_TYPE              3
+#define EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE_TYPE                      4
+#define EFI_ACPI_6_3_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE_TYPE            5
+#define EFI_ACPI_6_3_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE_TYPE                         6
+
+//
+// Definition for NFIT Structure Header
+//
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+} EFI_ACPI_6_3_NFIT_STRUCTURE_HEADER;
+
+//
+// Definition for System Physical Address Range Structure
+//
+#define EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_CONTROL_REGION_FOR_MANAGEMENT      BIT0
+#define EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_FLAGS_PROXIMITY_DOMAIN_VALID             BIT1
+#define EFI_ACPI_6_3_NFIT_GUID_VOLATILE_MEMORY_REGION                             { 0x7305944F, 0xFDDA, 0x44E3, { 0xB1, 0x6C, 0x3F, 0x22, 0xD2, 0x52, 0xE5, 0xD0 }}
+#define EFI_ACPI_6_3_NFIT_GUID_BYTE_ADDRESSABLE_PERSISTENT_MEMORY_REGION          { 0x66F0D379, 0xB4F3, 0x4074, { 0xAC, 0x43, 0x0D, 0x33, 0x18, 0xB7, 0x8C, 0xDB }}
+#define EFI_ACPI_6_3_NFIT_GUID_NVDIMM_CONTROL_REGION                              { 0x92F701F6, 0x13B4, 0x405D, { 0x91, 0x0B, 0x29, 0x93, 0x67, 0xE8, 0x23, 0x4C }}
+#define EFI_ACPI_6_3_NFIT_GUID_NVDIMM_BLOCK_DATA_WINDOW_REGION                    { 0x91AF0530, 0x5D86, 0x470E, { 0xA6, 0xB0, 0x0A, 0x2D, 0xB9, 0x40, 0x82, 0x49 }}
+#define EFI_ACPI_6_3_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_VOLATILE   { 0x77AB535A, 0x45FC, 0x624B, { 0x55, 0x60, 0xF7, 0xB2, 0x81, 0xD1, 0xF9, 0x6E }}
+#define EFI_ACPI_6_3_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_VOLATILE     { 0x3D5ABD30, 0x4175, 0x87CE, { 0x6D, 0x64, 0xD2, 0xAD, 0xE5, 0x23, 0xC4, 0xBB }}
+#define EFI_ACPI_6_3_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_DISK_REGION_PERSISTENT { 0x5CEA02C9, 0x4D07, 0x69D3, { 0x26, 0x9F ,0x44, 0x96, 0xFB, 0xE0, 0x96, 0xF9 }}
+#define EFI_ACPI_6_3_NFIT_GUID_RAM_DISK_SUPPORTING_VIRTUAL_CD_REGION_PERSISTENT   { 0x08018188, 0x42CD, 0xBB48, { 0x10, 0x0F, 0x53, 0x87, 0xD5, 0x3D, 0xED, 0x3D }}
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+  UINT16                                      SPARangeStructureIndex;
+  UINT16                                      Flags;
+  UINT32                                      Reserved_8;
+  UINT32                                      ProximityDomain;
+  GUID                                        AddressRangeTypeGUID;
+  UINT64                                      SystemPhysicalAddressRangeBase;
+  UINT64                                      SystemPhysicalAddressRangeLength;
+  UINT64                                      AddressRangeMemoryMappingAttribute;
+} EFI_ACPI_6_3_NFIT_SYSTEM_PHYSICAL_ADDRESS_RANGE_STRUCTURE;
+
+//
+// Definition for Memory Device to System Physical Address Range Mapping Structure
+//
+typedef struct {
+  UINT32                                      DIMMNumber:4;
+  UINT32                                      MemoryChannelNumber:4;
+  UINT32                                      MemoryControllerID:4;
+  UINT32                                      SocketID:4;
+  UINT32                                      NodeControllerID:12;
+  UINT32                                      Reserved_28:4;
+} EFI_ACPI_6_3_NFIT_DEVICE_HANDLE;
+
+#define EFI_ACPI_6_3_NFIT_MEMORY_DEVICE_STATE_FLAGS_PREVIOUS_SAVE_FAIL                                      BIT0
+#define EFI_ACPI_6_3_NFIT_MEMORY_DEVICE_STATE_FLAGS_LAST_RESTORE_FAIL                                       BIT1
+#define EFI_ACPI_6_3_NFIT_MEMORY_DEVICE_STATE_FLAGS_PLATFORM_FLUSH_FAIL                                     BIT2
+#define EFI_ACPI_6_3_NFIT_MEMORY_DEVICE_STATE_FLAGS_NOT_ARMED_PRIOR_TO_OSPM_HAND_OFF                        BIT3
+#define EFI_ACPI_6_3_NFIT_MEMORY_DEVICE_STATE_FLAGS_SMART_HEALTH_EVENTS_PRIOR_OSPM_HAND_OFF                 BIT4
+#define EFI_ACPI_6_3_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_ENABLED_TO_NOTIFY_OSPM_ON_SMART_HEALTH_EVENTS  BIT5
+#define EFI_ACPI_6_3_NFIT_MEMORY_DEVICE_STATE_FLAGS_FIRMWARE_NOT_MAP_NVDIMM_TO_SPA                          BIT6
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+  EFI_ACPI_6_3_NFIT_DEVICE_HANDLE             NFITDeviceHandle;
+  UINT16                                      NVDIMMPhysicalID;
+  UINT16                                      NVDIMMRegionID;
+  UINT16                                      SPARangeStructureIndex ;
+  UINT16                                      NVDIMMControlRegionStructureIndex;
+  UINT64                                      NVDIMMRegionSize;
+  UINT64                                      RegionOffset;
+  UINT64                                      NVDIMMPhysicalAddressRegionBase;
+  UINT16                                      InterleaveStructureIndex;
+  UINT16                                      InterleaveWays;
+  UINT16                                      NVDIMMStateFlags;
+  UINT16                                      Reserved_46;
+} EFI_ACPI_6_3_NFIT_NVDIMM_REGION_MAPPING_STRUCTURE;
+
+//
+// Definition for Interleave Structure
+//
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+  UINT16                                      InterleaveStructureIndex;
+  UINT16                                      Reserved_6;
+  UINT32                                      NumberOfLines;
+  UINT32                                      LineSize;
+//UINT32                                      LineOffset[NumberOfLines];
+} EFI_ACPI_6_3_NFIT_INTERLEAVE_STRUCTURE;
+
+//
+// Definition for SMBIOS Management Information Structure
+//
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+  UINT32                                      Reserved_4;
+//UINT8                                       Data[];
+} EFI_ACPI_6_3_NFIT_SMBIOS_MANAGEMENT_INFORMATION_STRUCTURE;
+
+//
+// Definition for NVDIMM Control Region Structure
+//
+#define EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_VALID_FIELDS_MANUFACTURING           BIT0
+
+#define EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_FLAGS_BLOCK_DATA_WINDOWS_BUFFERED    BIT0
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+  UINT16                                      NVDIMMControlRegionStructureIndex;
+  UINT16                                      VendorID;
+  UINT16                                      DeviceID;
+  UINT16                                      RevisionID;
+  UINT16                                      SubsystemVendorID;
+  UINT16                                      SubsystemDeviceID;
+  UINT16                                      SubsystemRevisionID;
+  UINT8                                       ValidFields;
+  UINT8                                       ManufacturingLocation;
+  UINT16                                      ManufacturingDate;
+  UINT8                                       Reserved_22[2];
+  UINT32                                      SerialNumber;
+  UINT16                                      RegionFormatInterfaceCode;
+  UINT16                                      NumberOfBlockControlWindows;
+  UINT64                                      SizeOfBlockControlWindow;
+  UINT64                                      CommandRegisterOffsetInBlockControlWindow;
+  UINT64                                      SizeOfCommandRegisterInBlockControlWindows;
+  UINT64                                      StatusRegisterOffsetInBlockControlWindow;
+  UINT64                                      SizeOfStatusRegisterInBlockControlWindows;
+  UINT16                                      NVDIMMControlRegionFlag;
+  UINT8                                       Reserved_74[6];
+} EFI_ACPI_6_3_NFIT_NVDIMM_CONTROL_REGION_STRUCTURE;
+
+//
+// Definition for NVDIMM Block Data Window Region Structure
+//
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+  UINT16                                      NVDIMMControlRegionStructureIndex;
+  UINT16                                      NumberOfBlockDataWindows;
+  UINT64                                      BlockDataWindowStartOffset;
+  UINT64                                      SizeOfBlockDataWindow;
+  UINT64                                      BlockAccessibleMemoryCapacity;
+  UINT64                                      BeginningAddressOfFirstBlockInBlockAccessibleMemory;
+} EFI_ACPI_6_3_NFIT_NVDIMM_BLOCK_DATA_WINDOW_REGION_STRUCTURE;
+
+//
+// Definition for Flush Hint Address Structure
+//
+typedef struct {
+  UINT16                                      Type;
+  UINT16                                      Length;
+  EFI_ACPI_6_3_NFIT_DEVICE_HANDLE             NFITDeviceHandle;
+  UINT16                                      NumberOfFlushHintAddresses;
+  UINT8                                       Reserved_10[6];
+//UINT64                                      FlushHintAddress[NumberOfFlushHintAddresses];
+} EFI_ACPI_6_3_NFIT_FLUSH_HINT_ADDRESS_STRUCTURE;
+
+///
+/// Secure DEVices Table (SDEV)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER   Header;
+} EFI_ACPI_6_3_SECURE_DEVICES_TABLE_HEADER;
+
+///
+/// SDEV Revision (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_SECURE_DEVICES_TABLE_REVISION      0x01
+
+///
+/// Secure Devcice types
+///
+#define EFI_ACPI_6_3_SDEV_TYPE_PCIE_ENDPOINT_DEVICE     0x01
+#define EFI_ACPI_6_3_SDEV_TYPE_ACPI_NAMESPACE_DEVICE    0x00
+
+///
+/// Secure Devcice flags
+///
+#define EFI_ACPI_6_3_SDEV_FLAG_ALLOW_HANDOFF            BIT0
+
+///
+/// SDEV Structure Header
+///
+typedef struct {
+  UINT8                         Type;
+  UINT8                         Flags;
+  UINT16                        Length;
+} EFI_ACPI_6_3_SDEV_STRUCTURE_HEADER;
+
+///
+/// PCIe Endpoint Device based Secure Device Structure
+///
+typedef struct {
+  UINT8                         Type;
+  UINT8                         Flags;
+  UINT16                        Length;
+  UINT16                        PciSegmentNumber;
+  UINT16                        StartBusNumber;
+  UINT16                        PciPathOffset;
+  UINT16                        PciPathLength;
+  UINT16                        VendorSpecificDataOffset;
+  UINT16                        VendorSpecificDataLength;
+} EFI_ACPI_6_3_SDEV_STRUCTURE_PCIE_ENDPOINT_DEVICE;
+
+///
+/// ACPI_NAMESPACE_DEVICE based Secure Device Structure
+///
+typedef struct {
+  UINT8                         Type;
+  UINT8                         Flags;
+  UINT16                        Length;
+  UINT16                        DeviceIdentifierOffset;
+  UINT16                        DeviceIdentifierLength;
+  UINT16                        VendorSpecificDataOffset;
+  UINT16                        VendorSpecificDataLength;
+} EFI_ACPI_6_3_SDEV_STRUCTURE_ACPI_NAMESPACE_DEVICE;
+
+///
+/// Boot Error Record Table (BERT)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      BootErrorRegionLength;
+  UINT64                      BootErrorRegion;
+} EFI_ACPI_6_3_BOOT_ERROR_RECORD_TABLE_HEADER;
+
+///
+/// BERT Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_BOOT_ERROR_RECORD_TABLE_REVISION 0x01
+
+///
+/// Boot Error Region Block Status Definition
+///
+typedef struct {
+  UINT32       UncorrectableErrorValid:1;
+  UINT32       CorrectableErrorValid:1;
+  UINT32       MultipleUncorrectableErrors:1;
+  UINT32       MultipleCorrectableErrors:1;
+  UINT32       ErrorDataEntryCount:10;
+  UINT32       Reserved:18;
+} EFI_ACPI_6_3_ERROR_BLOCK_STATUS;
+
+///
+/// Boot Error Region Definition
+///
+typedef struct {
+  EFI_ACPI_6_3_ERROR_BLOCK_STATUS              BlockStatus;
+  UINT32                                       RawDataOffset;
+  UINT32                                       RawDataLength;
+  UINT32                                       DataLength;
+  UINT32                                       ErrorSeverity;
+} EFI_ACPI_6_3_BOOT_ERROR_REGION_STRUCTURE;
+
+//
+// Boot Error Severity types
+//
+#define EFI_ACPI_6_3_ERROR_SEVERITY_CORRECTABLE  0x00
+#define EFI_ACPI_6_3_ERROR_SEVERITY_FATAL        0x01
+#define EFI_ACPI_6_3_ERROR_SEVERITY_CORRECTED    0x02
+#define EFI_ACPI_6_3_ERROR_SEVERITY_NONE         0x03
+
+///
+/// Generic Error Data Entry Definition
+///
+typedef struct {
+  UINT8    SectionType[16];
+  UINT32   ErrorSeverity;
+  UINT16   Revision;
+  UINT8    ValidationBits;
+  UINT8    Flags;
+  UINT32   ErrorDataLength;
+  UINT8    FruId[16];
+  UINT8    FruText[20];
+  UINT8    Timestamp[8];
+} EFI_ACPI_6_3_GENERIC_ERROR_DATA_ENTRY_STRUCTURE;
+
+///
+/// Generic Error Data Entry Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_GENERIC_ERROR_DATA_ENTRY_REVISION  0x0300
+
+///
+/// HEST - Hardware Error Source Table
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      ErrorSourceCount;
+} EFI_ACPI_6_3_HARDWARE_ERROR_SOURCE_TABLE_HEADER;
+
+///
+/// HEST Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_HARDWARE_ERROR_SOURCE_TABLE_REVISION 0x01
+
+//
+// Error Source structure types.
+//
+#define EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION  0x00
+#define EFI_ACPI_6_3_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK  0x01
+#define EFI_ACPI_6_3_IA32_ARCHITECTURE_NMI_ERROR                0x02
+#define EFI_ACPI_6_3_PCI_EXPRESS_ROOT_PORT_AER                  0x06
+#define EFI_ACPI_6_3_PCI_EXPRESS_DEVICE_AER                     0x07
+#define EFI_ACPI_6_3_PCI_EXPRESS_BRIDGE_AER                     0x08
+#define EFI_ACPI_6_3_GENERIC_HARDWARE_ERROR                     0x09
+#define EFI_ACPI_6_3_GENERIC_HARDWARE_ERROR_VERSION_2           0x0A
+#define EFI_ACPI_6_3_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK   0x0B
+
+//
+// Error Source structure flags.
+//
+#define EFI_ACPI_6_3_ERROR_SOURCE_FLAG_FIRMWARE_FIRST       (1 << 0)
+#define EFI_ACPI_6_3_ERROR_SOURCE_FLAG_GLOBAL               (1 << 1)
+#define EFI_ACPI_6_3_ERROR_SOURCE_FLAG_GHES_ASSIST          (1 << 2)
+
+///
+/// IA-32 Architecture Machine Check Exception Structure Definition
+///
+typedef struct {
+  UINT16  Type;
+  UINT16  SourceId;
+  UINT8   Reserved0[2];
+  UINT8   Flags;
+  UINT8   Enabled;
+  UINT32  NumberOfRecordsToPreAllocate;
+  UINT32  MaxSectionsPerRecord;
+  UINT64  GlobalCapabilityInitData;
+  UINT64  GlobalControlInitData;
+  UINT8   NumberOfHardwareBanks;
+  UINT8   Reserved1[7];
+} EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_EXCEPTION_STRUCTURE;
+
+///
+/// IA-32 Architecture Machine Check Bank Structure Definition
+///
+typedef struct {
+  UINT8   BankNumber;
+  UINT8   ClearStatusOnInitialization;
+  UINT8   StatusDataFormat;
+  UINT8   Reserved0;
+  UINT32  ControlRegisterMsrAddress;
+  UINT64  ControlInitData;
+  UINT32  StatusRegisterMsrAddress;
+  UINT32  AddressRegisterMsrAddress;
+  UINT32  MiscRegisterMsrAddress;
+} EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_BANK_STRUCTURE;
+
+///
+/// IA-32 Architecture Machine Check Bank Structure MCA data format
+///
+#define EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_IA32      0x00
+#define EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_INTEL64   0x01
+#define EFI_ACPI_6_3_IA32_ARCHITECTURE_MACHINE_CHECK_ERROR_DATA_FORMAT_AMD64     0x02
+
+//
+// Hardware Error Notification types. All other values are reserved
+//
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_POLLED                         0x00
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_EXTERNAL_INTERRUPT             0x01
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_LOCAL_INTERRUPT                0x02
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_SCI                            0x03
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_NMI                            0x04
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_CMCI                           0x05
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_MCE                            0x06
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_GPIO_SIGNAL                    0x07
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEA                      0x08
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_ARMV8_SEI                      0x09
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_GSIV                           0x0A
+#define EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_SOFTWARE_DELEGATED_EXCEPTION   0x0B
+
+///
+/// Hardware Error Notification Configuration Write Enable Structure Definition
+///
+typedef struct {
+  UINT16    Type:1;
+  UINT16    PollInterval:1;
+  UINT16    SwitchToPollingThresholdValue:1;
+  UINT16    SwitchToPollingThresholdWindow:1;
+  UINT16    ErrorThresholdValue:1;
+  UINT16    ErrorThresholdWindow:1;
+  UINT16    Reserved:10;
+} EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE;
+
+///
+/// Hardware Error Notification Structure Definition
+///
+typedef struct {
+  UINT8                                                                          Type;
+  UINT8                                                                          Length;
+  EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_CONFIGURATION_WRITE_ENABLE_STRUCTURE  ConfigurationWriteEnable;
+  UINT32                                                                         PollInterval;
+  UINT32                                                                         Vector;
+  UINT32                                                                         SwitchToPollingThresholdValue;
+  UINT32                                                                         SwitchToPollingThresholdWindow;
+  UINT32                                                                         ErrorThresholdValue;
+  UINT32                                                                         ErrorThresholdWindow;
+} EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE;
+
+///
+/// IA-32 Architecture Corrected Machine Check Structure Definition
+///
+typedef struct {
+  UINT16                                                 Type;
+  UINT16                                                 SourceId;
+  UINT8                                                  Reserved0[2];
+  UINT8                                                  Flags;
+  UINT8                                                  Enabled;
+  UINT32                                                 NumberOfRecordsToPreAllocate;
+  UINT32                                                 MaxSectionsPerRecord;
+  EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE     NotificationStructure;
+  UINT8                                                  NumberOfHardwareBanks;
+  UINT8                                                  Reserved1[3];
+} EFI_ACPI_6_3_IA32_ARCHITECTURE_CORRECTED_MACHINE_CHECK_STRUCTURE;
+
+///
+/// IA-32 Architecture NMI Error Structure Definition
+///
+typedef struct {
+  UINT16  Type;
+  UINT16  SourceId;
+  UINT8   Reserved0[2];
+  UINT32  NumberOfRecordsToPreAllocate;
+  UINT32  MaxSectionsPerRecord;
+  UINT32  MaxRawDataLength;
+} EFI_ACPI_6_3_IA32_ARCHITECTURE_NMI_ERROR_STRUCTURE;
+
+///
+/// PCI Express Root Port AER Structure Definition
+///
+typedef struct {
+  UINT16  Type;
+  UINT16  SourceId;
+  UINT8   Reserved0[2];
+  UINT8   Flags;
+  UINT8   Enabled;
+  UINT32  NumberOfRecordsToPreAllocate;
+  UINT32  MaxSectionsPerRecord;
+  UINT32  Bus;
+  UINT16  Device;
+  UINT16  Function;
+  UINT16  DeviceControl;
+  UINT8   Reserved1[2];
+  UINT32  UncorrectableErrorMask;
+  UINT32  UncorrectableErrorSeverity;
+  UINT32  CorrectableErrorMask;
+  UINT32  AdvancedErrorCapabilitiesAndControl;
+  UINT32  RootErrorCommand;
+} EFI_ACPI_6_3_PCI_EXPRESS_ROOT_PORT_AER_STRUCTURE;
+
+///
+/// PCI Express Device AER Structure Definition
+///
+typedef struct {
+  UINT16  Type;
+  UINT16  SourceId;
+  UINT8   Reserved0[2];
+  UINT8   Flags;
+  UINT8   Enabled;
+  UINT32  NumberOfRecordsToPreAllocate;
+  UINT32  MaxSectionsPerRecord;
+  UINT32  Bus;
+  UINT16  Device;
+  UINT16  Function;
+  UINT16  DeviceControl;
+  UINT8   Reserved1[2];
+  UINT32  UncorrectableErrorMask;
+  UINT32  UncorrectableErrorSeverity;
+  UINT32  CorrectableErrorMask;
+  UINT32  AdvancedErrorCapabilitiesAndControl;
+} EFI_ACPI_6_3_PCI_EXPRESS_DEVICE_AER_STRUCTURE;
+
+///
+/// PCI Express Bridge AER Structure Definition
+///
+typedef struct {
+  UINT16  Type;
+  UINT16  SourceId;
+  UINT8   Reserved0[2];
+  UINT8   Flags;
+  UINT8   Enabled;
+  UINT32  NumberOfRecordsToPreAllocate;
+  UINT32  MaxSectionsPerRecord;
+  UINT32  Bus;
+  UINT16  Device;
+  UINT16  Function;
+  UINT16  DeviceControl;
+  UINT8   Reserved1[2];
+  UINT32  UncorrectableErrorMask;
+  UINT32  UncorrectableErrorSeverity;
+  UINT32  CorrectableErrorMask;
+  UINT32  AdvancedErrorCapabilitiesAndControl;
+  UINT32  SecondaryUncorrectableErrorMask;
+  UINT32  SecondaryUncorrectableErrorSeverity;
+  UINT32  SecondaryAdvancedErrorCapabilitiesAndControl;
+} EFI_ACPI_6_3_PCI_EXPRESS_BRIDGE_AER_STRUCTURE;
+
+///
+/// Generic Hardware Error Source Structure Definition
+///
+typedef struct {
+  UINT16                                                 Type;
+  UINT16                                                 SourceId;
+  UINT16                                                 RelatedSourceId;
+  UINT8                                                  Flags;
+  UINT8                                                  Enabled;
+  UINT32                                                 NumberOfRecordsToPreAllocate;
+  UINT32                                                 MaxSectionsPerRecord;
+  UINT32                                                 MaxRawDataLength;
+  EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE                 ErrorStatusAddress;
+  EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE     NotificationStructure;
+  UINT32                                                 ErrorStatusBlockLength;
+} EFI_ACPI_6_3_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE;
+
+///
+/// Generic Hardware Error Source Version 2 Structure Definition
+///
+typedef struct {
+  UINT16                                                 Type;
+  UINT16                                                 SourceId;
+  UINT16                                                 RelatedSourceId;
+  UINT8                                                  Flags;
+  UINT8                                                  Enabled;
+  UINT32                                                 NumberOfRecordsToPreAllocate;
+  UINT32                                                 MaxSectionsPerRecord;
+  UINT32                                                 MaxRawDataLength;
+  EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE                 ErrorStatusAddress;
+  EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE     NotificationStructure;
+  UINT32                                                 ErrorStatusBlockLength;
+  EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE                 ReadAckRegister;
+  UINT64                                                 ReadAckPreserve;
+  UINT64                                                 ReadAckWrite;
+} EFI_ACPI_6_3_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE;
+
+///
+/// Generic Error Status Definition
+///
+typedef struct {
+  EFI_ACPI_6_3_ERROR_BLOCK_STATUS              BlockStatus;
+  UINT32                                       RawDataOffset;
+  UINT32                                       RawDataLength;
+  UINT32                                       DataLength;
+  UINT32                                       ErrorSeverity;
+} EFI_ACPI_6_3_GENERIC_ERROR_STATUS_STRUCTURE;
+
+///
+/// IA-32 Architecture Deferred Machine Check Structure Definition
+///
+typedef struct {
+  UINT16                                                Type;
+  UINT16                                                SourceId;
+  UINT8                                                 Reserved0[2];
+  UINT8                                                 Flags;
+  UINT8                                                 Enabled;
+  UINT32                                                NumberOfRecordsToPreAllocate;
+  UINT32                                                MaxSectionsPerRecord;
+  EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE    NotificationStructure;
+  UINT8                                                 NumberOfHardwareBanks;
+  UINT8                                                 Reserved1[3];
+} EFI_ACPI_6_3_IA32_ARCHITECTURE_DEFERRED_MACHINE_CHECK_STRUCTURE;;
+
+///
+/// HMAT - Heterogeneous Memory Attribute Table
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT8                       Reserved[4];
+} EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER;
+
+///
+/// HMAT Revision (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION 0x02
+
+///
+/// HMAT types
+///
+#define EFI_ACPI_6_3_HMAT_TYPE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES           0x00
+#define EFI_ACPI_6_3_HMAT_TYPE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO   0x01
+#define EFI_ACPI_6_3_HMAT_TYPE_MEMORY_SIDE_CACHE_INFO                       0x02
+
+///
+/// HMAT Structure Header
+///
+typedef struct {
+  UINT16                        Type;
+  UINT8                         Reserved[2];
+  UINT32                        Length;
+} EFI_ACPI_6_3_HMAT_STRUCTURE_HEADER;
+
+///
+/// Memory Proximity Domain Attributes Structure flags
+///
+typedef struct {
+  UINT16                        InitiatorProximityDomainValid:1;
+  UINT16                        Reserved:15;
+} EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_FLAGS;
+
+///
+/// Memory Proximity Domain Attributes Structure
+///
+typedef struct {
+  UINT16                                                                Type;
+  UINT8                                                                 Reserved[2];
+  UINT32                                                                Length;
+  EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_FLAGS  Flags;
+  UINT8                                                                 Reserved1[2];
+  UINT32                                                                InitiatorProximityDomain;
+  UINT32                                                                MemoryProximityDomain;
+  UINT8                                                                 Reserved2[20];
+} EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES;
+
+///
+/// System Locality Latency and Bandwidth Information Structure flags
+///
+typedef struct {
+  UINT8                         MemoryHierarchy:4;
+  UINT8                         Reserved:4;
+} EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS;
+
+///
+/// System Locality Latency and Bandwidth Information Structure
+///
+typedef struct {
+  UINT16                                                                        Type;
+  UINT8                                                                         Reserved[2];
+  UINT32                                                                        Length;
+  EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO_FLAGS  Flags;
+  UINT8                                                                         DataType;
+  UINT8                                                                         Reserved1[2];
+  UINT32                                                                        NumberOfInitiatorProximityDomains;
+  UINT32                                                                        NumberOfTargetProximityDomains;
+  UINT8                                                                         Reserved2[4];
+  UINT64                                                                        EntryBaseUnit;
+} EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO;
+
+///
+/// Memory Side Cache Information Structure cache attributes
+///
+typedef struct {
+  UINT32                        TotalCacheLevels:4;
+  UINT32                        CacheLevel:4;
+  UINT32                        CacheAssociativity:4;
+  UINT32                        WritePolicy:4;
+  UINT32                        CacheLineSize:16;
+} EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES;
+
+///
+/// Memory Side Cache Information Structure
+///
+typedef struct {
+  UINT16                                                                Type;
+  UINT8                                                                 Reserved[2];
+  UINT32                                                                Length;
+  UINT32                                                                MemoryProximityDomain;
+  UINT8                                                                 Reserved1[4];
+  UINT64                                                                MemorySideCacheSize;
+  EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES   CacheAttributes;
+  UINT8                                                                 Reserved2[2];
+  UINT16                                                                NumberOfSmbiosHandles;
+} EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO;
+
+///
+/// ERST - Error Record Serialization Table
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      SerializationHeaderSize;
+  UINT8                       Reserved0[4];
+  UINT32                      InstructionEntryCount;
+} EFI_ACPI_6_3_ERROR_RECORD_SERIALIZATION_TABLE_HEADER;
+
+///
+/// ERST Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_ERROR_RECORD_SERIALIZATION_TABLE_REVISION 0x01
+
+///
+/// ERST Serialization Actions
+///
+#define EFI_ACPI_6_3_ERST_BEGIN_WRITE_OPERATION                    0x00
+#define EFI_ACPI_6_3_ERST_BEGIN_READ_OPERATION                     0x01
+#define EFI_ACPI_6_3_ERST_BEGIN_CLEAR_OPERATION                    0x02
+#define EFI_ACPI_6_3_ERST_END_OPERATION                            0x03
+#define EFI_ACPI_6_3_ERST_SET_RECORD_OFFSET                        0x04
+#define EFI_ACPI_6_3_ERST_EXECUTE_OPERATION                        0x05
+#define EFI_ACPI_6_3_ERST_CHECK_BUSY_STATUS                        0x06
+#define EFI_ACPI_6_3_ERST_GET_COMMAND_STATUS                       0x07
+#define EFI_ACPI_6_3_ERST_GET_RECORD_IDENTIFIER                    0x08
+#define EFI_ACPI_6_3_ERST_SET_RECORD_IDENTIFIER                    0x09
+#define EFI_ACPI_6_3_ERST_GET_RECORD_COUNT                         0x0A
+#define EFI_ACPI_6_3_ERST_BEGIN_DUMMY_WRITE_OPERATION              0x0B
+#define EFI_ACPI_6_3_ERST_GET_ERROR_LOG_ADDRESS_RANGE              0x0D
+#define EFI_ACPI_6_3_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH       0x0E
+#define EFI_ACPI_6_3_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES   0x0F
+#define EFI_ACPI_6_3_ERST_GET_EXECUTE_OPERATION_TIMINGS            0x10
+
+///
+/// ERST Action Command Status
+///
+#define EFI_ACPI_6_3_ERST_STATUS_SUCCESS                           0x00
+#define EFI_ACPI_6_3_ERST_STATUS_NOT_ENOUGH_SPACE                  0x01
+#define EFI_ACPI_6_3_ERST_STATUS_HARDWARE_NOT_AVAILABLE            0x02
+#define EFI_ACPI_6_3_ERST_STATUS_FAILED                            0x03
+#define EFI_ACPI_6_3_ERST_STATUS_RECORD_STORE_EMPTY                0x04
+#define EFI_ACPI_6_3_ERST_STATUS_RECORD_NOT_FOUND                  0x05
+
+///
+/// ERST Serialization Instructions
+///
+#define EFI_ACPI_6_3_ERST_READ_REGISTER                            0x00
+#define EFI_ACPI_6_3_ERST_READ_REGISTER_VALUE                      0x01
+#define EFI_ACPI_6_3_ERST_WRITE_REGISTER                           0x02
+#define EFI_ACPI_6_3_ERST_WRITE_REGISTER_VALUE                     0x03
+#define EFI_ACPI_6_3_ERST_NOOP                                     0x04
+#define EFI_ACPI_6_3_ERST_LOAD_VAR1                                0x05
+#define EFI_ACPI_6_3_ERST_LOAD_VAR2                                0x06
+#define EFI_ACPI_6_3_ERST_STORE_VAR1                               0x07
+#define EFI_ACPI_6_3_ERST_ADD                                      0x08
+#define EFI_ACPI_6_3_ERST_SUBTRACT                                 0x09
+#define EFI_ACPI_6_3_ERST_ADD_VALUE                                0x0A
+#define EFI_ACPI_6_3_ERST_SUBTRACT_VALUE                           0x0B
+#define EFI_ACPI_6_3_ERST_STALL                                    0x0C
+#define EFI_ACPI_6_3_ERST_STALL_WHILE_TRUE                         0x0D
+#define EFI_ACPI_6_3_ERST_SKIP_NEXT_INSTRUCTION_IF_TRUE            0x0E
+#define EFI_ACPI_6_3_ERST_GOTO                                     0x0F
+#define EFI_ACPI_6_3_ERST_SET_SRC_ADDRESS_BASE                     0x10
+#define EFI_ACPI_6_3_ERST_SET_DST_ADDRESS_BASE                     0x11
+#define EFI_ACPI_6_3_ERST_MOVE_DATA                                0x12
+
+///
+/// ERST Instruction Flags
+///
+#define EFI_ACPI_6_3_ERST_PRESERVE_REGISTER                        0x01
+
+///
+/// ERST Serialization Instruction Entry
+///
+typedef struct {
+  UINT8                                    SerializationAction;
+  UINT8                                    Instruction;
+  UINT8                                    Flags;
+  UINT8                                    Reserved0;
+  EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE   RegisterRegion;
+  UINT64                                   Value;
+  UINT64                                   Mask;
+} EFI_ACPI_6_3_ERST_SERIALIZATION_INSTRUCTION_ENTRY;
+
+///
+/// EINJ - Error Injection Table
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      InjectionHeaderSize;
+  UINT8                       InjectionFlags;
+  UINT8                       Reserved0[3];
+  UINT32                      InjectionEntryCount;
+} EFI_ACPI_6_3_ERROR_INJECTION_TABLE_HEADER;
+
+///
+/// EINJ Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_ERROR_INJECTION_TABLE_REVISION 0x01
+
+///
+/// EINJ Error Injection Actions
+///
+#define EFI_ACPI_6_3_EINJ_BEGIN_INJECTION_OPERATION                0x00
+#define EFI_ACPI_6_3_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE           0x01
+#define EFI_ACPI_6_3_EINJ_SET_ERROR_TYPE                           0x02
+#define EFI_ACPI_6_3_EINJ_GET_ERROR_TYPE                           0x03
+#define EFI_ACPI_6_3_EINJ_END_OPERATION                            0x04
+#define EFI_ACPI_6_3_EINJ_EXECUTE_OPERATION                        0x05
+#define EFI_ACPI_6_3_EINJ_CHECK_BUSY_STATUS                        0x06
+#define EFI_ACPI_6_3_EINJ_GET_COMMAND_STATUS                       0x07
+#define EFI_ACPI_6_3_EINJ_TRIGGER_ERROR                            0xFF
+
+///
+/// EINJ Action Command Status
+///
+#define EFI_ACPI_6_3_EINJ_STATUS_SUCCESS                           0x00
+#define EFI_ACPI_6_3_EINJ_STATUS_UNKNOWN_FAILURE                   0x01
+#define EFI_ACPI_6_3_EINJ_STATUS_INVALID_ACCESS                    0x02
+
+///
+/// EINJ Error Type Definition
+///
+#define EFI_ACPI_6_3_EINJ_ERROR_PROCESSOR_CORRECTABLE                 (1 << 0)
+#define EFI_ACPI_6_3_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_NONFATAL      (1 << 1)
+#define EFI_ACPI_6_3_EINJ_ERROR_PROCESSOR_UNCORRECTABLE_FATAL         (1 << 2)
+#define EFI_ACPI_6_3_EINJ_ERROR_MEMORY_CORRECTABLE                    (1 << 3)
+#define EFI_ACPI_6_3_EINJ_ERROR_MEMORY_UNCORRECTABLE_NONFATAL         (1 << 4)
+#define EFI_ACPI_6_3_EINJ_ERROR_MEMORY_UNCORRECTABLE_FATAL            (1 << 5)
+#define EFI_ACPI_6_3_EINJ_ERROR_PCI_EXPRESS_CORRECTABLE               (1 << 6)
+#define EFI_ACPI_6_3_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_NONFATAL    (1 << 7)
+#define EFI_ACPI_6_3_EINJ_ERROR_PCI_EXPRESS_UNCORRECTABLE_FATAL       (1 << 8)
+#define EFI_ACPI_6_3_EINJ_ERROR_PLATFORM_CORRECTABLE                  (1 << 9)
+#define EFI_ACPI_6_3_EINJ_ERROR_PLATFORM_UNCORRECTABLE_NONFATAL       (1 << 10)
+#define EFI_ACPI_6_3_EINJ_ERROR_PLATFORM_UNCORRECTABLE_FATAL          (1 << 11)
+
+///
+/// EINJ Injection Instructions
+///
+#define EFI_ACPI_6_3_EINJ_READ_REGISTER                            0x00
+#define EFI_ACPI_6_3_EINJ_READ_REGISTER_VALUE                      0x01
+#define EFI_ACPI_6_3_EINJ_WRITE_REGISTER                           0x02
+#define EFI_ACPI_6_3_EINJ_WRITE_REGISTER_VALUE                     0x03
+#define EFI_ACPI_6_3_EINJ_NOOP                                     0x04
+
+///
+/// EINJ Instruction Flags
+///
+#define EFI_ACPI_6_3_EINJ_PRESERVE_REGISTER                        0x01
+
+///
+/// EINJ Injection Instruction Entry
+///
+typedef struct {
+  UINT8                                    InjectionAction;
+  UINT8                                    Instruction;
+  UINT8                                    Flags;
+  UINT8                                    Reserved0;
+  EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE   RegisterRegion;
+  UINT64                                   Value;
+  UINT64                                   Mask;
+} EFI_ACPI_6_3_EINJ_INJECTION_INSTRUCTION_ENTRY;
+
+///
+/// EINJ Trigger Action Table
+///
+typedef struct {
+  UINT32  HeaderSize;
+  UINT32  Revision;
+  UINT32  TableSize;
+  UINT32  EntryCount;
+} EFI_ACPI_6_3_EINJ_TRIGGER_ACTION_TABLE;
+
+///
+/// Platform Communications Channel Table (PCCT)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER Header;
+  UINT32                      Flags;
+  UINT64                      Reserved;
+} EFI_ACPI_6_3_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER;
+
+///
+/// PCCT Version (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_PLATFORM_COMMUNICATION_CHANNEL_TABLE_REVISION 0x02
+
+///
+/// PCCT Global Flags
+///
+#define EFI_ACPI_6_3_PCCT_FLAGS_PLATFORM_INTERRUPT  BIT0
+
+//
+// PCCT Subspace type
+//
+#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_GENERIC                         0x00
+#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_1_HW_REDUCED_COMMUNICATIONS     0x01
+#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_2_HW_REDUCED_COMMUNICATIONS     0x02
+#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_3_EXTENDED_PCC                  0x03
+#define EFI_ACPI_6_3_PCCT_SUBSPACE_TYPE_4_EXTENDED_PCC                  0x04
+
+///
+/// PCC Subspace Structure Header
+///
+typedef struct {
+  UINT8        Type;
+  UINT8        Length;
+} EFI_ACPI_6_3_PCCT_SUBSPACE_HEADER;
+
+///
+/// Generic Communications Subspace Structure
+///
+typedef struct {
+  UINT8                                    Type;
+  UINT8                                    Length;
+  UINT8                                    Reserved[6];
+  UINT64                                   BaseAddress;
+  UINT64                                   AddressLength;
+  EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE   DoorbellRegister;
+  UINT64                                   DoorbellPreserve;
+  UINT64                                   DoorbellWrite;
+  UINT32                                   NominalLatency;
+  UINT32                                   MaximumPeriodicAccessRate;
+  UINT16                                   MinimumRequestTurnaroundTime;
+} EFI_ACPI_6_3_PCCT_SUBSPACE_GENERIC;
+
+///
+/// Generic Communications Channel Shared Memory Region
+///
+
+typedef struct {
+  UINT8                                    Command;
+  UINT8                                    Reserved:7;
+  UINT8                                    NotifyOnCompletion:1;
+} EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND;
+
+typedef struct {
+  UINT8                                    CommandComplete:1;
+  UINT8                                    PlatformInterrupt:1;
+  UINT8                                    Error:1;
+  UINT8                                    PlatformNotification:1;
+  UINT8                                    Reserved:4;
+  UINT8                                    Reserved1;
+} EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;
+
+typedef struct {
+  UINT32                                                    Signature;
+  EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_COMMAND    Command;
+  EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS     Status;
+} EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER;
+
+#define EFI_ACPI_6_3_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_POLARITY    BIT0
+#define EFI_ACPI_6_3_PCCT_SUBSPACE_PLATFORM_INTERRUPT_FLAGS_MODE        BIT1
+
+///
+/// Type 1 HW-Reduced Communications Subspace Structure
+///
+typedef struct {
+  UINT8                                    Type;
+  UINT8                                    Length;
+  UINT32                                   PlatformInterrupt;
+  UINT8                                    PlatformInterruptFlags;
+  UINT8                                    Reserved;
+  UINT64                                   BaseAddress;
+  UINT64                                   AddressLength;
+  EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE   DoorbellRegister;
+  UINT64                                   DoorbellPreserve;
+  UINT64                                   DoorbellWrite;
+  UINT32                                   NominalLatency;
+  UINT32                                   MaximumPeriodicAccessRate;
+  UINT16                                   MinimumRequestTurnaroundTime;
+} EFI_ACPI_6_3_PCCT_SUBSPACE_1_HW_REDUCED_COMMUNICATIONS;
+
+///
+/// Type 2 HW-Reduced Communications Subspace Structure
+///
+typedef struct {
+  UINT8                                    Type;
+  UINT8                                    Length;
+  UINT32                                   PlatformInterrupt;
+  UINT8                                    PlatformInterruptFlags;
+  UINT8                                    Reserved;
+  UINT64                                   BaseAddress;
+  UINT64                                   AddressLength;
+  EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE   DoorbellRegister;
+  UINT64                                   DoorbellPreserve;
+  UINT64                                   DoorbellWrite;
+  UINT32                                   NominalLatency;
+  UINT32                                   MaximumPeriodicAccessRate;
+  UINT16                                   MinimumRequestTurnaroundTime;
+  EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE   PlatformInterruptAckRegister;
+  UINT64                                   PlatformInterruptAckPreserve;
+  UINT64                                   PlatformInterruptAckWrite;
+} EFI_ACPI_6_3_PCCT_SUBSPACE_2_HW_REDUCED_COMMUNICATIONS;
+
+///
+/// Type 3 Extended PCC Subspace Structure
+///
+typedef struct {
+  UINT8                                    Type;
+  UINT8                                    Length;
+  UINT32                                   PlatformInterrupt;
+  UINT8                                    PlatformInterruptFlags;
+  UINT8                                    Reserved;
+  UINT64                                   BaseAddress;
+  UINT32                                   AddressLength;
+  EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE   DoorbellRegister;
+  UINT64                                   DoorbellPreserve;
+  UINT64                                   DoorbellWrite;
+  UINT32                                   NominalLatency;
+  UINT32                                   MaximumPeriodicAccessRate;
+  UINT32                                   MinimumRequestTurnaroundTime;
+  EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE   PlatformInterruptAckRegister;
+  UINT64                                   PlatformInterruptAckPreserve;
+  UINT64                                   PlatformInterruptAckSet;
+  UINT8                                    Reserved1[8];
+  EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE   CommandCompleteCheckRegister;
+  UINT64                                   CommandCompleteCheckMask;
+  EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE   CommandCompleteUpdateRegister;
+  UINT64                                   CommandCompleteUpdatePreserve;
+  UINT64                                   CommandCompleteUpdateSet;
+  EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE   ErrorStatusRegister;
+  UINT64                                   ErrorStatusMask;
+} EFI_ACPI_6_3_PCCT_SUBSPACE_3_EXTENDED_PCC;
+
+///
+/// Type 4 Extended PCC Subspace Structure
+///
+typedef EFI_ACPI_6_3_PCCT_SUBSPACE_3_EXTENDED_PCC EFI_ACPI_6_3_PCCT_SUBSPACE_4_EXTENDED_PCC;
+
+#define EFI_ACPI_6_3_PCCT_MASTER_SLAVE_COMMUNICATIONS_CHANNEL_FLAGS_NOTIFY_ON_COMPLETION BIT0
+
+typedef struct {
+  UINT32                                    Signature;
+  UINT32                                    Flags;
+  UINT32                                    Length;
+  UINT32                                    Command;
+} EFI_ACPI_6_3_PCCT_EXTENDED_PCC_SHARED_MEMORY_REGION_HEADER;
+
+///
+/// Platform Debug Trigger Table (PDTT)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER   Header;
+  UINT8                         TriggerCount;
+  UINT8                         Reserved[3];
+  UINT32                        TriggerIdentifierArrayOffset;
+} EFI_ACPI_6_3_PLATFORM_DEBUG_TRIGGER_TABLE_HEADER;
+
+///
+/// PDTT Revision (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_PLATFORM_DEBUG_TRIGGER_TABLE_REVISION 0x00
+
+///
+/// PDTT Platform Communication Channel Identifier Structure
+///
+typedef struct {
+  UINT16                        SubChannelIdentifer:8;
+  UINT16                        Runtime:1;
+  UINT16                        WaitForCompletion:1;
+  UINT16                        TriggerOrder:1;
+  UINT16                        Reserved:5;
+} EFI_ACPI_6_3_PDTT_PCC_IDENTIFIER;
+
+///
+/// PCC Commands Codes used by Platform Debug Trigger Table
+///
+#define EFI_ACPI_6_3_PDTT_PCC_COMMAND_DOORBELL_ONLY     0x00
+#define EFI_ACPI_6_3_PDTT_PCC_COMMAND_VENDOR_SPECIFIC   0x01
+
+///
+/// PPTT Platform Communication Channel
+///
+typedef EFI_ACPI_6_3_PCCT_GENERIC_SHARED_MEMORY_REGION_HEADER EFI_ACPI_6_3_PDTT_PCC;
+
+///
+/// Processor Properties Topology Table (PPTT)
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER   Header;
+} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER;
+
+///
+/// PPTT Revision (as defined in ACPI 6.3 spec.)
+///
+#define EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION 0x02
+
+///
+/// PPTT types
+///
+#define EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR     0x00
+#define EFI_ACPI_6_3_PPTT_TYPE_CACHE         0x01
+#define EFI_ACPI_6_3_PPTT_TYPE_ID            0x02
+
+///
+/// PPTT Structure Header
+///
+typedef struct {
+  UINT8                         Type;
+  UINT8                         Length;
+  UINT8                         Reserved[2];
+} EFI_ACPI_6_3_PPTT_STRUCTURE_HEADER;
+
+///
+/// For PPTT struct processor flags
+///
+#define EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL          0x0
+#define EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL              0x1
+#define EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID          0x0
+#define EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID            0x1
+#define EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD       0x0
+#define EFI_ACPI_6_3_PPTT_PROCESSOR_IS_THREAD           0x1
+#define EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF              0x0
+#define EFI_ACPI_6_3_PPTT_NODE_IS_LEAF                  0x1
+#define EFI_ACPI_6_3_PPTT_IMPLEMENTATION_NOT_IDENTICAL  0x0
+#define EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL      0x1
+
+///
+/// Processor hierarchy node structure flags
+///
+typedef struct {
+  UINT32                        PhysicalPackage:1;
+  UINT32                        AcpiProcessorIdValid:1;
+  UINT32                        ProcessorIsAThread:1;
+  UINT32                        NodeIsALeaf:1;
+  UINT32                        IdenticalImplementation:1;
+  UINT32                        Reserved:27;
+} EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS;
+
+///
+/// Processor hierarchy node structure
+///
+typedef struct {
+  UINT8                                         Type;
+  UINT8                                         Length;
+  UINT8                                         Reserved[2];
+  EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS   Flags;
+  UINT32                                        Parent;
+  UINT32                                        AcpiProcessorId;
+  UINT32                                        NumberOfPrivateResources;
+} EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR;
+
+///
+/// For PPTT struct cache flags
+///
+#define EFI_ACPI_6_3_PPTT_CACHE_SIZE_INVALID        0x0
+#define EFI_ACPI_6_3_PPTT_CACHE_SIZE_VALID          0x1
+#define EFI_ACPI_6_3_PPTT_NUMBER_OF_SETS_INVALID    0x0
+#define EFI_ACPI_6_3_PPTT_NUMBER_OF_SETS_VALID      0x1
+#define EFI_ACPI_6_3_PPTT_ASSOCIATIVITY_INVALID     0x0
+#define EFI_ACPI_6_3_PPTT_ASSOCIATIVITY_VALID       0x1
+#define EFI_ACPI_6_3_PPTT_ALLOCATION_TYPE_INVALID   0x0
+#define EFI_ACPI_6_3_PPTT_ALLOCATION_TYPE_VALID     0x1
+#define EFI_ACPI_6_3_PPTT_CACHE_TYPE_INVALID        0x0
+#define EFI_ACPI_6_3_PPTT_CACHE_TYPE_VALID          0x1
+#define EFI_ACPI_6_3_PPTT_WRITE_POLICY_INVALID      0x0
+#define EFI_ACPI_6_3_PPTT_WRITE_POLICY_VALID        0x1
+#define EFI_ACPI_6_3_PPTT_LINE_SIZE_INVALID         0x0
+#define EFI_ACPI_6_3_PPTT_LINE_SIZE_VALID           0x1
+
+///
+/// Cache Type Structure flags
+///
+typedef struct {
+  UINT32                        SizePropertyValid:1;
+  UINT32                        NumberOfSetsValid:1;
+  UINT32                        AssociativityValid:1;
+  UINT32                        AllocationTypeValid:1;
+  UINT32                        CacheTypeValid:1;
+  UINT32                        WritePolicyValid:1;
+  UINT32                        LineSizeValid:1;
+  UINT32                        Reserved:25;
+} EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_FLAGS;
+
+///
+/// For cache attributes
+///
+#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ            0x0
+#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_WRITE           0x1
+#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE      0x2
+#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_DATA            0x0
+#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION     0x1
+#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED         0x2
+#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK    0x0
+#define EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_THROUGH 0x1
+
+///
+/// Cache Type Structure cache attributes
+///
+typedef struct {
+  UINT8                         AllocationType:2;
+  UINT8                         CacheType:2;
+  UINT8                         WritePolicy:1;
+  UINT8                         Reserved:3;
+} EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_ATTRIBUTES;
+
+///
+/// Cache Type Structure
+///
+typedef struct {
+  UINT8                                         Type;
+  UINT8                                         Length;
+  UINT8                                         Reserved[2];
+  EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_FLAGS       Flags;
+  UINT32                                        NextLevelOfCache;
+  UINT32                                        Size;
+  UINT32                                        NumberOfSets;
+  UINT8                                         Associativity;
+  EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_ATTRIBUTES  Attributes;
+  UINT16                                        LineSize;
+} EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE;
+
+///
+/// ID structure
+///
+typedef struct {
+  UINT8                         Type;
+  UINT8                         Length;
+  UINT8                         Reserved[2];
+  UINT32                        VendorId;
+  UINT64                        Level1Id;
+  UINT64                        Level2Id;
+  UINT16                        MajorRev;
+  UINT16                        MinorRev;
+  UINT16                        SpinRev;
+} EFI_ACPI_6_3_PPTT_STRUCTURE_ID;
+
+//
+// Known table signatures
+//
+
+///
+/// "RSD PTR " Root System Description Pointer
+///
+#define EFI_ACPI_6_3_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE  SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
+
+///
+/// "APIC" Multiple APIC Description Table
+///
+#define EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('A', 'P', 'I', 'C')
+
+///
+/// "BERT" Boot Error Record Table
+///
+#define EFI_ACPI_6_3_BOOT_ERROR_RECORD_TABLE_SIGNATURE  SIGNATURE_32('B', 'E', 'R', 'T')
+
+///
+/// "BGRT" Boot Graphics Resource Table
+///
+#define EFI_ACPI_6_3_BOOT_GRAPHICS_RESOURCE_TABLE_SIGNATURE  SIGNATURE_32('B', 'G', 'R', 'T')
+
+///
+/// "CDIT" Component Distance Information Table
+///
+#define EFI_ACPI_6_3_COMPONENT_DISTANCE_INFORMATION_TABLE_SIGNATURE  SIGNATURE_32('C', 'D', 'I', 'T')
+
+///
+/// "CPEP" Corrected Platform Error Polling Table
+///
+#define EFI_ACPI_6_3_CORRECTED_PLATFORM_ERROR_POLLING_TABLE_SIGNATURE  SIGNATURE_32('C', 'P', 'E', 'P')
+
+///
+/// "CRAT" Component Resource Attribute Table
+///
+#define EFI_ACPI_6_3_COMPONENT_RESOURCE_ATTRIBUTE_TABLE_SIGNATURE  SIGNATURE_32('C', 'R', 'A', 'T')
+
+///
+/// "DSDT" Differentiated System Description Table
+///
+#define EFI_ACPI_6_3_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('D', 'S', 'D', 'T')
+
+///
+/// "ECDT" Embedded Controller Boot Resources Table
+///
+#define EFI_ACPI_6_3_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE  SIGNATURE_32('E', 'C', 'D', 'T')
+
+///
+/// "EINJ" Error Injection Table
+///
+#define EFI_ACPI_6_3_ERROR_INJECTION_TABLE_SIGNATURE  SIGNATURE_32('E', 'I', 'N', 'J')
+
+///
+/// "ERST" Error Record Serialization Table
+///
+#define EFI_ACPI_6_3_ERROR_RECORD_SERIALIZATION_TABLE_SIGNATURE  SIGNATURE_32('E', 'R', 'S', 'T')
+
+///
+/// "FACP" Fixed ACPI Description Table
+///
+#define EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('F', 'A', 'C', 'P')
+
+///
+/// "FACS" Firmware ACPI Control Structure
+///
+#define EFI_ACPI_6_3_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE  SIGNATURE_32('F', 'A', 'C', 'S')
+
+///
+/// "FPDT" Firmware Performance Data Table
+///
+#define EFI_ACPI_6_3_FIRMWARE_PERFORMANCE_DATA_TABLE_SIGNATURE  SIGNATURE_32('F', 'P', 'D', 'T')
+
+///
+/// "GTDT" Generic Timer Description Table
+///
+#define EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('G', 'T', 'D', 'T')
+
+///
+/// "HEST" Hardware Error Source Table
+///
+#define EFI_ACPI_6_3_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE  SIGNATURE_32('H', 'E', 'S', 'T')
+
+///
+/// "HMAT" Heterogeneous Memory Attribute Table
+///
+#define EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE  SIGNATURE_32('H', 'M', 'A', 'T')
+
+///
+/// "MPST" Memory Power State Table
+///
+#define EFI_ACPI_6_3_MEMORY_POWER_STATE_TABLE_SIGNATURE  SIGNATURE_32('M', 'P', 'S', 'T')
+
+///
+/// "MSCT" Maximum System Characteristics Table
+///
+#define EFI_ACPI_6_3_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE_SIGNATURE  SIGNATURE_32('M', 'S', 'C', 'T')
+
+///
+/// "NFIT" NVDIMM Firmware Interface Table
+///
+#define EFI_ACPI_6_3_NVDIMM_FIRMWARE_INTERFACE_TABLE_STRUCTURE_SIGNATURE  SIGNATURE_32('N', 'F', 'I', 'T')
+
+///
+/// "PDTT" Platform Debug Trigger Table
+///
+#define EFI_ACPI_6_3_PLATFORM_DEBUG_TRIGGER_TABLE_STRUCTURE_SIGNATURE  SIGNATURE_32('P', 'D', 'T', 'T')
+
+///
+/// "PMTT" Platform Memory Topology Table
+///
+#define EFI_ACPI_6_3_PLATFORM_MEMORY_TOPOLOGY_TABLE_SIGNATURE  SIGNATURE_32('P', 'M', 'T', 'T')
+
+///
+/// "PPTT" Processor Properties Topology Table
+///
+#define EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE  SIGNATURE_32('P', 'P', 'T', 'T')
+
+///
+/// "PSDT" Persistent System Description Table
+///
+#define EFI_ACPI_6_3_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('P', 'S', 'D', 'T')
+
+///
+/// "RASF" ACPI RAS Feature Table
+///
+#define EFI_ACPI_6_3_ACPI_RAS_FEATURE_TABLE_SIGNATURE  SIGNATURE_32('R', 'A', 'S', 'F')
+
+///
+/// "RSDT" Root System Description Table
+///
+#define EFI_ACPI_6_3_ROOT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('R', 'S', 'D', 'T')
+
+///
+/// "SBST" Smart Battery Specification Table
+///
+#define EFI_ACPI_6_3_SMART_BATTERY_SPECIFICATION_TABLE_SIGNATURE  SIGNATURE_32('S', 'B', 'S', 'T')
+
+///
+/// "SDEV" Secure DEVices Table
+///
+#define EFI_ACPI_6_3_SECURE_DEVICES_TABLE_SIGNATURE  SIGNATURE_32('S', 'D', 'E', 'V')
+
+///
+/// "SLIT" System Locality Information Table
+///
+#define EFI_ACPI_6_3_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE  SIGNATURE_32('S', 'L', 'I', 'T')
+
+///
+/// "SRAT" System Resource Affinity Table
+///
+#define EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE  SIGNATURE_32('S', 'R', 'A', 'T')
+
+///
+/// "SSDT" Secondary System Description Table
+///
+#define EFI_ACPI_6_3_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('S', 'S', 'D', 'T')
+
+///
+/// "XSDT" Extended System Description Table
+///
+#define EFI_ACPI_6_3_EXTENDED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('X', 'S', 'D', 'T')
+
+///
+/// "BOOT" MS Simple Boot Spec
+///
+#define EFI_ACPI_6_3_SIMPLE_BOOT_FLAG_TABLE_SIGNATURE  SIGNATURE_32('B', 'O', 'O', 'T')
+
+///
+/// "CSRT" MS Core System Resource Table
+///
+#define EFI_ACPI_6_3_CORE_SYSTEM_RESOURCE_TABLE_SIGNATURE  SIGNATURE_32('C', 'S', 'R', 'T')
+
+///
+/// "DBG2" MS Debug Port 2 Spec
+///
+#define EFI_ACPI_6_3_DEBUG_PORT_2_TABLE_SIGNATURE  SIGNATURE_32('D', 'B', 'G', '2')
+
+///
+/// "DBGP" MS Debug Port Spec
+///
+#define EFI_ACPI_6_3_DEBUG_PORT_TABLE_SIGNATURE  SIGNATURE_32('D', 'B', 'G', 'P')
+
+///
+/// "DMAR" DMA Remapping Table
+///
+#define EFI_ACPI_6_3_DMA_REMAPPING_TABLE_SIGNATURE  SIGNATURE_32('D', 'M', 'A', 'R')
+
+///
+/// "DPPT" DMA Protection Policy Table
+///
+#define EFI_ACPI_6_3_DMA_PROTECTION_POLICY_TABLE_SIGNATURE  SIGNATURE_32('D', 'P', 'P', 'T')
+
+///
+/// "DRTM" Dynamic Root of Trust for Measurement Table
+///
+#define EFI_ACPI_6_3_DYNAMIC_ROOT_OF_TRUST_FOR_MEASUREMENT_TABLE_SIGNATURE  SIGNATURE_32('D', 'R', 'T', 'M')
+
+///
+/// "ETDT" Event Timer Description Table
+///
+#define EFI_ACPI_6_3_EVENT_TIMER_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('E', 'T', 'D', 'T')
+
+///
+/// "HPET" IA-PC High Precision Event Timer Table
+///
+#define EFI_ACPI_6_3_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE  SIGNATURE_32('H', 'P', 'E', 'T')
+
+///
+/// "iBFT" iSCSI Boot Firmware Table
+///
+#define EFI_ACPI_6_3_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE  SIGNATURE_32('i', 'B', 'F', 'T')
+
+///
+/// "IORT" I/O Remapping Table
+///
+#define EFI_ACPI_6_3_IO_REMAPPING_TABLE_SIGNATURE  SIGNATURE_32('I', 'O', 'R', 'T')
+
+///
+/// "IVRS" I/O Virtualization Reporting Structure
+///
+#define EFI_ACPI_6_3_IO_VIRTUALIZATION_REPORTING_STRUCTURE_SIGNATURE  SIGNATURE_32('I', 'V', 'R', 'S')
+
+///
+/// "LPIT" Low Power Idle Table
+///
+#define EFI_ACPI_6_3_LOW_POWER_IDLE_TABLE_STRUCTURE_SIGNATURE  SIGNATURE_32('L', 'P', 'I', 'T')
+
+///
+/// "MCFG" PCI Express Memory Mapped Configuration Space Base Address Description Table
+///
+#define EFI_ACPI_6_3_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('M', 'C', 'F', 'G')
+
+///
+/// "MCHI" Management Controller Host Interface Table
+///
+#define EFI_ACPI_6_3_MANAGEMENT_CONTROLLER_HOST_INTERFACE_TABLE_SIGNATURE  SIGNATURE_32('M', 'C', 'H', 'I')
+
+///
+/// "MSDM" MS Data Management Table
+///
+#define EFI_ACPI_6_3_DATA_MANAGEMENT_TABLE_SIGNATURE  SIGNATURE_32('M', 'S', 'D', 'M')
+
+///
+/// "PCCT" Platform Communications Channel Table
+///
+#define EFI_ACPI_6_3_PLATFORM_COMMUNICATIONS_CHANNEL_TABLE_SIGNATURE  SIGNATURE_32('P', 'C', 'C', 'T')
+
+///
+/// "SDEI" Software Delegated Exceptions Interface Table
+///
+#define EFI_ACPI_6_3_SOFTWARE_DELEGATED_EXCEPTIONS_INTERFACE_TABLE_SIGNATURE  SIGNATURE_32('S', 'D', 'E', 'I')
+
+///
+/// "SLIC" MS Software Licensing Table Specification
+///
+#define EFI_ACPI_6_3_SOFTWARE_LICENSING_TABLE_SIGNATURE  SIGNATURE_32('S', 'L', 'I', 'C')
+
+///
+/// "SPCR" Serial Port Concole Redirection Table
+///
+#define EFI_ACPI_6_3_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE  SIGNATURE_32('S', 'P', 'C', 'R')
+
+///
+/// "SPMI" Server Platform Management Interface Table
+///
+#define EFI_ACPI_6_3_SERVER_PLATFORM_MANAGEMENT_INTERFACE_TABLE_SIGNATURE  SIGNATURE_32('S', 'P', 'M', 'I')
+
+///
+/// "STAO" _STA Override Table
+///
+#define EFI_ACPI_6_3_STA_OVERRIDE_TABLE_SIGNATURE  SIGNATURE_32('S', 'T', 'A', 'O')
+
+///
+/// "TCPA" Trusted Computing Platform Alliance Capabilities Table
+///
+#define EFI_ACPI_6_3_TRUSTED_COMPUTING_PLATFORM_ALLIANCE_CAPABILITIES_TABLE_SIGNATURE  SIGNATURE_32('T', 'C', 'P', 'A')
+
+///
+/// "TPM2" Trusted Computing Platform 1 Table
+///
+#define EFI_ACPI_6_3_TRUSTED_COMPUTING_PLATFORM_2_TABLE_SIGNATURE  SIGNATURE_32('T', 'P', 'M', '2')
+
+///
+/// "UEFI" UEFI ACPI Data Table
+///
+#define EFI_ACPI_6_3_UEFI_ACPI_DATA_TABLE_SIGNATURE  SIGNATURE_32('U', 'E', 'F', 'I')
+
+///
+/// "WAET" Windows ACPI Emulated Devices Table
+///
+#define EFI_ACPI_6_3_WINDOWS_ACPI_EMULATED_DEVICES_TABLE_SIGNATURE  SIGNATURE_32('W', 'A', 'E', 'T')
+
+///
+/// "WDAT" Watchdog Action Table
+///
+#define EFI_ACPI_6_3_WATCHDOG_ACTION_TABLE_SIGNATURE  SIGNATURE_32('W', 'D', 'A', 'T')
+
+///
+/// "WDRT" Watchdog Resource Table
+///
+#define EFI_ACPI_6_3_WATCHDOG_RESOURCE_TABLE_SIGNATURE  SIGNATURE_32('W', 'D', 'R', 'T')
+
+///
+/// "WPBT" MS Platform Binary Table
+///
+#define EFI_ACPI_6_3_PLATFORM_BINARY_TABLE_SIGNATURE  SIGNATURE_32('W', 'P', 'B', 'T')
+
+///
+/// "WSMT" Windows SMM Security Mitigation Table
+///
+#define EFI_ACPI_6_3_WINDOWS_SMM_SECURITY_MITIGATION_TABLE_SIGNATURE  SIGNATURE_32('W', 'S', 'M', 'T')
+
+///
+/// "XENV" Xen Project Table
+///
+#define EFI_ACPI_6_3_XEN_PROJECT_TABLE_SIGNATURE  SIGNATURE_32('X', 'E', 'N', 'V')
+
+#pragma pack()
+
+#endif
diff --git a/MdePkg/Include/IndustryStandard/AcpiAml.h b/MdePkg/Include/IndustryStandard/AcpiAml.h
index 19d9684943eb..cba5848cb400 100644
--- a/MdePkg/Include/IndustryStandard/AcpiAml.h
+++ b/MdePkg/Include/IndustryStandard/AcpiAml.h
@@ -2,13 +2,8 @@
   This file contains AML code definition in the latest ACPI spec.
 
   Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2019, ARM Limited. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -36,6 +31,7 @@
 #define AML_PACKAGE_OP               0x12
 #define AML_VAR_PACKAGE_OP           0x13
 #define AML_METHOD_OP                0x14
+#define AML_EXTERNAL_OP              0x15
 #define AML_DUAL_NAME_PREFIX         0x2e
 #define AML_MULTI_NAME_PREFIX        0x2f
 #define AML_NAME_CHAR_A              0x41
@@ -172,4 +168,12 @@
 #define AML_EXT_BANK_FIELD_OP        0x87
 #define AML_EXT_DATA_REGION_OP       0x88
 
+//
+// FieldElement OpCode
+//
+#define AML_FIELD_RESERVED_OP        0x00
+#define AML_FIELD_ACCESS_OP          0x01
+#define AML_FIELD_CONNECTION_OP      0x02
+#define AML_FIELD_EXT_ACCESS_OP      0x03
+
 #endif
diff --git a/MdePkg/Include/IndustryStandard/AlertStandardFormatTable.h b/MdePkg/Include/IndustryStandard/AlertStandardFormatTable.h
index e7658541a3e4..8bb3ca66504b 100644
--- a/MdePkg/Include/IndustryStandard/AlertStandardFormatTable.h
+++ b/MdePkg/Include/IndustryStandard/AlertStandardFormatTable.h
@@ -1,14 +1,8 @@
-/** @file   
+/** @file
   ACPI Alert Standard Format Description Table ASF! as described in the ASF2.0 Specification
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
 #ifndef _ALERT_STANDARD_FORMAT_TABLE_H_
@@ -31,7 +25,7 @@ typedef struct {
 } EFI_ACPI_ASF_RECORD_HEADER;
 
 ///
-/// This structure contains information that identifies the system's type 
+/// This structure contains information that identifies the system's type
 /// and configuration
 ///
 typedef struct {
@@ -84,7 +78,7 @@ typedef struct {
   UINT8                                DeviceAddress;
   UINT8                                Command;
   UINT8                                DataValue;
-} EFI_ACPI_ASF_CONTROLDATA;       
+} EFI_ACPI_ASF_CONTROLDATA;
 
 ///
 /// Alert Remote Control System Actions
diff --git a/MdePkg/Include/IndustryStandard/Atapi.h b/MdePkg/Include/IndustryStandard/Atapi.h
index cb1fae429f09..a886f59e3cb5 100644
--- a/MdePkg/Include/IndustryStandard/Atapi.h
+++ b/MdePkg/Include/IndustryStandard/Atapi.h
@@ -2,14 +2,8 @@
   This file contains just some basic definitions that are needed by drivers
   that dealing with ATA/ATAPI interface.
 
-Copyright (c) 2007 - 2016, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -21,59 +15,59 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 ///
 /// ATA5_IDENTIFY_DATA is defined in ATA-5.
 /// (This structure is provided mainly for backward-compatibility support.
-/// Old drivers may reference fields that are marked "obsolete" in 
-/// ATA_IDENTIFY_DATA, which currently conforms to ATA-8.) 
+/// Old drivers may reference fields that are marked "obsolete" in
+/// ATA_IDENTIFY_DATA, which currently conforms to ATA-8.)
 ///
-typedef struct {    
+typedef struct {
   UINT16  config;             ///< General Configuration.
   UINT16  cylinders;          ///< Number of Cylinders.
-  UINT16  reserved_2; 
-  UINT16  heads;              ///< Number of logical heads. 
-  UINT16  vendor_data1; 
-  UINT16  vendor_data2; 
-  UINT16  sectors_per_track; 
-  UINT16  vendor_specific_7_9[3]; 
-  CHAR8   SerialNo[20];       ///< ASCII  
-  UINT16  vendor_specific_20_21[2];  
-  UINT16  ecc_bytes_available;    
-  CHAR8   FirmwareVer[8];     ///< ASCII  
-  CHAR8   ModelName[40];      ///< ASCII    
-  UINT16  multi_sector_cmd_max_sct_cnt; 
-  UINT16  reserved_48; 
-  UINT16  capabilities; 
-  UINT16  reserved_50;     
-  UINT16  pio_cycle_timing;    
-  UINT16  reserved_52;             
-  UINT16  field_validity;     
-  UINT16  current_cylinders; 
-  UINT16  current_heads; 
-  UINT16  current_sectors;    
-  UINT16  CurrentCapacityLsb; 
-  UINT16  CurrentCapacityMsb;     
-  UINT16  reserved_59;     
-  UINT16  user_addressable_sectors_lo; 
-  UINT16  user_addressable_sectors_hi; 
-  UINT16  reserved_62;     
-  UINT16  multi_word_dma_mode;    
-  UINT16  advanced_pio_modes; 
-  UINT16  min_multi_word_dma_cycle_time; 
-  UINT16  rec_multi_word_dma_cycle_time; 
-  UINT16  min_pio_cycle_time_without_flow_control; 
-  UINT16  min_pio_cycle_time_with_flow_control; 
-  UINT16  reserved_69_79[11];     
-  UINT16  major_version_no; 
-  UINT16  minor_version_no; 
-  UINT16  command_set_supported_82;    ///< word 82 
-  UINT16  command_set_supported_83;    ///< word 83 
-  UINT16  command_set_feature_extn;    ///< word 84 
-  UINT16  command_set_feature_enb_85;  ///< word 85 
-  UINT16  command_set_feature_enb_86;  ///< word 86 
-  UINT16  command_set_feature_default; ///< word 87 
-  UINT16  ultra_dma_mode;              ///< word 88 
-  UINT16  reserved_89_127[39]; 
-  UINT16  security_status; 
-  UINT16  vendor_data_129_159[31]; 
-  UINT16  reserved_160_255[96]; 
+  UINT16  reserved_2;
+  UINT16  heads;              ///< Number of logical heads.
+  UINT16  vendor_data1;
+  UINT16  vendor_data2;
+  UINT16  sectors_per_track;
+  UINT16  vendor_specific_7_9[3];
+  CHAR8   SerialNo[20];       ///< ASCII
+  UINT16  vendor_specific_20_21[2];
+  UINT16  ecc_bytes_available;
+  CHAR8   FirmwareVer[8];     ///< ASCII
+  CHAR8   ModelName[40];      ///< ASCII
+  UINT16  multi_sector_cmd_max_sct_cnt;
+  UINT16  reserved_48;
+  UINT16  capabilities;
+  UINT16  reserved_50;
+  UINT16  pio_cycle_timing;
+  UINT16  reserved_52;
+  UINT16  field_validity;
+  UINT16  current_cylinders;
+  UINT16  current_heads;
+  UINT16  current_sectors;
+  UINT16  CurrentCapacityLsb;
+  UINT16  CurrentCapacityMsb;
+  UINT16  reserved_59;
+  UINT16  user_addressable_sectors_lo;
+  UINT16  user_addressable_sectors_hi;
+  UINT16  reserved_62;
+  UINT16  multi_word_dma_mode;
+  UINT16  advanced_pio_modes;
+  UINT16  min_multi_word_dma_cycle_time;
+  UINT16  rec_multi_word_dma_cycle_time;
+  UINT16  min_pio_cycle_time_without_flow_control;
+  UINT16  min_pio_cycle_time_with_flow_control;
+  UINT16  reserved_69_79[11];
+  UINT16  major_version_no;
+  UINT16  minor_version_no;
+  UINT16  command_set_supported_82;    ///< word 82
+  UINT16  command_set_supported_83;    ///< word 83
+  UINT16  command_set_feature_extn;    ///< word 84
+  UINT16  command_set_feature_enb_85;  ///< word 85
+  UINT16  command_set_feature_enb_86;  ///< word 86
+  UINT16  command_set_feature_default; ///< word 87
+  UINT16  ultra_dma_mode;              ///< word 88
+  UINT16  reserved_89_127[39];
+  UINT16  security_status;
+  UINT16  vendor_data_129_159[31];
+  UINT16  reserved_160_255[96];
 } ATA5_IDENTIFY_DATA;
 
 ///
@@ -86,50 +80,50 @@ typedef struct {
   UINT16  obsolete_1;
   UINT16  specific_config;                         ///< Specific Configuration.
   UINT16  obsolete_3;
-  UINT16  retired_4_5[2]; 
+  UINT16  retired_4_5[2];
   UINT16  obsolete_6;
   UINT16  cfa_reserved_7_8[2];
-  UINT16  retired_9; 
+  UINT16  retired_9;
   CHAR8   SerialNo[20];                            ///< word 10~19
-  UINT16  retired_20_21[2];  
-  UINT16  obsolete_22;    
+  UINT16  retired_20_21[2];
+  UINT16  obsolete_22;
   CHAR8   FirmwareVer[8];                          ///< word 23~26
   CHAR8   ModelName[40];                           ///< word 27~46
   UINT16  multi_sector_cmd_max_sct_cnt;
-  UINT16  trusted_computing_support; 
+  UINT16  trusted_computing_support;
   UINT16  capabilities_49;
   UINT16  capabilities_50;
-  UINT16  obsolete_51_52[2];           
-  UINT16  field_validity;     
-  UINT16  obsolete_54_58[5];     
+  UINT16  obsolete_51_52[2];
+  UINT16  field_validity;
+  UINT16  obsolete_54_58[5];
   UINT16  multi_sector_setting;
-  UINT16  user_addressable_sectors_lo; 
-  UINT16  user_addressable_sectors_hi; 
-  UINT16  obsolete_62;     
-  UINT16  multi_word_dma_mode;    
-  UINT16  advanced_pio_modes; 
-  UINT16  min_multi_word_dma_cycle_time; 
-  UINT16  rec_multi_word_dma_cycle_time; 
-  UINT16  min_pio_cycle_time_without_flow_control; 
-  UINT16  min_pio_cycle_time_with_flow_control; 
+  UINT16  user_addressable_sectors_lo;
+  UINT16  user_addressable_sectors_hi;
+  UINT16  obsolete_62;
+  UINT16  multi_word_dma_mode;
+  UINT16  advanced_pio_modes;
+  UINT16  min_multi_word_dma_cycle_time;
+  UINT16  rec_multi_word_dma_cycle_time;
+  UINT16  min_pio_cycle_time_without_flow_control;
+  UINT16  min_pio_cycle_time_with_flow_control;
   UINT16  additional_supported;                    ///< word 69
   UINT16  reserved_70;
   UINT16  reserved_71_74[4];                       ///< Reserved for IDENTIFY PACKET DEVICE cmd.
-  UINT16  queue_depth;     
+  UINT16  queue_depth;
   UINT16  serial_ata_capabilities;
   UINT16  reserved_77;                             ///< Reserved for Serial ATA
   UINT16  serial_ata_features_supported;
   UINT16  serial_ata_features_enabled;
-  UINT16  major_version_no; 
-  UINT16  minor_version_no; 
+  UINT16  major_version_no;
+  UINT16  minor_version_no;
   UINT16  command_set_supported_82;                ///< word 82
   UINT16  command_set_supported_83;                ///< word 83
   UINT16  command_set_feature_extn;                ///< word 84
   UINT16  command_set_feature_enb_85;              ///< word 85
   UINT16  command_set_feature_enb_86;              ///< word 86
   UINT16  command_set_feature_default;             ///< word 87
-  UINT16  ultra_dma_mode;                          ///< word 88 
-  UINT16  time_for_security_erase_unit; 
+  UINT16  ultra_dma_mode;                          ///< word 88
+  UINT16  time_for_security_erase_unit;
   UINT16  time_for_enhanced_security_erase_unit;
   UINT16  advanced_power_management_level;
   UINT16  master_password_identifier;
@@ -154,7 +148,7 @@ typedef struct {
   UINT16  reserved_121_126[6];
   UINT16  obsolete_127;
   UINT16  security_status;                         ///< word 128
-  UINT16  vendor_specific_129_159[31]; 
+  UINT16  vendor_specific_129_159[31];
   UINT16  cfa_power_mode;                          ///< word 160
   UINT16  reserved_for_compactflash_161_167[7];
   UINT16  device_nominal_form_factor;
@@ -239,7 +233,7 @@ typedef struct {
   UINT16  reserved_95_107[13];
   UINT16  world_wide_name[4];                      ///< word 108~111
   UINT16  reserved_for_128bit_wwn_112_115[4];
-  UINT16  reserved_116_118[3];  
+  UINT16  reserved_116_118[3];
   UINT16  command_and_feature_sets_supported;      ///< word 119
   UINT16  command_and_feature_sets_supported_enabled;
   UINT16  reserved_121_124[4];
@@ -458,7 +452,7 @@ typedef struct {
 
 ///
 /// ATAPI_PACKET_COMMAND is not defined in the ATA specification.
-/// We add it here for the convenience of ATA/ATAPI module writers. 
+/// We add it here for the convenience of ATA/ATAPI module writers.
 ///
 typedef union {
   UINT16                    Data16[6];
@@ -477,7 +471,7 @@ typedef union {
 #define ATAPI_MAX_DMA_CMD_SECTORS                       0x100
 
 //  ATA/ATAPI Signature equates
-#define ATA_SIGNATURE                                   0x0101       ///< defined in ACS-3  
+#define ATA_SIGNATURE                                   0x0101       ///< defined in ACS-3
 #define ATAPI_SIGNATURE                                 0xeb14       ///< defined in ACS-3
 #define ATAPI_SIGNATURE_32                              0xeb140101   ///< defined in ACS-3
 
@@ -490,42 +484,42 @@ typedef union {
 //
 // ATA Packet Command Code
 //
-#define ATA_CMD_FORMAT_UNIT                             0x04   ///< defined in ATAPI Removable Rewritable Media Devcies
+#define ATA_CMD_FORMAT_UNIT                             0x04   ///< defined in ATAPI Removable Rewritable Media Devices
 #define ATA_CMD_SOFT_RESET                              0x08   ///< defined from ATA-3
 #define ATA_CMD_PACKET                                  0xA0   ///< defined from ATA-3
 #define ATA_CMD_IDENTIFY_DEVICE                         0xA1   ///< defined from ATA-3
 #define ATA_CMD_SERVICE                                 0xA2   ///< defined from ATA-3
 #define ATA_CMD_TEST_UNIT_READY                         0x00   ///< defined from ATA-1
 #define ATA_CMD_REQUEST_SENSE                           0x03   ///< defined from ATA-4
-#define ATA_CMD_INQUIRY                                 0x12   ///< defined in ATAPI Removable Rewritable Media Devcies
-#define ATA_CMD_READ_FORMAT_CAPACITY                    0x23   ///< defined in ATAPI Removable Rewritable Media Devcies
-#define ATA_CMD_READ_CAPACITY                           0x25   ///< defined in ATAPI Removable Rewritable Media Devcies
-#define ATA_CMD_READ_10                                 0x28   ///< defined in ATAPI Removable Rewritable Media Devcies
-#define ATA_CMD_WRITE_10                                0x2A   ///< defined in ATAPI Removable Rewritable Media Devcies
-#define ATA_CMD_ATAPI_SEEK                              0x2B   ///< defined in ATAPI Removable Rewritable Media Devcies
-#define ATA_CMD_WRITE_AND_VERIFY                        0x2E   ///< defined in ATAPI Removable Rewritable Media Devcies
-#define ATA_CMD_VERIFY                                  0x2F   ///< defined in ATAPI Removable Rewritable Media Devcies
-#define ATA_CMD_READ_12                                 0xA8   ///< defined in ATAPI Removable Rewritable Media Devcies
-#define ATA_CMD_WRITE_12                                0xAA   ///< defined in ATAPI Removable Rewritable Media Devcies
-#define ATA_CMD_START_STOP_UNIT                         0x1B   ///< defined in ATAPI Removable Rewritable Media Devcies
-#define ATA_CMD_PREVENT_ALLOW_MEDIA_REMOVAL             0x1E   ///< defined in ATAPI Removable Rewritable Media Devcies
-#define ATA_CMD_MODE_SELECT                             0x55   ///< defined in ATAPI Removable Rewritable Media Devcies
-
-#define ATA_CMD_MODE_SENSE                              0x5A   ///< defined in ATAPI Removable Rewritable Media Devcies
-    #define ATA_PAGE_CODE_READ_WRITE_ERROR                  0x01   ///< defined in ATAPI Removable Rewritable Media Devcies
-    #define ATA_PAGE_CODE_CACHING_PAGE                      0x08   ///< defined in ATAPI Removable Rewritable Media Devcies
-    #define ATA_PAGE_CODE_REMOVABLE_BLOCK_CAPABILITIES      0x1B   ///< defined in ATAPI Removable Rewritable Media Devcies
-    #define ATA_PAGE_CODE_TIMER_PROTECT_PAGE                0x1C   ///< defined in ATAPI Removable Rewritable Media Devcies
-    #define ATA_PAGE_CODE_RETURN_ALL_PAGES                  0x3F   ///< defined in ATAPI Removable Rewritable Media Devcies
+#define ATA_CMD_INQUIRY                                 0x12   ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_READ_FORMAT_CAPACITY                    0x23   ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_READ_CAPACITY                           0x25   ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_READ_10                                 0x28   ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_WRITE_10                                0x2A   ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_ATAPI_SEEK                              0x2B   ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_WRITE_AND_VERIFY                        0x2E   ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_VERIFY                                  0x2F   ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_READ_12                                 0xA8   ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_WRITE_12                                0xAA   ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_START_STOP_UNIT                         0x1B   ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_PREVENT_ALLOW_MEDIA_REMOVAL             0x1E   ///< defined in ATAPI Removable Rewritable Media Devices
+#define ATA_CMD_MODE_SELECT                             0x55   ///< defined in ATAPI Removable Rewritable Media Devices
+
+#define ATA_CMD_MODE_SENSE                              0x5A   ///< defined in ATAPI Removable Rewritable Media Devices
+    #define ATA_PAGE_CODE_READ_WRITE_ERROR                  0x01   ///< defined in ATAPI Removable Rewritable Media Devices
+    #define ATA_PAGE_CODE_CACHING_PAGE                      0x08   ///< defined in ATAPI Removable Rewritable Media Devices
+    #define ATA_PAGE_CODE_REMOVABLE_BLOCK_CAPABILITIES      0x1B   ///< defined in ATAPI Removable Rewritable Media Devices
+    #define ATA_PAGE_CODE_TIMER_PROTECT_PAGE                0x1C   ///< defined in ATAPI Removable Rewritable Media Devices
+    #define ATA_PAGE_CODE_RETURN_ALL_PAGES                  0x3F   ///< defined in ATAPI Removable Rewritable Media Devices
 
 #define ATA_CMD_GET_CONFIGURATION                       0x46   ///< defined in ATAPI Multimedia Devices
    #define ATA_GCCD_RT_FIELD_VALUE_ALL                      0x00   ///< defined in ATAPI Multimedia Devices
    #define ATA_GCCD_RT_FIELD_VALUE_CURRENT                  0x01   ///< defined in ATAPI Multimedia Devices
-   #define ATA_GCCD_RT_FIELD_VALUE_SINGLE                   0x02   ///< defined in ATAPI Multimedia Devices 
-   #define ATA_GCCD_RT_FIELD_VALUE_RESERVED                 0x03   ///< defined in ATAPI Multimedia Devices 
-   
+   #define ATA_GCCD_RT_FIELD_VALUE_SINGLE                   0x02   ///< defined in ATAPI Multimedia Devices
+   #define ATA_GCCD_RT_FIELD_VALUE_RESERVED                 0x03   ///< defined in ATAPI Multimedia Devices
+
    #define ATA_FEATURE_LIST_PROFILE_LIST                    0x0000   ///< defined in ATAPI Multimedia Devices
-   #define ATA_FEATURE_LIST_CORE                            0x0001   ///< defined in ATAPI Multimedia Devices   
+   #define ATA_FEATURE_LIST_CORE                            0x0001   ///< defined in ATAPI Multimedia Devices
    #define ATA_FEATURE_LIST_MORPHING                        0x0002   ///< defined in ATAPI Multimedia Devices
    #define ATA_FEATURE_LIST_REMOVEABLE_MEDIUM               0x0003   ///< defined in ATAPI Multimedia Devices
    #define ATA_FEATURE_LIST_WRITE_PROTECT                   0x0004   ///< defined in ATAPI Multimedia Devices
@@ -549,33 +543,33 @@ typedef union {
 //
 #define ATA_CMD_IDENTIFY_DRIVE                          0xec   ///< defined from ATA-3
 #define ATA_CMD_READ_BUFFER                             0xe4   ///< defined from ATA-1
-#define ATA_CMD_READ_SECTORS                            0x20   ///< defined from ATA-1     
+#define ATA_CMD_READ_SECTORS                            0x20   ///< defined from ATA-1
 #define ATA_CMD_READ_SECTORS_WITH_RETRY                 0x21   ///< defined from ATA-1, obsoleted from ATA-5
 #define ATA_CMD_READ_LONG                               0x22   ///< defined from ATA-1, obsoleted from ATA-5
 #define ATA_CMD_READ_LONG_WITH_RETRY                    0x23   ///< defined from ATA-1, obsoleted from ATA-5
 #define ATA_CMD_READ_SECTORS_EXT                        0x24   ///< defined from ATA-6
-#define ATA_CMD_READ_MULTIPLE                           0xc4   ///< defined in ACS-3  
-#define ATA_CMD_READ_MULTIPLE_EXT                       0x29   ///< defined in ACS-3  
-#define ATA_CMD_READ_LOG_EXT                            0x2f   ///< defined in ACS-3  
+#define ATA_CMD_READ_MULTIPLE                           0xc4   ///< defined in ACS-3
+#define ATA_CMD_READ_MULTIPLE_EXT                       0x29   ///< defined in ACS-3
+#define ATA_CMD_READ_LOG_EXT                            0x2f   ///< defined in ACS-3
 
 //
 // Class 2: PIO Data-Out Commands
 //
 #define ATA_CMD_FORMAT_TRACK                            0x50  ///< defined from ATA-1, obsoleted from ATA-4
-#define ATA_CMD_WRITE_BUFFER                            0xe8  ///< defined from ATA-1  
+#define ATA_CMD_WRITE_BUFFER                            0xe8  ///< defined from ATA-1
 #define ATA_CMD_WRITE_SECTORS                           0x30  ///< defined from ATA-1
 #define ATA_CMD_WRITE_SECTORS_WITH_RETRY                0x31  ///< defined from ATA-1, obsoleted from ATA-5
 #define ATA_CMD_WRITE_LONG                              0x32  ///< defined from ATA-1, obsoleted from ATA-5
 #define ATA_CMD_WRITE_LONG_WITH_RETRY                   0x33  ///< defined from ATA-1, obsoleted from ATA-5
 #define ATA_CMD_WRITE_VERIFY                            0x3c  ///< defined from ATA-1, obsoleted from ATA-5
 #define ATA_CMD_WRITE_SECTORS_EXT                       0x34  ///< defined from ATA-6
-#define ATA_CMD_WRITE_MULTIPLE                          0xc5  ///< defined in ACS-3  
-#define ATA_CMD_WRITE_MULTIPLE_EXT                      0x39  ///< defined in ACS-3  
+#define ATA_CMD_WRITE_MULTIPLE                          0xc5  ///< defined in ACS-3
+#define ATA_CMD_WRITE_MULTIPLE_EXT                      0x39  ///< defined in ACS-3
 
 //
 // Class 3 No Data Command
 //
-#define ATA_CMD_ACK_MEDIA_CHANGE                        0xdb  ///< defined from ATA-1, obsoleted from ATA-5 
+#define ATA_CMD_ACK_MEDIA_CHANGE                        0xdb  ///< defined from ATA-1, obsoleted from ATA-5
 #define ATA_CMD_BOOT_POST_BOOT                          0xdc  ///< defined from ATA-1, obsoleted from ATA-3
 #define ATA_CMD_BOOT_PRE_BOOT                           0xdd  ///< defined from ATA-1, obsoleted from ATA-3
 #define ATA_CMD_CHECK_POWER_MODE                        0x98  ///< defined from ATA-1, obsoleted from ATA-4
@@ -599,39 +593,39 @@ typedef union {
 #define ATA_CMD_STANDBY_ALIAS                           0xe2  ///< defined from ATA-1
 #define ATA_CMD_STANDBY_IMMEDIATE                       0x94  ///< defined from ATA-1, obsoleted from ATA-4
 #define ATA_CMD_STANDBY_IMMEDIATE_ALIAS                 0xe0  ///< defined from ATA-1
-#define ATA_CMD_SLEEP                                   0xe6  ///< defined in ACS-3  
-#define ATA_CMD_READ_NATIVE_MAX_ADDRESS                 0xf8  ///< defined in ATA-6  
-#define ATA_CMD_READ_NATIVE_MAX_ADDRESS_EXT             0x27  ///< defined in ATA-6  
+#define ATA_CMD_SLEEP                                   0xe6  ///< defined in ACS-3
+#define ATA_CMD_READ_NATIVE_MAX_ADDRESS                 0xf8  ///< defined in ATA-6
+#define ATA_CMD_READ_NATIVE_MAX_ADDRESS_EXT             0x27  ///< defined in ATA-6
 
 //
 // Set Features Sub Command
 //
-#define ATA_SUB_CMD_ENABLE_VOLATILE_WRITE_CACHE             0x02   ///< defined in ACS-3 
-#define ATA_SUB_CMD_SET_TRANSFER_MODE                       0x03   ///< defined in ACS-3 
-#define ATA_SUB_CMD_ENABLE_APM                              0x05   ///< defined in ACS-3 
-#define ATA_SUB_CMD_ENABLE_PUIS                             0x06   ///< defined in ACS-3 
-#define ATA_SUB_CMD_PUIS_SET_DEVICE_SPINUP                  0x07   ///< defined in ACS-3 
-#define ATA_SUB_CMD_ENABLE_WRITE_READ_VERIFY                0x0b   ///< defined in ACS-3 
-#define ATA_SUB_CMD_ENABLE_SATA_FEATURE                     0x10   ///< defined in ACS-3 
-#define ATA_SUB_CMD_DISABLE_MEDIA_STATUS_NOTIFICATION       0x31   ///< defined in ACS-3 
-#define ATA_SUB_CMD_ENABLE_FREE_FALL_CONTROL                0x41   ///< defined in ACS-3 
-#define ATA_SUB_CMD_ACOUSTIC_MANAGEMENT_ENABLE              0x42   ///< defined in ACS-3 
-#define ATA_SUB_CMD_SET_MAX_HOST_INTERFACE_SECTOR_TIMES     0x43   ///< defined in ACS-3 
-#define ATA_SUB_CMD_EXTENDED_POWER_CONDITIONS               0x4a   ///< defined in ACS-3 
-#define ATA_SUB_CMD_DISABLE_READ_LOOK_AHEAD                 0x55   ///< defined in ACS-3 
-#define ATA_SUB_CMD_EN_DIS_DSN_FEATURE                      0x63   ///< defined in ACS-3 
-#define ATA_SUB_CMD_DISABLE_REVERT_TO_POWER_ON_DEFAULTS     0x66   ///< defined in ACS-3 
-#define ATA_SUB_CMD_DISABLE_VOLATILE_WRITE_CACHE            0x82   ///< defined in ACS-3 
-#define ATA_SUB_CMD_DISABLE_APM                             0x85   ///< defined in ACS-3 
-#define ATA_SUB_CMD_DISABLE_PUIS                            0x86   ///< defined in ACS-3 
-#define ATA_SUB_CMD_DISABLE_WRITE_READ_VERIFY               0x8b   ///< defined in ACS-3 
-#define ATA_SUB_CMD_DISABLE_SATA_FEATURE                    0x90   ///< defined in ACS-3 
-#define ATA_SUB_CMD_ENABLE_MEDIA_STATUS_NOTIFICATION        0x95   ///< defined in ACS-3 
-#define ATA_SUB_CMD_ENABLE_READ_LOOK_AHEAD                  0xaa   ///< defined in ACS-3 
-#define ATA_SUB_CMD_DISABLE_FREE_FALL_CONTROL               0xc1   ///< defined in ACS-3 
-#define ATA_SUB_CMD_ACOUSTIC_MANAGEMENT_DISABLE             0xc2   ///< defined in ACS-3 
-#define ATA_SUB_CMD_EN_DIS_SENSE_DATA_REPORTING             0xc3   ///< defined in ACS-3 
-#define ATA_SUB_CMD_ENABLE_REVERT_TO_POWER_ON_DEFAULTS      0xcc   ///< defined in ACS-3 
+#define ATA_SUB_CMD_ENABLE_VOLATILE_WRITE_CACHE             0x02   ///< defined in ACS-3
+#define ATA_SUB_CMD_SET_TRANSFER_MODE                       0x03   ///< defined in ACS-3
+#define ATA_SUB_CMD_ENABLE_APM                              0x05   ///< defined in ACS-3
+#define ATA_SUB_CMD_ENABLE_PUIS                             0x06   ///< defined in ACS-3
+#define ATA_SUB_CMD_PUIS_SET_DEVICE_SPINUP                  0x07   ///< defined in ACS-3
+#define ATA_SUB_CMD_ENABLE_WRITE_READ_VERIFY                0x0b   ///< defined in ACS-3
+#define ATA_SUB_CMD_ENABLE_SATA_FEATURE                     0x10   ///< defined in ACS-3
+#define ATA_SUB_CMD_DISABLE_MEDIA_STATUS_NOTIFICATION       0x31   ///< defined in ACS-3
+#define ATA_SUB_CMD_ENABLE_FREE_FALL_CONTROL                0x41   ///< defined in ACS-3
+#define ATA_SUB_CMD_ACOUSTIC_MANAGEMENT_ENABLE              0x42   ///< defined in ACS-3
+#define ATA_SUB_CMD_SET_MAX_HOST_INTERFACE_SECTOR_TIMES     0x43   ///< defined in ACS-3
+#define ATA_SUB_CMD_EXTENDED_POWER_CONDITIONS               0x4a   ///< defined in ACS-3
+#define ATA_SUB_CMD_DISABLE_READ_LOOK_AHEAD                 0x55   ///< defined in ACS-3
+#define ATA_SUB_CMD_EN_DIS_DSN_FEATURE                      0x63   ///< defined in ACS-3
+#define ATA_SUB_CMD_DISABLE_REVERT_TO_POWER_ON_DEFAULTS     0x66   ///< defined in ACS-3
+#define ATA_SUB_CMD_DISABLE_VOLATILE_WRITE_CACHE            0x82   ///< defined in ACS-3
+#define ATA_SUB_CMD_DISABLE_APM                             0x85   ///< defined in ACS-3
+#define ATA_SUB_CMD_DISABLE_PUIS                            0x86   ///< defined in ACS-3
+#define ATA_SUB_CMD_DISABLE_WRITE_READ_VERIFY               0x8b   ///< defined in ACS-3
+#define ATA_SUB_CMD_DISABLE_SATA_FEATURE                    0x90   ///< defined in ACS-3
+#define ATA_SUB_CMD_ENABLE_MEDIA_STATUS_NOTIFICATION        0x95   ///< defined in ACS-3
+#define ATA_SUB_CMD_ENABLE_READ_LOOK_AHEAD                  0xaa   ///< defined in ACS-3
+#define ATA_SUB_CMD_DISABLE_FREE_FALL_CONTROL               0xc1   ///< defined in ACS-3
+#define ATA_SUB_CMD_ACOUSTIC_MANAGEMENT_DISABLE             0xc2   ///< defined in ACS-3
+#define ATA_SUB_CMD_EN_DIS_SENSE_DATA_REPORTING             0xc3   ///< defined in ACS-3
+#define ATA_SUB_CMD_ENABLE_REVERT_TO_POWER_ON_DEFAULTS      0xcc   ///< defined in ACS-3
 
 //
 // S.M.A.R.T
@@ -640,13 +634,13 @@ typedef union {
 #define ATA_CONSTANT_C2                                 0xc2  ///< reserved
 #define ATA_CONSTANT_4F                                 0x4f  ///< reserved
 
-#define ATA_SMART_READ_DATA                             0xd0   ///< defined in ACS-3 
+#define ATA_SMART_READ_DATA                             0xd0   ///< defined in ACS-3
 
-#define ATA_SMART_AUTOSAVE                              0xd2  ///< defined in ACS-3 
+#define ATA_SMART_AUTOSAVE                              0xd2  ///< defined in ACS-3
     #define ATA_AUTOSAVE_DISABLE_ATTR                       0x00
     #define ATA_AUTOSAVE_ENABLE_ATTR                        0xf1
 
-#define ATA_SMART_EXECUTE_OFFLINE_IMMEDIATE             0xd4  ///< defined in ACS-3 
+#define ATA_SMART_EXECUTE_OFFLINE_IMMEDIATE             0xd4  ///< defined in ACS-3
     #define ATA_EXECUTE_SMART_OFFLINE_ROUTINE               0x00  ///< defined in ACS-3
     #define ATA_EXECUTE_SMART_OFFLINE_SHORT_SELFTEST        0x01  ///< defined in ACS-3
     #define ATA_EXECUTE_SMART_OFFLINE_EXTENDED_SELFTEST     0x02  ///< defined in ACS-3
@@ -658,25 +652,25 @@ typedef union {
     #define ATA_EXECUTE_SMART_CAPTIVE_CONVEYANCE_SELFTEST   0x83  ///< defined in ACS-3
     #define ATA_EXECUTE_SMART_CAPTIVE_SELECTIVE_SELFTEST    0x84  ///< defined in ACS-3
 
-#define ATA_SMART_READLOG                               0xd5  ///< defined in ACS-3 
-#define ATA_SMART_WRITELOG                              0xd6  ///< defined in ACS-3 
+#define ATA_SMART_READLOG                               0xd5  ///< defined in ACS-3
+#define ATA_SMART_WRITELOG                              0xd6  ///< defined in ACS-3
 #define ATA_SMART_ENABLE_OPERATION                      0xd8  ///< reserved
-#define ATA_SMART_DISABLE_OPERATION                     0xd9  ///< defined in ACS-3 
+#define ATA_SMART_DISABLE_OPERATION                     0xd9  ///< defined in ACS-3
 #define ATA_SMART_RETURN_STATUS                         0xda  ///< defined from ATA-3
 
-#define ATA_SMART_THRESHOLD_NOT_EXCEEDED_VALUE              0xc24f  ///< defined in ACS-3 
-#define ATA_SMART_THRESHOLD_EXCEEDED_VALUE                  0x2cf4  ///< defined in ACS-3 
+#define ATA_SMART_THRESHOLD_NOT_EXCEEDED_VALUE              0xc24f  ///< defined in ACS-3
+#define ATA_SMART_THRESHOLD_EXCEEDED_VALUE                  0x2cf4  ///< defined in ACS-3
 
 // SMART Log Definitions
-#define ATA_SMART_LOG_DIRECTORY                             0x00  ///< defined in ACS-3 
-#define ATA_SMART_SUM_SMART_ERROR_LOG                       0x01  ///< defined in ACS-3 
-#define ATA_SMART_COMP_SMART_ERROR_LOG                      0x02  ///< defined in ACS-3 
-#define ATA_SMART_EXT_COMP_SMART_ERROR_LOG                  0x03  ///< defined in ACS-3 
-#define ATA_SMART_SMART_SELFTEST_LOG                        0x06  ///< defined in ACS-3 
-#define ATA_SMART_EXT_SMART_SELFTEST_LOG                    0x07  ///< defined in ACS-3 
-#define ATA_SMART_SELECTIVE_SELFTEST_LOG                    0x09  ///< defined in ACS-3 
-#define ATA_SMART_HOST_VENDOR_SPECIFIC                      0x80  ///< defined in ACS-3 
-#define ATA_SMART_DEVICE_VENDOR_SPECIFIC                    0xa0  ///< defined in ACS-3 
+#define ATA_SMART_LOG_DIRECTORY                             0x00  ///< defined in ACS-3
+#define ATA_SMART_SUM_SMART_ERROR_LOG                       0x01  ///< defined in ACS-3
+#define ATA_SMART_COMP_SMART_ERROR_LOG                      0x02  ///< defined in ACS-3
+#define ATA_SMART_EXT_COMP_SMART_ERROR_LOG                  0x03  ///< defined in ACS-3
+#define ATA_SMART_SMART_SELFTEST_LOG                        0x06  ///< defined in ACS-3
+#define ATA_SMART_EXT_SMART_SELFTEST_LOG                    0x07  ///< defined in ACS-3
+#define ATA_SMART_SELECTIVE_SELFTEST_LOG                    0x09  ///< defined in ACS-3
+#define ATA_SMART_HOST_VENDOR_SPECIFIC                      0x80  ///< defined in ACS-3
+#define ATA_SMART_DEVICE_VENDOR_SPECIFIC                    0xa0  ///< defined in ACS-3
 
 //
 // Class 4: DMA Command
@@ -687,18 +681,18 @@ typedef union {
 #define ATA_CMD_WRITE_DMA                               0xca   ///< defined from ATA-1
 #define ATA_CMD_WRITE_DMA_WITH_RETRY                    0xcb   ///< defined from ATA-1, obsoleted from ATA-
 #define ATA_CMD_WRITE_DMA_EXT                           0x35   ///< defined from ATA-6
-  
+
 //
 //  ATA Security commands
 //
-#define ATA_CMD_SECURITY_SET_PASSWORD                   0xf1  ///< defined in ACS-3 
-#define ATA_CMD_SECURITY_UNLOCK                         0xf2  ///< defined in ACS-3 
-#define ATA_CMD_SECURITY_ERASE_PREPARE                  0xf3  ///< defined in ACS-3 
-#define ATA_CMD_SECURITY_ERASE_UNIT                     0xf4  ///< defined in ACS-3 
-#define ATA_CMD_SECURITY_FREEZE_LOCK                    0xf5  ///< defined in ACS-3 
-#define ATA_CMD_SECURITY_DISABLE_PASSWORD               0xf6  ///< defined in ACS-3 
+#define ATA_CMD_SECURITY_SET_PASSWORD                   0xf1  ///< defined in ACS-3
+#define ATA_CMD_SECURITY_UNLOCK                         0xf2  ///< defined in ACS-3
+#define ATA_CMD_SECURITY_ERASE_PREPARE                  0xf3  ///< defined in ACS-3
+#define ATA_CMD_SECURITY_ERASE_UNIT                     0xf4  ///< defined in ACS-3
+#define ATA_CMD_SECURITY_FREEZE_LOCK                    0xf5  ///< defined in ACS-3
+#define ATA_CMD_SECURITY_DISABLE_PASSWORD               0xf6  ///< defined in ACS-3
 
-#define ATA_SECURITY_BUFFER_LENGTH                          512  ///< defined in ACS-3 
+#define ATA_SECURITY_BUFFER_LENGTH                          512  ///< defined in ACS-3
 
 //
 //  ATA Device Config Overlay
@@ -712,19 +706,19 @@ typedef union {
 //
 //  ATA Trusted Computing Feature Set Commands
 //
-#define ATA_CMD_TRUSTED_NON_DATA                        0x5b  ///< defined in ACS-3 
-#define ATA_CMD_TRUSTED_RECEIVE                         0x5c  ///< defined in ACS-3 
-#define ATA_CMD_TRUSTED_RECEIVE_DMA                     0x5d  ///< defined in ACS-3 
-#define ATA_CMD_TRUSTED_SEND                            0x5e  ///< defined in ACS-3 
-#define ATA_CMD_TRUSTED_SEND_DMA                        0x5f  ///< defined in ACS-3 
+#define ATA_CMD_TRUSTED_NON_DATA                        0x5b  ///< defined in ACS-3
+#define ATA_CMD_TRUSTED_RECEIVE                         0x5c  ///< defined in ACS-3
+#define ATA_CMD_TRUSTED_RECEIVE_DMA                     0x5d  ///< defined in ACS-3
+#define ATA_CMD_TRUSTED_SEND                            0x5e  ///< defined in ACS-3
+#define ATA_CMD_TRUSTED_SEND_DMA                        0x5f  ///< defined in ACS-3
 
 //
 //  ATA Trusted Receive Fields
 //
-#define ATA_TR_RETURN_SECURITY_PROTOCOL_INFORMATION     0x00  ///< defined in ACS-3 
-#define ATA_TR_SECURITY_PROTOCOL_JEDEC_RESERVED         0xec  ///< defined in ACS-3 
-#define ATA_TR_SECURITY_PROTOCOL_SDCARD_RESERVED        0xed  ///< defined in ACS-3 
-#define ATA_TR_SECURITY_PROTOCOL_IEEE1667_RESERVED      0xee  ///< defined in ACS-3 
+#define ATA_TR_RETURN_SECURITY_PROTOCOL_INFORMATION     0x00  ///< defined in ACS-3
+#define ATA_TR_SECURITY_PROTOCOL_JEDEC_RESERVED         0xec  ///< defined in ACS-3
+#define ATA_TR_SECURITY_PROTOCOL_SDCARD_RESERVED        0xed  ///< defined in ACS-3
+#define ATA_TR_SECURITY_PROTOCOL_IEEE1667_RESERVED      0xee  ///< defined in ACS-3
 
 //
 //  Equates used for Acoustic Flags
@@ -732,18 +726,18 @@ typedef union {
 #define ATA_ACOUSTIC_LEVEL_BYPASS                       0xff   ///< defined from ATA-6
 #define ATA_ACOUSTIC_LEVEL_MAXIMUM_PERFORMANCE          0xfe   ///< defined from ATA-6
 #define ATA_ACOUSTIC_LEVEL_QUIET                        0x80   ///< defined from ATA-6
-    	
+
 //
 //  Equates used for DiPM Support
 //
-#define ATA_CMD_DIPM_SUB                                0x03   // defined in ACS-3 : Count value in SetFeature identification : 03h  Device-initiated interface power state transitions 
-    #define ATA_DIPM_ENABLE                                 0x10   // defined in ACS-3 
-    #define ATA_DIPM_DISABLE                                0x90   // defined in ACS-3 
+#define ATA_CMD_DIPM_SUB                                0x03   // defined in ACS-3 : Count value in SetFeature identification : 03h  Device-initiated interface power state transitions
+    #define ATA_DIPM_ENABLE                                 0x10   // defined in ACS-3
+    #define ATA_DIPM_DISABLE                                0x90   // defined in ACS-3
 
 //
 //  Equates used for DevSleep Support
 //
-#define ATA_CMD_DEVSLEEP_SUB                            0x09   // defined in SATA 3.2 Gold Spec :  Count value in SetFeature identification : 09h  Device Sleep 
+#define ATA_CMD_DEVSLEEP_SUB                            0x09   // defined in SATA 3.2 Gold Spec :  Count value in SetFeature identification : 09h  Device Sleep
     #define ATA_DEVSLEEP_ENABLE                             0x10   // defined in SATA 3.2 Gold Spec
     #define ATA_DEVSLEEP_DISABLE                            0x90   // defined in SATA 3.2 Gold Spec
 
@@ -765,7 +759,7 @@ typedef union {
 /// Default content of device control register, disable INT,
 /// Bit3 is set to 1 according ATA-1
 ///
-#define ATA_DEFAULT_CTL                                 (0x0a)  
+#define ATA_DEFAULT_CTL                                 (0x0a)
 ///
 /// Default context of Device/Head Register,
 /// Bit7 and Bit5 are set to 1 for back-compatibilities.
@@ -778,9 +772,9 @@ typedef union {
 
 //
 // Sense Key, Additional Sense Codes and Additional Sense Code Qualifier
-// defined in MultiMedia Commands (MMC, MMC-2) 
+// defined in MultiMedia Commands (MMC, MMC-2)
 //
-// Sense Key 
+// Sense Key
 //
 #define ATA_SK_NO_SENSE                                 (0x0)
 #define ATA_SK_RECOVERY_ERROR                           (0x1)
@@ -825,7 +819,7 @@ typedef union {
 
 //
 // Error Register
-//  
+//
 #define ATA_ERRREG_BBK                                  BIT7  ///< Bad block detected      defined from ATA-1, obsoleted from ATA-2
 #define ATA_ERRREG_UNC                                  BIT6  ///< Uncorrectable Data      defined from ATA-1, obsoleted from ATA-4
 #define ATA_ERRREG_MC                                   BIT5  ///< Media Change            defined from ATA-1, obsoleted from ATA-4
diff --git a/MdePkg/Include/IndustryStandard/Bluetooth.h b/MdePkg/Include/IndustryStandard/Bluetooth.h
index f4b7372d5482..96940129ff7c 100644
--- a/MdePkg/Include/IndustryStandard/Bluetooth.h
+++ b/MdePkg/Include/IndustryStandard/Bluetooth.h
@@ -2,14 +2,8 @@
   This file contains the Bluetooth definitions that are consumed by drivers.
   These definitions are from Bluetooth Core Specification Version 4.0 June, 2010
 
-  Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -38,6 +32,21 @@ typedef struct {
   UINT16     MajorServiceClass:11;
 } BLUETOOTH_CLASS_OF_DEVICE;
 
+///
+/// BLUETOOTH_LE_ADDRESS
+///
+typedef struct {
+  ///
+  /// 48-bit Bluetooth device address
+  ///
+  UINT8      Address[6];
+  ///
+  /// 0x00 - Public Device Address
+  /// 0x01 - Random Device Address
+  ///
+  UINT8      Type;
+} BLUETOOTH_LE_ADDRESS;
+
 #pragma pack()
 
 #define BLUETOOTH_HCI_COMMAND_LOCAL_READABLE_NAME_MAX_SIZE    248
diff --git a/MdePkg/Include/IndustryStandard/Bmp.h b/MdePkg/Include/IndustryStandard/Bmp.h
index 25393911c42c..36f719403662 100644
--- a/MdePkg/Include/IndustryStandard/Bmp.h
+++ b/MdePkg/Include/IndustryStandard/Bmp.h
@@ -2,13 +2,7 @@
   This file defines BMP file header data structures.
 
 Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/IndustryStandard/DebugPort2Table.h b/MdePkg/Include/IndustryStandard/DebugPort2Table.h
index 03331069fc29..5f8fc82b69b8 100644
--- a/MdePkg/Include/IndustryStandard/DebugPort2Table.h
+++ b/MdePkg/Include/IndustryStandard/DebugPort2Table.h
@@ -1,16 +1,10 @@
-/** @file   
-  ACPI debug port 2 table definition, defined at 
+/** @file
+  ACPI debug port 2 table definition, defined at
   Microsoft DebugPort2Specification.
 
-  Copyright (c) 2012, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR>
   Copyright (c) 2012 - 2016, ARM Limited. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/IndustryStandard/DebugPortTable.h b/MdePkg/Include/IndustryStandard/DebugPortTable.h
index 99791c513311..1aaea8ec5264 100644
--- a/MdePkg/Include/IndustryStandard/DebugPortTable.h
+++ b/MdePkg/Include/IndustryStandard/DebugPortTable.h
@@ -1,15 +1,9 @@
-/** @file   
-  ACPI debug port table definition, defined at 
+/** @file
+  ACPI debug port table definition, defined at
   Microsoft DebugPortSpecification.
 
-  Copyright (c) 2012, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/IndustryStandard/Dhcp.h b/MdePkg/Include/IndustryStandard/Dhcp.h
index 9f09753624e4..f51bb93c3178 100644
--- a/MdePkg/Include/IndustryStandard/Dhcp.h
+++ b/MdePkg/Include/IndustryStandard/Dhcp.h
@@ -3,13 +3,8 @@
   They are used to carry additional information and parameters in DHCP messages.
 
   Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
 #ifndef _DHCP_H_
@@ -272,11 +267,17 @@ typedef enum {
 #define PXE_CLIENT_ARCH_EBC              0x0009    /// EBC for PXE
 #define PXE_CLIENT_ARCH_ARM              0x000A    /// Arm uefi 32 for PXE
 #define PXE_CLIENT_ARCH_AARCH64          0x000B    /// Arm uefi 64 for PXE
+#define PXE_CLIENT_ARCH_RISCV32          0x0019    /// RISC-V uefi 32 for PXE
+#define PXE_CLIENT_ARCH_RISCV64          0x001B    /// RISC-V uefi 64 for PXE
+#define PXE_CLIENT_ARCH_RISCV128         0x001D    /// RISC-V uefi 128 for PXE
 
 #define HTTP_CLIENT_ARCH_IA32            0x000F    /// x86 uefi boot from http
 #define HTTP_CLIENT_ARCH_X64             0x0010    /// x64 uefi boot from http
 #define HTTP_CLIENT_ARCH_EBC             0x0011    /// EBC boot from http
 #define HTTP_CLIENT_ARCH_ARM             0x0012    /// Arm uefi 32 boot from http
 #define HTTP_CLIENT_ARCH_AARCH64         0x0013    /// Arm uefi 64 boot from http
+#define HTTP_CLIENT_ARCH_RISCV32         0x001A    /// RISC-V uefi 32 boot from http
+#define HTTP_CLIENT_ARCH_RISCV64         0x001C    /// RISC-V uefi 64 boot from http
+#define HTTP_CLIENT_ARCH_RISCV128        0x001E    /// RISC-V uefi 128 boot from http
 
 #endif
diff --git a/MdePkg/Include/IndustryStandard/DmaRemappingReportingTable.h b/MdePkg/Include/IndustryStandard/DmaRemappingReportingTable.h
index 9c9afb358c4f..3e5aadc4a831 100644
--- a/MdePkg/Include/IndustryStandard/DmaRemappingReportingTable.h
+++ b/MdePkg/Include/IndustryStandard/DmaRemappingReportingTable.h
@@ -2,18 +2,12 @@
   DMA Remapping Reporting (DMAR) ACPI table definition from Intel(R)
   Virtualization Technology for Directed I/O (VT-D) Architecture Specification.
 
-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
     - Intel(R) Virtualization Technology for Directed I/O (VT-D) Architecture
-      Specification v2.4, Dated June 2016.
+      Specification v2.5, Dated November 2017.
       http://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/vt-directed-io-spec.pdf
 
   @par Glossary:
@@ -23,15 +17,18 @@
 #ifndef _DMA_REMAPPING_REPORTING_TABLE_H_
 #define _DMA_REMAPPING_REPORTING_TABLE_H_
 
+#include <IndustryStandard/Acpi.h>
+
 #pragma pack(1)
 
 ///
 /// DMA-Remapping Reporting Structure definitions from section 8.1
 ///@{
-#define EFI_ACPI_DMAR_REVISION                    0x01
+#define EFI_ACPI_DMAR_REVISION                             0x01
 
-#define EFI_ACPI_DMAR_FLAGS_INTR_REMAP            BIT0
-#define EFI_ACPI_DMAR_FLAGS_X2APIC_OPT_OUT        BIT1
+#define EFI_ACPI_DMAR_FLAGS_INTR_REMAP                     BIT0
+#define EFI_ACPI_DMAR_FLAGS_X2APIC_OPT_OUT                 BIT1
+#define EFI_ACPI_DMAR_FLAGS_DMA_CTRL_PLATFORM_OPT_IN_FLAG  BIT2
 ///@}
 
 ///
@@ -250,7 +247,12 @@ typedef struct {
                 firmware may Set this field to request system software to opt
                 out of enabling Extended xAPIC (X2APIC) mode. This field is
                 valid only when the INTR_REMAP field (bit 0) is Set.
-    - Bits[7:2] Reserved.
+    - Bit[2]:   DMA_CTRL_PLATFORM_OPT_IN_FLAG - Platform firmware is
+                recommended to Set this field to report any platform initiated
+                DMA is restricted to only reserved memory regions (reported in
+                RMRR structures) when transferring control to system software
+                such as on ExitBootServices().
+    - Bits[7:3] Reserved.
   **/
   UINT8                           Flags;
   UINT8                           Reserved[10];
diff --git a/MdePkg/Include/IndustryStandard/ElTorito.h b/MdePkg/Include/IndustryStandard/ElTorito.h
index 3a3d018ac7d3..e9b870f77801 100644
--- a/MdePkg/Include/IndustryStandard/ElTorito.h
+++ b/MdePkg/Include/IndustryStandard/ElTorito.h
@@ -1,18 +1,12 @@
 /** @file
-  ElTorito Partitions Format Definition. 
-  This file includes some defintions from 
+  ElTorito Partitions Format Definition.
+  This file includes some definitions from
   1. "El Torito" Bootable CD-ROM Format Specification, Version 1.0.
-  2. Volume and File Structure of CDROM for Information Interchange, 
+  2. Volume and File Structure of CDROM for Information Interchange,
      Standard ECMA-119. (IS0 9660)
 
-Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials                          
-are licensed and made available under the terms and conditions of the BSD License         
-which accompanies this distribution.  The full text of the license may be found at        
-http://opensource.org/licenses/bsd-license.php                                            
-                                                                                          
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -57,13 +51,13 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
 #pragma pack(1)
 
-/// 
+///
 /// CD-ROM Volume Descriptor
-/// 
-typedef union { 
+///
+typedef union {
   struct {
-    UINT8   Type;     
-    CHAR8   Id[5];           ///< "CD001"    
+    UINT8   Type;
+    CHAR8   Id[5];           ///< "CD001"
     CHAR8   Reserved[82];
   } Unknown;
 
@@ -72,29 +66,29 @@ typedef union {
   ///
   struct {
     UINT8   Type;            ///< Must be 0
-    CHAR8   Id[5];           ///< "CD001" 
-    UINT8   Version;         ///< Must be 1 
-    CHAR8   SystemId[32];    ///< "EL TORITO SPECIFICATION" 
-    CHAR8   Unused[32];      ///< Must be 0 
+    CHAR8   Id[5];           ///< "CD001"
+    UINT8   Version;         ///< Must be 1
+    CHAR8   SystemId[32];    ///< "EL TORITO SPECIFICATION"
+    CHAR8   Unused[32];      ///< Must be 0
     UINT8   EltCatalog[4];   ///< Absolute pointer to first sector of Boot Catalog
     CHAR8   Unused2[13];     ///< Must be 0
   } BootRecordVolume;
- 
+
   ///
-  /// Primary Volumn Descriptor, defined in ISO 9660.
+  /// Primary Volume Descriptor, defined in ISO 9660.
   ///
   struct {
-    UINT8   Type; 
+    UINT8   Type;
     CHAR8   Id[5];           ///< "CD001"
-    UINT8   Version; 
+    UINT8   Version;
     UINT8   Unused;          ///< Must be 0
-    CHAR8   SystemId[32];    
-    CHAR8   VolumeId[32];    
-    UINT8   Unused2[8];      ///< Must be 0 
+    CHAR8   SystemId[32];
+    CHAR8   VolumeId[32];
+    UINT8   Unused2[8];      ///< Must be 0
     UINT32  VolSpaceSize[2]; ///< the number of Logical Blocks
   } PrimaryVolume;
 
-} CDROM_VOLUME_DESCRIPTOR; 
+} CDROM_VOLUME_DESCRIPTOR;
 
 ///
 /// Catalog Entry
diff --git a/MdePkg/Include/IndustryStandard/Emmc.h b/MdePkg/Include/IndustryStandard/Emmc.h
index ad0ca55d7783..0987f6c4985c 100644
--- a/MdePkg/Include/IndustryStandard/Emmc.h
+++ b/MdePkg/Include/IndustryStandard/Emmc.h
@@ -4,13 +4,7 @@
   This header file contains some definitions defined in EMMC4.5/EMMC5.0 spec.
 
   Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -230,7 +224,7 @@ typedef struct {
   UINT8   MinPerfW8B52M;                          // Minimum Write Performance for 8bit at 52MHz [210]
   UINT8   Reserved17;                             // Reserved [211]
   UINT8   SecCount[4];                            // Sector Count [215:212]
-  UINT8   SleepNotificationTime;                  // Sleep Notification Timout [216]
+  UINT8   SleepNotificationTime;                  // Sleep Notification Timeout [216]
   UINT8   SATimeout;                              // Sleep/awake timeout [217]
   UINT8   ProductionStateAwarenessTimeout;        // Production state awareness timeout [218]
   UINT8   SCVccq;                                 // Sleep current (VCCQ) [219]
diff --git a/MdePkg/Include/IndustryStandard/HighPrecisionEventTimerTable.h b/MdePkg/Include/IndustryStandard/HighPrecisionEventTimerTable.h
index 97b1c45edfc9..d2bc6d57c401 100644
--- a/MdePkg/Include/IndustryStandard/HighPrecisionEventTimerTable.h
+++ b/MdePkg/Include/IndustryStandard/HighPrecisionEventTimerTable.h
@@ -1,15 +1,9 @@
 /** @file
   ACPI high precision event timer table definition, at www.intel.com
   Specification name is IA-PC HPET (High Precision Event Timers) Specification.
-    
-  Copyright (c) 2007 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+  Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
 #ifndef _HIGH_PRECISION_EVENT_TIMER_TABLE_H_
@@ -23,6 +17,22 @@
 #pragma pack(1)
 
 ///
+/// HPET Event Timer Block ID described in IA-PC HPET Specification, 3.2.4.
+///
+typedef union {
+  struct {
+    UINT32 Revision       : 8;
+    UINT32 NumberOfTimers : 5;
+    UINT32 CounterSize    : 1;
+    UINT32 Reserved       : 1;
+    UINT32 LegacyRoute    : 1;
+    UINT32 VendorId       : 16;
+  }      Bits;
+  UINT32 Uint32;
+} EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_BLOCK_ID;
+
+
+///
 /// High Precision Event Timer Table header definition.
 ///
 typedef struct {
diff --git a/MdePkg/Include/IndustryStandard/Hsti.h b/MdePkg/Include/IndustryStandard/Hsti.h
index 2d9994ecb7fa..6b403ccbe8af 100644
--- a/MdePkg/Include/IndustryStandard/Hsti.h
+++ b/MdePkg/Include/IndustryStandard/Hsti.h
@@ -1,15 +1,9 @@
 /** @file
-  Support for HSTI 1.0 specification, defined at 
+  Support for HSTI 1.1a specification, defined at
   Microsoft Hardware Security Testability Specification.
 
-  Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -25,8 +19,8 @@
 
 #define PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE 0x00000001  // IHV
 #define PLATFORM_SECURITY_ROLE_PLATFORM_IBV       0x00000002
-#define PLATFORM_SECURITY_ROLE_IMPLEMENTOR_OEM    0x00000003 
-#define PLATFORM_SECURITY_ROLE_IMPLEMENTOR_ODM    0x00000004  
+#define PLATFORM_SECURITY_ROLE_IMPLEMENTOR_OEM    0x00000003
+#define PLATFORM_SECURITY_ROLE_IMPLEMENTOR_ODM    0x00000004
 
 typedef struct {
   //
@@ -72,7 +66,7 @@ typedef struct {
   // which will describe the steps to remediate the failure - a URL to the
   // documentation is recommended.
   //
-//CHAR16	ErrorString[];
+//CHAR16  ErrorString[];
 } ADAPTER_INFO_PLATFORM_SECURITY;
 
 #pragma pack()
diff --git a/MdePkg/Include/IndustryStandard/Http11.h b/MdePkg/Include/IndustryStandard/Http11.h
index 797e74e4d4b9..50a182634d04 100644
--- a/MdePkg/Include/IndustryStandard/Http11.h
+++ b/MdePkg/Include/IndustryStandard/Http11.h
@@ -1,16 +1,10 @@
 /** @file
-  Hypertext Transfer Protocol -- HTTP/1.1 Standard definitions, from RFC 2616    
+  Hypertext Transfer Protocol -- HTTP/1.1 Standard definitions, from RFC 2616
 
-  This file contains common HTTP 1.1 definitions from RFC 2616 
-   
-  (C) Copyright 2015-2016 Hewlett Packard Enterprise Development LP<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
+  This file contains common HTTP 1.1 definitions from RFC 2616
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  (C) Copyright 2015-2016 Hewlett Packard Enterprise Development LP<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
 #ifndef __HTTP_11_H__
@@ -20,7 +14,7 @@
 
 ///
 /// HTTP Version (currently HTTP 1.1)
-/// 
+///
 /// The version of an HTTP message is indicated by an HTTP-Version field
 /// in the first line of the message.
 ///
@@ -28,7 +22,7 @@
 
 ///
 /// HTTP Request Method definitions
-/// 
+///
 /// The Method  token indicates the method to be performed on the
 /// resource identified by the Request-URI. The method is case-sensitive.
 ///
@@ -50,27 +44,27 @@
 
 ///
 /// Accept Request Header
-/// The Accept request-header field can be used to specify certain media types which are 
-/// acceptable for the response. Accept headers can be used to indicate that the request 
-/// is specifically limited to a small set of desired types, as in the case of a request 
+/// The Accept request-header field can be used to specify certain media types which are
+/// acceptable for the response. Accept headers can be used to indicate that the request
+/// is specifically limited to a small set of desired types, as in the case of a request
 /// for an in-line image.
 ///
 #define HTTP_HEADER_ACCEPT             "Accept"
 
 
-/// 
+///
 /// Accept-Charset Request Header
-/// The Accept-Charset request-header field can be used to indicate what character sets 
-/// are acceptable for the response. This field allows clients capable of understanding 
-/// more comprehensive or special-purpose character sets to signal that capability to a 
+/// The Accept-Charset request-header field can be used to indicate what character sets
+/// are acceptable for the response. This field allows clients capable of understanding
+/// more comprehensive or special-purpose character sets to signal that capability to a
 /// server which is capable of representing documents in those character sets.
 ///
 #define HTTP_HEADER_ACCEPT_CHARSET     "Accept-Charset"
 
-/// 
+///
 /// Accept-Language Request Header
-/// The Accept-Language request-header field is similar to Accept, 
-/// but restricts the set of natural languages that are preferred 
+/// The Accept-Language request-header field is similar to Accept,
+/// but restricts the set of natural languages that are preferred
 /// as a response to the request.
 ///
 #define HTTP_HEADER_ACCEPT_LANGUAGE    "Accept-Language"
@@ -83,39 +77,39 @@
 #define HTTP_HEADER_ACCEPT_RANGES      "Accept-Ranges"
 
 
-/// 
+///
 /// Accept-Encoding Request Header
-/// The Accept-Encoding request-header field is similar to Accept, 
+/// The Accept-Encoding request-header field is similar to Accept,
 /// but restricts the content-codings that are acceptable in the response.
 ///
 #define HTTP_HEADER_ACCEPT_ENCODING    "Accept-Encoding"
 
 ///
 /// Content-Encoding Header
-/// The Content-Encoding entity-header field is used as a modifier to the media-type. 
-/// When present, its value indicates what additional content codings have been applied 
-/// to the entity-body, and thus what decoding mechanisms must be applied in order to 
-/// obtain the media-type referenced by the Content-Type header field. Content-Encoding 
-/// is primarily used to allow a document to be compressed without losing the identity 
+/// The Content-Encoding entity-header field is used as a modifier to the media-type.
+/// When present, its value indicates what additional content codings have been applied
+/// to the entity-body, and thus what decoding mechanisms must be applied in order to
+/// obtain the media-type referenced by the Content-Type header field. Content-Encoding
+/// is primarily used to allow a document to be compressed without losing the identity
 /// of its underlying media type.
 ///
 #define HTTP_HEADER_CONTENT_ENCODING   "Content-Encoding"
 
-/// 
+///
 /// HTTP Content-Encoding Compression types
 ///
 
 #define HTTP_CONTENT_ENCODING_IDENTITY "identity"  /// No transformation is used. This is the default value for content coding.
 #define HTTP_CONTENT_ENCODING_GZIP     "gzip"      /// Content-Encoding: GNU zip format (described in RFC 1952).
-#define HTTP_CONTENT_ENCODING_COMPRESS "compress"  /// encoding format produced by the common UNIX file compression program "compress". 
-#define HTTP_CONTENT_ENCODING_DEFLATE  "deflate"   /// The "zlib" format defined in RFC 1950 in combination with the "deflate" 
+#define HTTP_CONTENT_ENCODING_COMPRESS "compress"  /// encoding format produced by the common UNIX file compression program "compress".
+#define HTTP_CONTENT_ENCODING_DEFLATE  "deflate"   /// The "zlib" format defined in RFC 1950 in combination with the "deflate"
                                                    /// compression mechanism described in RFC 1951.
 
 
 ///
 /// Content-Type Header
-/// The Content-Type entity-header field indicates the media type of the entity-body sent to 
-/// the recipient or, in the case of the HEAD method, the media type that would have been sent 
+/// The Content-Type entity-header field indicates the media type of the entity-body sent to
+/// the recipient or, in the case of the HEAD method, the media type that would have been sent
 /// had the request been a GET.
 ///
 #define HTTP_HEADER_CONTENT_TYPE       "Content-Type"
@@ -124,12 +118,12 @@
 //
 #define HTTP_CONTENT_TYPE_APP_JSON          "application/json"
 #define HTTP_CONTENT_TYPE_APP_OCTET_STREAM  "application/octet-stream"
-                                           
+
 #define HTTP_CONTENT_TYPE_TEXT_HTML         "text/html"
 #define HTTP_CONTENT_TYPE_TEXT_PLAIN        "text/plain"
 #define HTTP_CONTENT_TYPE_TEXT_CSS          "text/css"
 #define HTTP_CONTENT_TYPE_TEXT_XML          "text/xml"
-                                           
+
 #define HTTP_CONTENT_TYPE_IMAGE_GIF         "image/gif"
 #define HTTP_CONTENT_TYPE_IMAGE_JPEG        "image/jpeg"
 #define HTTP_CONTENT_TYPE_IMAGE_PNG         "image/png"
@@ -138,17 +132,17 @@
 
 ///
 /// Content-Length Header
-/// The Content-Length entity-header field indicates the size of the entity-body, 
-/// in decimal number of OCTETs, sent to the recipient or, in the case of the HEAD 
+/// The Content-Length entity-header field indicates the size of the entity-body,
+/// in decimal number of OCTETs, sent to the recipient or, in the case of the HEAD
 /// method, the size of the entity-body that would have been sent had the request been a GET.
 ///
 #define HTTP_HEADER_CONTENT_LENGTH     "Content-Length"
-                                                                                                              
+
 ///
 /// Transfer-Encoding Header
-/// The Transfer-Encoding general-header field indicates what (if any) type of transformation 
-/// has been applied to the message body in order to safely transfer it between the sender 
-/// and the recipient. This differs from the content-coding in that the transfer-coding 
+/// The Transfer-Encoding general-header field indicates what (if any) type of transformation
+/// has been applied to the message body in order to safely transfer it between the sender
+/// and the recipient. This differs from the content-coding in that the transfer-coding
 /// is a property of the message, not of the entity.
 ///
 #define HTTP_HEADER_TRANSFER_ENCODING  "Transfer-Encoding"
@@ -156,14 +150,14 @@
 
 ///
 /// User Agent Request Header
-/// 
-/// The User-Agent request-header field contains information about the user agent originating 
-/// the request. This is for statistical purposes, the tracing of protocol violations, and 
-/// automated recognition of user agents for the sake of tailoring responses to avoid 
-/// particular user agent limitations. User agents SHOULD include this field with requests. 
-/// The field can contain multiple product tokens and comments identifying the agent and any 
-/// subproducts which form a significant part of the user agent. 
-/// By convention, the product tokens are listed in order of their significance for 
+///
+/// The User-Agent request-header field contains information about the user agent originating
+/// the request. This is for statistical purposes, the tracing of protocol violations, and
+/// automated recognition of user agents for the sake of tailoring responses to avoid
+/// particular user agent limitations. User agents SHOULD include this field with requests.
+/// The field can contain multiple product tokens and comments identifying the agent and any
+/// subproducts which form a significant part of the user agent.
+/// By convention, the product tokens are listed in order of their significance for
 /// identifying the application.
 ///
 #define HTTP_HEADER_USER_AGENT         "User-Agent"
@@ -171,49 +165,49 @@
 ///
 /// Host Request Header
 ///
-/// The Host request-header field specifies the Internet host and port number of the resource 
-/// being requested, as obtained from the original URI given by the user or referring resource 
+/// The Host request-header field specifies the Internet host and port number of the resource
+/// being requested, as obtained from the original URI given by the user or referring resource
 ///
 #define HTTP_HEADER_HOST              "Host"
 
 ///
 /// Location Response Header
-/// 
-/// The Location response-header field is used to redirect the recipient to a location other than 
-/// the Request-URI for completion of the request or identification of a new resource. 
-/// For 201 (Created) responses, the Location is that of the new resource which was created by 
-/// the request. For 3xx responses, the location SHOULD indicate the server's preferred URI for 
+///
+/// The Location response-header field is used to redirect the recipient to a location other than
+/// the Request-URI for completion of the request or identification of a new resource.
+/// For 201 (Created) responses, the Location is that of the new resource which was created by
+/// the request. For 3xx responses, the location SHOULD indicate the server's preferred URI for
 /// automatic redirection to the resource. The field value consists of a single absolute URI.
 ///
 #define HTTP_HEADER_LOCATION           "Location"
 
 ///
 /// The If-Match request-header field is used with a method to make it conditional.
-/// A client that has one or more entities previously obtained from the resource 
-/// can verify that one of those entities is current by including a list of their 
-/// associated entity tags in the If-Match header field. 
-/// The purpose of this feature is to allow efficient updates of cached information 
-/// with a minimum amount of transaction overhead. It is also used, on updating requests, 
-/// to prevent inadvertent modification of the wrong version of a resource. 
+/// A client that has one or more entities previously obtained from the resource
+/// can verify that one of those entities is current by including a list of their
+/// associated entity tags in the If-Match header field.
+/// The purpose of this feature is to allow efficient updates of cached information
+/// with a minimum amount of transaction overhead. It is also used, on updating requests,
+/// to prevent inadvertent modification of the wrong version of a resource.
 /// As a special case, the value "*" matches any current entity of the resource.
 ///
 #define HTTP_HEADER_IF_MATCH          "If-Match"
 
 
 ///
-/// The If-None-Match request-header field is used with a method to make it conditional. 
-/// A client that has one or more entities previously obtained from the resource can verify 
-/// that none of those entities is current by including a list of their associated entity 
-/// tags in the If-None-Match header field. The purpose of this feature is to allow efficient 
-/// updates of cached information with a minimum amount of transaction overhead. It is also used 
-/// to prevent a method (e.g. PUT) from inadvertently modifying an existing resource when the 
+/// The If-None-Match request-header field is used with a method to make it conditional.
+/// A client that has one or more entities previously obtained from the resource can verify
+/// that none of those entities is current by including a list of their associated entity
+/// tags in the If-None-Match header field. The purpose of this feature is to allow efficient
+/// updates of cached information with a minimum amount of transaction overhead. It is also used
+/// to prevent a method (e.g. PUT) from inadvertently modifying an existing resource when the
 /// client believes that the resource does not exist.
 ///
 #define HTTP_HEADER_IF_NONE_MATCH     "If-None-Match"
 
 
 
-/// 
+///
 /// Authorization Request Header
 /// The Authorization field value consists of credentials
 /// containing the authentication information of the user agent for
@@ -223,8 +217,8 @@
 
 ///
 /// ETAG Response Header
-/// The ETag response-header field provides the current value of the entity tag 
-/// for the requested variant. 
+/// The ETag response-header field provides the current value of the entity tag
+/// for the requested variant.
 ///
 #define HTTP_HEADER_ETAG              "ETag"
 
diff --git a/MdePkg/Include/IndustryStandard/IScsiBootFirmwareTable.h b/MdePkg/Include/IndustryStandard/IScsiBootFirmwareTable.h
index d542b2c41291..547f2cc02f42 100644
--- a/MdePkg/Include/IndustryStandard/IScsiBootFirmwareTable.h
+++ b/MdePkg/Include/IndustryStandard/IScsiBootFirmwareTable.h
@@ -1,15 +1,9 @@
 /** @file
   The definition for iSCSI Boot Firmware Table, it's defined in Microsoft's
-  iSCSI Boot Firmware Table(iBFT) as Defined in ACPI 3.0b Specification. 
-  
-  Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
+  iSCSI Boot Firmware Table(iBFT) as Defined in ACPI 3.0b Specification.
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -58,7 +52,7 @@ typedef struct {
 } EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_HEADER;
 
 ///
-/// Common Header of Boot Firmware Table Structure 
+/// Common Header of Boot Firmware Table Structure
 ///
 typedef struct {
   UINT8   StructureId;
@@ -78,7 +72,7 @@ typedef struct {
   UINT16                                               NIC0Offset;
   UINT16                                               Target0Offset;
   UINT16                                               NIC1Offset;
-  UINT16                                               Target1Offset;  
+  UINT16                                               Target1Offset;
 } EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE;
 
 #define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE_VERSION              0x1
@@ -100,8 +94,8 @@ typedef struct {
 
 #define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_VERSION             0x1
 
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_FLAG_BLOCK_VALID    BIT0 
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_FLAG_BOOT_SELECTED  BIT1 
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_FLAG_BLOCK_VALID    BIT0
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_FLAG_BOOT_SELECTED  BIT1
 
 ///
 /// NIC Structure
diff --git a/MdePkg/Include/IndustryStandard/IoRemappingTable.h b/MdePkg/Include/IndustryStandard/IoRemappingTable.h
new file mode 100644
index 000000000000..5ecf46097def
--- /dev/null
+++ b/MdePkg/Include/IndustryStandard/IoRemappingTable.h
@@ -0,0 +1,203 @@
+/** @file
+  ACPI IO Remapping Table (IORT) as specified in ARM spec DEN0049D
+
+  http://infocenter.arm.com/help/topic/com.arm.doc.den0049d/DEN0049D_IO_Remapping_Table.pdf
+
+  Copyright (c) 2017, Linaro Limited. All rights reserved.<BR>
+  Copyright (c) 2018, ARM Limited. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __IO_REMAPPING_TABLE_H__
+#define __IO_REMAPPING_TABLE_H__
+
+#include <IndustryStandard/Acpi.h>
+
+#define EFI_ACPI_IO_REMAPPING_TABLE_REVISION        0x0
+
+#define EFI_ACPI_IORT_TYPE_ITS_GROUP                0x0
+#define EFI_ACPI_IORT_TYPE_NAMED_COMP               0x1
+#define EFI_ACPI_IORT_TYPE_ROOT_COMPLEX             0x2
+#define EFI_ACPI_IORT_TYPE_SMMUv1v2                 0x3
+#define EFI_ACPI_IORT_TYPE_SMMUv3                   0x4
+#define EFI_ACPI_IORT_TYPE_PMCG                     0x5
+
+#define EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA           BIT0
+
+#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_TR         BIT0
+#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_WA         BIT1
+#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_RA         BIT2
+#define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_AHO        BIT3
+
+#define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM          BIT0
+#define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS         BIT1
+
+#define EFI_ACPI_IORT_SMMUv1v2_MODEL_v1             0x0
+#define EFI_ACPI_IORT_SMMUv1v2_MODEL_v2             0x1
+#define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU400         0x2
+#define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU500         0x3
+#define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU401         0x4
+#define EFI_ACPI_IORT_SMMUv1v2_MODEL_CAVIUM_THX_v2  0x5
+
+#define EFI_ACPI_IORT_SMMUv1v2_FLAG_DVM             BIT0
+#define EFI_ACPI_IORT_SMMUv1v2_FLAG_COH_WALK        BIT1
+
+#define EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL       0x0
+#define EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_EDGE        0x1
+
+#define EFI_ACPI_IORT_SMMUv3_FLAG_COHAC_OVERRIDE    BIT0
+#define EFI_ACPI_IORT_SMMUv3_FLAG_HTTU_OVERRIDE     BIT1
+#define EFI_ACPI_IORT_SMMUv3_FLAG_PROXIMITY_DOMAIN  BIT3
+
+#define EFI_ACPI_IORT_SMMUv3_MODEL_GENERIC          0x0
+#define EFI_ACPI_IORT_SMMUv3_MODEL_HISILICON_HI161X 0x1
+#define EFI_ACPI_IORT_SMMUv3_MODEL_CAVIUM_CN99XX    0x2
+
+#define EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED  0x0
+#define EFI_ACPI_IORT_ROOT_COMPLEX_ATS_SUPPORTED    0x1
+
+#define EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE       BIT0
+
+#pragma pack(1)
+
+///
+/// Table header
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER             Header;
+  UINT32                                  NumNodes;
+  UINT32                                  NodeOffset;
+  UINT32                                  Reserved;
+} EFI_ACPI_6_0_IO_REMAPPING_TABLE;
+
+///
+/// Definition for ID mapping table shared by all node types
+///
+typedef struct {
+  UINT32                                  InputBase;
+  UINT32                                  NumIds;
+  UINT32                                  OutputBase;
+  UINT32                                  OutputReference;
+  UINT32                                  Flags;
+} EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE;
+
+///
+/// Node header definition shared by all node types
+///
+typedef struct {
+  UINT8                                   Type;
+  UINT16                                  Length;
+  UINT8                                   Revision;
+  UINT32                                  Reserved;
+  UINT32                                  NumIdMappings;
+  UINT32                                  IdReference;
+} EFI_ACPI_6_0_IO_REMAPPING_NODE;
+
+///
+/// Node type 0: ITS node
+///
+typedef struct {
+  EFI_ACPI_6_0_IO_REMAPPING_NODE          Node;
+
+  UINT32                                  NumItsIdentifiers;
+//UINT32                                  ItsIdentifiers[NumItsIdentifiers];
+} EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE;
+
+///
+/// Node type 1: root complex node
+///
+typedef struct {
+  EFI_ACPI_6_0_IO_REMAPPING_NODE          Node;
+
+  UINT32                                  CacheCoherent;
+  UINT8                                   AllocationHints;
+  UINT16                                  Reserved;
+  UINT8                                   MemoryAccessFlags;
+
+  UINT32                                  AtsAttribute;
+  UINT32                                  PciSegmentNumber;
+  UINT8                                   MemoryAddressSize;
+  UINT8                                   Reserved1[3];
+} EFI_ACPI_6_0_IO_REMAPPING_RC_NODE;
+
+///
+/// Node type 2: named component node
+///
+typedef struct {
+  EFI_ACPI_6_0_IO_REMAPPING_NODE          Node;
+
+  UINT32                                  Flags;
+  UINT32                                  CacheCoherent;
+  UINT8                                   AllocationHints;
+  UINT16                                  Reserved;
+  UINT8                                   MemoryAccessFlags;
+  UINT8                                   AddressSizeLimit;
+//UINT8                                   ObjectName[];
+} EFI_ACPI_6_0_IO_REMAPPING_NAMED_COMP_NODE;
+
+///
+/// Node type 3: SMMUv1 or SMMUv2 node
+///
+typedef struct {
+  UINT32                                  Interrupt;
+  UINT32                                  InterruptFlags;
+} EFI_ACPI_6_0_IO_REMAPPING_SMMU_INT;
+
+typedef struct {
+  EFI_ACPI_6_0_IO_REMAPPING_NODE          Node;
+
+  UINT64                                  Base;
+  UINT64                                  Span;
+  UINT32                                  Model;
+  UINT32                                  Flags;
+  UINT32                                  GlobalInterruptArrayRef;
+  UINT32                                  NumContextInterrupts;
+  UINT32                                  ContextInterruptArrayRef;
+  UINT32                                  NumPmuInterrupts;
+  UINT32                                  PmuInterruptArrayRef;
+
+  UINT32                                  SMMU_NSgIrpt;
+  UINT32                                  SMMU_NSgIrptFlags;
+  UINT32                                  SMMU_NSgCfgIrpt;
+  UINT32                                  SMMU_NSgCfgIrptFlags;
+
+//EFI_ACPI_6_0_IO_REMAPPING_SMMU_CTX_INT  ContextInterrupt[NumContextInterrupts];
+//EFI_ACPI_6_0_IO_REMAPPING_SMMU_CTX_INT  PmuInterrupt[NumPmuInterrupts];
+} EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE;
+
+///
+/// Node type 4: SMMUv3 node
+///
+typedef struct {
+  EFI_ACPI_6_0_IO_REMAPPING_NODE          Node;
+
+  UINT64                                  Base;
+  UINT32                                  Flags;
+  UINT32                                  Reserved;
+  UINT64                                  VatosAddress;
+  UINT32                                  Model;
+  UINT32                                  Event;
+  UINT32                                  Pri;
+  UINT32                                  Gerr;
+  UINT32                                  Sync;
+  UINT32                                  ProximityDomain;
+  UINT32                                  DeviceIdMappingIndex;
+} EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE;
+
+///
+/// Node type 5: PMCG node
+///
+typedef struct {
+  EFI_ACPI_6_0_IO_REMAPPING_NODE          Node;
+
+  UINT64                                  Base;
+  UINT32                                  OverflowInterruptGsiv;
+  UINT32                                  NodeReference;
+  UINT64                                  Page1Base;
+//EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE      OverflowInterruptMsiMapping[1];
+} EFI_ACPI_6_0_IO_REMAPPING_PMCG_NODE;
+
+#pragma pack()
+
+#endif
diff --git a/MdePkg/Include/IndustryStandard/Ipmi.h b/MdePkg/Include/IndustryStandard/Ipmi.h
index 4cb7494d7bca..0be12b659020 100644
--- a/MdePkg/Include/IndustryStandard/Ipmi.h
+++ b/MdePkg/Include/IndustryStandard/Ipmi.h
@@ -1,17 +1,12 @@
 /** @file
   IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1.
+  IPMI Platform Management FRU Information Storage Definition v1.0 Revision 1.3.
 
   See IPMI specification, Appendix G, Command Assignments
   and Appendix H, Sub-function Assignments.
 
-  Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
 #ifndef _IPMI_H_
@@ -26,4 +21,35 @@
 #include <IndustryStandard/IpmiNetFnTransport.h>
 #include <IndustryStandard/IpmiNetFnGroupExtension.h>
 
+#include <IndustryStandard/IpmiFruInformationStorage.h>
+
+//
+// Generic Completion Codes definitions
+//
+#define IPMI_COMP_CODE_NORMAL                           0x00
+#define IPMI_COMP_CODE_NODE_BUSY                        0xC0
+#define IPMI_COMP_CODE_INVALID_COMMAND                  0xC1
+#define IPMI_COMP_CODE_INVALID_FOR_GIVEN_LUN            0xC2
+#define IPMI_COMP_CODE_TIMEOUT                          0xC3
+#define IPMI_COMP_CODE_OUT_OF_SPACE                     0xC4
+#define IPMI_COMP_CODE_RESERVATION_CANCELED_OR_INVALID  0xC5
+#define IPMI_COMP_CODE_REQUEST_DATA_TRUNCATED           0xC6
+#define IPMI_COMP_CODE_INVALID_REQUEST_DATA_LENGTH      0xC7
+#define IPMI_COMP_CODE_REQUEST_EXCEED_LIMIT             0xC8
+#define IPMI_COMP_CODE_OUT_OF_RANGE                     0xC9
+#define IPMI_COMP_CODE_CANNOT_RETURN                    0xCA
+#define IPMI_COMP_CODE_NOT_PRESENT                      0xCB
+#define IPMI_COMP_CODE_INVALID_DATA_FIELD               0xCC
+#define IPMI_COMP_CODE_COMMAND_ILLEGAL                  0xCD
+#define IPMI_COMP_CODE_CMD_RESP_NOT_PROVIDED            0xCE
+#define IPMI_COMP_CODE_FAIL_DUP_REQUEST                 0xCF
+#define IPMI_COMP_CODE_SDR_REP_IN_UPDATE_MODE           0xD0
+#define IPMI_COMP_CODE_DEV_IN_FW_UPDATE_MODE            0xD1
+#define IPMI_COMP_CODE_BMC_INIT_IN_PROGRESS             0xD2
+#define IPMI_COMP_CODE_DEST_UNAVAILABLE                 0xD3
+#define IPMI_COMP_CODE_INSUFFICIENT_PRIVILEGE           0xD4
+#define IPMI_COMP_CODE_UNSUPPORTED_IN_PRESENT_STATE     0xD5
+#define IPMI_COMP_CODE_SUBFUNCTION_DISABLED             0xD6
+#define IPMI_COMP_CODE_UNSPECIFIED                      0xFF
+
 #endif
diff --git a/MdePkg/Include/IndustryStandard/IpmiFruInformationStorage.h b/MdePkg/Include/IndustryStandard/IpmiFruInformationStorage.h
new file mode 100644
index 000000000000..402b586ef109
--- /dev/null
+++ b/MdePkg/Include/IndustryStandard/IpmiFruInformationStorage.h
@@ -0,0 +1,86 @@
+/** @file
+  IPMI Platform Management FRU Information Storage Definitions
+
+  This file contains the definitions for:
+    Common Header Format (Chapter 8)
+    MultiRecord Header (Section 16.1)
+
+  Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+    - IPMI Platform Management FRU Information Storage Definition v1.0 Revision
+      1.3, Dated March 24, 2015.
+      https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/ipmi-platform-mgt-fru-info-storage-def-v1-0-rev-1-3-spec-update.pdf
+**/
+
+#ifndef _IPMI_FRU_INFORMATION_STORAGE_H_
+#define _IPMI_FRU_INFORMATION_STORAGE_H_
+
+#pragma pack(1)
+
+//
+//  Structure definitions for FRU Common Header
+//
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT8  FormatVersionNumber:4;
+    UINT8  Reserved:4;
+  } Bits;
+  ///
+  /// All bit fields as a 8-bit value
+  ///
+  UINT8  Uint8;
+} IPMI_FRU_COMMON_HEADER_FORMAT_VERSION;
+
+typedef struct {
+  IPMI_FRU_COMMON_HEADER_FORMAT_VERSION  FormatVersion;
+  UINT8                                  InternalUseStartingOffset;
+  UINT8                                  ChassisInfoStartingOffset;
+  UINT8                                  BoardAreaStartingOffset;
+  UINT8                                  ProductInfoStartingOffset;
+  UINT8                                  MultiRecInfoStartingOffset;
+  UINT8                                  Pad;
+  UINT8                                  Checksum;
+} IPMI_FRU_COMMON_HEADER;
+
+//
+//  Structure definition for FRU MultiRecord Header
+//
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT8  RecordFormatVersion:4;
+    UINT8  Reserved:3;
+    UINT8  EndofList:1;
+  } Bits;
+  ///
+  /// All bit fields as a 8-bit value
+  ///
+  UINT8  Uint8;
+} IPMI_FRU_MULTI_RECORD_HEADER_FORMAT_VERSION;
+
+typedef struct {
+  UINT8                                        RecordTypeId;
+  IPMI_FRU_MULTI_RECORD_HEADER_FORMAT_VERSION  FormatVersion;
+  UINT8                                        RecordLength;
+  UINT8                                        RecordChecksum;
+  UINT8                                        HeaderChecksum;
+} IPMI_FRU_MULTI_RECORD_HEADER;
+
+//
+//  Structure definition for System UUID Subrecord with checksum.
+//
+typedef struct {
+  UINT8       RecordCheckSum;
+  UINT8       SubRecordId;
+  EFI_GUID    Uuid;
+} IPMI_SYSTEM_UUID_SUB_RECORD_WITH_CHECKSUM;
+
+#pragma pack()
+#endif
diff --git a/MdePkg/Include/IndustryStandard/IpmiNetFnApp.h b/MdePkg/Include/IndustryStandard/IpmiNetFnApp.h
index 2d2d8e7c3681..499175f1c430 100644
--- a/MdePkg/Include/IndustryStandard/IpmiNetFnApp.h
+++ b/MdePkg/Include/IndustryStandard/IpmiNetFnApp.h
@@ -11,14 +11,8 @@
   See IPMI specification, Appendix G, Command Assignments
   and Appendix H, Sub-function Assignments.
 
-  Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
 #ifndef _IPMI_NET_FN_APP_H_
@@ -42,27 +36,48 @@
 //
 //  Constants and Structure definitions for "Get Device ID" command to follow here
 //
+typedef union {
+  struct {
+    UINT8  DeviceRevision : 4;
+    UINT8  Reserved : 3;
+    UINT8  DeviceSdr : 1;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_GET_DEVICE_ID_DEVICE_REV;
+
+typedef union {
+  struct {
+    UINT8  MajorFirmwareRev : 7;
+    UINT8  UpdateMode : 1;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_GET_DEVICE_ID_FIRMWARE_REV_1;
+
+typedef union {
+  struct {
+    UINT8  SensorDeviceSupport : 1;
+    UINT8  SdrRepositorySupport : 1;
+    UINT8  SelDeviceSupport : 1;
+    UINT8  FruInventorySupport : 1;
+    UINT8  IpmbMessageReceiver : 1;
+    UINT8  IpmbMessageGenerator : 1;
+    UINT8  BridgeSupport : 1;
+    UINT8  ChassisSupport : 1;
+  } Bits;
+  UINT8    Uint8;
+} IPMI_GET_DEVICE_ID_DEVICE_SUPPORT;
+
 typedef struct {
-  UINT8   CompletionCode;
-  UINT8   DeviceId;
-  UINT8   DeviceRevision : 4;
-  UINT8   Reserved : 3;
-  UINT8   DeviceSdr : 1;
-  UINT8   MajorFirmwareRev : 7;
-  UINT8   UpdateMode : 1;
-  UINT8   MinorFirmwareRev;
-  UINT8   SpecificationVersion;
-  UINT8   SensorDeviceSupport : 1;
-  UINT8   SdrRepositorySupport : 1;
-  UINT8   SelDeviceSupport : 1;
-  UINT8   FruInventorySupport : 1;
-  UINT8   IpmbMessageReceiver : 1;
-  UINT8   IpmbMessageGenerator : 1;
-  UINT8   BridgeSupport : 1;
-  UINT8   ChassisSupport : 1;
-  UINT8   ManufacturerId[3];
-  UINT16  ProductId;
-  UINT32  AuxFirmwareRevInfo;
+  UINT8                              CompletionCode;
+  UINT8                              DeviceId;
+  IPMI_GET_DEVICE_ID_DEVICE_REV      DeviceRevision;
+  IPMI_GET_DEVICE_ID_FIRMWARE_REV_1  FirmwareRev1;
+  UINT8                              MinorFirmwareRev;
+  UINT8                              SpecificationVersion;
+  IPMI_GET_DEVICE_ID_DEVICE_SUPPORT  DeviceSupport;
+  UINT8                              ManufacturerId[3];
+  UINT16                             ProductId;
+  UINT32                             AuxFirmwareRevInfo;
 } IPMI_GET_DEVICE_ID_RESPONSE;
 
 
@@ -128,11 +143,54 @@ typedef struct {
 //
 //  Constants and Structure definitions for "Set ACPI Power State" command to follow here
 //
+
+//
+//  Definitions for System Power State
+//
+// Working
+#define IPMI_SYSTEM_POWER_STATE_S0_G0        0x0
+#define IPMI_SYSTEM_POWER_STATE_S1           0x1
+#define IPMI_SYSTEM_POWER_STATE_S2           0x2
+#define IPMI_SYSTEM_POWER_STATE_S3           0x3
+#define IPMI_SYSTEM_POWER_STATE_S4           0x4
+// Soft off
+#define IPMI_SYSTEM_POWER_STATE_S5_G2        0x5
+// Sent when message source cannot differentiate between S4 and S5
+#define IPMI_SYSTEM_POWER_STATE_S4_S5        0x6
+// Mechanical off
+#define IPMI_SYSTEM_POWER_STATE_G3           0x7
+// Sleeping - cannot differentiate between S1-S3
+#define IPMI_SYSTEM_POWER_STATE_SLEEPING     0x8
+// Sleeping - cannot differentiate between S1-S4
+#define IPMI_SYSTEM_POWER_STATE_G1_SLEEPING  0x9
+// S5 entered by override
+#define IPMI_SYSTEM_POWER_STATE_OVERRIDE     0xA
+#define IPMI_SYSTEM_POWER_STATE_LEGACY_ON    0x20
+#define IPMI_SYSTEM_POWER_STATE_LEGACY_OFF   0x21
+#define IPMI_SYSTEM_POWER_STATE_UNKNOWN      0x2A
+#define IPMI_SYSTEM_POWER_STATE_NO_CHANGE    0x7F
+
+//
+//  Definitions for Device Power State
+//
+#define IPMI_DEVICE_POWER_STATE_D0           0x0
+#define IPMI_DEVICE_POWER_STATE_D1           0x1
+#define IPMI_DEVICE_POWER_STATE_D2           0x2
+#define IPMI_DEVICE_POWER_STATE_D3           0x3
+#define IPMI_DEVICE_POWER_STATE_UNKNOWN      0x2A
+#define IPMI_DEVICE_POWER_STATE_NO_CHANGE    0x7F
+
+typedef union {
+  struct {
+    UINT8  PowerState  : 7;
+    UINT8  StateChange : 1;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_ACPI_POWER_STATE;
+
 typedef struct {
-  UINT8  AcpiSystemPowerState  : 7;
-  UINT8  AcpiSystemStateChange : 1;
-  UINT8  AcpiDevicePowerState  : 7;
-  UINT8  AcpiDeviceStateChange : 1;
+  IPMI_ACPI_POWER_STATE  SystemPowerState;
+  IPMI_ACPI_POWER_STATE  DevicePowerState;
 } IPMI_SET_ACPI_POWER_STATE_REQUEST;
 
 //
@@ -170,26 +228,77 @@ typedef struct {
 #define IPMI_APP_RESET_WATCHDOG_TIMER  0x22
 
 //
-//  Constants and Structure definitions for "Reset WatchDog Timer" command to follow here
+//  Definitions for Set WatchDog Timer command
 //
-typedef struct {
-  UINT8 TimerUse : 3;
-  UINT8 Reserved : 3;
-  UINT8 TimerRunning : 1;
-  UINT8 TimerUseExpirationFlagLog : 1;
+#define IPMI_APP_SET_WATCHDOG_TIMER  0x24
+
+//
+//  Constants and Structure definitions for "Set WatchDog Timer" command to follow here
+//
+
+//
+// Definitions for watchdog timer use
+//
+#define IPMI_WATCHDOG_TIMER_BIOS_FRB2  0x1
+#define IPMI_WATCHDOG_TIMER_BIOS_POST  0x2
+#define IPMI_WATCHDOG_TIMER_OS_LOADER  0x3
+#define IPMI_WATCHDOG_TIMER_SMS        0x4
+#define IPMI_WATCHDOG_TIMER_OEM        0x5
+
+//
+//  Structure definition for timer Use
+//
+typedef union {
+  struct {
+    UINT8  TimerUse : 3;
+    UINT8  Reserved : 3;
+    UINT8  TimerRunning : 1;
+    UINT8  TimerUseExpirationFlagLog : 1;
+  } Bits;
+  UINT8  Uint8;
 } IPMI_WATCHDOG_TIMER_USE;
 
 //
-//  Definitions for Set WatchDog Timer command
+//  Definitions for watchdog timeout action
 //
-#define IPMI_APP_SET_WATCHDOG_TIMER  0x24
+#define IPMI_WATCHDOG_TIMER_ACTION_NO_ACTION    0x0
+#define IPMI_WATCHDOG_TIMER_ACTION_HARD_RESET   0x1
+#define IPMI_WATCHDOG_TIMER_ACTION_POWER_DONW   0x2
+#define IPMI_WATCHDOG_TIMER_ACTION_POWER_CYCLE  0x3
 
 //
-//  Constants and Structure definitions for "Set WatchDog Timer" command to follow here
+//  Definitions for watchdog pre-timeout interrupt
+//
+#define IPMI_WATCHDOG_PRE_TIMEOUT_INTERRUPT_NONE       0x0
+#define IPMI_WATCHDOG_PRE_TIMEOUT_INTERRUPT_SMI        0x1
+#define IPMI_WATCHDOG_PRE_TIMEOUT_INTERRUPT_NMI        0x2
+#define IPMI_WATCHDOG_PRE_TIMEOUT_INTERRUPT_MESSAGING  0x3
+
+//
+//  Structure definitions for Timer Actions
+//
+typedef union {
+  struct {
+    UINT8  TimeoutAction : 3;
+    UINT8  Reserved1 : 1;
+    UINT8  PreTimeoutInterrupt : 3;
+    UINT8  Reserved2 : 1;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_WATCHDOG_TIMER_ACTIONS;
+
+//
+//  Bit definitions for Timer use expiration flags
 //
+#define IPMI_WATCHDOG_TIMER_EXPIRATION_FLAG_BIOS_FRB2  BIT1
+#define IPMI_WATCHDOG_TIMER_EXPIRATION_FLAG_BIOS_POST  BIT2
+#define IPMI_WATCHDOG_TIMER_EXPIRATION_FLAG_OS_LOAD    BIT3
+#define IPMI_WATCHDOG_TIMER_EXPIRATION_FLAG_SMS_OS     BIT4
+#define IPMI_WATCHDOG_TIMER_EXPIRATION_FLAG_OEM        BIT5
+
 typedef struct {
   IPMI_WATCHDOG_TIMER_USE         TimerUse;
-  UINT8                           TimerActions;
+  IPMI_WATCHDOG_TIMER_ACTIONS     TimerActions;
   UINT8                           PretimeoutInterval;
   UINT8                           TimerUseExpirationFlagsClear;
   UINT16                          InitialCountdownValue;
@@ -206,7 +315,7 @@ typedef struct {
 typedef struct {
   UINT8                           CompletionCode;
   IPMI_WATCHDOG_TIMER_USE         TimerUse;
-  UINT8                           TimerActions;
+  IPMI_WATCHDOG_TIMER_ACTIONS     TimerActions;
   UINT8                           PretimeoutInterval;
   UINT8                           TimerUseExpirationFlagsClear;
   UINT16                          InitialCountdownValue;
@@ -225,6 +334,23 @@ typedef struct {
 //
 //  Constants and Structure definitions for "Set BMC Global Enables " command to follow here
 //
+typedef union {
+  struct {
+    UINT8  ReceiveMessageQueueInterrupt : 1;
+    UINT8  EventMessageBufferFullInterrupt : 1;
+    UINT8  EventMessageBuffer : 1;
+    UINT8  SystemEventLogging : 1;
+    UINT8  Reserved : 1;
+    UINT8  Oem0Enable : 1;
+    UINT8  Oem1Enable : 1;
+    UINT8  Oem2Enable : 1;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_BMC_GLOBAL_ENABLES;
+
+typedef struct {
+  IPMI_BMC_GLOBAL_ENABLES  SetEnables;
+} IPMI_SET_BMC_GLOBAL_ENABLES_REQUEST;
 
 //
 //  Definitions for Get BMC Global Enables command
@@ -234,6 +360,10 @@ typedef struct {
 //
 //  Constants and Structure definitions for "Get BMC Global Enables " command to follow here
 //
+typedef struct {
+  UINT8                    CompletionCode;
+  IPMI_BMC_GLOBAL_ENABLES  GetEnables;
+} IPMI_GET_BMC_GLOBAL_ENABLES_RESPONSE;
 
 //
 //  Definitions for Clear Message Flags command
@@ -243,6 +373,23 @@ typedef struct {
 //
 //  Constants and Structure definitions for "Clear Message Flags" command to follow here
 //
+typedef union {
+  struct {
+    UINT8  ReceiveMessageQueue : 1;
+    UINT8  EventMessageBuffer : 1;
+    UINT8  Reserved1 : 1;
+    UINT8  WatchdogPerTimeoutInterrupt : 1;
+    UINT8  Reserved2 : 1;
+    UINT8  Oem0 : 1;
+    UINT8  Oem1 : 1;
+    UINT8  Oem2 : 1;
+  } Bits;
+  UINT8    Uint8;
+} IPMI_MESSAGE_FLAGS;
+
+typedef struct {
+  IPMI_MESSAGE_FLAGS  ClearFlags;
+} IPMI_CLEAR_MESSAGE_FLAGS_REQUEST;
 
 //
 //  Definitions for Get Message Flags command
@@ -252,6 +399,10 @@ typedef struct {
 //
 //  Constants and Structure definitions for "Get Message Flags" command to follow here
 //
+typedef struct {
+  UINT8               CompletionCode;
+  IPMI_MESSAGE_FLAGS  GetFlags;
+} IPMI_GET_MESSAGE_FLAGS_RESPONSE;
 
 //
 //  Definitions for Enable Message Channel Receive command
@@ -270,6 +421,19 @@ typedef struct {
 //
 //  Constants and Structure definitions for "Get Message" command to follow here
 //
+typedef union {
+  struct {
+    UINT8  ChannelNumber : 4;
+    UINT8  InferredPrivilegeLevel : 4;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_GET_MESSAGE_CHANNEL_NUMBER;
+
+typedef struct {
+  UINT8                            CompletionCode;
+  IPMI_GET_MESSAGE_CHANNEL_NUMBER  ChannelNumber;
+  UINT8                            MessageData[0];
+} IPMI_GET_MESSAGE_RESPONSE;
 
 //
 //  Definitions for Send Message command
@@ -279,6 +443,26 @@ typedef struct {
 //
 //  Constants and Structure definitions for "Send Message" command to follow here
 //
+typedef union {
+  struct {
+    UINT8  ChannelNumber : 4;
+    UINT8  Authentication : 1;
+    UINT8  Encryption : 1;
+    UINT8  Tracking : 2;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_SEND_MESSAGE_CHANNEL_NUMBER;
+
+typedef struct {
+  UINT8                             CompletionCode;
+  IPMI_SEND_MESSAGE_CHANNEL_NUMBER  ChannelNumber;
+  UINT8                             MessageData[0];
+} IPMI_SEND_MESSAGE_REQUEST;
+
+typedef struct {
+  UINT8  CompletionCode;
+  UINT8  ResponseData[0];
+} IPMI_SEND_MESSAGE_RESPONSE;
 
 //
 //  Definitions for Read Event Message Buffer command
@@ -387,22 +571,65 @@ typedef struct {
 //
 //  Constants and Structure definitions for "Get Channel Access" command to follow here
 //
+
+//
+//  Definitions for channel access memory type in Get Channel Access command request
+//
+#define IPMI_CHANNEL_ACCESS_MEMORY_TYPE_NON_VOLATILE              0x1
+#define IPMI_CHANNEL_ACCESS_MEMORY_TYPE_PRESENT_VOLATILE_SETTING  0x2
+
+//
+//  Definitions for channel access modes in Get Channel Access command response
+//
+#define IPMI_CHANNEL_ACCESS_MODES_DISABLED          0x0
+#define IPMI_CHANNEL_ACCESS_MODES_PRE_BOOT_ONLY     0x1
+#define IPMI_CHANNEL_ACCESS_MODES_ALWAYS_AVAILABLE  0x2
+#define IPMI_CHANNEL_ACCESS_MODES_SHARED            0x3
+
+typedef union {
+  struct {
+    UINT8  ChannelNo : 4;
+    UINT8  Reserved : 4;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_GET_CHANNEL_ACCESS_CHANNEL_NUMBER;
+
+typedef union {
+  struct {
+    UINT8  Reserved : 6;
+    UINT8  MemoryType : 2;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_GET_CHANNEL_ACCESS_TYPE;
+
 typedef struct {
-  UINT8  ChannelNo : 4;
-  UINT8  Reserve1 : 4;
-  UINT8  Reserve2 : 6;
-  UINT8  MemoryType : 2;
+  IPMI_GET_CHANNEL_ACCESS_CHANNEL_NUMBER  ChannelNumber;
+  IPMI_GET_CHANNEL_ACCESS_TYPE            AccessType;
 } IPMI_GET_CHANNEL_ACCESS_REQUEST;
 
+typedef union {
+  struct {
+    UINT8  AccessMode : 3;
+    UINT8  UserLevelAuthEnabled : 1;
+    UINT8  MessageAuthEnable : 1;
+    UINT8  Alert : 1;
+    UINT8  Reserved : 2;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_GET_CHANNEL_ACCESS_CHANNEL_ACCESS;
+
+typedef union {
+  struct {
+    UINT8  ChannelPriviledgeLimit : 4;
+    UINT8  Reserved : 4;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_GET_CHANNEL_ACCESS_PRIVILEGE_LIMIT;
+
 typedef struct {
-  UINT8  CompletionCode;
-  UINT8  AccessMode : 3;
-  UINT8  UserLevelAuthEnabled : 1;
-  UINT8  MessageAuthEnable : 1;
-  UINT8  Alert : 1;
-  UINT8  Reserve1 : 2;
-  UINT8  ChannelPriviledgeLimit : 4;
-  UINT8  Reserve2 : 4;
+  UINT8                                    CompletionCode;
+  IPMI_GET_CHANNEL_ACCESS_CHANNEL_ACCESS   ChannelAccess;
+  IPMI_GET_CHANNEL_ACCESS_PRIVILEGE_LIMIT  PrivilegeLimit;
 } IPMI_GET_CHANNEL_ACCESS_RESPONSE;
 
 //
@@ -413,18 +640,78 @@ typedef struct {
 //
 //  Constants and Structure definitions for "Get Channel Info" command to follow here
 //
+
+//
+//  Definitions for channel media type
+//
+// IPMB (I2C)
+#define IPMI_CHANNEL_MEDIA_TYPE_IPMB              0x1
+// ICMB v1.0
+#define IPMI_CHANNEL_MEDIA_TYPE_ICMB_1_0          0x2
+// ICMB v0.9
+#define IPMI_CHANNEL_MEDIA_TYPE_ICMB_0_9          0x3
+// 802.3 LAN
+#define IPMI_CHANNEL_MEDIA_TYPE_802_3_LAN         0x4
+// Asynch. Serial/Modem (RS-232)
+#define IPMI_CHANNEL_MEDIA_TYPE_RS_232            0x5
+// Other LAN
+#define IPMI_CHANNEL_MEDIA_TYPE_OTHER_LAN         0x6
+// PCI SMBus
+#define IPMI_CHANNEL_MEDIA_TYPE_PCI_SM_BUS        0x7
+// SMBus v1.0/1.1
+#define IPMI_CHANNEL_MEDIA_TYPE_SM_BUS_V1         0x8
+// SMBus v2.0
+#define IPMI_CHANNEL_MEDIA_TYPE_SM_BUS_V2         0x9
+// USB 1.x
+#define IPMI_CHANNEL_MEDIA_TYPE_USB1              0xA
+// USB 2.x
+#define IPMI_CHANNEL_MEDIA_TYPE_USB2              0xB
+// System Interface (KCS, SMIC, or BT)
+#define IPMI_CHANNEL_MEDIA_TYPE_SYSTEM_INTERFACE  0xC
+// OEM
+#define IPMI_CHANNEL_MEDIA_TYPE_OEM_START         0x60
+#define IPMI_CHANNEL_MEDIA_TYPE_OEM_END           0x7F
+
+typedef union {
+  struct {
+    UINT8  ChannelNo : 4;
+    UINT8  Reserved : 4;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_CHANNEL_INFO_CHANNEL_NUMBER;
+
+typedef union {
+  struct {
+    UINT8  ChannelMediumType : 7;
+    UINT8  Reserved : 1;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_CHANNEL_INFO_MEDIUM_TYPE;
+
+typedef union {
+  struct {
+    UINT8  ChannelProtocolType : 5;
+    UINT8  Reserved : 3;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_CHANNEL_INFO_PROTOCOL_TYPE;
+
+typedef union {
+  struct {
+    UINT8  ActiveSessionCount : 6;
+    UINT8  SessionSupport : 2;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_CHANNEL_INFO_SESSION_SUPPORT;
+
 typedef struct {
   UINT8   CompletionCode;
-  UINT8   ChannelNo : 4;
-  UINT8   Reserve1 : 4;
-  UINT8   ChannelMediumType : 7;
-  UINT8   Reserve2 : 1;
-  UINT8   ChannelProtocolType : 5;
-  UINT8   Reserve3 : 3;
-  UINT8   ActiveSessionCount : 6;
-  UINT8   SessionSupport : 2;
-  UINT8   VendorId[3];
-  UINT16  AuxChannelInfo;
+  IPMI_CHANNEL_INFO_CHANNEL_NUMBER   ChannelNumber;
+  IPMI_CHANNEL_INFO_MEDIUM_TYPE      MediumType;
+  IPMI_CHANNEL_INFO_PROTOCOL_TYPE    ProtocolType;
+  IPMI_CHANNEL_INFO_SESSION_SUPPORT  SessionSupport;
+  UINT8                              VendorId[3];
+  UINT16                             AuxChannelInfo;
 } IPMI_GET_CHANNEL_INFO_RESPONSE;
 
 //
@@ -453,6 +740,69 @@ typedef struct {
 //
 //  Constants and Structure definitions for "Get User Access" command to follow here
 //
+typedef union {
+  struct {
+    UINT8  ChannelNo : 4;
+    UINT8  Reserved : 4;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_GET_USER_ACCESS_CHANNEL_NUMBER;
+
+typedef union {
+  struct {
+    UINT8  UserId : 6;
+    UINT8  Reserved : 2;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_USER_ID;
+
+typedef struct {
+  IPMI_GET_USER_ACCESS_CHANNEL_NUMBER  ChannelNumber;
+  IPMI_USER_ID                         UserId;
+} IPMI_GET_USER_ACCESS_REQUEST;
+
+typedef union {
+  struct {
+    UINT8  MaxUserId : 6;
+    UINT8  Reserved : 2;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_GET_USER_ACCESS_MAX_USER_ID;
+
+typedef union {
+  struct {
+    UINT8  CurrentUserId : 6;
+    UINT8  UserIdEnableStatus : 2;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_GET_USER_ACCESS_CURRENT_USER;
+
+typedef union {
+  struct {
+    UINT8  FixedUserId : 6;
+    UINT8  Reserved : 2;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_GET_USER_ACCESS_FIXED_NAME_USER;
+
+typedef union {
+  struct {
+    UINT8  UserPrivilegeLimit : 4;
+    UINT8  EnableIpmiMessaging : 1;
+    UINT8  EnableUserLinkAuthetication : 1;
+    UINT8  UserAccessAvailable : 1;
+    UINT8  Reserved : 1;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_GET_USER_ACCESS_CHANNEL_ACCESS;
+
+typedef struct {
+  UINT8                                 CompletionCode;
+  IPMI_GET_USER_ACCESS_MAX_USER_ID      MaxUserId;
+  IPMI_GET_USER_ACCESS_CURRENT_USER     CurrentUser;
+  IPMI_GET_USER_ACCESS_FIXED_NAME_USER  FixedNameUser;
+  IPMI_GET_USER_ACCESS_CHANNEL_ACCESS   ChannelAccess;
+} IPMI_GET_USER_ACCESS_RESPONSE;
 
 //
 //  Definitions for Set User Name command
@@ -462,6 +812,10 @@ typedef struct {
 //
 //  Constants and Structure definitions for "Set User Name" command to follow here
 //
+typedef struct {
+  IPMI_USER_ID  UserId;
+  UINT8         UserName[16];
+} IPMI_SET_USER_NAME_REQUEST;
 
 //
 //  Definitions for Get User Name command
@@ -471,6 +825,14 @@ typedef struct {
 //
 //  Constants and Structure definitions for "Get User Name" command to follow here
 //
+typedef struct {
+  IPMI_USER_ID  UserId;
+} IPMI_GET_USER_NAME_REQUEST;
+
+typedef struct {
+  UINT8  CompletionCode;
+  UINT8  UserName[16];
+} IPMI_GET_USER_NAME_RESPONSE;
 
 //
 //  Definitions for Set User Password command
@@ -482,6 +844,43 @@ typedef struct {
 //
 
 //
+//  Definitions for Set User password command operation type
+//
+#define IPMI_SET_USER_PASSWORD_OPERATION_TYPE_DISABLE_USER   0x0
+#define IPMI_SET_USER_PASSWORD_OPERATION_TYPE_ENABLE_USER    0x1
+#define IPMI_SET_USER_PASSWORD_OPERATION_TYPE_SET_PASSWORD   0x2
+#define IPMI_SET_USER_PASSWORD_OPERATION_TYPE_TEST_PASSWORD  0x3
+
+//
+//  Definitions for Set user password command password size
+//
+#define IPMI_SET_USER_PASSWORD_PASSWORD_SIZE_16  0x0
+#define IPMI_SET_USER_PASSWORD_PASSWORD_SIZE_20  0x1
+
+typedef union {
+  struct {
+    UINT8  UserId : 6;
+    UINT8  Reserved : 1;
+    UINT8  PasswordSize : 1;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_SET_USER_PASSWORD_USER_ID;
+
+typedef union {
+  struct {
+    UINT8  Operation : 2;
+    UINT8  Reserved : 6;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_SET_USER_PASSWORD_OPERATION;
+
+typedef struct {
+  IPMI_SET_USER_PASSWORD_USER_ID    UserId;
+  IPMI_SET_USER_PASSWORD_OPERATION  Operation;
+  UINT8                             PasswordData[0];  // 16 or 20 bytes, depending on the 'PasswordSize' field
+} IPMI_SET_USER_PASSWORD_REQUEST;
+
+//
 //  Below is Definitions for RMCP+ Support and Payload Commands (Chapter 24)
 //
 
@@ -619,5 +1018,12 @@ typedef struct {
 //  Constants and Structure definitions for "Get System Interface Capabilities" command to follow here
 //
 
+//
+//  Definitions for Get System Interface Capabilities command SSIF transaction support
+//
+#define IPMI_GET_SYSTEM_INTERFACE_CAPABILITIES_SSIF_TRANSACTION_SUPPORT_SINGLE_PARTITION_RW             0x0
+#define IPMI_GET_SYSTEM_INTERFACE_CAPABILITIES_SSIF_TRANSACTION_SUPPORT_MULTI_PARTITION_RW              0x1
+#define IPMI_GET_SYSTEM_INTERFACE_CAPABILITIES_SSIF_TRANSACTION_SUPPORT_MULTI_PARTITION_RW_WITH_MIDDLE  0x2
+
 #pragma pack()
 #endif
diff --git a/MdePkg/Include/IndustryStandard/IpmiNetFnBridge.h b/MdePkg/Include/IndustryStandard/IpmiNetFnBridge.h
index 7f174fdc6975..640a5402e305 100644
--- a/MdePkg/Include/IndustryStandard/IpmiNetFnBridge.h
+++ b/MdePkg/Include/IndustryStandard/IpmiNetFnBridge.h
@@ -7,13 +7,7 @@
   and Appendix H, Sub-function Assignments.
 
   Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
 #ifndef _IPMI_NET_FN_BRIDGE_H_
@@ -133,12 +127,12 @@
 //
 
 //
-//  Definitions for Prepare for Discoveery command
+//  Definitions for Prepare for Discovery command
 //
 #define IPMI_BRIDGE_PREPARE_FOR_DISCOVERY  0x10
 
 //
-//  Constants and Structure definitions for "Prepare for Discoveery" command to follow here
+//  Constants and Structure definitions for "Prepare for Discovery" command to follow here
 //
 
 //
diff --git a/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h b/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h
index 833feeb9dd87..c20091fedcf2 100644
--- a/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h
+++ b/MdePkg/Include/IndustryStandard/IpmiNetFnChassis.h
@@ -7,14 +7,8 @@
   See IPMI specification, Appendix G, Command Assignments
   and Appendix H, Sub-function Assignments.
 
-  Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
 #ifndef _IPMI_NET_FN_CHASSIS_H_
@@ -38,6 +32,15 @@
 //
 //  Constants and Structure definitions for "Get Chassis Capabilities" command to follow here
 //
+typedef struct {
+  UINT8   CompletionCode;
+  UINT8   CapabilitiesFlags;
+  UINT8   ChassisFruInfoDeviceAddress;
+  UINT8   ChassisSDRDeviceAddress;
+  UINT8   ChassisSELDeviceAddress;
+  UINT8   ChassisSystemManagementDeviceAddress;
+  UINT8   ChassisBridgeDeviceAddress;
+} IPMI_GET_CHASSIS_CAPABILITIES_RESPONSE;
 
 //
 //  Definitions for Get Chassis Status command
@@ -47,6 +50,13 @@
 //
 //  Constants and Structure definitions for "Get Chassis Status" command to follow here
 //
+typedef struct {
+  UINT8   CompletionCode;
+  UINT8   CurrentPowerState;
+  UINT8   LastPowerEvent;
+  UINT8   MiscChassisState;
+  UINT8   FrontPanelButtonCapabilities;
+} IPMI_GET_CHASSIS_STATUS_RESPONSE;
 
 //
 //  Definitions for Chassis Control command
@@ -56,6 +66,17 @@
 //
 //  Constants and Structure definitions for "Chassis Control" command to follow here
 //
+typedef union {
+  struct {
+    UINT8  ChassisControl:4;
+    UINT8  Reserved:4;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_CHASSIS_CONTROL_CHASSIS_CONTROL;
+
+typedef struct {
+  IPMI_CHASSIS_CONTROL_CHASSIS_CONTROL  ChassisControl;
+} IPMI_CHASSIS_CONTROL_REQUEST;
 
 //
 //  Definitions for Chassis Reset command
@@ -92,6 +113,22 @@
 //
 //  Constants and Structure definitions for "Set Power Restore Policy" command to follow here
 //
+typedef union {
+  struct {
+    UINT8  PowerRestorePolicy : 3;
+    UINT8  Reserved : 5;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_POWER_RESTORE_POLICY;
+
+typedef struct {
+  IPMI_POWER_RESTORE_POLICY  PowerRestorePolicy;
+} IPMI_SET_POWER_RESTORE_POLICY_REQUEST;
+
+typedef struct {
+  UINT8   CompletionCode;
+  UINT8   PowerRestorePolicySupport;
+} IPMI_SET_POWER_RESTORE_POLICY_RESPONSE;
 
 //
 //  Definitions for Get System Restart Cause command
@@ -101,26 +138,31 @@
 //
 //  Constants and Structure definitions for "Get System Restart Cause" command to follow here
 //
-typedef enum {
-  Unknown,
-  ChassisControlCommand,
-  ResetViaPushButton,
-  PowerupViaPowerButton,
-  WatchdogExpiration,
-  Oem,
-  AutoPowerOnAlwaysRestore,
-  AutoPowerOnRestorePrevious,
-  ResetViaPef,
-  PowerCycleViaPef,
-  SoftReset,
-  PowerUpViaRtc
+#define IPMI_SYSTEM_RESTART_CAUSE_UNKNOWN                    0x0
+#define IPMI_SYSTEM_RESTART_CAUSE_CHASSIS_CONTROL_COMMAND    0x1
+#define IPMI_SYSTEM_RESTART_CAUSE_PUSHBUTTON_RESET           0x2
+#define IPMI_SYSTEM_RESTART_CAUSE_PUSHBUTTON_POWERUP         0x3
+#define IPMI_SYSTEM_RESTART_CAUSE_WATCHDOG_EXPIRE            0x4
+#define IPMI_SYSTEM_RESTART_CAUSE_OEM                        0x5
+#define IPMI_SYSTEM_RESTART_CAUSE_AUTO_POWER_ALWAYS_RESTORE  0x6
+#define IPMI_SYSTEM_RESTART_CAUSE_AUTO_POWER_RESTORE_PREV    0x7
+#define IPMI_SYSTEM_RESTART_CAUSE_PEF_RESET                  0x8
+#define IPMI_SYSTEM_RESTART_CAUSE_PEF_POWERCYCLE             0x9
+#define IPMI_SYSTEM_RESTART_CAUSE_SOFT_RESET                 0xA
+#define IPMI_SYSTEM_RESTART_CAUSE_RTC_POWERUP                0xB
+
+typedef union {
+  struct {
+    UINT8  Cause:4;
+    UINT8  Reserved:4;
+  } Bits;
+  UINT8  Uint8;
 } IPMI_SYSTEM_RESTART_CAUSE;
 
 typedef struct {
-  UINT8  CompletionCode;
-  UINT8  Cause:4;
-  UINT8  Reserved:4;
-  UINT8  ChannelNumber;
+  UINT8                      CompletionCode;
+  IPMI_SYSTEM_RESTART_CAUSE  RestartCause;
+  UINT8                      ChannelNumber;
 } IPMI_GET_SYSTEM_RESTART_CAUSE_RESPONSE;
 
 //
@@ -131,25 +173,39 @@ typedef struct {
 //
 //  Constants and Structure definitions for "Set System boot options" command to follow here
 //
+typedef union {
+  struct {
+    UINT8  ParameterSelector:7;
+    UINT8  MarkParameterInvalid:1;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_SET_BOOT_OPTIONS_PARAMETER_VALID;
+
 typedef struct {
-  UINT8    ParameterSelector:7;
-  UINT8    MarkParameterInvalid:1;
-  UINT8    ParameterData[1];
+  IPMI_SET_BOOT_OPTIONS_PARAMETER_VALID  ParameterValid;
+  UINT8                                  ParameterData[0];
 } IPMI_SET_BOOT_OPTIONS_REQUEST;
 
 //
-//  Definitions for Get System BOOT options command
+//  Definitions for Get System Boot options command
 //
 #define IPMI_CHASSIS_GET_SYSTEM_BOOT_OPTIONS 0x09
 
 //
 //  Constants and Structure definitions for "Get System boot options" command to follow here
 //
+typedef union {
+  struct {
+    UINT8  ParameterSelector:7;
+    UINT8  Reserved:1;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_GET_BOOT_OPTIONS_PARAMETER_SELECTOR;
+
 typedef struct {
-  UINT8    ParameterSelector:7;
-  UINT8    Reserved:1;
-  UINT8    SetSelector;
-  UINT8    BlockSelector;
+  IPMI_GET_BOOT_OPTIONS_PARAMETER_SELECTOR  ParameterSelector;
+  UINT8                                     SetSelector;
+  UINT8                                     BlockSelector;
 } IPMI_GET_BOOT_OPTIONS_REQUEST;
 
 typedef struct {
@@ -172,26 +228,49 @@ typedef struct {
 } IPMI_BOOT_INITIATOR;
 
 //
+// Definitions for boot option parameter selector
+//
+#define IPMI_BOOT_OPTIONS_PARAMETER_SELECTOR_SET_IN_PROGRESS             0x0
+#define IPMI_BOOT_OPTIONS_PARAMETER_SELECTOR_SERVICE_PARTITION_SELECTOR  0x1
+#define IPMI_BOOT_OPTIONS_PARAMETER_SELECTOR_SERVICE_PARTITION_SCAN      0x2
+#define IPMI_BOOT_OPTIONS_PARAMETER_SELECTOR_BMC_BOOT_FLAG               0x3
+#define IPMI_BOOT_OPTIONS_PARAMETER_BOOT_INFO_ACK                        0x4
+#define IPMI_BOOT_OPTIONS_PARAMETER_BOOT_FLAGS                           0x5
+#define IPMI_BOOT_OPTIONS_PARAMETER_BOOT_INITIATOR_INFO                  0x6
+#define IPMI_BOOT_OPTIONS_PARAMETER_BOOT_INITIATOR_MAILBOX               0x7
+#define IPMI_BOOT_OPTIONS_PARAMETER_OEM_BEGIN                            0x60
+#define IPMI_BOOT_OPTIONS_PARAMETER_OEM_END                              0x7F
+
+//
 // Response Parameters for IPMI Get Boot Options
 //
-typedef struct {
-  UINT8   SetInProgress: 2;
-  UINT8   Reserved: 6;
+typedef union {
+  struct {
+    UINT8  SetInProgress : 2;
+    UINT8  Reserved : 6;
+  } Bits;
+  UINT8  Uint8;
 } IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_0;
 
 typedef struct {
   UINT8   ServicePartitionSelector;
 } IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_1;
 
-typedef struct {
-  UINT8   ServicePartitionDiscovered:1;
-  UINT8   ServicePartitionScanRequest:1;
-  UINT8   Reserved: 5;
+typedef union {
+  struct {
+    UINT8  ServicePartitionDiscovered : 1;
+    UINT8  ServicePartitionScanRequest : 1;
+    UINT8  Reserved: 6;
+  } Bits;
+  UINT8  Uint8;
 } IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_2;
 
-typedef struct {
-  UINT8   BmcBootFlagValid: 5;
-  UINT8   Reserved: 3;
+typedef union {
+  struct {
+    UINT8  BmcBootFlagValid : 5;
+    UINT8  Reserved : 3;
+  } Bits;
+  UINT8  Uint8;
 } IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_3;
 
 typedef struct {
@@ -199,45 +278,101 @@ typedef struct {
   UINT8   BootInitiatorAcknowledgeData;
 } IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_4;
 
+//
+//  Definitions for the 'Boot device selector' field of Boot Option Parameters #5
+//
+#define IPMI_BOOT_DEVICE_SELECTOR_NO_OVERRIDE           0x0
+#define IPMI_BOOT_DEVICE_SELECTOR_PXE                   0x1
+#define IPMI_BOOT_DEVICE_SELECTOR_HARDDRIVE             0x2
+#define IPMI_BOOT_DEVICE_SELECTOR_HARDDRIVE_SAFE_MODE   0x3
+#define IPMI_BOOT_DEVICE_SELECTOR_DIAGNOSTIC_PARTITION  0x4
+#define IPMI_BOOT_DEVICE_SELECTOR_CD_DVD                0x5
+#define IPMI_BOOT_DEVICE_SELECTOR_BIOS_SETUP            0x6
+#define IPMI_BOOT_DEVICE_SELECTOR_REMOTE_FLOPPY         0x7
+#define IPMI_BOOT_DEVICE_SELECTOR_REMOTE_CD_DVD         0x8
+#define IPMI_BOOT_DEVICE_SELECTOR_PRIMARY_REMOTE_MEDIA  0x9
+#define IPMI_BOOT_DEVICE_SELECTOR_REMOTE_HARDDRIVE      0xB
+#define IPMI_BOOT_DEVICE_SELECTOR_FLOPPY                0xF
+
 #define BOOT_OPTION_HANDLED_BY_BIOS 0x01
 
+//
+//  Constant definitions for the 'BIOS Mux Control Override' field of Boot Option Parameters #5
+//
+#define BIOS_MUX_CONTROL_OVERRIDE_RECOMMEND_SETTING    0x00
+#define BIOS_MUX_CONTROL_OVERRIDE_FORCE_TO_BMC         0x01
+#define BIOS_MUX_CONTROL_OVERRIDE_FORCE_TO_SYSTEM      0x02
+
+typedef union {
+  struct {
+    UINT8  Reserved:5;
+    UINT8  BiosBootType:1;
+    UINT8  PersistentOptions:1;
+    UINT8  BootFlagValid:1;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_1;
+
+typedef union {
+  struct {
+    UINT8  LockReset:1;
+    UINT8  ScreenBlank:1;
+    UINT8  BootDeviceSelector:4;
+    UINT8  LockKeyboard:1;
+    UINT8  CmosClear:1;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_2;
+
+typedef union {
+  struct {
+    UINT8  ConsoleRedirection:2;
+    UINT8  LockSleep:1;
+    UINT8  UserPasswordBypass:1;
+    UINT8  ForceProgressEventTrap:1;
+    UINT8  BiosVerbosity:2;
+    UINT8  LockPower:1;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_3;
+
+typedef union {
+  struct {
+    UINT8  BiosMuxControlOverride:3;
+    UINT8  BiosSharedModeOverride:1;
+    UINT8  Reserved:4;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_4;
+
+typedef union {
+  struct {
+    UINT8  DeviceInstanceSelector:5;
+    UINT8  Reserved:3;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_5;
+
 typedef struct {
-  //
-  // Data 1
-  //
-  UINT8   Reserved0:6;
-  UINT8   PersistentOptions:1;
-  UINT8   BootFlagValid:1;
-  //
-  // Data 2
-  //
-  UINT8   LockReset:1;
-  UINT8   ScreenBlank:1;
-  UINT8   BootDeviceSelector:4;
-  UINT8   LockKeyboard:1;
-  UINT8   CmosClear:1;
-  //
-  //
-  // Data 3
-  UINT8   ConsoleRedirection:2;
-  UINT8   LockSleep:1;
-  UINT8   UserPasswordBypass:1;
-  UINT8   ForceProgressEventTrap:1;
-  UINT8   BiosVerbosity:2;
-  UINT8   LockPower:1;
-  //
-  // Data 4
-  //
-  UINT8   BiosMuxControlOverride:2;
-  UINT8   BiosSharedModeOverride:1;
-  UINT8   Reserved1:4;
+  IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_1  Data1;
+  IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_2  Data2;
+  IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_3  Data3;
+  IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_4  Data4;
+  IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5_DATA_5  Data5;
 } IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_5;
 
+typedef union {
+  struct {
+    UINT8  ChannelNumber:4;
+    UINT8  Reserved:4;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_BOOT_OPTIONS_CHANNEL_NUMBER;
+
 typedef struct {
-  UINT8   ChannelNumber:4;
-  UINT8   Reserved:4;
-  UINT8   SessionId[4];
-  UINT8   BootInfoTimeStamp[4];
+  IPMI_BOOT_OPTIONS_CHANNEL_NUMBER  ChannelNumber;
+  UINT8                             SessionId[4];
+  UINT8                             BootInfoTimeStamp[4];
 } IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_6;
 
 typedef struct {
@@ -256,13 +391,27 @@ typedef union {
   IPMI_BOOT_OPTIONS_RESPONSE_PARAMETER_7   Parm7;
 } IPMI_BOOT_OPTIONS_PARAMETERS;
 
+typedef union {
+  struct {
+    UINT8  ParameterVersion:4;
+    UINT8  Reserved:4;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_GET_BOOT_OPTIONS_PARAMETER_VERSION;
+
+typedef union {
+  struct {
+    UINT8  ParameterSelector:7;
+    UINT8  ParameterValid:1;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_GET_BOOT_OPTIONS_PARAMETER_VALID;
+
 typedef struct {
-  UINT8    CompletionCode;
-  UINT8    ParameterVersion:4;
-  UINT8    Reserved:4;
-  UINT8    ParameterSelector:7;
-  UINT8    ParameterValid:1;
-  UINT8    ParameterData[1];
+  UINT8                                    CompletionCode;
+  IPMI_GET_BOOT_OPTIONS_PARAMETER_VERSION  ParameterVersion;
+  IPMI_GET_BOOT_OPTIONS_PARAMETER_VALID    ParameterValid;
+  UINT8                                    ParameterData[0];
 } IPMI_GET_BOOT_OPTIONS_RESPONSE;
 
 //
@@ -270,17 +419,23 @@ typedef struct {
 //
 #define IPMI_CHASSIS_SET_FRONT_PANEL_BUTTON_ENABLES 0x0A
 
-typedef struct {
-  UINT8    DisablePoweroffButton:1;
-  UINT8    DisableResetButton:1;
-  UINT8    DisableDiagnosticInterruptButton:1;
-  UINT8    DisableStandbyButton:1;
-  UINT8    Reserved:4;
-} IPMI_CHASSIS_SET_FRONT_PANEL_BUTTON_ENABLES_REQUEST;
-
 //
 //  Constants and Structure definitions for "Set front panel button enables" command to follow here
 //
+typedef union {
+  struct {
+    UINT8  DisablePoweroffButton:1;
+    UINT8  DisableResetButton:1;
+    UINT8  DisableDiagnosticInterruptButton:1;
+    UINT8  DisableStandbyButton:1;
+    UINT8  Reserved:4;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_FRONT_PANEL_BUTTON_ENABLES;
+
+typedef struct {
+  IPMI_FRONT_PANEL_BUTTON_ENABLES  FrontPanelButtonEnables;
+} IPMI_CHASSIS_SET_FRONT_PANEL_BUTTON_ENABLES_REQUEST;
 
 //
 //  Definitions for Set Power Cycle Interval command
diff --git a/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h b/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h
index aba3c41d06c3..55886b16dcd6 100644
--- a/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h
+++ b/MdePkg/Include/IndustryStandard/IpmiNetFnFirmware.h
@@ -2,13 +2,7 @@
   IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1.
 
   Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
 #ifndef _IPMI_NET_FN_FIRMWARE_H_
diff --git a/MdePkg/Include/IndustryStandard/IpmiNetFnGroupExtension.h b/MdePkg/Include/IndustryStandard/IpmiNetFnGroupExtension.h
index 2a8ec6956703..fbadfcd7f0a6 100644
--- a/MdePkg/Include/IndustryStandard/IpmiNetFnGroupExtension.h
+++ b/MdePkg/Include/IndustryStandard/IpmiNetFnGroupExtension.h
@@ -2,13 +2,7 @@
   IPMI 2.0 definitions from the IPMI Specification Version 2.0, Revision 1.1.
 
   Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
 #ifndef _IPMI_NET_FN_GROUP_EXTENSION_H_
diff --git a/MdePkg/Include/IndustryStandard/IpmiNetFnSensorEvent.h b/MdePkg/Include/IndustryStandard/IpmiNetFnSensorEvent.h
index f9d851e6ca1c..dd090004921f 100644
--- a/MdePkg/Include/IndustryStandard/IpmiNetFnSensorEvent.h
+++ b/MdePkg/Include/IndustryStandard/IpmiNetFnSensorEvent.h
@@ -10,13 +10,7 @@
   and Appendix H, Sub-function Assignments.
 
   Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
 #ifndef _IPMI_NET_FN_SENSOR_EVENT_H_
diff --git a/MdePkg/Include/IndustryStandard/IpmiNetFnStorage.h b/MdePkg/Include/IndustryStandard/IpmiNetFnStorage.h
index 210db1e7e933..c69df8f303fe 100644
--- a/MdePkg/Include/IndustryStandard/IpmiNetFnStorage.h
+++ b/MdePkg/Include/IndustryStandard/IpmiNetFnStorage.h
@@ -10,14 +10,8 @@
   See IPMI specification, Appendix G, Command Assignments
   and Appendix H, Sub-function Assignments.
 
-  Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
 #ifndef _IPMI_NET_FN_STORAGE_H_
@@ -45,14 +39,23 @@
 //
 //  Constants and Structure definitions for "Get Fru Inventory Area Info" command to follow here
 //
+typedef struct {
+  UINT8  DeviceId;
+} IPMI_GET_FRU_INVENTORY_AREA_INFO_REQUEST;
+
+typedef struct {
+  UINT8   CompletionCode;
+  UINT16  InventoryAreaSize;
+  UINT8   AccessType;
+} IPMI_GET_FRU_INVENTORY_AREA_INFO_RESPONSE;
 
 //
-//  Definitions for Get Fru Data command
+//  Definitions for Read Fru Data command
 //
 #define IPMI_STORAGE_READ_FRU_DATA 0x11
 
 //
-//  Constants and Structure definitions for "Get Fru Data" command to follow here
+//  Constants and Structure definitions for "Read Fru Data" command to follow here
 //
 typedef struct {
   UINT8   FruDeviceId;
@@ -64,6 +67,18 @@ typedef struct {
   UINT8                Count;
 } IPMI_FRU_READ_COMMAND;
 
+typedef struct {
+  UINT8   DeviceId;
+  UINT16  InventoryOffset;
+  UINT8   CountToRead;
+} IPMI_READ_FRU_DATA_REQUEST;
+
+typedef struct {
+  UINT8   CompletionCode;
+  UINT8   CountReturned;
+  UINT8   Data[0];
+} IPMI_READ_FRU_DATA_RESPONSE;
+
 //
 //  Definitions for Write Fru Data command
 //
@@ -77,6 +92,17 @@ typedef struct {
   UINT8                FruData[16];
 } IPMI_FRU_WRITE_COMMAND;
 
+typedef struct {
+  UINT8   DeviceId;
+  UINT16  InventoryOffset;
+  UINT8   Data[0];
+} IPMI_WRITE_FRU_DATA_REQUEST;
+
+typedef struct {
+  UINT8   CompletionCode;
+  UINT8   CountWritten;
+} IPMI_WRITE_FRU_DATA_RESPONSE;
+
 //
 //  Below is Definitions for SDR Repository (Chapter 33)
 //
@@ -89,21 +115,28 @@ typedef struct {
 //
 //  Constants and Structure definitions for "Get SDR Repository Info" command to follow here
 //
+typedef union {
+  struct {
+    UINT8  SdrRepAllocInfoCmd : 1;
+    UINT8  SdrRepReserveCmd : 1;
+    UINT8  PartialAddSdrCmd : 1;
+    UINT8  DeleteSdrRepCmd : 1;
+    UINT8  Reserved : 1;
+    UINT8  SdrRepUpdateOp : 2;
+    UINT8  Overflow : 1;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_SDR_OPERATION_SUPPORT;
+
 typedef struct {
-  UINT8   CompletionCode;
-  UINT8   Version;
-  UINT16  RecordCount;
-  UINT16  FreeSpace;
-  UINT32  RecentAdditionTimeStamp;
-  UINT32  RecentEraseTimeStamp;
-  UINT8   SdrRepAllocInfoCmd : 1;
-  UINT8   SdrRepReserveCmd : 1;
-  UINT8   PartialAddSdrCmd : 1;
-  UINT8   DeleteSdrRepCmd : 1;
-  UINT8   Reserved : 1;
-  UINT8   SdrRepUpdateOp : 2;
-  UINT8   Overflow : 1;
-} IPMI_GET_SDR_REPOSITORY_INFO;
+  UINT8                       CompletionCode;
+  UINT8                       Version;
+  UINT16                      RecordCount;
+  UINT16                      FreeSpace;
+  UINT32                      RecentAdditionTimeStamp;
+  UINT32                      RecentEraseTimeStamp;
+  IPMI_SDR_OPERATION_SUPPORT  OperationSupport;
+} IPMI_GET_SDR_REPOSITORY_INFO_RESPONSE;
 
 //
 //  Definitions for Get SDR Repository Allocateion Info command
@@ -122,6 +155,10 @@ typedef struct {
 //
 //  Constants and Structure definitions for "Reserve SDR Repository" command to follow here
 //
+typedef struct {
+  UINT8  CompletionCode;
+  UINT8  ReservationId[2];  // Reservation ID. LS byte first.
+} IPMI_RESERVE_SDR_REPOSITORY_RESPONSE;
 
 //
 //  Definitions for Get SDR command
@@ -131,149 +168,201 @@ typedef struct {
 //
 //  Constants and Structure definitions for "Get SDR" command to follow here
 //
+typedef union {
+  struct {
+    UINT8  EventScanningEnabled : 1;
+    UINT8  EventScanningDisabled : 1;
+    UINT8  InitSensorType : 1;
+    UINT8  InitHysteresis : 1;
+    UINT8  InitThresholds : 1;
+    UINT8  InitEvent : 1;
+    UINT8  InitScanning : 1;
+    UINT8  SettableSensor : 1;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_SDR_RECORD_SENSOR_INIT;
+
+typedef union {
+  struct {
+    UINT8  EventMessageControl : 2;
+    UINT8  ThresholdAccessSupport : 2;
+    UINT8  HysteresisSupport : 2;
+    UINT8  ReArmSupport : 1;
+    UINT8  IgnoreSensor : 1;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_SDR_RECORD_SENSOR_CAP;
+
+typedef union {
+  struct {
+    UINT8  Linearization : 7;
+    UINT8  Reserved : 1;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_SDR_RECORD_LINEARIZATION;
+
+typedef union {
+  struct {
+    UINT8  Toleremce : 6;
+    UINT8  MHi : 2;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_SDR_RECORD_M_TOLERANCE;
+
+typedef union {
+  struct {
+    UINT8  AccuracyLow : 6;
+    UINT8  BHi : 2;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_SDR_RECORD_B_ACCURACY;
+
+typedef union {
+  struct {
+    UINT8  Reserved : 2;
+    UINT8  AccuracyExp : 2;
+    UINT8  AccuracyHi : 4;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_SDR_RECORD_ACCURACY_SENSOR_DIR;
+
+typedef union {
+  struct {
+    UINT8  BExp : 4;
+    UINT8  RExp : 4;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_SDR_RECORD_R_EXP_B_EXP;
+
+typedef union {
+  struct {
+    UINT8  NominalReadingSpscified : 1;
+    UINT8  NominalMaxSpscified : 1;
+    UINT8  NominalMinSpscified : 1;
+    UINT8  Reserved : 5;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_SDR_RECORD_ANALOG_FLAGS;
 
 typedef struct {
-  UINT16  RecordId;                     // 1
-  UINT8   Version;                      // 3
-  UINT8   RecordType;                   // 4
-  UINT8   RecordLength;                 // 5
-  UINT8   OwnerId;                      // 6
-  UINT8   OwnerLun;                     // 7
-  UINT8   SensorNumber;                 // 8
-  UINT8   EntityId;                     // 9
-  UINT8   EntityInstance;               // 10
-  UINT8   EventScanningEnabled : 1;     // 11
-  UINT8   EventScanningDisabled : 1;    // 11
-  UINT8   InitSensorType : 1;           // 11
-  UINT8   InitHysteresis : 1;           // 11
-  UINT8   InitThresholds : 1;           // 11
-  UINT8   InitEvent : 1;                // 11
-  UINT8   InitScanning : 1;             // 11
-  UINT8   Reserved : 1;                 // 11
-  UINT8   EventMessageControl : 2;      // 12
-  UINT8   ThresholdAccessSupport : 2;   // 12
-  UINT8   HysteresisSupport : 2;        // 12
-  UINT8   ReArmSupport : 1;             // 12
-  UINT8   IgnoreSensor : 1;             // 12
-  UINT8   SensorType;                   // 13
-  UINT8   EventType;                    // 14
-  UINT8   Reserved1[7];                 // 15
-  UINT8   UnitType;                     // 22
-  UINT8   Reserved2;                    // 23
-  UINT8   Linearization : 7;            // 24
-  UINT8   Reserved3 : 1;                // 24
-  UINT8   MLo;                          // 25
-  UINT8   Toleremce : 6;                // 26
-  UINT8   MHi : 2;                      // 26
-  UINT8   BLo;                          // 27
-  UINT8   AccuracyLow : 6;              // 28
-  UINT8   BHi : 2;                      // 28
-  UINT8   Reserved4 : 2;                // 29
-  UINT8   AccuracyExp : 2;              // 29
-  UINT8   AccuracyHi : 4;               // 29
-  UINT8   BExp : 4;                     // 30
-  UINT8   RExp : 4;                     // 30
-  UINT8   NominalReadingSpscified : 1;  // 31
-  UINT8   NominalMaxSpscified : 1;      // 31
-  UINT8   NominalMinSpscified : 1;      // 31
-  UINT8   Reserved5 : 5;                // 31
-  UINT8   NominalReading;               // 32
-  UINT8   Reserved6[4];                 // 33
-  UINT8   UpperNonRecoverThreshold;     // 37
-  UINT8   UpperCriticalThreshold;       // 38
-  UINT8   UpperNonCriticalThreshold;    // 39
-  UINT8   LowerNonRecoverThreshold;     // 40
-  UINT8   LowerCriticalThreshold;       // 41
-  UINT8   LowerNonCriticalThreshold;    // 42
-  UINT8   Reserved7[5];                 // 43
-  UINT8   IdStringLength;               // 48
-  UINT8   AsciiIdString[16];            // 49 - 64
+  UINT16                         RecordId;                   // 1
+  UINT8                          Version;                    // 3
+  UINT8                          RecordType;                 // 4
+  UINT8                          RecordLength;               // 5
+  UINT8                          OwnerId;                    // 6
+  UINT8                          OwnerLun;                   // 7
+  UINT8                          SensorNumber;               // 8
+  UINT8                          EntityId;                   // 9
+  UINT8                          EntityInstance;             // 10
+  IPMI_SDR_RECORD_SENSOR_INIT    SensorInitialization;       // 11
+  IPMI_SDR_RECORD_SENSOR_CAP     SensorCapabilities;         // 12
+  UINT8                          SensorType;                 // 13
+  UINT8                          EventType;                  // 14
+  UINT8                          Reserved1[7];               // 15
+  UINT8                          UnitType;                   // 22
+  UINT8                          Reserved2;                  // 23
+  IPMI_SDR_RECORD_LINEARIZATION  Linearization;              // 24
+  UINT8                          MLo;                        // 25
+  IPMI_SDR_RECORD_M_TOLERANCE    MHiTolerance;               // 26
+  UINT8                          BLo;                        // 27
+  IPMI_SDR_RECORD_B_ACCURACY     BHiAccuracyLo;              // 28
+  IPMI_SDR_RECORD_ACCURACY_SENSOR_DIR  AccuracySensorDirection;  // 29
+  IPMI_SDR_RECORD_R_EXP_B_EXP    RExpBExp;                   // 30
+  IPMI_SDR_RECORD_ANALOG_FLAGS   AnalogFlags;                // 31
+  UINT8                          NominalReading;             // 32
+  UINT8                          Reserved3[4];               // 33
+  UINT8                          UpperNonRecoverThreshold;   // 37
+  UINT8                          UpperCriticalThreshold;     // 38
+  UINT8                          UpperNonCriticalThreshold;  // 39
+  UINT8                          LowerNonRecoverThreshold;   // 40
+  UINT8                          LowerCriticalThreshold;     // 41
+  UINT8                          LowerNonCriticalThreshold;  // 42
+  UINT8                          Reserved4[5];               // 43
+  UINT8                          IdStringLength;             // 48
+  UINT8                          AsciiIdString[16];          // 49 - 64
 } IPMI_SDR_RECORD_STRUCT_1;
 
 typedef struct {
-  UINT16  RecordId;                     // 1
-  UINT8   Version;                      // 3
-  UINT8   RecordType;                   // 4
-  UINT8   RecordLength;                 // 5
-  UINT8   OwnerId;                      // 6
-  UINT8   OwnerLun;                     // 7
-  UINT8   SensorNumber;                 // 8
-  UINT8   EntityId;                     // 9
-  UINT8   EntityInstance;               // 10
-  UINT8   SensorScanning : 1;           // 11
-  UINT8   EventScanning : 1;            // 11
-  UINT8   InitSensorType : 1;           // 11
-  UINT8   InitHysteresis : 1;           // 11
-  UINT8   InitThresholds : 1;           // 11
-  UINT8   InitEvent : 1;                // 11
-  UINT8   InitScanning : 1;             // 11
-  UINT8   Reserved : 1;                 // 11
-  UINT8   EventMessageControl : 2;      // 12
-  UINT8   ThresholdAccessSupport : 2;   // 12
-  UINT8   HysteresisSupport : 2;        // 12
-  UINT8   ReArmSupport : 1;             // 12
-  UINT8   IgnoreSensor : 1;             // 12
-  UINT8   SensorType;                   // 13
-  UINT8   EventType;                    // 14
-  UINT8   Reserved1[7];                 // 15
-  UINT8   UnitType;                     // 22
-  UINT8   Reserved2[9];                 // 23
-  UINT8   IdStringLength;               // 32
-  UINT8   AsciiIdString[16];            // 33 - 48
+  UINT16                       RecordId;              // 1
+  UINT8                        Version;               // 3
+  UINT8                        RecordType;            // 4
+  UINT8                        RecordLength;          // 5
+  UINT8                        OwnerId;               // 6
+  UINT8                        OwnerLun;              // 7
+  UINT8                        SensorNumber;          // 8
+  UINT8                        EntityId;              // 9
+  UINT8                        EntityInstance;        // 10
+  IPMI_SDR_RECORD_SENSOR_INIT  SensorInitialization;  // 11
+  IPMI_SDR_RECORD_SENSOR_CAP   SensorCapabilities;    // 12
+  UINT8                        SensorType;            // 13
+  UINT8                        EventType;             // 14
+  UINT8                        Reserved1[7];          // 15
+  UINT8                        UnitType;              // 22
+  UINT8                        Reserved2[9];          // 23
+  UINT8                        IdStringLength;        // 32
+  UINT8                        AsciiIdString[16];     // 33 - 48
 } IPMI_SDR_RECORD_STRUCT_2;
 
-typedef struct {
-  UINT8 Reserved1 : 1;
-  UINT8 ControllerSlaveAddress : 7;
-  UINT8 FruDeviceId;
-  UINT8 BusId : 3;
-  UINT8 Lun : 2;
-  UINT8 Reserved : 2;
-  UINT8 LogicalFruDevice : 1;
-  UINT8 Reserved3 : 4;
-  UINT8 ChannelNumber : 4;
+typedef union {
+  struct {
+    UINT8  Reserved1 : 1;
+    UINT8  ControllerSlaveAddress : 7;
+    UINT8  FruDeviceId;
+    UINT8  BusId : 3;
+    UINT8  Lun : 2;
+    UINT8  Reserved2 : 2;
+    UINT8  LogicalFruDevice : 1;
+    UINT8  Reserved3 : 4;
+    UINT8  ChannelNumber : 4;
+  } Bits;
+  UINT32  Uint32;
 } IPMI_FRU_DATA_INFO;
 
+typedef union {
+  struct {
+    UINT8  Length : 4;
+    UINT8  Reserved : 1;
+    UINT8  StringType : 3;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_SDR_RECORD_DEV_ID_STR_TYPE_LENGTH;
+
 typedef struct {
-  UINT16            RecordId;           // 1
-  UINT8             Version;            // 3
-  UINT8             RecordType;         // 4
-  UINT8             RecordLength;       // 5
-  IPMI_FRU_DATA_INFO FruDeviceData;      // 6
-  UINT8             Reserved1;          // 10
-  UINT8             DeviceType;         // 11
-  UINT8             DeviceTypeModifier; // 12
-  UINT8             FruEntityId;        // 13
-  UINT8             FruEntityInstance;  // 14
-  UINT8             OemReserved;        // 15
-  UINT8             Length : 4;         // 16
-  UINT8             Reserved2 : 1;      // 16
-  UINT8             StringType : 3;     // 16
-  UINT8             String[16];         // 17
+  UINT16                                  RecordId;            // 1
+  UINT8                                   Version;             // 3
+  UINT8                                   RecordType;          // 4
+  UINT8                                   RecordLength;        // 5
+  IPMI_FRU_DATA_INFO                      FruDeviceData;       // 6
+  UINT8                                   Reserved;            // 10
+  UINT8                                   DeviceType;          // 11
+  UINT8                                   DeviceTypeModifier;  // 12
+  UINT8                                   FruEntityId;         // 13
+  UINT8                                   FruEntityInstance;   // 14
+  UINT8                                   OemReserved;         // 15
+  IPMI_SDR_RECORD_DEV_ID_STR_TYPE_LENGTH  StringTypeLength;    // 16
+  UINT8                                   String[16];          // 17
 } IPMI_SDR_RECORD_STRUCT_11;
 
 typedef struct {
-  UINT16              NextRecordId;       //1
-  UINT16              RecordId;           //3
-  UINT8               Version;            //5
-  UINT8               RecordType;         //6
-  UINT8               RecordLength;       //7
-  UINT8               ManufacturerId[3];  //8
+  UINT16              RecordId;           //1
+  UINT8               Version;            //3
+  UINT8               RecordType;         //4
+  UINT8               RecordLength;       //5
+  UINT8               ManufacturerId[3];  //6
   UINT8               StringChars[20];
 } IPMI_SDR_RECORD_STRUCT_C0;
 
 typedef struct {
-  UINT16              NextRecordId;       //1
-  UINT16              RecordId;           //3
-  UINT8               Version;            //5
-  UINT8               RecordType;         //6
-  UINT8               RecordLength;       //7
+  UINT16              RecordId;           //1
+  UINT8               Version;            //3
+  UINT8               RecordType;         //4
+  UINT8               RecordLength;       //5
 } IPMI_SDR_RECORD_STRUCT_HEADER;
 
 typedef union {
-  IPMI_SDR_RECORD_STRUCT_1  SensorType1;
-  IPMI_SDR_RECORD_STRUCT_2  SensorType2;
-  IPMI_SDR_RECORD_STRUCT_11 SensorType11;
+  IPMI_SDR_RECORD_STRUCT_1        SensorType1;
+  IPMI_SDR_RECORD_STRUCT_2        SensorType2;
+  IPMI_SDR_RECORD_STRUCT_11       SensorType11;
   IPMI_SDR_RECORD_STRUCT_C0       SensorTypeC0;
   IPMI_SDR_RECORD_STRUCT_HEADER   SensorHeader;
 } IPMI_SENSOR_RECORD_STRUCT;
@@ -285,6 +374,12 @@ typedef struct {
   UINT8       BytesToRead;
 } IPMI_GET_SDR_REQUEST;
 
+typedef struct {
+  UINT8                        CompletionCode;
+  UINT16                       NextRecordId;
+  IPMI_SENSOR_RECORD_STRUCT    RecordData;
+} IPMI_GET_SDR_RESPONSE;
+
 //
 //  Definitions for Add SDR command
 //
@@ -378,6 +473,12 @@ typedef struct {
 //
 //  Constants and Structure definitions for "Get SEL Info" command to follow here
 //
+#define IPMI_GET_SEL_INFO_OPERATION_SUPPORT_GET_SEL_ALLOCATION_INFO_CMD    BIT0
+#define IPMI_GET_SEL_INFO_OPERATION_SUPPORT_RESERVE_SEL_CMD                BIT1
+#define IPMI_GET_SEL_INFO_OPERATION_SUPPORT_PARTIAL_ADD_SEL_ENTRY_CMD      BIT2
+#define IPMI_GET_SEL_INFO_OPERATION_SUPPORT_DELETE_SEL_CMD                 BIT3
+#define IPMI_GET_SEL_INFO_OPERATION_SUPPORT_OVERFLOW_FLAG                  BIT7
+
 typedef struct {
   UINT8   CompletionCode;
   UINT8   Version;              // Version of SEL
@@ -405,6 +506,10 @@ typedef struct {
 //
 //  Constants and Structure definitions for "Reserve SEL" command to follow here
 //
+typedef struct {
+  UINT8  CompletionCode;
+  UINT8  ReservationId[2];  // Reservation ID. LS byte first.
+} IPMI_RESERVE_SEL_RESPONSE;
 
 //
 //  Definitions for Get SEL Entry command
@@ -414,6 +519,38 @@ typedef struct {
 //
 //  Constants and Structure definitions for "Get SEL Entry" command to follow here
 //
+
+//
+//  Below is Definitions for SEL Record Formats (Chapter 32)
+//
+typedef struct {
+  UINT16  RecordId;
+  UINT8   RecordType;
+  UINT32  TimeStamp;
+  UINT16  GeneratorId;
+  UINT8   EvMRevision;
+  UINT8   SensorType;
+  UINT8   SensorNumber;
+  UINT8   EventDirType;
+  UINT8   OEMEvData1;
+  UINT8   OEMEvData2;
+  UINT8   OEMEvData3;
+} IPMI_SEL_EVENT_RECORD_DATA;
+
+typedef struct {
+  UINT16  RecordId;
+  UINT8   RecordType;  // C0h-DFh = OEM system event record
+  UINT32  TimeStamp;
+  UINT8   ManufacturerId[3];
+  UINT8   OEMDefined[6];
+} IPMI_TIMESTAMPED_OEM_SEL_RECORD_DATA;
+
+typedef struct {
+  UINT16  RecordId;
+  UINT8   RecordType;  // E0h-FFh = OEM system event record
+  UINT8   OEMDefined[13];
+} IPMI_NON_TIMESTAMPED_OEM_SEL_RECORD_DATA;
+
 typedef struct {
   UINT8 ReserveId[2]; // Reservation ID, LS Byte First
   UINT8 SelRecID[2];  // Sel Record ID, LS Byte First
@@ -421,6 +558,12 @@ typedef struct {
   UINT8 BytesToRead;  // Bytes to be Read, 0xFF for entire record
 } IPMI_GET_SEL_ENTRY_REQUEST;
 
+typedef struct {
+  UINT8                       CompletionCode;
+  UINT16                      NextSelRecordId; // Next SEL Record ID, LS Byte first
+  IPMI_SEL_EVENT_RECORD_DATA  RecordData;
+} IPMI_GET_SEL_ENTRY_RESPONSE;
+
 //
 //  Definitions for Add SEL Entry command
 //
@@ -429,6 +572,14 @@ typedef struct {
 //
 //  Constants and Structure definitions for "Add SEL Entry" command to follow here
 //
+typedef struct {
+  IPMI_SEL_EVENT_RECORD_DATA  RecordData;
+} IPMI_ADD_SEL_ENTRY_REQUEST;
+
+typedef struct {
+  UINT8   CompletionCode;
+  UINT16  RecordId;  // Record ID for added record, LS Byte first
+} IPMI_ADD_SEL_ENTRY_RESPONSE;
 
 //
 //  Definitions for Partial Add SEL Entry command
@@ -438,6 +589,18 @@ typedef struct {
 //
 //  Constants and Structure definitions for "Partial Add SEL Entry" command to follow here
 //
+typedef struct {
+  UINT16  ReservationId;
+  UINT16  RecordId;
+  UINT8   OffsetIntoRecord;
+  UINT8   InProgress;
+  UINT8   RecordData[0];
+} IPMI_PARTIAL_ADD_SEL_ENTRY_REQUEST;
+
+typedef struct {
+  UINT8   CompletionCode;
+  UINT16  RecordId;
+} IPMI_PARTIAL_ADD_SEL_ENTRY_RESPONSE;
 
 //
 //  Definitions for Delete SEL Entry command
@@ -450,7 +613,15 @@ typedef struct {
 typedef struct {
   UINT8 ReserveId[2];       // Reservation ID, LS byte first
   UINT8 RecordToDelete[2];  // Record to Delete, LS Byte First
-} IPMI_DELETE_SEL_REQUEST;
+} IPMI_DELETE_SEL_ENTRY_REQUEST;
+
+#define IPMI_DELETE_SEL_ENTRY_RESPONSE_TYPE_UNSUPPORTED     0x80
+#define IPMI_DELETE_SEL_ENTRY_RESPONSE_ERASE_IN_PROGRESS    0x81
+
+typedef struct {
+  UINT8   CompletionCode;
+  UINT16  RecordId;  // Record ID added. LS byte first
+} IPMI_DELETE_SEL_ENTRY_RESPONSE;
 
 //
 //  Definitions for Clear SEL command
@@ -460,6 +631,12 @@ typedef struct {
 //
 //  Constants and Structure definitions for "Clear SEL" command to follow here
 //
+#define IPMI_CLEAR_SEL_REQUEST_C_CHAR_ASCII        0x43
+#define IPMI_CLEAR_SEL_REQUEST_L_CHAR_ASCII        0x4C
+#define IPMI_CLEAR_SEL_REQUEST_R_CHAR_ASCII        0x52
+#define IPMI_CLEAR_SEL_REQUEST_INITIALIZE_ERASE    0xAA
+#define IPMI_CLEAR_SEL_REQUEST_GET_ERASE_STATUS    0x00
+
 typedef struct {
   UINT8 Reserve[2]; // Reserve ID, LSB first
   UINT8 AscC;       // Ascii for 'C' (0x43)
@@ -468,6 +645,14 @@ typedef struct {
   UINT8 Erase;      // 0xAA, Initiate Erase, 0x00 Get Erase Status
 } IPMI_CLEAR_SEL_REQUEST;
 
+#define IPMI_CLEAR_SEL_RESPONSE_ERASURE_IN_PROGRESS    0x00
+#define IPMI_CLEAR_SEL_RESPONSE_ERASURE_COMPLETED      0x01
+
+typedef struct {
+  UINT8  CompletionCode;
+  UINT8  ErasureProgress;
+} IPMI_CLEAR_SEL_RESPONSE;
+
 //
 //  Definitions for Get SEL Time command
 //
@@ -476,6 +661,10 @@ typedef struct {
 //
 //  Constants and Structure definitions for "Get SEL Time" command to follow here
 //
+typedef struct {
+  UINT8   CompletionCode;
+  UINT32  Timestamp;  // Present Timestamp clock reading. LS byte first.
+} IPMI_GET_SEL_TIME_RESPONSE;
 
 //
 //  Definitions for Set SEL Time command
@@ -485,6 +674,9 @@ typedef struct {
 //
 //  Constants and Structure definitions for "Set SEL Time" command to follow here
 //
+typedef struct {
+  UINT32  Timestamp;
+} IPMI_SET_SEL_TIME_REQUEST;
 
 //
 //  Definitions for Get Auxillary Log Status command
@@ -504,39 +696,88 @@ typedef struct {
 //  Constants and Structure definitions for "Set Auxillary Log Status" command to follow here
 //
 
-#define IPMI_COMPLETE_SEL_RECORD 0xFF
+//
+//  Definitions for Get SEL Time UTC Offset command
+//
+#define IPMI_STORAGE_GET_SEL_TIME_UTC_OFFSET   0x5C
 
 //
-//  Below is Definitions for SEL Record Formats (Chapter 32)
+//  Constants and Structure definitions for "Get SEL Time UTC Offset" command to follow here
 //
 typedef struct {
-  UINT16  RecordId;
-  UINT8   RecordType;
-  UINT32  TimeStamp;
-  UINT16  GeneratorId;
-  UINT8   EvMRevision;
-  UINT8   SensorType;
-  UINT8   SensorNumber;
-  UINT8   EventDirType;
-  UINT8   OEMEvData1;
-  UINT8   OEMEvData2;
-  UINT8   OEMEvData3;
-} IPMI_SEL_EVENT_RECORD_DATA;
+  UINT8  CompletionCode;
+  //
+  // 16-bit, 2s-complement signed integer for the offset in minutes from UTC to SEL Time.
+  // LS-byte first. (ranges from -1440 to 1440)
+  //
+  INT16  UtcOffset;
+} IPMI_GET_SEL_TIME_UTC_OFFSET_RESPONSE;
 
-#define IPMI_SEL_SYSTEM_RECORD                     0x02
+//
+//  Definitions for Set SEL Time UTC Offset command
+//
+#define IPMI_STORAGE_SET_SEL_TIME_UTC_OFFSET   0x5D
 
-#define IPMI_EVM_REVISION                          0x04
-#define IPMI_BIOS_ID                               0x18
-#define IPMI_FORMAT_REV                            0x00
-#define IPMI_FORMAT_REV1                           0x01
-#define IPMI_SOFTWARE_ID                           0x01
-#define IPMI_PLATFORM_VAL_ID                       0x01
-#define IPMI_GENERATOR_ID(i,f)                     ((i << 1) | (f << 1) | IPMI_SOFTWARE_ID)
+//
+//  Constants and Structure definitions for "Set SEL Time UTC Offset" command to follow here
+//
 
-#define IPMI_SENSOR_TYPE_EVENT_CODE_DISCRETE       0x6F
+#define IPMI_COMPLETE_SEL_RECORD 0xFF
 
-#define IPMI_OEM_SPECIFIC_DATA                     0x02
-#define IPMI_SENSOR_SPECIFIC_DATA                  0x03
+#define IPMI_SEL_SYSTEM_RECORD                          0x02
+#define IPMI_SEL_OEM_TIME_STAMP_RECORD_START            0xC0
+#define IPMI_SEL_OEM_TIME_STAMP_RECORD_END              0xDF
+#define IPMI_SEL_OEM_NO_TIME_STAMP_RECORD_START         0xE0
+#define IPMI_SEL_OEM_NO_TIME_STAMP_RECORD_END           0xFF
+
+#define IPMI_SEL_EVENT_DIR(EventDirType)                (EventDirType >> 7)
+#define IPMI_SEL_EVENT_DIR_ASSERTION_EVENT              0x00
+#define IPMI_SEL_EVENT_DIR_DEASSERTION_EVENT            0x01
+
+#define IPMI_SEL_EVENT_TYPE(EventDirType)               (EventDirType & 0x7F)
+//
+// Event/Reading Type Code Ranges (Chapter 42)
+//
+#define IPMI_SEL_EVENT_TYPE_UNSPECIFIED                 0x00
+#define IPMI_SEL_EVENT_TYPE_THRESHOLD                   0x01
+#define IPMI_SEL_EVENT_TYPE_GENERIC_START               0x02
+#define IPMI_SEL_EVENT_TYPE_GENERIC_END                 0x0C
+#define IPMI_SEL_EVENT_TYPE_SENSOR_SPECIFIC             0x6F
+#define IPMI_SEL_EVENT_TYPE_OEM_START                   0x70
+#define IPMI_SEL_EVENT_TYPE_OEM_END                     0x7F
+
+#define SOFTWARE_ID_FROM_GENERATOR_ID(GeneratorId)      ((GeneratorId & 0xFF) >> 1)
+//
+// System Software IDs definitions (Section 5.5)
+//
+#define IPMI_SWID_BIOS_RANGE_START                      0x00
+#define IPMI_SWID_BIOS_RANGE_END                        0x0F
+#define IPMI_SWID_SMI_HANDLER_RANGE_START               0x10
+#define IPMI_SWID_SMI_HANDLER_RANGE_END                 0x1F
+#define IPMI_SWID_SMS_RANGE_START                       0x20
+#define IPMI_SWID_SMS_RANGE_END                         0x2F
+#define IPMI_SWID_OEM_RANGE_START                       0x30
+#define IPMI_SWID_OEM_RANGE_END                         0x3F
+#define IPMI_SWID_REMOTE_CONSOLE_RANGE_START            0x40
+#define IPMI_SWID_REMOTE_CONSOLE_RANGE_END              0x46
+#define IPMI_SWID_TERMINAL_REMOTE_CONSOLE_ID            0x47
+
+#define SLAVE_ADDRESS_FROM_GENERATOR_ID(GeneratorId)    ((GeneratorId & 0xFF) >> 1)
+#define LUN_FROM_GENERATOR_ID(GeneratorId)              ((GeneratorId >> 8) & 0x03)
+#define CHANNEL_NUMBER_FROM_GENERATOR_ID(GeneratorId)   ((GeneratorId >> 12) & 0x0F)
+
+#define IPMI_EVM_REVISION                               0x04
+#define IPMI_BIOS_ID                                    0x18
+#define IPMI_FORMAT_REV                                 0x00
+#define IPMI_FORMAT_REV1                                0x01
+#define IPMI_SOFTWARE_ID                                0x01
+#define IPMI_PLATFORM_VAL_ID                            0x01
+#define IPMI_GENERATOR_ID(i,f)                          ((i << 1) | (f << 1) | IPMI_SOFTWARE_ID)
+
+#define IPMI_SENSOR_TYPE_EVENT_CODE_DISCRETE            0x6F
+
+#define IPMI_OEM_SPECIFIC_DATA                          0x02
+#define IPMI_SENSOR_SPECIFIC_DATA                       0x03
 
 #pragma pack()
 #endif
diff --git a/MdePkg/Include/IndustryStandard/IpmiNetFnTransport.h b/MdePkg/Include/IndustryStandard/IpmiNetFnTransport.h
index ad1a9aad707a..6ede54cbeaf3 100644
--- a/MdePkg/Include/IndustryStandard/IpmiNetFnTransport.h
+++ b/MdePkg/Include/IndustryStandard/IpmiNetFnTransport.h
@@ -10,14 +10,8 @@
   See IPMI specification, Appendix G, Command Assignments
   and Appendix H, Sub-function Assignments.
 
-  Copyright (c) 1999 - 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
 #ifndef _IPMI_NET_FN_TRANSPORT_H_
@@ -65,7 +59,22 @@ typedef enum {
   IpmiLanCommunityString,
   IpmiLanReserved3,
   IpmiLanDestinationType,
-  IpmiLanDestinationAddress
+  IpmiLanDestinationAddress,
+  IpmiIpv4OrIpv6Support = 0x32,
+  IpmiIpv4OrIpv6AddressEnable,
+  IpmiIpv6HdrStatTrafficClass,
+  IpmiIpv6HdrStatHopLimit,
+  IpmiIpv6HdrFlowLabel,
+  IpmiIpv6Status,
+  IpmiIpv6StaticAddress,
+  IpmiIpv6DhcpStaticDuidLen,
+  IpmiIpv6DhcpStaticDuid,
+  IpmiIpv6DhcpAddress,
+  IpmiIpv6DhcpDynamicDuidLen,
+  IpmiIpv6DhcpDynamicDuid,
+  IpmiIpv6RouterConfig = 0x40,
+  IpmiIpv6StaticRouter1IpAddr,
+  IpmiIpv6DynamicRouterIpAddr = 0x4a
 } IPMI_LAN_OPTION_TYPE;
 
 //
@@ -94,23 +103,29 @@ typedef enum {
   IpmiOem2
 } IPMI_LAN_DEST_TYPE_DEST_TYPE;
 
-typedef struct {
-  UINT8 NoAuth : 1;
-  UINT8 MD2Auth : 1;
-  UINT8 MD5Auth : 1;
-  UINT8 Reserved1 : 1;
-  UINT8 StraightPswd : 1;
-  UINT8 OemType : 1;
-  UINT8 Reserved2 : 2;
+typedef union {
+  struct {
+    UINT8  NoAuth : 1;
+    UINT8  MD2Auth : 1;
+    UINT8  MD5Auth : 1;
+    UINT8  Reserved1 : 1;
+    UINT8  StraightPswd : 1;
+    UINT8  OemType : 1;
+    UINT8  Reserved2 : 2;
+  } Bits;
+  UINT8  Uint8;
 } IPMI_LAN_AUTH_TYPE;
 
 typedef struct {
   UINT8 IpAddress[4];
 } IPMI_LAN_IP_ADDRESS;
 
-typedef struct {
-  UINT8 AddressSrc : 4;
-  UINT8 Reserved : 4;
+typedef union {
+  struct {
+    UINT8  AddressSrc : 4;
+    UINT8  Reserved : 4;
+  } Bits;
+  UINT8  Uint8;
 } IPMI_LAN_IP_ADDRESS_SRC;
 
 typedef struct {
@@ -121,13 +136,27 @@ typedef struct {
   UINT8 IpAddress[4];
 } IPMI_LAN_SUBNET_MASK;
 
-typedef struct {
-  UINT8 TimeToLive;
-  UINT8 IpFlag : 3;
-  UINT8 Reserved1 : 5;
-  UINT8 Precedence : 3;
-  UINT8 Reserved2 : 1;
-  UINT8 ServiceType : 4;
+typedef union {
+  struct {
+    UINT8  IpFlag : 3;
+    UINT8  Reserved : 5;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_LAN_IPV4_HDR_PARAM_DATA_2;
+
+typedef union {
+  struct {
+    UINT8  Precedence : 3;
+    UINT8  Reserved : 1;
+    UINT8  ServiceType : 4;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_LAN_IPV4_HDR_PARAM_DATA_3;
+
+typedef struct {
+  UINT8                           TimeToLive;
+  IPMI_LAN_IPV4_HDR_PARAM_DATA_2  Data2;
+  IPMI_LAN_IPV4_HDR_PARAM_DATA_3  Data3;
 } IPMI_LAN_IPV4_HDR_PARAM;
 
 typedef struct {
@@ -135,10 +164,13 @@ typedef struct {
   UINT8 RcmpPortLsb;
 } IPMI_LAN_RCMP_PORT;
 
-typedef struct {
-  UINT8 EnableBmcArpResponse : 1;
-  UINT8 EnableBmcGratuitousArp : 1;
-  UINT8 Reserved : 6;
+typedef union {
+  struct {
+    UINT8  EnableBmcArpResponse : 1;
+    UINT8  EnableBmcGratuitousArp : 1;
+    UINT8  Reserved : 6;
+  } Bits;
+  UINT8  Uint8;
 } IPMI_LAN_BMC_GENERATED_ARP_CONTROL;
 
 typedef struct {
@@ -149,23 +181,50 @@ typedef struct {
   UINT8 Data[18];
 } IPMI_LAN_COMMUNITY_STRING;
 
+typedef union {
+  struct {
+    UINT8  DestinationSelector : 4;
+    UINT8  Reserved : 4;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_LAN_SET_SELECTOR;
+
+typedef union {
+  struct {
+    UINT8  DestinationType : 3;
+    UINT8  Reserved : 4;
+    UINT8  AlertAcknowledged : 1;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_LAN_DEST_TYPE_DESTINATION_TYPE;
+
 typedef struct {
-  UINT8 DestinationSelector : 4;
-  UINT8 Reserved2 : 4;
-  UINT8 DestinationType : 3;
-  UINT8 Reserved1 : 4;
-  UINT8 AlertAcknowledged : 1;
+  IPMI_LAN_SET_SELECTOR                SetSelector;
+  IPMI_LAN_DEST_TYPE_DESTINATION_TYPE  DestinationType;
 } IPMI_LAN_DEST_TYPE;
 
-typedef struct {
-  UINT8               DestinationSelector : 4;
-  UINT8               Reserved1 : 4;
-  UINT8               AlertingIpAddressSelector : 4;
-  UINT8               AddressFormat : 4;
-  UINT8               UseDefaultGateway : 1;
-  UINT8               Reserved2 : 7;
-  IPMI_LAN_IP_ADDRESS  AlertingIpAddress;
-  IPMI_LAN_MAC_ADDRESS AlertingMacAddress;
+typedef union {
+  struct {
+    UINT8  AlertingIpAddressSelector : 4;
+    UINT8  AddressFormat : 4;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_LAN_ADDRESS_FORMAT;
+
+typedef union {
+  struct {
+    UINT8  UseDefaultGateway : 1;
+    UINT8  Reserved2 : 7;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_LAN_GATEWAY_SELECTOR;
+
+typedef struct {
+  IPMI_LAN_SET_SELECTOR      SetSelector;
+  IPMI_LAN_ADDRESS_FORMAT    AddressFormat;
+  IPMI_LAN_GATEWAY_SELECTOR  GatewaySelector;
+  IPMI_LAN_IP_ADDRESS        AlertingIpAddress;
+  IPMI_LAN_MAC_ADDRESS       AlertingMacAddress;
 } IPMI_LAN_DEST_ADDRESS;
 
 typedef union {
@@ -183,6 +242,48 @@ typedef union {
   IPMI_LAN_DEST_ADDRESS              IpmiLanDestAddress;
 } IPMI_LAN_OPTIONS;
 
+typedef union {
+  struct {
+    UINT8  AddressSourceType : 4;
+    UINT8  Reserved : 3;
+    UINT8  EnableStatus : 1;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_LAN_IPV6_ADDRESS_SOURCE_TYPE;
+
+typedef struct {
+  UINT8                              SetSelector;
+  IPMI_LAN_IPV6_ADDRESS_SOURCE_TYPE  AddressSourceType;
+  UINT8                              Ipv6Address[16];
+  UINT8                              AddressPrefixLen;
+  UINT8                              AddressStatus;
+} IPMI_LAN_IPV6_STATIC_ADDRESS;
+
+//
+//  Set in progress parameter
+//
+typedef union {
+  struct {
+    UINT8  SetInProgress:2;
+    UINT8  Reserved:6;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_LAN_SET_IN_PROGRESS;
+
+typedef union {
+  struct {
+    UINT8  ChannelNo : 4;
+    UINT8  Reserved : 4;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_SET_LAN_CONFIG_CHANNEL_NUM;
+
+typedef struct {
+  IPMI_SET_LAN_CONFIG_CHANNEL_NUM  ChannelNumber;
+  UINT8                            ParameterSelector;
+  UINT8                            ParameterData[0];
+} IPMI_SET_LAN_CONFIGURATION_PARAMETERS_COMMAND_REQUEST;
+
 //
 //  Definitions for Get Lan Configuration Parameters command
 //
@@ -191,6 +292,27 @@ typedef union {
 //
 //  Constants and Structure definitions for "Get Lan Configuration Parameters" command to follow here
 //
+typedef union {
+  struct {
+    UINT8  ChannelNo : 4;
+    UINT8  Reserved : 3;
+    UINT8  GetParameter : 1;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_GET_LAN_CONFIG_CHANNEL_NUM;
+
+typedef struct {
+  IPMI_GET_LAN_CONFIG_CHANNEL_NUM  ChannelNumber;
+  UINT8                            ParameterSelector;
+  UINT8                            SetSelector;
+  UINT8                            BlockSelector;
+} IPMI_GET_LAN_CONFIGURATION_PARAMETERS_REQUEST;
+
+typedef struct {
+  UINT8  CompletionCode;
+  UINT8  ParameterRevision;
+  UINT8  ParameterData[0];
+} IPMI_GET_LAN_CONFIGURATION_PARAMETERS_RESPONSE;
 
 //
 //  Definitions for Suspend BMC ARPs command
@@ -226,67 +348,100 @@ typedef union {
 //
 // EMP OPTION DATA
 //
-typedef struct {
-  UINT8 NoAuthentication : 1;
-  UINT8 MD2Authentication : 1;
-  UINT8 MD5Authentication : 1;
-  UINT8 Reserved1 : 1;
-  UINT8 StraightPassword : 1;
-  UINT8 OemProprietary : 1;
-  UINT8 Reservd2 : 2;
+typedef union {
+  struct {
+    UINT8  NoAuthentication : 1;
+    UINT8  MD2Authentication : 1;
+    UINT8  MD5Authentication : 1;
+    UINT8  Reserved1 : 1;
+    UINT8  StraightPassword : 1;
+    UINT8  OemProprietary : 1;
+    UINT8  Reservd2 : 2;
+  } Bits;
+  UINT8  Uint8;
 } IPMI_EMP_AUTH_TYPE;
 
-typedef struct {
-  UINT8 EnableBasicMode : 1;
-  UINT8 EnablePPPMode : 1;
-  UINT8 EnableTerminalMode : 1;
-  UINT8 Reserved1 : 2;
-  UINT8 SnoopOsPPPNegotiation : 1;
-  UINT8 Reserved2 : 1;
-  UINT8 DirectConnect : 1;
+typedef union {
+  struct {
+    UINT8  EnableBasicMode : 1;
+    UINT8  EnablePPPMode : 1;
+    UINT8  EnableTerminalMode : 1;
+    UINT8  Reserved1 : 2;
+    UINT8  SnoopOsPPPNegotiation : 1;
+    UINT8  Reserved2 : 1;
+    UINT8  DirectConnect : 1;
+  } Bits;
+  UINT8  Uint8;
 } IPMI_EMP_CONNECTION_TYPE;
 
-typedef struct {
-  UINT8 InactivityTimeout : 4;
-  UINT8 Reserved : 4;
+typedef union {
+  struct {
+    UINT8  InactivityTimeout : 4;
+    UINT8  Reserved : 4;
+  } Bits;
+  UINT8  Uint8;
 } IPMI_EMP_INACTIVITY_TIMEOUT;
 
-typedef struct {
-  UINT8 IpmiCallback : 1;
-  UINT8 CBCPCallback : 1;
-  UINT8 Reserved1 : 6;
-  UINT8 CbcpEnableNoCallback : 1;
-  UINT8 CbcpEnablePreSpecifiedNumber : 1;
-  UINT8 CbcpEnableUserSpecifiedNumber : 1;
-  UINT8 CbcpEnableCallbackFromList : 1;
-  UINT8 Reserved : 4;
-  UINT8 CallbackDestination1;
-  UINT8 CallbackDestination2;
-  UINT8 CallbackDestination3;
+typedef union {
+  struct {
+    UINT8  IpmiCallback : 1;
+    UINT8  CBCPCallback : 1;
+    UINT8  Reserved : 6;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_CHANNEL_CALLBACK_CONTROL_ENABLE;
+
+typedef union {
+  struct {
+    UINT8  CbcpEnableNoCallback : 1;
+    UINT8  CbcpEnablePreSpecifiedNumber : 1;
+    UINT8  CbcpEnableUserSpecifiedNumber : 1;
+    UINT8  CbcpEnableCallbackFromList : 1;
+    UINT8  Reserved : 4;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_CHANNEL_CALLBACK_CONTROL_CBCP;
+
+typedef struct {
+  IPMI_CHANNEL_CALLBACK_CONTROL_ENABLE  CallbackEnable;
+  IPMI_CHANNEL_CALLBACK_CONTROL_CBCP    CBCPNegotiation;
+  UINT8                                 CallbackDestination1;
+  UINT8                                 CallbackDestination2;
+  UINT8                                 CallbackDestination3;
 } IPMI_EMP_CHANNEL_CALLBACK_CONTROL;
 
-typedef struct {
-  UINT8 CloseSessionOnDCDLoss : 1;
-  UINT8 EnableSessionInactivityTimeout : 1;
-  UINT8 Reserved : 6;
+typedef union {
+  struct {
+    UINT8  CloseSessionOnDCDLoss : 1;
+    UINT8  EnableSessionInactivityTimeout : 1;
+    UINT8  Reserved : 6;
+  } Bits;
+  UINT8  Uint8;
 } IPMI_EMP_SESSION_TERMINATION;
 
-typedef struct {
-  UINT8 Reserved1 : 5;
-  UINT8 EnableDtrHangup : 1;
-  UINT8 FlowControl : 2;
-  UINT8 BitRate : 4;
-  UINT8 Reserved2 : 4;
-  UINT8 SaveSetting : 1;
-  UINT8 SetComPort : 1;
-  UINT8 Reserved3 : 6;
+typedef union {
+  struct {
+    UINT8  Reserved1 : 5;
+    UINT8  EnableDtrHangup : 1;
+    UINT8  FlowControl : 2;
+    UINT8  BitRate : 4;
+    UINT8  Reserved2 : 4;
+    UINT8  SaveSetting : 1;
+    UINT8  SetComPort : 1;
+    UINT8  Reserved3 : 6;
+  } Bits;
+  UINT8   Uint8;
+  UINT16  Uint16;
 } IPMI_EMP_MESSAGING_COM_SETTING;
 
-typedef struct {
-  UINT8 RingDurationInterval : 6;
-  UINT8 Reserved1 : 2;
-  UINT8 RingDeadTime : 4;
-  UINT8 Reserved : 4;
+typedef union {
+  struct {
+    UINT8  RingDurationInterval : 6;
+    UINT8  Reserved1 : 2;
+    UINT8  RingDeadTime : 4;
+    UINT8  Reserved2 : 4;
+  } Bits;
+  UINT8  Uint8;
 } IPMI_EMP_MODEM_RING_TIME;
 
 typedef struct {
@@ -314,14 +469,20 @@ typedef struct {
   UINT8 CommunityString[18];
 } IPMI_EMP_COMMUNITY_STRING;
 
-typedef struct {
-  UINT8 Reserved5 : 4;
-  UINT8 DialStringSelector : 4;
+typedef union {
+  struct {
+    UINT8  Reserved : 4;
+    UINT8  DialStringSelector : 4;
+  } Bits;
+  UINT8  Uint8;
 } IPMI_DIAL_PAGE_DESTINATION;
 
-typedef struct {
-  UINT8 TapAccountSelector : 4;
-  UINT8 Reserved : 4;
+typedef union {
+  struct {
+    UINT8  TapAccountSelector : 4;
+    UINT8  Reserved : 4;
+  } Bits;
+  UINT8  Uint8;
 } IPMI_TAP_PAGE_DESTINATION;
 
 typedef struct {
@@ -335,40 +496,78 @@ typedef union {
   IPMI_PPP_ALERT_DESTINATION    PppAlertDestination;
 } IPMI_DEST_TYPE_SPECIFIC;
 
-typedef struct {
-  UINT8 DestinationSelector : 4;
-  UINT8 Reserved1 : 4;
-  UINT8 DestinationType : 4;
-  UINT8 Reserved2 : 3;
-  UINT8 AlertAckRequired : 1;
-  UINT8 AlertAckTimeoutSeconds;
-  UINT8 NumRetriesCall : 3;
-  UINT8 Reserved3 : 1;
-  UINT8 NumRetryAlert : 3;
-  UINT8 Reserved4 : 1;
-  IPMI_DEST_TYPE_SPECIFIC DestinationTypeSpecific;
+typedef union {
+  struct {
+    UINT8 DestinationSelector : 4;
+    UINT8 Reserved : 4;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_EMP_DESTINATION_SELECTOR;
+
+typedef union {
+  struct {
+    UINT8  DestinationType : 4;
+    UINT8  Reserved : 3;
+    UINT8  AlertAckRequired : 1;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_EMP_DESTINATION_TYPE;
+
+typedef union {
+  struct {
+    UINT8  NumRetriesCall : 3;
+    UINT8  Reserved1 : 1;
+    UINT8  NumRetryAlert : 3;
+    UINT8  Reserved2 : 1;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_EMP_RETRIES;
+
+typedef struct {
+  IPMI_EMP_DESTINATION_SELECTOR  DestinationSelector;
+  IPMI_EMP_DESTINATION_TYPE      DestinationType;
+  UINT8                          AlertAckTimeoutSeconds;
+  IPMI_EMP_RETRIES               Retries;
+  IPMI_DEST_TYPE_SPECIFIC        DestinationTypeSpecific;
 } IPMI_EMP_DESTINATION_INFO;
 
+typedef union {
+  struct {
+    UINT8  Parity : 3;
+    UINT8  CharacterSize : 1;
+    UINT8  StopBit : 1;
+    UINT8  DtrHangup : 1;
+    UINT8  FlowControl : 2;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_EMP_DESTINATION_COM_SETTING_DATA_2;
+
+typedef union {
+  struct {
+    UINT8  BitRate : 4;
+    UINT8  Reserved : 4;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_EMP_BIT_RATE;
+
 typedef struct {
-  UINT8 DestinationSelector : 4;
-  UINT8 Reserved1 : 4;
-  UINT8 Parity : 3;
-  UINT8 CharacterSize : 1;
-  UINT8 StopBit : 1;
-  UINT8 DtrHangup : 1;
-  UINT8 FlowControl : 2;
-  UINT8 BitRate : 4;
-  UINT8 Reserved2 : 4;
-  UINT8 SaveSetting : 1;
-  UINT8 SetComPort : 1;
-  UINT8 Reserved3 : 6;
+  IPMI_EMP_DESTINATION_SELECTOR            DestinationSelector;
+  IPMI_EMP_DESTINATION_COM_SETTING_DATA_2  Data2;
+  IPMI_EMP_BIT_RATE                        BitRate;
 } IPMI_EMP_DESTINATION_COM_SETTING;
 
+typedef union {
+  struct {
+    UINT8  DialStringSelector : 4;
+    UINT8  Reserved : 4;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_DIAL_STRING_SELECTOR;
+
 typedef struct {
-  UINT8 DialStringSelector : 4;
-  UINT8 Reserved1 : 4;
-  UINT8 Reserved2;
-  UINT8 DialString[48];
+  IPMI_DIAL_STRING_SELECTOR  DestinationSelector;
+  UINT8                      Reserved;
+  UINT8                      DialString[48];
 } IPMI_DESTINATION_DIAL_STRING;
 
 typedef union {
@@ -376,16 +575,31 @@ typedef union {
   UINT8   IpAddress[4];
 } IPMI_PPP_IP_ADDRESS;
 
+typedef union {
+  struct {
+    UINT8  IpAddressSelector : 4;
+    UINT8  Reserved : 4;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_DESTINATION_IP_ADDRESS_SELECTOR;
+
 typedef struct {
-  UINT8 IpAddressSelector : 4;
-  UINT8 Reserved1 : 4;
-  IPMI_PPP_IP_ADDRESS PppIpAddress;
+  IPMI_DESTINATION_IP_ADDRESS_SELECTOR  DestinationSelector;
+  IPMI_PPP_IP_ADDRESS                   PppIpAddress;
 } IPMI_DESTINATION_IP_ADDRESS;
 
+typedef union {
+  struct {
+    UINT8  TapServiceSelector : 4;
+    UINT8  TapDialStringSelector : 4;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_TAP_DIAL_STRING_SERVICE_SELECTOR;
+
+
 typedef struct {
-  UINT8 TapSelector;
-  UINT8 TapServiceSelector : 4;
-  UINT8 TapDialStringSelector : 4;
+  UINT8                                  TapSelector;
+  IPMI_TAP_DIAL_STRING_SERVICE_SELECTOR  TapDialStringServiceSelector;
 } IPMI_DESTINATION_TAP_ACCOUNT;
 
 typedef struct {
@@ -434,21 +648,63 @@ typedef union {
 //
 //  Constants and Structure definitions for "Set Serial/Modem Mux" command to follow here
 //
+
+//
+// Set Serial/Modem Mux command request return status
+//
+#define IPMI_MUX_SETTING_REQUEST_REJECTED  0x00
+#define IPMI_MUX_SETTING_REQUEST_ACCEPTED  0x01
+
+//
+//  Definitions for serial multiplex settings
+//
+#define IPMI_MUX_SETTING_GET_MUX_SETTING              0x0
+#define IPMI_MUX_SETTING_REQUEST_MUX_TO_SYSTEM        0x1
+#define IPMI_MUX_SETTING_REQUEST_MUX_TO_BMC           0x2
+#define IPMI_MUX_SETTING_FORCE_MUX_TO_SYSTEM          0x3
+#define IPMI_MUX_SETTING_FORCE_MUX_TO_BMC             0x4
+#define IPMI_MUX_SETTING_BLOCK_REQUEST_MUX_TO_SYSTEM  0x5
+#define IPMI_MUX_SETTING_ALLOW_REQUEST_MUX_TO_SYSTEM  0x6
+#define IPMI_MUX_SETTING_BLOCK_REQUEST_MUX_TO_BMC     0x7
+#define IPMI_MUX_SETTING_ALLOW_REQUEST_MUX_TO_BMC     0x8
+
+typedef union {
+  struct {
+    UINT8  ChannelNo : 4;
+    UINT8  Reserved : 4;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_MUX_CHANNEL_NUM;
+
+typedef union {
+  struct {
+    UINT8  MuxSetting : 4;
+    UINT8  Reserved : 4;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_MUX_SETTING_REQUEST;
+
 typedef struct {
-  UINT8 ChannelNo : 4;
-  UINT8 Reserved1 : 4;
-  UINT8 MuxSetting : 4;
-  UINT8 Reserved2 : 4;
+  IPMI_MUX_CHANNEL_NUM      ChannelNumber;
+  IPMI_MUX_SETTING_REQUEST  MuxSetting;
 } IPMI_SET_SERIAL_MODEM_MUX_COMMAND_REQUEST;
 
-typedef struct {
-  UINT8 MuxSetToBmc : 1;
-  UINT8 CommandStatus : 1;
-  UINT8 MessagingSessionActive : 1;
-  UINT8 AlertInProgress : 1;
-  UINT8 Reserved2 : 2;
-  UINT8 MuxToBmcAllowed : 1;
-  UINT8 MuxToSystemBlocked : 1;
+typedef union {
+  struct {
+    UINT8  MuxSetToBmc : 1;
+    UINT8  CommandStatus : 1;
+    UINT8  MessagingSessionActive : 1;
+    UINT8  AlertInProgress : 1;
+    UINT8  Reserved : 2;
+    UINT8  MuxToBmcAllowed : 1;
+    UINT8  MuxToSystemBlocked : 1;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_MUX_SETTING_PRESENT_STATE;
+
+typedef struct {
+  UINT8                           CompletionCode;
+  IPMI_MUX_SETTING_PRESENT_STATE  MuxSetting;
 } IPMI_SET_SERIAL_MODEM_MUX_COMMAND_RESPONSE;
 
 //
@@ -544,6 +800,20 @@ typedef struct {
 //
 //  Constants and Structure definitions for "SOL activating" command to follow here
 //
+typedef union {
+  struct {
+    UINT8  SessionState : 4;
+    UINT8  Reserved : 4;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_SOL_SESSION_STATE;
+
+typedef struct {
+  IPMI_SOL_SESSION_STATE  SessionState;
+  UINT8                   PayloadInstance;
+  UINT8                   FormatVersionMajor; // 1
+  UINT8                   FormatVersionMinor; // 0
+} IPMI_SOL_ACTIVATING_REQUEST;
 
 //
 //  Definitions for Set SOL Configuration Parameters command
@@ -555,6 +825,33 @@ typedef struct {
 //
 
 //
+// SOL Configuration Parameters selector
+//
+#define IPMI_SOL_CONFIGURATION_PARAMETER_SET_IN_PROGRESS       0
+#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_ENABLE            1
+#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_AUTHENTICATION    2
+#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_CHARACTER_PARAM   3
+#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_RETRY             4
+#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_NV_BIT_RATE       5
+#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_VOLATILE_BIT_RATE 6
+#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_PAYLOAD_CHANNEL   7
+#define IPMI_SOL_CONFIGURATION_PARAMETER_SOL_PAYLOAD_PORT      8
+
+typedef union {
+  struct {
+    UINT8  ChannelNumber : 4;
+    UINT8  Reserved : 4;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_SET_SOL_CONFIG_PARAM_CHANNEL_NUM;
+
+typedef struct {
+  IPMI_SET_SOL_CONFIG_PARAM_CHANNEL_NUM  ChannelNumber;
+  UINT8                                  ParameterSelector;
+  UINT8                                  ParameterData[0];
+} IPMI_SET_SOL_CONFIGURATION_PARAMETERS_REQUEST;
+
+//
 //  Definitions for Get SOL Configuration Parameters command
 //
 #define IPMI_TRANSPORT_GET_SOL_CONFIG_PARAM  0x22
@@ -562,5 +859,27 @@ typedef struct {
 //
 //  Constants and Structure definitions for "Get SOL Configuration Parameters" command to follow here
 //
+typedef union {
+  struct {
+    UINT8  ChannelNumber : 4;
+    UINT8  Reserved : 3;
+    UINT8  GetParameter : 1;
+  } Bits;
+  UINT8  Uint8;
+} IPMI_GET_SOL_CONFIG_PARAM_CHANNEL_NUM;
+
+typedef struct {
+  IPMI_GET_SOL_CONFIG_PARAM_CHANNEL_NUM  ChannelNumber;
+  UINT8                                  ParameterSelector;
+  UINT8                                  SetSelector;
+  UINT8                                  BlockSelector;
+} IPMI_GET_SOL_CONFIGURATION_PARAMETERS_REQUEST;
+
+typedef struct {
+  UINT8  CompletionCode;
+  UINT8  ParameterRevision;
+  UINT8  ParameterData[0];
+} IPMI_GET_SOL_CONFIGURATION_PARAMETERS_RESPONSE;
+
 #pragma pack()
 #endif
diff --git a/MdePkg/Include/IndustryStandard/LegacyBiosMpTable.h b/MdePkg/Include/IndustryStandard/LegacyBiosMpTable.h
index 41045bd9765e..5c1f6ecfba0e 100644
--- a/MdePkg/Include/IndustryStandard/LegacyBiosMpTable.h
+++ b/MdePkg/Include/IndustryStandard/LegacyBiosMpTable.h
@@ -1,17 +1,11 @@
 /** @file
   Defives data structures per MultiProcessor Specification Ver 1.4.
-  
-  The MultiProcessor Specification defines an enhancement to the standard 
+
+  The MultiProcessor Specification defines an enhancement to the standard
   to which PC manufacturers design DOS-compatible systems.
 
-Copyright (c) 2007 - 2011, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials                          
-are licensed and made available under the terms and conditions of the BSD License         
-which accompanies this distribution.  The full text of the license may be found at        
-http://opensource.org/licenses/bsd-license.php                                            
-                                                                                          
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/IndustryStandard/LowPowerIdleTable.h b/MdePkg/Include/IndustryStandard/LowPowerIdleTable.h
index 2b361ed390a5..8de0cbf61283 100644
--- a/MdePkg/Include/IndustryStandard/LowPowerIdleTable.h
+++ b/MdePkg/Include/IndustryStandard/LowPowerIdleTable.h
@@ -2,13 +2,7 @@
   ACPI Low Power Idle Table (LPIT) definitions
 
   Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
     - ACPI Low Power Idle Table (LPIT) Revision 001, dated July 2014
diff --git a/MdePkg/Include/IndustryStandard/Mbr.h b/MdePkg/Include/IndustryStandard/Mbr.h
index 302e44d77301..2d8c1f1e198f 100644
--- a/MdePkg/Include/IndustryStandard/Mbr.h
+++ b/MdePkg/Include/IndustryStandard/Mbr.h
@@ -1,14 +1,8 @@
 /** @file
   Legacy Master Boot Record Format Definition.
 
-Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials                          
-are licensed and made available under the terms and conditions of the BSD License         
-which accompanies this distribution.  The full text of the license may be found at        
-http://opensource.org/licenses/bsd-license.php
-                                                                                          
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h b/MdePkg/Include/IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h
index d855d9b271d7..408971c019b1 100644
--- a/MdePkg/Include/IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h
+++ b/MdePkg/Include/IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h
@@ -1,16 +1,10 @@
 /** @file
-  ACPI memory mapped configuration space access table definition, defined at 
+  ACPI memory mapped configuration space access table definition, defined at
   in the PCI Firmware Specification, version 3.0.
   Specification is available at http://www.pcisig.com.
-    
-  Copyright (c) 2007 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+  Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
 #ifndef _MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_H_
@@ -35,7 +29,7 @@ typedef struct {
 } EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE;
 
 ///
-/// MCFG Table header definition.  The rest of the table 
+/// MCFG Table header definition.  The rest of the table
 /// must be defined in a platform specific manner.
 ///
 typedef struct {
diff --git a/MdePkg/Include/IndustryStandard/MemoryOverwriteRequestControlLock.h b/MdePkg/Include/IndustryStandard/MemoryOverwriteRequestControlLock.h
index 415c134779ae..3d5aaabf2764 100644
--- a/MdePkg/Include/IndustryStandard/MemoryOverwriteRequestControlLock.h
+++ b/MdePkg/Include/IndustryStandard/MemoryOverwriteRequestControlLock.h
@@ -1,16 +1,10 @@
 /** @file
-  Support for Microsoft Secure MOR implementation, defined at 
+  Support for Microsoft Secure MOR implementation, defined at
   Microsoft Secure MOR implementation.
   https://msdn.microsoft.com/en-us/library/windows/hardware/mt270973(v=vs.85).aspx
 
-  Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/IndustryStandard/Nvme.h b/MdePkg/Include/IndustryStandard/Nvme.h
index 5914b58cfdd4..1c5d4980edbf 100644
--- a/MdePkg/Include/IndustryStandard/Nvme.h
+++ b/MdePkg/Include/IndustryStandard/Nvme.h
@@ -2,13 +2,8 @@
   Definitions based on NVMe spec. version 1.1.
 
   (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Specification Reference:
   NVMe Specification 1.1
@@ -86,6 +81,8 @@ typedef struct {
   UINT8  Iocqes:4;   // I/O Completion Queue Entry Size
   UINT8  Rsvd2;
 } NVME_CC;
+#define NVME_CC_SHN_NORMAL_SHUTDOWN    1
+#define NVME_CC_SHN_ABRUPT_SHUTDOWN    2
 
 //
 // 3.1.6 Offset 1Ch: CSTS - Controller Status
@@ -97,7 +94,8 @@ typedef struct {
   UINT32 Nssro:1;    // NVM Subsystem Reset Occurred
   UINT32 Rsvd1:27;
 } NVME_CSTS;
-
+#define NVME_CSTS_SHST_SHUTDOWN_OCCURRING 1
+#define NVME_CSTS_SHST_SHUTDOWN_COMPLETED 2
 //
 // 3.1.8 Offset 24h: AQA - Admin Queue Attributes
 //
@@ -311,11 +309,11 @@ typedef struct {
   UINT32 Exlat;             /* Exit Latency */
   UINT8  Rrt:5;             /* Relative Read Throughput */
   UINT8  Rsvd3:3;           /* Reserved as of Nvm Express 1.1 Spec */
-  UINT8  Rrl:5;             /* Relative Read Leatency */
+  UINT8  Rrl:5;             /* Relative Read Latency */
   UINT8  Rsvd4:3;           /* Reserved as of Nvm Express 1.1 Spec */
   UINT8  Rwt:5;             /* Relative Write Throughput */
   UINT8  Rsvd5:3;           /* Reserved as of Nvm Express 1.1 Spec */
-  UINT8  Rwl:5;             /* Relative Write Leatency */
+  UINT8  Rwl:5;             /* Relative Write Latency */
   UINT8  Rsvd6:3;           /* Reserved as of Nvm Express 1.1 Spec */
   UINT8  Rsvd7[16];         /* Reserved as of Nvm Express 1.1 Spec */
 } NVME_PSDESCRIPTOR;
@@ -331,7 +329,7 @@ typedef struct {
   UINT16 Ssvid;               /* PCI sub-system vendor ID */
   UINT8  Sn[20];              /* Product serial number */
 
-  UINT8  Mn[40];              /* Proeduct model number */
+  UINT8  Mn[40];              /* Product model number */
   UINT8  Fr[8];               /* Firmware Revision */
   UINT8  Rab;                 /* Recommended Arbitration Burst */
   UINT8  Ieee_oui[3];         /* Organization Unique Identifier */
@@ -659,7 +657,7 @@ typedef union {
 //
 typedef struct {
   //
-  // CDW 0, Common to all comnmands
+  // CDW 0, Common to all commands
   //
   UINT8  Opc;               // Opcode
   UINT8  Fuse:2;            // Fused Operation
@@ -871,7 +869,7 @@ typedef struct {
   //
   UINT8  AvailableSpareThreshold;
   //
-  // Contains a vendor specific estimate of the percentage of NVM subsystem life used based on the actual usage and the manufacturer?s prediction of NVM life. A value of 100 indicates that the estimated endurance of the NVM in the NVM subsystem has been consumed, but may not indicate an NVM subsystem failure. The value is allowed to exceed 100. Percentages greater than 254 shall be represented as 255. This value shall be updated once per power-on hour (when the controller is not in a sleep state).
+  // Contains a vendor specific estimate of the percentage of NVM subsystem life used based on the actual usage and the manufacturer's prediction of NVM life. A value of 100 indicates that the estimated endurance of the NVM in the NVM subsystem has been consumed, but may not indicate an NVM subsystem failure. The value is allowed to exceed 100. Percentages greater than 254 shall be represented as 255. This value shall be updated once per power-on hour (when the controller is not in a sleep state).
   //
   UINT8  PercentageUsed;
   UINT8  Reserved1[26];
diff --git a/MdePkg/Include/IndustryStandard/Pal.h b/MdePkg/Include/IndustryStandard/Pal.h
deleted file mode 100644
index 5dc26a2f7b10..000000000000
--- a/MdePkg/Include/IndustryStandard/Pal.h
+++ /dev/null
@@ -1,3302 +0,0 @@
-/** @file
-  Main PAL API's defined in Intel Itanium Architecture Software Developer's Manual.
-
-  Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
-
-**/
-
-#ifndef __PAL_API_H__
-#define __PAL_API_H__
-
-#define PAL_SUCCESS             0x0
-
-///
-/// CacheType of PAL_CACHE_FLUSH.
-///
-#define PAL_CACHE_FLUSH_INSTRUCTION_ALL   1
-#define PAL_CACHE_FLUSH_DATA_ALL          2
-#define PAL_CACHE_FLUSH_ALL               3
-#define PAL_CACHE_FLUSH_SYNC_TO_DATA      4
-
-
-///
-/// Bitmask of Opearation of PAL_CACHE_FLUSH.
-///
-#define PAL_CACHE_FLUSH_INVALIDATE_LINES     BIT0
-#define PAL_CACHE_FLUSH_NO_INVALIDATE_LINES  0
-#define PAL_CACHE_FLUSH_POLL_INTERRUPT       BIT1
-#define PAL_CACHE_FLUSH_NO_INTERRUPT         0
-
-/**
-  PAL Procedure - PAL_CACHE_FLUSH.
-
-  Flush the instruction or data caches. It is required by Itanium processors.
-  The PAL procedure supports the Static Registers calling
-  convention. It could be called at virtual mode and physical
-  mode.
-
-  @param Index              Index of PAL_CACHE_FLUSH within the
-                            list of PAL procedures.
-  @param CacheType          Unsigned 64-bit integer indicating
-                            which cache to flush.
-  @param Operation          Formatted bit vector indicating the
-                            operation of this call.
-  @param ProgressIndicator  Unsigned 64-bit integer specifying
-                            the starting position of the flush
-                            operation.
-
-  @retval 2                 Call completed without error, but a PMI
-                            was taken during the execution of this
-                            procedure.
-  @retval 1                 Call has not completed flushing due to
-                            a pending interrupt.
-  @retval 0                 Call completed without error
-  @retval -2                Invalid argument
-  @retval -3                Call completed with error
-
-  @return R9                Unsigned 64-bit integer specifying the vector
-                            number of the pending interrupt.
-  @return R10               Unsigned 64-bit integer specifying the
-                            starting position of the flush operation.
-  @return R11               Unsigned 64-bit integer specifying the vector
-                            number of the pending interrupt.
-
-**/
-#define PAL_CACHE_FLUSH   1
-
-
-///
-/// Attributes of PAL_CACHE_CONFIG_INFO1
-///
-#define PAL_CACHE_ATTR_WT   0
-#define PAL_CACHE_ATTR_WB   1
-
-///
-/// PAL_CACHE_CONFIG_INFO1.StoreHint
-///
-#define PAL_CACHE_STORE_TEMPORAL      0
-#define PAL_CACHE_STORE_NONE_TEMPORAL 3
-
-///
-/// PAL_CACHE_CONFIG_INFO1.StoreHint
-///
-#define PAL_CACHE_STORE_TEMPORAL_LVL_1        0
-#define PAL_CACHE_STORE_NONE_TEMPORAL_LVL_ALL 3
-
-///
-/// PAL_CACHE_CONFIG_INFO1.StoreHint
-///
-#define PAL_CACHE_LOAD_TEMPORAL_LVL_1         0
-#define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_1    1
-#define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_ALL  3
-
-///
-/// Detail the characteristics of a given processor controlled
-/// cache in the cache hierarchy.
-///
-typedef struct {
-  UINT64  IsUnified   : 1;
-  UINT64  Attributes  : 2;
-  UINT64  Associativity:8;
-  UINT64  LineSize:8;
-  UINT64  Stride:8;
-  UINT64  StoreLatency:8;
-  UINT64  StoreHint:8;
-  UINT64  LoadHint:8;
-} PAL_CACHE_INFO_RETURN1;
-
-///
-/// Detail the characteristics of a given processor controlled
-/// cache in the cache hierarchy.
-///
-typedef struct {
-  UINT64  CacheSize:32;
-  UINT64  AliasBoundary:8;
-  UINT64  TagLsBits:8;
-  UINT64  TagMsBits:8;
-} PAL_CACHE_INFO_RETURN2;
-
-/**
-  PAL Procedure - PAL_CACHE_INFO.
-
-  Return detailed instruction or data cache information. It is
-  required by Itanium processors. The PAL procedure supports the Static
-  Registers calling convention. It could be called at virtual
-  mode and physical mode.
-
-  @param Index        Index of PAL_CACHE_INFO within the list of
-                      PAL procedures.
-  @param CacheLevel   Unsigned 64-bit integer specifying the
-                      level in the cache hierarchy for which
-                      information is requested. This value must
-                      be between 0 and one less than the value
-                      returned in the cache_levels return value
-                      from PAL_CACHE_SUMMARY.
-  @param CacheType    Unsigned 64-bit integer with a value of 1
-                      for instruction cache and 2 for data or
-                      unified cache. All other values are
-                      reserved.
-  @param Reserved     Should be 0.
-
-  @retval 0           Call completed without error
-  @retval -2          Invalid argument
-  @retval -3          Call completed with error
-
-  @return R9          Detail the characteristics of a given
-                      processor controlled cache in the cache
-                      hierarchy. See PAL_CACHE_INFO_RETURN1.
-  @return R10         Detail the characteristics of a given
-                      processor controlled cache in the cache
-                      hierarchy. See PAL_CACHE_INFO_RETURN2.
-  @return R11         Reserved with 0.
-
-**/
-#define PAL_CACHE_INFO    2
-
-
-
-///
-/// Level of PAL_CACHE_INIT.
-///
-#define PAL_CACHE_INIT_ALL  0xffffffffffffffffULL
-
-///
-/// CacheType
-///
-#define PAL_CACHE_INIT_TYPE_INSTRUCTION                 0x1
-#define PAL_CACHE_INIT_TYPE_DATA                        0x2
-#define PAL_CACHE_INIT_TYPE_INSTRUCTION_AND_DATA        0x3
-
-///
-/// Restrict of PAL_CACHE_INIT.
-///
-#define PAL_CACHE_INIT_NO_RESTRICT  0
-#define PAL_CACHE_INIT_RESTRICTED   1
-
-/**
-  PAL Procedure - PAL_CACHE_INIT.
-
-  Initialize the instruction or data caches. It is required by
-  Itanium processors. The PAL procedure supports the Static Registers calling
-  convention. It could be called at physical mode.
-
-  @param Index      Index of PAL_CACHE_INIT within the list of PAL
-                    procedures.
-  @param Level      Unsigned 64-bit integer containing the level of
-                    cache to initialize. If the cache level can be
-                    initialized independently, only that level will
-                    be initialized. Otherwise
-                    implementation-dependent side-effects will
-                    occur.
-  @param CacheType  Unsigned 64-bit integer with a value of 1 to
-                    initialize the instruction cache, 2 to
-                    initialize the data cache, or 3 to
-                    initialize both. All other values are
-                    reserved.
-  @param Restrict   Unsigned 64-bit integer with a value of 0 or
-                    1. All other values are reserved. If
-                    restrict is 1 and initializing the specified
-                    level and cache_type of the cache would
-                    cause side-effects, PAL_CACHE_INIT will
-                    return -4 instead of initializing the cache.
-
-  @retval 0         Call completed without error
-  @retval -2        Invalid argument
-  @retval -3        Call completed with error.
-  @retval -4        Call could not initialize the specified
-                    level and cache_type of the cache without
-                    side-effects and restrict was 1.
-
-**/
-#define PAL_CACHE_INIT    3
-
-
-///
-/// PAL_CACHE_PROTECTION.Method.
-///
-#define PAL_CACHE_PROTECTION_NONE_PROTECT   0
-#define PAL_CACHE_PROTECTION_ODD_PROTECT    1
-#define PAL_CACHE_PROTECTION_EVEN_PROTECT   2
-#define PAL_CACHE_PROTECTION_ECC_PROTECT    3
-
-
-
-///
-/// PAL_CACHE_PROTECTION.TagOrData.
-///
-#define PAL_CACHE_PROTECTION_PROTECT_DATA   0
-#define PAL_CACHE_PROTECTION_PROTECT_TAG    1
-#define PAL_CACHE_PROTECTION_PROTECT_TAG_ANDTHEN_DATA   2
-#define PAL_CACHE_PROTECTION_PROTECT_DATA_ANDTHEN_TAG   3
-
-///
-/// 32-bit protection information structures.
-///
-typedef struct {
-  UINT32  DataBits:8;
-  UINT32  TagProtLsb:6;
-  UINT32  TagProtMsb:6;
-  UINT32  ProtBits:6;
-  UINT32  Method:4;
-  UINT32  TagOrData:2;
-} PAL_CACHE_PROTECTION;
-
-/**
-  PAL Procedure - PAL_CACHE_PROT_INFO.
-
-  Return instruction or data cache protection information. It is
-  required by Itanium processors. The PAL procedure supports the Static
-  Registers calling convention. It could be called at physical
-  mode and Virtual mode.
-
-  @param Index      Index of PAL_CACHE_PROT_INFO within the list of
-                    PAL procedures.
-  @param CacheLevel Unsigned 64-bit integer specifying the level
-                    in the cache hierarchy for which information
-                    is requested. This value must be between 0
-                    and one less than the value returned in the
-                    cache_levels return value from
-                    PAL_CACHE_SUMMARY.
-  @param CacheType  Unsigned 64-bit integer with a value of 1
-                    for instruction cache and 2 for data or
-                    unified cache. All other values are
-                    reserved.
-
-  @retval 0         Call completed without error
-  @retval -2        Invalid argument
-  @retval -3        Call completed with error.
-
-  @return R9        Detail the characteristics of a given
-                    processor controlled cache in the cache
-                    hierarchy. See PAL_CACHE_PROTECTION[0..1].
-  @return R10       Detail the characteristics of a given
-                    processor controlled cache in the cache
-                    hierarchy. See PAL_CACHE_PROTECTION[2..3].
-  @return R11       Detail the characteristics of a given
-                    processor controlled cache in the cache
-                    hierarchy. See PAL_CACHE_PROTECTION[4..5].
-
-**/
-#define PAL_CACHE_PROT_INFO     38
-
-typedef struct {
-  UINT64  ThreadId : 16;    ///< The thread identifier of the logical
-                            ///< processor for which information is being
-                            ///< returned. This value will be unique on a per core basis.
-  UINT64  Reserved1: 16;
-  UINT64  CoreId: 16;       ///< The core identifier of the logical processor
-                            ///< for which information is being returned.
-                            ///< This value will be unique on a per physical
-                            ///< processor package basis.
-  UINT64  Reserved2: 16;
-} PAL_PCOC_N_CACHE_INFO1;
-
-
-typedef struct {
-  UINT64  LogicalAddress : 16;  ///< Logical address: geographical address
-                                ///< of the logical processor for which
-                                ///< information is being returned. This is
-                                ///< the same value that is returned by the
-                                ///< PAL_FIXED_ADDR procedure when it is
-                                ///< called on the logical processor.
-  UINT64  Reserved1: 16;
-  UINT64  Reserved2: 32;
-} PAL_PCOC_N_CACHE_INFO2;
-
-/**
-  PAL Procedure - PAL_CACHE_SHARED_INFO.
-
-  Returns information on which logical processors share caches.
-  It is optional. The PAL procedure supports the Static
-  Registers calling convention. It could be called at physical
-  mode and Virtual mode.
-
-  @param Index       Index of PAL_CACHE_SHARED_INFO within the list
-                     of PAL procedures.
-  @param CacheLevel  Unsigned 64-bit integer specifying the
-                     level in the cache hierarchy for which
-                     information is requested. This value must
-                     be between 0 and one less than the value
-                     returned in the cache_levels return value
-                     from PAL_CACHE_SUMMARY.
-  @param CacheType   Unsigned 64-bit integer with a value of 1
-                     for instruction cache and 2 for data or
-                     unified cache. All other values are
-                     reserved.
-  @param ProcNumber  Unsigned 64-bit integer that specifies for
-                     which logical processor information is
-                     being requested. This input argument must
-                     be zero for the first call to this
-                     procedure and can be a maximum value of
-                     one less than the number of logical
-                     processors sharing this cache, which is
-                     returned by the num_shared return value.
-
-  @retval 0          Call completed without error
-  @retval -1         Unimplemented procedure
-  @retval -2         Invalid argument
-  @retval -3         Call completed with error.
-
-  @return R9         Unsigned integer that returns the number of
-                     logical processors that share the processor
-                     cache level and type, for which information was
-                     requested.
-  @return R10        The format of PAL_PCOC_N_CACHE_INFO1.
-  @return R11        The format of PAL_PCOC_N_CACHE_INFO2.
-
-**/
-#define PAL_CACHE_SHARED_INFO   43
-
-
-/**
-  PAL Procedure - PAL_CACHE_SUMMARY.
-
-  Return a summary of the cache hierarchy. It is required by
-  Itanium processors. The PAL procedure supports the Static Registers calling
-  convention. It could be called at physical mode and Virtual
-  mode.
-
-  @param Index  Index of PAL_CACHE_SUMMARY within the list of
-                PAL procedures.
-
-  @retval 0     Call completed without error
-  @retval -2    Invalid argument
-  @retval -3    Call completed with error.
-
-  @return R9    CacheLevels   Unsigned 64-bit integer denoting the
-                              number of levels of cache
-                              implemented by the processor.
-                              Strictly, this is the number of
-                              levels for which the cache
-                              controller is integrated into the
-                              processor (the cache SRAMs may be
-                              external to the processor).
-  @return R10   UniqueCaches  Unsigned 64-bit integer denoting the
-                              number of unique caches implemented
-                              by the processor. This has a maximum
-                              of 2*cache_levels, but may be less
-                              if any of the levels in the cache
-                              hierarchy are unified caches or do
-                              not have both instruction and data
-                              caches.
-
-**/
-#define PAL_CACHE_SUMMARY   4
-
-
-//
-// Virtual Memory Attributes implemented by processor.
-//
-#define PAL_MEMORY_ATTR_WB      0
-#define PAL_MEMORY_ATTR_WC      6
-#define PAL_MEMORY_ATTR_UC      4
-#define PAL_MEMORY_ATTR_UCE     5
-#define PAL_MEMORY_ATTR_NATPAGE 7
-
-/**
-  PAL Procedure - PAL_MEM_ATTRIB.
-
-  Return a list of supported memory attributes.. It is required
-  by Itanium processors. The PAL procedure supports the Static Registers calling
-  convention. It could be called at physical mode and Virtual
-  mode.
-
-  @param Index  Index of PAL_MEM_ATTRIB within the list of PAL
-                procedures.
-
-  @retval 0     Call completed without error
-  @retval -2    Invalid argument
-  @retval -3    Call completed with error.
-
-  @return R9    Attributes  8-bit vector of memory attributes
-                            implemented by processor. See Virtual
-                            Memory Attributes above.
-
-**/
-
-#define PAL_MEM_ATTRIB      5
-
-/**
-  PAL Procedure - PAL_PREFETCH_VISIBILITY.
-
-  Used in architected sequence to transition pages from a
-  cacheable, speculative attribute to an uncacheable attribute.
-  It is required by Itanium processors. The PAL procedure supports the Static
-  Registers calling convention. It could be called at physical
-  mode and Virtual mode.
-
-  @param Index          Index of PAL_PREFETCH_VISIBILITY within the list
-                        of PAL procedures.
-  @param TransitionType Unsigned integer specifying the type
-                        of memory attribute transition that is
-                        being performed.
-
-  @retval 1             Call completed without error; this
-                        call is not necessary on remote
-                        processors.
-  @retval 0             Call completed without error
-  @retval -2            Invalid argument
-  @retval -3            Call completed with error.
-
-**/
-#define PAL_PREFETCH_VISIBILITY   41
-
-/**
-  PAL Procedure - PAL_PTCE_INFO.
-
-  Return information needed for ptc.e instruction to purge
-  entire TC. It is required by Itanium processors. The PAL procedure supports
-  the Static Registers calling convention. It could be called at
-  physical mode and Virtual mode.
-
-  @param Index  Index of PAL_PTCE_INFO within the list
-                of PAL procedures.
-
-  @retval 0     Call completed without error
-  @retval -2    Invalid argument
-  @retval -3    Call completed with error.
-
-  @return R9    Unsigned 64-bit integer denoting the beginning
-                address to be used by the first PTCE instruction
-                in the purge loop.
-  @return R10   Two unsigned 32-bit integers denoting the loop
-                counts of the outer (loop 1) and inner (loop 2)
-                purge loops. count1 (loop 1) is contained in bits
-                63:32 of the parameter, and count2 (loop 2) is
-                contained in bits 31:0 of the parameter.
-  @return R11   Two unsigned 32-bit integers denoting the loop
-                strides of the outer (loop 1) and inner (loop 2)
-                purge loops. stride1 (loop 1) is contained in bits
-                63:32 of the parameter, and stride2 (loop 2) is
-                contained in bits 31:0 of the parameter.
-
-**/
-#define PAL_PTCE_INFO     6
-
-typedef struct {
-  UINT64  NumberSets:8;             ///< Unsigned 8-bit integer denoting the number
-                                    ///< of hash sets for the specified level
-                                    ///< (1=fully associative)
-  UINT64  NumberWays:8;             ///< Unsigned 8-bit integer denoting the
-                                    ///< associativity of the specified level
-                                    ///< (1=direct).
-  UINT64  NumberEntries:16;         ///< Unsigned 16-bit integer denoting the
-                                    ///< number of entries in the specified TC.
-  UINT64  PageSizeIsOptimized:1;    ///< Flag denoting whether the
-                                    ///< specified level is optimized for
-                                    ///< the region's preferred page size
-                                    ///< (1=optimized) tc_pages indicates
-                                    ///< which page sizes are usable by
-                                    ///< this translation cache.
-  UINT64  TcIsUnified:1;            ///< Flag denoting whether the specified TC is
-                                    ///< unified (1=unified).
-  UINT64  EntriesReduction:1;       ///< Flag denoting whether installed
-                                    ///< translation registers will reduce
-                                    ///< the number of entries within the
-                                    ///< specified TC.
-} PAL_TC_INFO;
-
-/**
-  PAL Procedure - PAL_VM_INFO.
-
-  Return detailed information about virtual memory features
-  supported in the processor. It is required by Itanium processors. The PAL
-  procedure supports the Static Registers calling convention. It
-  could be called at physical mode and Virtual mode.
-
-  @param Index    Index of PAL_VM_INFO within the list
-                  of PAL procedures.
-  @param TcLevel  Unsigned 64-bit integer specifying the level
-                  in the TLB hierarchy for which information is
-                  required. This value must be between 0 and one
-                  less than the value returned in the
-                  vm_info_1.num_tc_levels return value from
-                  PAL_VM_SUMMARY.
-  @param TcType   Unsigned 64-bit integer with a value of 1 for
-                  instruction translation cache and 2 for data
-                  or unified translation cache. All other values
-                  are reserved.
-
-  @retval 0       Call completed without error
-  @retval -2      Invalid argument
-  @retval -3      Call completed with error.
-
-  @return R9      8-byte formatted value returning information
-                  about the specified TC. See PAL_TC_INFO above.
-  @return R10     64-bit vector containing a bit for each page
-                  size supported in the specified TC, where bit
-                  position n indicates a page size of 2**n.
-
-**/
-#define PAL_VM_INFO       7
-
-
-/**
-  PAL Procedure - PAL_VM_PAGE_SIZE.
-
-  Return virtual memory TC and hardware walker page sizes
-  supported in the processor. It is required by Itanium processors. The PAL
-  procedure supports the Static Registers calling convention. It
-  could be called at physical mode and Virtual mode.
-
-  @param Index  Index of PAL_VM_PAGE_SIZE within the list
-                of PAL procedures.
-
-  @retval 0     Call completed without error
-  @retval -2    Invalid argument
-  @retval -3    Call completed with error.
-
-  @return R9    64-bit vector containing a bit for each
-                architected page size that is supported for
-                TLB insertions and region registers.
-  @return R10   64-bit vector containing a bit for each
-                architected page size supported for TLB purge
-                operations.
-
-**/
-#define PAL_VM_PAGE_SIZE 34
-
-typedef struct {
-  UINT64  WalkerPresent:1;              ///< 1-bit flag indicating whether a hardware
-                                        ///< TLB walker is implemented (1 = walker
-                                        ///< present).
-  UINT64  WidthOfPhysicalAddress: 7;    ///< Unsigned 7-bit integer
-                                        ///< denoting the number of bits of
-                                        ///< physical address implemented.
-  UINT64  WidthOfKey:8;                 ///< Unsigned 8-bit integer denoting the number
-                                        ///< of bits mplemented in the PKR.key field.
-  UINT64  MaxPkrIndex:8;                ///< Unsigned 8-bit integer denoting the
-                                        ///< maximum PKR index (number of PKRs-1).
-  UINT64  HashTagId:8;                  ///< Unsigned 8-bit integer which uniquely
-                                        ///< identifies the processor hash and tag
-                                        ///< algorithm.
-  UINT64  MaxDtrIndex:8;                ///< Unsigned 8 bit integer denoting the
-                                        ///< maximum data translation register index
-                                        ///< (number of dtr entries - 1).
-  UINT64  MaxItrIndex:8;                ///< Unsigned 8 bit integer denoting the
-                                        ///< maximum instruction translation register
-                                        ///< index (number of itr entries - 1).
-  UINT64  NumberOfUniqueTc:8;           ///< Unsigned 8-bit integer denoting the
-                                        ///< number of unique TCs implemented.
-                                        ///< This is a maximum of
-                                        ///< 2*num_tc_levels.
-  UINT64  NumberOfTcLevels:8;           ///< Unsigned 8-bit integer denoting the
-                                        ///< number of TC levels.
-} PAL_VM_INFO1;
-
-typedef struct {
-  UINT64  WidthOfVirtualAddress:8;  ///< Unsigned 8-bit integer denoting
-                                    ///< is the total number of virtual
-                                    ///< address bits - 1.
-  UINT64  WidthOfRid:8;             ///< Unsigned 8-bit integer denoting the number
-                                    ///< of bits implemented in the RR.rid field.
-  UINT64  MaxPurgedTlbs:16;         ///< Unsigned 16 bit integer denoting the
-                                    ///< maximum number of concurrent outstanding
-                                    ///< TLB purges allowed by the processor. A
-                                    ///< value of 0 indicates one outstanding
-                                    ///< purge allowed. A value of 216-1
-                                    ///< indicates no limit on outstanding
-                                    ///< purges. All other values indicate the
-                                    ///< actual number of concurrent outstanding
-                                    ///< purges allowed.
-  UINT64  Reserved:32;
-} PAL_VM_INFO2;
-
-/**
-  PAL Procedure - PAL_VM_SUMMARY.
-
-  Return summary information about virtual memory features
-  supported in the processor. It is required by Itanium processors. The PAL
-  procedure supports the Static Registers calling convention. It
-  could be called at physical mode and Virtual mode.
-
-  @param Index  Index of PAL_VM_SUMMARY within the list
-                of PAL procedures.
-
-  @retval 0     Call completed without error
-  @retval -2    Invalid argument
-  @retval -3    Call completed with error.
-
-  @return R9    8-byte formatted value returning global virtual
-                memory information. See PAL_VM_INFO1 above.
-  @return R10   8-byte formatted value returning global virtual
-                memory information. See PAL_VM_INFO2 above.
-
-**/
-#define PAL_VM_SUMMARY  8
-
-
-//
-// Bit mask of TR_valid flag.
-//
-#define PAL_TR_ACCESS_RIGHT_IS_VALID      BIT0
-#define PAL_TR_PRIVILEGE_LEVEL_IS_VALID   BIT1
-#define PAL_TR_DIRTY_IS_VALID             BIT2
-#define PAL_TR_MEMORY_ATTR_IS_VALID       BIT3
-
-
-/**
-  PAL Procedure - PAL_VM_TR_READ.
-
-  Read contents of a translation register. It is required by
-  Itanium processors. The PAL procedure supports the Stacked Register calling
-  convention. It could be called at physical mode.
-
-  @param Index      Index of PAL_VM_TR_READ within the list
-                    of PAL procedures.
-  @param RegNumber  Unsigned 64-bit number denoting which TR to
-                    read.
-  @param TrType     Unsigned 64-bit number denoting whether to
-                    read an ITR (0) or DTR (1). All other values
-                    are reserved.
-  @param TrBuffer   64-bit pointer to the 32-byte memory buffer in
-                    which translation data is returned.
-
-  @retval 0         Call completed without error
-  @retval -2        Invalid argument
-  @retval -3        Call completed with error.
-
-  @return R9        Formatted bit vector denoting which fields are
-                    valid. See TR_valid above.
-
-**/
-#define PAL_VM_TR_READ  261
-
-
-
-
-//
-// Bit Mask of Processor Bus Fesatures .
-//
-
-/**
-
-  When 0, bus data errors are detected and single bit errors are
-  corrected. When 1, no error detection or correction is done.
-
-**/
-#define PAL_BUS_DISABLE_DATA_ERROR_SIGNALLING   BIT63
-
-
-/**
-
-  When 0, bus address errors are signalled on the bus. When 1,
-  no bus errors are signalled on the bus. If Disable Bus Address
-  Error Checking is 1, this bit is ignored.
-
-**/
-#define PAL_BUS_DISABLE_ADDRESS_ERROR_SIGNALLING   BIT62
-
-
-
-
-/**
-
-  When 0, bus errors are detected, single bit errors are
-  corrected., and a CMCI or MCA is generated internally to the
-  processor. When 1, no bus address errors are detected or
-  corrected.
-
-**/
-#define PAL_BUS_DISABLE_ADDRESS_ERROR_CHECK   BIT61
-
-
-/**
-
-  When 0, bus protocol errors (BINIT#) are signaled by the
-  processor on the bus. When 1, bus protocol errors (BINIT#) are
-  not signaled on the bus. If Disable Bus Initialization Event
-  Checking is 1, this bit is ignored.
-
-**/
-#define PAL_BUS_DISABLE_INITIALIZATION_EVENT_SIGNALLING   BIT60
-
-
-/**
-
-  When 0, bus protocol errors (BINIT#) are detected and sampled
-  and an MCA is generated internally to the processor. When 1,
-  the processor will ignore bus protocol error conditions
-  (BINIT#).
-
-**/
-#define PAL_BUS_DISABLE_INITIALIZATION_EVENT_CHECK   BIT59
-
-
-
-/**
-
-  When 0, BERR# is signalled if a bus error is detected. When 1,
-  bus errors are not signalled on the bus.
-
-**/
-#define PAL_BUS_DISABLE_ERROR_SIGNALLING   BIT58
-
-
-
-
-/**
-
-  When 0, BERR# is signalled when internal processor requestor
-  initiated bus errors are detected. When 1, internal requester
-  bus errors are not signalled on the bus.
-
-**/
-#define PAL_BUS_DISABLE__INTERNAL_ERROR_SIGNALLING   BIT57
-
-
-/**
-
-  When 0, the processor takes an MCA if BERR# is asserted. When
-  1, the processor ignores the BERR# signal.
-
-**/
-#define PAL_BUS_DISABLE_ERROR_CHECK   BIT56
-
-
-/**
-
-  When 0, the processor asserts BINIT# if it detects a parity
-  error on the signals which identify the transactions to which
-  this is a response. When 1, the processor ignores parity on
-  these signals.
-
-**/
-#define PAL_BUS_DISABLE_RSP_ERROR_CHECK   BIT55
-
-
-/**
-
-  When 0, the in-order transaction queue is limited only by the
-  number of hardware entries. When 1, the processor's in-order
-  transactions queue is limited to one entry.
-
-**/
-#define PAL_BUS_DISABLE_TRANSACTION_QUEUE   BIT54
-
-/**
-
-  Enable a bus cache line replacement transaction when a cache
-  line in the exclusive state is replaced from the highest level
-  processor cache and is not present in the lower level processor
-  caches. When 0, no bus cache line replacement transaction will
-  be seen on the bus. When 1, bus cache line replacement
-  transactions will be seen on the bus when the above condition is
-  detected.
-
-**/
-#define PAL_BUS_ENABLE_EXCLUSIVE_CACHE_LINE_REPLACEMENT   BIT53
-
-
-/**
-
-  Enable a bus cache line replacement transaction when a cache
-  line in the shared or exclusive state is replaced from the
-  highest level processor cache and is not present in the lower
-  level processor caches.
-  When 0, no bus cache line replacement transaction will be seen
-  on the bus. When 1, bus cache line replacement transactions
-  will be seen on the bus when the above condition is detected.
-
-**/
-#define PAL_BUS_ENABLE_SHARED_CACHE_LINE_REPLACEMENT   BIT52
-
-
-
-/**
-
-  When 0, the data bus is configured at the 2x data transfer
-  rate.When 1, the data bus is configured at the 1x data
-  transfer rate, 30 Opt. Req. Disable Bus Lock Mask. When 0, the
-  processor executes locked transactions atomically. When 1, the
-  processor masks the bus lock signal and executes locked
-  transactions as a non-atomic series of transactions.
-
-**/
-#define PAL_BUS_ENABLE_HALF_TRANSFER   BIT30
-
-/**
-
-  When 0, the processor will deassert bus request when finished
-  with each transaction. When 1, the processor will continue to
-  assert bus request after it has finished, if it was the last
-  agent to own the bus and if there are no other pending
-  requests.
-
-**/
-#define PAL_BUS_REQUEST_BUS_PARKING   BIT29
-
-
-/**
-  PAL Procedure - PAL_BUS_GET_FEATURES.
-
-  Return configurable processor bus interface features and their
-  current settings. It is required by Itanium processors. The PAL procedure
-  supports the Stacked Register calling convention. It could be
-  called at physical mode.
-
-  @param Index  Index of PAL_BUS_GET_FEATURES within the list
-                of PAL procedures.
-
-  @retval 0     Call completed without error
-  @retval -2    Invalid argument
-  @retval -3    Call completed with error.
-
-  @return R9    64-bit vector of features implemented.
-                (1=implemented, 0=not implemented)
-  @return R10   64-bit vector of current feature settings.
-  @return R11   64-bit vector of features controllable by
-                software. (1=controllable, 0= not controllable)
-
-**/
-#define PAL_BUS_GET_FEATURES 9
-
-/**
-  PAL Procedure - PAL_BUS_SET_FEATURES.
-
-  Enable or disable configurable features in processor bus
-  interface. It is required by Itanium processors. The PAL procedure
-  supports the Static Registers calling convention. It could be
-  called at physical mode.
-
-  @param Index          Index of PAL_BUS_SET_FEATURES within the list
-                        of PAL procedures.
-  @param FeatureSelect  64-bit vector denoting desired state of
-                        each feature (1=select, 0=non-select).
-
-  @retval 0             Call completed without error
-  @retval -2            Invalid argument
-  @retval -3            Call completed with error.
-
-**/
-#define PAL_BUS_SET_FEATURES 10
-
-
-/**
-  PAL Procedure - PAL_DEBUG_INFO.
-
-  Return the number of instruction and data breakpoint
-  registers. It is required by Itanium processors. The
-  PAL procedure supports the Static Registers calling
-  convention. It could be called at physical mode and virtual
-  mode.
-
-  @param Index  Index of PAL_DEBUG_INFO within the list of PAL
-                procedures.
-
-  @retval 0     Call completed without error
-  @retval -2    Invalid argument
-  @retval -3    Call completed with error.
-
-  @return R9    Unsigned 64-bit integer denoting the number of
-                pairs of instruction debug registers implemented
-                by the processor.
-  @return R10   Unsigned 64-bit integer denoting the number of
-                pairs of data debug registers implemented by the
-                processor.
-
-**/
-#define PAL_DEBUG_INFO  11
-
-/**
-  PAL Procedure - PAL_FIXED_ADDR.
-
-  Return the fixed component of a processor's directed address.
-  It is required by Itanium processors. The PAL
-  procedure supports the Static Registers calling convention. It
-  could be called at physical mode and virtual mode.
-
-  @param Index  Index of PAL_FIXED_ADDR within the list of PAL
-                procedures.
-
-  @retval 0     Call completed without error
-  @retval -2    Invalid argument
-  @retval -3    Call completed with error.
-
-  @return R9    Fixed geographical address of this processor.
-
-**/
-#define PAL_FIXED_ADDR 12
-
-/**
-  PAL Procedure - PAL_FREQ_BASE.
-
-  Return the frequency of the output clock for use by the
-  platform, if generated by the processor. It is optinal. The
-  PAL procedure supports the Static Registers calling
-  convention. It could be called at physical mode and virtual
-  mode.
-
-  @param Index  Index of PAL_FREQ_BASE within the list of PAL
-                procedures.
-
-  @retval 0     Call completed without error
-  @retval -1    Unimplemented procedure
-  @retval -2    Invalid argument
-  @retval -3    Call completed with error.
-
-  @return R9    Base frequency of the platform if generated by the
-                processor chip.
-
-**/
-#define PAL_FREQ_BASE 13
-
-
-/**
-  PAL Procedure - PAL_FREQ_RATIOS.
-
-  Return ratio of processor, bus, and interval time counter to
-  processor input clock or output clock for platform use, if
-  generated by the processor. It is required by Itanium processors. The PAL
-  procedure supports the Static Registers calling convention. It
-  could be called at physical mode and virtual mode.
-
-  @param Index  Index of PAL_FREQ_RATIOS within the list of PAL
-                procedures.
-
-  @retval 0     Call completed without error
-  @retval -2    Invalid argument
-  @retval -3    Call completed with error.
-
-  @return R9    Ratio of the processor frequency to the input
-                clock of the processor, if the platform clock is
-                generated externally or to the output clock to the
-                platform, if the platform clock is generated by
-                the processor.
-  @return R10   Ratio of the bus frequency to the input clock of
-                the processor, if the platform clock is generated
-                externally or to the output clock to the platform,
-                if the platform clock is generated by the
-                processor.
-  @return R11   Ratio of the interval timer counter rate to input
-                clock of the processor, if the platform clock is
-                generated externally or to the output clock to the
-                platform, if the platform clock is generated by
-                the processor.
-
-**/
-#define PAL_FREQ_RATIOS 14
-
-typedef struct {
-  UINT64  NumberOfLogicalProcessors:16;     ///< Total number of logical
-                                            ///< processors on this physical
-                                            ///< processor package that are
-                                            ///< enabled.
-  UINT64  ThreadsPerCore:8;                 ///< Number of threads per core.
-  UINT64  Reserved1:8;
-  UINT64  CoresPerProcessor:8;              ///< Total number of cores on this
-                                            ///< physical processor package.
-  UINT64  Reserved2:8;
-  UINT64  PhysicalProcessorPackageId:8;     ///< Physical processor package
-                                            ///< identifier which was
-                                            ///< assigned at reset by the
-                                            ///< platform or bus
-                                            ///< controller. This value may
-                                            ///< or may not be unique
-                                            ///< across the entire platform
-                                            ///< since it depends on the
-                                            ///< platform vendor's policy.
-  UINT64  Reserved3:8;
-} PAL_LOGICAL_PROCESSPR_OVERVIEW;
-
-typedef struct {
-   UINT64 ThreadId:16;      ///< The thread identifier of the logical
-                            ///< processor for which information is being
-                            ///< returned. This value will be unique on a per
-                            ///< core basis.
-   UINT64 Reserved1:16;
-   UINT64 CoreId:16;        ///< The core identifier of the logical processor
-                            ///< for which information is being returned.
-                            ///< This value will be unique on a per physical
-                            ///< processor package basis.
-   UINT64 Reserved2:16;
-} PAL_LOGICAL_PROCESSORN_INFO1;
-
-typedef struct {
-   UINT64 LogicalAddress:16;    ///< Geographical address of the logical
-                                ///< processor for which information is being
-                                ///< returned. This is the same value that is
-                                ///< returned by the PAL_FIXED_ADDR procedure
-                                ///< when it is called on the logical processor.
-   UINT64 Reserved:48;
-} PAL_LOGICAL_PROCESSORN_INFO2;
-
-/**
-  PAL Procedure - PAL_LOGICAL_TO_PHYSICAL.
-
-  Return information on which logical processors map to a
-  physical processor die. It is optinal. The PAL procedure
-  supports the Static Registers calling convention. It could be
-  called at physical mode and virtual mode.
-
-  @param Index            Index of PAL_LOGICAL_TO_PHYSICAL within the list of PAL
-                          procedures.
-  @param ProcessorNumber  Signed 64-bit integer that specifies
-                          for which logical processor
-                          information is being requested. When
-                          this input argument is -1, information
-                          is returned about the logical
-                          processor on which the procedure call
-                          is made. This input argument must be
-                          in the range of 1 up to one less than
-                          the number of logical processors
-                          returned by num_log in the
-                          log_overview return value.
-
-  @retval 0               Call completed without error
-  @retval -1              Unimplemented procedure
-  @retval -2              Invalid argument
-  @retval -3              Call completed with error.
-
-  @return R9              The format of PAL_LOGICAL_PROCESSPR_OVERVIEW.
-  @return R10             The format of PAL_LOGICAL_PROCESSORN_INFO1.
-  @return R11             The format of PAL_LOGICAL_PROCESSORN_INFO2.
-
-**/
-#define PAL_LOGICAL_TO_PHYSICAL 42
-
-typedef struct {
-  UINT64  NumberOfPmcPairs:8;               ///< Unsigned 8-bit number defining the
-                                            ///< number of generic PMC/PMD pairs.
-  UINT64  WidthOfCounter:8;                 ///< Unsigned 8-bit number in the range
-                                            ///< 0:60 defining the number of
-                                            ///< implemented counter bits.
-  UINT64  TypeOfCycleCounting:8;            ///< Unsigned 8-bit number defining the
-                                            ///< event type for counting processor cycles.
-  UINT64  TypeOfRetiredInstructionBundle:8; ///< Retired Unsigned 8-bit
-                                            ///< number defining the
-                                            ///< event type for retired
-                                            ///< instruction bundles.
-  UINT64  Reserved:32;
-} PAL_PERFORMANCE_INFO;
-
-/**
-  PAL Procedure - PAL_PERF_MON_INFO.
-
-  Return the number and type of performance monitors. It is
-  required by Itanium processors. The PAL procedure supports the Static
-  Registers calling convention. It could be called at physical
-  mode and virtual mode.
-
-  @param Index              Index of PAL_PERF_MON_INFO within the list of
-                            PAL procedures.
-  @param PerformanceBuffer  An address to an 8-byte aligned
-                            128-byte memory buffer.
-
-  @retval 0                 Call completed without error
-  @retval -2                Invalid argument
-  @retval -3                Call completed with error.
-
-  @return R9                Information about the performance monitors
-                            implemented. See PAL_PERFORMANCE_INFO;
-
-**/
-#define PAL_PERF_MON_INFO 15
-
-#define PAL_PLATFORM_ADDR_INTERRUPT_BLOCK_TOKEN                       0x0
-#define PAL_PLATFORM_ADDR_IO_BLOCK_TOKEN                              0x1
-
-/**
-  PAL Procedure - PAL_PLATFORM_ADDR.
-
-  Specify processor interrupt block address and I/O port space
-  address. It is required by Itanium processors. The PAL procedure supports the
-  Static Registers calling convention. It could be called at
-  physical mode and virtual mode.
-
-  @param Index    Index of PAL_PLATFORM_ADDR within the list of
-                  PAL procedures.
-  @param Type     Unsigned 64-bit integer specifying the type of
-                  block. 0 indicates that the processor interrupt
-                  block pointer should be initialized. 1 indicates
-                  that the processor I/O block pointer should be
-                  initialized.
-  @param Address  Unsigned 64-bit integer specifying the address
-                  to which the processor I/O block or interrupt
-                  block shall be set. The address must specify
-                  an implemented physical address on the
-                  processor model, bit 63 is ignored.
-
-  @retval 0       Call completed without error
-  @retval -1      Unimplemented procedure.
-  @retval -2      Invalid argument
-  @retval -3      Call completed with error.
-
-**/
-#define PAL_PLATFORM_ADDR 16
-
-typedef struct {
-  UINT64  Reserved1:36;
-  UINT64  FaultInUndefinedIns:1;                ///< Bit36, No Unimplemented
-                                                ///< instruction address reported as
-                                                ///< fault. Denotes how the processor
-                                                ///< reports the detection of
-                                                ///< unimplemented instruction
-                                                ///< addresses. When 1, the processor
-                                                ///< reports an Unimplemented
-                                                ///< Instruction Address fault on the
-                                                ///< unimplemented address; when 0, it
-                                                ///< reports an Unimplemented
-                                                ///< Instruction Address trap on the
-                                                ///< previous instruction in program
-                                                ///< order. This feature may only be
-                                                ///< interrogated by
-                                                ///< PAL_PROC_GET_FEATURES. It may not
-                                                ///< be enabled or disabled by
-                                                ///< PAL_PROC_SET_FEATURES. The
-                                                ///< corresponding argument is ignored.
-                                                
-  UINT64  NoPresentPmi:1;                       ///< Bit37, No INIT, PMI, and LINT pins
-                                                ///< present. Denotes the absence of INIT,
-                                                ///< PMI, LINT0 and LINT1 pins on the
-                                                ///< processor. When 1, the pins are absent.
-                                                ///< When 0, the pins are present. This
-                                                ///< feature may only be interrogated by
-                                                ///< PAL_PROC_GET_FEATURES. It may not be
-                                                ///< enabled or disabled by
-                                                ///< PAL_PROC_SET_FEATURES. The corresponding
-                                                ///< argument is ignored.
-                                                
-  UINT64  NoSimpleImpInUndefinedIns:1;          ///< Bit38, No Simple
-                                                ///< implementation of
-                                                ///< unimplemented instruction
-                                                ///< addresses. Denotes how an
-                                                ///< unimplemented instruction
-                                                ///< address is recorded in IIP
-                                                ///< on an Unimplemented
-                                                ///< Instruction Address trap or
-                                                ///< fault. When 1, the full
-                                                ///< unimplemented address is
-                                                ///< recorded in IIP; when 0, the
-                                                ///< address is sign extended
-                                                ///< (virtual addresses) or zero
-                                                ///< extended (physical
-                                                ///< addresses). This feature may
-                                                ///< only be interrogated by
-                                                ///< PAL_PROC_GET_FEATURES. It
-                                                ///< may not be enabled or
-                                                ///< disabled by
-                                                ///< PAL_PROC_SET_FEATURES. The
-                                                ///< corresponding argument is
-                                                ///< ignored.
-
-  UINT64  NoVariablePState:1;                   ///< Bit39, No Variable P-state
-                                                ///< performance: A value of 1, indicates
-                                                ///< that a processor implements
-                                                ///< techniques to optimize performance
-                                                ///< for the given P-state power budget
-                                                ///< by dynamically varying the
-                                                ///< frequency, such that maximum
-                                                ///< performance is achieved for the
-                                                ///< power budget. A value of 0,
-                                                ///< indicates that P-states have no
-                                                ///< frequency variation or very small
-                                                ///< frequency variations for their given
-                                                ///< power budget. This feature may only
-                                                ///< be interrogated by
-                                                ///< PAL_PROC_GET_FEATURES. it may not be
-                                                ///< enabled or disabled by
-                                                ///< PAL_PROC_SET_FEATURES. The
-                                                ///< corresponding argument is ignored.
-
-  UINT64  NoVM:1;                               ///< Bit40, No Virtual Machine features implemented.
-                                                ///< Denotes whether PSR.vm is implemented. This
-                                                ///< feature may only be interrogated by
-                                                ///< PAL_PROC_GET_FEATURES. It may not be enabled or
-                                                ///< disabled by PAL_PROC_SET_FEATURES. The
-                                                ///< corresponding argument is ignored.
-
-  UINT64  NoXipXpsrXfs:1;                       ///< Bit41, No XIP, XPSR, and XFS
-                                                ///< implemented. Denotes whether XIP, XPSR,
-                                                ///< and XFS are implemented for machine
-                                                ///< check recovery. This feature may only be
-                                                ///< interrogated by PAL_PROC_GET_FEATURES.
-                                                ///< It may not be enabled or disabled by
-                                                ///< PAL_PROC_SET_FEATURES. The corresponding
-                                                ///< argument is ignored.
-
-  UINT64  NoXr1ThroughXr3:1;                    ///< Bit42, No XR1 through XR3 implemented.
-                                                ///<   Denotes whether XR1 XR3 are
-                                                ///<   implemented for machine check
-                                                ///<   recovery. This feature may only be
-                                                ///<   interrogated by PAL_PROC_GET_FEATURES.
-                                                ///<   It may not be enabled or disabled by
-                                                ///<   PAL_PROC_SET_FEATURES. The
-                                                ///<   corresponding argument is ignored.
-
-  UINT64  DisableDynamicPrediction:1;           ///< Bit43, Disable Dynamic
-                                                ///< Predicate Prediction. When
-                                                ///< 0, the processor may predict
-                                                ///< predicate results and
-                                                ///< execute speculatively, but
-                                                ///< may not commit results until
-                                                ///< the actual predicates are
-                                                ///< known. When 1, the processor
-                                                ///< shall not execute predicated
-                                                ///< instructions until the
-                                                ///< actual predicates are known.
-
-  UINT64  DisableSpontaneousDeferral:1;         ///< Bit44, Disable Spontaneous
-                                                ///<   Deferral. When 1, the
-                                                ///<   processor may optionally
-                                                ///<   defer speculative loads
-                                                ///<   that do not encounter any
-                                                ///<   exception conditions, but
-                                                ///<   that trigger other
-                                                ///<   implementation-dependent
-                                                ///<   conditions (e.g., cache
-                                                ///<   miss). When 0, spontaneous
-                                                ///<   deferral is disabled.
-
-  UINT64  DisableDynamicDataCachePrefetch:1;    ///< Bit45, Disable Dynamic
-                                                ///<   Data Cache Prefetch.
-                                                ///<   When 0, the processor
-                                                ///<   may prefetch into the
-                                                ///<   caches any data which
-                                                ///<   has not been accessed
-                                                ///<   by instruction
-                                                ///<   execution, but which
-                                                ///<   is likely to be
-                                                ///<   accessed. When 1, no
-                                                ///<   data may be fetched
-                                                ///<   until it is needed for
-                                                ///<   instruction execution
-                                                ///<   or is fetched by an
-                                                ///<   lfetch instruction.
-
-  UINT64  DisableDynamicInsCachePrefetch:1;     ///< Bit46, Disable
-                                                ///< DynamicInstruction Cache
-                                                ///< Prefetch. When 0, the
-                                                ///< processor may prefetch
-                                                ///< into the caches any
-                                                ///< instruction which has
-                                                ///< not been executed, but
-                                                ///< whose execution is
-                                                ///< likely. When 1,
-                                                ///< instructions may not be
-                                                ///< fetched until needed or
-                                                ///< hinted for execution.
-                                                ///< (Prefetch for a hinted
-                                                ///< branch is allowed even
-                                                ///< when dynamic instruction
-                                                ///< cache prefetch is
-                                                ///< disabled.)
-
-  UINT64  DisableBranchPrediction:1;            ///< Bit47, Disable Dynamic branch
-                                                ///<   prediction. When 0, the
-                                                ///<   processor may predict branch
-                                                ///<   targets and speculatively
-                                                ///<   execute, but may not commit
-                                                ///<   results. When 1, the processor
-                                                ///<   must wait until branch targets
-                                                ///<   are known to execute.
-  UINT64  Reserved2:4;
-  UINT64  DisablePState:1;                      ///< Bit52, Disable P-states. When 1, the PAL
-                                                ///< P-state procedures (PAL_PSTATE_INFO,
-                                                ///< PAL_SET_PSTATE, PAL_GET_PSTATE) will
-                                                ///< return with a status of -1
-                                                ///< (Unimplemented procedure).
-
-  UINT64  EnableMcaOnDataPoisoning:1;           ///< Bit53, Enable MCA signaling
-                                                ///< on data-poisoning event
-                                                ///< detection. When 0, a CMCI
-                                                ///< will be signaled on error
-                                                ///< detection. When 1, an MCA
-                                                ///< will be signaled on error
-                                                ///< detection. If this feature
-                                                ///< is not supported, then the
-                                                ///< corresponding argument is
-                                                ///< ignored when calling
-                                                ///< PAL_PROC_SET_FEATURES. Note
-                                                ///< that the functionality of
-                                                ///< this bit is independent of
-                                                ///< the setting in bit 60
-                                                ///< (Enable CMCI promotion), and
-                                                ///< that the bit 60 setting does
-                                                ///< not affect CMCI signaling
-                                                ///< for data-poisoning related
-                                                ///< events. Volume 2: Processor
-                                                ///< Abstraction Layer 2:431
-                                                ///< PAL_PROC_GET_FEATURES
-
-  UINT64  EnableVmsw:1;                         ///< Bit54, Enable the use of the vmsw
-                                                ///<   instruction. When 0, the vmsw instruction
-                                                ///<   causes a Virtualization fault when
-                                                ///<   executed at the most privileged level.
-                                                ///<   When 1, this bit will enable normal
-                                                ///<   operation of the vmsw instruction.
-
-  UINT64  EnableEnvNotification:1;              ///< Bit55, Enable external
-                                                ///< notification when the processor
-                                                ///< detects hardware errors caused
-                                                ///< by environmental factors that
-                                                ///< could cause loss of
-                                                ///< deterministic behavior of the
-                                                ///< processor. When 1, this bit will
-                                                ///< enable external notification,
-                                                ///< when 0 external notification is
-                                                ///< not provided. The type of
-                                                ///< external notification of these
-                                                ///< errors is processor-dependent. A
-                                                ///< loss of processor deterministic
-                                                ///< behavior is considered to have
-                                                ///< occurred if these
-                                                ///< environmentally induced errors
-                                                ///< cause the processor to deviate
-                                                ///< from its normal execution and
-                                                ///< eventually causes different
-                                                ///< behavior which can be observed
-                                                ///<  at the processor bus pins.
-                                                ///< Processor errors that do not
-                                                ///< have this effects (i.e.,
-                                                ///< software induced machine checks)
-                                                ///< may or may not be promoted
-                                                ///< depending on the processor
-                                                ///< implementation.
-
-  UINT64  DisableBinitWithTimeout:1;            ///< Bit56, Disable a BINIT on
-                                                ///<   internal processor time-out.
-                                                ///<   When 0, the processor may
-                                                ///<   generate a BINIT on an
-                                                ///<   internal processor time-out.
-                                                ///<   When 1, the processor will not
-                                                ///<   generate a BINIT on an
-                                                ///<   internal processor time-out.
-                                                ///<   The event is silently ignored.
-
-  UINT64  DisableDPM:1;                         ///< Bit57, Disable Dynamic Power Management
-                                                ///<   (DPM). When 0, the hardware may reduce
-                                                ///<   power consumption by removing the clock
-                                                ///<   input from idle functional units. When 1,
-                                                ///<   all functional units will receive clock
-                                                ///<   input, even when idle.
-
-  UINT64  DisableCoherency:1;                   ///< Bit58, Disable Coherency. When 0,
-                                                ///< the processor uses normal coherency
-                                                ///< requests and responses. When 1, the
-                                                ///< processor answers all requests as if
-                                                ///< the line were not present.
-
-  UINT64  DisableCache:1;                       ///< Bit59, Disable Cache. When 0, the
-                                                ///< processor performs cast outs on
-                                                ///< cacheable pages and issues and responds
-                                                ///< to coherency requests normally. When 1,
-                                                ///< the processor performs a memory access
-                                                ///< for each reference regardless of cache
-                                                ///< contents and issues no coherence
-                                                ///< requests and responds as if the line
-                                                ///< were not present. Cache contents cannot
-                                                ///< be relied upon when the cache is
-                                                ///< disabled. WARNING: Semaphore
-                                                ///< instructions may not be atomic or may
-                                                ///< cause Unsupported Data Reference faults
-                                                ///< if caches are disabled.
-
-  UINT64  EnableCmciPromotion:1;                ///< Bit60, Enable CMCI promotion When
-                                                ///<   1, Corrected Machine Check
-                                                ///<   Interrupts (CMCI) are promoted to
-                                                ///<   MCAs. They are also further
-                                                ///<   promoted to BERR if bit 39, Enable
-                                                ///<   MCA promotion, is also set and
-                                                ///<   they are promoted to BINIT if bit
-                                                ///<   38, Enable MCA to BINIT promotion,
-                                                ///<   is also set. This bit has no
-                                                ///<   effect if MCA signalling is
-                                                ///<   disabled (see
-                                                ///<   PAL_BUS_GET/SET_FEATURES)
-
-  UINT64  EnableMcaToBinitPromotion:1;          ///< Bit61, Enable MCA to BINIT
-                                                ///< promotion. When 1, machine
-                                                ///< check aborts (MCAs) are
-                                                ///< promoted to the Bus
-                                                ///< Initialization signal, and
-                                                ///< the BINIT pin is assert on
-                                                ///< each occurrence of an MCA.
-                                                ///< Setting this bit has no
-                                                ///< effect if BINIT signalling
-                                                ///< is disabled. (See
-                                                ///< PAL_BUS_GET/SET_FEATURES)
-
-  UINT64  EnableMcaPromotion:1;                 ///< Bit62, Enable MCA promotion. When
-                                                ///<   1, machine check aborts (MCAs) are
-                                                ///<   promoted to the Bus Error signal,
-                                                ///<   and the BERR pin is assert on each
-                                                ///<   occurrence of an MCA. Setting this
-                                                ///<   bit has no effect if BERR
-                                                ///<   signalling is disabled. (See
-                                                ///<   PAL_BUS_GET/SET_FEATURES)
-                                                
-  UINT64  EnableBerrPromotion:1;                ///< Bit63. Enable BERR promotion. When
-                                                ///<   1, the Bus Error (BERR) signal is
-                                                ///<   promoted to the Bus Initialization
-                                                ///<   (BINIT) signal, and the BINIT pin
-                                                ///<   is asserted on the occurrence of
-                                                ///<   each Bus Error. Setting this bit
-                                                ///<   has no effect if BINIT signalling
-                                                ///<   is disabled. (See
-                                                ///<   PAL_BUS_GET/SET_FEATURES)
-} PAL_PROCESSOR_FEATURES;
-
-/**
-  PAL Procedure - PAL_PROC_GET_FEATURES.
-
-  Return configurable processor features and their current
-  setting. It is required by Itanium processors. The PAL procedure supports the
-  Static Registers calling convention. It could be called at
-  physical mode and virtual mode.
-
-  @param Index      Index of PAL_PROC_GET_FEATURES within the list of
-                    PAL procedures.
-  @param Reserved   Reserved parameter.
-  @param FeatureSet Feature set information is being requested
-                    for.
-
-  @retval 1         Call completed without error; The
-                    feature_set passed is not supported but a
-                    feature_set of a larger value is supported.
-  @retval 0         Call completed without error
-  @retval -2        Invalid argument
-  @retval -3        Call completed with error.
-  @retval -8        feature_set passed is beyond the maximum
-                    feature_set supported
-
-  @return R9        64-bit vector of features implemented. See
-                    PAL_PROCESSOR_FEATURES.
-  @return R10       64-bit vector of current feature settings. See
-                    PAL_PROCESSOR_FEATURES.
-  @return R11       64-bit vector of features controllable by
-                    software.
-
-**/
-#define PAL_PROC_GET_FEATURES 17
-
-
-/**
-  PAL Procedure - PAL_PROC_SET_FEATURES.
-
-  Enable or disable configurable processor features. It is
-  required by Itanium processors. The PAL procedure supports the Static
-  Registers calling convention. It could be called at physical
-  mode.
-
-  @param Index          Index of PAL_PROC_SET_FEATURES within the list of
-                        PAL procedures.
-  @param FeatureSelect  64-bit vector denoting desired state of
-                        each feature (1=select, 0=non-select).
-  @param FeatureSet     Feature set to apply changes to. See
-                        PAL_PROC_GET_FEATURES for more information
-                        on feature sets.
-
-  @retval 1             Call completed without error; The
-                        feature_set passed is not supported but a
-                        feature_set of a larger value is supported
-  @retval 0             Call completed without error
-  @retval -2            Invalid argument
-  @retval -3            Call completed with error.
-  @retval -8            feature_set passed is beyond the maximum
-                        feature_set supported
-
-**/
-#define PAL_PROC_SET_FEATURES 18
-
-
-//
-// Value of PAL_REGISTER_INFO.InfoRequest.
-//
-#define PAL_APPLICATION_REGISTER_IMPLEMENTED  0
-#define PAL_APPLICATION_REGISTER_READABLE     1
-#define PAL_CONTROL_REGISTER_IMPLEMENTED      2
-#define PAL_CONTROL_REGISTER_READABLE         3
-
-
-/**
-  PAL Procedure - PAL_REGISTER_INFO.
-
-  Return AR and CR register information. It is required by Itanium processors.
-  The PAL procedure supports the Static Registers calling
-  convention. It could be called at physical mode and virtual
-  mode.
-
-  @param Index        Index of PAL_REGISTER_INFO within the list of
-                      PAL procedures.
-  @param InfoRequest  Unsigned 64-bit integer denoting what
-                      register information is requested. See
-                      PAL_REGISTER_INFO.InfoRequest above.
-
-  @retval 0           Call completed without error
-  @retval -2          Invalid argument
-  @retval -3          Call completed with error.
-
-  @return R9          64-bit vector denoting information for registers
-                      0-63. Bit 0 is register 0, bit 63 is register 63.
-  @return R10         64-bit vector denoting information for registers
-                      64-127. Bit 0 is register 64, bit 63 is register
-                      127.
-
-**/
-#define PAL_REGISTER_INFO 39
-
-/**
-  PAL Procedure - PAL_RSE_INFO.
-
-  Return RSE information. It is required by Itanium processors. The PAL
-  procedure supports the Static Registers calling convention. It
-  could be called at physical mode and virtual mode.
-
-  @param Index        Index of PAL_RSE_INFO within the list of
-                      PAL procedures.
-  @param InfoRequest  Unsigned 64-bit integer denoting what
-                      register information is requested. See
-                      PAL_REGISTER_INFO.InfoRequest above.
-
-  @retval 0           Call completed without error
-  @retval -2          Invalid argument
-  @retval -3          Call completed with error.
-
-  @return R9          Number of physical stacked general registers.
-  @return R10         RSE hints supported by processor.
-
-**/
-#define PAL_RSE_INFO 19
-
-typedef struct {
-  UINT64  VersionOfPalB:16;     ///< Is a 16-bit binary coded decimal (BCD)
-                                ///< number that provides identification
-                                ///< information about the PAL_B firmware.
-  UINT64  Reserved1:8;
-  UINT64  PalVendor:8;          ///< Is an unsigned 8-bit integer indicating the
-                                ///< vendor of the PAL code.
-  UINT64  VersionOfPalA:16;     ///< Is a 16-bit binary coded decimal (BCD)
-                                ///< number that provides identification
-                                ///< information about the PAL_A firmware. In
-                                ///< the split PAL_A model, this return value
-                                ///< is the version number of the
-                                ///< processor-specific PAL_A. The generic
-                                ///< PAL_A version is not returned by this
-                                ///< procedure in the split PAL_A model.
-  UINT64  Reserved2:16;
-} PAL_VERSION_INFO;
-
-/**
-  PAL Procedure - PAL_VERSION.
-
-  Return version of PAL code. It is required by Itanium processors. The PAL
-  procedure supports the Static Registers calling convention. It
-  could be called at physical mode and virtual mode.
-
-  @param Index        Index of PAL_VERSION within the list of
-                      PAL procedures.
-  @param InfoRequest  Unsigned 64-bit integer denoting what
-                      register information is requested. See
-                      PAL_REGISTER_INFO.InfoRequest above.
-
-  @retval 0           Call completed without error
-  @retval -2          Invalid argument
-  @retval -3          Call completed with error.
-
-  @return R9          8-byte formatted value returning the minimum PAL
-                      version needed for proper operation of the
-                      processor. See PAL_VERSION_INFO above.
-  @return R10         8-byte formatted value returning the current PAL
-                      version running on the processor. See
-                      PAL_VERSION_INFO above.
-
-**/
-#define PAL_VERSION 20
-
-
-
-//
-// Vectors of PAL_MC_CLEAR_LOG.pending
-//
-#define PAL_MC_PENDING    BIT0
-#define PAL_INIT_PENDING  BIT1
-
-/**
-  PAL Procedure - PAL_MC_CLEAR_LOG.
-
-  Clear all error information from processor error logging
-  registers. It is required by Itanium processors. The PAL procedure supports
-  the Static Registers calling convention. It could be called at
-  physical mode and virtual mode.
-
-  @param Index  Index of PAL_MC_CLEAR_LOG within the list of
-                PAL procedures.
-
-  @retval 0     Call completed without error
-  @retval -2    Invalid argument
-  @retval -3    Call completed with error.
-
-  @return R9    64-bit vector denoting whether an event is
-                pending. See PAL_MC_CLEAR_LOG.pending above.
-
-**/
-#define PAL_MC_CLEAR_LOG 21
-
-/**
-  PAL Procedure - PAL_MC_DRAIN.
-
-  Ensure that all operations that could cause an MCA have
-  completed. It is required by Itanium processors. The PAL procedure supports
-  the Static Registers calling convention. It could be called at
-  physical mode and virtual mode.
-
-  @param Index  Index of PAL_MC_DRAIN within the list of PAL
-                procedures.
-
-  @retval 0     Call completed without error
-  @retval -2    Invalid argument
-  @retval -3    Call completed with error.
-
-**/
-#define PAL_MC_DRAIN 22
-
-
-/**
-  PAL Procedure - PAL_MC_DYNAMIC_STATE.
-
-  Return Processor Dynamic State for logging by SAL. It is
-  optional. The PAL procedure supports the Static Registers
-  calling convention. It could be called at physical mode.
-
-  @param Index  Index of PAL_MC_DYNAMIC_STATE within the list of PAL
-                procedures.
-  @param Offset Offset of the next 8 bytes of Dynamic Processor
-                State to return. (multiple of 8).
-
-  @retval 0     Call completed without error
-  @retval -1    Unimplemented procedure.
-  @retval -2    Invalid argument
-  @retval -3    Call completed with error.
-
-  @return R9    Unsigned 64-bit integer denoting bytes of Dynamic
-                Processor State returned.
-  @return R10   Next 8 bytes of Dynamic Processor State.
-
-**/
-#define PAL_MC_DYNAMIC_STATE 24
-
-
-
-//
-// Values of PAL_MC_ERROR_INFO.InfoIndex.
-//
-#define PAL_PROCESSOR_ERROR_MAP       0
-#define PAL_PROCESSOR_STATE_PARAM     1
-#define PAL_STRUCTURE_SPECIFIC_ERROR  2
-
-typedef struct {
- UINT64 CoreId:4;                   ///< Bit3:0,  Processor core ID (default is 0 for
-                                    ///< processors with a single core)
-
- UINT64 ThreadId:4;                 ///< Bit7:4, Logical thread ID (default is 0 for
-                                    ///< processors that execute a single thread)
-
- UINT64 InfoOfInsCache:4;           ///< Bit11:8, Error information is
-                                    ///< available for 1st, 2nd, 3rd, and 4th
-                                    ///< level instruction caches.
-
- UINT64 InfoOfDataCache:4;          ///< Bit15:12, Error information is
-                                    ///<   available for 1st, 2nd, 3rd, and 4th
-                                    ///<   level data/unified caches.
-
- UINT64 InfoOfInsTlb:4;             ///< Bit19:16 Error information is available
-                                    ///< for 1st, 2nd, 3rd, and 4th level
-                                    ///< instruction TLB.
-
- UINT64 InfoOfDataTlb:4;            ///< Bit23:20, Error information is available
-                                    ///< for 1st, 2nd, 3rd, and 4th level
-                                    ///< data/unified TLB
-
- UINT64 InfoOfProcessorBus:4;       ///< Bit27:24 Error information is
-                                    ///<   available for the 1st, 2nd, 3rd,
-                                    ///<   and 4th level processor bus
-                                    ///<   hierarchy.
- UINT64 InfoOfRegisterFile:4;       ///< Bit31:28 Error information is
-                                    ///<   available on register file
-                                    ///<   structures.
- UINT64 InfoOfMicroArch:4;          ///< Bit47:32, Error information is
-                                    ///<   available on micro-architectural
-                                    ///<   structures.
- UINT64 Reserved:16;
-} PAL_MC_ERROR_INFO_LEVEL_INDEX;
-
-//
-// Value of PAL_MC_ERROR_INFO.ErrorTypeIndex
-//
-#define PAL_ERR_INFO_BY_LEVEL_INDEX               0
-#define PAL_ERR_INFO_TARGET_ADDRESS               1
-#define PAL_ERR_INFO_REQUESTER_IDENTIFIER         2
-#define PAL_ERR_INFO_REPONSER_INDENTIFIER         3
-#define PAL_ERR_INFO_PRECISE_INSTRUCTION_POINTER  4
-
-typedef struct {
-  UINT64  Operation:4;                  ///< Bit3:0, Type of cache operation that caused
-                                        ///< the machine check: 0 - unknown or internal
-                                        ///< error 1 - load 2 - store 3 - instruction
-                                        ///< fetch or instruction prefetch 4 - data
-                                        ///< prefetch (both hardware and software) 5 -
-                                        ///< snoop (coherency check) 6 - cast out
-                                        ///< (explicit or implicit write-back of a cache
-                                        ///< line) 7 - move in (cache line fill)
-
-  UINT64  FailedCacheLevel:2;           ///< Bit5:4 Level of cache where the
-                                        ///< error occurred. A value of 0
-                                        ///< indicates the first level of cache.
-  UINT64  Reserved1:2;
-  UINT64  FailedInDataPart:1;           ///< Bit8, Failure located in the data part of the cache line.
-  UINT64  FailedInTagPart:1;            ///< Bit9, Failure located in the tag part of the cache line.
-  UINT64  FailedInDataCache:1;          ///< Bit10, Failure located in the data cache
-
-  UINT64  FailedInInsCache:1;           ///< Bit11, Failure located in the
-                                        ///< instruction cache.
-                                        
-  UINT64  Mesi:3;                       ///< Bit14:12,  0 - cache line is invalid. 1 - cache
-                                        ///< line is held shared. 2 - cache line is held
-                                        ///< exclusive. 3 - cache line is modified. All other
-                                        ///< values are reserved.
-                                        
-  UINT64  MesiIsValid:1;                ///< Bit15, The mesi field in the cache_check
-                                        ///< parameter is valid.
-                                        
-  UINT64  FailedWay:5;                  ///< Bit20:16, Failure located in the way of
-                                        ///< the cache indicated by this value.
-
-  UINT64  WayIndexIsValid:1;            ///< Bit21, The way and index field in the
-                                        ///< cache_check parameter is valid.
-
-  UINT64  Reserved2:1;
-  UINT64  MultipleBitsError:1;          ///< Bit23, A multiple-bit error was
-                                        ///< detected, and data was poisoned for
-                                        ///< the corresponding cache line during
-                                        ///< castout.
-  UINT64  Reserved3:8;
-  UINT64  IndexOfCacheLineError:20;     ///< Bit51:32, Index of the cache
-                                        ///< line where the error occurred.
-  UINT64  Reserved4:2;
-
-  UINT64  InstructionSet:1;             ///< Bit54, Instruction set. If this value
-                                        ///<   is set to zero, the instruction that
-                                        ///<   generated the machine check was an
-                                        ///<   Intel Itanium instruction. If this bit
-                                        ///<   is set to one, the instruction that
-                                        ///<   generated the machine check was IA-32
-                                        ///<   instruction.
-
-  UINT64  InstructionSetIsValid:1;      ///< Bit55, The is field in the
-                                        ///< cache_check parameter is valid.
-
-  UINT64  PrivilegeLevel:2;             ///< Bit57:56, Privilege level. The
-                                        ///<   privilege level of the instruction
-                                        ///<   bundle responsible for generating the
-                                        ///<   machine check.
-
-  UINT64  PrivilegeLevelIsValide:1;     ///< Bit58, The pl field of the
-                                        ///<   cache_check parameter is
-                                        ///<   valid.
-
-  UINT64  McCorrected:1;                ///< Bit59, Machine check corrected: This bit
-                                        ///<   is set to one to indicate that the machine
-                                        ///<   check has been corrected.
-
-  UINT64  TargetAddressIsValid:1;       ///< Bit60, Target address is valid:
-                                        ///< This bit is set to one to
-                                        ///< indicate that a valid target
-                                        ///< address has been logged.
-
-  UINT64  RequesterIdentifier:1;        ///< Bit61, Requester identifier: This
-                                        ///<   bit is set to one to indicate that
-                                        ///<   a valid requester identifier has
-                                        ///<   been logged.
-
-  UINT64  ResponserIdentifier:1;        ///< Bit62, Responder identifier: This
-                                        ///<   bit is set to one to indicate that
-                                        ///<   a valid responder identifier has
-                                        ///<   been logged.
-
-  UINT64  PreciseInsPointer:1;          ///< Bit63,  Precise instruction pointer.
-                                        ///< This bit is set to one to indicate
-                                        ///< that a valid precise instruction
-                                        ///< pointer has been logged.
-
-} PAL_CACHE_CHECK_INFO;
-
-
-typedef struct {
-  UINT64  FailedSlot:8;                 ///< Bit7:0, Slot number of the translation
-                                        ///< register where the failure occurred.
-  UINT64  FailedSlotIsValid:1;          ///< Bit8, The tr_slot field in the
-                                        ///< TLB_check parameter is valid.
-  UINT64  Reserved1 :1;
-  UINT64  TlbLevel:2;                   ///< Bit11:10,  The level of the TLB where the
-                                        ///< error occurred. A value of 0 indicates the
-                                        ///< first level of TLB
-  UINT64  Reserved2 :4;
-
-  UINT64  FailedInDataTr:1;             ///< Bit16, Error occurred in the data
-                                        ///< translation registers.
-
-  UINT64  FailedInInsTr:1;              ///< Bit17, Error occurred in the instruction
-                                        ///< translation registers
-
-  UINT64  FailedInDataTc:1;             ///< Bit18, Error occurred in data
-                                        ///< translation cache.
-
-  UINT64  FailedInInsTc:1;              ///< Bit19, Error occurred in the instruction
-                                        ///< translation cache.
-
-  UINT64  FailedOperation:4;            ///< Bit23:20, Type of cache operation that
-                                        ///<   caused the machine check: 0 - unknown
-                                        ///<   1 - TLB access due to load instruction
-                                        ///<   2 - TLB access due to store
-                                        ///<   instruction 3 - TLB access due to
-                                        ///<   instruction fetch or instruction
-                                        ///<   prefetch 4 - TLB access due to data
-                                        ///<   prefetch (both hardware and software)
-                                        ///<   5 - TLB shoot down access 6 - TLB
-                                        ///<   probe instruction (probe, tpa) 7 -
-                                        ///<   move in (VHPT fill) 8 - purge (insert
-                                        ///<   operation that purges entries or a TLB
-                                        ///<   purge instruction) All other values
-                                        ///<   are reserved.
-
-  UINT64  Reserved3:30;
-  UINT64  InstructionSet:1;             ///< Bit54, Instruction set. If this value
-                                        ///<   is set to zero, the instruction that
-                                        ///<   generated the machine check was an
-                                        ///<   Intel Itanium instruction. If this bit
-                                        ///<   is set to one, the instruction that
-                                        ///<   generated the machine check was IA-32
-                                        ///<   instruction.
-
-  UINT64  InstructionSetIsValid:1;      ///< Bit55, The is field in the
-                                        ///< TLB_check parameter is valid.
-
-  UINT64  PrivelegeLevel:2;             ///< Bit57:56, Privilege level. The
-                                        ///<   privilege level of the instruction
-                                        ///<   bundle responsible for generating the
-                                        ///<   machine check.
-
-  UINT64  PrivelegeLevelIsValid:1;      ///< Bit58,  The pl field of the
-                                        ///< TLB_check parameter is valid.
-
-  UINT64  McCorrected:1;                ///< Bit59, Machine check corrected: This bit
-                                        ///<   is set to one to indicate that the machine
-                                        ///<   check has been corrected.
-
-  UINT64  TargetAddressIsValid:1;       ///< Bit60, Target address is valid:
-                                        ///< This bit is set to one to
-                                        ///< indicate that a valid target
-                                        ///< address has been logged.
-
-  UINT64  RequesterIdentifier:1;        ///< Bit61 Requester identifier: This
-                                        ///<   bit is set to one to indicate that
-                                        ///<   a valid requester identifier has
-                                        ///<   been logged.
-
-  UINT64  ResponserIdentifier:1;        ///< Bit62, Responder identifier:  This
-                                        ///<   bit is set to one to indicate that
-                                        ///<   a valid responder identifier has
-                                        ///<   been logged.
-
-  UINT64  PreciseInsPointer:1;          ///< Bit63 Precise instruction pointer.
-                                        ///<   This bit is set to one to indicate
-                                        ///<   that a valid precise instruction
-                                        ///<   pointer has been logged.
-} PAL_TLB_CHECK_INFO;
-
-/**
-  PAL Procedure - PAL_MC_ERROR_INFO.
-
-  Return Processor Machine Check Information and Processor
-  Static State for logging by SAL. It is required by Itanium processors. The
-  PAL procedure supports the Static Registers calling
-  convention. It could be called at physical and virtual mode.
-
-  @param Index            Index of PAL_MC_ERROR_INFO within the list of PAL
-                          procedures.
-  @param InfoIndex        Unsigned 64-bit integer identifying the
-                          error information that is being requested.
-                          See PAL_MC_ERROR_INFO.InfoIndex.
-  @param LevelIndex       8-byte formatted value identifying the
-                          structure to return error information
-                          on. See PAL_MC_ERROR_INFO_LEVEL_INDEX.
-  @param ErrorTypeIndex   Unsigned 64-bit integer denoting the
-                          type of error information that is
-                          being requested for the structure
-                          identified in LevelIndex.
-
-  @retval 0               Call completed without error
-  @retval -2              Invalid argument
-  @retval -3              Call completed with error.
-  @retval -6              Argument was valid, but no error
-                          information was available
-
-  @return R9              Error information returned. The format of this
-                          value is dependant on the input values passed.
-  @return R10             If this value is zero, all the error information
-                          specified by err_type_index has been returned. If
-                          this value is one, more structure-specific error
-                          information is available and the caller needs to
-                          make this procedure call again with level_index
-                          unchanged and err_type_index, incremented.
-
-**/
-#define PAL_MC_ERROR_INFO 25
-
-/**
-  PAL Procedure - PAL_MC_EXPECTED.
-
-  Set/Reset Expected Machine Check Indicator. It is required by
-  Itanium processors. The PAL procedure supports the Static Registers calling
-  convention. It could be called at physical mode.
-
-  @param Index      Index of PAL_MC_EXPECTED within the list of PAL
-                    procedures.
-  @param Expected   Unsigned integer with a value of 0 or 1 to
-                    set or reset the hardware resource
-                    PALE_CHECK examines for expected machine
-                    checks.
-
-  @retval 0         Call completed without error
-  @retval -2        Invalid argument
-  @retval -3        Call completed with error.
-
-  @return R9        Unsigned integer denoting whether a machine check
-                    was previously expected.
-
-**/
-#define PAL_MC_EXPECTED 23
-
-/**
-  PAL Procedure - PAL_MC_REGISTER_MEM.
-
-  Register min-state save area with PAL for machine checks and
-  inits. It is required by Itanium processors. The PAL procedure supports the
-  Static Registers calling convention. It could be called at
-  physical mode.
-
-  @param Index    Index of PAL_MC_REGISTER_MEM within the list of PAL
-                  procedures.
-  @param Address  Physical address of the buffer to be
-                  registered with PAL.
-
-  @retval 0       Call completed without error
-  @retval -2      Invalid argument
-  @retval -3      Call completed with error.
-
-**/
-#define PAL_MC_REGISTER_MEM 27
-
-/**
-  PAL Procedure - PAL_MC_RESUME.
-
-  Restore minimal architected state and return to interrupted
-  process. It is required by Itanium processors. The PAL procedure supports the
-  Static Registers calling convention. It could be called at
-  physical mode.
-
-  @param Index        Index of PAL_MC_RESUME within the list of PAL
-                      procedures.
-  @param SetCmci      Unsigned 64 bit integer denoting whether to
-                      set the CMC interrupt. A value of 0 indicates
-                      not to set the interrupt, a value of 1
-                      indicated to set the interrupt, and all other
-                      values are reserved.
-  @param SavePtr      Physical address of min-state save area used
-                      to used to restore processor state.
-  @param NewContext   Unsigned 64-bit integer denoting whether
-                      the caller is returning to a new context.
-                      A value of 0 indicates the caller is
-                      returning to the interrupted context, a
-                      value of 1 indicates that the caller is
-                      returning to a new context.
-
-  @retval -2          Invalid argument
-  @retval -3          Call completed with error.
-
-**/
-#define PAL_MC_RESUME 26
-
-/**
-  PAL Procedure - PAL_HALT.
-
-  Enter the low-power HALT state or an implementation-dependent
-  low-power state. It is optinal. The PAL procedure supports the
-  Static Registers calling convention. It could be called at
-  physical mode.
-
-  @param Index        Index of PAL_HALT within the list of PAL
-                      procedures.
-  @param HaltState    Unsigned 64-bit integer denoting low power
-                      state requested.
-  @param IoDetailPtr  8-byte aligned physical address pointer to
-                      information on the type of I/O
-                      (load/store) requested.
-
-  @retval 0           Call completed without error
-  @retval -1          Unimplemented procedure
-  @retval -2          Invalid argument
-  @retval -3          Call completed with error.
-
-  @return R9          Value returned if a load instruction is requested
-                      in the io_detail_ptr
-
-**/
-#define PAL_HALT 28
-
-
-/**
-  PAL Procedure - PAL_HALT_INFO.
-
-  Return the low power capabilities of the processor. It is
-  required by Itanium processors. The PAL procedure supports the
-  Stacked Registers calling convention. It could be called at
-  physical and virtual mode.
-
-  @param Index        Index of PAL_HALT_INFO within the list of PAL
-                      procedures.
-  @param PowerBuffer  64-bit pointer to a 64-byte buffer aligned
-                      on an 8-byte boundary.
-
-  @retval 0           Call completed without error
-  @retval -2          Invalid argument
-  @retval -3          Call completed with error.
-
-**/
-#define PAL_HALT_INFO 257
-
-
-/**
-  PAL Procedure - PAL_HALT_LIGHT.
-
-  Enter the low power LIGHT HALT state. It is required by
-  Itanium processors. The PAL procedure supports the Static Registers calling
-  convention. It could be called at physical and virtual mode.
-
-  @param Index  Index of PAL_HALT_LIGHT within the list of PAL
-                procedures.
-
-  @retval 0     Call completed without error
-  @retval -2    Invalid argument
-  @retval -3    Call completed with error.
-
-**/
-#define PAL_HALT_LIGHT 29
-
-/**
-  PAL Procedure - PAL_CACHE_LINE_INIT.
-
-  Initialize tags and data of a cache line for processor
-  testing. It is required by Itanium processors. The PAL procedure supports the
-  Static Registers calling convention. It could be called at
-  physical and virtual mode.
-
-  @param Index      Index of PAL_CACHE_LINE_INIT within the list of PAL
-                    procedures.
-  @param Address    Unsigned 64-bit integer value denoting the
-                    physical address from which the physical page
-                    number is to be generated. The address must be
-                    an implemented physical address, bit 63 must
-                    be zero.
-  @param DataValue  64-bit data value which is used to
-                    initialize the cache line.
-
-  @retval 0         Call completed without error
-  @retval -2        Invalid argument
-  @retval -3        Call completed with error.
-
-**/
-#define PAL_CACHE_LINE_INIT 31
-
-/**
-  PAL Procedure - PAL_CACHE_READ.
-
-  Read tag and data of a cache line for diagnostic testing. It
-  is optional. The PAL procedure supports the
-  Satcked Registers calling convention. It could be called at
-  physical mode.
-
-  @param Index    Index of PAL_CACHE_READ within the list of PAL
-                  procedures.
-  @param LineId   8-byte formatted value describing where in the
-                  cache to read the data.
-  @param Address  64-bit 8-byte aligned physical address from
-                  which to read the data. The address must be an
-                  implemented physical address on the processor
-                  model with bit 63 set to zero.
-
-  @retval 1       The word at address was found in the
-                  cache, but the line was invalid.
-  @retval 0       Call completed without error
-  @retval -2      Invalid argument
-  @retval -3      Call completed with error.
-  @retval -5      The word at address was not found in the
-                  cache.
-  @retval -7      The operation requested is not supported
-                  for this cache_type and level.
-
-  @return R9      Right-justified value returned from the cache
-                  line.
-  @return R10     The number of bits returned in data.
-  @return R11     The status of the cache line.
-
-**/
-#define PAL_CACHE_READ 259
-
-
-/**
-  PAL Procedure - PAL_CACHE_WRITE.
-
-  Write tag and data of a cache for diagnostic testing. It is
-  optional. The PAL procedure supports the Satcked Registers
-  calling convention. It could be called at physical mode.
-
-  @param Index    Index of PAL_CACHE_WRITE within the list of PAL
-                  procedures.
-  @param LineId   8-byte formatted value describing where in the
-                  cache to write the data.
-  @param Address  64-bit 8-byte aligned physical address at
-                  which the data should be written. The address
-                  must be an implemented physical address on the
-                  processor model with bit 63 set to 0.
-  @param Data     Unsigned 64-bit integer value to write into
-                  the specified part of the cache.
-
-  @retval 0       Call completed without error
-  @retval -2      Invalid argument
-  @retval -3      Call completed with error.
-  @retval -7      The operation requested is not supported
-                  for this cache_type and level.
-
-**/
-#define PAL_CACHE_WRITE 260
-
-/**
-  PAL Procedure - PAL_TEST_INFO.
-
-  Returns alignment and size requirements needed for the memory
-  buffer passed to the PAL_TEST_PROC procedure as well as
-  information on self-test control words for the processor self
-  tests. It is required by Itanium processors. The PAL procedure supports the
-  Static Registers calling convention. It could be called at
-  physical mode.
-
-  @param Index      Index of PAL_TEST_INFO within the list of PAL
-                    procedures.
-  @param TestPhase  Unsigned integer that specifies which phase
-                    of the processor self-test information is
-                    being requested on. A value of 0 indicates
-                    the phase two of the processor self-test and
-                    a value of 1 indicates phase one of the
-                    processor self-test. All other values are
-                    reserved.
-
-  @retval 0         Call completed without error
-  @retval -2        Invalid argument
-  @retval -3        Call completed with error.
-
-  @return R9        Unsigned 64-bit integer denoting the number of
-                    bytes of main memory needed to perform the second
-                    phase of processor self-test.
-  @return R10       Unsigned 64-bit integer denoting the alignment
-                    required for the memory buffer.
-  @return R11       48-bit wide bit-field indicating if control of
-                    the processor self-tests is supported and which
-                    bits of the test_control field are defined for
-                    use.
-
-**/
-#define PAL_TEST_INFO 37
-
-typedef struct {
-  UINT64  BufferSize:56;    ///< Indicates the size in bytes of the memory
-                            ///< buffer that is passed to this procedure.
-                            ///< BufferSize must be greater than or equal in
-                            ///< size to the bytes_needed return value from
-                            ///< PAL_TEST_INFO, otherwise this procedure will
-                            ///< return with an invalid argument return
-                            ///< value.
-
-  UINT64  TestPhase:8;      ///< Defines which phase of the processor
-                            ///< self-tests are requested to be run. A value
-                            ///< of zero indicates to run phase two of the
-                            ///< processor self-tests. Phase two of the
-                            ///< processor self-tests are ones that require
-                            ///< external memory to execute correctly. A
-                            ///< value of one indicates to run phase one of
-                            ///< the processor self-tests. Phase one of the
-                            ///< processor self-tests are tests run during
-                            ///< PALE_RESET and do not depend on external
-                            ///< memory to run correctly. When the caller
-                            ///< requests to have phase one of the processor
-                            ///< self-test run via this procedure call, a
-                            ///< memory buffer may be needed to save and
-                            ///< restore state as required by the PAL calling
-                            ///< conventions. The procedure PAL_TEST_INFO
-                            ///< informs the caller about the requirements of
-                            ///< the memory buffer.
-} PAL_TEST_INFO_INFO;
-
-typedef struct {
-  UINT64  TestControl:47;       ///< This is an ordered implementation-specific
-                                ///<   control word that allows the user control
-                                ///<   over the length and runtime of the
-                                ///<   processor self-tests. This control word is
-                                ///<   ordered from the longest running tests up
-                                ///<   to the shortest running tests with bit 0
-                                ///<   controlling the longest running test. PAL
-                                ///<   may not implement all 47-bits of the
-                                ///<   test_control word. PAL communicates if a
-                                ///<   bit provides control by placing a zero in
-                                ///<   that bit. If a bit provides no control,
-                                ///<   PAL will place a one in it. PAL will have
-                                ///<   two sets of test_control bits for the two
-                                ///<   phases of the processor self-test. PAL
-                                ///<   provides information about implemented
-                                ///<   test_control bits at the hand-off from PAL
-                                ///<   to SAL for the firmware recovery check.
-                                ///<   These test_control bits provide control
-                                ///<   for phase one of processor self-test. It
-                                ///<   also provides this information via the PAL
-                                ///<   procedure call PAL_TEST_INFO for both the
-                                ///<   phase one and phase two processor tests
-                                ///<   depending on which information the caller
-                                ///<   is requesting. PAL interprets these bits
-                                ///<   as input parameters on two occasions. The
-                                ///<   first time is when SAL passes control back
-                                ///<   to PAL after the firmware recovery check.
-                                ///<   The second time is when a call to
-                                ///<   PAL_TEST_PROC is made. When PAL interprets
-                                ///<   these bits it will only interpret
-                                ///<   implemented test_control bits and will
-                                ///<   ignore the values located in the
-                                ///<   unimplemented test_control bits. PAL
-                                ///<   interprets the implemented bits such that
-                                ///<   if a bit contains a zero, this indicates
-                                ///<   to run the test. If a bit contains a one,
-                                ///<   this indicates to PAL to skip the test. If
-                                ///<   the cs bit indicates that control is not
-                                ///<    available, the test_control bits will be
-                                ///<   ignored or generate an illegal argument in
-                                ///<   procedure calls if the caller sets these
-                                ///<   bits.
-                                
-  UINT64  ControlSupport:1;     ///< This bit defines if an implementation
-                                ///<  supports control of the PAL self-tests
-                                ///<  via the self-test control word. If
-                                ///<  this bit is 0, the implementation does
-                                ///<  not support control of the processor
-                                ///<  self-tests via the self-test control
-                                ///<  word. If this bit is 1, the
-                                ///<  implementation does support control of
-                                ///<  the processor self-tests via the
-                                ///<  self-test control word. If control is
-                                ///<  not supported, GR37 will be ignored at
-                                ///<  the hand-off between SAL and PAL after
-                                ///<  the firmware recovery check and the
-                                ///<  PAL procedures related to the
-                                ///<  processor self-tests may return
-                                ///<  illegal arguments if a user tries to
-                                ///<  use the self-test control features.
-  UINT64  Reserved:16;
-} PAL_SELF_TEST_CONTROL;
-
-typedef struct {
-  UINT64  Attributes:8;         ///< Specifies the memory attributes that are
-                                ///<  allowed to be used with the memory buffer
-                                ///<  passed to this procedure. The attributes
-                                ///<  parameter is a vector where each bit
-                                ///<  represents one of the virtual memory
-                                ///<  attributes defined by the architecture.See
-                                ///<  MEMORY_AATRIBUTES. The caller is required
-                                ///<  to support the cacheable attribute for the
-                                ///<  memory buffer, otherwise an invalid
-                                ///<  argument will be returned.
-  UINT64  Reserved:8;
-  UINT64  TestControl:48;       ///< Is the self-test control word
-                                ///<  corresponding to the test_phase passed.
-                                ///<  This test_control directs the coverage and
-                                ///<  runtime of the processor self-tests
-                                ///<  specified by the test_phase input
-                                ///<  argument. Information on if this
-                                ///<  feature is implemented and the number of
-                                ///<  bits supported can be obtained by the
-                                ///<  PAL_TEST_INFO procedure call. If this
-                                ///<  feature is implemented by the processor,
-                                ///<  the caller can selectively skip parts of
-                                ///<  the processor self-test by setting
-                                ///<  test_control bits to a one. If a bit has a
-                                ///<  zero, this test will be run. The values in
-                                ///<  the unimplemented bits are ignored. If
-                                ///<  PAL_TEST_INFO indicated that the self-test
-                                ///<  control word is not implemented, this
-                                ///<  procedure will return with an invalid
-                                ///<  argument status if the caller sets any of
-                                ///<  the test_control bits. See
-                                ///<  PAL_SELF_TEST_CONTROL.
-} PAL_TEST_CONTROL;
-
-/**
-  PAL Procedure - PAL_TEST_PROC.
-
-  Perform late processor self test. It is required by Itanium processors. The
-  PAL procedure supports the Static Registers calling
-  convention. It could be called at physical mode.
-
-  @param Index        Index of PAL_TEST_PROC within the list of PAL
-                      procedures.
-  @param TestAddress  64-bit physical address of main memory
-                      area to be used by processor self-test.
-                      The memory region passed must be
-                      cacheable, bit 63 must be zero.
-  @param TestInfo     Input argument specifying the size of the
-                      memory buffer passed and the phase of the
-                      processor self-test that should be run. See
-                      PAL_TEST_INFO.
-  @param TestParam    Input argument specifying the self-test
-                      control word and the allowable memory
-                      attributes that can be used with the memory
-                      buffer. See PAL_TEST_CONTROL.
-
-  @retval 1           Call completed without error, but hardware
-                      failures occurred during self-test.
-  @retval 0           Call completed without error
-  @retval -2          Invalid argument
-  @retval -3          Call completed with error.
-
-  @return R9          Formatted 8-byte value denoting the state of the
-                      processor after self-test
-
-**/
-#define PAL_TEST_PROC 258
-
-typedef struct {
-  UINT32  NumberOfInterruptControllers;     ///< Number of interrupt
-                                            ///< controllers currently
-                                            ///< enabled on the system.
-
-  UINT32  NumberOfProcessors;               ///< Number of processors currently
-                                            ///< enabled on the system.
-} PAL_PLATFORM_INFO;
-
-/**
-  PAL Procedure - PAL_COPY_INFO.
-
-  Return information needed to relocate PAL procedures and PAL
-  PMI code to memory. It is required by Itanium processors. The PAL procedure
-  supports the Static Registers calling convention. It could be
-  called at physical mode.
-
-  @param Index              Index of PAL_COPY_INFO within the list of PAL
-                            procedures.
-  @param CopyType           Unsigned integer denoting type of procedures
-                            for which copy information is requested.
-  @param PlatformInfo       8-byte formatted value describing the
-                            number of processors and the number of
-                            interrupt controllers currently enabled
-                            on the system. See PAL_PLATFORM_INFO.
-  @param McaProcStateInfo   Unsigned integer denoting the number
-                            of bytes that SAL needs for the
-                            min-state save area for each
-                            processor.
-
-  @retval 0                 Call completed without error
-  @retval -2                Invalid argument
-  @retval -3                Call completed with error.
-
-  @return R9                Unsigned integer denoting the number of bytes of
-                            PAL information that must be copied to main
-                            memory.
-  @return R10               Unsigned integer denoting the starting alignment
-                            of the data to be copied.
-
-**/
-#define PAL_COPY_INFO 30
-
-/**
-  PAL Procedure - PAL_COPY_PAL.
-
-  Relocate PAL procedures and PAL PMI code to memory. It is
-  required by Itanium processors. The PAL procedure supports the Stacked
-  Registers calling convention. It could be called at physical
-  mode.
-
-  @param Index          Index of PAL_COPY_PAL within the list of PAL
-                        procedures.
-  @param TargetAddress  Physical address of a memory buffer to
-                        copy relocatable PAL procedures and PAL
-                        PMI code.
-  @param AllocSize      Unsigned integer denoting the size of the
-                        buffer passed by SAL for the copy operation.
-  @param CopyOption     Unsigned integer indicating whether
-                        relocatable PAL code and PAL PMI code
-                        should be copied from firmware address
-                        space to main memory.
-
-  @retval 0             Call completed without error
-  @retval -2            Invalid argument
-  @retval -3            Call completed with error.
-
-  @return R9            Unsigned integer denoting the offset of PAL_PROC
-                        in the relocatable segment copied.
-
-**/
-#define PAL_COPY_PAL 256
-
-/**
-  PAL Procedure - PAL_ENTER_IA_32_ENV.
-
-  Enter IA-32 System environment. It is optional. The PAL
-  procedure supports the Static Registers calling convention.
-  It could be called at physical mode.
-
-  Note: Since this is a special call, it does not follow the PAL
-  static register calling convention. GR28 contains the index of
-  PAL_ENTER_IA_32_ENV within the list of PAL procedures. All other
-  input arguments including GR29-GR31 are setup by SAL to values
-  as required by the IA-32 operating system defined in Table
-  11-67. The registers that are designated as preserved, scratch,
-  input arguments and procedure return values by the static
-  procedure calling convention are not followed by this call. For
-  instance, GR5 and GR6 need not be preserved since these are
-  regarded as scratch by the IA-32 operating system. Note: In an
-  MP system, this call must be COMPLETED on the first CPU to enter
-  the IA-32 System Environment (may or may not be the BSP) prior
-  to being called on the remaining processors in the MP system.
-
-  @param Index  GR28 contains the index of the
-                PAL_ENTER_IA_32_ENV call within the list of PAL
-                procedures.
-
-
-  @retval  The status is returned in GR4.
-                  -1 - Un-implemented procedure 0 JMPE detected
-                  at privilege level
-
-                  0 - 1 SAL allocated buffer for IA-32 System
-                  Environment operation is too small
-
-                  2 - IA-32 Firmware Checksum Error
-
-                  3 -  SAL allocated buffer for IA-32 System
-                  Environment operation is not properly aligned
-
-                  4 - Error in SAL MP Info Table
-
-                  5 - Error in SAL Memory Descriptor Table
-
-                  6 - Error in SAL System Table
-
-                  7 - Inconsistent IA-32 state
-
-                  8 - IA-32 Firmware Internal Error
-
-                  9 - IA-32 Soft Reset (Note: remaining register
-                  state is undefined for this termination
-                  reason)
-
-                  10 - Machine Check Error
-
-                  11 - Error in SAL I/O Intercept Table
-
-                  12 - Processor exit due to other processor in
-                  MP system terminating the IA32 system
-                  environment. (Note: remaining register state
-                  is undefined for this termination reason.)
-
-                  13 - Itanium architecture-based state
-                  corruption by either SAL PMI handler or I/O
-                  Intercept callback function.
-
-
-**/
-#define PAL_ENTER_IA_32_ENV 33
-
-/**
-  PAL Procedure - PAL_PMI_ENTRYPOINT.
-
-  Register PMI memory entrypoints with processor. It is required
-  by Itanium processors. The PAL procedure supports the Stacked Registers
-  calling convention. It could be called at physical mode.
-
-  @param Index        Index of PAL_PMI_ENTRYPOINT within the list of
-                      PAL procedures.
-  @param SalPmiEntry  256-byte aligned physical address of SAL
-                      PMI entrypoint in memory.
-
-  @retval 0           Call completed without error
-  @retval -2          Invalid argument
-  @retval -3          Call completed with error.
-
-**/
-#define PAL_PMI_ENTRYPOINT 32
-
-
-/**
-
-  The ASCII brand identification string will be copied to the
-  address specified in the address input argument. The processor
-  brand identification string is defined to be a maximum of 128
-  characters long; 127 bytes will contain characters and the 128th
-  byte is defined to be NULL (0). A processor may return less than
-  the 127 ASCII characters as long as the string is null
-  terminated. The string length will be placed in the brand_info
-  return argument.
-
-**/
-#define PAL_BRAND_INFO_ID_REQUEST  0
-
-/**
-  PAL Procedure - PAL_BRAND_INFO.
-
-  Provides processor branding information. It is optional by
-  Itanium processors. The PAL procedure supports the Stacked Registers calling
-  convention. It could be called at physical and Virtual mode.
-
-  @param Index        Index of PAL_BRAND_INFO within the list of PAL
-                      procedures.
-  @param InfoRequest  Unsigned 64-bit integer specifying the
-                      information that is being requested. (See
-                      PAL_BRAND_INFO_ID_REQUEST)
-  @param Address      Unsigned 64-bit integer specifying the
-                      address of the 128-byte block to which the
-                      processor brand string shall be written.
-
-  @retval 0           Call completed without error
-  @retval -1          Unimplemented procedure
-  @retval -2          Invalid argument
-  @retval -3          Call completed with error.
-  @retval -6          Input argument is not implemented.
-
-  @return R9          Brand information returned. The format of this
-                      value is dependent on the input values passed.
-
-**/
-#define PAL_BRAND_INFO  274
-
-/**
-  PAL Procedure - PAL_GET_HW_POLICY.
-
-  Returns the current hardware resource sharing policy of the
-  processor. It is optional by Itanium processors. The PAL procedure supports
-  the Static Registers calling convention. It could be called at
-  physical and Virtual mode.
-
-
-  @param Index            Index of PAL_GET_HW_POLICY within the list of PAL
-                          procedures.
-  @param ProcessorNumber  Unsigned 64-bit integer that specifies
-                          for which logical processor
-                          information is being requested. This
-                          input argument must be zero for the
-                          first call to this procedure and can
-                          be a maximum value of one less than
-                          the number of logical processors
-                          impacted by the hardware resource
-                          sharing policy, which is returned by
-                          the R10 return value.
-
-  @retval 0               Call completed without error
-  @retval -1              Unimplemented procedure
-  @retval -2              Invalid argument
-  @retval -3              Call completed with error.
-  @retval -9              Call requires PAL memory buffer.
-
-  @return R9              Unsigned 64-bit integer representing the current
-                          hardware resource sharing policy.
-  @return R10             Unsigned 64-bit integer that returns the number
-                          of logical processors impacted by the policy
-                          input argument.
-  @return R11             Unsigned 64-bit integer containing the logical
-                          address of one of the logical processors
-                          impacted by policy modification.
-
-**/
-#define PAL_GET_HW_POLICY   48
-
-
-//
-// Value of PAL_SET_HW_POLICY.Policy
-//
-#define PAL_SET_HW_POLICY_PERFORMANCE               0
-#define PAL_SET_HW_POLICY_FAIRNESS                  1
-#define PAL_SET_HW_POLICY_HIGH_PRIORITY             2
-#define PAL_SET_HW_POLICY_EXCLUSIVE_HIGH_PRIORITY   3
-
-/**
-  PAL Procedure - PAL_SET_HW_POLICY.
-
-  Sets the current hardware resource sharing policy of the
-  processor. It is optional by Itanium processors. The PAL procedure supports
-  the Static Registers calling convention. It could be called at
-  physical and Virtual mode.
-
-  @param Index    Index of PAL_SET_HW_POLICY within the list of PAL
-                  procedures.
-  @param Policy   Unsigned 64-bit integer specifying the hardware
-                  resource sharing policy the caller is setting.
-                  See Value of PAL_SET_HW_POLICY.Policy above.
-
-  @retval 1       Call completed successfully but could not
-                  change the hardware policy since a
-                  competing logical processor is set in
-                  exclusive high priority.
-  @retval 0       Call completed without error
-  @retval -1      Unimplemented procedure
-  @retval -2      Invalid argument
-  @retval -3      Call completed with error.
-  @retval -9      Call requires PAL memory buffer.
-
-**/
-#define PAL_SET_HW_POLICY   49
-
-typedef struct {
-  UINT64  Mode:3;                   ///< Bit2:0, Indicates the mode of operation for this
-                                    ///<    procedure: 0 - Query mode 1 - Error inject mode
-                                    ///<    (err_inj should also be specified) 2 - Cancel
-                                    ///<    outstanding trigger. All other fields in
-                                    ///<    PAL_MC_ERROR_TYPE_INFO,
-                                    ///<    PAL_MC_ERROR_STRUCTURE_INFO and
-                                    ///<    PAL_MC_ERROR_DATA_BUFFER are ignored. All other
-                                    ///<    values are reserved.
-
-  UINT64  ErrorInjection:3;         ///< Bit5:3, indicates the mode of error
-                                    ///<  injection: 0 - Error inject only (no
-                                    ///<  error consumption) 1 - Error inject
-                                    ///<  and consume All other values are
-                                    ///<  reserved.
-
-  UINT64  ErrorSeverity:2;          ///< Bit7:6, indicates the severity desired
-                                    ///<  for error injection/query. Definitions
-                                    ///<  of the different error severity types
-                                    ///<  0 - Corrected error 1 - Recoverable
-                                    ///<  error 2 - Fatal error 3 - Reserved
-
-  UINT64  ErrorStructure:5;         ///< Bit12:8, Indicates the structure
-                                    ///<  identification for error
-                                    ///<  injection/query: 0 - Any structure
-                                    ///<  (cannot be used during query mode).
-                                    ///<  When selected, the structure type used
-                                    ///<  for error injection is determined by
-                                    ///<  PAL. 1 - Cache 2 - TLB 3 - Register
-                                    ///<  file 4 - Bus/System interconnect 5-15
-                                    ///<  - Reserved 16-31 - Processor
-                                    ///<  specific error injection
-                                    ///<  capabilities.ErrorDataBuffer is used
-                                    ///<  to specify error types. Please refer
-                                    ///<  to the processor specific
-                                    ///<  documentation for additional details.
-
-  UINT64  StructureHierarchy:3;     ///< Bit15:13, Indicates the structure
-                                    ///<  hierarchy for error
-                                    ///<  injection/query: 0 - Any level of
-                                    ///<  hierarchy (cannot be used during
-                                    ///<  query mode). When selected, the
-                                    ///<  structure hierarchy used for error
-                                    ///<  injection is determined by PAL. 1
-                                    ///<  - Error structure hierarchy
-                                    ///<  level-1 2 - Error structure
-                                    ///<  hierarchy level-2 3 - Error
-                                    ///<  structure hierarchy level-3 4 -
-                                    ///<  Error structure hierarchy level-4
-                                    ///<  All other values are reserved.
-
-  UINT64  Reserved:32;              ///< Reserved 47:16 Reserved
-
-  UINT64  ImplSpec:16;              ///< Bit63:48, Processor specific error injection capabilities.
-} PAL_MC_ERROR_TYPE_INFO;
-
-typedef struct {
-  UINT64  StructInfoIsValid:1;              ///< Bit0 When 1, indicates that the
-                                            ///< structure information fields
-                                            ///< (c_t,cl_p,cl_id) are valid and
-                                            ///< should be used for error injection.
-                                            ///< When 0, the structure information
-                                            ///< fields are ignored, and the values
-                                            ///< of these fields used for error
-                                            ///< injection are
-                                            ///< implementation-specific.
-
-  UINT64  CacheType:2;                      ///< Bit2:1  Indicates which cache should be used
-                                            ///< for error injection: 0 - Reserved 1 -
-                                            ///< Instruction cache 2 - Data or unified cache
-                                            ///< 3 - Reserved
-
-  UINT64  PortionOfCacheLine:3;             ///< Bit5:3 Indicates the portion of the
-                                            ///<   cache line where the error should
-                                            ///<   be injected: 0 - Reserved 1 - Tag
-                                            ///<   2 - Data 3 - mesi All other
-                                            ///<   values are reserved.
-
-  UINT64  Mechanism:3;                      ///< Bit8:6 Indicates which mechanism is used to
-                                            ///< identify the cache line to be used for error
-                                            ///< injection: 0 - Reserved 1 - Virtual address
-                                            ///< provided in the inj_addr field of the buffer
-                                            ///< pointed to by err_data_buffer should be used
-                                            ///< to identify the cache line for error
-                                            ///< injection. 2 - Physical address provided in
-                                            ///< the inj_addr field of the buffer pointed to
-                                            ///< by err_data_buffershould be used to identify
-                                            ///< the cache line for error injection. 3 - way
-                                            ///< and index fields provided in err_data_buffer
-                                            ///< should be used to identify the cache line
-                                            ///< for error injection. All other values are
-                                            ///< reserved.
-
-  UINT64  DataPoisonOfCacheLine:1;          ///< Bit9 When 1, indicates that a
-                                            ///< multiple bit, non-correctable
-                                            ///< error should be injected in the
-                                            ///< cache line specified by cl_id.
-                                            ///< If this injected error is not
-                                            ///< consumed, it may eventually
-                                            ///< cause a data-poisoning event
-                                            ///< resulting in a corrected error
-                                            ///< signal, when the associated
-                                            ///< cache line is cast out (implicit
-                                            ///< or explicit write-back of the
-                                            ///< cache line). The error severity
-                                            ///< specified by err_sev in
-                                            ///< err_type_info must be set to 0
-                                            ///< (corrected error) when this bit
-                                            ///< is set.
-
-  UINT64  Reserved1:22;
-
-  UINT64  TrigerInfoIsValid:1;              ///< Bit32 When 1, indicates that the
-                                            ///< trigger information fields (trigger,
-                                            ///< trigger_pl) are valid and should be
-                                            ///< used for error injection. When 0,
-                                            ///< the trigger information fields are
-                                            ///< ignored and error injection is
-                                            ///< performed immediately.
-
-  UINT64  Triger:4;                         ///< Bit36:33 Indicates the operation type to be
-                                            ///<   used as the error trigger condition. The
-                                            ///<   address corresponding to the trigger is
-                                            ///<   specified in the trigger_addr field of the
-                                            ///<   buffer pointed to by err_data_buffer: 0 -
-                                            ///<   Instruction memory access. The trigger match
-                                            ///<   conditions for this operation type are similar
-                                            ///<   to the IBR address breakpoint match conditions
-                                            ///<   1 - Data memory access. The trigger match
-                                            ///<   conditions for this operation type are similar
-                                            ///<   to the DBR address breakpoint match conditions
-                                            ///<   All other values are reserved.
-
-  UINT64  PrivilegeOfTriger:3;              ///< Bit39:37  Indicates the privilege
-                                            ///< level of the context during which
-                                            ///< the error should be injected: 0 -
-                                            ///< privilege level 0 1 - privilege
-                                            ///< level 1 2 - privilege level 2 3 -
-                                            ///< privilege level 3 All other values
-                                            ///< are reserved. If the implementation
-                                            ///< does not support privilege level
-                                            ///< qualifier for triggers (i.e. if
-                                            ///< trigger_pl is 0 in the capabilities
-                                            ///< vector), this field is ignored and
-                                            ///< triggers can be taken at any
-                                            ///< privilege level.
-
-  UINT64  Reserved2:24;
-} PAL_MC_ERROR_STRUCT_INFO;
-
-/**
-
-   Buffer Pointed to by err_data_buffer - TLB
-
-**/
-typedef struct {
-  UINT64  TrigerAddress;
-  UINT64  VirtualPageNumber:52;
-  UINT64  Reserved1:8;
-  UINT64  RegionId:24;
-  UINT64  Reserved2:40;
-} PAL_MC_ERROR_DATA_BUFFER_TLB;
-
-/**
-  PAL Procedure - PAL_MC_ERROR_INJECT.
-
-  Injects the requested processor error or returns information
-  on the supported injection capabilities for this particular
-  processor implementation. It is optional by Itanium processors. The PAL
-  procedure supports the Stacked Registers calling convention.
-  It could be called at physical and Virtual mode.
-
-  @param Index            Index of PAL_MC_ERROR_INJECT within the list of PAL
-                          procedures.
-  @param ErrorTypeInfo    Unsigned 64-bit integer specifying the
-                          first level error information which
-                          identifies the error structure and
-                          corresponding structure hierarchy, and
-                          the error severity.
-  @param ErrorStructInfo  Unsigned 64-bit integer identifying
-                          the optional structure specific
-                          information that provides the  second
-                          level details for the requested error.
-  @param ErrorDataBuffer  64-bit physical address of a buffer
-                          providing additional parameters for
-                          the requested error. The address of
-                          this buffer must be 8-byte aligned.
-
-  @retval 0               Call completed without error
-  @retval -1              Unimplemented procedure
-  @retval -2              Invalid argument
-  @retval -3              Call completed with error.
-  @retval -4              Call completed with error; the requested
-                          error could not be injected due to failure in
-                          locating the target location in the specified
-                          structure.
-  @retval -5              Argument was valid, but requested error
-                          injection capability is not supported.
-  @retval -9              Call requires PAL memory buffer.
-
-  @return R9              64-bit vector specifying the supported error
-                          injection capabilities for the input argument
-                          combination of struct_hier, err_struct and
-                          err_sev fields in ErrorTypeInfo.
-  @return R10             64-bit vector specifying the architectural
-                          resources that are used by the procedure.
-
-**/
-#define PAL_MC_ERROR_INJECT 276
-
-
-//
-// Types of PAL_GET_PSTATE.Type
-//
-#define PAL_GET_PSTATE_RECENT                 0
-#define PAL_GET_PSTATE_AVERAGE_NEW_START      1
-#define PAL_GET_PSTATE_AVERAGE                2
-#define PAL_GET_PSTATE_NOW                    3
-
-/**
-  PAL Procedure - PAL_GET_PSTATE.
-
-  Returns the performance index of the processor. It is optional
-  by Itanium processors. The PAL procedure supports the Stacked Registers
-  calling convention. It could be called at physical and Virtual
-  mode.
-
-  @param Index  Index of PAL_GET_PSTATE within the list of PAL
-                procedures.
-  @param Type   Type of performance_index value to be returned
-                by this procedure.See PAL_GET_PSTATE.Type above.
-
-  @retval 1     Call completed without error, but accuracy
-                of performance index has been impacted by a
-                thermal throttling event, or a
-                hardware-initiated event.
-  @retval 0     Call completed without error
-  @retval -1    Unimplemented procedure
-  @retval -2    Invalid argument
-  @retval -3    Call completed with error.
-  @retval -9    Call requires PAL memory buffer.
-
-  @return R9    Unsigned integer denoting the processor
-                performance for the time duration since the last
-                PAL_GET_PSTATE procedure call was made. The
-                value returned is between 0 and 100, and is
-                relative to the performance index of the highest
-                available P-state.
-
-**/
-#define PAL_GET_PSTATE      262
-
-/**
-
-  Layout of PAL_PSTATE_INFO.PStateBuffer
-
-**/
-typedef struct {
-  UINT32  PerformanceIndex:7;
-  UINT32  Reserved1:5;
-  UINT32  TypicalPowerDissipation:20;
-  UINT32  TransitionLatency1;
-  UINT32  TransitionLatency2;
-  UINT32  Reserved2;
-} PAL_PSTATE_INFO_BUFFER;
-
-
-/**
-  PAL Procedure - PAL_PSTATE_INFO.
-
-  Returns information about the P-states supported by the
-  processor. It is optional by Itanium processors. The PAL procedure supports
-  the Static Registers calling convention. It could be called
-  at physical and Virtual mode.
-
-  @param Index          Index of PAL_PSTATE_INFO within the list of PAL
-                        procedures.
-  @param PStateBuffer   64-bit pointer to a 256-byte buffer
-                        aligned on an 8-byte boundary. See
-                        PAL_PSTATE_INFO_BUFFER above.
-
-  @retval 0             Call completed without error
-  @retval -1            Unimplemented procedure
-  @retval -2            Invalid argument
-  @retval -3            Call completed with error.
-
-  @return R9            Unsigned integer denoting the number of P-states
-                        supported. The maximum value of this field is 16.
-  @return R10           Dependency domain information
-
-**/
-#define PAL_PSTATE_INFO     44
-
-
-/**
-  PAL Procedure - PAL_SET_PSTATE.
-
-  To request a processor transition to a given P-state. It is
-  optional by Itanium processors. The PAL procedure supports the Stacked
-  Registers calling convention. It could be called at physical
-  and Virtual mode.
-
-  @param Index        Index of PAL_SET_PSTATE within the list of PAL
-                      procedures.
-  @param PState       Unsigned integer denoting the processor
-                      P-state being requested.
-  @param ForcePState  Unsigned integer denoting whether the
-                      P-state change should be forced for the
-                      logical processor.
-
-  @retval 1           Call completed without error, but
-                      transition request was not accepted
-  @retval 0           Call completed without error
-  @retval -1          Unimplemented procedure
-  @retval -2          Invalid argument
-  @retval -3          Call completed with error.
-  @retval -9          Call requires PAL memory buffer.
-
-**/
-#define PAL_SET_PSTATE      263
-
-/**
-  PAL Procedure - PAL_SHUTDOWN.
-
-  Put the logical processor into a low power state which can be
-  exited only by a reset event. It is optional by Itanium processors. The PAL
-  procedure supports the Static Registers calling convention. It
-  could be called at physical mode.
-
-  @param Index            Index of PAL_SHUTDOWN within the list of PAL
-                          procedures.
-  @param NotifyPlatform   8-byte aligned physical address
-                          pointer providing details on how to
-                          optionally notify the platform that
-                          the processor is entering a shutdown
-                          state.
-
-  @retval -1              Unimplemented procedure
-  @retval -2              Invalid argument
-  @retval -3              Call completed with error.
-  @retval -9              Call requires PAL memory buffer.
-
-**/
-#define PAL_SHUTDOWN        45
-
-/**
-
-  Layout of PAL_MEMORY_BUFFER.ControlWord
-
-**/
-typedef struct {
-  UINT64  Registration:1;
-  UINT64  ProbeInterrupt:1;
-  UINT64  Reserved:62;
-} PAL_MEMORY_CONTROL_WORD;
-
-/**
-  PAL Procedure - PAL_MEMORY_BUFFER.
-
-  Provides cacheable memory to PAL for exclusive use during
-  runtime. It is optional by Itanium processors. The PAL procedure supports the
-  Static Registers calling convention. It could be called at
-  physical mode.
-
-  @param Index        Index of PAL_MEMORY_BUFFER within the list of PAL
-                      procedures.
-  @param BaseAddress  Physical address of the memory buffer
-                      allocated for PAL use.
-  @param AllocSize    Unsigned integer denoting the size of the
-                      memory buffer.
-  @param ControlWord  Formatted bit vector that provides control
-                      options for this procedure. See
-                      PAL_MEMORY_CONTROL_WORD above.
-
-  @retval 1           Call has not completed a buffer relocation
-                      due to a pending interrupt
-  @retval 0           Call completed without error
-  @retval -1          Unimplemented procedure
-  @retval -2          Invalid argument
-  @retval -3          Call completed with error.
-  @retval -9          Call requires PAL memory buffer.
-
-  @return R9          Returns the minimum size of the memory buffer
-                      required if the alloc_size input argument was
-                      not large enough.
-
-**/
-#define PAL_MEMORY_BUFFER   277
-
-
-/**
-  PAL Procedure - PAL_VP_CREATE.
-
-  Initializes a new vpd for the operation of a new virtual
-  processor in the virtual environment. It is optional by Itanium processors.
-  The PAL procedure supports the Stacked Registers calling
-  convention. It could be called at Virtual mode.
-
-  @param Index            Index of PAL_VP_CREATE within the list of PAL
-                          procedures.
-  @param Vpd              64-bit host virtual pointer to the Virtual
-                          Processor Descriptor (VPD).
-  @param HostIva          64-bit host virtual pointer to the host IVT
-                          for the virtual processor
-  @param OptionalHandler  64-bit non-zero host-virtual pointer
-                          to an optional handler for
-                          virtualization intercepts.
-
-  @retval 0               Call completed without error
-  @retval -1              Unimplemented procedure
-  @retval -2              Invalid argument
-  @retval -3              Call completed with error.
-  @retval -9              Call requires PAL memory buffer.
-
-**/
-#define PAL_VP_CREATE       265
-
-/**
-
-  Virtual Environment Information Parameter
-
-**/
-typedef struct {
-  UINT64    Reserved1:8;
-  UINT64    Opcode:1;
-  UINT64    Reserved:53;
-} PAL_VP_ENV_INFO_RETURN;
-
-/**
-  PAL Procedure - PAL_VP_ENV_INFO.
-
-  Returns the parameters needed to enter a virtual environment.
-  It is optional by Itanium processors. The PAL procedure supports the Stacked
-  Registers calling convention. It could be called at Virtual
-  mode.
-
-  @param Index            Index of PAL_VP_ENV_INFO within the list of PAL
-                          procedures.
-  @param Vpd              64-bit host virtual pointer to the Virtual
-                          Processor Descriptor (VPD).
-  @param HostIva          64-bit host virtual pointer to the host IVT
-                          for the virtual processor
-  @param OptionalHandler  64-bit non-zero host-virtual pointer
-                          to an optional handler for
-                          virtualization intercepts.
-
-  @retval 0               Call completed without error
-  @retval -1              Unimplemented procedure
-  @retval -2              Invalid argument
-  @retval -3              Call completed with error.
-  @retval -9              Call requires PAL memory buffer.
-
-  @return R9              Unsigned integer denoting the number of bytes
-                          required by the PAL virtual environment buffer
-                          during PAL_VP_INIT_ENV
-  @return R10             64-bit vector of virtual environment
-                          information. See PAL_VP_ENV_INFO_RETURN.
-
-
-**/
-#define PAL_VP_ENV_INFO       266
-
-/**
-  PAL Procedure - PAL_VP_EXIT_ENV.
-
-  Allows a logical processor to exit a virtual environment.
-  It is optional by Itanium processors. The PAL procedure supports the Stacked
-  Registers calling convention. It could be called at Virtual
-  mode.
-
-  @param Index  Index of PAL_VP_EXIT_ENV within the list of PAL
-                procedures.
-  @param Iva    Optional 64-bit host virtual pointer to the IVT
-                when this procedure is done
-
-  @retval 0     Call completed without error
-  @retval -1    Unimplemented procedure
-  @retval -2    Invalid argument
-  @retval -3    Call completed with error.
-  @retval -9    Call requires PAL memory buffer.
-
-**/
-#define PAL_VP_EXIT_ENV       267
-
-
-
-/**
-  PAL Procedure - PAL_VP_INIT_ENV.
-
-  Allows a logical processor to enter a virtual environment. It
-  is optional by Itanium processors. The PAL procedure supports the Stacked
-  Registers calling convention. It could be called at Virtual
-  mode.
-
-  @param Index          Index of PAL_VP_INIT_ENV within the list of PAL
-                        procedures.
-  @param ConfigOptions  64-bit vector of global configuration
-                        settings.
-  @param PhysicalBase   Host physical base address of a block of
-                        contiguous physical memory for the PAL
-                        virtual environment buffer 1) This
-                        memory area must be allocated by the VMM
-                        and be 4K aligned. The first logical
-                        processor to enter the environment will
-                        initialize the physical block for
-                        virtualization operations.
-  @param VirtualBase    Host virtual base address of the
-                        corresponding physical memory block for
-                        the PAL virtual environment buffer : The
-                        VMM must maintain the host virtual to host
-                        physical data and instruction translations
-                        in TRs for addresses within the allocated
-                        address space. Logical processors in this
-                        virtual environment will use this address
-                        when transitioning to virtual mode
-                        operations.
-
-  @retval 0             Call completed without error
-  @retval -1            Unimplemented procedure
-  @retval -2            Invalid argument
-  @retval -3            Call completed with error.
-  @retval -9            Call requires PAL memory buffer.
-
-  @return R9            Virtualization Service Address - VSA specifies
-                        the virtual base address of the PAL
-                        virtualization services in this virtual
-                        environment.
-
-
-**/
-#define PAL_VP_INIT_ENV       268
-
-
-/**
-  PAL Procedure - PAL_VP_REGISTER.
-
-  Register a different host IVT and/or a different optional
-  virtualization intercept handler for the virtual processor
-  specified by vpd. It is optional by Itanium processors. The PAL procedure
-  supports the Stacked Registers calling convention. It could be
-  called at Virtual mode.
-
-  @param Index            Index of PAL_VP_REGISTER within the list of PAL
-                          procedures.
-  @param Vpd              64-bit host virtual pointer to the Virtual
-                          Processor Descriptor (VPD) host_iva 64-bit host
-                          virtual pointer to the host IVT for the virtual
-                          processor
-  @param OptionalHandler  64-bit non-zero host-virtual pointer
-                          to an optional handler for
-                          virtualization intercepts.
-
-  @retval 0               Call completed without error
-  @retval -1              Unimplemented procedure
-  @retval -2              Invalid argument
-  @retval -3              Call completed with error.
-  @retval -9              Call requires PAL memory buffer.
-
-**/
-#define PAL_VP_REGISTER       269
-
-
-/**
-  PAL Procedure - PAL_VP_RESTORE.
-
-  Restores virtual processor state for the specified vpd on the
-  logical processor. It is optional by Itanium processors. The PAL procedure
-  supports the Stacked Registers calling convention. It could be
-  called at Virtual mode.
-
-  @param Index      Index of PAL_VP_RESTORE within the list of PAL
-                    procedures.
-  @param Vpd        64-bit host virtual pointer to the Virtual
-                    Processor Descriptor (VPD) host_iva 64-bit host
-                    virtual pointer to the host IVT for the virtual
-                    processor
-  @param PalVector  Vector specifies PAL procedure
-                    implementation-specific state to be
-                    restored.
-
-  @retval 0         Call completed without error
-  @retval -1        Unimplemented procedure
-  @retval -2        Invalid argument
-  @retval -3        Call completed with error.
-  @retval -9        Call requires PAL memory buffer.
-
-**/
-#define PAL_VP_RESTORE       270
-
-/**
-  PAL Procedure - PAL_VP_SAVE.
-
-  Saves virtual processor state for the specified vpd on the
-  logical processor. It is optional by Itanium processors. The PAL procedure
-  supports the Stacked Registers calling convention. It could be
-  called at Virtual mode.
-
-  @param Index      Index of PAL_VP_SAVE within the list of PAL
-                    procedures.
-  @param Vpd        64-bit host virtual pointer to the Virtual
-                    Processor Descriptor (VPD) host_iva 64-bit host
-                    virtual pointer to the host IVT for the virtual
-                    processor
-  @param PalVector  Vector specifies PAL procedure
-                    implementation-specific state to be
-                    restored.
-
-  @retval 0         Call completed without error
-  @retval -1        Unimplemented procedure
-  @retval -2        Invalid argument
-  @retval -3        Call completed with error.
-  @retval -9        Call requires PAL memory buffer.
-
-**/
-#define PAL_VP_SAVE       271
-
-
-/**
-  PAL Procedure - PAL_VP_TERMINATE.
-
-  Terminates operation for the specified virtual processor. It
-  is optional by Itanium processors. The PAL procedure supports the Stacked
-  Registers calling convention. It could be called at Virtual
-  mode.
-
-  @param Index  Index of PAL_VP_TERMINATE within the list of PAL
-                procedures.
-  @param Vpd    64-bit host virtual pointer to the Virtual
-                Processor Descriptor (VPD)
-  @param Iva    Optional 64-bit host virtual pointer to the IVT
-                when this procedure is done.
-
-  @retval 0     Call completed without error
-  @retval -1    Unimplemented procedure
-  @retval -2    Invalid argument
-  @retval -3    Call completed with error.
-  @retval -9    Call requires PAL memory buffer.
-
-**/
-#define PAL_VP_TERMINATE       272
-
-#endif
diff --git a/MdePkg/Include/IndustryStandard/Pci.h b/MdePkg/Include/IndustryStandard/Pci.h
index e5954dbce7a5..ef5791ef568f 100644
--- a/MdePkg/Include/IndustryStandard/Pci.h
+++ b/MdePkg/Include/IndustryStandard/Pci.h
@@ -1,14 +1,8 @@
 /** @file
   Support for the latest PCI standard.
 
-Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.                                            
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/IndustryStandard/Pci22.h b/MdePkg/Include/IndustryStandard/Pci22.h
index 97f70e1d324f..69e15f7aa9d9 100644
--- a/MdePkg/Include/IndustryStandard/Pci22.h
+++ b/MdePkg/Include/IndustryStandard/Pci22.h
@@ -5,17 +5,11 @@
     PCI Local Bus Specification, 2.2
     PCI-to-PCI Bridge Architecture Specification, Revision 1.2
     PC Card Standard, 8.0
-    PCI Power Management Interface Specifiction, Revision 1.2
+    PCI Power Management Interface Specification, Revision 1.2
 
-  Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
   Copyright (c) 2014 - 2015, Hewlett-Packard Development Company, L.P.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -116,12 +110,12 @@ typedef union {
   PCI_TYPE01  Bridge;
 } PCI_TYPE_GENERIC;
 
-/// 
-/// CardBus Conroller Configuration Space, 
+///
+/// CardBus Controller Configuration Space,
 /// Section 4.5.1, PC Card Standard. 8.0
 ///
 typedef struct {
-  UINT32  CardBusSocketReg;     ///< Cardus Socket/ExCA Base
+  UINT32  CardBusSocketReg;     ///< Cardbus Socket/ExCA Base
   UINT8   Cap_Ptr;
   UINT8   Reserved;
   UINT16  SecondaryStatus;      ///< Secondary Status
@@ -158,7 +152,7 @@ typedef struct {
 #define   PCI_CLASS_MASS_STORAGE_OTHER  0x80
 
 #define PCI_CLASS_NETWORK             0x02
-#define   PCI_CLASS_NETWORK_ETHERNET    0x00  
+#define   PCI_CLASS_NETWORK_ETHERNET    0x00
 #define   PCI_CLASS_NETWORK_TOKENRING   0x01
 #define   PCI_CLASS_NETWORK_FDDI        0x02
 #define   PCI_CLASS_NETWORK_ATM         0x03
@@ -171,7 +165,7 @@ typedef struct {
 #define     PCI_IF_VGA_8514               0x01
 #define   PCI_CLASS_DISPLAY_XGA         0x01
 #define   PCI_CLASS_DISPLAY_3D          0x02
-#define   PCI_CLASS_DISPLAY_OTHER       0x80  
+#define   PCI_CLASS_DISPLAY_OTHER       0x80
 
 #define PCI_CLASS_MEDIA               0x04
 #define   PCI_CLASS_MEDIA_VIDEO         0x00
@@ -199,7 +193,7 @@ typedef struct {
 #define   PCI_CLASS_BRIDGE_OTHER        0x80
 #define   PCI_CLASS_BRIDGE_ISA_PDECODE  0x80
 
-#define PCI_CLASS_SCC                 0x07  ///< Simple communications controllers 
+#define PCI_CLASS_SCC                 0x07  ///< Simple communications controllers
 #define   PCI_SUBCLASS_SERIAL           0x00
 #define     PCI_IF_GENERIC_XT             0x00
 #define     PCI_IF_16450                  0x01
@@ -228,8 +222,8 @@ typedef struct {
 #define     PCI_IF_8259_PIC               0x00
 #define     PCI_IF_ISA_PIC                0x01
 #define     PCI_IF_EISA_PIC               0x02
-#define     PCI_IF_APIC_CONTROLLER        0x10  ///< I/O APIC interrupt controller , 32 bye none-prefectable memory.  
-#define     PCI_IF_APIC_CONTROLLER2       0x20 
+#define     PCI_IF_APIC_CONTROLLER        0x10  ///< I/O APIC interrupt controller , 32 byte none-prefetchable memory.
+#define     PCI_IF_APIC_CONTROLLER2       0x20
 #define   PCI_SUBCLASS_DMA              0x01
 #define     PCI_IF_8237_DMA               0x00
 #define     PCI_IF_ISA_DMA                0x01
@@ -297,25 +291,25 @@ typedef struct {
 
 #define PCI_SECURITY_CONTROLLER       0x10   ///< Encryption and decryption controller
 #define   PCI_SUBCLASS_NET_COMPUT       0x00
-#define   PCI_SUBCLASS_ENTERTAINMENT    0x10 
+#define   PCI_SUBCLASS_ENTERTAINMENT    0x10
 #define   PCI_SUBCLASS_SECURITY_OTHER   0x80
 
 #define PCI_CLASS_DPIO                0x11
 #define   PCI_SUBCLASS_DPIO             0x00
 #define   PCI_SUBCLASS_DPIO_OTHER       0x80
 
-/**  
+/**
   Macro that checks whether the Base Class code of device matched.
 
   @param  _p      Specified device.
   @param  c       Base Class code needs matching.
 
   @retval TRUE    Base Class code matches the specified device.
-  @retval FALSE   Base Class code doesn't match the specified device.         
+  @retval FALSE   Base Class code doesn't match the specified device.
 
 **/
 #define IS_CLASS1(_p, c)              ((_p)->Hdr.ClassCode[2] == (c))
-/**  
+/**
   Macro that checks whether the Base Class code and Sub-Class code of device matched.
 
   @param  _p      Specified device.
@@ -323,11 +317,11 @@ typedef struct {
   @param  s       Sub-Class code needs matching.
 
   @retval TRUE    Base Class code and Sub-Class code match the specified device.
-  @retval FALSE   Base Class code and Sub-Class code don't match the specified device.         
+  @retval FALSE   Base Class code and Sub-Class code don't match the specified device.
 
 **/
 #define IS_CLASS2(_p, c, s)           (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))
-/**  
+/**
   Macro that checks whether the Base Class code, Sub-Class code and Interface code of device matched.
 
   @param  _p      Specified device.
@@ -336,12 +330,12 @@ typedef struct {
   @param  p       Interface code needs matching.
 
   @retval TRUE    Base Class code, Sub-Class code and Interface code match the specified device.
-  @retval FALSE   Base Class code, Sub-Class code and Interface code don't match the specified device.         
+  @retval FALSE   Base Class code, Sub-Class code and Interface code don't match the specified device.
 
 **/
 #define IS_CLASS3(_p, c, s, p)        (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))
 
-/**  
+/**
   Macro that checks whether device is a display controller.
 
   @param  _p      Specified device.
@@ -351,7 +345,7 @@ typedef struct {
 
 **/
 #define IS_PCI_DISPLAY(_p)            IS_CLASS1 (_p, PCI_CLASS_DISPLAY)
-/**  
+/**
   Macro that checks whether device is a VGA-compatible controller.
 
   @param  _p      Specified device.
@@ -361,7 +355,7 @@ typedef struct {
 
 **/
 #define IS_PCI_VGA(_p)                IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_VGA)
-/**  
+/**
   Macro that checks whether device is an 8514-compatible controller.
 
   @param  _p      Specified device.
@@ -371,7 +365,7 @@ typedef struct {
 
 **/
 #define IS_PCI_8514(_p)               IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_8514)
-/**  
+/**
   Macro that checks whether device is built before the Class Code field was defined.
 
   @param  _p      Specified device.
@@ -381,7 +375,7 @@ typedef struct {
 
 **/
 #define IS_PCI_OLD(_p)                IS_CLASS1 (_p, PCI_CLASS_OLD)
-/**  
+/**
   Macro that checks whether device is a VGA-compatible device built before the Class Code field was defined.
 
   @param  _p      Specified device.
@@ -391,7 +385,7 @@ typedef struct {
 
 **/
 #define IS_PCI_OLD_VGA(_p)            IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)
-/**  
+/**
   Macro that checks whether device is an IDE controller.
 
   @param  _p      Specified device.
@@ -401,7 +395,7 @@ typedef struct {
 
 **/
 #define IS_PCI_IDE(_p)                IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)
-/**  
+/**
   Macro that checks whether device is a SCSI bus controller.
 
   @param  _p      Specified device.
@@ -411,7 +405,7 @@ typedef struct {
 
 **/
 #define IS_PCI_SCSI(_p)               IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI)
-/**  
+/**
   Macro that checks whether device is a RAID controller.
 
   @param  _p      Specified device.
@@ -421,7 +415,7 @@ typedef struct {
 
 **/
 #define IS_PCI_RAID(_p)               IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID)
-/**  
+/**
   Macro that checks whether device is an ISA bridge.
 
   @param  _p      Specified device.
@@ -431,7 +425,7 @@ typedef struct {
 
 **/
 #define IS_PCI_LPC(_p)                IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA)
-/**  
+/**
   Macro that checks whether device is a PCI-to-PCI bridge.
 
   @param  _p      Specified device.
@@ -441,7 +435,7 @@ typedef struct {
 
 **/
 #define IS_PCI_P2P(_p)                IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P)
-/**  
+/**
   Macro that checks whether device is a Subtractive Decode PCI-to-PCI bridge.
 
   @param  _p      Specified device.
@@ -451,7 +445,7 @@ typedef struct {
 
 **/
 #define IS_PCI_P2P_SUB(_p)            IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P_SUBTRACTIVE)
-/**  
+/**
   Macro that checks whether device is a 16550-compatible serial controller.
 
   @param  _p      Specified device.
@@ -461,7 +455,7 @@ typedef struct {
 
 **/
 #define IS_PCI_16550_SERIAL(_p)       IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)
-/**  
+/**
   Macro that checks whether device is a Universal Serial Bus controller.
 
   @param  _p      Specified device.
@@ -473,7 +467,7 @@ typedef struct {
 #define IS_PCI_USB(_p)                IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)
 
 //
-// the definition of Header Type 
+// the definition of Header Type
 //
 #define HEADER_TYPE_DEVICE            0x00
 #define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01
@@ -483,7 +477,7 @@ typedef struct {
 // Mask of Header type
 //
 #define HEADER_LAYOUT_CODE            0x7f
-/**  
+/**
   Macro that checks whether device is a PCI-PCI bridge.
 
   @param  _p      Specified device.
@@ -493,7 +487,7 @@ typedef struct {
 
 **/
 #define IS_PCI_BRIDGE(_p)             (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))
-/**  
+/**
   Macro that checks whether device is a CardBus bridge.
 
   @param  _p      Specified device.
@@ -503,7 +497,7 @@ typedef struct {
 
 **/
 #define IS_CARDBUS_BRIDGE(_p)         (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))
-/**  
+/**
   Macro that checks whether device is a multiple functions device.
 
   @param  _p      Specified device.
@@ -515,7 +509,7 @@ typedef struct {
 #define IS_PCI_MULTI_FUNC(_p)         ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)
 
 ///
-/// Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecure Specification,
+/// Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecture Specification,
 ///
 #define PCI_BRIDGE_ROMBAR             0x38
 
@@ -548,17 +542,17 @@ typedef struct {
 //
 // defined in PCI-to-PCI Bridge Architecture Specification
 //
-#define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET      0x18   
-#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET    0x19   
-#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET  0x1a   
+#define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET      0x18
+#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET    0x19
+#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET  0x1a
 #define PCI_BRIDGE_SECONDARY_LATENCY_TIMER_OFFSET   0x1b
-#define PCI_BRIDGE_STATUS_REGISTER_OFFSET           0x1E   
-#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET          0x3E   
+#define PCI_BRIDGE_STATUS_REGISTER_OFFSET           0x1E
+#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET          0x3E
 
 ///
 /// Interrupt Line "Unknown" or "No connection" value defined for x86 based system
 ///
-#define PCI_INT_LINE_UNKNOWN                        0xFF               
+#define PCI_INT_LINE_UNKNOWN                        0xFF
 
 ///
 /// PCI Access Data Format
@@ -648,7 +642,7 @@ typedef struct {
 
 ///
 /// PMC - Power Management Capabilities
-/// Section 3.2.3, PCI Power Management Interface Specifiction, Revision 1.2
+/// Section 3.2.3, PCI Power Management Interface Specification, Revision 1.2
 ///
 typedef union {
   struct {
@@ -668,7 +662,7 @@ typedef union {
 
 ///
 /// PMCSR - Power Management Control/Status
-/// Section 3.2.4, PCI Power Management Interface Specifiction, Revision 1.2
+/// Section 3.2.4, PCI Power Management Interface Specification, Revision 1.2
 ///
 typedef union {
   struct {
@@ -691,7 +685,7 @@ typedef union {
 
 ///
 /// PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions
-/// Section 3.2.5, PCI Power Management Interface Specifiction, Revision 1.2
+/// Section 3.2.5, PCI Power Management Interface Specification, Revision 1.2
 ///
 typedef union {
   struct {
@@ -704,7 +698,7 @@ typedef union {
 
 ///
 /// Power Management Register Block Definition
-/// Section 3.2, PCI Power Management Interface Specifiction, Revision 1.2
+/// Section 3.2, PCI Power Management Interface Specification, Revision 1.2
 ///
 typedef struct {
   EFI_PCI_CAPABILITY_HDR  Hdr;
@@ -738,7 +732,7 @@ typedef struct {
 
 ///
 /// Slot Numbering Capabilities Register
-/// Section 3.2.6, PCI-to-PCI Bridge Architeture Specification, Revision 1.2
+/// Section 3.2.6, PCI-to-PCI Bridge Architecture Specification, Revision 1.2
 ///
 typedef struct {
   EFI_PCI_CAPABILITY_HDR  Hdr;
@@ -770,7 +764,7 @@ typedef struct {
 } EFI_PCI_CAPABILITY_MSI64;
 
 ///
-/// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG, 
+/// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG,
 /// CompactPCI Hot Swap Specification PICMG 2.1, R1.0
 ///
 typedef struct {
@@ -780,25 +774,6 @@ typedef struct {
   ///
 } EFI_PCI_CAPABILITY_HOTPLUG;
 
-///
-/// Below macros (till PCI_BAR_NOCHANGE) were used by EfiIncompatiblePciDeviceSupport Protocol.
-///
-#ifndef DISABLE_NEW_DEPRECATED_INTERFACES
-
-///
-/// [ATTENTION] These macros are deprecated because they don't match Spec or not defined in Spec.
-///
-#define DEVICE_ID_NOCARE    0xFFFF                 ///< Deprecated. Value doesn't match Spec.
-#define PCI_BAR_OLD_ALIGN   0xFFFFFFFFFFFFFFFFULL  ///< Deprecated. Value isn't defined in Spec.
-#define PCI_BAR_EVEN_ALIGN  0xFFFFFFFFFFFFFFFEULL  ///< Deprecated. Value isn't defined in Spec.
-#define PCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL  ///< Deprecated. Value isn't defined in Spec.
-#define PCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL  ///< Deprecated. Value isn't defined in Spec.
-#define PCI_BAR_ALL         0xFF                   ///< Deprecated. Value doesn't match Spec.
-#define PCI_ACPI_UNUSED     0                      ///< Deprecated. Macro name is too general.
-#define PCI_BAR_NOCHANGE    0                      ///< Deprecated. Macro name is too general.
-
-#endif
-
 #define PCI_BAR_IDX0        0x00
 #define PCI_BAR_IDX1        0x01
 #define PCI_BAR_IDX2        0x02
@@ -808,8 +783,8 @@ typedef struct {
 
 ///
 /// EFI PCI Option ROM definitions
-/// 
-#define EFI_ROOT_BRIDGE_LIST                            'eprb'  
+///
+#define EFI_ROOT_BRIDGE_LIST                            'eprb'
 #define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE       0x0EF1  ///< defined in UEFI Spec.
 
 #define PCI_EXPANSION_ROM_HEADER_SIGNATURE              0xaa55
diff --git a/MdePkg/Include/IndustryStandard/Pci23.h b/MdePkg/Include/IndustryStandard/Pci23.h
index b4698ac2fbfa..0ce38eb867d9 100644
--- a/MdePkg/Include/IndustryStandard/Pci23.h
+++ b/MdePkg/Include/IndustryStandard/Pci23.h
@@ -1,14 +1,8 @@
 /** @file
   Support for PCI 2.3 standard.
 
-  Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php.                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -92,10 +86,11 @@
 /// PCI Capability List IDs and records.
 ///
 #define EFI_PCI_CAPABILITY_ID_PCIX    0x07
+#define EFI_PCI_CAPABILITY_ID_VENDOR  0x09
 
 #pragma pack(1)
 ///
-/// PCI-X Capabilities List, 
+/// PCI-X Capabilities List,
 /// Section 7.2, PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b.
 ///
 typedef struct {
@@ -105,7 +100,7 @@ typedef struct {
 } EFI_PCI_CAPABILITY_PCIX;
 
 ///
-/// PCI-X Bridge Capabilities List, 
+/// PCI-X Bridge Capabilities List,
 /// Section 8.6.2, PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b.
 ///
 typedef struct {
@@ -116,6 +111,15 @@ typedef struct {
   UINT32                  SplitTransCtrlRegDn;
 } EFI_PCI_CAPABILITY_PCIX_BRDG;
 
+///
+/// Vendor Specific Capability Header
+/// Table H-1: Capability IDs, PCI Local Bus Specification, 2.3
+///
+typedef struct {
+  EFI_PCI_CAPABILITY_HDR  Hdr;
+  UINT8                   Length;
+} EFI_PCI_CAPABILITY_VENDOR_HDR;
+
 #pragma pack()
 
 #define PCI_CODE_TYPE_EFI_IMAGE       0x03
diff --git a/MdePkg/Include/IndustryStandard/Pci30.h b/MdePkg/Include/IndustryStandard/Pci30.h
index 57bd5a4179d2..beefb1aeb438 100644
--- a/MdePkg/Include/IndustryStandard/Pci30.h
+++ b/MdePkg/Include/IndustryStandard/Pci30.h
@@ -1,14 +1,8 @@
 /** @file
   Support for PCI 3.0 standard.
 
-  Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/IndustryStandard/PciCodeId.h b/MdePkg/Include/IndustryStandard/PciCodeId.h
index 31b6b8ec5d3a..e5b63c3f42d4 100644
--- a/MdePkg/Include/IndustryStandard/PciCodeId.h
+++ b/MdePkg/Include/IndustryStandard/PciCodeId.h
@@ -2,14 +2,8 @@
   The file lists the PCI class codes only defined in PCI code and ID assignment specification
   revision 1.3.
 
-  Copyright (c) 2012, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/IndustryStandard/PciExpress21.h b/MdePkg/Include/IndustryStandard/PciExpress21.h
index 61ec5542072f..4f1322310bea 100644
--- a/MdePkg/Include/IndustryStandard/PciExpress21.h
+++ b/MdePkg/Include/IndustryStandard/PciExpress21.h
@@ -1,15 +1,9 @@
 /** @file
   Support for the latest PCI standard.
 
-  Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
-  (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>  
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -18,6 +12,23 @@
 
 #include <IndustryStandard/Pci30.h>
 
+/**
+  Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
+  ECAM (Enhanced Configuration Access Mechanism) address. The unused upper bits
+  of Bus, Device, Function and Register are stripped prior to the generation of
+  the address.
+
+  @param  Bus       PCI Bus number. Range 0..255.
+  @param  Device    PCI Device number. Range 0..31.
+  @param  Function  PCI Function number. Range 0..7.
+  @param  Register  PCI Register number. Range 0..4095.
+
+  @return The encode ECAM address.
+
+**/
+#define PCI_ECAM_ADDRESS(Bus,Device,Function,Offset) \
+  (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
+
 #pragma pack(1)
 ///
 /// PCI Express Capability Structure
@@ -80,6 +91,24 @@ typedef union {
   UINT16   Uint16;
 } PCI_REG_PCIE_DEVICE_CONTROL;
 
+#define PCIE_MAX_PAYLOAD_SIZE_128B   0
+#define PCIE_MAX_PAYLOAD_SIZE_256B   1
+#define PCIE_MAX_PAYLOAD_SIZE_512B   2
+#define PCIE_MAX_PAYLOAD_SIZE_1024B  3
+#define PCIE_MAX_PAYLOAD_SIZE_2048B  4
+#define PCIE_MAX_PAYLOAD_SIZE_4096B  5
+#define PCIE_MAX_PAYLOAD_SIZE_RVSD1  6
+#define PCIE_MAX_PAYLOAD_SIZE_RVSD2  7
+
+#define PCIE_MAX_READ_REQ_SIZE_128B    0
+#define PCIE_MAX_READ_REQ_SIZE_256B    1
+#define PCIE_MAX_READ_REQ_SIZE_512B    2
+#define PCIE_MAX_READ_REQ_SIZE_1024B   3
+#define PCIE_MAX_READ_REQ_SIZE_2048B   4
+#define PCIE_MAX_READ_REQ_SIZE_4096B   5
+#define PCIE_MAX_READ_REQ_SIZE_RVSD1   6
+#define PCIE_MAX_READ_REQ_SIZE_RVSD2   7
+
 typedef union {
   struct {
     UINT16 CorrectableError : 1;
@@ -165,18 +194,18 @@ typedef union {
 
 typedef union {
   struct {
-    UINT32 AttentionButtonPressed : 1;
-    UINT32 PowerFaultDetected : 1;
-    UINT32 MrlSensorChanged : 1;
-    UINT32 PresenceDetectChanged : 1;
-    UINT32 CommandCompletedInterrupt : 1;
-    UINT32 HotPlugInterrupt : 1;
-    UINT32 AttentionIndicator : 2;
-    UINT32 PowerIndicator : 2;
-    UINT32 PowerController : 1;
-    UINT32 ElectromechanicalInterlock : 1;
-    UINT32 DataLinkLayerStateChanged : 1;
-    UINT32 Reserved : 3;
+    UINT16 AttentionButtonPressed : 1;
+    UINT16 PowerFaultDetected : 1;
+    UINT16 MrlSensorChanged : 1;
+    UINT16 PresenceDetectChanged : 1;
+    UINT16 CommandCompletedInterrupt : 1;
+    UINT16 HotPlugInterrupt : 1;
+    UINT16 AttentionIndicator : 2;
+    UINT16 PowerIndicator : 2;
+    UINT16 PowerController : 1;
+    UINT16 ElectromechanicalInterlock : 1;
+    UINT16 DataLinkLayerStateChanged : 1;
+    UINT16 Reserved : 3;
   } Bits;
   UINT16   Uint16;
 } PCI_REG_PCIE_SLOT_CONTROL;
@@ -239,16 +268,30 @@ typedef union {
     UINT32 NoRoEnabledPrPrPassing : 1;
     UINT32 LtrMechanism : 1;
     UINT32 TphCompleter : 2;
-    UINT32 Reserved : 4;
+    UINT32 LnSystemCLS : 2;
+    UINT32 TenBitTagCompleterSupported : 1;
+    UINT32 TenBitTagRequesterSupported : 1;
     UINT32 Obff : 2;
     UINT32 ExtendedFmtField : 1;
     UINT32 EndEndTlpPrefix : 1;
     UINT32 MaxEndEndTlpPrefixes : 2;
-    UINT32 Reserved2 : 8;
+    UINT32 EmergencyPowerReductionSupported : 2;
+    UINT32 EmergencyPowerReductionInitializationRequired : 1;
+    UINT32 Reserved3 : 4;
+    UINT32 FrsSupported : 1;
   } Bits;
   UINT32   Uint32;
 } PCI_REG_PCIE_DEVICE_CAPABILITY2;
 
+#define PCIE_COMPLETION_TIMEOUT_NOT_SUPPORTED           0
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_SUPPORTED       1
+#define PCIE_COMPLETION_TIMEOUT_RANGE_B_SUPPORTED       2
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_SUPPORTED     3
+#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_SUPPORTED     6
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_SUPPORTED   7
+#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_D_SUPPORTED   14
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_D_SUPPORTED 15
+
 #define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0
 #define PCIE_DEVICE_CAPABILITY_OBFF_WAKE    BIT1
 
@@ -261,8 +304,9 @@ typedef union {
     UINT16 AtomicOpEgressBlocking : 1;
     UINT16 IdoRequest : 1;
     UINT16 IdoCompletion : 1;
-    UINT16 LtrMechanism : 2;
-    UINT16 Reserved : 2;
+    UINT16 LtrMechanism : 1;
+    UINT16 EmergencyPowerReductionRequest : 1;
+    UINT16 TenBitTagRequesterEnable : 1;
     UINT16 Obff : 2;
     UINT16 EndEndTlpPrefixBlocking : 1;
   } Bits;
diff --git a/MdePkg/Include/IndustryStandard/PciExpress30.h b/MdePkg/Include/IndustryStandard/PciExpress30.h
index 5ab7feb8d64f..2e52e0782af6 100644
--- a/MdePkg/Include/IndustryStandard/PciExpress30.h
+++ b/MdePkg/Include/IndustryStandard/PciExpress30.h
@@ -3,14 +3,8 @@
 
   This header file may not define all structures.  Please extend as required.
 
-  Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/IndustryStandard/PciExpress31.h b/MdePkg/Include/IndustryStandard/PciExpress31.h
index 72a3ccda81ee..2e5e097be9db 100644
--- a/MdePkg/Include/IndustryStandard/PciExpress31.h
+++ b/MdePkg/Include/IndustryStandard/PciExpress31.h
@@ -4,13 +4,7 @@ Support for the PCI Express 3.1 standard.
 This header file may not define all structures.  Please extend as required.
 
 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/IndustryStandard/PciExpress40.h b/MdePkg/Include/IndustryStandard/PciExpress40.h
new file mode 100644
index 000000000000..a76f1bd5ae81
--- /dev/null
+++ b/MdePkg/Include/IndustryStandard/PciExpress40.h
@@ -0,0 +1,111 @@
+/** @file
+Support for the PCI Express 4.0 standard.
+
+This header file may not define all structures.  Please extend as required.
+
+Copyright (c) 2018, American Megatrends, Inc. All rights reserved.<BR>
+Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCIEXPRESS40_H_
+#define _PCIEXPRESS40_H_
+
+#include <IndustryStandard/PciExpress31.h>
+
+#pragma pack(1)
+
+/// The Physical Layer PCI Express Extended Capability definitions.
+///
+/// Based on section 7.7.5 of PCI Express Base Specification 4.0.
+///@{
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_ID    0x0026
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_VER1  0x1
+
+// Register offsets from Physical Layer PCI-E Ext Cap Header
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES_OFFSET                         0x04
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL_OFFSET                              0x08
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS_OFFSET                               0x0C
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LOCAL_DATA_PARITY_STATUS_OFFSET             0x10
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_FIRST_RETIMER_DATA_PARITY_STATUS_OFFSET     0x14
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_SECOND_RETIMER_DATA_PARITY_STATUS_OFFSET    0x18
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL_OFFSET            0x20
+
+typedef union {
+  struct {
+    UINT32 Reserved                  : 32; // Reserved bit 0:31
+  } Bits;
+  UINT32   Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES;
+
+typedef union {
+  struct {
+    UINT32 Reserved                  : 32; // Reserved bit 0:31
+  } Bits;
+  UINT32   Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL;
+
+typedef union {
+  struct {
+    UINT32 EqualizationComplete      : 1; // bit 0
+    UINT32 EqualizationPhase1Success : 1; // bit 1
+    UINT32 EqualizationPhase2Success : 1; // bit 2
+    UINT32 EqualizationPhase3Success : 1; // bit 3
+    UINT32 LinkEqualizationRequest   : 1; // bit 4
+    UINT32 Reserved                  : 27; // Reserved bit 5:31
+  } Bits;
+  UINT32   Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS;
+
+typedef union {
+  struct {
+    UINT8 DownstreamPortTransmitterPreset : 4; //bit 0..3
+    UINT8 UpstreamPortTransmitterPreset   : 4; //bit 4..7
+  } Bits;
+  UINT8   Uint8;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL;
+
+typedef struct {
+  PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER                      Header;
+  PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES              Capablities;
+  PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL                   Control;
+  PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS                    Status;
+  UINT32                                                        LocalDataParityMismatchStatus;
+  UINT32                                                        FirstRetimerDataParityMismatchStatus;
+  UINT32                                                        SecondRetimerDataParityMismatchStatus;
+  UINT32                                                        Reserved;
+  PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL LaneEqualizationControl[1];
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_16_0;
+///@}
+
+/// The Designated Vendor Specific Capability definitions
+/// Based on section 7.9.6 of PCI Express Base Specification 4.0.
+///@{
+typedef union {
+  struct {
+    UINT32 DvsecVendorId                                        : 16; //bit 0..15
+    UINT32 DvsecRevision                                        : 4;  //bit 16..19
+    UINT32 DvsecLength                                          : 12; //bit 20..31
+  }Bits;
+  UINT32                                                        Uint32;
+}PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1;
+
+typedef union {
+  struct {
+    UINT16 DvsecId                                              : 16; //bit 0..15
+  }Bits;
+  UINT16                                                        Uint16;
+}PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2;
+
+typedef struct {
+  PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER                      Header;
+  PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1               DesignatedVendorSpecificHeader1;
+  PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2               DesignatedVendorSpecificHeader2;
+  UINT8                                                         DesignatedVendorSpecific[1];
+}PCI_EXPRESS_EXTENDED_CAPABILITIES_DESIGNATED_VENDOR_SPECIFIC;
+///@}
+
+#pragma pack()
+
+#endif
diff --git a/MdePkg/Include/IndustryStandard/PciExpress50.h b/MdePkg/Include/IndustryStandard/PciExpress50.h
new file mode 100644
index 000000000000..3765875869eb
--- /dev/null
+++ b/MdePkg/Include/IndustryStandard/PciExpress50.h
@@ -0,0 +1,136 @@
+/** @file
+Support for the PCI Express 5.0 standard.
+
+This header file may not define all structures.  Please extend as required.
+
+Copyright (c) 2020, American Megatrends International LLC. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PCIEXPRESS50_H_
+#define _PCIEXPRESS50_H_
+
+#include <IndustryStandard/PciExpress40.h>
+
+#pragma pack(1)
+
+/// The Physical Layer PCI Express Extended Capability definitions.
+///
+/// Based on section 7.7.6 of PCI Express Base Specification 5.0.
+///@{
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_32_0_ID    0x002A
+#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_32_0_VER1  0x1
+
+// Register offsets from Physical Layer PCI-E Ext Cap Header
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES_OFFSET                         0x04
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL_OFFSET                              0x08
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS_OFFSET                               0x0C
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1_OFFSET               0x10
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2_OFFSET               0x14
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1_OFFSET              0x18
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2_OFFSET              0x1C
+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL_OFFSET            0x20
+
+typedef union {
+  struct {
+    UINT32 EqualizationByPassToHighestRateSupport                  : 1; // bit 0
+    UINT32 NoEqualizationNeededSupport                             : 1; // bit 1
+    UINT32 Reserved1                                               : 6; // Reserved bit 2:7
+    UINT32 ModifiedTSUsageMode0Support                             : 1; // bit 8
+    UINT32 ModifiedTSUsageMode1Support                             : 1; // bit 9
+    UINT32 ModifiedTSUsageMode2Support                             : 1; // bit 10
+    UINT32 ModifiedTSReservedUsageModes                            : 5; // bit 11:15
+    UINT32 Reserved2                                               : 16; // Reserved bit 16:31
+  } Bits;
+  UINT32   Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES;
+
+typedef union {
+  struct {
+    UINT32 EqualizationByPassToHighestRateDisable                  : 1; // bit 0
+    UINT32 NoEqualizationNeededDisable                             : 1; // bit 1
+    UINT32 Reserved1                                               : 6; // Reserved bit 2:7
+    UINT32 ModifiedTSUsageModeSelected                             : 3; // bit 8:10
+    UINT32 Reserved2                                               : 21; // Reserved bit 11:31
+  } Bits;
+  UINT32   Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL;
+
+typedef union {
+  struct {
+    UINT32 EqualizationComplete      : 1; // bit 0
+    UINT32 EqualizationPhase1Success : 1; // bit 1
+    UINT32 EqualizationPhase2Success : 1; // bit 2
+    UINT32 EqualizationPhase3Success : 1; // bit 3
+    UINT32 LinkEqualizationRequest   : 1; // bit 4
+    UINT32 ModifiedTSRcvd            : 1; // bit 5
+    UINT32 RcvdEnhancedLinkControl   : 2; // bit 6:7
+    UINT32 TransmitterPrecodingOn    : 1; // bit 8
+    UINT32 TransmitterPrecodeRequest : 1; // bit 9
+    UINT32 NoEqualizationNeededRcvd  : 1; // bit 10
+    UINT32 Reserved                  : 21; // Reserved bit 11:31
+  } Bits;
+  UINT32   Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS;
+
+typedef union {
+  struct {
+    UINT32 RcvdModifiedTSUsageMode   : 3; // bit 0:2
+    UINT32 RcvdModifiedTSUsageInfo1  : 13; // bit 3:15
+    UINT32 RcvdModifiedTSVendorId    : 16; // bit 16:31
+  } Bits;
+  UINT32   Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1;
+
+typedef union {
+  struct {
+    UINT32 RcvdModifiedTSUsageInfo2     : 24; // bit 0:23
+    UINT32 AltProtocolNegotiationStatus : 2; // bit 24:25
+    UINT32 Reserved                     : 6; // Reserved bit 26:31
+  } Bits;
+  UINT32   Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2;
+
+typedef union {
+  struct {
+    UINT32 TransModifiedTSUsageMode   : 3; // bit 0:2
+    UINT32 TransModifiedTSUsageInfo1  : 13; // bit 3:15
+    UINT32 TransModifiedTSVendorId    : 16; // bit 16:31
+  } Bits;
+  UINT32   Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1;
+
+typedef union {
+  struct {
+    UINT32 TransModifiedTSUsageInfo2    : 24; // bit 0:23
+    UINT32 AltProtocolNegotiationStatus : 2; // bit 24:25
+    UINT32 Reserved                     : 6; // Reserved bit 26:31
+  } Bits;
+  UINT32   Uint32;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2;
+
+typedef union {
+  struct {
+    UINT8 DownstreamPortTransmitterPreset : 4; //bit 0..3
+    UINT8 UpstreamPortTransmitterPreset   : 4; //bit 4..7
+  } Bits;
+  UINT8   Uint8;
+} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL;
+
+typedef struct {
+  PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER                      Header;
+  PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES              Capablities;
+  PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL                   Control;
+  PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS                    Status;
+  PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1    RcvdModifiedTs1Data;
+  PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2    RcvdModifiedTs2Data;
+  PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1   TransModifiedTs1Data;
+  PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2   TransModifiedTs2Data;
+  PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL LaneEqualizationControl[1];
+} PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_32_0;
+///@}
+
+#pragma pack()
+
+#endif
diff --git a/MdePkg/Include/IndustryStandard/PeImage.h b/MdePkg/Include/IndustryStandard/PeImage.h
index 3af3edbd8ec2..15a713ea06e7 100644
--- a/MdePkg/Include/IndustryStandard/PeImage.h
+++ b/MdePkg/Include/IndustryStandard/PeImage.h
@@ -1,21 +1,17 @@
 /** @file
-  EFI image format for PE32, PE32+ and TE. Please note some data structures are 
-  different for PE32 and PE32+. EFI_IMAGE_NT_HEADERS32 is for PE32 and 
-  EFI_IMAGE_NT_HEADERS64 is for PE32+. 
+  EFI image format for PE32, PE32+ and TE. Please note some data structures are
+  different for PE32 and PE32+. EFI_IMAGE_NT_HEADERS32 is for PE32 and
+  EFI_IMAGE_NT_HEADERS64 is for PE32+.
 
-  This file is coded to the Visual Studio, Microsoft Portable Executable and 
+  This file is coded to the Visual Studio, Microsoft Portable Executable and
   Common Object File Format Specification, Revision 8.3 - February 6, 2013.
   This file also includes some definitions in PI Specification, Revision 1.0.
 
-Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
 Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-This program and the accompanying materials                          
-are licensed and made available under the terms and conditions of the BSD License         
-which accompanies this distribution.  The full text of the license may be found at        
-http://opensource.org/licenses/bsd-license.php.                                           
+Portions Copyright (c) 2016 - 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
 
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -40,6 +36,9 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #define IMAGE_FILE_MACHINE_X64             0x8664
 #define IMAGE_FILE_MACHINE_ARMTHUMB_MIXED  0x01c2
 #define IMAGE_FILE_MACHINE_ARM64           0xAA64
+#define IMAGE_FILE_MACHINE_RISCV32         0x5032
+#define IMAGE_FILE_MACHINE_RISCV64         0x5064
+#define IMAGE_FILE_MACHINE_RISCV128        0x5128
 
 //
 // EXE file formats
@@ -98,7 +97,7 @@ typedef struct {
 //
 #define EFI_IMAGE_FILE_RELOCS_STRIPPED      BIT0     ///< 0x0001  Relocation info stripped from file.
 #define EFI_IMAGE_FILE_EXECUTABLE_IMAGE     BIT1     ///< 0x0002  File is executable  (i.e. no unresolved externel references).
-#define EFI_IMAGE_FILE_LINE_NUMS_STRIPPED   BIT2     ///< 0x0004  Line nunbers stripped from file.
+#define EFI_IMAGE_FILE_LINE_NUMS_STRIPPED   BIT2     ///< 0x0004  Line numbers stripped from file.
 #define EFI_IMAGE_FILE_LOCAL_SYMS_STRIPPED  BIT3     ///< 0x0008  Local symbols stripped from file.
 #define EFI_IMAGE_FILE_BYTES_REVERSED_LO    BIT7     ///< 0x0080  Bytes of machine word are reversed.
 #define EFI_IMAGE_FILE_32BIT_MACHINE        BIT8     ///< 0x0100  32 bit word machine.
@@ -134,12 +133,12 @@ typedef struct {
 
 ///
 /// @attention
-/// EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC means PE32 and 
+/// EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC means PE32 and
 /// EFI_IMAGE_OPTIONAL_HEADER32 must be used. The data structures only vary
 /// after NT additional fields.
 ///
 #define EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC 0x10b
-          
+
 ///
 /// Optional Header Standard Fields for PE32.
 ///
@@ -185,7 +184,7 @@ typedef struct {
 
 ///
 /// @attention
-/// EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC means PE32+ and 
+/// EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC means PE32+ and
 /// EFI_IMAGE_OPTIONAL_HEADER64 must be used. The data structures only vary
 /// after NT additional fields.
 ///
@@ -296,7 +295,7 @@ typedef struct {
 /// Size of EFI_IMAGE_SECTION_HEADER.
 ///
 #define EFI_IMAGE_SIZEOF_SECTION_HEADER       40
-         
+
 //
 // Section Flags Values
 //
@@ -304,12 +303,12 @@ typedef struct {
 #define EFI_IMAGE_SCN_CNT_CODE                     BIT5   ///< 0x00000020
 #define EFI_IMAGE_SCN_CNT_INITIALIZED_DATA         BIT6   ///< 0x00000040
 #define EFI_IMAGE_SCN_CNT_UNINITIALIZED_DATA       BIT7   ///< 0x00000080
-                                                   
+
 #define EFI_IMAGE_SCN_LNK_OTHER                    BIT8   ///< 0x00000100  ///< Reserved.
 #define EFI_IMAGE_SCN_LNK_INFO                     BIT9   ///< 0x00000200  ///< Section contains comments or some other type of information.
 #define EFI_IMAGE_SCN_LNK_REMOVE                   BIT11  ///< 0x00000800  ///< Section contents will not become part of image.
 #define EFI_IMAGE_SCN_LNK_COMDAT                   BIT12  ///< 0x00001000
-                                                   
+
 #define EFI_IMAGE_SCN_ALIGN_1BYTES                 BIT20  ///< 0x00100000
 #define EFI_IMAGE_SCN_ALIGN_2BYTES                 BIT21  ///< 0x00200000
 #define EFI_IMAGE_SCN_ALIGN_4BYTES          (BIT20|BIT21) ///< 0x00300000
@@ -317,7 +316,7 @@ typedef struct {
 #define EFI_IMAGE_SCN_ALIGN_16BYTES         (BIT20|BIT22) ///< 0x00500000
 #define EFI_IMAGE_SCN_ALIGN_32BYTES         (BIT21|BIT22) ///< 0x00600000
 #define EFI_IMAGE_SCN_ALIGN_64BYTES   (BIT20|BIT21|BIT22) ///< 0x00700000
-                                              
+
 #define EFI_IMAGE_SCN_MEM_DISCARDABLE              BIT25  ///< 0x02000000
 #define EFI_IMAGE_SCN_MEM_NOT_CACHED               BIT26  ///< 0x04000000
 #define EFI_IMAGE_SCN_MEM_NOT_PAGED                BIT27  ///< 0x08000000
@@ -415,7 +414,7 @@ typedef struct {
 #define EFI_IMAGE_COMDAT_SELECT_SAME_SIZE       3
 #define EFI_IMAGE_COMDAT_SELECT_EXACT_MATCH     4
 #define EFI_IMAGE_COMDAT_SELECT_ASSOCIATIVE     5
-                                       
+
 //
 // the following values only be referred in PeCoff, not defined in PECOFF.
 //
@@ -450,9 +449,9 @@ typedef struct {
 #define EFI_IMAGE_REL_I386_SECREL   0x000B
 #define EFI_IMAGE_REL_I386_REL32    0x0014  ///< PC-relative 32-bit reference to the symbols virtual address.
 
-// 
+//
 // x64 processor relocation types.
-// 
+//
 #define IMAGE_REL_AMD64_ABSOLUTE  0x0000
 #define IMAGE_REL_AMD64_ADDR64    0x0001
 #define IMAGE_REL_AMD64_ADDR32    0x0002
@@ -500,6 +499,13 @@ typedef struct {
 #define EFI_IMAGE_REL_BASED_DIR64           10
 
 ///
+/// Relocation types of RISC-V processor.
+///
+#define EFI_IMAGE_REL_BASED_RISCV_HI20      5
+#define EFI_IMAGE_REL_BASED_RISCV_LOW12I    7
+#define EFI_IMAGE_REL_BASED_RISCV_LOW12S    8
+
+///
 /// Line number format.
 ///
 typedef struct {
diff --git a/MdePkg/Include/IndustryStandard/Sal.h b/MdePkg/Include/IndustryStandard/Sal.h
deleted file mode 100644
index cda4e28bcde1..000000000000
--- a/MdePkg/Include/IndustryStandard/Sal.h
+++ /dev/null
@@ -1,915 +0,0 @@
-/** @file
-  Main SAL API's defined in Intel Itanium Processor Family System Abstraction
-  Layer Specification Revision 3.2 (December 2003)
-
-Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
-
-**/
-
-#ifndef __SAL_API_H__
-#define __SAL_API_H__
-
-///
-/// SAL return status type 
-///
-typedef INTN EFI_SAL_STATUS;
-
-///
-/// Call completed without error. 
-///
-#define EFI_SAL_SUCCESS               ((EFI_SAL_STATUS) 0)
-///
-/// Call completed without error, but some information was lost due to overflow. 
-///
-#define EFI_SAL_OVERFLOW              ((EFI_SAL_STATUS) 1)
-///
-/// Call completed without error; effect a warm boot of the system to complete the update.
-///
-#define EFI_SAL_WARM_BOOT_NEEDED      ((EFI_SAL_STATUS) 2)
-///
-/// More information is available for retrieval. 
-///
-#define EFI_SAL_MORE_RECORDS          ((EFI_SAL_STATUS) 3)
-///
-/// Not implemented.
-///
-#define EFI_SAL_NOT_IMPLEMENTED       ((EFI_SAL_STATUS) - 1)
-///
-/// Invalid Argument.
-///
-#define EFI_SAL_INVALID_ARGUMENT      ((EFI_SAL_STATUS) - 2)
-///
-/// Call completed without error. 
-///
-#define EFI_SAL_ERROR                 ((EFI_SAL_STATUS) - 3)
-///
-/// Virtual address not registered. 
-///
-#define EFI_SAL_VIRTUAL_ADDRESS_ERROR ((EFI_SAL_STATUS) - 4)
-///
-/// No information available. 
-///
-#define EFI_SAL_NO_INFORMATION        ((EFI_SAL_STATUS) - 5)
-///
-/// Scratch buffer required.
-///
-#define EFI_SAL_NOT_ENOUGH_SCRATCH    ((EFI_SAL_STATUS) - 9)
-
-///
-/// Return registers from SAL.
-///
-typedef struct {
-  ///
-  /// SAL return status value in r8.
-  ///
-  EFI_SAL_STATUS  Status;
-  ///
-  /// SAL returned value in r9.
-  ///
-  UINTN           r9;
-  ///
-  /// SAL returned value in r10.
-  ///
-  UINTN           r10;
-  ///
-  /// SAL returned value in r11.
-  ///
-  UINTN           r11;
-} SAL_RETURN_REGS;
-
-/**
-  Prototype of SAL procedures.
-
-  @param  FunctionId         Functional identifier.
-                             The upper 32 bits are ignored and only the lower 32 bits
-                             are used. The following functional identifiers are defined:
-                             0x01XXXXXX - Architected SAL functional group.
-                             0x02XXXXXX to 0x03XXXXXX - OEM SAL functional group. Each OEM is
-                             allowed to use the entire range in the 0x02XXXXXX to 0x03XXXXXX range.
-                             0x04XXXXXX to 0xFFFFFFFF - Reserved.
-  @param  Arg1               The first parameter of the architected/OEM specific SAL functions.
-  @param  Arg2               The second parameter of the architected/OEM specific SAL functions.
-  @param  Arg3               The third parameter passed to the ESAL function based.
-  @param  Arg4               The fourth parameter passed to the ESAL function based.
-  @param  Arg5               The fifth parameter passed to the ESAL function based.
-  @param  Arg6               The sixth parameter passed to the ESAL function.
-  @param  Arg7               The seventh parameter passed to the ESAL function based.
-
-  @return r8                 Return status: positive number indicates successful,
-                             negative number indicates failure.
-          r9                 Other return parameter in r9.
-          r10                Other return parameter in r10.
-          r11                Other return parameter in r11.
-
-**/
-typedef
-SAL_RETURN_REGS
-(EFIAPI *SAL_PROC)(
-  IN UINT64 FunctionId,
-  IN UINT64 Arg1,
-  IN UINT64 Arg2,
-  IN UINT64 Arg3,
-  IN UINT64 Arg4,
-  IN UINT64 Arg5,
-  IN UINT64 Arg6,
-  IN UINT64 Arg7
-  );
-
-//
-// SAL Procedure FunctionId definition
-//
-
-///
-/// Register software code locations with SAL.
-///
-#define EFI_SAL_SET_VECTORS             0x01000000
-///
-/// Return Machine State information obtained by SAL.
-///
-#define EFI_SAL_GET_STATE_INFO          0x01000001
-///
-/// Obtain size of Machine State information.
-///
-#define EFI_SAL_GET_STATE_INFO_SIZE     0x01000002
-///
-/// Clear Machine State information.
-///
-#define EFI_SAL_CLEAR_STATE_INFO        0x01000003
-///
-/// Cause the processor to go into a spin loop within SAL.
-///
-#define EFI_SAL_MC_RENDEZ               0x01000004
-///
-/// Register the machine check interface layer with SAL.
-///
-#define EFI_SAL_MC_SET_PARAMS           0x01000005
-///
-/// Register the physical addresses of locations needed by SAL.
-///
-#define EFI_SAL_REGISTER_PHYSICAL_ADDR  0x01000006
-///
-/// Flush the instruction or data caches.
-///
-#define EFI_SAL_CACHE_FLUSH             0x01000008
-///
-/// Initialize the instruction and data caches.
-///
-#define EFI_SAL_CACHE_INIT              0x01000009
-///
-/// Read from the PCI configuration space.
-///
-#define EFI_SAL_PCI_CONFIG_READ         0x01000010
-///
-/// Write to the PCI configuration space.
-///
-#define EFI_SAL_PCI_CONFIG_WRITE        0x01000011
-///
-/// Return the base frequency of the platform.
-///
-#define EFI_SAL_FREQ_BASE               0x01000012
-///
-/// Returns information on the physical processor mapping within the platform.
-///
-#define EFI_SAL_PHYSICAL_ID_INFO        0x01000013
-///
-/// Update the contents of firmware blocks.
-///
-#define EFI_SAL_UPDATE_PAL              0x01000020
-
-#define EFI_SAL_FUNCTION_ID_MASK        0x0000ffff
-#define EFI_SAL_MAX_SAL_FUNCTION_ID     0x00000021
-
-//
-// SAL Procedure parameter definitions
-// Not much point in using typedefs or enums because all params
-// are UINT64 and the entry point is common
-//
-
-//
-// Parameter of EFI_SAL_SET_VECTORS
-//
-// Vector type
-//
-#define EFI_SAL_SET_MCA_VECTOR          0x0
-#define EFI_SAL_SET_INIT_VECTOR         0x1
-#define EFI_SAL_SET_BOOT_RENDEZ_VECTOR  0x2
-///
-/// The format of a length_cs_n argument.
-///
-typedef struct {
-  UINT64  Length : 32;
-  UINT64  ChecksumValid : 1;
-  UINT64  Reserved1 : 7;
-  UINT64  ByteChecksum : 8;
-  UINT64  Reserved2 : 16;
-} SAL_SET_VECTORS_CS_N;
-
-//
-// Parameter of EFI_SAL_GET_STATE_INFO, EFI_SAL_GET_STATE_INFO_SIZE, and EFI_SAL_CLEAR_STATE_INFO
-// 
-// Type of information
-//
-#define EFI_SAL_MCA_STATE_INFO  0x0
-#define EFI_SAL_INIT_STATE_INFO 0x1
-#define EFI_SAL_CMC_STATE_INFO  0x2
-#define EFI_SAL_CP_STATE_INFO   0x3
-
-//
-// Parameter of EFI_SAL_MC_SET_PARAMS
-//
-// Unsigned 64-bit integer value for the parameter type of the machine check interface
-//
-#define EFI_SAL_MC_SET_RENDEZ_PARAM 0x1
-#define EFI_SAL_MC_SET_WAKEUP_PARAM 0x2
-#define EFI_SAL_MC_SET_CPE_PARAM    0x3
-//
-// Unsigned 64-bit integer value indicating whether interrupt vector or
-// memory address is specified
-//
-#define EFI_SAL_MC_SET_INTR_PARAM   0x1
-#define EFI_SAL_MC_SET_MEM_PARAM    0x2
-
-//
-// Parameter of EFI_SAL_REGISTER_PAL_PHYSICAL_ADDR
-//
-// The encoded value of the entity whose physical address is registered
-//
-#define EFI_SAL_REGISTER_PAL_ADDR 0x0
-
-//
-// Parameter of EFI_SAL_CACHE_FLUSH
-//
-// Unsigned 64-bit integer denoting type of cache flush operation
-//
-#define EFI_SAL_FLUSH_I_CACHE       0x01
-#define EFI_SAL_FLUSH_D_CACHE       0x02
-#define EFI_SAL_FLUSH_BOTH_CACHE    0x03
-#define EFI_SAL_FLUSH_MAKE_COHERENT 0x04
-
-//
-// Parameter of EFI_SAL_PCI_CONFIG_READ and EFI_SAL_PCI_CONFIG_WRITE
-//
-// PCI config size
-//
-#define EFI_SAL_PCI_CONFIG_ONE_BYTE   0x1
-#define EFI_SAL_PCI_CONFIG_TWO_BYTES  0x2
-#define EFI_SAL_PCI_CONFIG_FOUR_BYTES 0x4
-//
-// The type of PCI configuration address
-//
-#define EFI_SAL_PCI_COMPATIBLE_ADDRESS         0x0
-#define EFI_SAL_PCI_EXTENDED_REGISTER_ADDRESS  0x1
-///
-/// The format of PCI Compatible Address.
-///
-typedef struct {
-  UINT64  Register : 8;
-  UINT64  Function : 3;
-  UINT64  Device : 5;
-  UINT64  Bus : 8;
-  UINT64  Segment : 8;
-  UINT64  Reserved : 32;
-} SAL_PCI_ADDRESS;
-///
-/// The format of Extended Register Address.
-///
-typedef struct {
-  UINT64  Register : 8;
-  UINT64  ExtendedRegister : 4;
-  UINT64  Function : 3;
-  UINT64  Device : 5;
-  UINT64  Bus : 8;
-  UINT64  Segment : 16;
-  UINT64  Reserved : 20;
-} SAL_PCI_EXTENDED_REGISTER_ADDRESS;
-
-//
-// Parameter of EFI_SAL_FREQ_BASE
-//
-// Unsigned 64-bit integer specifying the type of clock source
-//
-#define EFI_SAL_CPU_INPUT_FREQ_BASE     0x0
-#define EFI_SAL_PLATFORM_IT_FREQ_BASE   0x1
-#define EFI_SAL_PLATFORM_RTC_FREQ_BASE  0x2
-
-//
-// Parameter and return value of EFI_SAL_UPDATE_PAL
-//
-// Return parameter provides additional information on the
-// failure when the status field contains a value of -3,
-// returned in r9.
-//
-#define EFI_SAL_UPDATE_BAD_PAL_VERSION  ((UINT64) -1)
-#define EFI_SAL_UPDATE_PAL_AUTH_FAIL    ((UINT64) -2)
-#define EFI_SAL_UPDATE_PAL_BAD_TYPE     ((UINT64) -3)
-#define EFI_SAL_UPDATE_PAL_READONLY     ((UINT64) -4)
-#define EFI_SAL_UPDATE_PAL_WRITE_FAIL   ((UINT64) -10)
-#define EFI_SAL_UPDATE_PAL_ERASE_FAIL   ((UINT64) -11)
-#define EFI_SAL_UPDATE_PAL_READ_FAIL    ((UINT64) -12)
-#define EFI_SAL_UPDATE_PAL_CANT_FIT     ((UINT64) -13)
-///
-/// 64-byte header of update data block.
-///
-typedef struct {
-  UINT32  Size;
-  UINT32  MmddyyyyDate;
-  UINT16  Version;
-  UINT8   Type;
-  UINT8   Reserved[5];
-  UINT64  FwVendorId;
-  UINT8   Reserved2[40];
-} SAL_UPDATE_PAL_DATA_BLOCK;
-///
-/// Data structure pointed by the parameter param_buf.
-/// It is a 16-byte aligned data structure in memory with a length of 32 bytes
-/// that describes the new firmware. This information is organized in the form
-/// of a linked list with each element describing one firmware component.
-///
-typedef struct _SAL_UPDATE_PAL_INFO_BLOCK {
-  struct _SAL_UPDATE_PAL_INFO_BLOCK *Next;
-  struct SAL_UPDATE_PAL_DATA_BLOCK  *DataBlock;
-  UINT8                             StoreChecksum;
-  UINT8                             Reserved[15];
-} SAL_UPDATE_PAL_INFO_BLOCK;
-
-///
-/// SAL System Table Definitions.
-///
-#pragma pack(1)
-typedef struct {
-  ///
-  /// The ASCII string representation of "SST_" that confirms the presence of the table. 
-  /// 
-  UINT32  Signature;
-  ///
-  /// The length of the entire table in bytes, starting from offset zero and including the
-  /// header and all entries indicated by the EntryCount field.
-  ///
-  UINT32  Length;
-  ///
-  /// The revision number of the Itanium Processor Family System Abstraction Layer
-  /// Specification supported by the SAL implementation, in binary coded decimal (BCD) format.
-  ///
-  UINT16  SalRevision;
-  ///
-  /// The number of entries in the variable portion of the table.
-  ///
-  UINT16  EntryCount;
-  ///
-  /// A modulo checksum of the entire table and the entries following this table.
-  ///
-  UINT8   CheckSum;
-  ///
-  /// Unused, must be zero.
-  ///
-  UINT8   Reserved[7];
-  ///
-  /// Version Number of the SAL_A firmware implementation in BCD format.
-  ///
-  UINT16  SalAVersion;
-  ///
-  /// Version Number of the SAL_B firmware implementation in BCD format.
-  ///
-  UINT16  SalBVersion;
-  ///
-  /// An ASCII identification string which uniquely identifies the manufacturer
-  /// of the system hardware.
-  ///
-  UINT8   OemId[32];
-  ///
-  /// An ASCII identification string which uniquely identifies a family of
-  /// compatible products from the manufacturer.
-  ///
-  UINT8   ProductId[32];
-  ///
-  /// Unused, must be zero.
-  ///
-  UINT8   Reserved2[8];
-} SAL_SYSTEM_TABLE_HEADER;
-
-#define EFI_SAL_ST_HEADER_SIGNATURE "SST_"
-#define EFI_SAL_REVISION            0x0320
-//
-// SAL System Types
-//
-#define EFI_SAL_ST_ENTRY_POINT        0
-#define EFI_SAL_ST_MEMORY_DESCRIPTOR  1
-#define EFI_SAL_ST_PLATFORM_FEATURES  2
-#define EFI_SAL_ST_TR_USAGE           3
-#define EFI_SAL_ST_PTC                4
-#define EFI_SAL_ST_AP_WAKEUP          5
-
-//
-// SAL System Type Sizes
-//
-#define EFI_SAL_ST_ENTRY_POINT_SIZE        48
-#define EFI_SAL_ST_MEMORY_DESCRIPTOR_SIZE  32
-#define EFI_SAL_ST_PLATFORM_FEATURES_SIZE  16
-#define EFI_SAL_ST_TR_USAGE_SIZE           32
-#define EFI_SAL_ST_PTC_SIZE                16
-#define EFI_SAL_ST_AP_WAKEUP_SIZE          16
-
-///
-/// Format of Entrypoint Descriptor Entry.
-///
-typedef struct {
-  UINT8   Type;         ///< Type here should be 0.
-  UINT8   Reserved[7];
-  UINT64  PalProcEntry;
-  UINT64  SalProcEntry;
-  UINT64  SalGlobalDataPointer;
-  UINT64  Reserved2[2];
-} SAL_ST_ENTRY_POINT_DESCRIPTOR;
-
-///
-/// Format of Platform Features Descriptor Entry.
-///
-typedef struct {
-  UINT8 Type;           ///< Type here should be 2.
-  UINT8 PlatformFeatures;
-  UINT8 Reserved[14];
-} SAL_ST_PLATFORM_FEATURES;
-
-//
-// Value of Platform Feature List
-//
-#define SAL_PLAT_FEAT_BUS_LOCK      0x01
-#define SAL_PLAT_FEAT_PLAT_IPI_HINT 0x02
-#define SAL_PLAT_FEAT_PROC_IPI_HINT 0x04
-
-///
-/// Format of Translation Register Descriptor Entry.
-///
-typedef struct {
-  UINT8   Type;         ///< Type here should be 3.
-  UINT8   TRType;
-  UINT8   TRNumber;
-  UINT8   Reserved[5];
-  UINT64  VirtualAddress;
-  UINT64  EncodedPageSize;
-  UINT64  Reserved1;
-} SAL_ST_TR_DECRIPTOR;
-
-//
-// Type of Translation Register
-//
-#define EFI_SAL_ST_TR_USAGE_INSTRUCTION 00
-#define EFI_SAL_ST_TR_USAGE_DATA        01
-
-///
-/// Definition of Coherence Domain Information.
-///
-typedef struct {
-  UINT64  NumberOfProcessors;
-  UINT64  LocalIDRegister;
-} SAL_COHERENCE_DOMAIN_INFO;
-           
-///
-/// Format of Purge Translation Cache Coherence Domain Entry.
-///
-typedef struct {
-  UINT8                     Type;       ///< Type here should be 4.
-  UINT8                     Reserved[3];
-  UINT32                    NumberOfDomains;
-  SAL_COHERENCE_DOMAIN_INFO *DomainInformation;
-} SAL_ST_CACHE_COHERENCE_DECRIPTOR;
-
-///
-/// Format of Application Processor Wake-Up Descriptor Entry.
-///
-typedef struct {
-  UINT8   Type;                   ///< Type here should be 5.
-  UINT8   WakeUpType;
-  UINT8   Reserved[6];
-  UINT64  ExternalInterruptVector;
-} SAL_ST_AP_WAKEUP_DECRIPTOR;
-
-///
-/// Format of Firmware Interface Table (FIT) Entry.
-///
-typedef struct {
-  UINT64  Address;
-  UINT8   Size[3];
-  UINT8   Reserved;
-  UINT16  Revision;
-  UINT8   Type : 7;
-  UINT8   CheckSumValid : 1;
-  UINT8   CheckSum;
-} EFI_SAL_FIT_ENTRY;
-//
-// FIT Types 
-//
-#define EFI_SAL_FIT_FIT_HEADER_TYPE                0x00
-#define EFI_SAL_FIT_PAL_B_TYPE                     0x01
-//
-// Type from 0x02 to 0x0D is reserved.
-//
-#define EFI_SAL_FIT_PROCESSOR_SPECIFIC_PAL_A_TYPE  0x0E
-#define EFI_SAL_FIT_PAL_A_TYPE                     0x0F
-//
-// OEM-defined type range is from 0x10 to 0x7E.
-// Here we defined the PEI_CORE type as 0x10
-//
-#define EFI_SAL_FIT_PEI_CORE_TYPE                  0x10
-#define EFI_SAL_FIT_UNUSED_TYPE                    0x7F
-
-//
-// FIT Entry
-//
-#define EFI_SAL_FIT_ENTRY_PTR   (0x100000000 - 32)  // 4GB - 24
-#define EFI_SAL_FIT_PALA_ENTRY  (0x100000000 - 48)  // 4GB - 32
-#define EFI_SAL_FIT_PALB_TYPE   01
-
-//
-// Following definitions are for Error Record Structure
-//
-
-///
-/// Format of TimeStamp field in Record Header.
-///
-typedef struct {
-  UINT8 Seconds;
-  UINT8 Minutes;
-  UINT8 Hours;
-  UINT8 Reserved;
-  UINT8 Day;
-  UINT8 Month;
-  UINT8 Year;
-  UINT8 Century;
-} SAL_TIME_STAMP;
-///
-/// Definition of Record Header.
-///
-typedef struct {
-  UINT64          RecordId;
-  UINT16          Revision;
-  UINT8           ErrorSeverity;
-  UINT8           ValidationBits;
-  UINT32          RecordLength;
-  SAL_TIME_STAMP  TimeStamp;
-  UINT8           OemPlatformId[16];
-} SAL_RECORD_HEADER;
-///
-/// Definition of Section Header.
-///
-typedef struct {
-  GUID      Guid;
-  UINT16    Revision;
-  UINT8     ErrorRecoveryInfo;
-  UINT8     Reserved;
-  UINT32    SectionLength;
-} SAL_SEC_HEADER;
-
-///
-/// GUID of Processor Machine Check Errors.
-///
-#define SAL_PROCESSOR_ERROR_RECORD_INFO \
-  { \
-    0xe429faf1, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
-  }
-//
-// Bit masks for valid bits of MOD_ERROR_INFO
-//
-#define CHECK_INFO_VALID_BIT_MASK   0x1
-#define REQUESTOR_ID_VALID_BIT_MASK 0x2
-#define RESPONDER_ID_VALID_BIT_MASK 0x4
-#define TARGER_ID_VALID_BIT_MASK    0x8
-#define PRECISE_IP_VALID_BIT_MASK   0x10
-///
-/// Definition of MOD_ERROR_INFO_STRUCT.
-///
-typedef struct {
-  UINT64  InfoValid : 1;
-  UINT64  ReqValid : 1;
-  UINT64  RespValid : 1;
-  UINT64  TargetValid : 1;
-  UINT64  IpValid : 1;
-  UINT64  Reserved : 59;
-  UINT64  Info;
-  UINT64  Req;
-  UINT64  Resp;
-  UINT64  Target;
-  UINT64  Ip;
-} MOD_ERROR_INFO;
-///
-/// Definition of CPUID_INFO_STRUCT.
-///
-typedef struct {
-  UINT8 CpuidInfo[40];
-  UINT8 Reserved;
-} CPUID_INFO;
-
-typedef struct {
-  UINT64  FrLow;
-  UINT64  FrHigh;
-} FR_STRUCT;
-//
-// Bit masks for PSI_STATIC_STRUCT.ValidFieldBits
-//
-#define MIN_STATE_VALID_BIT_MASK  0x1
-#define BR_VALID_BIT_MASK         0x2
-#define CR_VALID_BIT_MASK         0x4
-#define AR_VALID_BIT_MASK         0x8
-#define RR_VALID_BIT_MASK         0x10
-#define FR_VALID_BIT_MASK         0x20
-///
-/// Definition of PSI_STATIC_STRUCT.
-///
-typedef struct {
-  UINT64    ValidFieldBits;
-  UINT8     MinStateInfo[1024];
-  UINT64    Br[8];
-  UINT64    Cr[128];
-  UINT64    Ar[128];
-  UINT64    Rr[8];
-  FR_STRUCT Fr[128];
-} PSI_STATIC_STRUCT;
-//
-// Bit masks for SAL_PROCESSOR_ERROR_RECORD.ValidationBits
-//
-#define PROC_ERROR_MAP_VALID_BIT_MASK       0x1
-#define PROC_STATE_PARAMETER_VALID_BIT_MASK 0x2
-#define PROC_CR_LID_VALID_BIT_MASK          0x4
-#define PROC_STATIC_STRUCT_VALID_BIT_MASK   0x8
-#define CPU_INFO_VALID_BIT_MASK             0x1000000
-///
-/// Definition of Processor Machine Check Error Record.
-///
-typedef struct {
-  SAL_SEC_HEADER    SectionHeader;
-  UINT64            ValidationBits;
-  UINT64            ProcErrorMap;
-  UINT64            ProcStateParameter;
-  UINT64            ProcCrLid;
-  MOD_ERROR_INFO    CacheError[15];
-  MOD_ERROR_INFO    TlbError[15];
-  MOD_ERROR_INFO    BusError[15];
-  MOD_ERROR_INFO    RegFileCheck[15];
-  MOD_ERROR_INFO    MsCheck[15];
-  CPUID_INFO        CpuInfo;
-  PSI_STATIC_STRUCT PsiValidData;
-} SAL_PROCESSOR_ERROR_RECORD;
-
-///
-/// GUID of Platform Memory Device Error Info.
-///
-#define SAL_MEMORY_ERROR_RECORD_INFO \
-  { \
-    0xe429faf2, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
-  }
-//
-// Bit masks for SAL_MEMORY_ERROR_RECORD.ValidationBits
-//
-#define MEMORY_ERROR_STATUS_VALID_BIT_MASK                0x1
-#define MEMORY_PHYSICAL_ADDRESS_VALID_BIT_MASK            0x2
-#define MEMORY_ADDR_BIT_MASK                              0x4
-#define MEMORY_NODE_VALID_BIT_MASK                        0x8
-#define MEMORY_CARD_VALID_BIT_MASK                        0x10
-#define MEMORY_MODULE_VALID_BIT_MASK                      0x20
-#define MEMORY_BANK_VALID_BIT_MASK                        0x40
-#define MEMORY_DEVICE_VALID_BIT_MASK                      0x80
-#define MEMORY_ROW_VALID_BIT_MASK                         0x100
-#define MEMORY_COLUMN_VALID_BIT_MASK                      0x200
-#define MEMORY_BIT_POSITION_VALID_BIT_MASK                0x400
-#define MEMORY_PLATFORM_REQUESTOR_ID_VALID_BIT_MASK       0x800
-#define MEMORY_PLATFORM_RESPONDER_ID_VALID_BIT_MASK       0x1000
-#define MEMORY_PLATFORM_TARGET_VALID_BIT_MASK             0x2000
-#define MEMORY_PLATFORM_BUS_SPECIFIC_DATA_VALID_BIT_MASK  0x4000
-#define MEMORY_PLATFORM_OEM_ID_VALID_BIT_MASK             0x8000
-#define MEMORY_PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK    0x10000
-///
-/// Definition of Platform Memory Device Error Info Record.
-///
-typedef struct {
-  SAL_SEC_HEADER  SectionHeader;
-  UINT64          ValidationBits;
-  UINT64          MemErrorStatus;
-  UINT64          MemPhysicalAddress;
-  UINT64          MemPhysicalAddressMask;
-  UINT16          MemNode;
-  UINT16          MemCard;
-  UINT16          MemModule;
-  UINT16          MemBank;
-  UINT16          MemDevice;
-  UINT16          MemRow;
-  UINT16          MemColumn;
-  UINT16          MemBitPosition;
-  UINT64          ModRequestorId;
-  UINT64          ModResponderId;
-  UINT64          ModTargetId;
-  UINT64          BusSpecificData;
-  UINT8           MemPlatformOemId[16];
-} SAL_MEMORY_ERROR_RECORD;
-
-///
-/// GUID of Platform PCI Bus Error Info.
-///
-#define SAL_PCI_BUS_ERROR_RECORD_INFO \
-  { \
-    0xe429faf4, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
-  }
-//
-// Bit masks for SAL_PCI_BUS_ERROR_RECORD.ValidationBits
-//
-#define PCI_BUS_ERROR_STATUS_VALID_BIT_MASK     0x1
-#define PCI_BUS_ERROR_TYPE_VALID_BIT_MASK       0x2
-#define PCI_BUS_ID_VALID_BIT_MASK               0x4
-#define PCI_BUS_ADDRESS_VALID_BIT_MASK          0x8
-#define PCI_BUS_DATA_VALID_BIT_MASK             0x10
-#define PCI_BUS_CMD_VALID_BIT_MASK              0x20
-#define PCI_BUS_REQUESTOR_ID_VALID_BIT_MASK     0x40
-#define PCI_BUS_RESPONDER_ID_VALID_BIT_MASK     0x80
-#define PCI_BUS_TARGET_VALID_BIT_MASK           0x100
-#define PCI_BUS_OEM_ID_VALID_BIT_MASK           0x200
-#define PCI_BUS_OEM_DATA_STRUCT_VALID_BIT_MASK  0x400
-
-///
-/// Designated PCI Bus identifier.
-///
-typedef struct {
-  UINT8 BusNumber;
-  UINT8 SegmentNumber;
-} PCI_BUS_ID;
-
-///
-/// Definition of Platform PCI Bus Error Info Record.
-///
-typedef struct {
-  SAL_SEC_HEADER  SectionHeader;
-  UINT64          ValidationBits;
-  UINT64          PciBusErrorStatus;
-  UINT16          PciBusErrorType;
-  PCI_BUS_ID      PciBusId;
-  UINT32          Reserved;
-  UINT64          PciBusAddress;
-  UINT64          PciBusData;
-  UINT64          PciBusCommand;
-  UINT64          PciBusRequestorId;
-  UINT64          PciBusResponderId;
-  UINT64          PciBusTargetId;
-  UINT8           PciBusOemId[16];
-} SAL_PCI_BUS_ERROR_RECORD;
-
-///
-/// GUID of Platform PCI Component Error Info.
-///
-#define SAL_PCI_COMP_ERROR_RECORD_INFO \
-  { \
-    0xe429faf6, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
-  }
-//
-// Bit masks for SAL_PCI_COMPONENT_ERROR_RECORD.ValidationBits
-//
-#define PCI_COMP_ERROR_STATUS_VALID_BIT_MASK    0x1
-#define PCI_COMP_INFO_VALID_BIT_MASK            0x2
-#define PCI_COMP_MEM_NUM_VALID_BIT_MASK         0x4
-#define PCI_COMP_IO_NUM_VALID_BIT_MASK          0x8
-#define PCI_COMP_REG_DATA_PAIR_VALID_BIT_MASK   0x10
-#define PCI_COMP_OEM_DATA_STRUCT_VALID_BIT_MASK 0x20
-///
-/// Format of PCI Component Information to identify the device.
-///
-typedef struct {
-  UINT16  VendorId;
-  UINT16  DeviceId;
-  UINT8   ClassCode[3];
-  UINT8   FunctionNumber;
-  UINT8   DeviceNumber;
-  UINT8   BusNumber;
-  UINT8   SegmentNumber;
-  UINT8   Reserved[5];
-} PCI_COMP_INFO;
-///
-/// Definition of Platform PCI Component Error Info.
-///
-typedef struct {
-  SAL_SEC_HEADER  SectionHeader;
-  UINT64          ValidationBits;
-  UINT64          PciComponentErrorStatus;
-  PCI_COMP_INFO   PciComponentInfo;
-  UINT32          PciComponentMemNum;
-  UINT32          PciComponentIoNum;
-  UINT8           PciBusOemId[16];
-} SAL_PCI_COMPONENT_ERROR_RECORD;
-
-///
-/// Platform SEL Device Error Info.
-///
-#define SAL_SEL_DEVICE_ERROR_RECORD_INFO \
-  { \
-    0xe429faf3, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
-  }
-//
-// Bit masks for SAL_SEL_DEVICE_ERROR_RECORD.ValidationBits
-//
-#define SEL_RECORD_ID_VALID_BIT_MASK      0x1;
-#define SEL_RECORD_TYPE_VALID_BIT_MASK    0x2;
-#define SEL_GENERATOR_ID_VALID_BIT_MASK   0x4;
-#define SEL_EVM_REV_VALID_BIT_MASK        0x8;
-#define SEL_SENSOR_TYPE_VALID_BIT_MASK    0x10;
-#define SEL_SENSOR_NUM_VALID_BIT_MASK     0x20;
-#define SEL_EVENT_DIR_TYPE_VALID_BIT_MASK 0x40;
-#define SEL_EVENT_DATA1_VALID_BIT_MASK    0x80;
-#define SEL_EVENT_DATA2_VALID_BIT_MASK    0x100;
-#define SEL_EVENT_DATA3_VALID_BIT_MASK    0x200;
-///
-/// Definition of Platform SEL Device Error Info Record.
-///
-typedef struct {
-  SAL_SEC_HEADER  SectionHeader;
-  UINT64          ValidationBits;
-  UINT16          SelRecordId;
-  UINT8           SelRecordType;
-  UINT32          TimeStamp;
-  UINT16          GeneratorId;
-  UINT8           EvmRevision;
-  UINT8           SensorType;
-  UINT8           SensorNum;
-  UINT8           EventDirType;
-  UINT8           Data1;
-  UINT8           Data2;
-  UINT8           Data3;
-} SAL_SEL_DEVICE_ERROR_RECORD;
-
-///
-/// GUID of Platform SMBIOS Device Error Info.
-///
-#define SAL_SMBIOS_ERROR_RECORD_INFO \
-  { \
-    0xe429faf5, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
-  }
-//
-// Bit masks for SAL_SMBIOS_DEVICE_ERROR_RECORD.ValidationBits
-//
-#define SMBIOS_EVENT_TYPE_VALID_BIT_MASK  0x1
-#define SMBIOS_LENGTH_VALID_BIT_MASK      0x2
-#define SMBIOS_TIME_STAMP_VALID_BIT_MASK  0x4
-#define SMBIOS_DATA_VALID_BIT_MASK        0x8
-///
-/// Definition of Platform SMBIOS Device Error Info Record.
-///
-typedef struct {
-  SAL_SEC_HEADER  SectionHeader;
-  UINT64          ValidationBits;
-  UINT8           SmbiosEventType;
-  UINT8           SmbiosLength;
-  UINT8           SmbiosBcdTimeStamp[6];
-} SAL_SMBIOS_DEVICE_ERROR_RECORD;
-
-///
-/// GUID of Platform Specific Error Info.
-///
-#define SAL_PLATFORM_ERROR_RECORD_INFO \
-  { \
-    0xe429faf7, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
-  }
-//
-// Bit masks for SAL_PLATFORM_SPECIFIC_ERROR_RECORD.ValidationBits
-//
-#define PLATFORM_ERROR_STATUS_VALID_BIT_MASK    0x1
-#define PLATFORM_REQUESTOR_ID_VALID_BIT_MASK    0x2
-#define PLATFORM_RESPONDER_ID_VALID_BIT_MASK    0x4
-#define PLATFORM_TARGET_VALID_BIT_MASK          0x8
-#define PLATFORM_SPECIFIC_DATA_VALID_BIT_MASK   0x10
-#define PLATFORM_OEM_ID_VALID_BIT_MASK          0x20
-#define PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x40
-#define PLATFORM_OEM_DEVICE_PATH_VALID_BIT_MASK 0x80
-///
-/// Definition of Platform Specific Error Info Record.
-///
-typedef struct {
-  SAL_SEC_HEADER  SectionHeader;
-  UINT64          ValidationBits;
-  UINT64          PlatformErrorStatus;
-  UINT64          PlatformRequestorId;
-  UINT64          PlatformResponderId;
-  UINT64          PlatformTargetId;
-  UINT64          PlatformBusSpecificData;
-  UINT8           OemComponentId[16];
-} SAL_PLATFORM_SPECIFIC_ERROR_RECORD;
-
-///
-/// Union of all the possible SAL Error Record Types.
-///
-typedef union {
-  SAL_RECORD_HEADER                   *RecordHeader;
-  SAL_PROCESSOR_ERROR_RECORD          *SalProcessorRecord;
-  SAL_PCI_BUS_ERROR_RECORD            *SalPciBusRecord;
-  SAL_PCI_COMPONENT_ERROR_RECORD      *SalPciComponentRecord;
-  SAL_SEL_DEVICE_ERROR_RECORD         *ImpiRecord;
-  SAL_SMBIOS_DEVICE_ERROR_RECORD      *SmbiosRecord;
-  SAL_PLATFORM_SPECIFIC_ERROR_RECORD  *PlatformRecord;
-  SAL_MEMORY_ERROR_RECORD             *MemoryRecord;
-  UINT8                               *Raw;
-} SAL_ERROR_RECORDS_POINTERS;
-
-#pragma pack()
-
-#endif
diff --git a/MdePkg/Include/IndustryStandard/Scsi.h b/MdePkg/Include/IndustryStandard/Scsi.h
index 6de1cfd978e7..f49c55b036e2 100644
--- a/MdePkg/Include/IndustryStandard/Scsi.h
+++ b/MdePkg/Include/IndustryStandard/Scsi.h
@@ -1,14 +1,8 @@
 /** @file
   Support for SCSI-2 standard
 
-  Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -160,7 +154,7 @@
 #define EFI_SCSI_OP_SEND_VOL_TAG      0xb6
 
 //
-// Additional commands for Communition Devices
+// Additional commands for Communication Devices
 //
 #define EFI_SCSI_OP_GET_MESSAGE6    0x08
 #define EFI_SCSI_OP_GET_MESSAGE10   0x28
@@ -170,30 +164,50 @@
 #define EFI_SCSI_OP_SEND_MESSAGE12  0xaa
 
 //
+// Additional commands for Secure Transactions
+//
+#define EFI_SCSI_OP_SECURITY_PROTOCOL_IN  0xa2
+#define EFI_SCSI_OP_SECURITY_PROTOCOL_OUT 0xb5
+
+//
 // SCSI Data Transfer Direction
 //
 #define EFI_SCSI_DATA_IN  0
 #define EFI_SCSI_DATA_OUT 1
 
 //
-// Peripheral Device Type Definitions
+// SCSI Block Command Cache Control Parameters
 //
-#define EFI_SCSI_TYPE_DISK          0x00  ///< Direct-access device (e.g. magnetic disk)
-#define EFI_SCSI_TYPE_TAPE          0x01  ///< Sequential-access device (e.g. magnetic tape)
-#define EFI_SCSI_TYPE_PRINTER       0x02  ///< Printer device
-#define EFI_SCSI_TYPE_PROCESSOR     0x03  ///< Processor device
-#define EFI_SCSI_TYPE_WORM          0x04  ///< Write-once device (e.g. some optical disks)
-#define EFI_SCSI_TYPE_CDROM         0x05  ///< CD-ROM device
-#define EFI_SCSI_TYPE_SCANNER       0x06  ///< Scanner device
-#define EFI_SCSI_TYPE_OPTICAL       0x07  ///< Optical memory device (e.g. some optical disks)
-#define EFI_SCSI_TYPE_MEDIUMCHANGER 0x08  ///< Medium changer device (e.g. jukeboxes)
-#define EFI_SCSI_TYPE_COMMUNICATION 0x09  ///< Communications device
-#define EFI_SCSI_TYPE_ASCIT8_1      0x0A  ///< Defined by ASC IT8 (Graphic arts pre-press devices)
-#define EFI_SCSI_TYPE_ASCIT8_2      0x0B  ///< Defined by ASC IT8 (Graphic arts pre-press devices)
+#define EFI_SCSI_BLOCK_FUA  BIT3  ///< Force Unit Access
+#define EFI_SCSI_BLOCK_DPO  BIT4  ///< Disable Page Out
+
 //
-// 0Ch - 1Eh are reserved
+// Peripheral Device Type Definitions
 //
-#define EFI_SCSI_TYPE_UNKNOWN       0x1F  ///< Unknown or no device type
+#define EFI_SCSI_TYPE_DISK            0x00  ///< Direct-access device (e.g. magnetic disk)
+#define EFI_SCSI_TYPE_TAPE            0x01  ///< Sequential-access device (e.g. magnetic tape)
+#define EFI_SCSI_TYPE_PRINTER         0x02  ///< Printer device
+#define EFI_SCSI_TYPE_PROCESSOR       0x03  ///< Processor device
+#define EFI_SCSI_TYPE_WORM            0x04  ///< Write-once device (e.g. some optical disks)
+#define EFI_SCSI_TYPE_CDROM           0x05  ///< CD/DVD device
+#define EFI_SCSI_TYPE_SCANNER         0x06  ///< Scanner device (obsolete)
+#define EFI_SCSI_TYPE_OPTICAL         0x07  ///< Optical memory device (e.g. some optical disks)
+#define EFI_SCSI_TYPE_MEDIUMCHANGER   0x08  ///< Medium changer device (e.g. jukeboxes)
+#define EFI_SCSI_TYPE_COMMUNICATION   0x09  ///< Communications device (obsolete)
+#define EFI_SCSI_TYPE_ASCIT8_1        0x0A  ///< Defined by ASC IT8 (Graphic arts pre-press devices)
+#define EFI_SCSI_TYPE_ASCIT8_2        0x0B  ///< Defined by ASC IT8 (Graphic arts pre-press devices)
+#define EFI_SCSI_TYPE_RAID            0x0C  ///< Storage array controller device (e.g., RAID)
+#define EFI_SCSI_TYPE_SES             0x0D  ///< Enclosure services device
+#define EFI_SCSI_TYPE_RBC             0x0E  ///< Simplified direct-access device (e.g., magnetic disk)
+#define EFI_SCSI_TYPE_OCRW            0x0F  ///< Optical card reader/writer device
+#define EFI_SCSI_TYPE_BRIDGE          0x10  ///< Bridge Controller Commands
+#define EFI_SCSI_TYPE_OSD             0x11  ///< Object-based Storage Device
+#define EFI_SCSI_TYPE_AUTOMATION      0x12  ///< Automation/Drive Interface
+#define EFI_SCSI_TYPE_SECURITYMANAGER 0x13  ///< Security manager device
+#define EFI_SCSI_TYPE_RESERVED_LOW    0x14  ///< Reserved (low)
+#define EFI_SCSI_TYPE_RESERVED_HIGH   0x1D  ///< Reserved (high)
+#define EFI_SCSI_TYPE_WLUN            0x1E  ///< Well known logical unit
+#define EFI_SCSI_TYPE_UNKNOWN         0x1F  ///< Unknown or no device type
 
 //
 // Page Codes for INQUIRY command
@@ -346,9 +360,9 @@ typedef struct {
   UINT8 BlockSize0;
   UINT8 Protection;
   UINT8 LogicPerPhysical;
-  UINT8 LowestAlignLogic2;  
-  UINT8 LowestAlignLogic1;    
-  UINT8 Reserved[16];  
+  UINT8 LowestAlignLogic2;
+  UINT8 LowestAlignLogic1;
+  UINT8 Reserved[16];
 } EFI_SCSI_DISK_CAPACITY_DATA16;
 
 typedef struct {
diff --git a/MdePkg/Include/IndustryStandard/Sd.h b/MdePkg/Include/IndustryStandard/Sd.h
index 693dfcf6dcfb..415aaf893d63 100644
--- a/MdePkg/Include/IndustryStandard/Sd.h
+++ b/MdePkg/Include/IndustryStandard/Sd.h
@@ -5,13 +5,7 @@
   Specification Version 4.10 spec.
 
   Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/IndustryStandard/SdramSpd.h b/MdePkg/Include/IndustryStandard/SdramSpd.h
index 0a4d8943c001..30958588a0f8 100644
--- a/MdePkg/Include/IndustryStandard/SdramSpd.h
+++ b/MdePkg/Include/IndustryStandard/SdramSpd.h
@@ -2,13 +2,7 @@
   This file contains definitions for the SPD fields on an SDRAM.
 
   Copyright (c) 2007 - 2016, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
 #ifndef _SDRAM_SPD_H_
diff --git a/MdePkg/Include/IndustryStandard/SdramSpdDdr3.h b/MdePkg/Include/IndustryStandard/SdramSpdDdr3.h
index 4bcf706616f6..ae4a771fafcc 100644
--- a/MdePkg/Include/IndustryStandard/SdramSpdDdr3.h
+++ b/MdePkg/Include/IndustryStandard/SdramSpdDdr3.h
@@ -2,13 +2,7 @@
   This file contains definitions for SPD DDR3.
 
   Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
     - Serial Presence Detect (SPD) for DDR3 SDRAM Modules Document Release 6
diff --git a/MdePkg/Include/IndustryStandard/SdramSpdDdr4.h b/MdePkg/Include/IndustryStandard/SdramSpdDdr4.h
index d6bc76f6cf8d..2eeb95ba2ab7 100644
--- a/MdePkg/Include/IndustryStandard/SdramSpdDdr4.h
+++ b/MdePkg/Include/IndustryStandard/SdramSpdDdr4.h
@@ -2,13 +2,7 @@
   This file contains definitions for SPD DDR4.
 
   Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
     - Serial Presence Detect (SPD) for DDR4 SDRAM Modules Document Release 4
diff --git a/MdePkg/Include/IndustryStandard/SdramSpdLpDdr.h b/MdePkg/Include/IndustryStandard/SdramSpdLpDdr.h
index 1f2302b42423..4cc9241afd9b 100644
--- a/MdePkg/Include/IndustryStandard/SdramSpdLpDdr.h
+++ b/MdePkg/Include/IndustryStandard/SdramSpdLpDdr.h
@@ -2,13 +2,7 @@
   This file contains definitions for SPD LPDDR.
 
   Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
     - Serial Presence Detect (SPD) for LPDDR3 and LPDDR4 SDRAM Modules Document Release 2
diff --git a/MdePkg/Include/IndustryStandard/SerialPortConsoleRedirectionTable.h b/MdePkg/Include/IndustryStandard/SerialPortConsoleRedirectionTable.h
index e3fe03e3199b..37f528e6ae65 100644
--- a/MdePkg/Include/IndustryStandard/SerialPortConsoleRedirectionTable.h
+++ b/MdePkg/Include/IndustryStandard/SerialPortConsoleRedirectionTable.h
@@ -1,17 +1,11 @@
 /** @file
   ACPI Serial Port Console Redirection Table as defined by Microsoft in
   http://www.microsoft.com/whdc/system/platform/server/spcr.mspx
-    
-  Copyright (c) 2007 - 2015, Intel Corporation. All rights reserved.<BR>
+
+  Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
   (C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>
   Copyright (c) 2014 - 2016, ARM Limited. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
 #ifndef _SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_H_
@@ -96,6 +90,16 @@ typedef struct {
 ///
 #define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_SBSA_GENERIC_UART     0x0e
 
+///
+/// ARM DCC
+///
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_DCC                       0x0f
+
+///
+/// BCM2835 UART
+///
+#define EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_BCM2835_UART              0x10
+
 //
 // Interrupt Type
 //
diff --git a/MdePkg/Include/IndustryStandard/ServiceProcessorManagementInterfaceTable.h b/MdePkg/Include/IndustryStandard/ServiceProcessorManagementInterfaceTable.h
new file mode 100644
index 000000000000..2006e12473fd
--- /dev/null
+++ b/MdePkg/Include/IndustryStandard/ServiceProcessorManagementInterfaceTable.h
@@ -0,0 +1,98 @@
+/** @file
+  Service Processor Management Interface (SPMI) ACPI table definition from
+  Intelligent Platform Management Interface Specification Second Generation.
+
+  Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+    - Intelligent Platform Management Interface Specification Second Generation
+      v2.0 Revision 1.1, Dated October 2013.
+      https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/ipmi-intelligent-platform-mgt-interface-spec-2nd-gen-v2-0-spec-update.pdf
+**/
+#ifndef _SERVICE_PROCESSOR_MANAGEMENT_INTERFACE_TABLE_H_
+#define _SERVICE_PROCESSOR_MANAGEMENT_INTERFACE_TABLE_H_
+
+#include <IndustryStandard/Acpi.h>
+
+#pragma pack(1)
+
+///
+/// Definition for the device identification information used by the Service
+/// Processor Management Interface Description Table
+///
+typedef union {
+  ///
+  /// For PCI IPMI device
+  ///
+  struct {
+    UINT8                                 SegmentGroup;
+    UINT8                                 Bus;
+    UINT8                                 Device;
+    UINT8                                 Function;
+  } Pci;
+  ///
+  /// For non-PCI IPMI device, the ACPI _UID value of the device
+  ///
+  UINT32                                  Uid;
+} EFI_ACPI_SERVICE_PROCESSOR_MANAGEMENT_INTERFACE_TABLE_DEVICE_ID;
+
+
+///
+/// Definition for Service Processor Management Interface Description Table
+///
+typedef struct {
+  EFI_ACPI_DESCRIPTION_HEADER               Header;
+  ///
+  /// Indicates the type of IPMI interface.
+  ///
+  UINT8                                     InterfaceType;
+  ///
+  /// This field must always be 01h to be compatible with any software that
+  /// implements previous versions of this spec.
+  ///
+  UINT8                                     Reserved1;
+  ///
+  /// Identifies the IPMI specification revision, in BCD format.
+  ///
+  UINT16                                    SpecificationRevision;
+  ///
+  /// Interrupt type(s) used by the interface.
+  ///
+  UINT8                                     InterruptType;
+  ///
+  /// The bit assignment of the SCI interrupt within the GPEx_STS register of a
+  /// GPE described if the FADT that the interface triggers.
+  ///
+  UINT8                                     Gpe;
+  ///
+  /// Reserved, must be 00h.
+  ///
+  UINT8                                     Reserved2;
+  ///
+  /// PCI Device Flag.
+  ///
+  UINT8                                     PciDeviceFlag;
+  ///
+  /// The I/O APIC or I/O SAPIC Global System Interrupt used by the interface.
+  ///
+  UINT32                                    GlobalSystemInterrupt;
+  ///
+  /// The base address of the interface register set described using the
+  /// Generic Address Structure (GAS, See [ACPI 2.0] for the definition).
+  ///
+  EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE    BaseAddress;
+  ///
+  /// Device identification information.
+  ///
+  EFI_ACPI_SERVICE_PROCESSOR_MANAGEMENT_INTERFACE_TABLE_DEVICE_ID    DeviceId;
+  ///
+  /// This field must always be null (0x00) to be compatible with any software
+  /// that implements previous versions of this spec.
+  ///
+  UINT8                                     Reserved3;
+} EFI_ACPI_SERVICE_PROCESSOR_MANAGEMENT_INTERFACE_TABLE;
+
+#pragma pack()
+
+#endif
diff --git a/MdePkg/Include/IndustryStandard/SmBios.h b/MdePkg/Include/IndustryStandard/SmBios.h
index 8548f62261ed..c04df502a462 100644
--- a/MdePkg/Include/IndustryStandard/SmBios.h
+++ b/MdePkg/Include/IndustryStandard/SmBios.h
@@ -1,15 +1,10 @@
 /** @file
-  Industry Standard Definitions of SMBIOS Table Specification v3.1.0.
+  Industry Standard Definitions of SMBIOS Table Specification v3.3.0.
 
-Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
 (C) Copyright 2015-2017 Hewlett Packard Enterprise Development LP<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+(C) Copyright 2015 - 2019 Hewlett Packard Enterprise Development LP<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -52,7 +47,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #define SMBIOS_3_0_TABLE_MAX_LENGTH 0xFFFFFFFF
 
 //
-// SMBIOS type macros which is according to SMBIOS 2.7 specification.
+// SMBIOS type macros which is according to SMBIOS 3.3.0 specification.
 //
 #define SMBIOS_TYPE_BIOS_INFORMATION                     0
 #define SMBIOS_TYPE_SYSTEM_INFORMATION                   1
@@ -98,13 +93,14 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #define SMBIOS_TYPE_ONBOARD_DEVICES_EXTENDED_INFORMATION 41
 #define SMBIOS_TYPE_MANAGEMENT_CONTROLLER_HOST_INTERFACE 42
 #define SMBIOS_TYPE_TPM_DEVICE                           43
+#define SMBIOS_TYPE_PROCESSOR_ADDITIONAL_INFORMATION     44
 
 ///
 /// Inactive type is added from SMBIOS 2.2. Reference SMBIOS 2.6, chapter 3.3.43.
-/// Upper-level software that interprets the SMBIOS structure-table should bypass an 
+/// Upper-level software that interprets the SMBIOS structure-table should bypass an
 /// Inactive structure just like a structure type that the software does not recognize.
 ///
-#define SMBIOS_TYPE_INACTIVE         0x007E    
+#define SMBIOS_TYPE_INACTIVE         0x007E
 
 ///
 /// End-of-table type is added from SMBIOS 2.2. Reference SMBIOS 2.6, chapter 3.3.44.
@@ -117,7 +113,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
 ///
 /// Types 0 through 127 (7Fh) are reserved for and defined by this
-/// specification. Types 128 through 256 (80h to FFh) are available for system- and OEM-specific information.  
+/// specification. Types 128 through 256 (80h to FFh) are available for system- and OEM-specific information.
 ///
 typedef UINT8  SMBIOS_TYPE;
 
@@ -225,8 +221,8 @@ typedef struct {
   UINT32  PrinterIsSupported                :1;
   UINT32  CgaMonoIsSupported                :1;
   UINT32  NecPc98                           :1;
-  UINT32  ReservedForVendor                 :32; ///< Bits 32-63. Bits 32-47 reserved for BIOS vendor 
-                                                 ///< and bits 48-63 reserved for System Vendor. 
+  UINT32  ReservedForVendor                 :32; ///< Bits 32-63. Bits 32-47 reserved for BIOS vendor
+                                                 ///< and bits 48-63 reserved for System Vendor.
 } MISC_BIOS_CHARACTERISTICS;
 
 ///
@@ -300,7 +296,7 @@ typedef struct {
 ///
 ///  System Wake-up Type.
 ///
-typedef enum {  
+typedef enum {
   SystemWakeupTypeReserved         = 0x00,
   SystemWakeupTypeOther            = 0x01,
   SystemWakeupTypeUnknown          = 0x02,
@@ -314,10 +310,10 @@ typedef enum {
 
 ///
 /// System Information (Type 1).
-/// 
-/// The information in this structure defines attributes of the overall system and is 
+///
+/// The information in this structure defines attributes of the overall system and is
 /// intended to be associated with the Component ID group of the system's MIF.
-/// An SMBIOS implementation is associated with a single system instance and contains 
+/// An SMBIOS implementation is associated with a single system instance and contains
 /// one and only one System Information (Type 1) structure.
 ///
 typedef struct {
@@ -333,7 +329,7 @@ typedef struct {
 } SMBIOS_TABLE_TYPE1;
 
 ///
-///  Base Board - Feature Flags. 
+///  Base Board - Feature Flags.
 ///
 typedef struct {
   UINT8  Motherboard           :1;
@@ -347,7 +343,7 @@ typedef struct {
 ///
 ///  Base Board - Board Type.
 ///
-typedef enum {  
+typedef enum {
   BaseBoardTypeUnknown                  = 0x1,
   BaseBoardTypeOther                    = 0x2,
   BaseBoardTypeServerBlade              = 0x3,
@@ -366,7 +362,7 @@ typedef enum {
 ///
 /// Base Board (or Module) Information (Type 2).
 ///
-/// The information in this structure defines attributes of a system baseboard - 
+/// The information in this structure defines attributes of a system baseboard -
 /// for example a motherboard, planar, or server blade or other standard system module.
 ///
 typedef struct {
@@ -387,7 +383,7 @@ typedef struct {
 ///
 /// System Enclosure or Chassis Types
 ///
-typedef enum {  
+typedef enum {
   MiscChassisTypeOther                = 0x01,
   MiscChassisTypeUnknown              = 0x02,
   MiscChassisTypeDeskTop              = 0x03,
@@ -429,7 +425,7 @@ typedef enum {
 ///
 /// System Enclosure or Chassis States .
 ///
-typedef enum {  
+typedef enum {
   ChassisStateOther           = 0x01,
   ChassisStateUnknown         = 0x02,
   ChassisStateSafe            = 0x03,
@@ -441,7 +437,7 @@ typedef enum {
 ///
 /// System Enclosure or Chassis Security Status.
 ///
-typedef enum {  
+typedef enum {
   ChassisSecurityStatusOther                          = 0x01,
   ChassisSecurityStatusUnknown                        = 0x02,
   ChassisSecurityStatusNone                           = 0x03,
@@ -462,11 +458,11 @@ typedef struct {
 ///
 /// System Enclosure or Chassis (Type 3).
 ///
-/// The information in this structure defines attributes of the system's mechanical enclosure(s).  
-/// For example, if a system included a separate enclosure for its peripheral devices, 
+/// The information in this structure defines attributes of the system's mechanical enclosure(s).
+/// For example, if a system included a separate enclosure for its peripheral devices,
 /// two structures would be returned: one for the main, system enclosure and the second for
 /// the peripheral device enclosure.  The additions to this structure in v2.1 of this specification
-/// support the population of the CIM_Chassis class. 
+/// support the population of the CIM_Chassis class.
 ///
 typedef struct {
   SMBIOS_STRUCTURE            Hdr;
@@ -514,29 +510,29 @@ typedef enum {
 /// Processor Information - Processor Family.
 ///
 typedef enum {
-  ProcessorFamilyOther                  = 0x01, 
+  ProcessorFamilyOther                  = 0x01,
   ProcessorFamilyUnknown                = 0x02,
-  ProcessorFamily8086                   = 0x03, 
+  ProcessorFamily8086                   = 0x03,
   ProcessorFamily80286                  = 0x04,
-  ProcessorFamilyIntel386               = 0x05, 
+  ProcessorFamilyIntel386               = 0x05,
   ProcessorFamilyIntel486               = 0x06,
   ProcessorFamily8087                   = 0x07,
   ProcessorFamily80287                  = 0x08,
-  ProcessorFamily80387                  = 0x09, 
+  ProcessorFamily80387                  = 0x09,
   ProcessorFamily80487                  = 0x0A,
-  ProcessorFamilyPentium                = 0x0B, 
+  ProcessorFamilyPentium                = 0x0B,
   ProcessorFamilyPentiumPro             = 0x0C,
   ProcessorFamilyPentiumII              = 0x0D,
   ProcessorFamilyPentiumMMX             = 0x0E,
   ProcessorFamilyCeleron                = 0x0F,
   ProcessorFamilyPentiumIIXeon          = 0x10,
-  ProcessorFamilyPentiumIII             = 0x11, 
+  ProcessorFamilyPentiumIII             = 0x11,
   ProcessorFamilyM1                     = 0x12,
   ProcessorFamilyM2                     = 0x13,
   ProcessorFamilyIntelCeleronM          = 0x14,
   ProcessorFamilyIntelPentium4Ht        = 0x15,
   ProcessorFamilyAmdDuron               = 0x18,
-  ProcessorFamilyK5                     = 0x19, 
+  ProcessorFamilyK5                     = 0x19,
   ProcessorFamilyK6                     = 0x1A,
   ProcessorFamilyK6_2                   = 0x1B,
   ProcessorFamilyK6_3                   = 0x1C,
@@ -630,7 +626,7 @@ typedef enum {
   ProcessorFamilyAmdPhenomFxQuadCore    = 0x8C,
   ProcessorFamilyAmdPhenomX4QuadCore    = 0x8D,
   ProcessorFamilyAmdPhenomX2DualCore    = 0x8E,
-  ProcessorFamilyAmdAthlonX2DualCore    = 0x8F,  
+  ProcessorFamilyAmdAthlonX2DualCore    = 0x8F,
   ProcessorFamilyPARISC                 = 0x90,
   ProcessorFamilyPaRisc8500             = 0x91,
   ProcessorFamilyPaRisc8000             = 0x92,
@@ -677,7 +673,7 @@ typedef enum {
   ProcessorFamilyIntelCore2DuoMobile    = 0xC4,
   ProcessorFamilyIntelCore2SoloMobile   = 0xC5,
   ProcessorFamilyIntelCoreI7            = 0xC6,
-  ProcessorFamilyDualCoreIntelCeleron   = 0xC7,  
+  ProcessorFamilyDualCoreIntelCeleron   = 0xC7,
   ProcessorFamilyIBM390                 = 0xC8,
   ProcessorFamilyG4                     = 0xC9,
   ProcessorFamilyG5                     = 0xCA,
@@ -685,6 +681,7 @@ typedef enum {
   ProcessorFamilyzArchitecture          = 0xCC,
   ProcessorFamilyIntelCoreI5            = 0xCD,
   ProcessorFamilyIntelCoreI3            = 0xCE,
+  ProcessorFamilyIntelCoreI9            = 0xCF,
   ProcessorFamilyViaC7M                 = 0xD2,
   ProcessorFamilyViaC7D                 = 0xD3,
   ProcessorFamilyViaC7                  = 0xD4,
@@ -732,16 +729,19 @@ typedef enum {
   ProcessorFamilyMII                   = 0x012E,
   ProcessorFamilyWinChip               = 0x0140,
   ProcessorFamilyDSP                   = 0x015E,
-  ProcessorFamilyVideoProcessor        = 0x01F4
+  ProcessorFamilyVideoProcessor        = 0x01F4,
+  ProcessorFamilyRiscvRV32             = 0x0200,
+  ProcessorFamilyRiscVRV64             = 0x0201,
+  ProcessorFamilyRiscVRV128            = 0x0202
 } PROCESSOR_FAMILY2_DATA;
 
 ///
-/// Processor Information - Voltage. 
+/// Processor Information - Voltage.
 ///
 typedef struct {
-  UINT8  ProcessorVoltageCapability5V        :1; 
-  UINT8  ProcessorVoltageCapability3_3V      :1;  
-  UINT8  ProcessorVoltageCapability2_9V      :1;  
+  UINT8  ProcessorVoltageCapability5V        :1;
+  UINT8  ProcessorVoltageCapability3_3V      :1;
+  UINT8  ProcessorVoltageCapability2_9V      :1;
   UINT8  ProcessorVoltageCapabilityReserved  :1; ///< Bit 3, must be zero.
   UINT8  ProcessorVoltageReserved            :3; ///< Bits 4-6, must be zero.
   UINT8  ProcessorVoltageIndicateLegacy      :1;
@@ -806,7 +806,11 @@ typedef enum {
   ProcessorUpgradeSocketBGA1515   = 0x35,
   ProcessorUpgradeSocketLGA3647_1 = 0x36,
   ProcessorUpgradeSocketSP3       = 0x37,
-  ProcessorUpgradeSocketSP3r2     = 0x38
+  ProcessorUpgradeSocketSP3r2     = 0x38,
+  ProcessorUpgradeSocketLGA2066   = 0x39,
+  ProcessorUpgradeSocketBGA1392   = 0x3A,
+  ProcessorUpgradeSocketBGA1510   = 0x3B,
+  ProcessorUpgradeSocketBGA1528   = 0x3C
 } PROCESSOR_UPGRADE;
 
 ///
@@ -858,6 +862,19 @@ typedef struct {
 } PROCESSOR_FEATURE_FLAGS;
 
 typedef struct {
+  UINT32  ProcessorReserved1             :1;
+  UINT32  ProcessorUnknown               :1;
+  UINT32  Processor64BitCapble           :1;
+  UINT32  ProcessorMultiCore             :1;
+  UINT32  ProcessorHardwareThread        :1;
+  UINT32  ProcessorExecuteProtection     :1;
+  UINT32  ProcessorEnhancedVirtulization :1;
+  UINT32  ProcessorPowerPerformanceCtrl  :1;
+  UINT32  Processor128bitCapble          :1;
+  UINT32  ProcessorReserved2             :7;
+} PROCESSOR_CHARACTERISTIC_FLAGS;
+
+typedef struct {
   PROCESSOR_SIGNATURE     Signature;
   PROCESSOR_FEATURE_FLAGS FeatureFlags;
 } PROCESSOR_ID_DATA;
@@ -865,13 +882,13 @@ typedef struct {
 ///
 /// Processor Information (Type 4).
 ///
-/// The information in this structure defines the attributes of a single processor; 
-/// a separate structure instance is provided for each system processor socket/slot. 
-/// For example, a system with an IntelDX2 processor would have a single 
+/// The information in this structure defines the attributes of a single processor;
+/// a separate structure instance is provided for each system processor socket/slot.
+/// For example, a system with an IntelDX2 processor would have a single
 /// structure instance, while a system with an IntelSX2 processor would have a structure
-/// to describe the main CPU, and a second structure to describe the 80487 co-processor. 
+/// to describe the main CPU, and a second structure to describe the 80487 co-processor.
 ///
-typedef struct { 
+typedef struct {
   SMBIOS_STRUCTURE      Hdr;
   SMBIOS_TABLE_STRING   Socket;
   UINT8                 ProcessorType;          ///< The enumeration value from PROCESSOR_TYPE_DATA.
@@ -913,7 +930,7 @@ typedef struct {
 ///
 /// Memory Controller Error Detecting Method.
 ///
-typedef enum {  
+typedef enum {
   ErrorDetectingMethodOther   = 0x01,
   ErrorDetectingMethodUnknown = 0x02,
   ErrorDetectingMethodNone    = 0x03,
@@ -940,7 +957,7 @@ typedef struct {
 ///
 /// Memory Controller Information - Interleave Support.
 ///
-typedef enum {  
+typedef enum {
   MemoryInterleaveOther      = 0x01,
   MemoryInterleaveUnknown    = 0x02,
   MemoryInterleaveOneWay     = 0x03,
@@ -965,10 +982,10 @@ typedef struct {
 ///
 /// Memory Controller Information (Type 5, Obsolete).
 ///
-/// The information in this structure defines the attributes of the system's memory controller(s) 
-/// and the supported attributes of any memory-modules present in the sockets controlled by 
-/// this controller. 
-/// Note: This structure, and its companion Memory Module Information (Type 6, Obsolete), 
+/// The information in this structure defines the attributes of the system's memory controller(s)
+/// and the supported attributes of any memory-modules present in the sockets controlled by
+/// this controller.
+/// Note: This structure, and its companion Memory Module Information (Type 6, Obsolete),
 /// are obsolete starting with version 2.1 of this specification. The Physical Memory Array (Type 16)
 /// and Memory Device (Type 17) structures should be used instead.  BIOS providers might
 /// choose to implement both memory description types to allow existing DMI browsers
@@ -979,7 +996,7 @@ typedef struct {
   UINT8                           ErrDetectMethod;            ///< The enumeration value from MEMORY_ERROR_DETECT_METHOD.
   MEMORY_ERROR_CORRECT_CAPABILITY ErrCorrectCapability;
   UINT8                           SupportInterleave;          ///< The enumeration value from MEMORY_SUPPORT_INTERLEAVE_TYPE.
-  UINT8                           CurrentInterleave;          ///< The enumeration value from MEMORY_SUPPORT_INTERLEAVE_TYPE .     
+  UINT8                           CurrentInterleave;          ///< The enumeration value from MEMORY_SUPPORT_INTERLEAVE_TYPE .
   UINT8                           MaxMemoryModuleSize;
   MEMORY_SPEED_TYPE               SupportSpeed;
   UINT16                          SupportMemoryType;
@@ -1017,11 +1034,11 @@ typedef struct {
 ///
 /// Memory Module Information (Type 6, Obsolete)
 ///
-/// One Memory Module Information structure is included for each memory-module socket 
+/// One Memory Module Information structure is included for each memory-module socket
 /// in the system.  The structure describes the speed, type, size, and error status
-/// of each system memory module.  The supported attributes of each module are described 
-/// by the "owning" Memory Controller Information structure.  
-/// Note:  This structure, and its companion Memory Controller Information (Type 5, Obsolete), 
+/// of each system memory module.  The supported attributes of each module are described
+/// by the "owning" Memory Controller Information structure.
+/// Note:  This structure, and its companion Memory Controller Information (Type 5, Obsolete),
 /// are obsolete starting with version 2.1 of this specification. The Physical Memory Array (Type 16)
 /// and Memory Device (Type 17) structures should be used instead.
 ///
@@ -1063,7 +1080,7 @@ typedef enum {
 } CACHE_ERROR_TYPE_DATA;
 
 ///
-/// Cache Information - System Cache Type. 
+/// Cache Information - System Cache Type.
 ///
 typedef enum {
   CacheTypeOther       = 0x01,
@@ -1074,7 +1091,7 @@ typedef enum {
 } CACHE_TYPE_DATA;
 
 ///
-/// Cache Information - Associativity. 
+/// Cache Information - Associativity.
 ///
 typedef enum {
   CacheAssociativityOther        = 0x01,
@@ -1096,7 +1113,7 @@ typedef enum {
 ///
 /// Cache Information (Type 7).
 ///
-/// The information in this structure defines the attributes of CPU cache device in the system. 
+/// The information in this structure defines the attributes of CPU cache device in the system.
 /// One structure is specified for each such device, whether the device is internal to
 /// or external to the CPU module.  Cache modules can be associated with a processor structure
 /// in one or two ways, depending on the SMBIOS version.
@@ -1121,7 +1138,7 @@ typedef struct {
 } SMBIOS_TABLE_TYPE7;
 
 ///
-/// Port Connector Information - Connector Types. 
+/// Port Connector Information - Connector Types.
 ///
 typedef enum {
   PortConnectorTypeNone                   = 0x00,
@@ -1159,6 +1176,7 @@ typedef enum {
   PortConnectorTypeBNC                    = 0x20,
   PortConnectorType1394                   = 0x21,
   PortConnectorTypeSasSata                = 0x22,
+  PortConnectorTypeUsbTypeC               = 0x23,
   PortConnectorTypePC98                   = 0xA0,
   PortConnectorTypePC98Hireso             = 0xA1,
   PortConnectorTypePCH98                  = 0xA2,
@@ -1168,7 +1186,7 @@ typedef enum {
 } MISC_PORT_CONNECTOR_TYPE;
 
 ///
-/// Port Connector Information - Port Types 
+/// Port Connector Information - Port Types
 ///
 typedef enum {
   PortTypeNone                      = 0x00,
@@ -1205,6 +1223,8 @@ typedef enum {
   PortTypeNetworkPort               = 0x1F,
   PortTypeSata                      = 0x20,
   PortTypeSas                       = 0x21,
+  PortTypeMfdp                      = 0x22, ///< Multi-Function Display Port
+  PortTypeThunderbolt               = 0x23,
   PortType8251Compatible            = 0xA0,
   PortType8251FifoCompatible        = 0xA1,
   PortTypeOther                     = 0xFF
@@ -1213,8 +1233,8 @@ typedef enum {
 ///
 /// Port Connector Information (Type 8).
 ///
-/// The information in this structure defines the attributes of a system port connector, 
-/// e.g. parallel, serial, keyboard, or mouse ports.  The port's type and connector information 
+/// The information in this structure defines the attributes of a system port connector,
+/// e.g. parallel, serial, keyboard, or mouse ports.  The port's type and connector information
 /// are provided. One structure is present for each port provided by the system.
 ///
 typedef struct {
@@ -1265,6 +1285,7 @@ typedef enum {
   SlotTypePciExpressMini52pinWithBSKO  = 0x21,      ///< PCI Express Mini 52-pin (CEM spec. 2.0) with bottom-side keep-outs.
   SlotTypePciExpressMini52pinWithoutBSKO = 0x22,    ///< PCI Express Mini 52-pin (CEM spec. 2.0) without bottom-side keep-outs.
   SlotTypePciExpressMini76pin          = 0x23,      ///< PCI Express Mini 76-pin (CEM spec. 2.0) Corresponds to Display-Mini card.
+  SlotTypeCXLFlexbus10                 = 0x30,
   SlotTypePC98C20                      = 0xA0,
   SlotTypePC98C24                      = 0xA1,
   SlotTypePC98E                        = 0xA2,
@@ -1287,7 +1308,13 @@ typedef enum {
   SlotTypePciExpressGen3X2             = 0xB3,
   SlotTypePciExpressGen3X4             = 0xB4,
   SlotTypePciExpressGen3X8             = 0xB5,
-  SlotTypePciExpressGen3X16            = 0xB6
+  SlotTypePciExpressGen3X16            = 0xB6,
+  SlotTypePciExpressGen4               = 0xB8,
+  SlotTypePciExpressGen4X1             = 0xB9,
+  SlotTypePciExpressGen4X2             = 0xBA,
+  SlotTypePciExpressGen4X4             = 0xBB,
+  SlotTypePciExpressGen4X8             = 0xBC,
+  SlotTypePciExpressGen4X16            = 0xBD
 } MISC_SLOT_TYPE;
 
 ///
@@ -1314,14 +1341,15 @@ typedef enum {
 /// System Slots - Current Usage.
 ///
 typedef enum {
-  SlotUsageOther     = 0x01,
-  SlotUsageUnknown   = 0x02,
-  SlotUsageAvailable = 0x03,
-  SlotUsageInUse     = 0x04
+  SlotUsageOther        = 0x01,
+  SlotUsageUnknown      = 0x02,
+  SlotUsageAvailable    = 0x03,
+  SlotUsageInUse        = 0x04,
+  SlotUsageUnavailable  = 0x05
 } MISC_SLOT_USAGE;
 
 ///
-/// System Slots - Slot Length. 
+/// System Slots - Slot Length.
 ///
 typedef enum {
   SlotLengthOther   = 0x01,
@@ -1331,7 +1359,7 @@ typedef enum {
 } MISC_SLOT_LENGTH;
 
 ///
-/// System Slots - Slot Characteristics 1. 
+/// System Slots - Slot Characteristics 1.
 ///
 typedef struct {
   UINT8  CharacteristicsUnknown  :1;
@@ -1344,19 +1372,30 @@ typedef struct {
   UINT8  ModemRingResumeSupported:1;
 } MISC_SLOT_CHARACTERISTICS1;
 ///
-/// System Slots - Slot Characteristics 2.  
+/// System Slots - Slot Characteristics 2.
 ///
 typedef struct {
   UINT8  PmeSignalSupported      :1;
   UINT8  HotPlugDevicesSupported :1;
   UINT8  SmbusSignalSupported    :1;
-  UINT8  Reserved                :5;  ///< Set to 0.
+  UINT8  BifurcationSupported    :1;
+  UINT8  Reserved                :4;  ///< Set to 0.
 } MISC_SLOT_CHARACTERISTICS2;
 
 ///
+/// System Slots - Peer Segment/Bus/Device/Function/Width Groups
+///
+typedef struct {
+  UINT16                      SegmentGroupNum;
+  UINT8                       BusNum;
+  UINT8                       DevFuncNum;
+  UINT8                       DataBusWidth;
+} MISC_SLOT_PEER_GROUP;
+
+///
 /// System Slots (Type 9)
 ///
-/// The information in this structure defines the attributes of a system slot. 
+/// The information in this structure defines the attributes of a system slot.
 /// One structure is provided for each slot in the system.
 ///
 ///
@@ -1376,10 +1415,16 @@ typedef struct {
   UINT16                      SegmentGroupNum;
   UINT8                       BusNum;
   UINT8                       DevFuncNum;
+  //
+  // Add for smbios 3.2
+  //
+  UINT8                       DataBusWidth;
+  UINT8                       PeerGroupingCount;
+  MISC_SLOT_PEER_GROUP        PeerGroups[1];
 } SMBIOS_TABLE_TYPE9;
 
 ///
-/// On Board Devices Information - Device Types. 
+/// On Board Devices Information - Device Types.
 ///
 typedef enum {
   OnBoardDeviceTypeOther          = 0x01,
@@ -1406,10 +1451,10 @@ typedef struct {
 ///
 /// On Board Devices Information (Type 10, obsolete).
 ///
-/// Note: This structure is obsolete starting with version 2.6 specification; the Onboard Devices Extended 
-/// Information (Type 41) structure should be used instead . BIOS providers can choose to implement both 
-/// types to allow existing SMBIOS browsers to properly display the system's onboard devices information.  
-/// The information in this structure defines the attributes of devices that are onboard (soldered onto) 
+/// Note: This structure is obsolete starting with version 2.6 specification; the Onboard Devices Extended
+/// Information (Type 41) structure should be used instead . BIOS providers can choose to implement both
+/// types to allow existing SMBIOS browsers to properly display the system's onboard devices information.
+/// The information in this structure defines the attributes of devices that are onboard (soldered onto)
 /// a system element, usually the baseboard.  In general, an entry in this table implies that the BIOS
 /// has some level of control over the enabling of the associated device for use by the system.
 ///
@@ -1420,8 +1465,8 @@ typedef struct {
 
 ///
 /// OEM Strings (Type 11).
-/// This structure contains free form strings defined by the OEM. Examples of this are: 
-/// Part Numbers for Reference Documents for the system, contact information for the manufacturer, etc. 
+/// This structure contains free form strings defined by the OEM. Examples of this are:
+/// Part Numbers for Reference Documents for the system, contact information for the manufacturer, etc.
 ///
 typedef struct {
   SMBIOS_STRUCTURE      Hdr;
@@ -1431,7 +1476,7 @@ typedef struct {
 ///
 /// System Configuration Options (Type 12).
 ///
-/// This structure contains information required to configure the base board's Jumpers and Switches. 
+/// This structure contains information required to configure the base board's Jumpers and Switches.
 ///
 typedef struct {
   SMBIOS_STRUCTURE      Hdr;
@@ -1442,8 +1487,8 @@ typedef struct {
 ///
 /// BIOS Language Information (Type 13).
 ///
-/// The information in this structure defines the installable language attributes of the BIOS.  
-/// 
+/// The information in this structure defines the installable language attributes of the BIOS.
+///
 typedef struct {
   SMBIOS_STRUCTURE      Hdr;
   UINT8                 InstallableLanguages;
@@ -1463,9 +1508,9 @@ typedef struct {
 ///
 /// Group Associations (Type 14).
 ///
-/// The Group Associations structure is provided for OEMs who want to specify 
-/// the arrangement or hierarchy of certain components (including other Group Associations) 
-/// within the system. 
+/// The Group Associations structure is provided for OEMs who want to specify
+/// the arrangement or hierarchy of certain components (including other Group Associations)
+/// within the system.
 ///
 typedef struct {
   SMBIOS_STRUCTURE      Hdr;
@@ -1475,7 +1520,7 @@ typedef struct {
 
 ///
 /// System Event Log - Event Log Types.
-/// 
+///
 typedef enum {
   EventLogTypeReserved         = 0x00,
   EventLogTypeSingleBitECC     = 0x01,
@@ -1506,8 +1551,8 @@ typedef enum {
 } EVENT_LOG_TYPE_DATA;
 
 ///
-/// System Event Log - Variable Data Format Types. 
-/// 
+/// System Event Log - Variable Data Format Types.
+///
 typedef enum {
   EventLogVariableNone                        = 0x00,
   EventLogVariableHandle                      = 0x01,
@@ -1515,7 +1560,7 @@ typedef enum {
   EventLogVariableMutilEventHandle            = 0x03,
   EventLogVariablePOSTResultBitmap            = 0x04,
   EventLogVariableSysManagementType           = 0x05,
-  EventLogVariableMutliEventSysManagmentType  = 0x06,                               
+  EventLogVariableMutliEventSysManagmentType  = 0x06,
   EventLogVariableUnused                      = 0x07,
   EventLogVariableOEMAssigned                 = 0x80
 } EVENT_LOG_VARIABLE_DATA;
@@ -1531,10 +1576,10 @@ typedef struct {
 ///
 /// System Event Log (Type 15).
 ///
-/// The presence of this structure within the SMBIOS data returned for a system indicates 
-/// that the system supports an event log.  An event log is a fixed-length area within a 
-/// non-volatile storage element, starting with a fixed-length (and vendor-specific) header 
-/// record, followed by one or more variable-length log records. 
+/// The presence of this structure within the SMBIOS data returned for a system indicates
+/// that the system supports an event log.  An event log is a fixed-length area within a
+/// non-volatile storage element, starting with a fixed-length (and vendor-specific) header
+/// record, followed by one or more variable-length log records.
 ///
 typedef struct {
   SMBIOS_STRUCTURE      Hdr;
@@ -1568,7 +1613,8 @@ typedef enum {
   MemoryArrayLocationPc98C20AddonCard      = 0xA0,
   MemoryArrayLocationPc98C24AddonCard      = 0xA1,
   MemoryArrayLocationPc98EAddonCard        = 0xA2,
-  MemoryArrayLocationPc98LocalBusAddonCard = 0xA3
+  MemoryArrayLocationPc98LocalBusAddonCard = 0xA3,
+  MemoryArrayLocationCXLFlexbus10AddonCard = 0xA4
 } MEMORY_ARRAY_LOCATION;
 
 ///
@@ -1585,7 +1631,7 @@ typedef enum {
 } MEMORY_ARRAY_USE;
 
 ///
-/// Physical Memory Array - Error Correction Types. 
+/// Physical Memory Array - Error Correction Types.
 ///
 typedef enum {
   MemoryErrorCorrectionOther               = 0x01,
@@ -1600,8 +1646,8 @@ typedef enum {
 ///
 /// Physical Memory Array (Type 16).
 ///
-/// This structure describes a collection of memory devices that operate 
-/// together to form a memory address space. 
+/// This structure describes a collection of memory devices that operate
+/// together to form a memory address space.
 ///
 typedef struct {
   SMBIOS_STRUCTURE          Hdr;
@@ -1635,7 +1681,8 @@ typedef enum {
   MemoryFormFactorRimm                     = 0x0C,
   MemoryFormFactorSodimm                   = 0x0D,
   MemoryFormFactorSrimm                    = 0x0E,
-  MemoryFormFactorFbDimm                   = 0x0F
+  MemoryFormFactorFbDimm                   = 0x0F,
+  MemoryFormFactorDie                      = 0x10
 } MEMORY_FORM_FACTOR;
 
 ///
@@ -1668,9 +1715,15 @@ typedef enum {
   MemoryTypeLpddr                          = 0x1B,
   MemoryTypeLpddr2                         = 0x1C,
   MemoryTypeLpddr3                         = 0x1D,
-  MemoryTypeLpddr4                         = 0x1E
+  MemoryTypeLpddr4                         = 0x1E,
+  MemoryTypeLogicalNonVolatileDevice       = 0x1F,
+  MemoryTypeHBM                            = 0x20,
+  MemoryTypeHBM2                           = 0x21
 } MEMORY_DEVICE_TYPE;
 
+///
+/// Memory Device - Type Detail
+///
 typedef struct {
   UINT16    Reserved        :1;
   UINT16    Other           :1;
@@ -1691,53 +1744,116 @@ typedef struct {
 } MEMORY_DEVICE_TYPE_DETAIL;
 
 ///
+/// Memory Device - Memory Technology
+///
+typedef enum {
+  MemoryTechnologyOther                     = 0x01,
+  MemoryTechnologyUnknown                   = 0x02,
+  MemoryTechnologyDram                      = 0x03,
+  MemoryTechnologyNvdimmN                   = 0x04,
+  MemoryTechnologyNvdimmF                   = 0x05,
+  MemoryTechnologyNvdimmP                   = 0x06,
+  //
+  // This definition is updated to represent Intel
+  // Optane DC Presistent Memory in SMBIOS spec 3.3.0
+  //
+  MemoryTechnologyIntelPersistentMemory     = 0x07
+} MEMORY_DEVICE_TECHNOLOGY;
+
+///
+/// Memory Device - Memory Operating Mode Capability
+///
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT16 Reserved                         :1;   ///< Set to 0.
+    UINT16 Other                            :1;
+    UINT16 Unknown                          :1;
+    UINT16 VolatileMemory                   :1;
+    UINT16 ByteAccessiblePersistentMemory   :1;
+    UINT16 BlockAccessiblePersistentMemory  :1;
+    UINT16 Reserved2                        :10;  ///< Set to 0.
+  } Bits;
+  ///
+  /// All bit fields as a 16-bit value
+  ///
+  UINT16 Uint16;
+} MEMORY_DEVICE_OPERATING_MODE_CAPABILITY;
+
+///
 /// Memory Device (Type 17).
 ///
-/// This structure describes a single memory device that is part of 
+/// This structure describes a single memory device that is part of
 /// a larger Physical Memory Array (Type 16).
-/// Note:  If a system includes memory-device sockets, the SMBIOS implementation 
-/// includes a Memory Device structure instance for each slot, whether or not the 
+/// Note:  If a system includes memory-device sockets, the SMBIOS implementation
+/// includes a Memory Device structure instance for each slot, whether or not the
 /// socket is currently populated.
 ///
 typedef struct {
-  SMBIOS_STRUCTURE          Hdr;
-  UINT16                    MemoryArrayHandle;
-  UINT16                    MemoryErrorInformationHandle;
-  UINT16                    TotalWidth;
-  UINT16                    DataWidth;
-  UINT16                    Size;
-  UINT8                     FormFactor;                     ///< The enumeration value from MEMORY_FORM_FACTOR.
-  UINT8                     DeviceSet;
-  SMBIOS_TABLE_STRING       DeviceLocator;
-  SMBIOS_TABLE_STRING       BankLocator;
-  UINT8                     MemoryType;                     ///< The enumeration value from MEMORY_DEVICE_TYPE.
-  MEMORY_DEVICE_TYPE_DETAIL TypeDetail;
-  UINT16                    Speed;
-  SMBIOS_TABLE_STRING       Manufacturer;
-  SMBIOS_TABLE_STRING       SerialNumber;
-  SMBIOS_TABLE_STRING       AssetTag;
-  SMBIOS_TABLE_STRING       PartNumber;
+  SMBIOS_STRUCTURE                          Hdr;
+  UINT16                                    MemoryArrayHandle;
+  UINT16                                    MemoryErrorInformationHandle;
+  UINT16                                    TotalWidth;
+  UINT16                                    DataWidth;
+  UINT16                                    Size;
+  UINT8                                     FormFactor;         ///< The enumeration value from MEMORY_FORM_FACTOR.
+  UINT8                                     DeviceSet;
+  SMBIOS_TABLE_STRING                       DeviceLocator;
+  SMBIOS_TABLE_STRING                       BankLocator;
+  UINT8                                     MemoryType;         ///< The enumeration value from MEMORY_DEVICE_TYPE.
+  MEMORY_DEVICE_TYPE_DETAIL                 TypeDetail;
+  UINT16                                    Speed;
+  SMBIOS_TABLE_STRING                       Manufacturer;
+  SMBIOS_TABLE_STRING                       SerialNumber;
+  SMBIOS_TABLE_STRING                       AssetTag;
+  SMBIOS_TABLE_STRING                       PartNumber;
   //
   // Add for smbios 2.6
-  //  
-  UINT8                     Attributes;
+  //
+  UINT8                                     Attributes;
   //
   // Add for smbios 2.7
   //
-  UINT32                    ExtendedSize;
-  UINT16                    ConfiguredMemoryClockSpeed;
+  UINT32                                    ExtendedSize;
+  //
+  // Keep using name "ConfiguredMemoryClockSpeed" for compatibility
+  // although this field is renamed from "Configured Memory Clock Speed"
+  // to "Configured Memory Speed" in smbios 3.2.0.
+  //
+  UINT16                                    ConfiguredMemoryClockSpeed;
   //
   // Add for smbios 2.8.0
   //
-  UINT16                    MinimumVoltage;
-  UINT16                    MaximumVoltage;
-  UINT16                    ConfiguredVoltage;
+  UINT16                                    MinimumVoltage;
+  UINT16                                    MaximumVoltage;
+  UINT16                                    ConfiguredVoltage;
+  //
+  // Add for smbios 3.2.0
+  //
+  UINT8                                     MemoryTechnology;   ///< The enumeration value from MEMORY_DEVICE_TECHNOLOGY
+  MEMORY_DEVICE_OPERATING_MODE_CAPABILITY   MemoryOperatingModeCapability;
+  SMBIOS_TABLE_STRING                       FirwareVersion;
+  UINT16                                    ModuleManufacturerID;
+  UINT16                                    ModuleProductID;
+  UINT16                                    MemorySubsystemControllerManufacturerID;
+  UINT16                                    MemorySubsystemControllerProductID;
+  UINT64                                    NonVolatileSize;
+  UINT64                                    VolatileSize;
+  UINT64                                    CacheSize;
+  UINT64                                    LogicalSize;
+  //
+  // Add for smbios 3.3.0
+  //
+  UINT32                                    ExtendedSpeed;
+  UINT32                                    ExtendedConfiguredMemorySpeed;
 } SMBIOS_TABLE_TYPE17;
 
 ///
-/// 32-bit Memory Error Information - Error Type. 
+/// 32-bit Memory Error Information - Error Type.
 ///
-typedef enum {  
+typedef enum {
   MemoryErrorOther             = 0x01,
   MemoryErrorUnknown           = 0x02,
   MemoryErrorOk                = 0x03,
@@ -1755,9 +1871,9 @@ typedef enum {
 } MEMORY_ERROR_TYPE;
 
 ///
-/// 32-bit Memory Error Information - Error Granularity. 
+/// 32-bit Memory Error Information - Error Granularity.
 ///
-typedef enum {  
+typedef enum {
   MemoryGranularityOther               = 0x01,
   MemoryGranularityOtherUnknown        = 0x02,
   MemoryGranularityDeviceLevel         = 0x03,
@@ -1765,9 +1881,9 @@ typedef enum {
 } MEMORY_ERROR_GRANULARITY;
 
 ///
-/// 32-bit Memory Error Information - Error Operation. 
+/// 32-bit Memory Error Information - Error Operation.
 ///
-typedef enum {  
+typedef enum {
   MemoryErrorOperationOther            = 0x01,
   MemoryErrorOperationUnknown          = 0x02,
   MemoryErrorOperationRead             = 0x03,
@@ -1777,8 +1893,8 @@ typedef enum {
 
 ///
 /// 32-bit Memory Error Information (Type 18).
-/// 
-/// This structure identifies the specifics of an error that might be detected 
+///
+/// This structure identifies the specifics of an error that might be detected
 /// within a Physical Memory Array.
 ///
 typedef struct {
@@ -1795,7 +1911,7 @@ typedef struct {
 ///
 /// Memory Array Mapped Address (Type 19).
 ///
-/// This structure provides the address mapping for a Physical Memory Array.  
+/// This structure provides the address mapping for a Physical Memory Array.
 /// One structure is present for each contiguous address range described.
 ///
 typedef struct {
@@ -1814,8 +1930,8 @@ typedef struct {
 ///
 /// Memory Device Mapped Address (Type 20).
 ///
-/// This structure maps memory address space usually to a device-level granularity.  
-/// One structure is present for each contiguous address range described. 
+/// This structure maps memory address space usually to a device-level granularity.
+/// One structure is present for each contiguous address range described.
 ///
 typedef struct {
   SMBIOS_STRUCTURE      Hdr;
@@ -1868,9 +1984,9 @@ typedef enum {
 ///
 /// Built-in Pointing Device (Type 21).
 ///
-/// This structure describes the attributes of the built-in pointing device for the 
+/// This structure describes the attributes of the built-in pointing device for the
 /// system. The presence of this structure does not imply that the built-in
-/// pointing device is active for the system's use! 
+/// pointing device is active for the system's use!
 ///
 typedef struct {
   SMBIOS_STRUCTURE                  Hdr;
@@ -1882,7 +1998,7 @@ typedef struct {
 ///
 /// Portable Battery - Device Chemistry
 ///
-typedef enum {  
+typedef enum {
   PortableBatteryDeviceChemistryOther               = 0x01,
   PortableBatteryDeviceChemistryUnknown             = 0x02,
   PortableBatteryDeviceChemistryLeadAcid            = 0x03,
@@ -1896,8 +2012,8 @@ typedef enum {
 ///
 /// Portable Battery (Type 22).
 ///
-/// This structure describes the attributes of the portable battery(s) for the system.  
-/// The structure contains the static attributes for the group.  Each structure describes 
+/// This structure describes the attributes of the portable battery(s) for the system.
+/// The structure contains the static attributes for the group.  Each structure describes
 /// a single battery pack's attributes.
 ///
 typedef struct {
@@ -1922,11 +2038,11 @@ typedef struct {
 ///
 /// System Reset (Type 23)
 ///
-/// This structure describes whether Automatic System Reset functions enabled (Status).  
+/// This structure describes whether Automatic System Reset functions enabled (Status).
 /// If the system has a watchdog Timer and the timer is not reset (Timer Reset)
-/// before the Interval elapses, an automatic system reset will occur. The system will re-boot 
-/// according to the Boot Option. This function may repeat until the Limit is reached, at which time 
-/// the system will re-boot according to the Boot Option at Limit.  
+/// before the Interval elapses, an automatic system reset will occur. The system will re-boot
+/// according to the Boot Option. This function may repeat until the Limit is reached, at which time
+/// the system will re-boot according to the Boot Option at Limit.
 ///
 typedef struct {
   SMBIOS_STRUCTURE      Hdr;
@@ -1940,7 +2056,7 @@ typedef struct {
 ///
 /// Hardware Security (Type 24).
 ///
-/// This structure describes the system-wide hardware security settings. 
+/// This structure describes the system-wide hardware security settings.
 ///
 typedef struct {
   SMBIOS_STRUCTURE      Hdr;
@@ -1950,10 +2066,10 @@ typedef struct {
 ///
 /// System Power Controls (Type 25).
 ///
-/// This structure describes the attributes for controlling the main power supply to the system. 
-/// Software that interprets this structure uses the month, day, hour, minute, and second values 
-/// to determine the number of seconds until the next power-on of the system.  The presence of  
-/// this structure implies that a timed power-on facility is available for the system. 
+/// This structure describes the attributes for controlling the main power supply to the system.
+/// Software that interprets this structure uses the month, day, hour, minute, and second values
+/// to determine the number of seconds until the next power-on of the system.  The presence of
+/// this structure implies that a timed power-on facility is available for the system.
 ///
 typedef struct {
   SMBIOS_STRUCTURE      Hdr;
@@ -1975,7 +2091,7 @@ typedef struct {
 ///
 /// Voltage Probe (Type 26)
 ///
-/// This describes the attributes for a voltage probe in the system.   
+/// This describes the attributes for a voltage probe in the system.
 /// Each structure describes a single voltage probe.
 ///
 typedef struct {
@@ -2002,9 +2118,9 @@ typedef struct {
 ///
 /// Cooling Device (Type 27)
 ///
-/// This structure describes the attributes for a cooling device in the system.  
-/// Each structure describes a single cooling device. 
-/// 
+/// This structure describes the attributes for a cooling device in the system.
+/// Each structure describes a single cooling device.
+///
 typedef struct {
   SMBIOS_STRUCTURE                  Hdr;
   UINT16                            TemperatureProbeHandle;
@@ -2029,8 +2145,8 @@ typedef struct {
 ///
 /// Temperature Probe (Type 28).
 ///
-/// This structure describes the attributes for a temperature probe in the system.  
-/// Each structure describes a single temperature probe. 
+/// This structure describes the attributes for a temperature probe in the system.
+/// Each structure describes a single temperature probe.
 ///
 typedef struct {
   SMBIOS_STRUCTURE                  Hdr;
@@ -2057,7 +2173,7 @@ typedef struct {
 /// Electrical Current Probe (Type 29).
 ///
 /// This structure describes the attributes for an electrical current probe in the system.
-/// Each structure describes a single electrical current probe. 
+/// Each structure describes a single electrical current probe.
 ///
 typedef struct {
   SMBIOS_STRUCTURE                        Hdr;
@@ -2075,9 +2191,9 @@ typedef struct {
 ///
 /// Out-of-Band Remote Access (Type 30).
 ///
-/// This structure describes the attributes and policy settings of a hardware facility 
-/// that may be used to gain remote access to a hardware system when the operating system 
-/// is not available due to power-down status, hardware failures, or boot failures. 
+/// This structure describes the attributes and policy settings of a hardware facility
+/// that may be used to gain remote access to a hardware system when the operating system
+/// is not available due to power-down status, hardware failures, or boot failures.
 ///
 typedef struct {
   SMBIOS_STRUCTURE      Hdr;
@@ -2088,8 +2204,8 @@ typedef struct {
 ///
 /// Boot Integrity Services (BIS) Entry Point (Type 31).
 ///
-/// Structure type 31 (decimal) is reserved for use by the Boot Integrity Services (BIS). 
-/// 
+/// Structure type 31 (decimal) is reserved for use by the Boot Integrity Services (BIS).
+///
 typedef struct {
   SMBIOS_STRUCTURE      Hdr;
   UINT8                 Checksum;
@@ -2122,12 +2238,12 @@ typedef enum {
 ///
 /// System Boot Information (Type 32).
 ///
-/// The client system firmware, e.g. BIOS, communicates the System Boot Status to the 
-/// client's Pre-boot Execution Environment (PXE) boot image or OS-present management 
-/// application via this structure. When used in the PXE environment, for example, 
-/// this code identifies the reason the PXE was initiated and can be used by boot-image 
-/// software to further automate an enterprise's PXE sessions.  For example, an enterprise  
-/// could choose to automatically download a hardware-diagnostic image to a client whose 
+/// The client system firmware, e.g. BIOS, communicates the System Boot Status to the
+/// client's Pre-boot Execution Environment (PXE) boot image or OS-present management
+/// application via this structure. When used in the PXE environment, for example,
+/// this code identifies the reason the PXE was initiated and can be used by boot-image
+/// software to further automate an enterprise's PXE sessions.  For example, an enterprise
+/// could choose to automatically download a hardware-diagnostic image to a client whose
 /// reason code indicated either a firmware- or operating system-detected hardware failure.
 ///
 typedef struct {
@@ -2139,9 +2255,9 @@ typedef struct {
 ///
 /// 64-bit Memory Error Information (Type 33).
 ///
-/// This structure describes an error within a Physical Memory Array, 
+/// This structure describes an error within a Physical Memory Array,
 /// when the error address is above 4G (0xFFFFFFFF).
-///    
+///
 typedef struct {
   SMBIOS_STRUCTURE          Hdr;
   UINT8                     ErrorType;                    ///< The enumeration value from MEMORY_ERROR_TYPE.
@@ -2154,7 +2270,7 @@ typedef struct {
 } SMBIOS_TABLE_TYPE33;
 
 ///
-/// Management Device -  Type. 
+/// Management Device -  Type.
 ///
 typedef enum {
   ManagementDeviceTypeOther      = 0x01,
@@ -2173,7 +2289,7 @@ typedef enum {
 } MISC_MANAGEMENT_DEVICE_TYPE;
 
 ///
-/// Management Device -  Address Type. 
+/// Management Device -  Address Type.
 ///
 typedef enum {
   ManagementDeviceAddressTypeOther   = 0x01,
@@ -2186,7 +2302,7 @@ typedef enum {
 ///
 /// Management Device (Type 34).
 ///
-/// The information in this structure defines the attributes of a Management Device.  
+/// The information in this structure defines the attributes of a Management Device.
 /// A Management Device might control one or more fans or voltage, current, or temperature
 /// probes as defined by one or more Management Device Component structures.
 ///
@@ -2201,8 +2317,8 @@ typedef struct {
 ///
 /// Management Device Component (Type 35)
 ///
-/// This structure associates a cooling device or environmental probe with structures 
-/// that define the controlling hardware device and (optionally) the component's thresholds. 
+/// This structure associates a cooling device or environmental probe with structures
+/// that define the controlling hardware device and (optionally) the component's thresholds.
 ///
 typedef struct {
   SMBIOS_STRUCTURE      Hdr;
@@ -2215,8 +2331,8 @@ typedef struct {
 ///
 /// Management Device Threshold Data (Type 36).
 ///
-/// The information in this structure defines threshold information for 
-/// a component (probe or cooling-unit) contained within a Management Device.  
+/// The information in this structure defines threshold information for
+/// a component (probe or cooling-unit) contained within a Management Device.
 ///
 typedef struct {
   SMBIOS_STRUCTURE      Hdr;
@@ -2250,7 +2366,7 @@ typedef enum {
 /// Memory Channel (Type 37)
 ///
 /// The information in this structure provides the correlation between a Memory Channel
-/// and its associated Memory Devices.  Each device presents one or more loads to the channel. 
+/// and its associated Memory Devices.  Each device presents one or more loads to the channel.
 /// The sum of all device loads cannot exceed the channel's defined maximum.
 ///
 typedef struct {
@@ -2269,7 +2385,7 @@ typedef enum {
   IPMIDeviceInfoInterfaceTypeKCS           = 0x01, ///< The Keyboard Controller Style.
   IPMIDeviceInfoInterfaceTypeSMIC          = 0x02, ///< The Server Management Interface Chip.
   IPMIDeviceInfoInterfaceTypeBT            = 0x03, ///< The Block Transfer
-  IPMIDeviceInfoInterfaceTypeReserved      = 0x04
+  IPMIDeviceInfoInterfaceTypeSSIF          = 0x04  ///< SMBus System Interface
 } BMC_INTERFACE_TYPE;
 
 ///
@@ -2331,26 +2447,26 @@ typedef struct {
 } SMBIOS_TABLE_TYPE39;
 
 ///
-/// Additional Information Entry Format. 
+/// Additional Information Entry Format.
 ///
-typedef struct {                       
-  UINT8                   EntryLength; 
+typedef struct {
+  UINT8                   EntryLength;
   UINT16                  ReferencedHandle;
   UINT8                   ReferencedOffset;
   SMBIOS_TABLE_STRING     EntryString;
   UINT8                   Value[1];
-}ADDITIONAL_INFORMATION_ENTRY;
+} ADDITIONAL_INFORMATION_ENTRY;
 
 ///
 /// Additional Information (Type 40).
 ///
-/// This structure is intended to provide additional information for handling unspecified 
-/// enumerated values and interim field updates in another structure. 
+/// This structure is intended to provide additional information for handling unspecified
+/// enumerated values and interim field updates in another structure.
 ///
 typedef struct {
   SMBIOS_STRUCTURE                      Hdr;
   UINT8                                 NumberOfAdditionalInformationEntries;
-  ADDITIONAL_INFORMATION_ENTRY          AdditionalInfoEntries[1];  
+  ADDITIONAL_INFORMATION_ENTRY          AdditionalInfoEntries[1];
 } SMBIOS_TABLE_TYPE40;
 
 ///
@@ -2372,10 +2488,10 @@ typedef enum{
 ///
 /// Onboard Devices Extended Information (Type 41).
 ///
-/// The information in this structure defines the attributes of devices that 
-/// are onboard (soldered onto) a system element, usually the baseboard.  
-/// In general, an entry in this table implies that the BIOS has some level of 
-/// control over the enabling of the associated device for use by the system. 
+/// The information in this structure defines the attributes of devices that
+/// are onboard (soldered onto) a system element, usually the baseboard.
+/// In general, an entry in this table implies that the BIOS has some level of
+/// control over the enabling of the associated device for use by the system.
 ///
 typedef struct {
   SMBIOS_STRUCTURE                  Hdr;
@@ -2425,10 +2541,62 @@ typedef enum{
 ///
 typedef struct {
   SMBIOS_STRUCTURE                  Hdr;
-  UINT8                             InterfaceType;          ///< The enumeration value from MC_HOST_INTERFACE_TYPE
-  UINT8                             MCHostInterfaceData[1]; ///< This field has a minimum of four bytes
+  UINT8                             InterfaceType;                  ///< The enumeration value from MC_HOST_INTERFACE_TYPE
+  UINT8                             InterfaceTypeSpecificDataLength;
+  UINT8                             InterfaceTypeSpecificData[4];   ///< This field has a minimum of four bytes
 } SMBIOS_TABLE_TYPE42;
 
+
+///
+/// Processor Specific Block - Processor Architecture Type
+///
+typedef enum{
+  ProcessorSpecificBlockArchTypeReserved   = 0x00,
+  ProcessorSpecificBlockArchTypeIa32       = 0x01,
+  ProcessorSpecificBlockArchTypeX64        = 0x02,
+  ProcessorSpecificBlockArchTypeItanium    = 0x03,
+  ProcessorSpecificBlockArchTypeAarch32    = 0x04,
+  ProcessorSpecificBlockArchTypeAarch64    = 0x05,
+  ProcessorSpecificBlockArchTypeRiscVRV32  = 0x06,
+  ProcessorSpecificBlockArchTypeRiscVRV64  = 0x07,
+  ProcessorSpecificBlockArchTypeRiscVRV128 = 0x08
+} PROCESSOR_SPECIFIC_BLOCK_ARCH_TYPE;
+
+///
+/// Processor Specific Block is the standard container of processor-specific data.
+///
+typedef struct {
+  UINT8                              Length;
+  UINT8                              ProcessorArchType;
+  ///
+  /// Below followed by Processor-specific data
+  ///
+  ///
+} PROCESSOR_SPECIFIC_BLOCK;
+
+///
+/// Processor Additional Information(Type 44).
+///
+/// The information in this structure defines the processor additional information in case
+/// SMBIOS type 4 is not sufficient to describe processor characteristics.
+/// The SMBIOS type 44 structure has a reference handle field to link back to the related
+/// SMBIOS type 4 structure. There may be multiple SMBIOS type 44 structures linked to the
+/// same SMBIOS type 4 structure. For example, when cores are not identical in a processor,
+/// SMBIOS type 44 structures describe different core-specific information.
+///
+/// SMBIOS type 44 defines the standard header for the processor-specific block, while the
+/// contents of processor-specific data are maintained by processor
+/// architecture workgroups or vendors in separate documents.
+///
+typedef struct {
+  SMBIOS_STRUCTURE                  Hdr;
+  SMBIOS_HANDLE                     RefHandle;                 ///< This field refer to associated SMBIOS type 4
+  ///
+  /// Below followed by Processor-specific block
+  ///
+  PROCESSOR_SPECIFIC_BLOCK          ProcessorSpecificBlock;
+} SMBIOS_TABLE_TYPE44;
+
 ///
 /// TPM Device (Type 43).
 ///
@@ -2507,6 +2675,7 @@ typedef union {
   SMBIOS_TABLE_TYPE41   *Type41;
   SMBIOS_TABLE_TYPE42   *Type42;
   SMBIOS_TABLE_TYPE43   *Type43;
+  SMBIOS_TABLE_TYPE44   *Type44;
   SMBIOS_TABLE_TYPE126  *Type126;
   SMBIOS_TABLE_TYPE127  *Type127;
   UINT8                 *Raw;
diff --git a/MdePkg/Include/IndustryStandard/SmBus.h b/MdePkg/Include/IndustryStandard/SmBus.h
index be6851800c71..43bf6f5950af 100644
--- a/MdePkg/Include/IndustryStandard/SmBus.h
+++ b/MdePkg/Include/IndustryStandard/SmBus.h
@@ -1,15 +1,9 @@
 /** @file
-  This file declares the SMBus definitions defined in SmBus Specifciation V2.0
+  This file declares the SMBus definitions defined in SmBus Specification V2.0
   and defined in PI1.0 specification volume 5.
 
-  Copyright (c) 2007 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/IndustryStandard/Spdm.h b/MdePkg/Include/IndustryStandard/Spdm.h
new file mode 100644
index 000000000000..ff465253335d
--- /dev/null
+++ b/MdePkg/Include/IndustryStandard/Spdm.h
@@ -0,0 +1,320 @@
+/** @file
+  Definitions of Security Protocol & Data Model Specification (SPDM)
+  version 1.0.0 in Distributed Management Task Force (DMTF).
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+#ifndef __SPDM_H__
+#define __SPDM_H__
+
+#pragma pack(1)
+
+///
+/// SPDM response code
+///
+#define SPDM_DIGESTS               0x01
+#define SPDM_CERTIFICATE           0x02
+#define SPDM_CHALLENGE_AUTH        0x03
+#define SPDM_VERSION               0x04
+#define SPDM_MEASUREMENTS          0x60
+#define SPDM_CAPABILITIES          0x61
+#define SPDM_SET_CERT_RESPONSE     0x62
+#define SPDM_ALGORITHMS            0x63
+#define SPDM_ERROR                 0x7F
+///
+/// SPDM request code
+///
+#define SPDM_GET_DIGESTS           0x81
+#define SPDM_GET_CERTIFICATE       0x82
+#define SPDM_CHALLENGE             0x83
+#define SPDM_GET_VERSION           0x84
+#define SPDM_GET_MEASUREMENTS      0xE0
+#define SPDM_GET_CAPABILITIES      0xE1
+#define SPDM_NEGOTIATE_ALGORITHMS  0xE3
+#define SPDM_RESPOND_IF_READY      0xFF
+
+///
+/// SPDM message header
+///
+typedef struct {
+  UINT8   SPDMVersion;
+  UINT8   RequestResponseCode;
+  UINT8   Param1;
+  UINT8   Param2;
+} SPDM_MESSAGE_HEADER;
+
+#define SPDM_MESSAGE_VERSION  0x10
+
+///
+/// SPDM GET_VERSION request
+///
+typedef struct {
+  SPDM_MESSAGE_HEADER  Header;
+} SPDM_GET_VERSION_REQUEST;
+
+///
+/// SPDM GET_VERSION response
+///
+typedef struct {
+  SPDM_MESSAGE_HEADER  Header;
+  UINT8                Reserved;
+  UINT8                VersionNumberEntryCount;
+//SPDM_VERSION_NUMBER  VersionNumberEntry[VersionNumberEntryCount];
+} SPDM_VERSION_RESPONSE;
+
+///
+/// SPDM VERSION structure
+///
+typedef struct {
+  UINT16               Alpha:4;
+  UINT16               UpdateVersionNumber:4;
+  UINT16               MinorVersion:4;
+  UINT16               MajorVersion:4;
+} SPDM_VERSION_NUMBER;
+
+///
+/// SPDM GET_CAPABILITIES request
+///
+typedef struct {
+  SPDM_MESSAGE_HEADER  Header;
+} SPDM_GET_CAPABILITIES_REQUEST;
+
+///
+/// SPDM GET_CAPABILITIES response
+///
+typedef struct {
+  SPDM_MESSAGE_HEADER  Header;
+  UINT8                Reserved;
+  UINT8                CTExponent;
+  UINT16               Reserved2;
+  UINT32               Flags;
+} SPDM_CAPABILITIES_RESPONSE;
+
+///
+/// SPDM GET_CAPABILITIES response Flags
+///
+#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CACHE_CAP       BIT0
+#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CERT_CAP        BIT1
+#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CHAL_CAP        BIT2
+#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP        (BIT3 | BIT4)
+#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP_NO_SIG   BIT3
+#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP_SIG      BIT4
+#define SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_FRESH_CAP  BIT5
+
+///
+/// SPDM NEGOTIATE_ALGORITHMS request
+///
+typedef struct {
+  SPDM_MESSAGE_HEADER  Header;
+  UINT16               Length;
+  UINT8                MeasurementSpecification;
+  UINT8                Reserved;
+  UINT32               BaseAsymAlgo;
+  UINT32               BaseHashAlgo;
+  UINT8                Reserved2[12];
+  UINT8                ExtAsymCount;
+  UINT8                ExtHashCount;
+  UINT16               Reserved3;
+//UINT32               ExtAsym[ExtAsymCount];
+//UINT32               ExtHash[ExtHashCount];
+} SPDM_NEGOTIATE_ALGORITHMS_REQUEST;
+
+///
+/// SPDM NEGOTIATE_ALGORITHMS request BaseAsymAlgo
+///
+#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_2048           BIT0
+#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_2048           BIT1
+#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_3072           BIT2
+#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_3072           BIT3
+#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P256   BIT4
+#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSASSA_4096           BIT5
+#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_RSAPSS_4096           BIT6
+#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P384   BIT7
+#define SPDM_ALGORITHMS_BASE_ASYM_ALGO_TPM_ALG_ECDSA_ECC_NIST_P521   BIT8
+
+///
+/// SPDM NEGOTIATE_ALGORITHMS request BaseHashAlgo
+///
+#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_256               BIT0
+#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_384               BIT1
+#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA_512               BIT2
+#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_256              BIT3
+#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_384              BIT4
+#define SPDM_ALGORITHMS_BASE_HASH_ALGO_TPM_ALG_SHA3_512              BIT5
+
+///
+/// SPDM NEGOTIATE_ALGORITHMS response
+///
+typedef struct {
+  SPDM_MESSAGE_HEADER  Header;
+  UINT16               Length;
+  UINT8                MeasurementSpecificationSel;
+  UINT8                Reserved;
+  UINT32               MeasurementHashAlgo;
+  UINT32               BaseAsymSel;
+  UINT32               BaseHashSel;
+  UINT8                Reserved2[12];
+  UINT8                ExtAsymSelCount;
+  UINT8                ExtHashSelCount;
+  UINT16               Reserved3;
+//UINT32               ExtAsymSel[ExtAsymSelCount];
+//UINT32               ExtHashSel[ExtHashSelCount];
+} SPDM_ALGORITHMS_RESPONSE;
+
+///
+/// SPDM NEGOTIATE_ALGORITHMS response MeasurementHashAlgo
+///
+#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_RAW_BIT_STREAM_ONLY BIT0
+#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA_256     BIT1
+#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA_384     BIT2
+#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA_512     BIT3
+#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA3_256    BIT4
+#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA3_384    BIT5
+#define SPDM_ALGORITHMS_MEASUREMENT_HASH_ALGO_TPM_ALG_SHA3_512    BIT6
+
+///
+/// SPDM GET_DIGESTS request
+///
+typedef struct {
+  SPDM_MESSAGE_HEADER  Header;
+} SPDM_GET_DIGESTS_REQUEST;
+
+///
+/// SPDM GET_DIGESTS response
+///
+typedef struct {
+  SPDM_MESSAGE_HEADER  Header;
+//UINT8                Digest[DigestSize];
+} SPDM_DIGESTS_RESPONSE;
+
+///
+/// SPDM GET_DIGESTS request
+///
+typedef struct {
+  SPDM_MESSAGE_HEADER  Header;
+  UINT16               Offset;
+  UINT16               Length;
+} SPDM_GET_CERTIFICATE_REQUEST;
+
+///
+/// SPDM GET_DIGESTS response
+///
+typedef struct {
+  SPDM_MESSAGE_HEADER  Header;
+  UINT16               PortionLength;
+  UINT16               RemainderLength;
+//UINT8                CertChain[CertChainSize];
+} SPDM_CERTIFICATE_RESPONSE;
+
+///
+/// SPDM CHALLENGE request
+///
+typedef struct {
+  SPDM_MESSAGE_HEADER  Header;
+  UINT8                Nonce[32];
+} SPDM_CHALLENGE_REQUEST;
+
+///
+/// SPDM CHALLENGE response
+///
+typedef struct {
+  SPDM_MESSAGE_HEADER  Header;
+//UINT8                CertChainHash[DigestSize];
+//UINT8                Nonce[32];
+//UINT8                MeasurementSummaryHash[DigestSize];
+//UINT16               OpaqueLength;
+//UINT8                OpaqueData[OpaqueLength];
+//UINT8                Signature[KeySize];
+} SPDM_CHALLENGE_AUTH_RESPONSE;
+
+///
+/// SPDM GET_MEASUREMENTS request
+///
+typedef struct {
+  SPDM_MESSAGE_HEADER  Header;
+  UINT8                Nonce[32];
+} SPDM_GET_MEASUREMENTS_REQUEST;
+
+///
+/// SPDM MEASUREMENTS block common header
+///
+typedef struct {
+  UINT8                Index;
+  UINT8                MeasurementSpecification;
+  UINT16               MeasurementSize;
+//UINT8                Measurement[MeasurementSize];
+} SPDM_MEASUREMENT_BLOCK_COMMON_HEADER;
+
+#define SPDM_MEASUREMENT_BLOCK_HEADER_SPECIFICATION_DMTF BIT0
+
+///
+/// SPDM MEASUREMENTS block DMTF header
+///
+typedef struct {
+  UINT8                DMTFSpecMeasurementValueType;
+  UINT16               DMTFSpecMeasurementValueSize;
+//UINT8                DMTFSpecMeasurementValue[DMTFSpecMeasurementValueSize];
+} SPDM_MEASUREMENT_BLOCK_DMTF_HEADER;
+
+///
+/// SPDM MEASUREMENTS block MeasurementValueType
+///
+#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_TYPE_IMMUTABLE_ROM           0
+#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_TYPE_MUTABLE_FIRMWARE        1
+#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_TYPE_HARDWARE_CONFIGURATION  2
+#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_TYPE_FIRMWARE_CONFIGURATION  3
+#define SPDM_MEASUREMENT_BLOCK_MEASUREMENT_TYPE_RAW_BIT_STREAM          BIT7
+
+///
+/// SPDM GET_MEASUREMENTS response
+///
+typedef struct {
+  SPDM_MESSAGE_HEADER  Header;
+  UINT8                NumberOfBlocks;
+  UINT8                MeasurementRecordLength[3];
+//UINT8                MeasurementRecord[MeasurementRecordLength];
+//UINT8                Nonce[32];
+//UINT16               OpaqueLength;
+//UINT8                OpaqueData[OpaqueLength];
+//UINT8                Signature[KeySize];
+} SPDM_MEASUREMENTS_RESPONSE;
+
+///
+/// SPDM ERROR response
+///
+typedef struct {
+  SPDM_MESSAGE_HEADER  Header;
+  // Param1 == Error Code
+  // Param2 == Error Data
+//UINT8                ExtendedErrorData[];
+} SPDM_ERROR_RESPONSE;
+
+///
+/// SPDM error code
+///
+#define SPDM_ERROR_CODE_INVALID_REQUEST         0x01
+#define SPDM_ERROR_CODE_BUSY                    0x03
+#define SPDM_ERROR_CODE_UNEXPECTED_REQUEST      0x04
+#define SPDM_ERROR_CODE_UNSPECIFIED             0x05
+#define SPDM_ERROR_CODE_UNSUPPORTED_REQUEST     0x07
+#define SPDM_ERROR_CODE_MAJOR_VERSION_MISMATCH  0x41
+#define SPDM_ERROR_CODE_RESPONSE_NOT_READY      0x42
+#define SPDM_ERROR_CODE_REQUEST_RESYNCH         0x43
+
+///
+/// SPDM RESPONSE_IF_READY request
+///
+typedef struct {
+  SPDM_MESSAGE_HEADER  Header;
+  // Param1 == RequestCode
+  // Param2 == Token
+} SPDM_RESPONSE_IF_READY_REQUEST;
+
+#pragma pack()
+
+#endif
+
diff --git a/MdePkg/Include/IndustryStandard/TcgPhysicalPresence.h b/MdePkg/Include/IndustryStandard/TcgPhysicalPresence.h
index 23d7a09c44fa..f35c1f51a3ff 100644
--- a/MdePkg/Include/IndustryStandard/TcgPhysicalPresence.h
+++ b/MdePkg/Include/IndustryStandard/TcgPhysicalPresence.h
@@ -1,14 +1,8 @@
 /** @file
   TCG Physical Presence definition.
 
-Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials 
-are licensed and made available under the terms and conditions of the BSD License 
-which accompanies this distribution.  The full text of the license may be found at 
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -65,7 +59,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #define TCG_PHYSICAL_PRESENCE_ENABLE                                  1
 #define TCG_PHYSICAL_PRESENCE_DISABLE                                 2
 #define TCG_PHYSICAL_PRESENCE_ACTIVATE                                3
-#define TCG_PHYSICAL_PRESENCE_DEACTIVATE                              4 
+#define TCG_PHYSICAL_PRESENCE_DEACTIVATE                              4
 #define TCG_PHYSICAL_PRESENCE_CLEAR                                   5
 #define TCG_PHYSICAL_PRESENCE_ENABLE_ACTIVATE                         6
 #define TCG_PHYSICAL_PRESENCE_DEACTIVATE_DISABLE                      7
diff --git a/MdePkg/Include/IndustryStandard/TcgStorageCore.h b/MdePkg/Include/IndustryStandard/TcgStorageCore.h
index 79954df5ad37..a9c1332d2d24 100644
--- a/MdePkg/Include/IndustryStandard/TcgStorageCore.h
+++ b/MdePkg/Include/IndustryStandard/TcgStorageCore.h
@@ -1,14 +1,13 @@
 /** @file
   TCG defined values and structures.
 
-Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
+  (TCG Storage Architecture Core Specification, Version 2.01, Revision 1.00,
+  https://trustedcomputinggroup.org/tcg-storage-architecture-core-specification/)
 
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Check http://trustedcomputinggroup.org for latest specification updates.
+
+Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -228,7 +227,9 @@ typedef enum {
 #define TCG_FEATURE_OPAL_SSC_V2_0_0     (UINT16)0x0203
 #define TCG_FEATURE_OPAL_SSC_LITE       (UINT16)0x0301
 #define TCG_FEATURE_PYRITE_SSC          (UINT16)0x0302
+#define TCG_FEATURE_PYRITE_SSC_V2_0_0   (UINT16)0x0303
 #define TCG_FEATURE_BLOCK_SID           (UINT16)0x0402
+#define TCG_FEATURE_DATA_REMOVAL        (UINT16)0x0404
 
 // ACE Expression values
 #define TCG_ACE_EXPRESSION_AND 0x0
diff --git a/MdePkg/Include/IndustryStandard/TcgStorageOpal.h b/MdePkg/Include/IndustryStandard/TcgStorageOpal.h
index 1f32b7ecca6b..cd83e32b10fb 100644
--- a/MdePkg/Include/IndustryStandard/TcgStorageOpal.h
+++ b/MdePkg/Include/IndustryStandard/TcgStorageOpal.h
@@ -1,14 +1,22 @@
 /** @file
   Opal Specification defined values and structures.
 
-Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
+  (TCG Storage Architecture Core Specification, Version 2.01, Revision 1.00,
+  https://trustedcomputinggroup.org/tcg-storage-architecture-core-specification/
 
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Storage Work Group Storage Security Subsystem Class: Pyrite, Version 1.00 Final, Revision 1.00,
+  https://trustedcomputinggroup.org/tcg-storage-security-subsystem-class-pyrite/
+
+  Storage Work Group Storage Security Subsystem Class: Opal, Version 2.01 Final, Revision 1.00,
+  https://trustedcomputinggroup.org/storage-work-group-storage-security-subsystem-class-opal/
+
+  TCG Storage Security Subsystem Class: Opalite Version 1.00 Revision 1.00,
+  https://trustedcomputinggroup.org/tcg-storage-security-subsystem-class-opalite/)
+
+  Check http://trustedcomputinggroup.org for latest specification updates.
+
+Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -34,6 +42,9 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #define OPAL_ADMIN_SP_ACTIVATE_METHOD       TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x02, 0x03)
 #define OPAL_ADMIN_SP_REVERT_METHOD         TCG_TO_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x02, 0x02)
 
+// ADMIN_SP
+// Data Removal mechanism
+#define OPAL_UID_ADMIN_SP_DATA_REMOVAL_MECHANISM  TCG_TO_UID(0x00, 0x00, 0x11, 0x01, 0x00, 0x00, 0x00, 0x01)
 
 // LOCKING SP
 // Authorities
@@ -93,6 +104,23 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #define OPAL_LOCKING_SP_C_PIN_TRYLIMIT_COL 5
 #define OPAL_RANDOM_METHOD_MAX_COUNT_SIZE 32
 
+// Data Removal Mechanism column.
+#define OPAL_ADMIN_SP_ACTIVE_DATA_REMOVAL_MECHANISM_COL  1
+
+//
+// Supported Data Removal Mechanism.
+// Detail see Pyrite SSC v2 spec.
+//
+typedef enum {
+  OverwriteDataErase = 0,
+  BlockErase,
+  CryptoErase,
+  Unmap,
+  ResetWritePointers,
+  VendorSpecificErase,
+  ResearvedMechanism
+} SUPPORTED_DATA_REMOVAL_MECHANISM;
+
 #pragma pack(1)
 
 typedef struct _OPAL_GEOMETRY_REPORTING_FEATURE {
@@ -162,6 +190,38 @@ typedef struct _PYRITE_SSC_FEATURE_DESCRIPTOR {
   UINT8                                Future[5];
 } PYRITE_SSC_FEATURE_DESCRIPTOR;
 
+typedef struct _PYRITE_SSCV2_FEATURE_DESCRIPTOR {
+  TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;
+  UINT16                               BaseComdIdBE;
+  UINT16                               NumComIdsBE;
+  UINT8                                Reserved[5];
+  UINT8                                InitialCPINSIDPIN;
+  UINT8                                CPINSIDPINRevertBehavior;
+  UINT8                                Future[5];
+} PYRITE_SSCV2_FEATURE_DESCRIPTOR;
+
+typedef struct _DATA_REMOVAL_FEATURE_DESCRIPTOR {
+  TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER Header;
+  UINT8                                Reserved;
+  UINT8                                OperationProcessing : 1;
+  UINT8                                Reserved2 : 7;
+  UINT8                                RemovalMechanism;
+  UINT8                                FormatBit0 : 1;   // Data Removal Time Format for Bit 0
+  UINT8                                FormatBit1 : 1;   // Data Removal Time Format for Bit 1
+  UINT8                                FormatBit2 : 1;   // Data Removal Time Format for Bit 2
+  UINT8                                FormatBit3 : 1;   // Data Removal Time Format for Bit 3
+  UINT8                                FormatBit4 : 1;   // Data Removal Time Format for Bit 4
+  UINT8                                FormatBit5 : 1;   // Data Removal Time Format for Bit 5
+  UINT8                                Reserved3 : 2;
+  UINT16                               TimeBit0;         // Data Removal Time for Supported Data Removal Mechanism Bit 0
+  UINT16                               TimeBit1;         // Data Removal Time for Supported Data Removal Mechanism Bit 1
+  UINT16                               TimeBit2;         // Data Removal Time for Supported Data Removal Mechanism Bit 2
+  UINT16                               TimeBit3;         // Data Removal Time for Supported Data Removal Mechanism Bit 3
+  UINT16                               TimeBit4;         // Data Removal Time for Supported Data Removal Mechanism Bit 4
+  UINT16                               TimeBit5;         // Data Removal Time for Supported Data Removal Mechanism Bit 5
+  UINT8                                Future[16];
+} DATA_REMOVAL_FEATURE_DESCRIPTOR;
+
 typedef union {
   TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER     CommonHeader;
   TCG_TPER_FEATURE_DESCRIPTOR              Tper;
@@ -173,7 +233,9 @@ typedef union {
   OPAL_SSCV2_FEATURE_DESCRIPTOR            OpalSscV2;
   OPAL_SSCLITE_FEATURE_DESCRIPTOR          OpalSscLite;
   PYRITE_SSC_FEATURE_DESCRIPTOR            PyriteSsc;
+  PYRITE_SSCV2_FEATURE_DESCRIPTOR          PyriteSscV2;
   TCG_BLOCK_SID_FEATURE_DESCRIPTOR         BlockSid;
+  DATA_REMOVAL_FEATURE_DESCRIPTOR          DataRemoval;
 } OPAL_LEVEL0_FEATURE_DESCRIPTOR;
 
 #pragma pack()
diff --git a/MdePkg/Include/IndustryStandard/TcpaAcpi.h b/MdePkg/Include/IndustryStandard/TcpaAcpi.h
index fde31ab8b23a..4b02c9158789 100644
--- a/MdePkg/Include/IndustryStandard/TcpaAcpi.h
+++ b/MdePkg/Include/IndustryStandard/TcpaAcpi.h
@@ -2,13 +2,7 @@
   TCPA ACPI table definition.
 
 Copyright (c) 2013, Intel Corporation. All rights reserved. <BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/IndustryStandard/Tls1.h b/MdePkg/Include/IndustryStandard/Tls1.h
index 019ff617de22..9d98bbbe2800 100644
--- a/MdePkg/Include/IndustryStandard/Tls1.h
+++ b/MdePkg/Include/IndustryStandard/Tls1.h
@@ -1,16 +1,10 @@
 /** @file
-  Transport Layer Security  -- TLS 1.0/1.1/1.2 Standard definitions, from RFC 2246/4346/5246    
+  Transport Layer Security  -- TLS 1.0/1.1/1.2 Standard definitions, from RFC 2246/4346/5246
 
-  This file contains common TLS 1.0/1.1/1.2 definitions from RFC 2246/4346/5246 
+  This file contains common TLS 1.0/1.1/1.2 definitions from RFC 2246/4346/5246
 
-  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
 #ifndef __TLS_1_H__
@@ -81,12 +75,26 @@ typedef enum {
 ///
 /// TLS Record Header, refers to A.1 of rfc-2246, rfc-4346 and rfc-5246.
 ///
-typedef struct {   
+typedef struct {
   UINT8                   ContentType;
   EFI_TLS_VERSION         Version;
   UINT16                  Length;
 } TLS_RECORD_HEADER;
 
+#define TLS_RECORD_HEADER_LENGTH   5
+
+//
+// The length (in bytes) of the TLSPlaintext records payload MUST NOT exceed 2^14.
+// Refers to section 6.2 of RFC5246.
+//
+#define TLS_PLAINTEXT_RECORD_MAX_PAYLOAD_LENGTH   16384
+
+//
+// The length (in bytes) of the TLSCiphertext records payload MUST NOT exceed 2^14 + 2048.
+// Refers to section 6.2 of RFC5246.
+//
+#define TLS_CIPHERTEXT_RECORD_MAX_PAYLOAD_LENGTH   18432
+
 #pragma pack()
 
 #endif
diff --git a/MdePkg/Include/IndustryStandard/Tpm12.h b/MdePkg/Include/IndustryStandard/Tpm12.h
index 0736c02a8004..4ac86c4c9d1a 100644
--- a/MdePkg/Include/IndustryStandard/Tpm12.h
+++ b/MdePkg/Include/IndustryStandard/Tpm12.h
@@ -1,15 +1,9 @@
-/** @file   
+/** @file
   TPM Specification data structures (TCG TPM Specification Version 1.2 Revision 103)
   See http://trustedcomputinggroup.org for latest specification updates
 
-  Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
 
@@ -155,8 +149,8 @@ typedef UINT32                      TPM_KEY_CONTROL;
 ///
 typedef UINT32                      TPM_NV_INDEX;
 ///
-/// The family ID. Family IDs are automatically assigned a sequence number by the TPM. 
-/// A trusted process can set the FamilyID value in an individual row to NULL, which 
+/// The family ID. Family IDs are automatically assigned a sequence number by the TPM.
+/// A trusted process can set the FamilyID value in an individual row to NULL, which
 /// invalidates that row. The family ID resets to NULL on each change of TPM Owner.
 ///
 typedef UINT32                      TPM_FAMILY_ID;
@@ -603,7 +597,7 @@ typedef struct tdTPM_CHANGEAUTH_VALIDATE {
 
 ///
 /// Part 2, section 5.12: TPM_MIGRATIONKEYAUTH
-///   decalared after section 10 to catch declaration of TPM_PUBKEY
+///   declared after section 10 to catch declaration of TPM_PUBKEY
 ///
 /// Part 2 section 10.1: TPM_KEY_PARMS
 ///   [size_is(parmSize)] BYTE* parms;
@@ -826,7 +820,7 @@ typedef struct tdTPM_STANY_FLAGS{
 #define TPM_AF_TOSPRESENT           ((TPM_CAPABILITY_AREA) 4)
 
 //
-// All those structures defined in section 7.4, 7.5, 7.6 are not normative and 
+// All those structures defined in section 7.4, 7.5, 7.6 are not normative and
 // thus no definitions here
 //
 // Part 2, section 7.4: TPM_PERMANENT_DATA
@@ -901,7 +895,7 @@ typedef struct tdTPM_STANY_FLAGS{
 
 //
 // Part 2, section 8: PCR Structures
-// 
+//
 
 ///
 /// Part 2, section 8.1: TPM_PCR_SELECTION
@@ -1039,7 +1033,7 @@ typedef struct tdTPM_BOUND_DATA {
 
 //
 // Part 2 section 10: TPM_KEY complex
-// 
+//
 
 //
 // Section 10.1, 10.4, and 10.5 have been defined previously
diff --git a/MdePkg/Include/IndustryStandard/Tpm20.h b/MdePkg/Include/IndustryStandard/Tpm20.h
index 697a2d7be408..39332b15e83d 100644
--- a/MdePkg/Include/IndustryStandard/Tpm20.h
+++ b/MdePkg/Include/IndustryStandard/Tpm20.h
@@ -6,13 +6,7 @@
   Check http://trustedcomputinggroup.org for latest specification updates.
 
 Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved. <BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/IndustryStandard/Tpm2Acpi.h b/MdePkg/Include/IndustryStandard/Tpm2Acpi.h
index b5d5e522dd56..f52b7c7fd471 100644
--- a/MdePkg/Include/IndustryStandard/Tpm2Acpi.h
+++ b/MdePkg/Include/IndustryStandard/Tpm2Acpi.h
@@ -1,14 +1,8 @@
 /** @file
   TPM2 ACPI table definition.
 
-Copyright (c) 2013 - 2017, Intel Corporation. All rights reserved. <BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2013 - 2019, Intel Corporation. All rights reserved. <BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -31,13 +25,16 @@ typedef struct {
   UINT32                      Flags;
   UINT64                      AddressOfControlArea;
   UINT32                      StartMethod;
-//UINT8                       PlatformSpecificParameters[];
+//UINT8                       PlatformSpecificParameters[];  // size up to 12
+//UINT32                      Laml;                          // Optional
+//UINT64                      Lasa;                          // Optional
 } EFI_TPM2_ACPI_TABLE;
 
 #define EFI_TPM2_ACPI_TABLE_START_METHOD_ACPI                                          2
 #define EFI_TPM2_ACPI_TABLE_START_METHOD_TIS                                           6
 #define EFI_TPM2_ACPI_TABLE_START_METHOD_COMMAND_RESPONSE_BUFFER_INTERFACE             7
 #define EFI_TPM2_ACPI_TABLE_START_METHOD_COMMAND_RESPONSE_BUFFER_INTERFACE_WITH_ACPI   8
+#define EFI_TPM2_ACPI_TABLE_START_METHOD_COMMAND_RESPONSE_BUFFER_INTERFACE_WITH_SMC    11
 
 typedef struct {
   UINT32   Reserved;
diff --git a/MdePkg/Include/IndustryStandard/TpmPtp.h b/MdePkg/Include/IndustryStandard/TpmPtp.h
index f4c6b0676bc6..4481a0891b27 100644
--- a/MdePkg/Include/IndustryStandard/TpmPtp.h
+++ b/MdePkg/Include/IndustryStandard/TpmPtp.h
@@ -2,14 +2,8 @@
   Platform TPM Profile Specification definition for TPM2.0.
   It covers both FIFO and CRB interface.
 
-Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -338,7 +332,8 @@ typedef union {
     UINT32   InterfaceType:4;
     UINT32   InterfaceVersion:4;
     UINT32   CapLocality:1;
-    UINT32   Reserved1:2;
+    UINT32   CapCRBIdleBypass:1;
+    UINT32   Reserved1:1;
     UINT32   CapDataXferSizeSupport:2;
     UINT32   CapFIFO:1;
     UINT32   CapCRB:1;
@@ -519,4 +514,4 @@ typedef union {
 #define PTP_TIMEOUT_C               (200 * 1000)   // 200ms
 #define PTP_TIMEOUT_D               (30 * 1000)    // 30ms
 
-#endif
\ No newline at end of file
+#endif
diff --git a/MdePkg/Include/IndustryStandard/TpmTis.h b/MdePkg/Include/IndustryStandard/TpmTis.h
index 1e1d23725d08..85c2969cc3df 100644
--- a/MdePkg/Include/IndustryStandard/TpmTis.h
+++ b/MdePkg/Include/IndustryStandard/TpmTis.h
@@ -2,14 +2,8 @@
   TPM Interface Specification definition.
   It covers both TPM1.2 and TPM2.0.
 
-Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -143,6 +137,10 @@ typedef TIS_PC_REGISTERS  *TIS_PC_REGISTERS_PTR;
 #define TIS_PC_ACC_ESTABLISH        BIT0
 
 ///
+/// Write a 1 to this bit to notify TPM to cancel currently executing command
+///
+#define TIS_PC_STS_CANCEL           BIT24
+///
 /// This field indicates that STS_DATA and STS_EXPECT are valid
 ///
 #define TIS_PC_STS_VALID            BIT7
@@ -180,4 +178,4 @@ typedef TIS_PC_REGISTERS  *TIS_PC_REGISTERS_PTR;
 #define TIS_TIMEOUT_C               (750  * 1000)  // 750ms
 #define TIS_TIMEOUT_D               (750  * 1000)  // 750ms
 
-#endif
\ No newline at end of file
+#endif
diff --git a/MdePkg/Include/IndustryStandard/Udf.h b/MdePkg/Include/IndustryStandard/Udf.h
new file mode 100644
index 000000000000..e299b7559929
--- /dev/null
+++ b/MdePkg/Include/IndustryStandard/Udf.h
@@ -0,0 +1,141 @@
+/** @file
+  OSTA Universal Disk Format (UDF) definitions.
+
+  Copyright (C) 2014-2017 Paulo Alcantara <pcacjr@zytor.com>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __UDF_H__
+#define __UDF_H__
+
+#define UDF_BEA_IDENTIFIER   "BEA01"
+#define UDF_NSR2_IDENTIFIER  "NSR02"
+#define UDF_NSR3_IDENTIFIER  "NSR03"
+#define UDF_TEA_IDENTIFIER   "TEA01"
+
+#define UDF_LOGICAL_SECTOR_SHIFT  11
+#define UDF_LOGICAL_SECTOR_SIZE   ((UINT64)(1ULL << UDF_LOGICAL_SECTOR_SHIFT))
+#define UDF_VRS_START_OFFSET      ((UINT64)(16ULL << UDF_LOGICAL_SECTOR_SHIFT))
+
+typedef enum {
+  UdfPrimaryVolumeDescriptor = 1,
+  UdfAnchorVolumeDescriptorPointer = 2,
+  UdfVolumeDescriptorPointer = 3,
+  UdfImplemenationUseVolumeDescriptor = 4,
+  UdfPartitionDescriptor = 5,
+  UdfLogicalVolumeDescriptor = 6,
+  UdfUnallocatedSpaceDescriptor = 7,
+  UdfTerminatingDescriptor = 8,
+  UdfLogicalVolumeIntegrityDescriptor = 9,
+  UdfFileSetDescriptor = 256,
+  UdfFileIdentifierDescriptor = 257,
+  UdfAllocationExtentDescriptor = 258,
+  UdfFileEntry = 261,
+  UdfExtendedFileEntry = 266,
+} UDF_VOLUME_DESCRIPTOR_ID;
+
+#pragma pack(1)
+
+typedef struct {
+  UINT16  TagIdentifier;
+  UINT16  DescriptorVersion;
+  UINT8   TagChecksum;
+  UINT8   Reserved;
+  UINT16  TagSerialNumber;
+  UINT16  DescriptorCRC;
+  UINT16  DescriptorCRCLength;
+  UINT32  TagLocation;
+} UDF_DESCRIPTOR_TAG;
+
+typedef struct {
+  UINT32  ExtentLength;
+  UINT32  ExtentLocation;
+} UDF_EXTENT_AD;
+
+typedef struct {
+  UINT8           CharacterSetType;
+  UINT8           CharacterSetInfo[63];
+} UDF_CHAR_SPEC;
+
+typedef struct {
+  UINT8           Flags;
+  UINT8           Identifier[23];
+  union {
+    //
+    // Domain Entity Identifier
+    //
+    struct {
+      UINT16      UdfRevision;
+      UINT8       DomainFlags;
+      UINT8       Reserved[5];
+    } Domain;
+    //
+    // UDF Entity Identifier
+    //
+    struct {
+      UINT16      UdfRevision;
+      UINT8       OSClass;
+      UINT8       OSIdentifier;
+      UINT8       Reserved[4];
+    } Entity;
+    //
+    // Implementation Entity Identifier
+    //
+    struct {
+      UINT8       OSClass;
+      UINT8       OSIdentifier;
+      UINT8       ImplementationUseArea[6];
+    } ImplementationEntity;
+    //
+    // Application Entity Identifier
+    //
+    struct {
+      UINT8       ApplicationUseArea[8];
+    } ApplicationEntity;
+    //
+    // Raw Identifier Suffix
+    //
+    struct {
+      UINT8       Data[8];
+    } Raw;
+  } Suffix;
+} UDF_ENTITY_ID;
+
+typedef struct {
+  UINT32        LogicalBlockNumber;
+  UINT16        PartitionReferenceNumber;
+} UDF_LB_ADDR;
+
+typedef struct {
+  UINT32                           ExtentLength;
+  UDF_LB_ADDR                      ExtentLocation;
+  UINT8                            ImplementationUse[6];
+} UDF_LONG_ALLOCATION_DESCRIPTOR;
+
+typedef struct {
+  UDF_DESCRIPTOR_TAG  DescriptorTag;
+  UDF_EXTENT_AD       MainVolumeDescriptorSequenceExtent;
+  UDF_EXTENT_AD       ReserveVolumeDescriptorSequenceExtent;
+  UINT8               Reserved[480];
+} UDF_ANCHOR_VOLUME_DESCRIPTOR_POINTER;
+
+typedef struct {
+  UDF_DESCRIPTOR_TAG              DescriptorTag;
+  UINT32                          VolumeDescriptorSequenceNumber;
+  UDF_CHAR_SPEC                   DescriptorCharacterSet;
+  UINT8                           LogicalVolumeIdentifier[128];
+  UINT32                          LogicalBlockSize;
+  UDF_ENTITY_ID                   DomainIdentifier;
+  UDF_LONG_ALLOCATION_DESCRIPTOR  LogicalVolumeContentsUse;
+  UINT32                          MapTableLength;
+  UINT32                          NumberOfPartitionMaps;
+  UDF_ENTITY_ID                   ImplementationIdentifier;
+  UINT8                           ImplementationUse[128];
+  UDF_EXTENT_AD                   IntegritySequenceExtent;
+  UINT8                           PartitionMaps[6];
+} UDF_LOGICAL_VOLUME_DESCRIPTOR;
+
+#pragma pack()
+
+#endif
diff --git a/MdePkg/Include/IndustryStandard/UefiTcgPlatform.h b/MdePkg/Include/IndustryStandard/UefiTcgPlatform.h
index 0a7469ad4177..dc97358c8f1e 100644
--- a/MdePkg/Include/IndustryStandard/UefiTcgPlatform.h
+++ b/MdePkg/Include/IndustryStandard/UefiTcgPlatform.h
@@ -1,14 +1,9 @@
 /** @file
-  TCG EFI Platform Definition in TCG_EFI_Platform_1_20_Final
+  TCG EFI Platform Definition in TCG_EFI_Platform_1_20_Final and
+  TCG PC Client Platform Firmware Profile Specification, Revision 1.05
 
-  Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -22,13 +17,22 @@
 //
 // Standard event types
 //
+#define EV_PREBOOT_CERT             ((TCG_EVENTTYPE) 0x00000000)
 #define EV_POST_CODE                ((TCG_EVENTTYPE) 0x00000001)
 #define EV_NO_ACTION                ((TCG_EVENTTYPE) 0x00000003)
 #define EV_SEPARATOR                ((TCG_EVENTTYPE) 0x00000004)
+#define EV_ACTION                   ((TCG_EVENTTYPE) 0x00000005)
+#define EV_EVENT_TAG                ((TCG_EVENTTYPE) 0x00000006)
 #define EV_S_CRTM_CONTENTS          ((TCG_EVENTTYPE) 0x00000007)
 #define EV_S_CRTM_VERSION           ((TCG_EVENTTYPE) 0x00000008)
 #define EV_CPU_MICROCODE            ((TCG_EVENTTYPE) 0x00000009)
+#define EV_PLATFORM_CONFIG_FLAGS    ((TCG_EVENTTYPE) 0x0000000A)
 #define EV_TABLE_OF_DEVICES         ((TCG_EVENTTYPE) 0x0000000B)
+#define EV_COMPACT_HASH             ((TCG_EVENTTYPE) 0x0000000C)
+#define EV_NONHOST_CODE             ((TCG_EVENTTYPE) 0x0000000F)
+#define EV_NONHOST_CONFIG           ((TCG_EVENTTYPE) 0x00000010)
+#define EV_NONHOST_INFO             ((TCG_EVENTTYPE) 0x00000011)
+#define EV_OMIT_BOOT_DEVICE_EVENTS  ((TCG_EVENTTYPE) 0x00000012)
 
 //
 // EFI specific event types
@@ -43,11 +47,16 @@
 #define EV_EFI_ACTION                       (EV_EFI_EVENT_BASE + 7)
 #define EV_EFI_PLATFORM_FIRMWARE_BLOB       (EV_EFI_EVENT_BASE + 8)
 #define EV_EFI_HANDOFF_TABLES               (EV_EFI_EVENT_BASE + 9)
+#define EV_EFI_PLATFORM_FIRMWARE_BLOB2      (EV_EFI_EVENT_BASE + 0xA)
+#define EV_EFI_HANDOFF_TABLES2              (EV_EFI_EVENT_BASE + 0xB)
+#define EV_EFI_HCRTM_EVENT                  (EV_EFI_EVENT_BASE + 0x10)
 #define EV_EFI_VARIABLE_AUTHORITY           (EV_EFI_EVENT_BASE + 0xE0)
+#define EV_EFI_SPDM_FIRMWARE_BLOB           (EV_EFI_EVENT_BASE + 0xE1)
+#define EV_EFI_SPDM_FIRMWARE_CONFIG         (EV_EFI_EVENT_BASE + 0xE2)
 
 #define EFI_CALLING_EFI_APPLICATION         \
   "Calling EFI Application from Boot Option"
-#define EFI_RETURNING_FROM_EFI_APPLICATOIN  \
+#define EFI_RETURNING_FROM_EFI_APPLICATION  \
   "Returning from EFI Application from Boot Option"
 #define EFI_EXIT_BOOT_SERVICES_INVOCATION   \
   "Exit Boot Services Invocation"
@@ -75,6 +84,9 @@
 #define EV_POSTCODE_INFO_OPROM        "Embedded Option ROM"
 #define OPROM_LEN                     (sizeof(EV_POSTCODE_INFO_OPROM) - 1)
 
+#define EV_POSTCODE_INFO_EMBEDDED_UEFI_DRIVER  "Embedded UEFI Driver"
+#define EMBEDDED_UEFI_DRIVER_LEN               (sizeof(EV_POSTCODE_INFO_EMBEDDED_UEFI_DRIVER) - 1)
+
 #define FIRMWARE_DEBUGGER_EVENT_STRING      "UEFI Debug Mode"
 #define FIRMWARE_DEBUGGER_EVENT_STRING_LEN  (sizeof(FIRMWARE_DEBUGGER_EVENT_STRING) - 1)
 
@@ -121,6 +133,30 @@ typedef struct tdEFI_PLATFORM_FIRMWARE_BLOB {
 } EFI_PLATFORM_FIRMWARE_BLOB;
 
 ///
+/// UEFI_PLATFORM_FIRMWARE_BLOB
+///
+/// This structure is used in EV_EFI_PLATFORM_FIRMWARE_BLOB
+/// event to facilitate the measurement of firmware volume.
+///
+typedef struct tdUEFI_PLATFORM_FIRMWARE_BLOB {
+  EFI_PHYSICAL_ADDRESS              BlobBase;
+  UINT64                            BlobLength;
+} UEFI_PLATFORM_FIRMWARE_BLOB;
+
+///
+/// UEFI_PLATFORM_FIRMWARE_BLOB2
+///
+/// This structure is used in EV_EFI_PLATFORM_FIRMWARE_BLOB2
+/// event to facilitate the measurement of firmware volume.
+///
+typedef struct tdUEFI_PLATFORM_FIRMWARE_BLOB2 {
+  UINT8                             BlobDescriptionSize;
+//UINT8                             BlobDescription[BlobDescriptionSize];
+//EFI_PHYSICAL_ADDRESS              BlobBase;
+//UINT64                            BlobLength;
+} UEFI_PLATFORM_FIRMWARE_BLOB2;
+
+///
 /// EFI_IMAGE_LOAD_EVENT
 ///
 /// This structure is used in EV_EFI_BOOT_SERVICES_APPLICATION,
@@ -135,6 +171,20 @@ typedef struct tdEFI_IMAGE_LOAD_EVENT {
 } EFI_IMAGE_LOAD_EVENT;
 
 ///
+/// UEFI_IMAGE_LOAD_EVENT
+///
+/// This structure is used in EV_EFI_BOOT_SERVICES_APPLICATION,
+/// EV_EFI_BOOT_SERVICES_DRIVER and EV_EFI_RUNTIME_SERVICES_DRIVER
+///
+typedef struct tdUEFI_IMAGE_LOAD_EVENT {
+  EFI_PHYSICAL_ADDRESS              ImageLocationInMemory;
+  UINT64                            ImageLengthInMemory;
+  UINT64                            ImageLinkTimeAddress;
+  UINT64                            LengthOfDevicePath;
+  EFI_DEVICE_PATH_PROTOCOL          DevicePath[1];
+} UEFI_IMAGE_LOAD_EVENT;
+
+///
 /// EFI_HANDOFF_TABLE_POINTERS
 ///
 /// This structure is used in EV_EFI_HANDOFF_TABLES event to facilitate
@@ -146,6 +196,30 @@ typedef struct tdEFI_HANDOFF_TABLE_POINTERS {
 } EFI_HANDOFF_TABLE_POINTERS;
 
 ///
+/// UEFI_HANDOFF_TABLE_POINTERS
+///
+/// This structure is used in EV_EFI_HANDOFF_TABLES event to facilitate
+/// the measurement of given configuration tables.
+///
+typedef struct tdUEFI_HANDOFF_TABLE_POINTERS {
+  UINT64                            NumberOfTables;
+  EFI_CONFIGURATION_TABLE           TableEntry[1];
+} UEFI_HANDOFF_TABLE_POINTERS;
+
+///
+/// UEFI_HANDOFF_TABLE_POINTERS2
+///
+/// This structure is used in EV_EFI_HANDOFF_TABLES2 event to facilitate
+/// the measurement of given configuration tables.
+///
+typedef struct tdUEFI_HANDOFF_TABLE_POINTERS2 {
+  UINT8                             TableDescriptionSize;
+//UINT8                             TableDescription[TableDescriptionSize];
+//UINT64                            NumberOfTables;
+//EFI_CONFIGURATION_TABLE           TableEntry[1];
+} UEFI_HANDOFF_TABLE_POINTERS2;
+
+///
 /// EFI_VARIABLE_DATA
 ///
 /// This structure serves as the header for measuring variables. The name of the
@@ -190,10 +264,70 @@ typedef struct {
 
 typedef struct tdEFI_GPT_DATA {
   EFI_PARTITION_TABLE_HEADER  EfiPartitionHeader;
-  UINTN                       NumberOfPartitions; 
+  UINTN                       NumberOfPartitions;
   EFI_PARTITION_ENTRY         Partitions[1];
 } EFI_GPT_DATA;
 
+typedef struct tdUEFI_GPT_DATA {
+  EFI_PARTITION_TABLE_HEADER  EfiPartitionHeader;
+  UINT64                      NumberOfPartitions;
+  EFI_PARTITION_ENTRY         Partitions[1];
+} UEFI_GPT_DATA;
+
+#define TCG_DEVICE_SECURITY_EVENT_DATA_SIGNATURE "SPDM Device Sec"
+#define TCG_DEVICE_SECURITY_EVENT_DATA_VERSION   0
+
+#define TCG_DEVICE_SECURITY_EVENT_DATA_DEVICE_TYPE_NULL  0
+#define TCG_DEVICE_SECURITY_EVENT_DATA_DEVICE_TYPE_PCI   1
+#define TCG_DEVICE_SECURITY_EVENT_DATA_DEVICE_TYPE_USB   2
+
+///
+/// TCG_DEVICE_SECURITY_EVENT_DATA_HEADER
+/// This is the header of TCG_DEVICE_SECURITY_EVENT_DATA, which is
+/// used in EV_EFI_SPDM_FIRMWARE_BLOB and EV_EFI_SPDM_FIRMWARE_CONFIG.
+///
+typedef struct {
+  UINT8                          Signature[16];
+  UINT16                         Version;
+  UINT16                         Length;
+  UINT32                         SpdmHashAlgo;
+  UINT32                         DeviceType;
+//SPDM_MEASUREMENT_BLOCK         SpdmMeasurementBlock;
+} TCG_DEVICE_SECURITY_EVENT_DATA_HEADER;
+
+#define TCG_DEVICE_SECURITY_EVENT_DATA_PCI_CONTEXT_VERSION  0
+
+///
+/// TCG_DEVICE_SECURITY_EVENT_DATA_PCI_CONTEXT
+/// This is the PCI context data of TCG_DEVICE_SECURITY_EVENT_DATA, which is
+/// used in EV_EFI_SPDM_FIRMWARE_BLOB and EV_EFI_SPDM_FIRMWARE_CONFIG.
+///
+typedef struct {
+  UINT16  Version;
+  UINT16  Length;
+  UINT16  VendorId;
+  UINT16  DeviceId;
+  UINT8   RevisionID;
+  UINT8   ClassCode[3];
+  UINT16  SubsystemVendorID;
+  UINT16  SubsystemID;
+} TCG_DEVICE_SECURITY_EVENT_DATA_PCI_CONTEXT;
+
+#define TCG_DEVICE_SECURITY_EVENT_DATA_USB_CONTEXT_VERSION  0
+
+///
+/// TCG_DEVICE_SECURITY_EVENT_DATA_USB_CONTEXT
+/// This is the USB context data of TCG_DEVICE_SECURITY_EVENT_DATA, which is
+/// used in EV_EFI_SPDM_FIRMWARE_BLOB and EV_EFI_SPDM_FIRMWARE_CONFIG.
+///
+typedef struct {
+  UINT16  Version;
+  UINT16  Length;
+//UINT8   DeviceDescriptor[DescLen];
+//UINT8   BodDescriptor[DescLen];
+//UINT8   ConfigurationDescriptor[DescLen][NumOfConfiguration];
+} TCG_DEVICE_SECURITY_EVENT_DATA_USB_CONTEXT;
+
 //
 // Crypto Agile Log Entry Format
 //
@@ -240,6 +374,7 @@ typedef struct {
 #define TCG_EfiSpecIDEventStruct_SPEC_VERSION_MAJOR_TPM2   2
 #define TCG_EfiSpecIDEventStruct_SPEC_VERSION_MINOR_TPM2   0
 #define TCG_EfiSpecIDEventStruct_SPEC_ERRATA_TPM2          0
+#define TCG_EfiSpecIDEventStruct_SPEC_ERRATA_TPM2_REV_105  105
 
 typedef struct {
   UINT8               signature[16];
@@ -296,20 +431,52 @@ typedef struct {
 //UINT8               vendorInfo[vendorInfoSize];
 } TCG_EfiSpecIDEventStruct;
 
+typedef struct tdTCG_PCClientTaggedEvent {
+  UINT32              taggedEventID;
+  UINT32              taggedEventDataSize;
+//UINT8               taggedEventData[taggedEventDataSize];
+} TCG_PCClientTaggedEvent;
+
+#define TCG_Sp800_155_PlatformId_Event_SIGNATURE  "SP800-155 Event"
+#define TCG_Sp800_155_PlatformId_Event2_SIGNATURE "SP800-155 Event2"
 
+typedef struct tdTCG_Sp800_155_PlatformId_Event2 {
+  UINT8               Signature[16];
+  //
+  // Where Vendor ID is an integer defined
+  // at http://www.iana.org/assignments/enterprisenumbers
+  //
+  UINT32              VendorId;
+  //
+  // 16-byte identifier of a given platform's static configuration of code
+  //
+  EFI_GUID            ReferenceManifestGuid;
+  //
+  // Below structure is newly added in TCG_Sp800_155_PlatformId_Event2.
+  //
+//UINT8               PlatformManufacturerStrSize;
+//UINT8               PlatformManufacturerStr[PlatformManufacturerStrSize];
+//UINT8               PlatformModelSize;
+//UINT8               PlatformModel[PlatformModelSize];
+//UINT8               PlatformVersionSize;
+//UINT8               PlatformVersion[PlatformVersionSize];
+//UINT8               PlatformModelSize;
+//UINT8               PlatformModel[PlatformModelSize];
+//UINT8               FirmwareManufacturerStrSize;
+//UINT8               FirmwareManufacturerStr[FirmwareManufacturerStrSize];
+//UINT32              FirmwareManufacturerId;
+//UINT8               FirmwareVersion;
+//UINT8               FirmwareVersion[FirmwareVersionSize]];
+} TCG_Sp800_155_PlatformId_Event2;
 
 #define TCG_EfiStartupLocalityEvent_SIGNATURE      "StartupLocality"
 
 
 //
-// PC Client PTP spec Table 8 Relationship between Locality and Locality Attribute
+// The Locality Indicator which sent the TPM2_Startup command
 //
-#define LOCALITY_0_INDICATOR        0x01
-#define LOCALITY_1_INDICATOR        0x02
-#define LOCALITY_2_INDICATOR        0x03
-#define LOCALITY_3_INDICATOR        0x04
-#define LOCALITY_4_INDICATOR        0x05
-
+#define LOCALITY_0_INDICATOR        0x00
+#define LOCALITY_3_INDICATOR        0x03
 
 //
 // Startup Locality Event
diff --git a/MdePkg/Include/IndustryStandard/Usb.h b/MdePkg/Include/IndustryStandard/Usb.h
index 38c4d853e5ec..e7c02e5a4677 100644
--- a/MdePkg/Include/IndustryStandard/Usb.h
+++ b/MdePkg/Include/IndustryStandard/Usb.h
@@ -2,13 +2,7 @@
   Support for USB 2.0 standard.
 
   Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/IndustryStandard/WatchdogActionTable.h b/MdePkg/Include/IndustryStandard/WatchdogActionTable.h
index 124a5e77753b..d30c4615072c 100644
--- a/MdePkg/Include/IndustryStandard/WatchdogActionTable.h
+++ b/MdePkg/Include/IndustryStandard/WatchdogActionTable.h
@@ -1,15 +1,9 @@
-/** @file   
+/** @file
   ACPI Watchdog Action Table (WADT) as defined at
   Microsoft Hardware Watchdog Timers Design Specification.
 
-  Copyright (c) 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
 
@@ -36,8 +30,8 @@ typedef struct {
   UINT32                                  TimerPeriod;
   UINT32                                  MaxCount;
   UINT32                                  MinCount;
-  UINT8                                   WatchdogFlags;  
-  UINT8                                   Reserved_61[3];  
+  UINT8                                   WatchdogFlags;
+  UINT8                                   Reserved_61[3];
   UINT32                                  NumberWatchdogInstructionEntries;
 } EFI_ACPI_WATCHDOG_ACTION_1_0_TABLE;
 
diff --git a/MdePkg/Include/IndustryStandard/WatchdogResourceTable.h b/MdePkg/Include/IndustryStandard/WatchdogResourceTable.h
index a0b0cf2c1830..3ff87a3ea3d7 100644
--- a/MdePkg/Include/IndustryStandard/WatchdogResourceTable.h
+++ b/MdePkg/Include/IndustryStandard/WatchdogResourceTable.h
@@ -1,15 +1,9 @@
-/** @file   
+/** @file
   ACPI Watchdog Resource Table (WDRT) as defined at
   Microsoft Windows Hardware Developer Central.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
 #ifndef _WATCHDOG_RESOURCE_TABLE_H_
diff --git a/MdePkg/Include/IndustryStandard/WindowsSmmSecurityMitigationTable.h b/MdePkg/Include/IndustryStandard/WindowsSmmSecurityMitigationTable.h
index 390a3c83720b..4256d24f58e4 100644
--- a/MdePkg/Include/IndustryStandard/WindowsSmmSecurityMitigationTable.h
+++ b/MdePkg/Include/IndustryStandard/WindowsSmmSecurityMitigationTable.h
@@ -2,14 +2,8 @@
   Defines Windows SMM Security Mitigation Table
   @ https://msdn.microsoft.com/windows/hardware/drivers/bringup/acpi-system-description-tables#wsmt
 
-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials 
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/IndustryStandard/WindowsUxCapsule.h b/MdePkg/Include/IndustryStandard/WindowsUxCapsule.h
index 611c8f6377cc..3434fd6c4b84 100644
--- a/MdePkg/Include/IndustryStandard/WindowsUxCapsule.h
+++ b/MdePkg/Include/IndustryStandard/WindowsUxCapsule.h
@@ -2,14 +2,8 @@
   Defines Windows UX Capsule GUID and layout defined at Microsoft
   Windows UEFI Firmware Update Platform specification
 
-  Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials 
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/Ipf/IpfMacro.i b/MdePkg/Include/Ipf/IpfMacro.i
deleted file mode 100644
index 95cd13442c1a..000000000000
--- a/MdePkg/Include/Ipf/IpfMacro.i
+++ /dev/null
@@ -1,58 +0,0 @@
-// @file
-// Contains the macros required by calling procedures in Itanium-based assembly code.
-//
-// Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
-// This program and the accompanying materials
-// are licensed and made available under the terms and conditions of the BSD License
-// which accompanies this distribution.  The full text of the license may be found at
-// http://opensource.org/licenses/bsd-license.php
-//
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-
-#ifndef  __IA64PROC_I__
-#define  __IA64PROC_I__
-
-//
-// Delcare the begin of assembly function entry.
-//
-// @param name Name of function in assembly code.
-//
-#define PROCEDURE_ENTRY(name)   .##text;            \
-                                .##type name, @function;    \
-                                .##proc name;           \
-name::
-
-//
-// End of assembly function.
-//
-// @param name Name of function in assembly code.
-//
-#define PROCEDURE_EXIT(name)    .##endp name
-
-//
-// NESTED_SETUP Requires number of locals (l) >= 3
-//
-#define NESTED_SETUP(i,l,o,r) \
-         alloc loc1=ar##.##pfs,i,l,o,r ;\
-         mov loc0=b0
-
-//
-// End of Nested
-//
-#define NESTED_RETURN \
-         mov b0=loc0 ;\
-         mov ar##.##pfs=loc1 ;;\
-         br##.##ret##.##dpnt  b0;;
-
-//
-// Export assembly function as the global function.
-//
-// @param Function Name of function in assembly code.
-//
-#define GLOBAL_FUNCTION(Function) \
-         .##type   Function, @function; \
-         .##globl Function
-
-#endif
diff --git a/MdePkg/Include/Ipf/ProcessorBind.h b/MdePkg/Include/Ipf/ProcessorBind.h
deleted file mode 100644
index 8ed5c7840178..000000000000
--- a/MdePkg/Include/Ipf/ProcessorBind.h
+++ /dev/null
@@ -1,319 +0,0 @@
-/** @file
-  Processor or Compiler specific defines and types for Intel Itanium(TM) processors.
-
-Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available 
-under the terms and conditions of the BSD License which accompanies this
-distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __PROCESSOR_BIND_H__
-#define __PROCESSOR_BIND_H__
-
-
-///
-/// Define the processor type so other code can make processor-based choices.
-///
-#define MDE_CPU_IPF
-
-
-//
-// Make sure we are using the correct packing rules per EFI specification
-//
-#pragma pack()
-
-
-#if defined(__INTEL_COMPILER)
-//
-// Disable ICC's remark #869: "Parameter" was never referenced warning.
-// This is legal ANSI C code so we disable the remark that is turned on with -Wall
-//
-#pragma warning ( disable : 869 )
-
-//
-// Disable ICC's remark #1418: external function definition with no prior declaration.
-// This is legal ANSI C code so we disable the remark that is turned on with /W4
-//
-#pragma warning ( disable : 1418 )
-
-//
-// Disable ICC's remark #1419: external declaration in primary source file
-// This is legal ANSI C code so we disable the remark that is turned on with /W4
-//
-#pragma warning ( disable : 1419 )
-
-//
-// Disable ICC's remark #593: "Variable" was set but never used.
-// This is legal ANSI C code so we disable the remark that is turned on with /W4
-//
-#pragma warning ( disable : 593 )
-
-#endif
-
-
-#if defined(_MSC_EXTENSIONS)
-//
-// Disable warning that make it impossible to compile at /W4
-// This only works for Microsoft* tools
-//
-
-//
-// Disabling bitfield type checking warnings.
-//
-#pragma warning ( disable : 4214 )
-
-//
-// Disabling the unreferenced formal parameter warnings.
-//
-#pragma warning ( disable : 4100 )
-
-//
-// Disable slightly different base types warning as CHAR8 * can not be set
-// to a constant string.
-//
-#pragma warning ( disable : 4057 )
-
-//
-// Disable warning on conversion from function pointer to a data pointer
-//
-#pragma warning ( disable : 4054 )
-
-//
-// ASSERT(FALSE) or while (TRUE) are legal constructs so suppress this warning
-//
-#pragma warning ( disable : 4127 )
-
-//
-// Can not cast a function pointer to a data pointer. We need to do this on
-// Itanium processors to get access to the PLABEL.
-//
-#pragma warning ( disable : 4514 )
-
-//
-// This warning is caused by functions defined but not used. For precompiled header only.
-//
-#pragma warning ( disable : 4505 )
-
-//
-// This warning is caused by empty (after preprocessing) source file. For precompiled header only.
-//
-#pragma warning ( disable : 4206 )
-
-#endif
-
-#if defined(_MSC_EXTENSIONS)
-  //
-  // use Microsoft C compiler dependent integer width types
-  //
-
-  ///
-  /// 8-byte unsigned value.
-  ///
-  typedef unsigned __int64    UINT64;
-  ///
-  /// 8-byte signed value.
-  ///
-  typedef __int64             INT64;
-  ///
-  /// 4-byte unsigned value.
-  ///
-  typedef unsigned __int32    UINT32;
-  ///
-  /// 4-byte signed value.
-  ///
-  typedef __int32             INT32;
-  ///
-  /// 2-byte unsigned value.
-  ///
-  typedef unsigned short      UINT16;
-  ///
-  /// 2-byte Character.  Unless otherwise specified all strings are stored in the
-  /// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.
-  ///
-  typedef unsigned short      CHAR16;
-  ///
-  /// 2-byte signed value.
-  ///
-  typedef short               INT16;
-  ///
-  /// Logical Boolean.  1-byte value containing 0 for FALSE or a 1 for TRUE.  Other
-  /// values are undefined.
-  ///
-  typedef unsigned char       BOOLEAN;
-  ///
-  /// 1-byte unsigned value.
-  ///
-  typedef unsigned char       UINT8;
-  ///
-  /// 1-byte Character.
-  ///
-  typedef char                CHAR8;
-  ///
-  /// 1-byte signed value.
-  ///
-  typedef signed char         INT8;
-#else
-  ///
-  /// 8-byte unsigned value.
-  ///
-  typedef unsigned long long  UINT64;
-  ///
-  /// 8-byte signed value.
-  ///
-  typedef long long           INT64;
-  ///
-  /// 4-byte unsigned value.
-  ///
-  typedef unsigned int        UINT32;
-  ///
-  /// 4-byte signed value.
-  ///
-  typedef int                 INT32;
-  ///
-  /// 2-byte unsigned value.
-  ///
-  typedef unsigned short      UINT16;
-  ///
-  /// 2-byte Character.  Unless otherwise specified all strings are stored in the
-  /// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.
-  ///
-  typedef unsigned short      CHAR16;
-  ///
-  /// 2-byte signed value.
-  ///
-  typedef short               INT16;
-  ///
-  /// Logical Boolean.  1-byte value containing 0 for FALSE or a 1 for TRUE.  Other
-  /// values are undefined.
-  ///
-  typedef unsigned char       BOOLEAN;
-  ///
-  /// 1-byte unsigned value.
-  ///
-  typedef unsigned char       UINT8;
-  ///
-  /// 1-byte Character.
-  ///
-  typedef char                CHAR8;
-  ///
-  /// 1-byte signed value.
-  ///
-  typedef signed char         INT8;
-#endif
-
-///
-/// Unsigned value of native width.  (4 bytes on supported 32-bit processor instructions;
-/// 8 bytes on supported 64-bit processor instructions.)
-///
-typedef UINT64  UINTN;
-///
-/// Signed value of native width.  (4 bytes on supported 32-bit processor instructions;
-/// 8 bytes on supported 64-bit processor instructions.)
-///
-typedef INT64   INTN;
-
-
-//
-// Processor specific defines
-//
-
-///
-/// A value of native width with the highest bit set.
-///
-#define MAX_BIT     0x8000000000000000ULL
-///
-/// A value of native width with the two highest bits set.
-///
-#define MAX_2_BITS  0xC000000000000000ULL
-
-///
-/// The maximum legal Itanium-based address
-///
-#define MAX_ADDRESS   0xFFFFFFFFFFFFFFFFULL
-
-///
-/// Maximum legal Itanium-based INTN and UINTN values.
-///
-#define MAX_INTN   ((INTN)0x7FFFFFFFFFFFFFFFULL)
-#define MAX_UINTN  ((UINTN)0xFFFFFFFFFFFFFFFFULL)
-
-///
-/// Per the Itanium Software Conventions and Runtime Architecture Guide,
-/// section 3.3.4, IPF stack must always be 16-byte aligned.
-///
-#define CPU_STACK_ALIGNMENT   16
-
-///
-/// Page allocation granularity for Itanium
-///
-#define DEFAULT_PAGE_ALLOCATION_GRANULARITY   (0x1000)
-#define RUNTIME_PAGE_ALLOCATION_GRANULARITY   (0x2000)
-
-//
-// Modifier to ensure that all protocol member functions and EFI intrinsics
-// use the correct C calling convention. All protocol member functions and
-// EFI intrinsics are required to modify their member functions with EFIAPI.
-//
-#ifdef EFIAPI
-  ///
-  /// If EFIAPI is already defined, then we use that definition.
-  ///
-#elif defined(_MSC_EXTENSIONS)
-  ///
-  /// Microsoft* compiler-specific method for EFIAPI calling convention.
-  /// 
-  #define EFIAPI __cdecl
-#else
-  #define EFIAPI
-#endif
-
-///
-/// For GNU assembly code, .global or .globl can declare global symbols.
-/// Define this macro to unify the usage.
-///
-#define ASM_GLOBAL .globl
-
-///
-/// A pointer to a function in IPF points to a plabel.
-///
-typedef struct {
-  UINT64  EntryPoint;
-  UINT64  GP;
-} EFI_PLABEL;
-
-///
-/// PAL Call return structure.
-///
-typedef struct {
-  UINT64                    Status;
-  UINT64                    r9;
-  UINT64                    r10;
-  UINT64                    r11;
-} PAL_CALL_RETURN;
-
-/**
-  Return the pointer to the first instruction of a function given a function pointer.
-  For Itanium processors, all function calls are made through a PLABEL, so a pointer to a function 
-  is actually a pointer to a PLABEL.  The pointer to the first instruction of the function 
-  is contained within the PLABEL.  This macro may be used to retrieve a pointer to the first 
-  instruction of a function independent of the CPU architecture being used.  This is very 
-  useful when printing function addresses through DEBUG() macros.
-  
-  @param  FunctionPointer   A pointer to a function.
-
-  @return The pointer to the first instruction of a function given a function pointer.
-  
-**/
-#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(((EFI_PLABEL *)(FunctionPointer))->EntryPoint)
-
-#ifndef __USER_LABEL_PREFIX__
-#define __USER_LABEL_PREFIX__
-#endif
-
-#endif
-
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index b41c10b1b661..762cb9ac3abb 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -2,15 +2,12 @@
   Provides string functions, linked list functions, math functions, synchronization
   functions, file path functions, and CPU architecture-specific functions.
 
-Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
 Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.
+Copyright (c) Microsoft Corporation.<BR>
+Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
 
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -31,62 +28,13 @@ typedef struct {
   UINT32                            Ebp;
   UINT32                            Esp;
   UINT32                            Eip;
+  UINT32                            Ssp;
 } BASE_LIBRARY_JUMP_BUFFER;
 
 #define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 4
 
 #endif // defined (MDE_CPU_IA32)
 
-#if defined (MDE_CPU_IPF)
-
-///
-/// The Itanium architecture context buffer used by SetJump() and LongJump().
-///
-typedef struct {
-  UINT64                            F2[2];
-  UINT64                            F3[2];
-  UINT64                            F4[2];
-  UINT64                            F5[2];
-  UINT64                            F16[2];
-  UINT64                            F17[2];
-  UINT64                            F18[2];
-  UINT64                            F19[2];
-  UINT64                            F20[2];
-  UINT64                            F21[2];
-  UINT64                            F22[2];
-  UINT64                            F23[2];
-  UINT64                            F24[2];
-  UINT64                            F25[2];
-  UINT64                            F26[2];
-  UINT64                            F27[2];
-  UINT64                            F28[2];
-  UINT64                            F29[2];
-  UINT64                            F30[2];
-  UINT64                            F31[2];
-  UINT64                            R4;
-  UINT64                            R5;
-  UINT64                            R6;
-  UINT64                            R7;
-  UINT64                            SP;
-  UINT64                            BR0;
-  UINT64                            BR1;
-  UINT64                            BR2;
-  UINT64                            BR3;
-  UINT64                            BR4;
-  UINT64                            BR5;
-  UINT64                            InitialUNAT;
-  UINT64                            AfterSpillUNAT;
-  UINT64                            PFS;
-  UINT64                            BSP;
-  UINT64                            Predicates;
-  UINT64                            LoopCount;
-  UINT64                            FPSR;
-} BASE_LIBRARY_JUMP_BUFFER;
-
-#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 0x10
-
-#endif // defined (MDE_CPU_IPF)
-
 #if defined (MDE_CPU_X64)
 ///
 /// The x64 architecture context buffer used by SetJump() and LongJump().
@@ -104,6 +52,7 @@ typedef struct {
   UINT64                            Rip;
   UINT64                            MxCsr;
   UINT8                             XmmBuffer[160]; ///< XMM6-XMM15.
+  UINT64                            Ssp;
 } BASE_LIBRARY_JUMP_BUFFER;
 
 #define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8
@@ -178,6 +127,30 @@ typedef struct {
 
 #endif  // defined (MDE_CPU_AARCH64)
 
+#if defined (MDE_CPU_RISCV64)
+///
+/// The RISC-V architecture context buffer used by SetJump() and LongJump().
+///
+typedef struct {
+  UINT64                            RA;
+  UINT64                            S0;
+  UINT64                            S1;
+  UINT64                            S2;
+  UINT64                            S3;
+  UINT64                            S4;
+  UINT64                            S5;
+  UINT64                            S6;
+  UINT64                            S7;
+  UINT64                            S8;
+  UINT64                            S9;
+  UINT64                            S10;
+  UINT64                            S11;
+  UINT64                            SP;
+} BASE_LIBRARY_JUMP_BUFFER;
+
+#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8
+
+#endif // defined (MDE_CPU_RISCV64)
 
 //
 // String Services
@@ -243,7 +216,6 @@ StrnSizeS (
 
   If Destination is not aligned on a 16-bit boundary, then ASSERT().
   If Source is not aligned on a 16-bit boundary, then ASSERT().
-  If an error would be returned, then the function will also ASSERT().
 
   If an error is returned, then the Destination is unmodified.
 
@@ -257,7 +229,7 @@ StrnSizeS (
   @retval RETURN_INVALID_PARAMETER If Destination is NULL.
                                    If Source is NULL.
                                    If PcdMaximumUnicodeStringLength is not zero,
-                                    and DestMax is greater than 
+                                    and DestMax is greater than
                                     PcdMaximumUnicodeStringLength.
                                    If DestMax is 0.
   @retval RETURN_ACCESS_DENIED     If Source and Destination overlap.
@@ -279,7 +251,6 @@ StrCpyS (
 
   If Length > 0 and Destination is not aligned on a 16-bit boundary, then ASSERT().
   If Length > 0 and Source is not aligned on a 16-bit boundary, then ASSERT().
-  If an error would be returned, then the function will also ASSERT().
 
   If an error is returned, then the Destination is unmodified.
 
@@ -290,12 +261,12 @@ StrCpyS (
   @param  Length                   The maximum number of Unicode characters to copy.
 
   @retval RETURN_SUCCESS           String is copied.
-  @retval RETURN_BUFFER_TOO_SMALL  If DestMax is NOT greater than 
+  @retval RETURN_BUFFER_TOO_SMALL  If DestMax is NOT greater than
                                    MIN(StrLen(Source), Length).
   @retval RETURN_INVALID_PARAMETER If Destination is NULL.
                                    If Source is NULL.
                                    If PcdMaximumUnicodeStringLength is not zero,
-                                    and DestMax is greater than 
+                                    and DestMax is greater than
                                     PcdMaximumUnicodeStringLength.
                                    If DestMax is 0.
   @retval RETURN_ACCESS_DENIED     If Source and Destination overlap.
@@ -317,7 +288,6 @@ StrnCpyS (
 
   If Destination is not aligned on a 16-bit boundary, then ASSERT().
   If Source is not aligned on a 16-bit boundary, then ASSERT().
-  If an error would be returned, then the function will also ASSERT().
 
   If an error is returned, then the Destination is unmodified.
 
@@ -327,14 +297,14 @@ StrnCpyS (
   @param  Source                   A pointer to a Null-terminated Unicode string.
 
   @retval RETURN_SUCCESS           String is appended.
-  @retval RETURN_BAD_BUFFER_SIZE   If DestMax is NOT greater than 
+  @retval RETURN_BAD_BUFFER_SIZE   If DestMax is NOT greater than
                                    StrLen(Destination).
   @retval RETURN_BUFFER_TOO_SMALL  If (DestMax - StrLen(Destination)) is NOT
                                    greater than StrLen(Source).
   @retval RETURN_INVALID_PARAMETER If Destination is NULL.
                                    If Source is NULL.
                                    If PcdMaximumUnicodeStringLength is not zero,
-                                    and DestMax is greater than 
+                                    and DestMax is greater than
                                     PcdMaximumUnicodeStringLength.
                                    If DestMax is 0.
   @retval RETURN_ACCESS_DENIED     If Source and Destination overlap.
@@ -357,7 +327,6 @@ StrCatS (
 
   If Destination is not aligned on a 16-bit boundary, then ASSERT().
   If Source is not aligned on a 16-bit boundary, then ASSERT().
-  If an error would be returned, then the function will also ASSERT().
 
   If an error is returned, then the Destination is unmodified.
 
@@ -375,7 +344,7 @@ StrCatS (
   @retval RETURN_INVALID_PARAMETER If Destination is NULL.
                                    If Source is NULL.
                                    If PcdMaximumUnicodeStringLength is not zero,
-                                    and DestMax is greater than 
+                                    and DestMax is greater than
                                     PcdMaximumUnicodeStringLength.
                                    If DestMax is 0.
   @retval RETURN_ACCESS_DENIED     If Source and Destination overlap.
@@ -404,12 +373,7 @@ StrnCatS (
   be ignored. Then, the function stops at the first character that is a not a
   valid decimal character or a Null-terminator, whichever one comes first.
 
-  If String is NULL, then ASSERT().
-  If Data is NULL, then ASSERT().
   If String is not aligned in a 16-bit boundary, then ASSERT().
-  If PcdMaximumUnicodeStringLength is not zero, and String contains more than
-  PcdMaximumUnicodeStringLength Unicode characters, not including the
-  Null-terminator, then ASSERT().
 
   If String has no valid decimal digits in the above format, then 0 is stored
   at the location pointed to by Data.
@@ -460,12 +424,7 @@ StrDecimalToUintnS (
   be ignored. Then, the function stops at the first character that is a not a
   valid decimal character or a Null-terminator, whichever one comes first.
 
-  If String is NULL, then ASSERT().
-  If Data is NULL, then ASSERT().
   If String is not aligned in a 16-bit boundary, then ASSERT().
-  If PcdMaximumUnicodeStringLength is not zero, and String contains more than
-  PcdMaximumUnicodeStringLength Unicode characters, not including the
-  Null-terminator, then ASSERT().
 
   If String has no valid decimal digits in the above format, then 0 is stored
   at the location pointed to by Data.
@@ -521,12 +480,7 @@ StrDecimalToUint64S (
   the first character that is a not a valid hexadecimal character or NULL,
   whichever one comes first.
 
-  If String is NULL, then ASSERT().
-  If Data is NULL, then ASSERT().
   If String is not aligned in a 16-bit boundary, then ASSERT().
-  If PcdMaximumUnicodeStringLength is not zero, and String contains more than
-  PcdMaximumUnicodeStringLength Unicode characters, not including the
-  Null-terminator, then ASSERT().
 
   If String has no valid hexadecimal digits in the above format, then 0 is
   stored at the location pointed to by Data.
@@ -582,12 +536,7 @@ StrHexToUintnS (
   the first character that is a not a valid hexadecimal character or NULL,
   whichever one comes first.
 
-  If String is NULL, then ASSERT().
-  If Data is NULL, then ASSERT().
   If String is not aligned in a 16-bit boundary, then ASSERT().
-  If PcdMaximumUnicodeStringLength is not zero, and String contains more than
-  PcdMaximumUnicodeStringLength Unicode characters, not including the
-  Null-terminator, then ASSERT().
 
   If String has no valid hexadecimal digits in the above format, then 0 is
   stored at the location pointed to by Data.
@@ -676,8 +625,6 @@ AsciiStrnSizeS (
 
   This function is similar as strcpy_s defined in C11.
 
-  If an error would be returned, then the function will also ASSERT().
-
   If an error is returned, then the Destination is unmodified.
 
   @param  Destination              A pointer to a Null-terminated Ascii string.
@@ -690,7 +637,7 @@ AsciiStrnSizeS (
   @retval RETURN_INVALID_PARAMETER If Destination is NULL.
                                    If Source is NULL.
                                    If PcdMaximumAsciiStringLength is not zero,
-                                    and DestMax is greater than 
+                                    and DestMax is greater than
                                     PcdMaximumAsciiStringLength.
                                    If DestMax is 0.
   @retval RETURN_ACCESS_DENIED     If Source and Destination overlap.
@@ -710,8 +657,6 @@ AsciiStrCpyS (
 
   This function is similar as strncpy_s defined in C11.
 
-  If an error would be returned, then the function will also ASSERT().
-
   If an error is returned, then the Destination is unmodified.
 
   @param  Destination              A pointer to a Null-terminated Ascii string.
@@ -721,12 +666,12 @@ AsciiStrCpyS (
   @param  Length                   The maximum number of Ascii characters to copy.
 
   @retval RETURN_SUCCESS           String is copied.
-  @retval RETURN_BUFFER_TOO_SMALL  If DestMax is NOT greater than 
+  @retval RETURN_BUFFER_TOO_SMALL  If DestMax is NOT greater than
                                    MIN(StrLen(Source), Length).
   @retval RETURN_INVALID_PARAMETER If Destination is NULL.
                                    If Source is NULL.
                                    If PcdMaximumAsciiStringLength is not zero,
-                                    and DestMax is greater than 
+                                    and DestMax is greater than
                                     PcdMaximumAsciiStringLength.
                                    If DestMax is 0.
   @retval RETURN_ACCESS_DENIED     If Source and Destination overlap.
@@ -746,8 +691,6 @@ AsciiStrnCpyS (
 
   This function is similar as strcat_s defined in C11.
 
-  If an error would be returned, then the function will also ASSERT().
-
   If an error is returned, then the Destination is unmodified.
 
   @param  Destination              A pointer to a Null-terminated Ascii string.
@@ -756,14 +699,14 @@ AsciiStrnCpyS (
   @param  Source                   A pointer to a Null-terminated Ascii string.
 
   @retval RETURN_SUCCESS           String is appended.
-  @retval RETURN_BAD_BUFFER_SIZE   If DestMax is NOT greater than 
+  @retval RETURN_BAD_BUFFER_SIZE   If DestMax is NOT greater than
                                    StrLen(Destination).
   @retval RETURN_BUFFER_TOO_SMALL  If (DestMax - StrLen(Destination)) is NOT
                                    greater than StrLen(Source).
   @retval RETURN_INVALID_PARAMETER If Destination is NULL.
                                    If Source is NULL.
                                    If PcdMaximumAsciiStringLength is not zero,
-                                    and DestMax is greater than 
+                                    and DestMax is greater than
                                     PcdMaximumAsciiStringLength.
                                    If DestMax is 0.
   @retval RETURN_ACCESS_DENIED     If Source and Destination overlap.
@@ -784,8 +727,6 @@ AsciiStrCatS (
 
   This function is similar as strncat_s defined in C11.
 
-  If an error would be returned, then the function will also ASSERT().
-
   If an error is returned, then the Destination is unmodified.
 
   @param  Destination              A pointer to a Null-terminated Ascii string.
@@ -802,7 +743,7 @@ AsciiStrCatS (
   @retval RETURN_INVALID_PARAMETER If Destination is NULL.
                                    If Source is NULL.
                                    If PcdMaximumAsciiStringLength is not zero,
-                                    and DestMax is greater than 
+                                    and DestMax is greater than
                                     PcdMaximumAsciiStringLength.
                                    If DestMax is 0.
   @retval RETURN_ACCESS_DENIED     If Source and Destination overlap.
@@ -831,12 +772,6 @@ AsciiStrnCatS (
   be ignored. Then, the function stops at the first character that is a not a
   valid decimal character or a Null-terminator, whichever one comes first.
 
-  If String is NULL, then ASSERT().
-  If Data is NULL, then ASSERT().
-  If PcdMaximumAsciiStringLength is not zero, and String contains more than
-  PcdMaximumAsciiStringLength Ascii characters, not including the
-  Null-terminator, then ASSERT().
-
   If String has no valid decimal digits in the above format, then 0 is stored
   at the location pointed to by Data.
   If the number represented by String exceeds the range defined by UINTN, then
@@ -886,12 +821,6 @@ AsciiStrDecimalToUintnS (
   be ignored. Then, the function stops at the first character that is a not a
   valid decimal character or a Null-terminator, whichever one comes first.
 
-  If String is NULL, then ASSERT().
-  If Data is NULL, then ASSERT().
-  If PcdMaximumAsciiStringLength is not zero, and String contains more than
-  PcdMaximumAsciiStringLength Ascii characters, not including the
-  Null-terminator, then ASSERT().
-
   If String has no valid decimal digits in the above format, then 0 is stored
   at the location pointed to by Data.
   If the number represented by String exceeds the range defined by UINT64, then
@@ -945,12 +874,6 @@ AsciiStrDecimalToUint64S (
   character that is a not a valid hexadecimal character or Null-terminator,
   whichever on comes first.
 
-  If String is NULL, then ASSERT().
-  If Data is NULL, then ASSERT().
-  If PcdMaximumAsciiStringLength is not zero, and String contains more than
-  PcdMaximumAsciiStringLength Ascii characters, not including the
-  Null-terminator, then ASSERT().
-
   If String has no valid hexadecimal digits in the above format, then 0 is
   stored at the location pointed to by Data.
   If the number represented by String exceeds the range defined by UINTN, then
@@ -1004,12 +927,6 @@ AsciiStrHexToUintnS (
   character that is a not a valid hexadecimal character or Null-terminator,
   whichever on comes first.
 
-  If String is NULL, then ASSERT().
-  If Data is NULL, then ASSERT().
-  If PcdMaximumAsciiStringLength is not zero, and String contains more than
-  PcdMaximumAsciiStringLength Ascii characters, not including the
-  Null-terminator, then ASSERT().
-
   If String has no valid hexadecimal digits in the above format, then 0 is
   stored at the location pointed to by Data.
   If the number represented by String exceeds the range defined by UINT64, then
@@ -1083,7 +1000,7 @@ StrCpy (
 /**
   [ATTENTION] This function is deprecated for security reason.
 
-  Copies up to a specified length from one Null-terminated Unicode string to 
+  Copies up to a specified length from one Null-terminated Unicode string to
   another Null-terminated Unicode string and returns the new Unicode string.
 
   This function copies the contents of the Unicode string Source to the Unicode
@@ -1099,7 +1016,7 @@ StrCpy (
   If Length > 0 and Source is NULL, then ASSERT().
   If Length > 0 and Source is not aligned on a 16-bit boundary, then ASSERT().
   If Source and Destination overlap, then ASSERT().
-  If PcdMaximumUnicodeStringLength is not zero, and Length is greater than 
+  If PcdMaximumUnicodeStringLength is not zero, and Length is greater than
   PcdMaximumUnicodeStringLength, then ASSERT().
   If PcdMaximumUnicodeStringLength is not zero, and Source contains more than
   PcdMaximumUnicodeStringLength Unicode characters, not including the Null-terminator,
@@ -1119,7 +1036,7 @@ StrnCpy (
   IN      CONST CHAR16              *Source,
   IN      UINTN                     Length
   );
-#endif
+#endif // !defined (DISABLE_NEW_DEPRECATED_INTERFACES)
 
 /**
   Returns the length of a Null-terminated Unicode string.
@@ -1149,7 +1066,7 @@ StrLen (
   Returns the size of a Null-terminated Unicode string in bytes, including the
   Null terminator.
 
-  This function returns the size, in bytes, of the Null-terminated Unicode string 
+  This function returns the size, in bytes, of the Null-terminated Unicode string
   specified by String.
 
   If String is NULL, then ASSERT().
@@ -1209,7 +1126,7 @@ StrCmp (
 /**
   Compares up to a specified length the contents of two Null-terminated Unicode strings,
   and returns the difference between the first mismatched Unicode characters.
-  
+
   This function compares the Null-terminated Unicode string FirstString to the
   Null-terminated Unicode string SecondString. At most, Length Unicode
   characters will be compared. If Length is 0, then 0 is returned. If
@@ -1294,8 +1211,8 @@ StrCat (
 /**
   [ATTENTION] This function is deprecated for security reason.
 
-  Concatenates up to a specified length one Null-terminated Unicode to the end 
-  of another Null-terminated Unicode string, and returns the concatenated 
+  Concatenates up to a specified length one Null-terminated Unicode to the end
+  of another Null-terminated Unicode string, and returns the concatenated
   Unicode string.
 
   This function concatenates two Null-terminated Unicode strings. The contents
@@ -1311,7 +1228,7 @@ StrCat (
   If Length > 0 and Source is NULL, then ASSERT().
   If Length > 0 and Source is not aligned on a 16-bit boundary, then ASSERT().
   If Source and Destination overlap, then ASSERT().
-  If PcdMaximumUnicodeStringLength is not zero, and Length is greater than 
+  If PcdMaximumUnicodeStringLength is not zero, and Length is greater than
   PcdMaximumUnicodeStringLength, then ASSERT().
   If PcdMaximumUnicodeStringLength is not zero, and Destination contains more
   than PcdMaximumUnicodeStringLength Unicode characters, not including the
@@ -1338,7 +1255,7 @@ StrnCat (
   IN      CONST CHAR16              *Source,
   IN      UINTN                     Length
   );
-#endif
+#endif // !defined (DISABLE_NEW_DEPRECATED_INTERFACES)
 
 /**
   Returns the first occurrence of a Null-terminated Unicode sub-string
@@ -1451,7 +1368,7 @@ EFIAPI
 StrDecimalToUint64 (
   IN      CONST CHAR16              *String
   );
- 
+
 
 /**
   Convert a Null-terminated Unicode hexadecimal string to a value of type UINTN.
@@ -1468,7 +1385,7 @@ StrDecimalToUint64 (
   The function will ignore the pad space, which includes spaces or tab characters,
   before [zeros], [x] or [hexadecimal digit]. The running zero before [x] or
   [hexadecimal digit] will be ignored. Then, the decoding starts after [x] or the
-  first valid hexadecimal digit. Then, the function stops at the first character 
+  first valid hexadecimal digit. Then, the function stops at the first character
   that is a not a valid hexadecimal character or NULL, whichever one comes first.
 
   If String is NULL, then ASSERT().
@@ -1560,16 +1477,8 @@ StrHexToUint64 (
   "::" can be used to compress one or more groups of X when X contains only 0.
   The "::" can only appear once in the String.
 
-  If String is NULL, then ASSERT().
-
-  If Address is NULL, then ASSERT().
-
   If String is not aligned in a 16-bit boundary, then ASSERT().
 
-  If PcdMaximumUnicodeStringLength is not zero, and String contains more than
-  PcdMaximumUnicodeStringLength Unicode characters, not including the
-  Null-terminator, then ASSERT().
-
   If EndPointer is not NULL and Address is translated from String, a pointer
   to the character that stopped the scan is stored at the location pointed to
   by EndPointer.
@@ -1621,16 +1530,8 @@ StrToIpv6Address (
   When /P is in the String, the function stops at the first character that is not
   a valid decimal digit character after P is converted.
 
-  If String is NULL, then ASSERT().
-
-  If Address is NULL, then ASSERT().
-
   If String is not aligned in a 16-bit boundary, then ASSERT().
 
-  If PcdMaximumUnicodeStringLength is not zero, and String contains more than
-  PcdMaximumUnicodeStringLength Unicode characters, not including the
-  Null-terminator, then ASSERT().
-
   If EndPointer is not NULL and Address is translated from String, a pointer
   to the character that stopped the scan is stored at the location pointed to
   by EndPointer.
@@ -1694,8 +1595,6 @@ StrToIpv4Address (
                   oo          Data4[48:55]
                   pp          Data4[56:63]
 
-  If String is NULL, then ASSERT().
-  If Guid is NULL, then ASSERT().
   If String is not aligned in a 16-bit boundary, then ASSERT().
 
   @param  String                   Pointer to a Null-terminated Unicode string.
@@ -1730,17 +1629,6 @@ StrToGuid (
 
   If String is not aligned in a 16-bit boundary, then ASSERT().
 
-  If String is NULL, then ASSERT().
-
-  If Buffer is NULL, then ASSERT().
-
-  If Length is not multiple of 2, then ASSERT().
-
-  If PcdMaximumUnicodeStringLength is not zero and Length is greater than
-  PcdMaximumUnicodeStringLength, then ASSERT().
-
-  If MaxBufferSize is less than (Length / 2), then ASSERT().
-
   @param  String                   Pointer to a Null-terminated Unicode string.
   @param  Length                   The number of Unicode characters to decode.
   @param  Buffer                   Pointer to the converted bytes array.
@@ -1811,7 +1699,7 @@ UnicodeStrToAsciiStr (
   OUT     CHAR8                     *Destination
   );
 
-#endif
+#endif // !defined (DISABLE_NEW_DEPRECATED_INTERFACES)
 
 /**
   Convert a Null-terminated Unicode string to a Null-terminated
@@ -1831,7 +1719,6 @@ UnicodeStrToAsciiStr (
   the upper 8 bits, then ASSERT().
 
   If Source is not aligned on a 16-bit boundary, then ASSERT().
-  If an error would be returned, then the function will also ASSERT().
 
   If an error is returned, then the Destination is unmodified.
 
@@ -1878,7 +1765,6 @@ UnicodeStrToAsciiStrS (
   If any Unicode characters in Source contain non-zero value in the upper 8
   bits, then ASSERT().
   If Source is not aligned on a 16-bit boundary, then ASSERT().
-  If an error would be returned, then the function will also ASSERT().
 
   If an error is returned, then the Destination is unmodified.
 
@@ -1952,7 +1838,7 @@ AsciiStrCpy (
 /**
   [ATTENTION] This function is deprecated for security reason.
 
-  Copies up to a specified length one Null-terminated ASCII string to another 
+  Copies up to a specified length one Null-terminated ASCII string to another
   Null-terminated ASCII string and returns the new ASCII string.
 
   This function copies the contents of the ASCII string Source to the ASCII
@@ -1965,7 +1851,7 @@ AsciiStrCpy (
   If Destination is NULL, then ASSERT().
   If Source is NULL, then ASSERT().
   If Source and Destination overlap, then ASSERT().
-  If PcdMaximumAsciiStringLength is not zero, and Length is greater than 
+  If PcdMaximumAsciiStringLength is not zero, and Length is greater than
   PcdMaximumAsciiStringLength, then ASSERT().
   If PcdMaximumAsciiStringLength is not zero, and Source contains more than
   PcdMaximumAsciiStringLength ASCII characters, not including the Null-terminator,
@@ -1985,7 +1871,7 @@ AsciiStrnCpy (
   IN      CONST CHAR8               *Source,
   IN      UINTN                     Length
   );
-#endif
+#endif // !defined (DISABLE_NEW_DEPRECATED_INTERFACES)
 
 /**
   Returns the length of a Null-terminated ASCII string.
@@ -2119,7 +2005,7 @@ AsciiStriCmp (
 
   If Length > 0 and FirstString is NULL, then ASSERT().
   If Length > 0 and SecondString is NULL, then ASSERT().
-  If PcdMaximumAsciiStringLength is not zero, and Length is greater than 
+  If PcdMaximumAsciiStringLength is not zero, and Length is greater than
   PcdMaximumAsciiStringLength, then ASSERT().
   If PcdMaximumAsciiStringLength is not zero, and FirstString contains more than
   PcdMaximumAsciiStringLength ASCII characters, not including the Null-terminator,
@@ -2131,7 +2017,7 @@ AsciiStriCmp (
   @param  FirstString   The pointer to a Null-terminated ASCII string.
   @param  SecondString  The pointer to a Null-terminated ASCII string.
   @param  Length        The maximum number of ASCII characters for compare.
-  
+
   @retval ==0       FirstString is identical to SecondString.
   @retval !=0       FirstString is not identical to SecondString.
 
@@ -2187,8 +2073,8 @@ AsciiStrCat (
 /**
   [ATTENTION] This function is deprecated for security reason.
 
-  Concatenates up to a specified length one Null-terminated ASCII string to 
-  the end of another Null-terminated ASCII string, and returns the 
+  Concatenates up to a specified length one Null-terminated ASCII string to
+  the end of another Null-terminated ASCII string, and returns the
   concatenated ASCII string.
 
   This function concatenates two Null-terminated ASCII strings. The contents
@@ -2229,7 +2115,7 @@ AsciiStrnCat (
   IN      CONST CHAR8               *Source,
   IN      UINTN                     Length
   );
-#endif
+#endif // !defined (DISABLE_NEW_DEPRECATED_INTERFACES)
 
 /**
   Returns the first occurrence of a Null-terminated ASCII sub-string
@@ -2442,10 +2328,6 @@ AsciiStrHexToUint64 (
   "::" can be used to compress one or more groups of X when X contains only 0.
   The "::" can only appear once in the String.
 
-  If String is NULL, then ASSERT().
-
-  If Address is NULL, then ASSERT().
-
   If EndPointer is not NULL and Address is translated from String, a pointer
   to the character that stopped the scan is stored at the location pointed to
   by EndPointer.
@@ -2497,10 +2379,6 @@ AsciiStrToIpv6Address (
   When /P is in the String, the function stops at the first character that is not
   a valid decimal digit character after P is converted.
 
-  If String is NULL, then ASSERT().
-
-  If Address is NULL, then ASSERT().
-
   If EndPointer is not NULL and Address is translated from String, a pointer
   to the character that stopped the scan is stored at the location pointed to
   by EndPointer.
@@ -2562,9 +2440,6 @@ AsciiStrToIpv4Address (
                   oo          Data4[48:55]
                   pp          Data4[56:63]
 
-  If String is NULL, then ASSERT().
-  If Guid is NULL, then ASSERT().
-
   @param  String                   Pointer to a Null-terminated ASCII string.
   @param  Guid                     Pointer to the converted GUID.
 
@@ -2595,17 +2470,6 @@ AsciiStrToGuid (
   decoding stops after Length of characters and outputs Buffer containing
   (Length / 2) bytes.
 
-  If String is NULL, then ASSERT().
-
-  If Buffer is NULL, then ASSERT().
-
-  If Length is not multiple of 2, then ASSERT().
-
-  If PcdMaximumAsciiStringLength is not zero and Length is greater than
-  PcdMaximumAsciiStringLength, then ASSERT().
-
-  If MaxBufferSize is less than (Length / 2), then ASSERT().
-
   @param  String                   Pointer to a Null-terminated ASCII string.
   @param  Length                   The number of ASCII characters to decode.
   @param  Buffer                   Pointer to the converted bytes array.
@@ -2670,7 +2534,7 @@ AsciiStrToUnicodeStr (
   OUT     CHAR16                    *Destination
   );
 
-#endif
+#endif // !defined (DISABLE_NEW_DEPRECATED_INTERFACES)
 
 /**
   Convert one Null-terminated ASCII string to a Null-terminated
@@ -2686,7 +2550,6 @@ AsciiStrToUnicodeStr (
   equal or greater than ((AsciiStrLen (Source) + 1) * sizeof (CHAR16)) in bytes.
 
   If Destination is not aligned on a 16-bit boundary, then ASSERT().
-  If an error would be returned, then the function will also ASSERT().
 
   If an error is returned, then the Destination is unmodified.
 
@@ -2732,7 +2595,6 @@ AsciiStrToUnicodeStrS (
   ((MIN(AsciiStrLen(Source), Length) + 1) * sizeof (CHAR8)) in bytes.
 
   If Destination is not aligned on a 16-bit boundary, then ASSERT().
-  If an error would be returned, then the function will also ASSERT().
 
   If an error is returned, then Destination and DestinationLength are
   unmodified.
@@ -2771,6 +2633,165 @@ AsciiStrnToUnicodeStrS (
   );
 
 /**
+  Convert a Unicode character to upper case only if
+  it maps to a valid small-case ASCII character.
+
+  This internal function only deal with Unicode character
+  which maps to a valid small-case ASCII character, i.e.
+  L'a' to L'z'. For other Unicode character, the input character
+  is returned directly.
+
+  @param  Char  The character to convert.
+
+  @retval LowerCharacter   If the Char is with range L'a' to L'z'.
+  @retval Unchanged        Otherwise.
+
+**/
+CHAR16
+EFIAPI
+CharToUpper (
+  IN      CHAR16                    Char
+  );
+
+/**
+  Converts a lowercase Ascii character to upper one.
+
+  If Chr is lowercase Ascii character, then converts it to upper one.
+
+  If Value >= 0xA0, then ASSERT().
+  If (Value & 0x0F) >= 0x0A, then ASSERT().
+
+  @param  Chr   one Ascii character
+
+  @return The uppercase value of Ascii character
+
+**/
+CHAR8
+EFIAPI
+AsciiCharToUpper (
+  IN      CHAR8                     Chr
+  );
+
+/**
+  Convert binary data to a Base64 encoded ascii string based on RFC4648.
+
+  Produce a Null-terminated Ascii string in the output buffer specified by Destination and DestinationSize.
+  The Ascii string is produced by converting the data string specified by Source and SourceLength.
+
+  @param Source           Input UINT8 data
+  @param SourceLength     Number of UINT8 bytes of data
+  @param Destination      Pointer to output string buffer
+  @param DestinationSize  Size of ascii buffer. Set to 0 to get the size needed.
+                          Caller is responsible for passing in buffer of DestinationSize
+
+  @retval RETURN_SUCCESS             When ascii buffer is filled in.
+  @retval RETURN_INVALID_PARAMETER   If Source is NULL or DestinationSize is NULL.
+  @retval RETURN_INVALID_PARAMETER   If SourceLength or DestinationSize is bigger than (MAX_ADDRESS - (UINTN)Destination).
+  @retval RETURN_BUFFER_TOO_SMALL    If SourceLength is 0 and DestinationSize is <1.
+  @retval RETURN_BUFFER_TOO_SMALL    If Destination is NULL or DestinationSize is smaller than required buffersize.
+
+**/
+RETURN_STATUS
+EFIAPI
+Base64Encode (
+  IN  CONST UINT8  *Source,
+  IN        UINTN   SourceLength,
+  OUT       CHAR8  *Destination  OPTIONAL,
+  IN OUT    UINTN  *DestinationSize
+  );
+
+/**
+  Decode Base64 ASCII encoded data to 8-bit binary representation, based on
+  RFC4648.
+
+  Decoding occurs according to "Table 1: The Base 64 Alphabet" in RFC4648.
+
+  Whitespace is ignored at all positions:
+  - 0x09 ('\t') horizontal tab
+  - 0x0A ('\n') new line
+  - 0x0B ('\v') vertical tab
+  - 0x0C ('\f') form feed
+  - 0x0D ('\r') carriage return
+  - 0x20 (' ')  space
+
+  The minimum amount of required padding (with ASCII 0x3D, '=') is tolerated
+  and enforced at the end of the Base64 ASCII encoded data, and only there.
+
+  Other characters outside of the encoding alphabet cause the function to
+  reject the Base64 ASCII encoded data.
+
+  @param[in] Source               Array of CHAR8 elements containing the Base64
+                                  ASCII encoding. May be NULL if SourceSize is
+                                  zero.
+
+  @param[in] SourceSize           Number of CHAR8 elements in Source.
+
+  @param[out] Destination         Array of UINT8 elements receiving the decoded
+                                  8-bit binary representation. Allocated by the
+                                  caller. May be NULL if DestinationSize is
+                                  zero on input. If NULL, decoding is
+                                  performed, but the 8-bit binary
+                                  representation is not stored. If non-NULL and
+                                  the function returns an error, the contents
+                                  of Destination are indeterminate.
+
+  @param[in,out] DestinationSize  On input, the number of UINT8 elements that
+                                  the caller allocated for Destination. On
+                                  output, if the function returns
+                                  RETURN_SUCCESS or RETURN_BUFFER_TOO_SMALL,
+                                  the number of UINT8 elements that are
+                                  required for decoding the Base64 ASCII
+                                  representation. If the function returns a
+                                  value different from both RETURN_SUCCESS and
+                                  RETURN_BUFFER_TOO_SMALL, then DestinationSize
+                                  is indeterminate on output.
+
+  @retval RETURN_SUCCESS            SourceSize CHAR8 elements at Source have
+                                    been decoded to on-output DestinationSize
+                                    UINT8 elements at Destination. Note that
+                                    RETURN_SUCCESS covers the case when
+                                    DestinationSize is zero on input, and
+                                    Source decodes to zero bytes (due to
+                                    containing at most ignored whitespace).
+
+  @retval RETURN_BUFFER_TOO_SMALL   The input value of DestinationSize is not
+                                    large enough for decoding SourceSize CHAR8
+                                    elements at Source. The required number of
+                                    UINT8 elements has been stored to
+                                    DestinationSize.
+
+  @retval RETURN_INVALID_PARAMETER  DestinationSize is NULL.
+
+  @retval RETURN_INVALID_PARAMETER  Source is NULL, but SourceSize is not zero.
+
+  @retval RETURN_INVALID_PARAMETER  Destination is NULL, but DestinationSize is
+                                    not zero on input.
+
+  @retval RETURN_INVALID_PARAMETER  Source is non-NULL, and (Source +
+                                    SourceSize) would wrap around MAX_ADDRESS.
+
+  @retval RETURN_INVALID_PARAMETER  Destination is non-NULL, and (Destination +
+                                    DestinationSize) would wrap around
+                                    MAX_ADDRESS, as specified on input.
+
+  @retval RETURN_INVALID_PARAMETER  None of Source and Destination are NULL,
+                                    and CHAR8[SourceSize] at Source overlaps
+                                    UINT8[DestinationSize] at Destination, as
+                                    specified on input.
+
+  @retval RETURN_INVALID_PARAMETER  Invalid CHAR8 element encountered in
+                                    Source.
+**/
+RETURN_STATUS
+EFIAPI
+Base64Decode (
+  IN     CONST CHAR8 *Source          OPTIONAL,
+  IN     UINTN       SourceSize,
+  OUT    UINT8       *Destination     OPTIONAL,
+  IN OUT UINTN       *DestinationSize
+  );
+
+/**
   Converts an 8-bit value to an 8-bit BCD value.
 
   Converts the 8-bit value specified by Value to BCD. The BCD value is
@@ -2867,6 +2888,59 @@ PathCleanUpDirectories(
 **/
 #define INITIALIZE_LIST_HEAD_VARIABLE(ListHead)  {&(ListHead), &(ListHead)}
 
+/**
+  Iterates over each node in a doubly linked list using each node's forward link.
+
+  @param  Entry     A pointer to a list node used as a loop cursor during iteration
+  @param  ListHead  The head node of the doubly linked list
+
+**/
+#define BASE_LIST_FOR_EACH(Entry, ListHead)    \
+  for(Entry = (ListHead)->ForwardLink; Entry != (ListHead); Entry = Entry->ForwardLink)
+
+/**
+  Iterates over each node in a doubly linked list using each node's forward link
+  with safety against node removal.
+
+  This macro uses NextEntry to temporarily store the next list node so the node
+  pointed to by Entry may be deleted in the current loop iteration step and
+  iteration can continue from the node pointed to by NextEntry.
+
+  @param  Entry     A pointer to a list node used as a loop cursor during iteration
+  @param  NextEntry A pointer to a list node used to temporarily store the next node
+  @param  ListHead  The head node of the doubly linked list
+
+**/
+#define BASE_LIST_FOR_EACH_SAFE(Entry, NextEntry, ListHead)            \
+  for(Entry = (ListHead)->ForwardLink, NextEntry = Entry->ForwardLink;\
+      Entry != (ListHead); Entry = NextEntry, NextEntry = Entry->ForwardLink)
+
+/**
+  Checks whether FirstEntry and SecondEntry are part of the same doubly-linked
+  list.
+
+  If FirstEntry is NULL, then ASSERT().
+  If FirstEntry->ForwardLink is NULL, then ASSERT().
+  If FirstEntry->BackLink is NULL, then ASSERT().
+  If SecondEntry is NULL, then ASSERT();
+  If PcdMaximumLinkedListLength is not zero, and List contains more than
+  PcdMaximumLinkedListLength nodes, then ASSERT().
+
+  @param  FirstEntry   A pointer to a node in a linked list.
+  @param  SecondEntry  A pointer to the node to locate.
+
+  @retval TRUE   SecondEntry is in the same doubly-linked list as FirstEntry.
+  @retval FALSE  SecondEntry isn't in the same doubly-linked list as FirstEntry,
+                 or FirstEntry is invalid.
+
+**/
+BOOLEAN
+EFIAPI
+IsNodeInList (
+  IN      CONST LIST_ENTRY      *FirstEntry,
+  IN      CONST LIST_ENTRY      *SecondEntry
+  );
+
 
 /**
   Initializes the head node of a doubly linked list, and returns the pointer to
@@ -2930,7 +3004,7 @@ InsertHeadList (
 
   If ListHead is NULL, then ASSERT().
   If Entry is NULL, then ASSERT().
-  If ListHead was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or 
+  If ListHead was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or
   InitializeListHead(), then ASSERT().
   If PcdMaximumLinkedListLength is not zero, and prior to insertion the number
   of nodes in ListHead, including the ListHead node, is greater than or
@@ -2954,12 +3028,12 @@ InsertTailList (
 /**
   Retrieves the first node of a doubly linked list.
 
-  Returns the first node of a doubly linked list.  List must have been 
+  Returns the first node of a doubly linked list.  List must have been
   initialized with INTIALIZE_LIST_HEAD_VARIABLE() or InitializeListHead().
   If List is empty, then List is returned.
 
   If List is NULL, then ASSERT().
-  If List was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or 
+  If List was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or
   InitializeListHead(), then ASSERT().
   If PcdMaximumLinkedListLength is not zero, and the number of nodes
   in List, including the List node, is greater than or equal to
@@ -2981,13 +3055,13 @@ GetFirstNode (
 /**
   Retrieves the next node of a doubly linked list.
 
-  Returns the node of a doubly linked list that follows Node.  
+  Returns the node of a doubly linked list that follows Node.
   List must have been initialized with INTIALIZE_LIST_HEAD_VARIABLE()
   or InitializeListHead().  If List is empty, then List is returned.
 
   If List is NULL, then ASSERT().
   If Node is NULL, then ASSERT().
-  If List was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or 
+  If List was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or
   InitializeListHead(), then ASSERT().
   If PcdMaximumLinkedListLength is not zero, and List contains more than
   PcdMaximumLinkedListLength nodes, then ASSERT().
@@ -3006,27 +3080,27 @@ GetNextNode (
   IN      CONST LIST_ENTRY          *Node
   );
 
-  
+
 /**
   Retrieves the previous node of a doubly linked list.
- 
-  Returns the node of a doubly linked list that precedes Node.  
+
+  Returns the node of a doubly linked list that precedes Node.
   List must have been initialized with INTIALIZE_LIST_HEAD_VARIABLE()
   or InitializeListHead().  If List is empty, then List is returned.
- 
+
   If List is NULL, then ASSERT().
   If Node is NULL, then ASSERT().
-  If List was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or 
+  If List was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or
   InitializeListHead(), then ASSERT().
   If PcdMaximumLinkedListLength is not zero, and List contains more than
   PcdMaximumLinkedListLength nodes, then ASSERT().
   If PcdVerifyNodeInList is TRUE and Node is not a node in List, then ASSERT().
- 
+
   @param  List  A pointer to the head node of a doubly linked list.
   @param  Node  A pointer to a node in the doubly linked list.
- 
+
   @return The pointer to the previous node if one exists. Otherwise List is returned.
- 
+
 **/
 LIST_ENTRY *
 EFIAPI
@@ -3035,7 +3109,7 @@ GetPreviousNode (
   IN      CONST LIST_ENTRY          *Node
   );
 
-  
+
 /**
   Checks to see if a doubly linked list is empty or not.
 
@@ -3043,7 +3117,7 @@ GetPreviousNode (
   zero nodes, this function returns TRUE. Otherwise, it returns FALSE.
 
   If ListHead is NULL, then ASSERT().
-  If ListHead was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or 
+  If ListHead was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or
   InitializeListHead(), then ASSERT().
   If PcdMaximumLinkedListLength is not zero, and the number of nodes
   in List, including the List node, is greater than or equal to
@@ -3073,12 +3147,12 @@ IsListEmpty (
 
   If List is NULL, then ASSERT().
   If Node is NULL, then ASSERT().
-  If List was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or InitializeListHead(), 
+  If List was not initialized with INTIALIZE_LIST_HEAD_VARIABLE() or InitializeListHead(),
   then ASSERT().
   If PcdMaximumLinkedListLength is not zero, and the number of nodes
   in List, including the List node, is greater than or equal to
   PcdMaximumLinkedListLength, then ASSERT().
-  If PcdVerifyNodeInList is TRUE and Node is not a node in List the and Node is not equal 
+  If PcdVerifyNodeInList is TRUE and Node is not a node in List the and Node is not equal
   to List, then ASSERT().
 
   @param  List  A pointer to the head node of a doubly linked list.
@@ -3135,12 +3209,12 @@ IsNodeAtEnd (
   Otherwise, the location of the FirstEntry node is swapped with the location
   of the SecondEntry node in a doubly linked list. SecondEntry must be in the
   same double linked list as FirstEntry and that double linked list must have
-  been initialized with INTIALIZE_LIST_HEAD_VARIABLE() or InitializeListHead(). 
+  been initialized with INTIALIZE_LIST_HEAD_VARIABLE() or InitializeListHead().
   SecondEntry is returned after the nodes are swapped.
 
   If FirstEntry is NULL, then ASSERT().
   If SecondEntry is NULL, then ASSERT().
-  If PcdVerifyNodeInList is TRUE and SecondEntry and FirstEntry are not in the 
+  If PcdVerifyNodeInList is TRUE and SecondEntry and FirstEntry are not in the
   same linked list, then ASSERT().
   If PcdMaximumLinkedListLength is not zero, and the number of nodes in the
   linked list containing the FirstEntry and SecondEntry nodes, including
@@ -3149,7 +3223,7 @@ IsNodeAtEnd (
 
   @param  FirstEntry  A pointer to a node in a linked list.
   @param  SecondEntry A pointer to another node in the same linked list.
-  
+
   @return SecondEntry.
 
 **/
@@ -3717,7 +3791,7 @@ DivU64x64Remainder (
   function returns the 64-bit signed quotient.
 
   It is the caller's responsibility to not call this function with a Divisor of 0.
-  If Divisor is 0, then the quotient and remainder should be assumed to be 
+  If Divisor is 0, then the quotient and remainder should be assumed to be
   the largest negative integer.
 
   If Divisor is 0, then ASSERT().
@@ -4049,7 +4123,7 @@ BitFieldAnd8 (
   bitwise OR, and returns the result.
 
   Performs a bitwise AND between the bit field specified by StartBit and EndBit
-  in Operand and the value specified by AndData, followed by a bitwise 
+  in Operand and the value specified by AndData, followed by a bitwise
   OR with value specified by OrData. All other bits in Operand are
   preserved. The new 8-bit value is returned.
 
@@ -4216,7 +4290,7 @@ BitFieldAnd16 (
   bitwise OR, and returns the result.
 
   Performs a bitwise AND between the bit field specified by StartBit and EndBit
-  in Operand and the value specified by AndData, followed by a bitwise 
+  in Operand and the value specified by AndData, followed by a bitwise
   OR with value specified by OrData. All other bits in Operand are
   preserved. The new 16-bit value is returned.
 
@@ -4383,7 +4457,7 @@ BitFieldAnd32 (
   bitwise OR, and returns the result.
 
   Performs a bitwise AND between the bit field specified by StartBit and EndBit
-  in Operand and the value specified by AndData, followed by a bitwise 
+  in Operand and the value specified by AndData, followed by a bitwise
   OR with value specified by OrData. All other bits in Operand are
   preserved. The new 32-bit value is returned.
 
@@ -4550,7 +4624,7 @@ BitFieldAnd64 (
   bitwise OR, and returns the result.
 
   Performs a bitwise AND between the bit field specified by StartBit and EndBit
-  in Operand and the value specified by AndData, followed by a bitwise 
+  in Operand and the value specified by AndData, followed by a bitwise
   OR with value specified by OrData. All other bits in Operand are
   preserved. The new 64-bit value is returned.
 
@@ -4582,6 +4656,62 @@ BitFieldAndThenOr64 (
   IN      UINT64                    OrData
   );
 
+/**
+  Reads a bit field from a 32-bit value, counts and returns
+  the number of set bits.
+
+  Counts the number of set bits in the  bit field specified by
+  StartBit and EndBit in Operand. The count is returned.
+
+  If StartBit is greater than 31, then ASSERT().
+  If EndBit is greater than 31, then ASSERT().
+  If EndBit is less than StartBit, then ASSERT().
+
+  @param  Operand   Operand on which to perform the bitfield operation.
+  @param  StartBit  The ordinal of the least significant bit in the bit field.
+                    Range 0..31.
+  @param  EndBit    The ordinal of the most significant bit in the bit field.
+                    Range 0..31.
+
+  @return The number of bits set between StartBit and EndBit.
+
+**/
+UINT8
+EFIAPI
+BitFieldCountOnes32 (
+  IN       UINT32                   Operand,
+  IN       UINTN                    StartBit,
+  IN       UINTN                    EndBit
+  );
+
+/**
+   Reads a bit field from a 64-bit value, counts and returns
+   the number of set bits.
+
+   Counts the number of set bits in the  bit field specified by
+   StartBit and EndBit in Operand. The count is returned.
+
+   If StartBit is greater than 63, then ASSERT().
+   If EndBit is greater than 63, then ASSERT().
+   If EndBit is less than StartBit, then ASSERT().
+
+   @param  Operand   Operand on which to perform the bitfield operation.
+   @param  StartBit  The ordinal of the least significant bit in the bit field.
+   Range 0..63.
+   @param  EndBit    The ordinal of the most significant bit in the bit field.
+   Range 0..63.
+
+   @return The number of bits set between StartBit and EndBit.
+
+**/
+UINT8
+EFIAPI
+BitFieldCountOnes64 (
+  IN       UINT64                   Operand,
+  IN       UINTN                    StartBit,
+  IN       UINTN                    EndBit
+  );
+
 //
 // Base Library Checksum Functions
 //
@@ -4802,6 +4932,25 @@ CalculateCheckSum64 (
   IN      UINTN                     Length
   );
 
+/**
+  Computes and returns a 32-bit CRC for a data buffer.
+  CRC32 value bases on ITU-T V.42.
+
+  If Buffer is NULL, then ASSERT().
+  If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
+
+  @param[in]  Buffer       A pointer to the buffer on which the 32-bit CRC is to be computed.
+  @param[in]  Length       The number of bytes in the buffer Data.
+
+  @retval Crc32            The 32-bit CRC was computed for the data buffer.
+
+**/
+UINT32
+EFIAPI
+CalculateCrc32(
+  IN  VOID                         *Buffer,
+  IN  UINTN                        Length
+  );
 
 //
 // Base Library CPU Functions
@@ -4846,17 +4995,18 @@ MemoryFence (
 
   If JumpBuffer is NULL, then ASSERT().
   For Itanium processors, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().
-  
+
   NOTE: The structure BASE_LIBRARY_JUMP_BUFFER is CPU architecture specific.
   The same structure must never be used for more than one CPU architecture context.
-  For example, a BASE_LIBRARY_JUMP_BUFFER allocated by an IA-32 module must never be used from an x64 module. 
-  SetJump()/LongJump() is not currently supported for the EBC processor type.   
+  For example, a BASE_LIBRARY_JUMP_BUFFER allocated by an IA-32 module must never be used from an x64 module.
+  SetJump()/LongJump() is not currently supported for the EBC processor type.
 
   @param  JumpBuffer  A pointer to CPU context buffer.
 
   @retval 0 Indicates a return from SetJump().
 
 **/
+RETURNS_TWICE
 UINTN
 EFIAPI
 SetJump (
@@ -5011,9 +5161,9 @@ CpuPause (
                       function.
   @param  NewStack    A pointer to the new stack to use for the EntryPoint
                       function.
-  @param  ...         This variable argument list is ignored for IA-32, x64, and 
-                      EBC architectures.  For Itanium processors, this variable 
-                      argument list is expected to contain a single parameter of 
+  @param  ...         This variable argument list is ignored for IA-32, x64, and
+                      EBC architectures.  For Itanium processors, this variable
+                      argument list is expected to contain a single parameter of
                       type VOID * that specifies the new backing store pointer.
 
 
@@ -5057,1399 +5207,22 @@ EFIAPI
 CpuDeadLoop (
   VOID
   );
- 
-#if defined (MDE_CPU_IPF)
-
-/**
-  Flush a range of  cache lines in the cache coherency domain of the calling
-  CPU.
-
-  Flushes the cache lines specified by Address and Length.  If Address is not aligned 
-  on a cache line boundary, then entire cache line containing Address is flushed.  
-  If Address + Length is not aligned on a cache line boundary, then the entire cache 
-  line containing Address + Length - 1 is flushed.  This function may choose to flush 
-  the entire cache if that is more efficient than flushing the specified range.  If 
-  Length is 0, the no cache lines are flushed.  Address is returned.   
-  This function is only available on Itanium processors.
-
-  If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
-
-  @param  Address The base address of the instruction lines to invalidate. If
-                  the CPU is in a physical addressing mode, then Address is a
-                  physical address. If the CPU is in a virtual addressing mode,
-                  then Address is a virtual address.
-
-  @param  Length  The number of bytes to invalidate from the instruction cache.
-
-  @return Address.
-
-**/
-VOID *
-EFIAPI
-AsmFlushCacheRange (
-  IN      VOID                      *Address,
-  IN      UINTN                     Length
-  );
-
-
-/**
-  Executes an FC instruction.
-  Executes an FC instruction on the cache line specified by Address.
-  The cache line size affected is at least 32-bytes (aligned on a 32-byte boundary).
-  An implementation may flush a larger region.  This function is only available on Itanium processors.
-
-  @param Address    The Address of cache line to be flushed.
-
-  @return The address of FC instruction executed.
-
-**/
-UINT64
-EFIAPI
-AsmFc (
-  IN  UINT64  Address
-  );
-
-
-/**
-  Executes an FC.I instruction.
-  Executes an FC.I instruction on the cache line specified by Address.
-  The cache line size affected is at least 32-bytes (aligned on a 32-byte boundary).
-  An implementation may flush a larger region.  This function is only available on Itanium processors.
-
-  @param Address    The Address of cache line to be flushed.
-
-  @return The address of the FC.I instruction executed.
-
-**/
-UINT64
-EFIAPI
-AsmFci (
-  IN  UINT64  Address
-  );
-
-
-/**
-  Reads the current value of a Processor Identifier Register (CPUID).
-  
-  Reads and returns the current value of Processor Identifier Register specified by Index. 
-  The Index of largest implemented CPUID (One less than the number of implemented CPUID
-  registers) is determined by CPUID [3] bits {7:0}.
-  No parameter checking is performed on Index.  If the Index value is beyond the
-  implemented CPUID register range, a Reserved Register/Field fault may occur.  The caller
-  must either guarantee that Index is valid, or the caller must set up fault handlers to
-  catch the faults.  This function is only available on Itanium processors.
-
-  @param Index    The 8-bit Processor Identifier Register index to read.
-
-  @return The current value of Processor Identifier Register specified by Index.
-
-**/
-UINT64
-EFIAPI
-AsmReadCpuid (
-  IN  UINT8   Index
-  );
-
-
-/**
-  Reads the current value of 64-bit Processor Status Register (PSR).
-  This function is only available on Itanium processors.
-
-  @return The current value of PSR.
-
-**/
-UINT64
-EFIAPI
-AsmReadPsr (
-  VOID
-  );
-
-
-/**
-  Writes the current value of 64-bit Processor Status Register (PSR).
-
-  No parameter checking is performed on Value.  All bits of Value corresponding to
-  reserved fields of PSR must be 0 or a Reserved Register/Field fault may occur.
-  The caller must either guarantee that Value is valid, or the caller must set up
-  fault handlers to catch the faults. This function is only available on Itanium processors.
-
-  @param Value    The 64-bit value to write to PSR.
-
-  @return The 64-bit value written to the PSR.
-
-**/
-UINT64
-EFIAPI
-AsmWritePsr (
-  IN UINT64  Value
-  );
-
-
-/**
-  Reads the current value of 64-bit Kernel Register #0 (KR0).
-  
-  Reads and returns the current value of KR0. 
-  This function is only available on Itanium processors.
-
-  @return The current value of KR0.
-
-**/
-UINT64
-EFIAPI
-AsmReadKr0 (
-  VOID
-  );
-
-
-/**
-  Reads the current value of 64-bit Kernel Register #1 (KR1).
-
-  Reads and returns the current value of KR1. 
-  This function is only available on Itanium processors.
-
-  @return The current value of KR1.
-
-**/
-UINT64
-EFIAPI
-AsmReadKr1 (
-  VOID
-  );
-
-
-/**
-  Reads the current value of 64-bit Kernel Register #2 (KR2).
-
-  Reads and returns the current value of KR2. 
-  This function is only available on Itanium processors.
-
-  @return The current value of KR2.
-
-**/
-UINT64
-EFIAPI
-AsmReadKr2 (
-  VOID
-  );
-
-
-/**
-  Reads the current value of 64-bit Kernel Register #3 (KR3).
-
-  Reads and returns the current value of KR3. 
-  This function is only available on Itanium processors.
-
-  @return The current value of KR3.
-
-**/
-UINT64
-EFIAPI
-AsmReadKr3 (
-  VOID
-  );
-
-
-/**
-  Reads the current value of 64-bit Kernel Register #4 (KR4).
-
-  Reads and returns the current value of KR4. 
-  This function is only available on Itanium processors.
-  
-  @return The current value of KR4.
-
-**/
-UINT64
-EFIAPI
-AsmReadKr4 (
-  VOID
-  );
-
-
-/**
-  Reads the current value of 64-bit Kernel Register #5 (KR5).
-
-  Reads and returns the current value of KR5. 
-  This function is only available on Itanium processors.
-
-  @return The current value of KR5.
-
-**/
-UINT64
-EFIAPI
-AsmReadKr5 (
-  VOID
-  );
-
-
-/**
-  Reads the current value of 64-bit Kernel Register #6 (KR6).
-
-  Reads and returns the current value of KR6. 
-  This function is only available on Itanium processors.
-
-  @return The current value of KR6.
-
-**/
-UINT64
-EFIAPI
-AsmReadKr6 (
-  VOID
-  );
 
 
 /**
-  Reads the current value of 64-bit Kernel Register #7 (KR7).
+  Uses as a barrier to stop speculative execution.
 
-  Reads and returns the current value of KR7. 
-  This function is only available on Itanium processors.
-
-  @return The current value of KR7.
-
-**/
-UINT64
-EFIAPI
-AsmReadKr7 (
-  VOID
-  );
-
-
-/**
-  Write the current value of 64-bit Kernel Register #0 (KR0).
-  
-  Writes the current value of KR0.  The 64-bit value written to 
-  the KR0 is returned. This function is only available on Itanium processors.
-
-  @param  Value   The 64-bit value to write to KR0.
-
-  @return The 64-bit value written to the KR0.
-
-**/
-UINT64
-EFIAPI
-AsmWriteKr0 (
-  IN UINT64  Value
-  );
-
-
-/**
-  Write the current value of 64-bit Kernel Register #1 (KR1).
-
-  Writes the current value of KR1.  The 64-bit value written to 
-  the KR1 is returned. This function is only available on Itanium processors.
-
-  @param  Value   The 64-bit value to write to KR1.
-
-  @return The 64-bit value written to the KR1.
-
-**/
-UINT64
-EFIAPI
-AsmWriteKr1 (
-  IN UINT64  Value
-  );
-
-
-/**
-  Write the current value of 64-bit Kernel Register #2 (KR2).
-
-  Writes the current value of KR2.  The 64-bit value written to 
-  the KR2 is returned. This function is only available on Itanium processors.
-
-  @param  Value   The 64-bit value to write to KR2.
-
-  @return The 64-bit value written to the KR2.
-
-**/
-UINT64
-EFIAPI
-AsmWriteKr2 (
-  IN UINT64  Value
-  );
-
-
-/**
-  Write the current value of 64-bit Kernel Register #3 (KR3).
-
-  Writes the current value of KR3.  The 64-bit value written to 
-  the KR3 is returned. This function is only available on Itanium processors.
-
-  @param  Value   The 64-bit value to write to KR3.
-
-  @return The 64-bit value written to the KR3.
-
-**/
-UINT64
-EFIAPI
-AsmWriteKr3 (
-  IN UINT64  Value
-  );
-
-
-/**
-  Write the current value of 64-bit Kernel Register #4 (KR4).
-
-  Writes the current value of KR4.  The 64-bit value written to 
-  the KR4 is returned. This function is only available on Itanium processors.
-
-  @param  Value   The 64-bit value to write to KR4.
-
-  @return The 64-bit value written to the KR4.
-
-**/
-UINT64
-EFIAPI
-AsmWriteKr4 (
-  IN UINT64  Value
-  );
-
-
-/**
-  Write the current value of 64-bit Kernel Register #5 (KR5).
-
-  Writes the current value of KR5.  The 64-bit value written to 
-  the KR5 is returned. This function is only available on Itanium processors.
-
-  @param  Value   The 64-bit value to write to KR5.
-
-  @return The 64-bit value written to the KR5.
-
-**/
-UINT64
-EFIAPI
-AsmWriteKr5 (
-  IN UINT64  Value
-  );
-
-
-/**
-  Write the current value of 64-bit Kernel Register #6 (KR6).
-
-  Writes the current value of KR6.  The 64-bit value written to 
-  the KR6 is returned. This function is only available on Itanium processors.
-
-  @param  Value   The 64-bit value to write to KR6.
-
-  @return The 64-bit value written to the KR6.
-
-**/
-UINT64
-EFIAPI
-AsmWriteKr6 (
-  IN UINT64  Value
-  );
-
-
-/**
-  Write the current value of 64-bit Kernel Register #7 (KR7).
-
-  Writes the current value of KR7.  The 64-bit value written to 
-  the KR7 is returned. This function is only available on Itanium processors.
-
-  @param  Value   The 64-bit value to write to KR7.
-
-  @return The 64-bit value written to the KR7.
-
-**/
-UINT64
-EFIAPI
-AsmWriteKr7 (
-  IN UINT64  Value
-  );
-
-
-/**
-  Reads the current value of Interval Timer Counter Register (ITC).
-  
-  Reads and returns the current value of ITC.
-  This function is only available on Itanium processors.
-
-  @return The current value of ITC.
-
-**/
-UINT64
-EFIAPI
-AsmReadItc (
-  VOID
-  );
-
-
-/**
-  Reads the current value of Interval Timer Vector Register (ITV).
-  
-  Reads and returns the current value of ITV. 
-  This function is only available on Itanium processors.
-
-  @return The current value of ITV.
-
-**/
-UINT64
-EFIAPI
-AsmReadItv (
-  VOID
-  );
-
-
-/**
-  Reads the current value of Interval Timer Match Register (ITM).
-  
-  Reads and returns the current value of ITM.
-  This function is only available on Itanium processors.
-
-  @return The current value of ITM.
-**/
-UINT64
-EFIAPI
-AsmReadItm (
-  VOID
-  );
-
-
-/**
-  Writes the current value of 64-bit Interval Timer Counter Register (ITC).
-  
-  Writes the current value of ITC.  The 64-bit value written to the ITC is returned. 
-  This function is only available on Itanium processors.
-
-  @param Value    The 64-bit value to write to ITC.
-
-  @return The 64-bit value written to the ITC.
-
-**/
-UINT64
-EFIAPI
-AsmWriteItc (
-  IN UINT64  Value
-  );
-
-
-/**
-  Writes the current value of 64-bit Interval Timer Match Register (ITM).
-  
-  Writes the current value of ITM.  The 64-bit value written to the ITM is returned. 
-  This function is only available on Itanium processors.
-
-  @param Value    The 64-bit value to write to ITM.
-
-  @return The 64-bit value written to the ITM.
-
-**/
-UINT64
-EFIAPI
-AsmWriteItm (
-  IN UINT64  Value
-  );
-
-
-/**
-  Writes the current value of 64-bit Interval Timer Vector Register (ITV).
-  
-  Writes the current value of ITV.  The 64-bit value written to the ITV is returned.  
-  No parameter checking is performed on Value.  All bits of Value corresponding to
-  reserved fields of ITV must be 0 or a Reserved Register/Field fault may occur.
-  The caller must either guarantee that Value is valid, or the caller must set up
-  fault handlers to catch the faults.
-  This function is only available on Itanium processors.
-
-  @param Value    The 64-bit value to write to ITV.
-
-  @return The 64-bit value written to the ITV.
-
-**/
-UINT64
-EFIAPI
-AsmWriteItv (
-  IN UINT64  Value
-  );
-
-
-/**
-  Reads the current value of Default Control Register (DCR).
-  
-  Reads and returns the current value of DCR.  This function is only available on Itanium processors.
-
-  @return The current value of DCR.
-
-**/
-UINT64
-EFIAPI
-AsmReadDcr (
-  VOID
-  );
-
-
-/**
-  Reads the current value of Interruption Vector Address Register (IVA).
-  
-  Reads and returns the current value of IVA.  This function is only available on Itanium processors.
-
-  @return The current value of IVA.
-**/
-UINT64
-EFIAPI
-AsmReadIva (
-  VOID
-  );
-
-
-/**
-  Reads the current value of Page Table Address Register (PTA).
-  
-  Reads and returns the current value of PTA.  This function is only available on Itanium processors.
-
-  @return The current value of PTA.
-
-**/
-UINT64
-EFIAPI
-AsmReadPta (
-  VOID
-  );
-
-
-/**
-  Writes the current value of 64-bit Default Control Register (DCR).
-  
-  Writes the current value of DCR.  The 64-bit value written to the DCR is returned. 
-  No parameter checking is performed on Value.  All bits of Value corresponding to
-  reserved fields of DCR must be 0 or a Reserved Register/Field fault may occur.
-  The caller must either guarantee that Value is valid, or the caller must set up
-  fault handlers to catch the faults.
-  This function is only available on Itanium processors.
-
-  @param Value    The 64-bit value to write to DCR.
-
-  @return The 64-bit value written to the DCR.
-
-**/
-UINT64
-EFIAPI
-AsmWriteDcr (
-  IN UINT64  Value
-  );
-
-
-/**
-  Writes the current value of 64-bit Interruption Vector Address Register (IVA).
-  
-  Writes the current value of IVA.  The 64-bit value written to the IVA is returned.  
-  The size of vector table is 32 K bytes and is 32 K bytes aligned
-  the low 15 bits of Value is ignored when written.
-  This function is only available on Itanium processors.
-
-  @param Value    The 64-bit value to write to IVA.
-
-  @return The 64-bit value written to the IVA.
-
-**/
-UINT64
-EFIAPI
-AsmWriteIva (
-  IN UINT64  Value
-  );
-
-
-/**
-  Writes the current value of 64-bit Page Table Address Register (PTA).
-  
-  Writes the current value of PTA.  The 64-bit value written to the PTA is returned. 
-  No parameter checking is performed on Value.  All bits of Value corresponding to
-  reserved fields of DCR must be 0 or a Reserved Register/Field fault may occur.
-  The caller must either guarantee that Value is valid, or the caller must set up
-  fault handlers to catch the faults.
-  This function is only available on Itanium processors.
-
-  @param Value    The 64-bit value to write to PTA.
-
-  @return The 64-bit value written to the PTA.
-**/
-UINT64
-EFIAPI
-AsmWritePta (
-  IN UINT64  Value
-  );
-
-
-/**
-  Reads the current value of Local Interrupt ID Register (LID).
-  
-  Reads and returns the current value of LID.  This function is only available on Itanium processors.
-
-  @return The current value of LID.
-
-**/
-UINT64
-EFIAPI
-AsmReadLid (
-  VOID
-  );
-
-
-/**
-  Reads the current value of External Interrupt Vector Register (IVR).
-  
-  Reads and returns the current value of IVR.  This function is only available on Itanium processors. 
-
-  @return The current value of IVR.
-
-**/
-UINT64
-EFIAPI
-AsmReadIvr (
-  VOID
-  );
-
-
-/**
-  Reads the current value of Task Priority Register (TPR).
-  
-  Reads and returns the current value of TPR.  This function is only available on Itanium processors. 
-
-  @return The current value of TPR.
-
-**/
-UINT64
-EFIAPI
-AsmReadTpr (
-  VOID
-  );
-
-
-/**
-  Reads the current value of External Interrupt Request Register #0 (IRR0).
-  
-  Reads and returns the current value of IRR0.  This function is only available on Itanium processors.  
-
-  @return The current value of IRR0.
-
-**/
-UINT64
-EFIAPI
-AsmReadIrr0 (
-  VOID
-  );
-
-
-/**
-  Reads the current value of External Interrupt Request Register #1 (IRR1).
-  
-  Reads and returns the current value of IRR1.  This function is only available on Itanium processors. 
-
-  @return The current value of IRR1.
-
-**/
-UINT64
-EFIAPI
-AsmReadIrr1 (
-  VOID
-  );
-
-
-/**
-  Reads the current value of External Interrupt Request Register #2 (IRR2).
-  
-  Reads and returns the current value of IRR2.  This function is only available on Itanium processors.
-
-  @return The current value of IRR2.
-
-**/
-UINT64
-EFIAPI
-AsmReadIrr2 (
-  VOID
-  );
-
-
-/**
-  Reads the current value of External Interrupt Request Register #3 (IRR3).
-  
-  Reads and returns the current value of IRR3.  This function is only available on Itanium processors.  
-
-  @return The current value of IRR3.
-
-**/
-UINT64
-EFIAPI
-AsmReadIrr3 (
-  VOID
-  );
-
-
-/**
-  Reads the current value of Performance Monitor Vector Register (PMV).
-  
-  Reads and returns the current value of PMV.  This function is only available on Itanium processors. 
-
-  @return The current value of PMV.
-
-**/
-UINT64
-EFIAPI
-AsmReadPmv (
-  VOID
-  );
-
-
-/**
-  Reads the current value of Corrected Machine Check Vector Register (CMCV).
-  
-  Reads and returns the current value of CMCV.  This function is only available on Itanium processors.
-
-  @return The current value of CMCV.
-
-**/
-UINT64
-EFIAPI
-AsmReadCmcv (
-  VOID
-  );
-
-
-/**
-  Reads the current value of Local Redirection Register #0 (LRR0).
-  
-  Reads and returns the current value of LRR0.  This function is only available on Itanium processors. 
-
-  @return The current value of LRR0.
-
-**/
-UINT64
-EFIAPI
-AsmReadLrr0 (
-  VOID
-  );
-
-
-/**
-  Reads the current value of Local Redirection Register #1 (LRR1).
-  
-  Reads and returns the current value of LRR1.  This function is only available on Itanium processors.
-
-  @return The current value of LRR1.
-
-**/
-UINT64
-EFIAPI
-AsmReadLrr1 (
-  VOID
-  );
-
-
-/**
-  Writes the current value of 64-bit Page Local Interrupt ID Register (LID).
-  
-  Writes the current value of LID.  The 64-bit value written to the LID is returned.  
-  No parameter checking is performed on Value.  All bits of Value corresponding to
-  reserved fields of LID must be 0 or a Reserved Register/Field fault may occur.
-  The caller must either guarantee that Value is valid, or the caller must set up
-  fault handlers to catch the faults.
-  This function is only available on Itanium processors.
-
-  @param Value    The 64-bit value to write to LID.
-
-  @return The 64-bit value written to the LID.
-
-**/
-UINT64
-EFIAPI
-AsmWriteLid (
-  IN UINT64  Value
-  );
-
-
-/**
-  Writes the current value of 64-bit Task Priority Register (TPR).
-  
-  Writes the current value of TPR.  The 64-bit value written to the TPR is returned. 
-  No parameter checking is performed on Value.  All bits of Value corresponding to
-  reserved fields of TPR must be 0 or a Reserved Register/Field fault may occur.
-  The caller must either guarantee that Value is valid, or the caller must set up
-  fault handlers to catch the faults.
-  This function is only available on Itanium processors.
-
-  @param Value    The 64-bit value to write to TPR.
-
-  @return The 64-bit value written to the TPR.
-
-**/
-UINT64
-EFIAPI
-AsmWriteTpr (
-  IN UINT64  Value
-  );
-
-
-/**
-  Performs a write operation on End OF External Interrupt Register (EOI).
-  
-  Writes a value of 0 to the EOI Register.  This function is only available on Itanium processors.
+  Ensures that no later instruction will execute speculatively, until all prior
+  instructions have completed.
 
 **/
 VOID
 EFIAPI
-AsmWriteEoi (
+SpeculationBarrier (
   VOID
   );
 
 
-/**
-  Writes the current value of 64-bit Performance Monitor Vector Register (PMV).
-  
-  Writes the current value of PMV.  The 64-bit value written to the PMV is returned.  
-  No parameter checking is performed on Value.  All bits of Value corresponding
-  to reserved fields of PMV must be 0 or a Reserved Register/Field fault may occur.
-  The caller must either guarantee that Value is valid, or the caller must set up
-  fault handlers to catch the faults.
-  This function is only available on Itanium processors.
-
-  @param Value    The 64-bit value to write to PMV.
-
-  @return The 64-bit value written to the PMV.
-
-**/
-UINT64
-EFIAPI
-AsmWritePmv (
-  IN UINT64  Value
-  );
-
-
-/**
-  Writes the current value of 64-bit Corrected Machine Check Vector Register (CMCV).
-  
-  Writes the current value of CMCV.  The 64-bit value written to the CMCV is returned. 
-  No parameter checking is performed on Value.  All bits of Value corresponding
-  to reserved fields of CMCV must be 0 or a Reserved Register/Field fault may occur.
-  The caller must either guarantee that Value is valid, or the caller must set up
-  fault handlers to catch the faults.
-  This function is only available on Itanium processors.
-
-  @param Value    The 64-bit value to write to CMCV.
-
-  @return The 64-bit value written to the CMCV.
-
-**/
-UINT64
-EFIAPI
-AsmWriteCmcv (
-  IN UINT64  Value
-  );
-
-
-/**
-  Writes the current value of 64-bit Local Redirection Register #0 (LRR0).
-  
-  Writes the current value of LRR0.  The 64-bit value written to the LRR0 is returned.  
-  No parameter checking is performed on Value.  All bits of Value corresponding
-  to reserved fields of LRR0 must be 0 or a Reserved Register/Field fault may occur.
-  The caller must either guarantee that Value is valid, or the caller must set up
-  fault handlers to catch the faults.
-  This function is only available on Itanium processors.
-
-  @param Value    The 64-bit value to write to LRR0.
-
-  @return The 64-bit value written to the LRR0.
-
-**/
-UINT64
-EFIAPI
-AsmWriteLrr0 (
-  IN UINT64  Value
-  );
-
-
-/**
-  Writes the current value of 64-bit Local Redirection Register #1 (LRR1).
-  
-  Writes the current value of LRR1.  The 64-bit value written to the LRR1 is returned. 
-  No parameter checking is performed on Value.  All bits of Value corresponding
-  to reserved fields of LRR1 must be 0 or a Reserved Register/Field fault may occur.
-  The caller must either guarantee that Value is valid, or the caller must
-  set up fault handlers to catch the faults.
-  This function is only available on Itanium processors.
-
-  @param Value    The 64-bit value to write to LRR1.
-
-  @return The 64-bit value written to the LRR1.
-
-**/
-UINT64
-EFIAPI
-AsmWriteLrr1 (
-  IN UINT64  Value
-  );
-
-
-/**
-  Reads the current value of Instruction Breakpoint Register (IBR).
-  
-  The Instruction Breakpoint Registers are used in pairs.  The even numbered
-  registers contain breakpoint addresses, and the odd numbered registers contain
-  breakpoint mask conditions.  At least four instruction registers pairs are implemented
-  on all processor models.   Implemented registers are contiguous starting with
-  register 0.  No parameter checking is performed on Index, and if the Index value
-  is beyond the implemented IBR register range, a Reserved Register/Field fault may
-  occur.  The caller must either guarantee that Index is valid, or the caller must
-  set up fault handlers to catch the faults.
-  This function is only available on Itanium processors.
-
-  @param Index    The 8-bit Instruction Breakpoint Register index to read.
-
-  @return The current value of Instruction Breakpoint Register specified by Index.
-
-**/
-UINT64
-EFIAPI
-AsmReadIbr (
-  IN  UINT8   Index
-  );
-
-
-/**
-  Reads the current value of Data Breakpoint Register (DBR).
-
-  The Data Breakpoint Registers are used in pairs.  The even numbered registers
-  contain breakpoint addresses, and odd numbered registers contain breakpoint
-  mask conditions.  At least four data registers pairs are implemented on all processor
-  models.  Implemented registers are contiguous starting with register 0.
-  No parameter checking is performed on Index.  If the Index value is beyond
-  the implemented DBR register range, a Reserved Register/Field fault may occur.
-  The caller must either guarantee that Index is valid, or the caller must set up
-  fault handlers to catch the faults.
-  This function is only available on Itanium processors.
-
-  @param Index    The 8-bit Data Breakpoint Register index to read.
-
-  @return The current value of Data Breakpoint Register specified by Index.
-
-**/
-UINT64
-EFIAPI
-AsmReadDbr (
-  IN  UINT8   Index
-  );
-
-
-/**
-  Reads the current value of Performance Monitor Configuration Register (PMC).
-
-  All processor implementations provide at least four performance counters
-  (PMC/PMD [4]...PMC/PMD [7] pairs), and four performance monitor counter overflow
-  status registers (PMC [0]... PMC [3]).  Processor implementations may provide
-  additional implementation-dependent PMC and PMD to increase the number of
-  'generic' performance counters (PMC/PMD pairs).  The remainder of PMC and PMD
-  register set is implementation dependent.  No parameter checking is performed
-  on Index.  If the Index value is beyond the implemented PMC register range,
-  zero value will be returned.
-  This function is only available on Itanium processors.
-
-  @param Index    The 8-bit Performance Monitor Configuration Register index to read.
-
-  @return   The current value of Performance Monitor Configuration Register
-            specified by Index.
-
-**/
-UINT64
-EFIAPI
-AsmReadPmc (
-  IN  UINT8   Index
-  );
-
-
-/**
-  Reads the current value of Performance Monitor Data Register (PMD).
-
-  All processor implementations provide at least 4 performance counters
-  (PMC/PMD [4]...PMC/PMD [7] pairs), and 4 performance monitor counter
-  overflow status registers (PMC [0]... PMC [3]).  Processor implementations may
-  provide additional implementation-dependent PMC and PMD to increase the number
-  of 'generic' performance counters (PMC/PMD pairs).  The remainder of PMC and PMD
-  register set is implementation dependent.  No parameter checking is performed
-  on Index.  If the Index value is beyond the implemented PMD register range,
-  zero value will be returned.
-  This function is only available on Itanium processors.
-
-  @param Index    The 8-bit Performance Monitor Data Register index to read.
-
-  @return The current value of Performance Monitor Data Register specified by Index.
-
-**/
-UINT64
-EFIAPI
-AsmReadPmd (
-  IN  UINT8   Index
-  );
-
-
-/**
-  Writes the current value of 64-bit Instruction Breakpoint Register (IBR).
-
-  Writes current value of Instruction Breakpoint Register specified by Index.
-  The Instruction Breakpoint Registers are used in pairs.  The even numbered
-  registers contain breakpoint addresses, and odd numbered registers contain
-  breakpoint mask conditions.  At least four instruction registers pairs are implemented
-  on all processor models.  Implemented registers are contiguous starting with
-  register 0.  No parameter checking is performed on Index.  If the Index value
-  is beyond the implemented IBR register range, a Reserved Register/Field fault may
-  occur.  The caller must either guarantee that Index is valid, or the caller must
-  set up fault handlers to catch the faults.
-  This function is only available on Itanium processors.
-
-  @param Index    The 8-bit Instruction Breakpoint Register index to write.
-  @param Value    The 64-bit value to write to IBR.
-
-  @return The 64-bit value written to the IBR.
-
-**/
-UINT64
-EFIAPI
-AsmWriteIbr (
-  IN UINT8   Index,
-  IN UINT64  Value
-  );
-
-
-/**
-  Writes the current value of 64-bit Data Breakpoint Register (DBR).
-
-  Writes current value of Data Breakpoint Register specified by Index.
-  The Data Breakpoint Registers are used in pairs.  The even numbered registers
-  contain breakpoint addresses, and odd numbered registers contain breakpoint
-  mask conditions.  At least four data registers pairs are implemented on all processor
-  models.  Implemented registers are contiguous starting with register 0.  No parameter
-  checking is performed on Index.  If the Index value is beyond the implemented
-  DBR register range, a Reserved Register/Field fault may occur.  The caller must
-  either guarantee that Index is valid, or the caller must set up fault handlers to
-  catch the faults.
-  This function is only available on Itanium processors.
-
-  @param Index    The 8-bit Data Breakpoint Register index to write.
-  @param Value    The 64-bit value to write to DBR.
-
-  @return The 64-bit value written to the DBR.
-
-**/
-UINT64
-EFIAPI
-AsmWriteDbr (
-  IN UINT8   Index,
-  IN UINT64  Value
-  );
-
-
-/**
-  Writes the current value of 64-bit Performance Monitor Configuration Register (PMC).
-
-  Writes current value of Performance Monitor Configuration Register specified by Index.
-  All processor implementations provide at least four performance counters
-  (PMC/PMD [4]...PMC/PMD [7] pairs), and four performance monitor counter overflow status
-  registers (PMC [0]... PMC [3]).  Processor implementations may provide additional
-  implementation-dependent PMC and PMD to increase the number of 'generic' performance
-  counters (PMC/PMD pairs).  The remainder of PMC and PMD register set is implementation
-  dependent.  No parameter checking is performed on Index.  If the Index value is
-  beyond the implemented PMC register range, the write is ignored.
-  This function is only available on Itanium processors.
-
-  @param Index    The 8-bit Performance Monitor Configuration Register index to write.
-  @param Value    The 64-bit value to write to PMC.
-
-  @return The 64-bit value written to the PMC.
-
-**/
-UINT64
-EFIAPI
-AsmWritePmc (
-  IN UINT8   Index,
-  IN UINT64  Value
-  );
-
-
-/**
-  Writes the current value of 64-bit Performance Monitor Data Register (PMD).
-
-  Writes current value of Performance Monitor Data Register specified by Index.
-  All processor implementations provide at least four performance counters
-  (PMC/PMD [4]...PMC/PMD [7] pairs), and four performance monitor counter overflow
-  status registers (PMC [0]... PMC [3]).  Processor implementations may provide
-  additional implementation-dependent PMC and PMD to increase the number of 'generic'
-  performance counters (PMC/PMD pairs).  The remainder of PMC and PMD register set
-  is implementation dependent.  No parameter checking is performed on Index.  If the
-  Index value is beyond the implemented PMD register range, the write is ignored.
-  This function is only available on Itanium processors.
-
-  @param Index    The 8-bit Performance Monitor Data Register index to write.
-  @param Value    The 64-bit value to write to PMD.
-
-  @return The 64-bit value written to the PMD.
-
-**/
-UINT64
-EFIAPI
-AsmWritePmd (
-  IN UINT8   Index,
-  IN UINT64  Value
-  );
-
-
-/**
-  Reads the current value of 64-bit Global Pointer (GP).
-
-  Reads and returns the current value of GP.
-  This function is only available on Itanium processors.
-
-  @return The current value of GP.
-
-**/
-UINT64
-EFIAPI
-AsmReadGp (
-  VOID
-  );
-
-
-/**
-  Write the current value of 64-bit Global Pointer (GP).
-
-  Writes the current value of GP. The 64-bit value written to the GP is returned.
-  No parameter checking is performed on Value.
-  This function is only available on Itanium processors.
-
-  @param Value  The 64-bit value to write to GP.
-
-  @return The 64-bit value written to the GP.
-
-**/
-UINT64
-EFIAPI
-AsmWriteGp (
-  IN UINT64  Value
-  );
-
-
-/**
-  Reads the current value of 64-bit Stack Pointer (SP).
-
-  Reads and returns the current value of SP.
-  This function is only available on Itanium processors.
-
-  @return The current value of SP.
-
-**/
-UINT64
-EFIAPI
-AsmReadSp (
-  VOID
-  );
-
-
-///
-/// Valid Index value for AsmReadControlRegister().
-///
-#define IPF_CONTROL_REGISTER_DCR   0
-#define IPF_CONTROL_REGISTER_ITM   1
-#define IPF_CONTROL_REGISTER_IVA   2
-#define IPF_CONTROL_REGISTER_PTA   8
-#define IPF_CONTROL_REGISTER_IPSR  16
-#define IPF_CONTROL_REGISTER_ISR   17
-#define IPF_CONTROL_REGISTER_IIP   19
-#define IPF_CONTROL_REGISTER_IFA   20
-#define IPF_CONTROL_REGISTER_ITIR  21
-#define IPF_CONTROL_REGISTER_IIPA  22
-#define IPF_CONTROL_REGISTER_IFS   23
-#define IPF_CONTROL_REGISTER_IIM   24
-#define IPF_CONTROL_REGISTER_IHA   25
-#define IPF_CONTROL_REGISTER_LID   64
-#define IPF_CONTROL_REGISTER_IVR   65
-#define IPF_CONTROL_REGISTER_TPR   66
-#define IPF_CONTROL_REGISTER_EOI   67
-#define IPF_CONTROL_REGISTER_IRR0  68
-#define IPF_CONTROL_REGISTER_IRR1  69
-#define IPF_CONTROL_REGISTER_IRR2  70
-#define IPF_CONTROL_REGISTER_IRR3  71
-#define IPF_CONTROL_REGISTER_ITV   72
-#define IPF_CONTROL_REGISTER_PMV   73
-#define IPF_CONTROL_REGISTER_CMCV  74
-#define IPF_CONTROL_REGISTER_LRR0  80
-#define IPF_CONTROL_REGISTER_LRR1  81
-
-/**
-  Reads a 64-bit control register.
-
-  Reads and returns the control register specified by Index. The valid Index valued 
-  are defined above in "Related Definitions".
-  If Index is invalid then 0xFFFFFFFFFFFFFFFF is returned.  This function is only 
-  available on Itanium processors.
-
-  @param  Index                     The index of the control register to read.
-
-  @return The control register specified by Index.
-
-**/
-UINT64
-EFIAPI
-AsmReadControlRegister (
-  IN UINT64  Index
-  );
-
-
-///
-/// Valid Index value for AsmReadApplicationRegister().
-///
-#define IPF_APPLICATION_REGISTER_K0        0
-#define IPF_APPLICATION_REGISTER_K1        1
-#define IPF_APPLICATION_REGISTER_K2        2
-#define IPF_APPLICATION_REGISTER_K3        3
-#define IPF_APPLICATION_REGISTER_K4        4
-#define IPF_APPLICATION_REGISTER_K5        5
-#define IPF_APPLICATION_REGISTER_K6        6
-#define IPF_APPLICATION_REGISTER_K7        7
-#define IPF_APPLICATION_REGISTER_RSC       16
-#define IPF_APPLICATION_REGISTER_BSP       17
-#define IPF_APPLICATION_REGISTER_BSPSTORE  18
-#define IPF_APPLICATION_REGISTER_RNAT      19
-#define IPF_APPLICATION_REGISTER_FCR       21
-#define IPF_APPLICATION_REGISTER_EFLAG     24
-#define IPF_APPLICATION_REGISTER_CSD       25
-#define IPF_APPLICATION_REGISTER_SSD       26
-#define IPF_APPLICATION_REGISTER_CFLG      27
-#define IPF_APPLICATION_REGISTER_FSR       28
-#define IPF_APPLICATION_REGISTER_FIR       29
-#define IPF_APPLICATION_REGISTER_FDR       30
-#define IPF_APPLICATION_REGISTER_CCV       32
-#define IPF_APPLICATION_REGISTER_UNAT      36
-#define IPF_APPLICATION_REGISTER_FPSR      40
-#define IPF_APPLICATION_REGISTER_ITC       44
-#define IPF_APPLICATION_REGISTER_PFS       64
-#define IPF_APPLICATION_REGISTER_LC        65
-#define IPF_APPLICATION_REGISTER_EC        66
-
-/**
-  Reads a 64-bit application register.
-
-  Reads and returns the application register specified by Index. The valid Index 
-  valued are defined above in "Related Definitions".
-  If Index is invalid then 0xFFFFFFFFFFFFFFFF is returned.  This function is only 
-  available on Itanium processors.
-
-  @param  Index                     The index of the application register to read.
-
-  @return The application register specified by Index.
-
-**/
-UINT64
-EFIAPI
-AsmReadApplicationRegister (
-  IN UINT64  Index
-  );
-
-
-/**
-  Reads the current value of a Machine Specific Register (MSR).
-
-  Reads and returns the current value of the Machine Specific Register specified by Index.  No
-  parameter checking is performed on Index, and if the Index value is beyond the implemented MSR
-  register range, a Reserved Register/Field fault may occur.  The caller must either guarantee that
-  Index is valid, or the caller must set up fault handlers to catch the faults.  This function is
-  only available on Itanium processors.
-
-  @param  Index                     The 8-bit Machine Specific Register index to read.
-
-  @return The current value of the Machine Specific Register specified by Index.  
-
-**/
-UINT64
-EFIAPI
-AsmReadMsr (
-  IN UINT8   Index  
-  );
-
-
-/**
-  Writes the current value of a Machine Specific Register (MSR).
-
-  Writes Value to the Machine Specific Register specified by Index.  Value is returned.  No
-  parameter checking is performed on Index, and if the Index value is beyond the implemented MSR
-  register range, a Reserved Register/Field fault may occur.  The caller must either guarantee that
-  Index is valid, or the caller must set up fault handlers to catch the faults.  This function is
-  only available on Itanium processors.
-
-  @param  Index                     The 8-bit Machine Specific Register index to write.
-  @param  Value                     The 64-bit value to write to the Machine Specific Register.
-
-  @return The 64-bit value to write to the Machine Specific Register.  
-
-**/
-UINT64
-EFIAPI
-AsmWriteMsr (
-  IN UINT8   Index, 
-  IN UINT64  Value  
-  );
-
-
-/**
-  Determines if the CPU is currently executing in virtual, physical, or mixed mode.
-
-  Determines the current execution mode of the CPU.
-  If the CPU is in virtual mode(PSR.RT=1, PSR.DT=1, PSR.IT=1), then 1 is returned.
-  If the CPU is in physical mode(PSR.RT=0, PSR.DT=0, PSR.IT=0), then 0 is returned.
-  If the CPU is not in physical mode or virtual mode, then it is in mixed mode,
-  and -1 is returned.
-  This function is only available on Itanium processors.
-
-  @retval  1  The CPU is in virtual mode.
-  @retval  0  The CPU is in physical mode.
-  @retval -1  The CPU is in mixed mode.
-
-**/
-INT64
-EFIAPI
-AsmCpuVirtual (
-  VOID
-  );
-
-
-/**
-  Makes a PAL procedure call.
-
-  This is a wrapper function to make a PAL procedure call.  Based on the Index
-  value this API will make static or stacked PAL call.  The following table
-  describes the usage of PAL Procedure Index Assignment. Architected procedures
-  may be designated as required or optional.  If a PAL procedure is specified
-  as optional, a unique return code of 0xFFFFFFFFFFFFFFFF is returned in the
-  Status field of the PAL_CALL_RETURN structure.
-  This indicates that the procedure is not present in this PAL implementation.
-  It is the caller's responsibility to check for this return code after calling
-  any optional PAL procedure.
-  No parameter checking is performed on the 5 input parameters, but there are
-  some common rules that the caller should follow when making a PAL call.  Any
-  address passed to PAL as buffers for return parameters must be 8-byte aligned.
-  Unaligned addresses may cause undefined results.  For those parameters defined
-  as reserved or some fields defined as reserved must be zero filled or the invalid
-  argument return value may be returned or undefined result may occur during the
-  execution of the procedure.  If the PalEntryPoint  does not point to a valid
-  PAL entry point then the system behavior is undefined.  This function is only
-  available on Itanium processors.
-
-  @param PalEntryPoint  The PAL procedure calls entry point.
-  @param Index          The PAL procedure Index number.
-  @param Arg2           The 2nd parameter for PAL procedure calls.
-  @param Arg3           The 3rd parameter for PAL procedure calls.
-  @param Arg4           The 4th parameter for PAL procedure calls.
-
-  @return structure returned from the PAL Call procedure, including the status and return value.
-
-**/
-PAL_CALL_RETURN
-EFIAPI
-AsmPalCall (
-  IN UINT64  PalEntryPoint,
-  IN UINT64  Index,
-  IN UINT64  Arg2,
-  IN UINT64  Arg3,
-  IN UINT64  Arg4
-  );
-#endif
-
 #if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)
 ///
 /// IA32 and x64 Specific Functions.
@@ -6556,9 +5329,19 @@ typedef union {
     UINT32  OSXMMEXCPT:1;   ///< Operating System Support for
                             ///< Unmasked SIMD Floating Point
                             ///< Exceptions.
-    UINT32  Reserved_0:2;   ///< Reserved.
-    UINT32  VMXE:1;         ///< VMX Enable
-    UINT32  Reserved_1:18;  ///< Reserved.
+    UINT32  UMIP:1;         ///< User-Mode Instruction Prevention.
+    UINT32  LA57:1;         ///< Linear Address 57bit.
+    UINT32  VMXE:1;         ///< VMX Enable.
+    UINT32  SMXE:1;         ///< SMX Enable.
+    UINT32  Reserved_3:1;   ///< Reserved.
+    UINT32  FSGSBASE:1;     ///< FSGSBASE Enable.
+    UINT32  PCIDE:1;        ///< PCID Enable.
+    UINT32  OSXSAVE:1;      ///< XSAVE and Processor Extended States Enable.
+    UINT32  Reserved_4:1;   ///< Reserved.
+    UINT32  SMEP:1;         ///< SMEP Enable.
+    UINT32  SMAP:1;         ///< SMAP Enable.
+    UINT32  PKE:1;          ///< Protection-Key Enable.
+    UINT32  Reserved_5:9;   ///< Reserved.
   } Bits;
   UINTN     UintN;
 } IA32_CR4;
@@ -6601,6 +5384,8 @@ typedef struct {
 #define IA32_IDT_GATE_TYPE_INTERRUPT_32  0x8E
 #define IA32_IDT_GATE_TYPE_TRAP_32       0x8F
 
+#define IA32_GDT_TYPE_TSS               0x9
+#define IA32_GDT_ALIGNMENT              8
 
 #if defined (MDE_CPU_IA32)
 ///
@@ -6617,7 +5402,71 @@ typedef union {
   UINT64  Uint64;
 } IA32_IDT_GATE_DESCRIPTOR;
 
-#endif
+#pragma pack (1)
+//
+// IA32 Task-State Segment Definition
+//
+typedef struct {
+  UINT16    PreviousTaskLink;
+  UINT16    Reserved_2;
+  UINT32    ESP0;
+  UINT16    SS0;
+  UINT16    Reserved_10;
+  UINT32    ESP1;
+  UINT16    SS1;
+  UINT16    Reserved_18;
+  UINT32    ESP2;
+  UINT16    SS2;
+  UINT16    Reserved_26;
+  UINT32    CR3;
+  UINT32    EIP;
+  UINT32    EFLAGS;
+  UINT32    EAX;
+  UINT32    ECX;
+  UINT32    EDX;
+  UINT32    EBX;
+  UINT32    ESP;
+  UINT32    EBP;
+  UINT32    ESI;
+  UINT32    EDI;
+  UINT16    ES;
+  UINT16    Reserved_74;
+  UINT16    CS;
+  UINT16    Reserved_78;
+  UINT16    SS;
+  UINT16    Reserved_82;
+  UINT16    DS;
+  UINT16    Reserved_86;
+  UINT16    FS;
+  UINT16    Reserved_90;
+  UINT16    GS;
+  UINT16    Reserved_94;
+  UINT16    LDTSegmentSelector;
+  UINT16    Reserved_98;
+  UINT16    T;
+  UINT16    IOMapBaseAddress;
+} IA32_TASK_STATE_SEGMENT;
+
+typedef union {
+  struct {
+    UINT32  LimitLow:16;    ///< Segment Limit 15..00
+    UINT32  BaseLow:16;     ///< Base Address  15..00
+    UINT32  BaseMid:8;      ///< Base Address  23..16
+    UINT32  Type:4;         ///< Type (1 0 B 1)
+    UINT32  Reserved_43:1;  ///< 0
+    UINT32  DPL:2;          ///< Descriptor Privilege Level
+    UINT32  P:1;            ///< Segment Present
+    UINT32  LimitHigh:4;    ///< Segment Limit 19..16
+    UINT32  AVL:1;          ///< Available for use by system software
+    UINT32  Reserved_52:2;  ///< 0 0
+    UINT32  G:1;            ///< Granularity
+    UINT32  BaseHigh:8;     ///< Base Address 31..24
+  } Bits;
+  UINT64  Uint64;
+} IA32_TSS_DESCRIPTOR;
+#pragma pack ()
+
+#endif // defined (MDE_CPU_IA32)
 
 #if defined (MDE_CPU_X64)
 ///
@@ -6636,10 +5485,50 @@ typedef union {
   struct {
     UINT64  Uint64;
     UINT64  Uint64_1;
-  } Uint128;   
+  } Uint128;
 } IA32_IDT_GATE_DESCRIPTOR;
 
-#endif
+#pragma pack (1)
+//
+// IA32 Task-State Segment Definition
+//
+typedef struct {
+  UINT32    Reserved_0;
+  UINT64    RSP0;
+  UINT64    RSP1;
+  UINT64    RSP2;
+  UINT64    Reserved_28;
+  UINT64    IST[7];
+  UINT64    Reserved_92;
+  UINT16    Reserved_100;
+  UINT16    IOMapBaseAddress;
+} IA32_TASK_STATE_SEGMENT;
+
+typedef union {
+  struct {
+    UINT32  LimitLow:16;    ///< Segment Limit 15..00
+    UINT32  BaseLow:16;     ///< Base Address  15..00
+    UINT32  BaseMidl:8;     ///< Base Address  23..16
+    UINT32  Type:4;         ///< Type (1 0 B 1)
+    UINT32  Reserved_43:1;  ///< 0
+    UINT32  DPL:2;          ///< Descriptor Privilege Level
+    UINT32  P:1;            ///< Segment Present
+    UINT32  LimitHigh:4;    ///< Segment Limit 19..16
+    UINT32  AVL:1;          ///< Available for use by system software
+    UINT32  Reserved_52:2;  ///< 0 0
+    UINT32  G:1;            ///< Granularity
+    UINT32  BaseMidh:8;     ///< Base Address  31..24
+    UINT32  BaseHigh:32;    ///< Base Address  63..32
+    UINT32  Reserved_96:32; ///< Reserved
+  } Bits;
+  struct {
+    UINT64  Uint64;
+    UINT64  Uint64_1;
+  } Uint128;
+} IA32_TSS_DESCRIPTOR;
+#pragma pack ()
+
+#endif // defined (MDE_CPU_X64)
 
 ///
 /// Byte packed structure for an FP/SSE/SSE2 context.
@@ -6728,6 +5617,20 @@ typedef struct {
 #define THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15   0x00000002
 #define THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL 0x00000004
 
+///
+/// Type definition for representing labels in NASM source code that allow for
+/// the patching of immediate operands of IA32 and X64 instructions.
+///
+/// While the type is technically defined as a function type (note: not a
+/// pointer-to-function type), such labels in NASM source code never stand for
+/// actual functions, and identifiers declared with this function type should
+/// never be called. This is also why the EFIAPI calling convention specifier
+/// is missing from the typedef, and why the typedef does not follow the usual
+/// edk2 coding style for function (or pointer-to-function) typedefs. The VOID
+/// return type and the VOID argument list are merely artifacts.
+///
+typedef VOID (X86_ASSEMBLY_PATCH_LABEL) (VOID);
+
 /**
   Retrieves CPUID information.
 
@@ -7004,8 +5907,8 @@ AsmMsrBitFieldRead32 (
   Writes Value to a bit field in the lower 32-bits of a 64-bit MSR. The bit
   field is specified by the StartBit and the EndBit. All other bits in the
   destination MSR are preserved. The lower 32-bits of the MSR written is
-  returned. The caller must either guarantee that Index and the data written 
-  is valid, or the caller must set up exception handlers to catch the exceptions. 
+  returned. The caller must either guarantee that Index and the data written
+  is valid, or the caller must set up exception handlers to catch the exceptions.
   This function is only available on IA-32 and x64.
 
   If StartBit is greater than 31, then ASSERT().
@@ -7248,7 +6151,7 @@ AsmMsrAnd64 (
 
 
 /**
-  Reads a 64-bit MSR, performs a bitwise AND followed by a bitwise 
+  Reads a 64-bit MSR, performs a bitwise AND followed by a bitwise
   OR, and writes the result back to the 64-bit MSR.
 
   Reads the 64-bit MSR specified by Index, performs a bitwise AND between read
@@ -7313,8 +6216,8 @@ AsmMsrBitFieldRead64 (
 
   Writes Value to a bit field in a 64-bit MSR. The bit field is specified by
   the StartBit and the EndBit. All other bits in the destination MSR are
-  preserved. The MSR written is returned. The caller must either guarantee 
-  that Index and the data written is valid, or the caller must set up exception 
+  preserved. The MSR written is returned. The caller must either guarantee
+  that Index and the data written is valid, or the caller must set up exception
   handlers to catch the exceptions. This function is only available on IA-32 and x64.
 
   If StartBit is greater than 63, then ASSERT().
@@ -8726,7 +7629,7 @@ AsmDisablePaging64 (
   in ExtraStackSize. If parameters are passed to the 16-bit real mode code,
   then the actual minimum stack size is ExtraStackSize plus the maximum number
   of bytes that need to be passed to the 16-bit real mode code.
-  
+
   If RealModeBufferSize is NULL, then ASSERT().
   If ExtraStackSize is NULL, then ASSERT().
 
@@ -8750,7 +7653,7 @@ AsmGetThunk16Properties (
   Prepares all structures a code required to use AsmThunk16().
 
   Prepares all structures and code required to use AsmThunk16().
-  
+
   This interface is limited to be used in either physical mode or virtual modes with paging enabled where the
   virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.
 
@@ -8774,43 +7677,43 @@ AsmPrepareThunk16 (
   AsmPrepareThunk16() must be called with ThunkContext before this function is used.
   This function must be called with interrupts disabled.
 
-  The register state from the RealModeState field of ThunkContext is restored just prior 
-  to calling the 16-bit real mode entry point.  This includes the EFLAGS field of RealModeState, 
+  The register state from the RealModeState field of ThunkContext is restored just prior
+  to calling the 16-bit real mode entry point.  This includes the EFLAGS field of RealModeState,
   which is used to set the interrupt state when a 16-bit real mode entry point is called.
   Control is transferred to the 16-bit real mode entry point specified by the CS and Eip fields of RealModeState.
-  The stack is initialized to the SS and ESP fields of RealModeState.  Any parameters passed to 
-  the 16-bit real mode code must be populated by the caller at SS:ESP prior to calling this function.  
+  The stack is initialized to the SS and ESP fields of RealModeState.  Any parameters passed to
+  the 16-bit real mode code must be populated by the caller at SS:ESP prior to calling this function.
   The 16-bit real mode entry point is invoked with a 16-bit CALL FAR instruction,
-  so when accessing stack contents, the 16-bit real mode code must account for the 16-bit segment 
-  and 16-bit offset of the return address that were pushed onto the stack. The 16-bit real mode entry 
-  point must exit with a RETF instruction. The register state is captured into RealModeState immediately 
+  so when accessing stack contents, the 16-bit real mode code must account for the 16-bit segment
+  and 16-bit offset of the return address that were pushed onto the stack. The 16-bit real mode entry
+  point must exit with a RETF instruction. The register state is captured into RealModeState immediately
   after the RETF instruction is executed.
-  
-  If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts, 
-  or any of the 16-bit real mode code makes a SW interrupt, then the caller is responsible for making sure 
-  the IDT at address 0 is initialized to handle any HW or SW interrupts that may occur while in 16-bit real mode. 
-  
-  If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts, 
-  then the caller is responsible for making sure the 8259 PIC is in a state compatible with 16-bit real mode.  
+
+  If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts,
+  or any of the 16-bit real mode code makes a SW interrupt, then the caller is responsible for making sure
+  the IDT at address 0 is initialized to handle any HW or SW interrupts that may occur while in 16-bit real mode.
+
+  If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts,
+  then the caller is responsible for making sure the 8259 PIC is in a state compatible with 16-bit real mode.
   This includes the base vectors, the interrupt masks, and the edge/level trigger mode.
-  
-  If THUNK_ATTRIBUTE_BIG_REAL_MODE is set in the ThunkAttributes field of ThunkContext, then the user code 
+
+  If THUNK_ATTRIBUTE_BIG_REAL_MODE is set in the ThunkAttributes field of ThunkContext, then the user code
   is invoked in big real mode.  Otherwise, the user code is invoked in 16-bit real mode with 64KB segment limits.
-  
-  If neither THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 nor THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in 
-  ThunkAttributes, then it is assumed that the user code did not enable the A20 mask, and no attempt is made to 
+
+  If neither THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 nor THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in
+  ThunkAttributes, then it is assumed that the user code did not enable the A20 mask, and no attempt is made to
   disable the A20 mask.
-  
-  If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is set and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is clear in 
-  ThunkAttributes, then attempt to use the INT 15 service to disable the A20 mask.  If this INT 15 call fails, 
+
+  If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is set and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is clear in
+  ThunkAttributes, then attempt to use the INT 15 service to disable the A20 mask.  If this INT 15 call fails,
   then attempt to disable the A20 mask by directly accessing the 8042 keyboard controller I/O ports.
-  
-  If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is clear and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is set in 
+
+  If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is clear and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is set in
   ThunkAttributes, then attempt to disable the A20 mask by directly accessing the 8042 keyboard controller I/O ports.
-    
+
   If ThunkContext is NULL, then ASSERT().
   If AsmPrepareThunk16() was not previously called with ThunkContext, then ASSERT().
-  If both THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in 
+  If both THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in
   ThunkAttributes, then ASSERT().
 
   This interface is limited to be used in either physical mode or virtual modes with paging enabled where the
@@ -8904,7 +7807,71 @@ AsmRdRand64  (
   OUT     UINT64                    *Rand
   );
 
-#endif
-#endif
+/**
+  Load given selector into TR register.
+
+  @param[in] Selector     Task segment selector
+**/
+VOID
+EFIAPI
+AsmWriteTr (
+  IN UINT16 Selector
+  );
+
+/**
+  Performs a serializing operation on all load-from-memory instructions that
+  were issued prior the AsmLfence function.
+
+  Executes a LFENCE instruction. This function is only available on IA-32 and x64.
 
+**/
+VOID
+EFIAPI
+AsmLfence (
+  VOID
+  );
+
+/**
+  Patch the immediate operand of an IA32 or X64 instruction such that the byte,
+  word, dword or qword operand is encoded at the end of the instruction's
+  binary representation.
+
+  This function should be used to update object code that was compiled with
+  NASM from assembly source code. Example:
+
+  NASM source code:
+
+        mov     eax, strict dword 0 ; the imm32 zero operand will be patched
+    ASM_PFX(gPatchCr3):
+        mov     cr3, eax
+
+  C source code:
+
+    X86_ASSEMBLY_PATCH_LABEL gPatchCr3;
+    PatchInstructionX86 (gPatchCr3, AsmReadCr3 (), 4);
+
+  @param[out] InstructionEnd  Pointer right past the instruction to patch. The
+                              immediate operand to patch is expected to
+                              comprise the trailing bytes of the instruction.
+                              If InstructionEnd is closer to address 0 than
+                              ValueSize permits, then ASSERT().
+
+  @param[in] PatchValue       The constant to write to the immediate operand.
+                              The caller is responsible for ensuring that
+                              PatchValue can be represented in the byte, word,
+                              dword or qword operand (as indicated through
+                              ValueSize); otherwise ASSERT().
+
+  @param[in] ValueSize        The size of the operand in bytes; must be 1, 2,
+                              4, or 8. ASSERT() otherwise.
+**/
+VOID
+EFIAPI
+PatchInstructionX86 (
+  OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,
+  IN  UINT64                   PatchValue,
+  IN  UINTN                    ValueSize
+  );
 
+#endif // defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)
+#endif // !defined (__BASE_LIB__)
diff --git a/MdePkg/Include/Library/BaseMemoryLib.h b/MdePkg/Include/Library/BaseMemoryLib.h
index 31a403c56ab9..3c764aebc517 100644
--- a/MdePkg/Include/Library/BaseMemoryLib.h
+++ b/MdePkg/Include/Library/BaseMemoryLib.h
@@ -1,18 +1,12 @@
 /** @file
   Provides copy memory, fill memory, zero memory, and GUID functions.
-   
-  The Base Memory Library provides optimized implementations for common memory-based operations. 
-  These functions should be used in place of coding your own loops to do equivalent common functions. 
-  This allows optimized library implementations to help increase performance. 
 
-Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.
+  The Base Memory Library provides optimized implementations for common memory-based operations.
+  These functions should be used in place of coding your own loops to do equivalent common functions.
+  This allows optimized library implementations to help increase performance.
 
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -25,7 +19,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   This function copies Length bytes from SourceBuffer to DestinationBuffer, and returns
   DestinationBuffer.  The implementation must be reentrant, and it must handle the case
   where SourceBuffer overlaps DestinationBuffer.
-  
+
   If Length is greater than (MAX_ADDRESS - DestinationBuffer + 1), then ASSERT().
   If Length is greater than (MAX_ADDRESS - SourceBuffer + 1), then ASSERT().
 
@@ -48,7 +42,7 @@ CopyMem (
   Fills a target buffer with a byte value, and returns the target buffer.
 
   This function fills Length bytes of Buffer with Value, and returns Buffer.
-  
+
   If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
 
   @param  Buffer    The memory to set.
@@ -178,7 +172,7 @@ SetMemN (
   Fills a target buffer with zeros, and returns the target buffer.
 
   This function fills Length bytes of Buffer with zeros, and returns Buffer.
-  
+
   If Length > 0 and Buffer is NULL, then ASSERT().
   If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
 
@@ -202,7 +196,7 @@ ZeroMem (
   If all Length bytes of the two buffers are identical, then 0 is returned.  Otherwise, the
   value returned is the first mismatched byte in SourceBuffer subtracted from the first
   mismatched byte in DestinationBuffer.
-  
+
   If Length > 0 and DestinationBuffer is NULL, then ASSERT().
   If Length > 0 and SourceBuffer is NULL, then ASSERT().
   If Length is greater than (MAX_ADDRESS - DestinationBuffer + 1), then ASSERT().
@@ -215,7 +209,7 @@ ZeroMem (
   @return 0                 All Length bytes of the two buffers are identical.
   @retval Non-zero          The first mismatched byte in SourceBuffer subtracted from the first
                             mismatched byte in DestinationBuffer.
-                            
+
 **/
 INTN
 EFIAPI
@@ -233,7 +227,7 @@ CompareMem (
   address to the highest address for an 8-bit value that matches Value.  If a match is found,
   then a pointer to the matching byte in the target buffer is returned.  If no match is found,
   then NULL is returned.  If Length is 0, then NULL is returned.
-  
+
   If Length > 0 and Buffer is NULL, then ASSERT().
   If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
 
@@ -260,7 +254,7 @@ ScanMem8 (
   address to the highest address for a 16-bit value that matches Value.  If a match is found,
   then a pointer to the matching byte in the target buffer is returned.  If no match is found,
   then NULL is returned.  If Length is 0, then NULL is returned.
-  
+
   If Length > 0 and Buffer is NULL, then ASSERT().
   If Buffer is not aligned on a 16-bit boundary, then ASSERT().
   If Length is not aligned on a 16-bit boundary, then ASSERT().
@@ -289,7 +283,7 @@ ScanMem16 (
   address to the highest address for a 32-bit value that matches Value.  If a match is found,
   then a pointer to the matching byte in the target buffer is returned.  If no match is found,
   then NULL is returned.  If Length is 0, then NULL is returned.
-  
+
   If Length > 0 and Buffer is NULL, then ASSERT().
   If Buffer is not aligned on a 32-bit boundary, then ASSERT().
   If Length is not aligned on a 32-bit boundary, then ASSERT().
@@ -318,7 +312,7 @@ ScanMem32 (
   address to the highest address for a 64-bit value that matches Value.  If a match is found,
   then a pointer to the matching byte in the target buffer is returned.  If no match is found,
   then NULL is returned.  If Length is 0, then NULL is returned.
-  
+
   If Length > 0 and Buffer is NULL, then ASSERT().
   If Buffer is not aligned on a 64-bit boundary, then ASSERT().
   If Length is not aligned on a 64-bit boundary, then ASSERT().
@@ -340,14 +334,14 @@ ScanMem64 (
   );
 
 /**
-  Scans a target buffer for a UINTN sized value, and returns a pointer to the matching 
+  Scans a target buffer for a UINTN sized value, and returns a pointer to the matching
   UINTN sized value in the target buffer.
 
   This function searches target the buffer specified by Buffer and Length from the lowest
   address to the highest address for a UINTN sized value that matches Value.  If a match is found,
   then a pointer to the matching byte in the target buffer is returned.  If no match is found,
   then NULL is returned.  If Length is 0, then NULL is returned.
-  
+
   If Length > 0 and Buffer is NULL, then ASSERT().
   If Buffer is not aligned on a UINTN boundary, then ASSERT().
   If Length is not aligned on a UINTN boundary, then ASSERT().
@@ -367,13 +361,13 @@ ScanMemN (
   IN UINTN       Length,
   IN UINTN       Value
   );
-  
+
 /**
   Copies a source GUID to a destination GUID.
 
   This function copies the contents of the 128-bit GUID specified by SourceGuid to
   DestinationGuid, and returns DestinationGuid.
-  
+
   If DestinationGuid is NULL, then ASSERT().
   If SourceGuid is NULL, then ASSERT().
 
@@ -395,7 +389,7 @@ CopyGuid (
 
   This function compares Guid1 to Guid2.  If the GUIDs are identical then TRUE is returned.
   If there are any bit differences in the two GUIDs, then FALSE is returned.
-  
+
   If Guid1 is NULL, then ASSERT().
   If Guid2 is NULL, then ASSERT().
 
@@ -422,7 +416,7 @@ CompareGuid (
   GUID value that matches Guid.  If a match is found, then a pointer to the matching
   GUID in the target buffer is returned.  If no match is found, then NULL is returned.
   If Length is 0, then NULL is returned.
-  
+
   If Length > 0 and Buffer is NULL, then ASSERT().
   If Buffer is not aligned on a 32-bit boundary, then ASSERT().
   If Length is not aligned on a 128-bit boundary, then ASSERT().
diff --git a/MdePkg/Include/Library/CacheMaintenanceLib.h b/MdePkg/Include/Library/CacheMaintenanceLib.h
index b2c6258a32a4..18bd6050f41d 100644
--- a/MdePkg/Include/Library/CacheMaintenanceLib.h
+++ b/MdePkg/Include/Library/CacheMaintenanceLib.h
@@ -1,17 +1,11 @@
 /** @file
   Provides services to maintain instruction and data caches.
-  
+
   The Cache Maintenance Library provides abstractions for basic processor cache operations.
   It removes the need to use assembly in C code.
-    
-Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/Library/CpuLib.h b/MdePkg/Include/Library/CpuLib.h
index 662e4d9ce69c..76e4fd1708d3 100644
--- a/MdePkg/Include/Library/CpuLib.h
+++ b/MdePkg/Include/Library/CpuLib.h
@@ -1,20 +1,14 @@
 /** @file
   Provides CPU architecture specific functions that can not be defined
   in the Base Library due to dependencies on the PAL Library
-  
+
   The CPU Library provides services to flush CPU TLBs and place the CPU in a sleep state.
   The implementation of these services on Itanium processors requires the use of PAL Calls.
   PAL Calls require PEI and DXE specific mechanisms to look up PAL Entry Point.
   As a result, these services could not be defined in the Base Library.
 
-Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/Library/DebugLib.h b/MdePkg/Include/Library/DebugLib.h
index a26b635a22f1..d71dacd79d4a 100644
--- a/MdePkg/Include/Library/DebugLib.h
+++ b/MdePkg/Include/Library/DebugLib.h
@@ -1,6 +1,6 @@
 /** @file
   Provides services to print debug and assert messages to a debug output device.
-  
+
   The Debug library supports debug print and asserts based on a combination of macros and code.
   The debug library can be turned on and off so that the debug code does not increase the size of an image.
 
@@ -8,14 +8,8 @@
   of size reduction when compiler optimization is disabled. If MDEPKG_NDEBUG is
   defined, then debug and assert related macros wrapped by it are the NULL implementations.
 
-Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -80,15 +74,15 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 /**
   Prints a debug message to the debug output device if the specified error level is enabled.
 
-  If any bit in ErrorLevel is also set in DebugPrintErrorLevelLib function 
-  GetDebugPrintErrorLevel (), then print the message specified by Format and the 
+  If any bit in ErrorLevel is also set in DebugPrintErrorLevelLib function
+  GetDebugPrintErrorLevel (), then print the message specified by Format and the
   associated variable argument list to the debug output device.
 
   If Format is NULL, then ASSERT().
 
   @param  ErrorLevel  The error level of the debug message.
   @param  Format      The format string for the debug message to print.
-  @param  ...         The variable argument list whose contents are accessed 
+  @param  ...         The variable argument list whose contents are accessed
                       based on the format string specified by Format.
 
 **/
@@ -102,14 +96,64 @@ DebugPrint (
 
 
 /**
-  Prints an assert message containing a filename, line number, and description.  
+  Prints a debug message to the debug output device if the specified
+  error level is enabled.
+
+  If any bit in ErrorLevel is also set in DebugPrintErrorLevelLib function
+  GetDebugPrintErrorLevel (), then print the message specified by Format and
+  the associated variable argument list to the debug output device.
+
+  If Format is NULL, then ASSERT().
+
+  @param  ErrorLevel    The error level of the debug message.
+  @param  Format        Format string for the debug message to print.
+  @param  VaListMarker  VA_LIST marker for the variable argument list.
+
+**/
+VOID
+EFIAPI
+DebugVPrint (
+  IN  UINTN         ErrorLevel,
+  IN  CONST CHAR8   *Format,
+  IN  VA_LIST       VaListMarker
+  );
+
+
+/**
+  Prints a debug message to the debug output device if the specified
+  error level is enabled.
+  This function use BASE_LIST which would provide a more compatible
+  service than VA_LIST.
+
+  If any bit in ErrorLevel is also set in DebugPrintErrorLevelLib function
+  GetDebugPrintErrorLevel (), then print the message specified by Format and
+  the associated variable argument list to the debug output device.
+
+  If Format is NULL, then ASSERT().
+
+  @param  ErrorLevel      The error level of the debug message.
+  @param  Format          Format string for the debug message to print.
+  @param  BaseListMarker  BASE_LIST marker for the variable argument list.
+
+**/
+VOID
+EFIAPI
+DebugBPrint (
+  IN  UINTN         ErrorLevel,
+  IN  CONST CHAR8   *Format,
+  IN  BASE_LIST     BaseListMarker
+  );
+
+
+/**
+  Prints an assert message containing a filename, line number, and description.
   This may be followed by a breakpoint or a dead loop.
 
   Print a message of the form "ASSERT <FileName>(<LineNumber>): <Description>\n"
-  to the debug output device.  If DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED bit of 
-  PcdDebugProperyMask is set then CpuBreakpoint() is called. Otherwise, if 
-  DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of PcdDebugProperyMask is set then 
-  CpuDeadLoop() is called.  If neither of these bits are set, then this function 
+  to the debug output device.  If DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED bit of
+  PcdDebugProperyMask is set then CpuBreakpoint() is called. Otherwise, if
+  DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of PcdDebugProperyMask is set then
+  CpuDeadLoop() is called.  If neither of these bits are set, then this function
   returns immediately after the message is printed to the debug output device.
   DebugAssert() must actively prevent recursion.  If DebugAssert() is called while
   processing another DebugAssert(), then DebugAssert() must return immediately.
@@ -134,14 +178,14 @@ DebugAssert (
 /**
   Fills a target buffer with PcdDebugClearMemoryValue, and returns the target buffer.
 
-  This function fills Length bytes of Buffer with the value specified by 
+  This function fills Length bytes of Buffer with the value specified by
   PcdDebugClearMemoryValue, and returns Buffer.
 
   If Buffer is NULL, then ASSERT().
-  If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). 
+  If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
 
   @param   Buffer  The pointer to the target buffer to be filled with PcdDebugClearMemoryValue.
-  @param   Length  The number of bytes in Buffer to fill with zeros PcdDebugClearMemoryValue. 
+  @param   Length  The number of bytes in Buffer to fill with zeros PcdDebugClearMemoryValue.
 
   @return  Buffer  The pointer to the target buffer filled with PcdDebugClearMemoryValue.
 
@@ -157,7 +201,7 @@ DebugClearMemory (
 /**
   Returns TRUE if ASSERT() macros are enabled.
 
-  This function returns TRUE if the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of 
+  This function returns TRUE if the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of
   PcdDebugProperyMask is set.  Otherwise, FALSE is returned.
 
   @retval  TRUE    The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugProperyMask is set.
@@ -171,10 +215,10 @@ DebugAssertEnabled (
   );
 
 
-/**  
+/**
   Returns TRUE if DEBUG() macros are enabled.
 
-  This function returns TRUE if the DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of 
+  This function returns TRUE if the DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of
   PcdDebugProperyMask is set.  Otherwise, FALSE is returned.
 
   @retval  TRUE    The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugProperyMask is set.
@@ -188,10 +232,10 @@ DebugPrintEnabled (
   );
 
 
-/**  
+/**
   Returns TRUE if DEBUG_CODE() macros are enabled.
 
-  This function returns TRUE if the DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of 
+  This function returns TRUE if the DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of
   PcdDebugProperyMask is set.  Otherwise, FALSE is returned.
 
   @retval  TRUE    The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is set.
@@ -205,10 +249,10 @@ DebugCodeEnabled (
   );
 
 
-/**  
+/**
   Returns TRUE if DEBUG_CLEAR_MEMORY() macro is enabled.
 
-  This function returns TRUE if the DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of 
+  This function returns TRUE if the DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of
   PcdDebugProperyMask is set.  Otherwise, FALSE is returned.
 
   @retval  TRUE    The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of PcdDebugProperyMask is set.
@@ -236,7 +280,7 @@ DebugPrintLevelEnabled (
   IN  CONST UINTN        ErrorLevel
   );
 
-/**  
+/**
   Internal worker macro that calls DebugAssert().
 
   This macro calls DebugAssert(), passing in the filename, line number, and an
@@ -245,18 +289,22 @@ DebugPrintLevelEnabled (
   @param  Expression  Boolean expression that evaluated to FALSE
 
 **/
+#if defined(__clang__) && defined(__FILE_NAME__)
+#define _ASSERT(Expression)  DebugAssert (__FILE_NAME__, __LINE__, #Expression)
+#else
 #define _ASSERT(Expression)  DebugAssert (__FILE__, __LINE__, #Expression)
+#endif
 
 
-/**  
+/**
   Internal worker macro that calls DebugPrint().
 
-  This macro calls DebugPrint() passing in the debug error level, a format 
+  This macro calls DebugPrint() passing in the debug error level, a format
   string, and a variable argument list.
   __VA_ARGS__ is not supported by EBC compiler, Microsoft Visual Studio .NET 2003
   and Microsoft Windows Server 2003 Driver Development Kit (Microsoft WINDDK) version 3790.1830.
 
-  @param  Expression  Expression containing an error level, a format string, 
+  @param  Expression  Expression containing an error level, a format string,
                       and a variable argument list based on the format string.
 
 **/
@@ -273,19 +321,19 @@ DebugPrintLevelEnabled (
 #define _DEBUG(Expression)   DebugPrint Expression
 #endif
 
-/**  
+/**
   Macro that calls DebugAssert() if an expression evaluates to FALSE.
 
-  If MDEPKG_NDEBUG is not defined and the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED 
-  bit of PcdDebugProperyMask is set, then this macro evaluates the Boolean 
-  expression specified by Expression.  If Expression evaluates to FALSE, then 
-  DebugAssert() is called passing in the source filename, source line number, 
+  If MDEPKG_NDEBUG is not defined and the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED
+  bit of PcdDebugProperyMask is set, then this macro evaluates the Boolean
+  expression specified by Expression.  If Expression evaluates to FALSE, then
+  DebugAssert() is called passing in the source filename, source line number,
   and Expression.
 
   @param  Expression  Boolean expression.
 
 **/
-#if !defined(MDEPKG_NDEBUG)       
+#if !defined(MDEPKG_NDEBUG)
   #define ASSERT(Expression)        \
     do {                            \
       if (DebugAssertEnabled ()) {  \
@@ -299,19 +347,19 @@ DebugPrintLevelEnabled (
   #define ASSERT(Expression)
 #endif
 
-/**  
+/**
   Macro that calls DebugPrint().
 
-  If MDEPKG_NDEBUG is not defined and the DEBUG_PROPERTY_DEBUG_PRINT_ENABLED 
-  bit of PcdDebugProperyMask is set, then this macro passes Expression to 
+  If MDEPKG_NDEBUG is not defined and the DEBUG_PROPERTY_DEBUG_PRINT_ENABLED
+  bit of PcdDebugProperyMask is set, then this macro passes Expression to
   DebugPrint().
 
-  @param  Expression  Expression containing an error level, a format string, 
+  @param  Expression  Expression containing an error level, a format string,
                       and a variable argument list based on the format string.
-  
+
 
 **/
-#if !defined(MDEPKG_NDEBUG)      
+#if !defined(MDEPKG_NDEBUG)
   #define DEBUG(Expression)        \
     do {                           \
       if (DebugPrintEnabled ()) {  \
@@ -322,13 +370,13 @@ DebugPrintLevelEnabled (
   #define DEBUG(Expression)
 #endif
 
-/**  
+/**
   Macro that calls DebugAssert() if an EFI_STATUS evaluates to an error code.
 
-  If MDEPKG_NDEBUG is not defined and the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED 
-  bit of PcdDebugProperyMask is set, then this macro evaluates the EFI_STATUS 
-  value specified by StatusParameter.  If StatusParameter is an error code, 
-  then DebugAssert() is called passing in the source filename, source line 
+  If MDEPKG_NDEBUG is not defined and the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED
+  bit of PcdDebugProperyMask is set, then this macro evaluates the EFI_STATUS
+  value specified by StatusParameter.  If StatusParameter is an error code,
+  then DebugAssert() is called passing in the source filename, source line
   number, and StatusParameter.
 
   @param  StatusParameter  EFI_STATUS value to evaluate.
@@ -375,23 +423,23 @@ DebugPrintLevelEnabled (
   #define ASSERT_RETURN_ERROR(StatusParameter)
 #endif
 
-/**  
-  Macro that calls DebugAssert() if a protocol is already installed in the 
+/**
+  Macro that calls DebugAssert() if a protocol is already installed in the
   handle database.
 
-  If MDEPKG_NDEBUG is defined or the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit 
+  If MDEPKG_NDEBUG is defined or the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit
   of PcdDebugProperyMask is clear, then return.
 
-  If Handle is NULL, then a check is made to see if the protocol specified by Guid 
-  is present on any handle in the handle database.  If Handle is not NULL, then 
-  a check is made to see if the protocol specified by Guid is present on the 
-  handle specified by Handle.  If the check finds the protocol, then DebugAssert() 
+  If Handle is NULL, then a check is made to see if the protocol specified by Guid
+  is present on any handle in the handle database.  If Handle is not NULL, then
+  a check is made to see if the protocol specified by Guid is present on the
+  handle specified by Handle.  If the check finds the protocol, then DebugAssert()
   is called passing in the source filename, source line number, and Guid.
 
   If Guid is NULL, then ASSERT().
 
-  @param  Handle  The handle to check for the protocol.  This is an optional 
-                  parameter that may be NULL.  If it is NULL, then the entire 
+  @param  Handle  The handle to check for the protocol.  This is an optional
+                  parameter that may be NULL.  If it is NULL, then the entire
                   handle database is searched.
 
   @param  Guid    The pointer to a protocol GUID.
@@ -421,32 +469,32 @@ DebugPrintLevelEnabled (
 /**
   Macro that marks the beginning of debug source code.
 
-  If the DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is set, 
+  If the DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is set,
   then this macro marks the beginning of source code that is included in a module.
-  Otherwise, the source lines between DEBUG_CODE_BEGIN() and DEBUG_CODE_END() 
+  Otherwise, the source lines between DEBUG_CODE_BEGIN() and DEBUG_CODE_END()
   are not included in a module.
 
 **/
 #define DEBUG_CODE_BEGIN()  do { if (DebugCodeEnabled ()) { UINT8  __DebugCodeLocal
 
 
-/**  
+/**
   The macro that marks the end of debug source code.
 
-  If the DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is set, 
-  then this macro marks the end of source code that is included in a module.  
-  Otherwise, the source lines between DEBUG_CODE_BEGIN() and DEBUG_CODE_END() 
+  If the DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is set,
+  then this macro marks the end of source code that is included in a module.
+  Otherwise, the source lines between DEBUG_CODE_BEGIN() and DEBUG_CODE_END()
   are not included in a module.
 
 **/
 #define DEBUG_CODE_END()    __DebugCodeLocal = 0; __DebugCodeLocal++; } } while (FALSE)
 
 
-/**  
+/**
   The macro that declares a section of debug source code.
 
-  If the DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is set, 
-  then the source code specified by Expression is included in a module.  
+  If the DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is set,
+  then the source code specified by Expression is included in a module.
   Otherwise, the source specified by Expression is not included in a module.
 
 **/
@@ -456,10 +504,10 @@ DebugPrintLevelEnabled (
   DEBUG_CODE_END ()
 
 
-/**  
+/**
   The macro that calls DebugClearMemory() to clear a buffer to a default value.
 
-  If the DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of PcdDebugProperyMask is set, 
+  If the DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of PcdDebugProperyMask is set,
   then this macro calls DebugClearMemory() passing in Address and Length.
 
   @param  Address  The pointer to a buffer.
@@ -475,42 +523,42 @@ DebugPrintLevelEnabled (
 
 
 /**
-  Macro that calls DebugAssert() if the containing record does not have a 
-  matching signature.  If the signatures matches, then a pointer to the data 
-  structure that contains a specified field of that data structure is returned.  
-  This is a lightweight method hide information by placing a public data 
-  structure inside a larger private data structure and using a pointer to the 
+  Macro that calls DebugAssert() if the containing record does not have a
+  matching signature.  If the signatures matches, then a pointer to the data
+  structure that contains a specified field of that data structure is returned.
+  This is a lightweight method hide information by placing a public data
+  structure inside a larger private data structure and using a pointer to the
   public data structure to retrieve a pointer to the private data structure.
 
-  If MDEPKG_NDEBUG is defined or the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit 
+  If MDEPKG_NDEBUG is defined or the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit
   of PcdDebugProperyMask is clear, then this macro computes the offset, in bytes,
-  of the field specified by Field from the beginning of the data structure specified 
-  by TYPE.  This offset is subtracted from Record, and is used to return a pointer 
+  of the field specified by Field from the beginning of the data structure specified
+  by TYPE.  This offset is subtracted from Record, and is used to return a pointer
   to a data structure of the type specified by TYPE.
 
   If MDEPKG_NDEBUG is not defined and the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit
-  of PcdDebugProperyMask is set, then this macro computes the offset, in bytes, 
-  of field specified by Field from the beginning of the data structure specified 
+  of PcdDebugProperyMask is set, then this macro computes the offset, in bytes,
+  of field specified by Field from the beginning of the data structure specified
   by TYPE.  This offset is subtracted from Record, and is used to compute a pointer
-  to a data structure of the type specified by TYPE.  The Signature field of the 
-  data structure specified by TYPE is compared to TestSignature.  If the signatures 
-  match, then a pointer to the pointer to a data structure of the type specified by 
-  TYPE is returned.  If the signatures do not match, then DebugAssert() is called 
-  with a description of "CR has a bad signature" and Record is returned.  
+  to a data structure of the type specified by TYPE.  The Signature field of the
+  data structure specified by TYPE is compared to TestSignature.  If the signatures
+  match, then a pointer to the pointer to a data structure of the type specified by
+  TYPE is returned.  If the signatures do not match, then DebugAssert() is called
+  with a description of "CR has a bad signature" and Record is returned.
 
-  If the data type specified by TYPE does not contain the field specified by Field, 
+  If the data type specified by TYPE does not contain the field specified by Field,
   then the module will not compile.
 
-  If TYPE does not contain a field called Signature, then the module will not 
+  If TYPE does not contain a field called Signature, then the module will not
   compile.
 
-  @param  Record         The pointer to the field specified by Field within a data 
+  @param  Record         The pointer to the field specified by Field within a data
                          structure of type TYPE.
 
-  @param  TYPE           The name of the data structure type to return  This 
-                         data structure must contain the field specified by Field. 
+  @param  TYPE           The name of the data structure type to return  This
+                         data structure must contain the field specified by Field.
 
-  @param  Field          The name of the field in the data structure specified 
+  @param  Field          The name of the field in the data structure specified
                          by TYPE to which Record points.
 
   @param  TestSignature  The 32-bit signature value to match.
@@ -525,5 +573,5 @@ DebugPrintLevelEnabled (
   #define CR(Record, TYPE, Field, TestSignature)                                              \
     BASE_CR (Record, TYPE, Field)
 #endif
-    
+
 #endif
diff --git a/MdePkg/Include/Library/DebugPrintErrorLevelLib.h b/MdePkg/Include/Library/DebugPrintErrorLevelLib.h
index 496f07b54d17..f57097f815b4 100644
--- a/MdePkg/Include/Library/DebugPrintErrorLevelLib.h
+++ b/MdePkg/Include/Library/DebugPrintErrorLevelLib.h
@@ -1,14 +1,8 @@
 /** @file
   Debug Print Error Level Library class
 
-  Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php.
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 #ifndef _DEBUG_PRINT_ERROR_LEVEL_LIB_H_
@@ -28,9 +22,9 @@ GetDebugPrintErrorLevel (
 
 /**
   Sets the global debug print error level mask fpr the entire platform.
-  
+
   @param   ErrorLevel     Global debug print error level
-  
+
   @retval  TRUE           The debug print error level mask was successfully set.
   @retval  FALSE          The debug print error level mask could not be set.
 
diff --git a/MdePkg/Include/Library/DevicePathLib.h b/MdePkg/Include/Library/DevicePathLib.h
index 61fa19ce690d..687b5b30dda0 100644
--- a/MdePkg/Include/Library/DevicePathLib.h
+++ b/MdePkg/Include/Library/DevicePathLib.h
@@ -1,17 +1,11 @@
 /** @file
   Provides library functions to construct and parse UEFI Device Paths.
 
-  This library provides defines, macros, and functions to help create and parse 
+  This library provides defines, macros, and functions to help create and parse
   EFI_DEVICE_PATH_PROTOCOL structures.
 
-Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -22,12 +16,13 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
 /**
   Determine whether a given device path is valid.
-  If DevicePath is NULL, then ASSERT().
 
   @param  DevicePath  A pointer to a device path data structure.
   @param  MaxSize     The maximum size of the device path data structure.
 
   @retval TRUE        DevicePath is valid.
+  @retval FALSE       DevicePath is NULL.
+  @retval FALSE       Maxsize is less than sizeof(EFI_DEVICE_PATH_PROTOCOL).
   @retval FALSE       The length of any node node in the DevicePath is less
                       than sizeof (EFI_DEVICE_PATH_PROTOCOL).
   @retval FALSE       If MaxSize is not zero, the size of the DevicePath
@@ -81,9 +76,9 @@ DevicePathSubType (
 /**
   Returns the 16-bit Length field of a device path node.
 
-  Returns the 16-bit Length field of the device path node specified by Node.  
+  Returns the 16-bit Length field of the device path node specified by Node.
   Node is not required to be aligned on a 16-bit boundary, so it is recommended
-  that a function such as ReadUnaligned16() be used to extract the contents of 
+  that a function such as ReadUnaligned16() be used to extract the contents of
   the Length field.
 
   If Node is NULL, then ASSERT().
@@ -119,12 +114,12 @@ NextDevicePathNode (
 
 /**
   Determines if a device path node is an end node of a device path.
-  This includes nodes that are the end of a device path instance and nodes that 
+  This includes nodes that are the end of a device path instance and nodes that
   are the end of an entire device path.
 
-  Determines if the device path node specified by Node is an end node of a device path.  
-  This includes nodes that are the end of a device path instance and nodes that are the 
-  end of an entire device path.  If Node represents an end node of a device path, 
+  Determines if the device path node specified by Node is an end node of a device path.
+  This includes nodes that are the end of a device path instance and nodes that are the
+  end of an entire device path.  If Node represents an end node of a device path,
   then TRUE is returned.  Otherwise, FALSE is returned.
 
   If Node is NULL, then ASSERT().
@@ -133,7 +128,7 @@ NextDevicePathNode (
 
   @retval TRUE      The device path node specified by Node is an end node of a device path.
   @retval FALSE     The device path node specified by Node is not an end node of a device path.
-  
+
 **/
 BOOLEAN
 EFIAPI
@@ -186,8 +181,8 @@ IsDevicePathEndInstance (
 /**
   Sets the length, in bytes, of a device path node.
 
-  Sets the length of the device path node specified by Node to the value specified 
-  by NodeLength.  NodeLength is returned.  Node is not required to be aligned on 
+  Sets the length of the device path node specified by Node to the value specified
+  by NodeLength.  NodeLength is returned.  Node is not required to be aligned on
   a 16-bit boundary, so it is recommended that a function such as WriteUnaligned16()
   be used to set the contents of the Length field.
 
@@ -211,15 +206,15 @@ SetDevicePathNodeLength (
 /**
   Fills in all the fields of a device path node that is the end of an entire device path.
 
-  Fills in all the fields of a device path node specified by Node so Node represents 
-  the end of an entire device path.  The Type field of Node is set to 
-  END_DEVICE_PATH_TYPE, the SubType field of Node is set to 
-  END_ENTIRE_DEVICE_PATH_SUBTYPE, and the Length field of Node is set to 
-  END_DEVICE_PATH_LENGTH.  Node is not required to be aligned on a 16-bit boundary, 
-  so it is recommended that a function such as WriteUnaligned16() be used to set 
-  the contents of the Length field. 
+  Fills in all the fields of a device path node specified by Node so Node represents
+  the end of an entire device path.  The Type field of Node is set to
+  END_DEVICE_PATH_TYPE, the SubType field of Node is set to
+  END_ENTIRE_DEVICE_PATH_SUBTYPE, and the Length field of Node is set to
+  END_DEVICE_PATH_LENGTH.  Node is not required to be aligned on a 16-bit boundary,
+  so it is recommended that a function such as WriteUnaligned16() be used to set
+  the contents of the Length field.
 
-  If Node is NULL, then ASSERT(). 
+  If Node is NULL, then ASSERT().
 
   @param  Node      A pointer to a device path node data structure.
 
@@ -233,7 +228,7 @@ SetDevicePathEndNode (
 /**
   Returns the size of a device path in bytes.
 
-  This function returns the size, in bytes, of the device path data structure 
+  This function returns the size, in bytes, of the device path data structure
   specified by DevicePath including the end of device path node.
   If DevicePath is NULL or invalid, then 0 is returned.
 
@@ -255,15 +250,15 @@ GetDevicePathSize (
   This function allocates space for a new copy of the device path specified by DevicePath.  If
   DevicePath is NULL, then NULL is returned.  If the memory is successfully allocated, then the
   contents of DevicePath are copied to the newly allocated buffer, and a pointer to that buffer
-  is returned.  Otherwise, NULL is returned.  
-  The memory for the new device path is allocated from EFI boot services memory. 
-  It is the responsibility of the caller to free the memory allocated. 
-  
+  is returned.  Otherwise, NULL is returned.
+  The memory for the new device path is allocated from EFI boot services memory.
+  It is the responsibility of the caller to free the memory allocated.
+
   @param  DevicePath                 A pointer to a device path data structure.
 
   @retval NULL    DevicePath is NULL or invalid.
   @retval Others  A pointer to the duplicated device path.
-  
+
 **/
 EFI_DEVICE_PATH_PROTOCOL *
 EFIAPI
@@ -276,18 +271,18 @@ DuplicateDevicePath (
 
   This function creates a new device path by appending a copy of SecondDevicePath to a copy of
   FirstDevicePath in a newly allocated buffer.  Only the end-of-device-path device node from
-  SecondDevicePath is retained. The newly created device path is returned.  
-  If FirstDevicePath is NULL, then it is ignored, and a duplicate of SecondDevicePath is returned.  
-  If SecondDevicePath is NULL, then it is ignored, and a duplicate of FirstDevicePath is returned.  
+  SecondDevicePath is retained. The newly created device path is returned.
+  If FirstDevicePath is NULL, then it is ignored, and a duplicate of SecondDevicePath is returned.
+  If SecondDevicePath is NULL, then it is ignored, and a duplicate of FirstDevicePath is returned.
   If both FirstDevicePath and SecondDevicePath are NULL, then a copy of an end-of-device-path is
-  returned.  
+  returned.
   If there is not enough memory for the newly allocated buffer, then NULL is returned.
   The memory for the new device path is allocated from EFI boot services memory. It is the
   responsibility of the caller to free the memory allocated.
 
   @param  FirstDevicePath            A pointer to a device path data structure.
   @param  SecondDevicePath           A pointer to a device path data structure.
-  
+
   @retval NULL      If there is not enough memory for the newly allocated buffer.
   @retval NULL      If FirstDevicePath or SecondDevicePath is invalid.
   @retval Others    A pointer to the new device path if success.
@@ -312,7 +307,7 @@ AppendDevicePath (
   node is returned.
   If both DevicePathNode and DevicePath are NULL then a copy of an end-of-device-path device node
   is returned.
-  If there is not enough memory to allocate space for the new device path, then NULL is returned.  
+  If there is not enough memory to allocate space for the new device path, then NULL is returned.
   The memory is allocated from EFI boot services memory. It is the responsibility of the caller to
   free the memory allocated.
 
@@ -321,7 +316,7 @@ AppendDevicePath (
 
   @retval NULL      There is not enough memory for the new device path.
   @retval Others    A pointer to the new device path if success.
-                    A copy of DevicePathNode followed by an end-of-device-path node 
+                    A copy of DevicePathNode followed by an end-of-device-path node
                     if both FirstDevicePath and SecondDevicePath are NULL.
                     A copy of an end-of-device-path node if both FirstDevicePath and SecondDevicePath are NULL.
 
@@ -336,18 +331,18 @@ AppendDevicePathNode (
 /**
   Creates a new device path by appending the specified device path instance to the specified device
   path.
- 
+
   This function creates a new device path by appending a copy of the device path instance specified
   by DevicePathInstance to a copy of the device path secified by DevicePath in a allocated buffer.
   The end-of-device-path device node is moved after the end of the appended device path instance
-  and a new end-of-device-path-instance node is inserted between. 
+  and a new end-of-device-path-instance node is inserted between.
   If DevicePath is NULL, then a copy if DevicePathInstance is returned.
   If DevicePathInstance is NULL, then NULL is returned.
   If DevicePath or DevicePathInstance is invalid, then NULL is returned.
-  If there is not enough memory to allocate space for the new device path, then NULL is returned.  
+  If there is not enough memory to allocate space for the new device path, then NULL is returned.
   The memory is allocated from EFI boot services memory. It is the responsibility of the caller to
   free the memory allocated.
-  
+
   @param  DevicePath                 A pointer to a device path data structure.
   @param  DevicePathInstance         A pointer to a device path instance.
 
@@ -370,11 +365,11 @@ AppendDevicePathInstance (
   to hold the size of the device path instance copy.
   If DevicePath is NULL, then NULL is returned.
   If DevicePath points to a invalid device path, then NULL is returned.
-  If there is not enough memory to allocate space for the new device path, then NULL is returned.  
+  If there is not enough memory to allocate space for the new device path, then NULL is returned.
   The memory is allocated from EFI boot services memory. It is the responsibility of the caller to
   free the memory allocated.
   If Size is NULL, then ASSERT().
- 
+
   @param  DevicePath                 On input, this holds the pointer to the current device path
                                      instance. On output, this holds the pointer to the next device
                                      path instance or NULL if there are no more device path
@@ -399,8 +394,8 @@ GetNextDevicePathInstance (
   This function creates a new device node in a newly allocated buffer of size NodeLength and
   initializes the device path node header with NodeType and NodeSubType.  The new device path node
   is returned.
-  If NodeLength is smaller than a device path header, then NULL is returned.  
-  If there is not enough memory to allocate space for the new device path, then NULL is returned.  
+  If NodeLength is smaller than a device path header, then NULL is returned.
+  If there is not enough memory to allocate space for the new device path, then NULL is returned.
   The memory is allocated from EFI boot services memory. It is the responsibility of the caller to
   free the memory allocated.
 
@@ -443,7 +438,7 @@ IsDevicePathMultiInstance (
 
   This function returns the device path protocol from the handle specified by Handle.  If Handle is
   NULL or Handle does not contain a device path protocol, then NULL is returned.
- 
+
   @param  Handle                     The handle from which to retrieve the device path protocol.
 
   @return The device path protocol from the handle specified by Handle.
@@ -465,7 +460,7 @@ DevicePathFromHandle (
   path node for the file specified by FileName is allocated and returned.
   The memory for the new device path is allocated from EFI boot services memory. It is the responsibility
   of the caller to free the memory allocated.
-  
+
   If FileName is NULL, then ASSERT().
   If FileName is not aligned on a 16-bit boundary, then ASSERT().
 
diff --git a/MdePkg/Include/Library/DxeCoreEntryPoint.h b/MdePkg/Include/Library/DxeCoreEntryPoint.h
index b0de4ee9ff3e..0a18966e03ea 100644
--- a/MdePkg/Include/Library/DxeCoreEntryPoint.h
+++ b/MdePkg/Include/Library/DxeCoreEntryPoint.h
@@ -1,14 +1,8 @@
 /** @file
   Module entry point library for DXE core.
 
-Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -16,13 +10,13 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #define __MODULE_ENTRY_POINT_H__
 
 ///
-/// Global variable that contains a pointer to the Hob List passed into the DXE Core entry point. 
-/// 
+/// Global variable that contains a pointer to the Hob List passed into the DXE Core entry point.
+///
 extern VOID  *gHobList;
 
 
 /**
-  The entry point of PE/COFF Image for the DXE Core. 
+  The entry point of PE/COFF Image for the DXE Core.
 
   This function is the entry point for the DXE Core. This function is required to call
   ProcessModuleEntryPointList() and ProcessModuleEntryPointList() is never expected to return.
@@ -30,7 +24,7 @@ extern VOID  *gHobList;
   System Table and the image handle for the DXE Core itself have been established.
   If ProcessModuleEntryPointList() returns, then ASSERT() and halt the system.
 
-  @param  HobStart  Pointer to the beginning of the HOB List passed in from the PEI Phase. 
+  @param  HobStart  Pointer to the beginning of the HOB List passed in from the PEI Phase.
 
 **/
 VOID
@@ -45,7 +39,7 @@ _ModuleEntryPoint (
 
   This function is required to call _ModuleEntryPoint() passing in HobStart.
 
-  @param  HobStart  Pointer to the beginning of the HOB List passed in from the PEI Phase. 
+  @param  HobStart  Pointer to the beginning of the HOB List passed in from the PEI Phase.
 
 **/
 VOID
@@ -83,12 +77,12 @@ ProcessLibraryConstructorList (
   Autogenerated function that calls a set of module entry points.
 
   This function must be called by _ModuleEntryPoint().
-  This function calls the set of module entry points.  
+  This function calls the set of module entry points.
   This function is autogenerated by build tools and those build tools are responsible
   for collecting the module entry points and calling them in a specified order.
 
-  @param  HobStart  Pointer to the beginning of the HOB List passed in from the PEI Phase. 
- 
+  @param  HobStart  Pointer to the beginning of the HOB List passed in from the PEI Phase.
+
 **/
 VOID
 EFIAPI
diff --git a/MdePkg/Include/Library/DxeServicesLib.h b/MdePkg/Include/Library/DxeServicesLib.h
index 48cb70339850..54040e8289eb 100644
--- a/MdePkg/Include/Library/DxeServicesLib.h
+++ b/MdePkg/Include/Library/DxeServicesLib.h
@@ -1,16 +1,10 @@
 /** @file
-  MDE DXE Services Library provides functions that simplify the development of DXE Drivers.  
+  MDE DXE Services Library provides functions that simplify the development of DXE Drivers.
   These functions help access data from sections of FFS files or from file path.
 
-Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
 (C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                           
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -18,20 +12,20 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #define __DXE_SERVICES_LIB_H__
 
 /**
-  Searches all the available firmware volumes and returns the first matching FFS section. 
+  Searches all the available firmware volumes and returns the first matching FFS section.
 
   This function searches all the firmware volumes for FFS files with FV file type specified by FileType
-  The order that the firmware volumes is searched is not deterministic. For each available FV a search 
-  is made for FFS file of type FileType. If the FV contains more than one FFS file with the same FileType, 
-  the FileInstance instance will be the matched FFS file. For each FFS file found a search 
-  is made for FFS sections of type SectionType. If the FFS file contains at least SectionInstance instances 
-  of the FFS section specified by SectionType, then the SectionInstance instance is returned in Buffer. 
-  Buffer is allocated using AllocatePool(), and the size of the allocated buffer is returned in Size. 
-  It is the caller's responsibility to use FreePool() to free the allocated buffer.  
-  See EFI_FIRMWARE_VOLUME2_PROTOCOL.ReadSection() for details on how sections 
+  The order that the firmware volumes is searched is not deterministic. For each available FV a search
+  is made for FFS file of type FileType. If the FV contains more than one FFS file with the same FileType,
+  the FileInstance instance will be the matched FFS file. For each FFS file found a search
+  is made for FFS sections of type SectionType. If the FFS file contains at least SectionInstance instances
+  of the FFS section specified by SectionType, then the SectionInstance instance is returned in Buffer.
+  Buffer is allocated using AllocatePool(), and the size of the allocated buffer is returned in Size.
+  It is the caller's responsibility to use FreePool() to free the allocated buffer.
+  See EFI_FIRMWARE_VOLUME2_PROTOCOL.ReadSection() for details on how sections
   are retrieved from an FFS file based on SectionType and SectionInstance.
 
-  If SectionType is EFI_SECTION_TE, and the search with an FFS file fails, 
+  If SectionType is EFI_SECTION_TE, and the search with an FFS file fails,
   the search will be retried with a section type of EFI_SECTION_PE32.
   This function must be called with a TPL <= TPL_NOTIFY.
 
@@ -41,9 +35,9 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   @param  FileType             Indicates the FV file type to search for within all available FVs.
   @param  FileInstance         Indicates which file instance within all available FVs specified by FileType.
                                FileInstance starts from zero.
-  @param  SectionType          Indicates the FFS section type to search for within the FFS file 
+  @param  SectionType          Indicates the FFS section type to search for within the FFS file
                                specified by FileType with FileInstance.
-  @param  SectionInstance      Indicates which section instance within the FFS file 
+  @param  SectionInstance      Indicates which section instance within the FFS file
                                specified by FileType with FileInstance to retrieve. SectionInstance starts from zero.
   @param  Buffer               On output, a pointer to a callee allocated buffer containing the FFS file section that was found.
                                Is it the caller's responsibility to free this buffer using FreePool().
@@ -53,7 +47,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   @retval  EFI_NOT_FOUND        The specified FFS section could not be found.
   @retval  EFI_OUT_OF_RESOURCES There are not enough resources available to retrieve the matching FFS section.
   @retval  EFI_DEVICE_ERROR     The FFS section could not be retrieves due to a device error.
-  @retval  EFI_ACCESS_DENIED    The FFS section could not be retrieves because the firmware volume that 
+  @retval  EFI_ACCESS_DENIED    The FFS section could not be retrieves because the firmware volume that
                                 contains the matching FFS section does not allow reads.
 **/
 EFI_STATUS
@@ -68,18 +62,18 @@ GetSectionFromAnyFvByFileType  (
   );
 
 /**
-  Searches all the available firmware volumes and returns the first matching FFS section. 
-
-  This function searches all the firmware volumes for FFS files with an FFS filename specified by NameGuid.  
-  The order in which the firmware volumes are searched is not deterministic. For each FFS file found, a search 
-  is made for FFS sections of type SectionType. If the FFS file contains at least SectionInstance instances 
-  of the FFS section specified by SectionType, then the SectionInstance instance is returned in Buffer. 
-  Buffer is allocated using AllocatePool(), and the size of the allocated buffer is returned in Size. 
-  It is the caller's responsibility to use FreePool() to free the allocated buffer.  
-  See EFI_FIRMWARE_VOLUME2_PROTOCOL.ReadSection() for details on how sections 
+  Searches all the available firmware volumes and returns the first matching FFS section.
+
+  This function searches all the firmware volumes for FFS files with an FFS filename specified by NameGuid.
+  The order in which the firmware volumes are searched is not deterministic. For each FFS file found, a search
+  is made for FFS sections of type SectionType. If the FFS file contains at least SectionInstance instances
+  of the FFS section specified by SectionType, then the SectionInstance instance is returned in Buffer.
+  Buffer is allocated using AllocatePool(), and the size of the allocated buffer is returned in Size.
+  It is the caller's responsibility to use FreePool() to free the allocated buffer.
+  See EFI_FIRMWARE_VOLUME2_PROTOCOL.ReadSection() for details on how sections
   are retrieved from an FFS file based on SectionType and SectionInstance.
 
-  If SectionType is EFI_SECTION_TE, and the search with an FFS file fails, 
+  If SectionType is EFI_SECTION_TE, and the search with an FFS file fails,
   the search will be retried with a section type of EFI_SECTION_PE32.
   This function must be called with a TPL <= TPL_NOTIFY.
 
@@ -88,26 +82,26 @@ GetSectionFromAnyFvByFileType  (
   If Size is NULL, then ASSERT().
 
 
-  @param  NameGuid             A pointer to to the FFS filename GUID to search for  
-                               within any of the firmware volumes in the platform. 
-  @param  SectionType          Indicates the FFS section type to search for within 
+  @param  NameGuid             A pointer to to the FFS filename GUID to search for
+                               within any of the firmware volumes in the platform.
+  @param  SectionType          Indicates the FFS section type to search for within
                                the FFS file specified by NameGuid.
-  @param  SectionInstance      Indicates which section instance within the FFS file 
+  @param  SectionInstance      Indicates which section instance within the FFS file
                                specified by NameGuid to retrieve.
-  @param  Buffer               On output, a pointer to a callee-allocated buffer 
-                               containing the FFS file section that was found.  
-                               It is the caller's responsibility to free this 
+  @param  Buffer               On output, a pointer to a callee-allocated buffer
+                               containing the FFS file section that was found.
+                               It is the caller's responsibility to free this
                                buffer using FreePool().
   @param  Size                 On output, a pointer to the size, in bytes, of Buffer.
 
   @retval  EFI_SUCCESS          The specified FFS section was returned.
   @retval  EFI_NOT_FOUND        The specified FFS section could not be found.
-  @retval  EFI_OUT_OF_RESOURCES There are not enough resources available to retrieve 
+  @retval  EFI_OUT_OF_RESOURCES There are not enough resources available to retrieve
                                 the matching FFS section.
-  @retval  EFI_DEVICE_ERROR     The FFS section could not be retrieves due to a 
+  @retval  EFI_DEVICE_ERROR     The FFS section could not be retrieves due to a
                                 device error.
-  @retval  EFI_ACCESS_DENIED    The FFS section could not be retrieves because the 
-                                firmware volume that contains the matching FFS 
+  @retval  EFI_ACCESS_DENIED    The FFS section could not be retrieves because the
+                                firmware volume that contains the matching FFS
                                 section does not allow reads.
 **/
 EFI_STATUS
@@ -121,49 +115,49 @@ GetSectionFromAnyFv  (
   );
 
 /**
-  Searches the firmware volume that the currently executing module was loaded from and returns the first matching FFS section. 
+  Searches the firmware volume that the currently executing module was loaded from and returns the first matching FFS section.
 
-  This function searches the firmware volume that the currently executing module was loaded 
-  from for an FFS file with an FFS filename specified by NameGuid. If the FFS file is found, a search 
-  is made for FFS sections of type SectionType. If the FFS file contains at least SectionInstance 
+  This function searches the firmware volume that the currently executing module was loaded
+  from for an FFS file with an FFS filename specified by NameGuid. If the FFS file is found, a search
+  is made for FFS sections of type SectionType. If the FFS file contains at least SectionInstance
   instances of the FFS section specified by SectionType, then the SectionInstance instance is returned in Buffer.
-  Buffer is allocated using AllocatePool(), and the size of the allocated buffer is returned in Size. 
-  It is the caller's responsibility to use FreePool() to free the allocated buffer. 
-  See EFI_FIRMWARE_VOLUME2_PROTOCOL.ReadSection() for details on how sections are retrieved from 
+  Buffer is allocated using AllocatePool(), and the size of the allocated buffer is returned in Size.
+  It is the caller's responsibility to use FreePool() to free the allocated buffer.
+  See EFI_FIRMWARE_VOLUME2_PROTOCOL.ReadSection() for details on how sections are retrieved from
   an FFS file based on SectionType and SectionInstance.
 
   If the currently executing module was not loaded from a firmware volume, then EFI_NOT_FOUND is returned.
-  If SectionType is EFI_SECTION_TE, and the search with an FFS file fails, 
+  If SectionType is EFI_SECTION_TE, and the search with an FFS file fails,
   the search will be retried with a section type of EFI_SECTION_PE32.
-  
+
   This function must be called with a TPL <= TPL_NOTIFY.
   If NameGuid is NULL, then ASSERT().
   If Buffer is NULL, then ASSERT().
   If Size is NULL, then ASSERT().
 
-  @param  NameGuid             A pointer to to the FFS filename GUID to search for  
-                               within the firmware volumes that the currently 
+  @param  NameGuid             A pointer to to the FFS filename GUID to search for
+                               within the firmware volumes that the currently
                                executing module was loaded from.
-  @param  SectionType          Indicates the FFS section type to search for within 
+  @param  SectionType          Indicates the FFS section type to search for within
                                the FFS file specified by NameGuid.
-  @param  SectionInstance      Indicates which section instance within the FFS 
+  @param  SectionInstance      Indicates which section instance within the FFS
                                file specified by NameGuid to retrieve.
-  @param  Buffer               On output, a pointer to a callee allocated buffer 
-                               containing the FFS file section that was found.  
-                               It is the caller's responsibility to free this buffer 
+  @param  Buffer               On output, a pointer to a callee allocated buffer
+                               containing the FFS file section that was found.
+                               It is the caller's responsibility to free this buffer
                                using FreePool().
   @param  Size                 On output, a pointer to the size, in bytes, of Buffer.
 
 
   @retval  EFI_SUCCESS          The specified FFS section was returned.
   @retval  EFI_NOT_FOUND        The specified FFS section could not be found.
-  @retval  EFI_OUT_OF_RESOURCES There are not enough resources available to retrieve 
+  @retval  EFI_OUT_OF_RESOURCES There are not enough resources available to retrieve
                                 the matching FFS section.
-  @retval  EFI_DEVICE_ERROR     The FFS section could not be retrieves due to a 
+  @retval  EFI_DEVICE_ERROR     The FFS section could not be retrieves due to a
                                 device error.
-  @retval  EFI_ACCESS_DENIED    The FFS section could not be retrieves because the 
-                                firmware volume that contains the matching FFS 
-                                section does not allow reads.  
+  @retval  EFI_ACCESS_DENIED    The FFS section could not be retrieves because the
+                                firmware volume that contains the matching FFS
+                                section does not allow reads.
 **/
 EFI_STATUS
 EFIAPI
@@ -177,46 +171,46 @@ GetSectionFromFv (
 
 
 /**
-  Searches the FFS file the the currently executing module was loaded from and returns the first matching FFS section.
+  Searches the FFS file the currently executing module was loaded from and returns the first matching FFS section.
 
   This function searches the FFS file that the currently executing module was loaded from for a FFS sections of type SectionType.
-  If the FFS file contains at least SectionInstance instances of the FFS section specified by SectionType, 
-  then the SectionInstance instance is returned in Buffer. Buffer is allocated using AllocatePool(), 
-  and the size of the allocated buffer is returned in Size. It is the caller's responsibility 
-  to use FreePool() to free the allocated buffer. See EFI_FIRMWARE_VOLUME2_PROTOCOL.ReadSection() for 
+  If the FFS file contains at least SectionInstance instances of the FFS section specified by SectionType,
+  then the SectionInstance instance is returned in Buffer. Buffer is allocated using AllocatePool(),
+  and the size of the allocated buffer is returned in Size. It is the caller's responsibility
+  to use FreePool() to free the allocated buffer. See EFI_FIRMWARE_VOLUME2_PROTOCOL.ReadSection() for
   details on how sections are retrieved from an FFS file based on SectionType and SectionInstance.
 
   If the currently executing module was not loaded from an FFS file, then EFI_NOT_FOUND is returned.
-  If SectionType is EFI_SECTION_TE, and the search with an FFS file fails, 
+  If SectionType is EFI_SECTION_TE, and the search with an FFS file fails,
   the search will be retried with a section type of EFI_SECTION_PE32.
   This function must be called with a TPL <= TPL_NOTIFY.
-  
+
   If Buffer is NULL, then ASSERT().
   If Size is NULL, then ASSERT().
 
 
-  @param  SectionType          Indicates the FFS section type to search for within  
-                               the FFS file that the currently executing module 
+  @param  SectionType          Indicates the FFS section type to search for within
+                               the FFS file that the currently executing module
                                was loaded from.
-  @param  SectionInstance      Indicates which section instance to retrieve within 
-                               the FFS file that the currently executing module 
+  @param  SectionInstance      Indicates which section instance to retrieve within
+                               the FFS file that the currently executing module
                                was loaded from.
-  @param  Buffer               On output, a pointer to a callee allocated buffer 
-                               containing the FFS file section that was found.  
-                               It is the caller's responsibility to free this buffer 
+  @param  Buffer               On output, a pointer to a callee allocated buffer
+                               containing the FFS file section that was found.
+                               It is the caller's responsibility to free this buffer
                                using FreePool().
   @param  Size                 On output, a pointer to the size, in bytes, of Buffer.
 
   @retval  EFI_SUCCESS          The specified FFS section was returned.
   @retval  EFI_NOT_FOUND        The specified FFS section could not be found.
-  @retval  EFI_OUT_OF_RESOURCES There are not enough resources available to retrieve 
+  @retval  EFI_OUT_OF_RESOURCES There are not enough resources available to retrieve
                                 the matching FFS section.
-  @retval  EFI_DEVICE_ERROR     The FFS section could not be retrieves due to a 
+  @retval  EFI_DEVICE_ERROR     The FFS section could not be retrieves due to a
                                 device error.
-  @retval  EFI_ACCESS_DENIED    The FFS section could not be retrieves because the 
-                                firmware volume that contains the matching FFS 
-                                section does not allow reads.  
-  
+  @retval  EFI_ACCESS_DENIED    The FFS section could not be retrieves because the
+                                firmware volume that contains the matching FFS
+                                section does not allow reads.
+
 **/
 EFI_STATUS
 EFIAPI
@@ -229,22 +223,22 @@ GetSectionFromFfs (
 
 
 /**
-  Get the image file buffer data and buffer size by its device path. 
-  
-  Access the file either from a firmware volume, from a file system interface, 
+  Get the image file buffer data and buffer size by its device path.
+
+  Access the file either from a firmware volume, from a file system interface,
   or from the load file interface.
-  
+
   Allocate memory to store the found image. The caller is responsible to free memory.
 
   If FilePath is NULL, then NULL is returned.
   If FileSize is NULL, then NULL is returned.
   If AuthenticationStatus is NULL, then NULL is returned.
 
-  @param[in]       BootPolicy           The policy for Open Image File.If TRUE, 
-                                        indicates that the request originates from 
+  @param[in]       BootPolicy           The policy for Open Image File.If TRUE,
+                                        indicates that the request originates from
                                         the boot manager, and that the boot manager is
-                                        attempting to load FilePath as a boot selection. 
-                                        If FALSE, then FilePath must match an exact 
+                                        attempting to load FilePath as a boot selection.
+                                        If FALSE, then FilePath must match an exact
                                         file to be loaded.
   @param[in]       FilePath             Pointer to the device path of the file that is abstracted to
                                         the file buffer.
@@ -305,5 +299,26 @@ GetFileDevicePathFromAnyFv (
   OUT       EFI_DEVICE_PATH_PROTOCOL  **FvFileDevicePath
   );
 
-#endif
+/**
+  Allocates one or more 4KB pages of a given type from a memory region that is
+  accessible to PEI.
+
+  Allocates the number of 4KB pages of type 'MemoryType' and returns a
+  pointer to the allocated buffer.  The buffer returned is aligned on a 4KB
+  boundary.  If Pages is 0, then NULL is returned.  If there is not enough
+  memory remaining to satisfy the request, then NULL is returned.
+
+  @param[in]  MemoryType            The memory type to allocate
+  @param[in]  Pages                 The number of 4 KB pages to allocate.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
 
+**/
+VOID *
+EFIAPI
+AllocatePeiAccessiblePages (
+  IN EFI_MEMORY_TYPE  MemoryType,
+  IN UINTN            Pages
+  );
+
+#endif
diff --git a/MdePkg/Include/Library/DxeServicesTableLib.h b/MdePkg/Include/Library/DxeServicesTableLib.h
index 0038715530fb..d604f4174747 100644
--- a/MdePkg/Include/Library/DxeServicesTableLib.h
+++ b/MdePkg/Include/Library/DxeServicesTableLib.h
@@ -1,24 +1,18 @@
 /** @file
   Provides a service to retrieve a pointer to the DXE Services Table.
   Only available to DXE module types.
-  
-  This library does not contain any functions or macros.  It simply exports a global 
-  pointer to the DXE Services Table as defined in the Platform Initialization Driver 
-  Execution Environment Core Interface Specification.  The library constructor must 
+
+  This library does not contain any functions or macros.  It simply exports a global
+  pointer to the DXE Services Table as defined in the Platform Initialization Driver
+  Execution Environment Core Interface Specification.  The library constructor must
   initialize this global pointer to the DX Services Table, so it is available at the
-  module's entry point.  Since there is overhead in looking up the pointer to the DXE 
-  Services Table, only those modules that actually require access to the DXE Services 
-  Table should use this library.  This will typically be DXE Drivers that require GCD 
+  module's entry point.  Since there is overhead in looking up the pointer to the DXE
+  Services Table, only those modules that actually require access to the DXE Services
+  Table should use this library.  This will typically be DXE Drivers that require GCD
   or Dispatcher services.
-   
-Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
 
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/Library/ExtendedSalLib.h b/MdePkg/Include/Library/ExtendedSalLib.h
deleted file mode 100644
index 710675ff8eeb..000000000000
--- a/MdePkg/Include/Library/ExtendedSalLib.h
+++ /dev/null
@@ -1,494 +0,0 @@
-/** @file
-  Library class definition of Extended SAL Library.
-
-Copyright (c) 2007 - 2011, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef _EXTENDED_SAL_LIB_H__
-#define _EXTENDED_SAL_LIB_H__
-
-#include <IndustryStandard/Sal.h>
-
-/**
-  Register ESAL Class and its associated global.
-  
-  This function Registers one or more Extended SAL services in a given
-  class along with the associated global context.
-  This function is only available prior to ExitBootServices().
-
-  @param  ClassGuidLo          GUID of function class, lower 64-bits
-  @param  ClassGuidHi          GUID of function class, upper 64-bits
-  @param  ModuleGlobal         Module global for Function.
-  @param  ...                  List of Function/FunctionId pairs, ended by NULL
-
-  @retval EFI_SUCCESS          The Extended SAL services were registered.
-  @retval EFI_UNSUPPORTED      This function was called after ExitBootServices().
-  @retval EFI_OUT_OF_RESOURCES There are not enough resources available to register one or more of the specified services.
-  @retval Other                ClassGuid could not be installed onto a new handle.  
-
-**/
-EFI_STATUS
-EFIAPI
-RegisterEsalClass (
-  IN  CONST UINT64    ClassGuidLo,
-  IN  CONST UINT64    ClassGuidHi,
-  IN  VOID            *ModuleGlobal,  OPTIONAL
-  ...
-  );
-
-/**
-  Calls an Extended SAL Class service that was previously registered with RegisterEsalClass().
-  
-  This function calls an Extended SAL Class service that was previously registered with RegisterEsalClass().
-
-  @param  ClassGuidLo    GUID of function, lower 64-bits
-  @param  ClassGuidHi    GUID of function, upper 64-bits
-  @param  FunctionId     Function in ClassGuid to call
-  @param  Arg2           Argument 2 ClassGuid/FunctionId defined
-  @param  Arg3           Argument 3 ClassGuid/FunctionId defined
-  @param  Arg4           Argument 4 ClassGuid/FunctionId defined
-  @param  Arg5           Argument 5 ClassGuid/FunctionId defined
-  @param  Arg6           Argument 6 ClassGuid/FunctionId defined
-  @param  Arg7           Argument 7 ClassGuid/FunctionId defined
-  @param  Arg8           Argument 8 ClassGuid/FunctionId defined
-  
-  @retval EFI_SAL_ERROR  The address of ExtendedSalProc() can not be determined
-                         for the current CPU execution mode.
-  @retval Other          See the return status from ExtendedSalProc() in the
-                         EXTENDED_SAL_BOOT_SERVICE_PROTOCOL.  
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalCall (
-  IN UINT64  ClassGuidLo,
-  IN UINT64  ClassGuidHi,
-  IN UINT64  FunctionId,
-  IN UINT64  Arg2,
-  IN UINT64  Arg3,
-  IN UINT64  Arg4,
-  IN UINT64  Arg5,
-  IN UINT64  Arg6,
-  IN UINT64  Arg7,
-  IN UINT64  Arg8
-  );
-
-/**
-  Wrapper for the EsalStallFunctionId service of Extended SAL Stall Services Class.
-  
-  This function is a wrapper for the EsalStallFunctionId service of Extended SAL
-  Stall Services Class. See EsalStallFunctionId of Extended SAL Specification.
-
-  @param  Microseconds                  The number of microseconds to delay.
-
-  @retval EFI_SAL_SUCCESS               Call completed without error.
-  @retval EFI_SAL_INVALID_ARGUMENT      Invalid argument.
-  @retval EFI_SAL_VIRTUAL_ADDRESS_ERROR Virtual address not registered
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalStall (
-  IN UINTN  Microseconds
-  );
-
-/**
-  Wrapper for the EsalSetNewPalEntryFunctionId service of Extended SAL PAL Services Services Class.
-  
-  This function is a wrapper for the EsalSetNewPalEntryFunctionId service of Extended SAL
-  PAL Services Services Class. See EsalSetNewPalEntryFunctionId of Extended SAL Specification.
-
-  @param  PhysicalAddress                If TRUE, then PalEntryPoint is a physical address.
-                                         If FALSE, then PalEntryPoint is a virtual address.
-  @param  PalEntryPoint                  The PAL Entry Point being set.
-
-  @retval EFI_SAL_SUCCESS                The PAL Entry Point was set.
-  @retval EFI_SAL_VIRTUAL_ADDRESS_ERROR  This function was called in virtual mode before
-                                         virtual mappings for the specified Extended SAL
-                                         Procedure are available.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalSetNewPalEntry (
-  IN BOOLEAN  PhysicalAddress,
-  IN UINT64   PalEntryPoint
-  );
-
-/**
-  Wrapper for the EsalGetNewPalEntryFunctionId service of Extended SAL PAL Services Services Class.
-  
-  This function is a wrapper for the EsalGetNewPalEntryFunctionId service of Extended SAL
-  PAL Services Services Class. See EsalGetNewPalEntryFunctionId of Extended SAL Specification.
-
-  @param  PhysicalAddress                If TRUE, then PalEntryPoint is a physical address.
-                                         If FALSE, then PalEntryPoint is a virtual address.
-
-  @retval EFI_SAL_SUCCESS                The PAL Entry Point was retrieved and returned in
-                                         SAL_RETURN_REGS.r9.
-  @retval EFI_SAL_VIRTUAL_ADDRESS_ERROR  This function was called in virtual mode before
-                                         virtual mappings for the specified Extended SAL
-                                         Procedure are available.
-  @return r9                             PAL entry point retrieved.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalGetNewPalEntry (
-  IN BOOLEAN  PhysicalAddress
-  );
-
-/**
-  Wrapper for the EsalGetStateBufferFunctionId service of Extended SAL MCA Log Services Class.
-  
-  This function is a wrapper for the EsalGetStateBufferFunctionId service of Extended SAL
-  MCA Log Services Class. See EsalGetStateBufferFunctionId of Extended SAL Specification.
-
-  @param  McaType               See type parameter of SAL Procedure SAL_GET_STATE_INFO.
-  @param  McaBuffer             A pointer to the base address of the returned buffer.
-                                Copied from SAL_RETURN_REGS.r9.
-  @param  BufferSize            A pointer to the size, in bytes, of the returned buffer.
-                                Copied from SAL_RETURN_REGS.r10.
-
-  @retval EFI_SAL_SUCCESS       The memory buffer to store error records was returned in r9 and r10.
-  @retval EFI_OUT_OF_RESOURCES  A memory buffer for string error records in not available
-  @return r9                    Base address of the returned buffer
-  @return r10                   Size of the returned buffer in bytes
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalGetStateBuffer (
-  IN  UINT64  McaType,
-  OUT UINT8   **McaBuffer,
-  OUT UINTN   *BufferSize
-  );
-
-/**
-  Wrapper for the EsalSaveStateBufferFunctionId service of Extended SAL MCA Log Services Class.
-  
-  This function is a wrapper for the EsalSaveStateBufferFunctionId service of Extended SAL
-  MCA Log Services Class. See EsalSaveStateBufferFunctionId of Extended SAL Specification.
-
-  @param  McaType      See type parameter of SAL Procedure SAL_GET_STATE_INFO.
-
-  @retval EFI_SUCCESS  The memory buffer containing the error record was written to nonvolatile storage.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalSaveStateBuffer (
-  IN  UINT64  McaType
-  );
-
-/**
-  Wrapper for the EsalGetVectorsFunctionId service of Extended SAL Base Services Class.
-  
-  This function is a wrapper for the EsalGetVectorsFunctionId service of Extended SAL
-  Base Services Class. See EsalGetVectorsFunctionId of Extended SAL Specification.
-
-  @param  VectorType               The vector type to retrieve.
-                                   0 - MCA, 1 - BSP INIT, 2 - BOOT_RENDEZ, 3 - AP INIT.
-
-  @retval EFI_SAL_SUCCESS          Call completed without error.
-  @retval EFI_SAL_INVALID_ARGUMENT Invalid argument.
-  @retval EFI_SAL_NO_INFORMATION   The requested vector has not been registered
-                                   with the SAL Procedure SAL_SET_VECTORS.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalGetVectors (
-  IN  UINT64  VectorType
-  );
-
-/**
-  Wrapper for the EsalMcGetParamsFunctionId service of Extended SAL Base Services Class.
-  
-  This function is a wrapper for the EsalMcGetParamsFunctionId service of Extended SAL
-  Base Services Class. See EsalMcGetParamsFunctionId of Extended SAL Specification.
-
-  @param  ParamInfoType            The parameter type to retrieve.
-                                   1 - rendezvous interrupt
-                                   2 - wake up
-                                   3 - Corrected Platform Error Vector.
-
-  @retval EFI_SAL_SUCCESS          Call completed without error.
-  @retval EFI_SAL_INVALID_ARGUMENT Invalid argument.
-  @retval EFI_SAL_NO_INFORMATION   The requested vector has not been registered
-                                   with the SAL Procedure SAL_MC_SET_PARAMS.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalMcGetParams (
-  IN  UINT64  ParamInfoType
-  );
-
-/**
-  Wrapper for the EsalMcGetParamsFunctionId service of Extended SAL Base Services Class.
-  
-  This function is a wrapper for the EsalMcGetParamsFunctionId service of Extended SAL
-  Base Services Class. See EsalMcGetParamsFunctionId of Extended SAL Specification.
-
-  @retval EFI_SAL_SUCCESS          Call completed without error.
-  @retval EFI_SAL_NO_INFORMATION   The requested vector has not been registered
-                                   with the SAL Procedure SAL_MC_SET_PARAMS.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalMcGetMcParams (
-  VOID
-  );
-
-/**
-  Wrapper for the EsalGetMcCheckinFlagsFunctionId service of Extended SAL Base Services Class.
-  
-  This function is a wrapper for the EsalGetMcCheckinFlagsFunctionId service of Extended SAL
-  Base Services Class. See EsalGetMcCheckinFlagsFunctionId of Extended SAL Specification.
-
-  @param  CpuIndex         The index of the CPU of set of enabled CPUs to check.
-
-  @retval EFI_SAL_SUCCESS  The checkin status of the requested CPU was returned.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalGetMcCheckinFlags (
-  IN  UINT64  CpuIndex
-  );
-
-/**
-  Wrapper for the EsalAddCpuDataFunctionId service of Extended SAL MP Services Class.
-  
-  This function is a wrapper for the EsalAddCpuDataFunctionId service of Extended SAL
-  MP Services Class. See EsalAddCpuDataFunctionId of Extended SAL Specification.
-
-  @param  CpuGlobalId                 The Global ID for the CPU being added.
-  @param  Enabled                     The enable flag for the CPU being added.
-                                      TRUE means the CPU is enabled.
-                                      FALSE means the CPU is disabled.
-  @param  PalCompatibility            The PAL Compatibility value for the CPU being added.
-
-  @retval EFI_SAL_SUCCESS             The CPU was added to the database.
-  @retval EFI_SAL_NOT_ENOUGH_SCRATCH  There are not enough resource available to add the CPU.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalAddCpuData (
-  IN UINT64   CpuGlobalId,
-  IN BOOLEAN  Enabled,
-  IN UINT64   PalCompatibility
-  );
-
-/**
-  Wrapper for the EsalRemoveCpuDataFunctionId service of Extended SAL MP Services Class.
-  
-  This function is a wrapper for the EsalRemoveCpuDataFunctionId service of Extended SAL
-  MP Services Class. See EsalRemoveCpuDataFunctionId of Extended SAL Specification.
-
-  @param  CpuGlobalId             The Global ID for the CPU being removed.
-
-  @retval EFI_SAL_SUCCESS         The CPU was removed from the database.
-  @retval EFI_SAL_NO_INFORMATION  The specified CPU is not in the database.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalRemoveCpuData (
-  IN UINT64  CpuGlobalId
-  );
-
-/**
-  Wrapper for the EsalModifyCpuDataFunctionId service of Extended SAL MP Services Class.
-  
-  This function is a wrapper for the EsalModifyCpuDataFunctionId service of Extended SAL
-  MP Services Class. See EsalModifyCpuDataFunctionId of Extended SAL Specification.
-
-  @param  CpuGlobalId             The Global ID for the CPU being modified.
-  @param  Enabled                 The enable flag for the CPU being modified.
-                                  TRUE means the CPU is enabled.
-                                  FALSE means the CPU is disabled.
-  @param  PalCompatibility        The PAL Compatibility value for the CPU being modified.
-
-  @retval EFI_SAL_SUCCESS         The CPU database was updated.
-  @retval EFI_SAL_NO_INFORMATION  The specified CPU is not in the database.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalModifyCpuData (
-  IN UINT64   CpuGlobalId,
-  IN BOOLEAN  Enabled,
-  IN UINT64   PalCompatibility
-  );
-
-/**
-  Wrapper for the EsalGetCpuDataByIdFunctionId service of Extended SAL MP Services Class.
-  
-  This function is a wrapper for the EsalGetCpuDataByIdFunctionId service of Extended SAL
-  MP Services Class. See EsalGetCpuDataByIdFunctionId of Extended SAL Specification.
-
-  @param  CpuGlobalId             The Global ID for the CPU being looked up.
-  @param  IndexByEnabledCpu       If TRUE, then the index of set of enabled CPUs of database is returned.
-                                  If FALSE, then the index of set of all CPUs of database is returned.
-
-  @retval EFI_SAL_SUCCESS         The information on the specified CPU was returned.
-  @retval EFI_SAL_NO_INFORMATION  The specified CPU is not in the database.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalGetCpuDataById (
-  IN UINT64   CpuGlobalId,
-  IN BOOLEAN  IndexByEnabledCpu
-  );
-
-/**
-  Wrapper for the EsalGetCpuDataByIndexFunctionId service of Extended SAL MP Services Class.
-  
-  This function is a wrapper for the EsalGetCpuDataByIndexFunctionId service of Extended SAL
-  MP Services Class. See EsalGetCpuDataByIndexFunctionId of Extended SAL Specification.
-
-  @param  Index                   The Global ID for the CPU being modified.
-  @param  IndexByEnabledCpu       If TRUE, then the index of set of enabled CPUs of database is returned.
-                                  If FALSE, then the index of set of all CPUs of database is returned.
-
-  @retval EFI_SAL_SUCCESS         The information on the specified CPU was returned.
-  @retval EFI_SAL_NO_INFORMATION  The specified CPU is not in the database.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalGetCpuDataByIndex (
-  IN UINT64   Index,
-  IN BOOLEAN  IndexByEnabledCpu
-  );
-
-/**
-  Wrapper for the EsalWhoAmIFunctionId service of Extended SAL MP Services Class.
-  
-  This function is a wrapper for the EsalWhoAmIFunctionId service of Extended SAL
-  MP Services Class. See EsalWhoAmIFunctionId of Extended SAL Specification.
-
-  @param  IndexByEnabledCpu       If TRUE, then the index of set of enabled CPUs of database is returned.
-                                  If FALSE, then the index of set of all CPUs of database is returned.
-
-  @retval EFI_SAL_SUCCESS         The Global ID for the calling CPU was returned.
-  @retval EFI_SAL_NO_INFORMATION  The calling CPU is not in the database.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalWhoAmI (
-  IN BOOLEAN  IndexByEnabledCpu
-  );
-
-/**
-  Wrapper for the EsalNumProcessors service of Extended SAL MP Services Class.
-  
-  This function is a wrapper for the EsalNumProcessors service of Extended SAL
-  MP Services Class. See EsalNumProcessors of Extended SAL Specification.
-
-  @retval EFI_SAL_SUCCESS    The information on the number of CPUs in the platform
-                             was returned.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalNumProcessors (
-  VOID
-  );
-
-/**
-  Wrapper for the EsalSetMinStateFnctionId service of Extended SAL MP Services Class.
-  
-  This function is a wrapper for the EsalSetMinStateFnctionId service of Extended SAL
-  MP Services Class. See EsalSetMinStateFnctionId of Extended SAL Specification.
-
-  @param  CpuGlobalId              The Global ID for the CPU whose MINSTATE pointer is being set.
-  @param  MinStatePointer          The physical address of the MINSTATE buffer for the CPU
-                                   specified by CpuGlobalId.
-
-  @retval EFI_SAL_SUCCESS          The MINSTATE pointer was set for the specified CPU.
-  @retval EFI_SAL_NO_INFORMATION   The specified CPU is not in the database.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalSetMinState (
-  IN UINT64                CpuGlobalId,
-  IN EFI_PHYSICAL_ADDRESS  MinStatePointer
-  );
-
-/**
-  Wrapper for the EsalGetMinStateFunctionId service of Extended SAL MP Services Class.
-  
-  This function is a wrapper for the EsalGetMinStateFunctionId service of Extended SAL
-  MP Services Class. See EsalGetMinStateFunctionId of Extended SAL Specification.
-
-  @param  CpuGlobalId            The Global ID for the CPU whose MINSTATE pointer is being retrieved.
-
-  @retval EFI_SAL_SUCCESS        The MINSTATE pointer for the specified CPU was retrieved.
-  @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the database.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalGetMinState (
-  IN UINT64  CpuGlobalId
-  );
-
-/**
-  Wrapper for the EsalMcsGetStateInfoFunctionId service of Extended SAL MCA Services Class.
-  
-  This function is a wrapper for the EsalMcsGetStateInfoFunctionId service of Extended SAL
-  MCA Services Class. See EsalMcsGetStateInfoFunctionId of Extended SAL Specification.
-
-  @param  CpuGlobalId               The Global ID for the CPU whose MCA state buffer is being retrieved.
-  @param  StateBufferPointer        A pointer to the returned MCA state buffer.
-  @param  RequiredStateBufferSize   A pointer to the size, in bytes, of the returned MCA state buffer.
-
-  @retval EFI_SUCCESS               MINSTATE successfully got and size calculated.
-  @retval EFI_SAL_NO_INFORMATION    Fail to get MINSTATE.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalMcaGetStateInfo (
-  IN  UINT64                CpuGlobalId,
-  OUT EFI_PHYSICAL_ADDRESS  *StateBufferPointer,
-  OUT UINT64                *RequiredStateBufferSize
-  );
-
-/**
-  Wrapper for the EsalMcaRegisterCpuFunctionId service of Extended SAL MCA Services Class.
-  
-  This function is a wrapper for the EsalMcaRegisterCpuFunctionId service of Extended SAL
-  MCA Services Class. See EsalMcaRegisterCpuFunctionId of Extended SAL Specification.
-
-  @param  CpuGlobalId              The Global ID for the CPU whose MCA state buffer is being set.
-  @param  StateBufferPointer       A pointer to the MCA state buffer.
-
-  @retval EFI_SAL_NO_INFORMATION   Cannot get the processor info with the CpuId
-  @retval EFI_SUCCESS              Save the processor's state info successfully
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalMcaRegisterCpu (
-  IN UINT64                CpuGlobalId,
-  IN EFI_PHYSICAL_ADDRESS  StateBufferPointer
-  );
-
-#endif
diff --git a/MdePkg/Include/Library/ExtractGuidedSectionLib.h b/MdePkg/Include/Library/ExtractGuidedSectionLib.h
index 73dfed2e292f..95c7670ada66 100644
--- a/MdePkg/Include/Library/ExtractGuidedSectionLib.h
+++ b/MdePkg/Include/Library/ExtractGuidedSectionLib.h
@@ -1,23 +1,17 @@
 /** @file
-  This library provides common functions to process the different guided section data. 
-  
-  This library provides functions to process GUIDed sections of FFS files.  Handlers may 
-  be registered to decode GUIDed sections of FFS files.  Services are provided to determine 
-  the set of supported section GUIDs, collection information about a specific GUIDed section, 
-  and decode a specific GUIDed section. 
-  
-  A library instance that produces this library class may be used to produce a 
-  EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI or a EFI_GUIDED_SECTION_EXTRACTION_PROTOCOL 
-  providing a simple method to extend the number of GUIDed sections types a platform supports.
+  This library provides common functions to process the different guided section data.
+
+  This library provides functions to process GUIDed sections of FFS files.  Handlers may
+  be registered to decode GUIDed sections of FFS files.  Services are provided to determine
+  the set of supported section GUIDs, collection information about a specific GUIDed section,
+  and decode a specific GUIDed section.
 
-Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
+  A library instance that produces this library class may be used to produce a
+  EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI or a EFI_GUIDED_SECTION_EXTRACTION_PROTOCOL
+  providing a simple method to extend the number of GUIDed sections types a platform supports.
 
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 #ifndef __EXTRACT_GUIDED_SECTION_H__
@@ -27,16 +21,16 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   Examines a GUIDed section and returns the size of the decoded buffer and the
   size of an optional scratch buffer required to actually decode the data in a GUIDed section.
 
-  Examines a GUIDed section specified by InputSection.  
+  Examines a GUIDed section specified by InputSection.
   If GUID for InputSection does not match the GUID that this handler supports,
-  then RETURN_UNSUPPORTED is returned.  
+  then RETURN_UNSUPPORTED is returned.
   If the required information can not be retrieved from InputSection,
   then RETURN_INVALID_PARAMETER is returned.
   If the GUID of InputSection does match the GUID that this handler supports,
   then the size required to hold the decoded buffer is returned in OututBufferSize,
   the size of an optional scratch buffer is returned in ScratchSize, and the Attributes field
   from EFI_GUID_DEFINED_SECTION header of InputSection is returned in SectionAttribute.
-  
+
   If InputSection is NULL, then ASSERT().
   If OutputBufferSize is NULL, then ASSERT().
   If ScratchBufferSize is NULL, then ASSERT().
@@ -67,16 +61,16 @@ RETURN_STATUS
 
 /**
   Decodes a GUIDed section into a caller allocated output buffer.
-  
-  Decodes the GUIDed section specified by InputSection.  
-  If GUID for InputSection does not match the GUID that this handler supports, then RETURN_UNSUPPORTED is returned.  
+
+  Decodes the GUIDed section specified by InputSection.
+  If GUID for InputSection does not match the GUID that this handler supports, then RETURN_UNSUPPORTED is returned.
   If the data in InputSection can not be decoded, then RETURN_INVALID_PARAMETER is returned.
   If the GUID of InputSection does match the GUID that this handler supports, then InputSection
   is decoded into the buffer specified by OutputBuffer and the authentication status of this
   decode operation is returned in AuthenticationStatus.  If the decoded buffer is identical to the
   data in InputSection, then OutputBuffer is set to point at the data in InputSection.  Otherwise,
   the decoded data will be placed in caller allocated buffer specified by OutputBuffer.
-  
+
   If InputSection is NULL, then ASSERT().
   If OutputBuffer is NULL, then ASSERT().
   If ScratchBuffer is NULL and this decode operation requires a scratch buffer, then ASSERT().
@@ -84,10 +78,10 @@ RETURN_STATUS
 
 
   @param[in]  InputSection  A pointer to a GUIDed section of an FFS formatted file.
-  @param[out] OutputBuffer  A pointer to a buffer that contains the result of a decode operation. 
+  @param[out] OutputBuffer  A pointer to a buffer that contains the result of a decode operation.
   @param[out] ScratchBuffer A caller allocated buffer that may be required by this function
-                            as a scratch buffer to perform the decode operation. 
-  @param[out] AuthenticationStatus 
+                            as a scratch buffer to perform the decode operation.
+  @param[out] AuthenticationStatus
                             A pointer to the authentication status of the decoded output buffer.
                             See the definition of authentication status in the EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI
                             section of the PI Specification. EFI_AUTH_STATUS_PLATFORM_OVERRIDE must
@@ -114,7 +108,7 @@ RETURN_STATUS
   Registers the handlers specified by GetInfoHandler and DecodeHandler with the GUID specified by SectionGuid.
   If the GUID value specified by SectionGuid has already been registered, then return RETURN_ALREADY_STARTED.
   If there are not enough resources available to register the handlers  then RETURN_OUT_OF_RESOURCES is returned.
-  
+
   If SectionGuid is NULL, then ASSERT().
   If GetInfoHandler is NULL, then ASSERT().
   If DecodeHandler is NULL, then ASSERT().
@@ -125,7 +119,7 @@ RETURN_STATUS
                              size of the decoded buffer and the size of an optional scratch buffer
                              required to actually decode the data in a GUIDed section.
   @param[in]  DecodeHandler  Pointer to a function that decodes a GUIDed section into a caller
-                             allocated output buffer. 
+                             allocated output buffer.
 
   @retval  RETURN_SUCCESS           The handlers were registered.
   @retval  RETURN_OUT_OF_RESOURCES  There are not enough resources available to register the handlers.
@@ -144,7 +138,7 @@ ExtractGuidedSectionRegisterHandlers (
 
   Sets ExtractHandlerGuidTable so it points at a callee allocated array of registered GUIDs.
   The total number of GUIDs in the array are returned. Since the array of GUIDs is callee allocated
-  and caller must treat this array of GUIDs as read-only data. 
+  and caller must treat this array of GUIDs as read-only data.
   If ExtractHandlerGuidTable is NULL, then ASSERT().
 
   @param[out]  ExtractHandlerGuidTable  A pointer to the array of GUIDs that have been registered through
@@ -165,14 +159,14 @@ ExtractGuidedSectionGetGuidList (
   The selected handler is used to retrieve and return the size of the decoded buffer and the size of an
   optional scratch buffer required to actually decode the data in a GUIDed section.
 
-  Examines a GUIDed section specified by InputSection.  
+  Examines a GUIDed section specified by InputSection.
   If GUID for InputSection does not match any of the GUIDs registered through ExtractGuidedSectionRegisterHandlers(),
-  then RETURN_UNSUPPORTED is returned.  
-  If the GUID of InputSection does match the GUID that this handler supports, then the the associated handler 
+  then RETURN_UNSUPPORTED is returned.
+  If the GUID of InputSection does match the GUID that this handler supports, then the the associated handler
   of type EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER that was registered with ExtractGuidedSectionRegisterHandlers()
   is used to retrieve the OututBufferSize, ScratchSize, and Attributes values. The return status from the handler of
   type EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER is returned.
-  
+
   If InputSection is NULL, then ASSERT().
   If OutputBufferSize is NULL, then ASSERT().
   If ScratchBufferSize is NULL, then ASSERT().
@@ -199,7 +193,7 @@ ExtractGuidedSectionGetInfo (
   IN  CONST VOID    *InputSection,
   OUT       UINT32  *OutputBufferSize,
   OUT       UINT32  *ScratchBufferSize,
-  OUT       UINT16  *SectionAttribute   
+  OUT       UINT16  *SectionAttribute
   );
 
 /**
@@ -208,26 +202,26 @@ ExtractGuidedSectionGetInfo (
   The selected handler is used to decode the data in a GUIDed section and return the result in a caller
   allocated output buffer.
 
-  Decodes the GUIDed section specified by InputSection.  
+  Decodes the GUIDed section specified by InputSection.
   If GUID for InputSection does not match any of the GUIDs registered through ExtractGuidedSectionRegisterHandlers(),
-  then RETURN_UNSUPPORTED is returned.  
+  then RETURN_UNSUPPORTED is returned.
   If the GUID of InputSection does match the GUID that this handler supports, then the the associated handler
   of type EXTRACT_GUIDED_SECTION_DECODE_HANDLER that was registered with ExtractGuidedSectionRegisterHandlers()
   is used to decode InputSection into the buffer specified by OutputBuffer and the authentication status of this
   decode operation is returned in AuthenticationStatus.  If the decoded buffer is identical to the data in InputSection,
   then OutputBuffer is set to point at the data in InputSection.  Otherwise, the decoded data will be placed in caller
   allocated buffer specified by OutputBuffer.    This function is responsible for computing the  EFI_AUTH_STATUS_PLATFORM_OVERRIDE
-  bit of in AuthenticationStatus.  The return status from the handler of type EXTRACT_GUIDED_SECTION_DECODE_HANDLER is returned. 
-   
+  bit of in AuthenticationStatus.  The return status from the handler of type EXTRACT_GUIDED_SECTION_DECODE_HANDLER is returned.
+
   If InputSection is NULL, then ASSERT().
   If OutputBuffer is NULL, then ASSERT().
   If ScratchBuffer is NULL and this decode operation requires a scratch buffer, then ASSERT().
-  If AuthenticationStatus is NULL, then ASSERT().  
+  If AuthenticationStatus is NULL, then ASSERT().
 
   @param[in]  InputSection   A pointer to a GUIDed section of an FFS formatted file.
-  @param[out] OutputBuffer   A pointer to a buffer that contains the result of a decode operation. 
-  @param[in]  ScratchBuffer  A caller allocated buffer that may be required by this function as a scratch buffer to perform the decode operation. 
-  @param[out] AuthenticationStatus 
+  @param[out] OutputBuffer   A pointer to a buffer that contains the result of a decode operation.
+  @param[in]  ScratchBuffer  A caller allocated buffer that may be required by this function as a scratch buffer to perform the decode operation.
+  @param[out] AuthenticationStatus
                              A pointer to the authentication status of the decoded output buffer. See the definition
                              of authentication status in the EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI section of the PI
                              Specification.
@@ -243,27 +237,27 @@ ExtractGuidedSectionDecode (
   IN  CONST VOID    *InputSection,
   OUT       VOID    **OutputBuffer,
   IN        VOID    *ScratchBuffer,        OPTIONAL
-  OUT       UINT32  *AuthenticationStatus  
+  OUT       UINT32  *AuthenticationStatus
   );
 
 /**
-  Retrieves handlers of type EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER and 
+  Retrieves handlers of type EXTRACT_GUIDED_SECTION_GET_INFO_HANDLER and
   EXTRACT_GUIDED_SECTION_DECODE_HANDLER for a specific GUID section type.
-  
-  Retrieves the handlers associated with SectionGuid and returns them in 
+
+  Retrieves the handlers associated with SectionGuid and returns them in
   GetInfoHandler and DecodeHandler.
 
-  If the GUID value specified by SectionGuid has not been registered, then 
+  If the GUID value specified by SectionGuid has not been registered, then
   return RETURN_NOT_FOUND.
-  
+
   If SectionGuid is NULL, then ASSERT().
 
-  @param[in]  SectionGuid    A pointer to the GUID associated with the handlersof the GUIDed 
+  @param[in]  SectionGuid    A pointer to the GUID associated with the handlersof the GUIDed
                              section type being retrieved.
-  @param[out] GetInfoHandler Pointer to a function that examines a GUIDed section and returns 
-                             the size of the decoded buffer and the size of an optional scratch 
-                             buffer required to actually decode the data in a GUIDed section.  
-                             This is an optional parameter that may be NULL. If it is NULL, then 
+  @param[out] GetInfoHandler Pointer to a function that examines a GUIDed section and returns
+                             the size of the decoded buffer and the size of an optional scratch
+                             buffer required to actually decode the data in a GUIDed section.
+                             This is an optional parameter that may be NULL. If it is NULL, then
                              the previously registered handler is not returned.
   @param[out] DecodeHandler  Pointer to a function that decodes a GUIDed section into a caller
                              allocated output buffer. This is an optional parameter that may be NULL.
diff --git a/MdePkg/Include/Library/FileHandleLib.h b/MdePkg/Include/Library/FileHandleLib.h
index cbafa4aca82c..c473c668ba94 100644
--- a/MdePkg/Include/Library/FileHandleLib.h
+++ b/MdePkg/Include/Library/FileHandleLib.h
@@ -1,14 +1,8 @@
 /** @file
   Provides interface to EFI_FILE_HANDLE functionality.
 
-  Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -249,8 +243,8 @@ FileHandleFlush (
   @param[in] DirHandle          Handle to open file.
 
   @retval EFI_SUCCESS           DirHandle is a directory.
-  @retval EFI_INVALID_PARAMETER DirHandle is NULL. 
-                                The file information returns from FileHandleGetInfo is NULL. 
+  @retval EFI_INVALID_PARAMETER DirHandle is NULL.
+                                The file information returns from FileHandleGetInfo is NULL.
   @retval EFI_NOT_FOUND         DirHandle is not a directory.
 **/
 EFI_STATUS
@@ -357,8 +351,8 @@ FileHandleSetSize (
 
 /**
   Function to get a full filename given a EFI_FILE_HANDLE somewhere lower on the
-  directory 'stack'. If the file is a directory, then append the '\' char at the 
-  end of name string. If it's not a directory, then the last '\' should not be 
+  directory 'stack'. If the file is a directory, then append the '\' char at the
+  end of name string. If it's not a directory, then the last '\' should not be
   added.
 
   @param[in] Handle             Handle to the Directory or File to create path to.
@@ -439,11 +433,11 @@ FileHandleReturnLine(
 
 /**
   Function to write a line of text to a file.
-  
-  If the file is a Unicode file (with UNICODE file tag) then write the unicode 
+
+  If the file is a Unicode file (with UNICODE file tag) then write the unicode
   text.
   If the file is an ASCII file then write the ASCII text.
-  If the size of file is zero (without file tag at the beginning) then write 
+  If the size of file is zero (without file tag at the beginning) then write
   ASCII text as default.
 
   @param[in]     Handle         FileHandle to write to.
@@ -453,7 +447,7 @@ FileHandleReturnLine(
   @retval  EFI_SUCCESS            The data was written.
                                   Buffer is NULL.
   @retval  EFI_INVALID_PARAMETER  Handle is NULL.
-  @retval  EFI_OUT_OF_RESOURCES   Unable to allocate temporary space for ASCII 
+  @retval  EFI_OUT_OF_RESOURCES   Unable to allocate temporary space for ASCII
                                   string due to out of resources.
 
   @sa FileHandleWrite
diff --git a/MdePkg/Include/Library/HobLib.h b/MdePkg/Include/Library/HobLib.h
index 292321cd3d72..b1adb5276f96 100644
--- a/MdePkg/Include/Library/HobLib.h
+++ b/MdePkg/Include/Library/HobLib.h
@@ -6,16 +6,10 @@
   defined in the PI Specification.
   A HOB is a Hand-Off Block, defined in the Framework architecture, that
   allows the PEI phase to pass information to the DXE phase. HOBs are position
-  independent and can be relocated easily to different memory memory locations.
+  independent and can be relocated easily to different memory locations.
 
-Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -190,7 +184,7 @@ BuildModuleHob (
   This function builds a HOB that describes a chunk of system memory.
   It can only be invoked during PEI phase;
   for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase.
-  
+
   If there is no additional space for HOB creation, then ASSERT().
 
   @param  ResourceType        The type of resource described by this HOB.
@@ -343,6 +337,38 @@ BuildFv2Hob (
   );
 
 /**
+  Builds a EFI_HOB_TYPE_FV3 HOB.
+
+  This function builds a EFI_HOB_TYPE_FV3 HOB.
+  It can only be invoked during PEI phase;
+  for DXE phase, it will ASSERT() since PEI HOB is read-only for DXE phase.
+
+  If there is no additional space for HOB creation, then ASSERT().
+  If the FvImage buffer is not at its required alignment, then ASSERT().
+
+  @param BaseAddress            The base address of the Firmware Volume.
+  @param Length                 The size of the Firmware Volume in bytes.
+  @param AuthenticationStatus   The authentication status.
+  @param ExtractedFv            TRUE if the FV was extracted as a file within
+                                another firmware volume. FALSE otherwise.
+  @param FvName                 The name of the Firmware Volume.
+                                Valid only if IsExtractedFv is TRUE.
+  @param FileName               The name of the file.
+                                Valid only if IsExtractedFv is TRUE.
+
+**/
+VOID
+EFIAPI
+BuildFv3Hob (
+  IN          EFI_PHYSICAL_ADDRESS        BaseAddress,
+  IN          UINT64                      Length,
+  IN          UINT32                      AuthenticationStatus,
+  IN          BOOLEAN                     ExtractedFv,
+  IN CONST    EFI_GUID                    *FvName, OPTIONAL
+  IN CONST    EFI_GUID                    *FileName OPTIONAL
+  );
+
+/**
   Builds a Capsule Volume HOB.
 
   This function builds a Capsule Volume HOB.
diff --git a/MdePkg/Include/Library/HstiLib.h b/MdePkg/Include/Library/HstiLib.h
index 2ae87f67d19e..83d9bc46e330 100644
--- a/MdePkg/Include/Library/HstiLib.h
+++ b/MdePkg/Include/Library/HstiLib.h
@@ -2,13 +2,7 @@
   Provides services to create, get and update HSTI table in AIP protocol.
 
   Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/Library/IoLib.h b/MdePkg/Include/Library/IoLib.h
index 7c27f1cf6531..d0ffe98ecb14 100644
--- a/MdePkg/Include/Library/IoLib.h
+++ b/MdePkg/Include/Library/IoLib.h
@@ -1,16 +1,10 @@
 /** @file
   Provide services to access I/O Ports and MMIO registers.
 
-Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
 
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -20,14 +14,14 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 /**
   Macro that converts PCI Segment and I/O Port to an address that can be
   passed to the I/O Library functions.
-  
-  Computes an address that is compatible with the I/O Library functions.  
-  The unused upper bits of Segment, and Port are stripped prior to the 
+
+  Computes an address that is compatible with the I/O Library functions.
+  The unused upper bits of Segment, and Port are stripped prior to the
   generation of the address.
-  
+
   @param  Segment   PCI Segment number.  Range 0..65535.
   @param  Port      I/O Port number.  Range 0..65535.
-  
+
   @return An address that the I/o Library functions need.
 
 **/
@@ -178,7 +172,7 @@ IoAnd8 (
   );
 
 /**
-  Reads an 8-bit I/O port, performs a bitwise AND followed by a bitwise 
+  Reads an 8-bit I/O port, performs a bitwise AND followed by a bitwise
   OR, and writes the result back to the 8-bit I/O port.
 
   Reads the 8-bit I/O port specified by Port, performs a bitwise AND between
@@ -238,7 +232,7 @@ IoBitFieldRead8 (
 
   Writes Value to the bit field of the I/O register. The bit field is specified
   by the StartBit and the EndBit. All other bits in the destination I/O
-  register are preserved. The value written to the I/O port is returned. 
+  register are preserved. The value written to the I/O port is returned.
 
   If 8-bit I/O port operations are not supported, then ASSERT().
   If StartBit is greater than 7, then ASSERT().
@@ -405,7 +399,7 @@ IoRead16 (
 
   If 16-bit I/O port operations are not supported, then ASSERT().
   If Port is not aligned on a 16-bit boundary, then ASSERT().
-  
+
   @param  Port  The I/O port to write.
   @param  Value The value to write to the I/O port.
 
@@ -507,7 +501,7 @@ IoOr16 (
 
   If 16-bit I/O port operations are not supported, then ASSERT().
   If Port is not aligned on a 16-bit boundary, then ASSERT().
-  
+
   @param  Port    The I/O port to write.
   @param  AndData The value to AND with the read value from the I/O port.
 
@@ -522,7 +516,7 @@ IoAnd16 (
   );
 
 /**
-  Reads a 16-bit I/O port, performs a bitwise AND followed by a bitwise 
+  Reads a 16-bit I/O port, performs a bitwise AND followed by a bitwise
   OR, and writes the result back to the 16-bit I/O port.
 
   Reads the 16-bit I/O port specified by Port, performs a bitwise AND between
@@ -534,7 +528,7 @@ IoAnd16 (
 
   If 16-bit I/O port operations are not supported, then ASSERT().
   If Port is not aligned on a 16-bit boundary, then ASSERT().
-  
+
   @param  Port    The I/O port to write.
   @param  AndData The value to AND with the read value from the I/O port.
   @param  OrData  The value to OR with the result of the AND operation.
@@ -735,7 +729,7 @@ IoBitFieldAndThenOr16 (
 
   If 32-bit I/O port operations are not supported, then ASSERT().
   If Port is not aligned on a 32-bit boundary, then ASSERT().
-  
+
   @param  Port  The I/O port to read.
 
   @return The value read.
@@ -756,7 +750,7 @@ IoRead32 (
 
   If 32-bit I/O port operations are not supported, then ASSERT().
   If Port is not aligned on a 32-bit boundary, then ASSERT().
-  
+
   @param  Port  The I/O port to write.
   @param  Value The value to write to the I/O port.
 
@@ -873,7 +867,7 @@ IoAnd32 (
   );
 
 /**
-  Reads a 32-bit I/O port, performs a bitwise AND followed by a bitwise 
+  Reads a 32-bit I/O port, performs a bitwise AND followed by a bitwise
   OR, and writes the result back to the 32-bit I/O port.
 
   Reads the 32-bit I/O port specified by Port, performs a bitwise AND between
@@ -1174,7 +1168,7 @@ IoAnd64 (
   );
 
 /**
-  Reads a 64-bit I/O port, performs a bitwise AND followed by a bitwise 
+  Reads a 64-bit I/O port, performs a bitwise AND followed by a bitwise
   OR, and writes the result back to the 64-bit I/O port.
 
   Reads the 64-bit I/O port specified by Port, performs a bitwise AND between
@@ -1409,7 +1403,7 @@ MmioRead8 (
 
   @param  Address The MMIO register to write.
   @param  Value   The value to write to the MMIO register.
-  
+
   @return Value.
 
 **/
@@ -1424,7 +1418,7 @@ MmioWrite8 (
   Reads an 8-bit MMIO register, performs a bitwise OR, and writes the
   result back to the 8-bit MMIO register.
 
-  Reads the 8-bit MMIO register specified by Address, performs a bitwise 
+  Reads the 8-bit MMIO register specified by Address, performs a bitwise
   OR between the read result and the value specified by OrData, and
   writes the result to the 8-bit MMIO register specified by Address. The value
   written to the MMIO register is returned. This function must guarantee that
@@ -1471,7 +1465,7 @@ MmioAnd8 (
   );
 
 /**
-  Reads an 8-bit MMIO register, performs a bitwise AND followed by a bitwise 
+  Reads an 8-bit MMIO register, performs a bitwise AND followed by a bitwise
   OR, and writes the result back to the 8-bit MMIO register.
 
   Reads the 8-bit MMIO register specified by Address, performs a bitwise AND
@@ -1563,7 +1557,7 @@ MmioBitFieldWrite8 (
   Reads a bit field in an 8-bit MMIO register, performs a bitwise OR, and
   writes the result back to the bit field in the 8-bit MMIO register.
 
-  Reads the 8-bit MMIO register specified by Address, performs a bitwise 
+  Reads the 8-bit MMIO register specified by Address, performs a bitwise
   OR between the read result and the value specified by OrData, and
   writes the result to the 8-bit MMIO register specified by Address. The value
   written to the MMIO register is returned. This function must guarantee that
@@ -1704,7 +1698,7 @@ MmioRead16 (
 
   @param  Address The MMIO register to write.
   @param  Value   The value to write to the MMIO register.
-  
+
   @return Value.
 
 **/
@@ -1719,7 +1713,7 @@ MmioWrite16 (
   Reads a 16-bit MMIO register, performs a bitwise OR, and writes the
   result back to the 16-bit MMIO register.
 
-  Reads the 16-bit MMIO register specified by Address, performs a bitwise 
+  Reads the 16-bit MMIO register specified by Address, performs a bitwise
   OR between the read result and the value specified by OrData, and
   writes the result to the 16-bit MMIO register specified by Address. The value
   written to the MMIO register is returned. This function must guarantee that
@@ -1768,7 +1762,7 @@ MmioAnd16 (
   );
 
 /**
-  Reads a 16-bit MMIO register, performs a bitwise AND followed by a bitwise 
+  Reads a 16-bit MMIO register, performs a bitwise AND followed by a bitwise
   OR, and writes the result back to the 16-bit MMIO register.
 
   Reads the 16-bit MMIO register specified by Address, performs a bitwise AND
@@ -1862,7 +1856,7 @@ MmioBitFieldWrite16 (
   Reads a bit field in a 16-bit MMIO register, performs a bitwise OR, and
   writes the result back to the bit field in the 16-bit MMIO register.
 
-  Reads the 16-bit MMIO register specified by Address, performs a bitwise 
+  Reads the 16-bit MMIO register specified by Address, performs a bitwise
   OR between the read result and the value specified by OrData, and
   writes the result to the 16-bit MMIO register specified by Address. The value
   written to the MMIO register is returned. This function must guarantee that
@@ -2006,7 +2000,7 @@ MmioRead32 (
 
   @param  Address The MMIO register to write.
   @param  Value   The value to write to the MMIO register.
-  
+
   @return Value.
 
 **/
@@ -2021,7 +2015,7 @@ MmioWrite32 (
   Reads a 32-bit MMIO register, performs a bitwise OR, and writes the
   result back to the 32-bit MMIO register.
 
-  Reads the 32-bit MMIO register specified by Address, performs a bitwise 
+  Reads the 32-bit MMIO register specified by Address, performs a bitwise
   OR between the read result and the value specified by OrData, and
   writes the result to the 32-bit MMIO register specified by Address. The value
   written to the MMIO register is returned. This function must guarantee that
@@ -2070,7 +2064,7 @@ MmioAnd32 (
   );
 
 /**
-  Reads a 32-bit MMIO register, performs a bitwise AND followed by a bitwise 
+  Reads a 32-bit MMIO register, performs a bitwise AND followed by a bitwise
   OR, and writes the result back to the 32-bit MMIO register.
 
   Reads the 32-bit MMIO register specified by Address, performs a bitwise AND
@@ -2164,7 +2158,7 @@ MmioBitFieldWrite32 (
   Reads a bit field in a 32-bit MMIO register, performs a bitwise OR, and
   writes the result back to the bit field in the 32-bit MMIO register.
 
-  Reads the 32-bit MMIO register specified by Address, performs a bitwise 
+  Reads the 32-bit MMIO register specified by Address, performs a bitwise
   OR between the read result and the value specified by OrData, and
   writes the result to the 32-bit MMIO register specified by Address. The value
   written to the MMIO register is returned. This function must guarantee that
@@ -2321,7 +2315,7 @@ MmioWrite64 (
   Reads a 64-bit MMIO register, performs a bitwise OR, and writes the
   result back to the 64-bit MMIO register.
 
-  Reads the 64-bit MMIO register specified by Address, performs a bitwise 
+  Reads the 64-bit MMIO register specified by Address, performs a bitwise
   OR between the read result and the value specified by OrData, and
   writes the result to the 64-bit MMIO register specified by Address. The value
   written to the MMIO register is returned. This function must guarantee that
@@ -2370,7 +2364,7 @@ MmioAnd64 (
   );
 
 /**
-  Reads a 64-bit MMIO register, performs a bitwise AND followed by a bitwise 
+  Reads a 64-bit MMIO register, performs a bitwise AND followed by a bitwise
   OR, and writes the result back to the 64-bit MMIO register.
 
   Reads the 64-bit MMIO register specified by Address, performs a bitwise AND
@@ -2464,7 +2458,7 @@ MmioBitFieldWrite64 (
   Reads a bit field in a 64-bit MMIO register, performs a bitwise OR, and
   writes the result back to the bit field in the 64-bit MMIO register.
 
-  Reads the 64-bit MMIO register specified by Address, performs a bitwise 
+  Reads the 64-bit MMIO register specified by Address, performs a bitwise
   OR between the read result and the value specified by OrData, and
   writes the result to the 64-bit MMIO register specified by Address. The value
   written to the MMIO register is returned. This function must guarantee that
@@ -2578,11 +2572,11 @@ MmioBitFieldAndThenOr64 (
 /**
   Copy data from MMIO region to system memory by using 8-bit access.
 
-  Copy data from MMIO region specified by starting address StartAddress 
-  to system memory specified by Buffer by using 8-bit access. The total 
+  Copy data from MMIO region specified by starting address StartAddress
+  to system memory specified by Buffer by using 8-bit access. The total
   number of byte to be copied is specified by Length. Buffer is returned.
-  
-  If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT(). 
+
+  If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
   If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
 
 
@@ -2604,13 +2598,13 @@ MmioReadBuffer8 (
 /**
   Copy data from MMIO region to system memory by using 16-bit access.
 
-  Copy data from MMIO region specified by starting address StartAddress 
-  to system memory specified by Buffer by using 16-bit access. The total 
+  Copy data from MMIO region specified by starting address StartAddress
+  to system memory specified by Buffer by using 16-bit access. The total
   number of byte to be copied is specified by Length. Buffer is returned.
-  
+
   If StartAddress is not aligned on a 16-bit boundary, then ASSERT().
 
-  If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT(). 
+  If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
   If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
 
   If Length is not aligned on a 16-bit boundary, then ASSERT().
@@ -2634,13 +2628,13 @@ MmioReadBuffer16 (
 /**
   Copy data from MMIO region to system memory by using 32-bit access.
 
-  Copy data from MMIO region specified by starting address StartAddress 
-  to system memory specified by Buffer by using 32-bit access. The total 
+  Copy data from MMIO region specified by starting address StartAddress
+  to system memory specified by Buffer by using 32-bit access. The total
   number of byte to be copied is specified by Length. Buffer is returned.
-  
+
   If StartAddress is not aligned on a 32-bit boundary, then ASSERT().
 
-  If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT(). 
+  If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
   If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
 
   If Length is not aligned on a 32-bit boundary, then ASSERT().
@@ -2664,13 +2658,13 @@ MmioReadBuffer32 (
 /**
   Copy data from MMIO region to system memory by using 64-bit access.
 
-  Copy data from MMIO region specified by starting address StartAddress 
-  to system memory specified by Buffer by using 64-bit access. The total 
+  Copy data from MMIO region specified by starting address StartAddress
+  to system memory specified by Buffer by using 64-bit access. The total
   number of byte to be copied is specified by Length. Buffer is returned.
-  
+
   If StartAddress is not aligned on a 64-bit boundary, then ASSERT().
 
-  If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT(). 
+  If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
   If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
 
   If Length is not aligned on a 64-bit boundary, then ASSERT().
@@ -2694,11 +2688,11 @@ MmioReadBuffer64 (
 /**
   Copy data from system memory to MMIO region by using 8-bit access.
 
-  Copy data from system memory specified by Buffer to MMIO region specified 
-  by starting address StartAddress by using 8-bit access. The total number 
+  Copy data from system memory specified by Buffer to MMIO region specified
+  by starting address StartAddress by using 8-bit access. The total number
   of byte to be copied is specified by Length. Buffer is returned.
-  
-  If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT(). 
+
+  If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
   If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().
 
 
@@ -2720,13 +2714,13 @@ MmioWriteBuffer8 (
 /**
   Copy data from system memory to MMIO region by using 16-bit access.
 
-  Copy data from system memory specified by Buffer to MMIO region specified 
-  by starting address StartAddress by using 16-bit access. The total number 
+  Copy data from system memory specified by Buffer to MMIO region specified
+  by starting address StartAddress by using 16-bit access. The total number
   of byte to be copied is specified by Length. Buffer is returned.
-  
+
   If StartAddress is not aligned on a 16-bit boundary, then ASSERT().
 
-  If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT(). 
+  If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
   If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().
 
   If Length is not aligned on a 16-bit boundary, then ASSERT().
@@ -2751,13 +2745,13 @@ MmioWriteBuffer16 (
 /**
   Copy data from system memory to MMIO region by using 32-bit access.
 
-  Copy data from system memory specified by Buffer to MMIO region specified 
-  by starting address StartAddress by using 32-bit access. The total number 
+  Copy data from system memory specified by Buffer to MMIO region specified
+  by starting address StartAddress by using 32-bit access. The total number
   of byte to be copied is specified by Length. Buffer is returned.
-  
+
   If StartAddress is not aligned on a 32-bit boundary, then ASSERT().
 
-  If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT(). 
+  If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
   If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().
 
   If Length is not aligned on a 32-bit boundary, then ASSERT().
@@ -2782,13 +2776,13 @@ MmioWriteBuffer32 (
 /**
   Copy data from system memory to MMIO region by using 64-bit access.
 
-  Copy data from system memory specified by Buffer to MMIO region specified 
-  by starting address StartAddress by using 64-bit access. The total number 
+  Copy data from system memory specified by Buffer to MMIO region specified
+  by starting address StartAddress by using 64-bit access. The total number
   of byte to be copied is specified by Length. Buffer is returned.
-  
+
   If StartAddress is not aligned on a 64-bit boundary, then ASSERT().
 
-  If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT(). 
+  If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
   If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().
 
   If Length is not aligned on a 64-bit boundary, then ASSERT().
diff --git a/MdePkg/Include/Library/MemoryAllocationLib.h b/MdePkg/Include/Library/MemoryAllocationLib.h
index 204a8b51235f..14efb568955a 100644
--- a/MdePkg/Include/Library/MemoryAllocationLib.h
+++ b/MdePkg/Include/Library/MemoryAllocationLib.h
@@ -1,19 +1,13 @@
 /** @file
   Provides services to allocate and free memory buffers of various memory types and alignments.
-  
-  The Memory Allocation Library abstracts various common memory allocation operations. This library 
-  allows code to be written in a phase-independent manner because the allocation of memory in PEI, DXE, 
-  and SMM (for example) is done via a different mechanism. Using a common library interface makes it 
-  much easier to port algorithms from phase to phase. 
-  
-Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  The Memory Allocation Library abstracts various common memory allocation operations. This library
+  allows code to be written in a phase-independent manner because the allocation of memory in PEI, DXE,
+  and SMM (for example) is done via a different mechanism. Using a common library interface makes it
+  much easier to port algorithms from phase to phase.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -85,11 +79,11 @@ AllocateReservedPages (
   must have been allocated on a previous call to the page allocation services of the Memory
   Allocation Library.  If it is not possible to free allocated pages, then this function will
   perform no actions.
-  
+
   If Buffer was not allocated with a page allocation function in the Memory Allocation Library,
   then ASSERT().
   If Pages is zero, then ASSERT().
- 
+
   @param  Buffer                Pointer to the buffer of pages to free.
   @param  Pages                 The number of 4 KB pages to free.
 
@@ -108,7 +102,7 @@ FreePages (
   alignment specified by Alignment.  The allocated buffer is returned.  If Pages is 0, then NULL is
   returned.  If there is not enough memory at the specified alignment remaining to satisfy the
   request, then NULL is returned.
-  
+
   If Alignment is not a power of two and Alignment is not zero, then ASSERT().
   If Pages plus EFI_SIZE_TO_PAGES (Alignment) overflows, then ASSERT().
 
@@ -133,7 +127,7 @@ AllocateAlignedPages (
   alignment specified by Alignment.  The allocated buffer is returned.  If Pages is 0, then NULL is
   returned.  If there is not enough memory at the specified alignment remaining to satisfy the
   request, then NULL is returned.
-  
+
   If Alignment is not a power of two and Alignment is not zero, then ASSERT().
   If Pages plus EFI_SIZE_TO_PAGES (Alignment) overflows, then ASSERT().
 
@@ -158,7 +152,7 @@ AllocateAlignedRuntimePages (
   alignment specified by Alignment.  The allocated buffer is returned.  If Pages is 0, then NULL is
   returned.  If there is not enough memory at the specified alignment remaining to satisfy the
   request, then NULL is returned.
-  
+
   If Alignment is not a power of two and Alignment is not zero, then ASSERT().
   If Pages plus EFI_SIZE_TO_PAGES (Alignment) overflows, then ASSERT().
 
@@ -182,13 +176,13 @@ AllocateAlignedReservedPages (
 
   Frees the number of 4KB pages specified by Pages from the buffer specified by Buffer.  Buffer
   must have been allocated on a previous call to the aligned page allocation services of the Memory
-  Allocation Library.  If it is not possible to free allocated pages, then this function will 
+  Allocation Library.  If it is not possible to free allocated pages, then this function will
   perform no actions.
-  
+
   If Buffer was not allocated with an aligned page allocation function in the Memory Allocation
   Library, then ASSERT().
   If Pages is zero, then ASSERT().
-  
+
   @param  Buffer                Pointer to the buffer of pages to free.
   @param  Pages                 The number of 4 KB pages to free.
 
@@ -318,9 +312,9 @@ AllocateReservedZeroPool (
   AllocationSize bytes from Buffer to the newly allocated buffer, and returns a pointer to the
   allocated buffer.  If AllocationSize is 0, then a valid buffer of 0 size is returned.  If there
   is not enough memory remaining to satisfy the request, then NULL is returned.
-  
+
   If Buffer is NULL, then ASSERT().
-  If AllocationSize is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). 
+  If AllocationSize is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
 
   @param  AllocationSize        The number of bytes to allocate and zero.
   @param  Buffer                The buffer to copy to the allocated buffer.
@@ -342,9 +336,9 @@ AllocateCopyPool (
   AllocationSize bytes from Buffer to the newly allocated buffer, and returns a pointer to the
   allocated buffer.  If AllocationSize is 0, then a valid buffer of 0 size is returned.  If there
   is not enough memory remaining to satisfy the request, then NULL is returned.
-  
+
   If Buffer is NULL, then ASSERT().
-  If AllocationSize is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). 
+  If AllocationSize is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
 
   @param  AllocationSize        The number of bytes to allocate and zero.
   @param  Buffer                The buffer to copy to the allocated buffer.
@@ -366,9 +360,9 @@ AllocateRuntimeCopyPool (
   AllocationSize bytes from Buffer to the newly allocated buffer, and returns a pointer to the
   allocated buffer.  If AllocationSize is 0, then a valid buffer of 0 size is returned.  If there
   is not enough memory remaining to satisfy the request, then NULL is returned.
-  
+
   If Buffer is NULL, then ASSERT().
-  If AllocationSize is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT(). 
+  If AllocationSize is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
 
   @param  AllocationSize        The number of bytes to allocate and zero.
   @param  Buffer                The buffer to copy to the allocated buffer.
@@ -387,18 +381,18 @@ AllocateReservedCopyPool (
   Reallocates a buffer of type EfiBootServicesData.
 
   Allocates and zeros the number bytes specified by NewSize from memory of type
-  EfiBootServicesData.  If OldBuffer is not NULL, then the smaller of OldSize and 
-  NewSize bytes are copied from OldBuffer to the newly allocated buffer, and 
-  OldBuffer is freed.  A pointer to the newly allocated buffer is returned.  
-  If NewSize is 0, then a valid buffer of 0 size is  returned.  If there is not 
+  EfiBootServicesData.  If OldBuffer is not NULL, then the smaller of OldSize and
+  NewSize bytes are copied from OldBuffer to the newly allocated buffer, and
+  OldBuffer is freed.  A pointer to the newly allocated buffer is returned.
+  If NewSize is 0, then a valid buffer of 0 size is  returned.  If there is not
   enough memory remaining to satisfy the request, then NULL is returned.
-  
+
   If the allocation of the new buffer is successful and the smaller of NewSize and OldSize
   is greater than (MAX_ADDRESS - OldBuffer + 1), then ASSERT().
 
   @param  OldSize        The size, in bytes, of OldBuffer.
   @param  NewSize        The size, in bytes, of the buffer to reallocate.
-  @param  OldBuffer      The buffer to copy to the allocated buffer.  This is an optional 
+  @param  OldBuffer      The buffer to copy to the allocated buffer.  This is an optional
                          parameter that may be NULL.
 
   @return A pointer to the allocated buffer or NULL if allocation fails.
@@ -416,10 +410,10 @@ ReallocatePool (
   Reallocates a buffer of type EfiRuntimeServicesData.
 
   Allocates and zeros the number bytes specified by NewSize from memory of type
-  EfiRuntimeServicesData.  If OldBuffer is not NULL, then the smaller of OldSize and 
-  NewSize bytes are copied from OldBuffer to the newly allocated buffer, and 
-  OldBuffer is freed.  A pointer to the newly allocated buffer is returned.  
-  If NewSize is 0, then a valid buffer of 0 size is  returned.  If there is not 
+  EfiRuntimeServicesData.  If OldBuffer is not NULL, then the smaller of OldSize and
+  NewSize bytes are copied from OldBuffer to the newly allocated buffer, and
+  OldBuffer is freed.  A pointer to the newly allocated buffer is returned.
+  If NewSize is 0, then a valid buffer of 0 size is  returned.  If there is not
   enough memory remaining to satisfy the request, then NULL is returned.
 
   If the allocation of the new buffer is successful and the smaller of NewSize and OldSize
@@ -427,7 +421,7 @@ ReallocatePool (
 
   @param  OldSize        The size, in bytes, of OldBuffer.
   @param  NewSize        The size, in bytes, of the buffer to reallocate.
-  @param  OldBuffer      The buffer to copy to the allocated buffer.  This is an optional 
+  @param  OldBuffer      The buffer to copy to the allocated buffer.  This is an optional
                          parameter that may be NULL.
 
   @return A pointer to the allocated buffer or NULL if allocation fails.
@@ -445,10 +439,10 @@ ReallocateRuntimePool (
   Reallocates a buffer of type EfiReservedMemoryType.
 
   Allocates and zeros the number bytes specified by NewSize from memory of type
-  EfiReservedMemoryType.  If OldBuffer is not NULL, then the smaller of OldSize and 
-  NewSize bytes are copied from OldBuffer to the newly allocated buffer, and 
-  OldBuffer is freed.  A pointer to the newly allocated buffer is returned.  
-  If NewSize is 0, then a valid buffer of 0 size is  returned.  If there is not 
+  EfiReservedMemoryType.  If OldBuffer is not NULL, then the smaller of OldSize and
+  NewSize bytes are copied from OldBuffer to the newly allocated buffer, and
+  OldBuffer is freed.  A pointer to the newly allocated buffer is returned.
+  If NewSize is 0, then a valid buffer of 0 size is  returned.  If there is not
   enough memory remaining to satisfy the request, then NULL is returned.
 
   If the allocation of the new buffer is successful and the smaller of NewSize and OldSize
@@ -456,7 +450,7 @@ ReallocateRuntimePool (
 
   @param  OldSize        The size, in bytes, of OldBuffer.
   @param  NewSize        The size, in bytes, of the buffer to reallocate.
-  @param  OldBuffer      The buffer to copy to the allocated buffer.  This is an optional 
+  @param  OldBuffer      The buffer to copy to the allocated buffer.  This is an optional
                          parameter that may be NULL.
 
   @return A pointer to the allocated buffer or NULL if allocation fails.
@@ -477,7 +471,7 @@ ReallocateReservedPool (
   Frees the buffer specified by Buffer.  Buffer must have been allocated on a previous call to the
   pool allocation services of the Memory Allocation Library.  If it is not possible to free pool
   resources, then this function will perform no actions.
-  
+
   If Buffer was not allocated with a pool allocation function in the Memory Allocation Library,
   then ASSERT().
 
diff --git a/MdePkg/Include/Library/MmServicesTableLib.h b/MdePkg/Include/Library/MmServicesTableLib.h
new file mode 100644
index 000000000000..e9e4abebea5c
--- /dev/null
+++ b/MdePkg/Include/Library/MmServicesTableLib.h
@@ -0,0 +1,19 @@
+/** @file
+  Provides a service to retrieve a pointer to the Standalone MM Services Table.
+  Only available to MM_STANDALONE, SMM/DXE Combined and SMM module types.
+
+Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2016 - 2018, ARM Limited. All rights reserved.<BR>
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __MM_SERVICES_TABLE_LIB_H__
+#define __MM_SERVICES_TABLE_LIB_H__
+
+#include <PiMm.h>
+
+extern EFI_MM_SYSTEM_TABLE         *gMmst;
+
+#endif
diff --git a/MdePkg/Include/Library/OrderedCollectionLib.h b/MdePkg/Include/Library/OrderedCollectionLib.h
index e4191b82026f..6e1db6f859cc 100644
--- a/MdePkg/Include/Library/OrderedCollectionLib.h
+++ b/MdePkg/Include/Library/OrderedCollectionLib.h
@@ -6,13 +6,7 @@
 
   Copyright (C) 2014, Red Hat, Inc.
 
-  This program and the accompanying materials are licensed and made available
-  under the terms and conditions of the BSD License that accompanies this
-  distribution. The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php.
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
-  WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
 #ifndef __ORDERED_COLLECTION_LIB__
diff --git a/MdePkg/Include/Library/PalLib.h b/MdePkg/Include/Library/PalLib.h
deleted file mode 100644
index e5c3473c61d4..000000000000
--- a/MdePkg/Include/Library/PalLib.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/** @file
-  Provides library services to make PAL Calls.
-  
-  The PAL Library provides a service to make a PAL CALL.  This service is identical
-  in functionality to AsmPalCall() in the functions of the Base Library specific to Intel Itanium architecture.
-  The only difference is that the PAL Entry Point is not passed in.  Implementations
-  of this library class must manage PAL Entry Point on their own.  For example, a PEI
-  implementation can use a PPI to lookup the PAL Entry Point, and a DXE implementation
-  can contain a constructor to look up the PAL Entry Point from a HOB.  This library class 
-  is only available on Intel Itanium-based platforms.
-  
-Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials                          
-are licensed and made available under the terms and conditions of the BSD License         
-which accompanies this distribution.  The full text of the license may be found at        
-http://opensource.org/licenses/bsd-license.php                                            
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
-
-**/
-
-#ifndef __PAL_CALL_LIB_H__
-#define __PAL_CALL_LIB_H__
-
-#include <IndustryStandard/Pal.h>
-
-/**
-  Makes a PAL procedure call.
-
-  This is a wrapper function to make a PAL procedure call.  Based on the Index value,
-  this API will make static or stacked PAL call. Architected procedures may be designated
-  as required or optional.  If a PAL procedure is specified as optional, a unique return
-  code of 0xFFFFFFFFFFFFFFFF is returned in the Status field of the PAL_CALL_RETURN structure.
-  This indicates that the procedure is not present in this PAL implementation.  It is the
-  caller's responsibility to check for this return code after calling any optional PAL
-  procedure. No parameter checking is performed on the 4 input parameters, but there are
-  some common rules that the caller should follow when making a PAL call.  Any address
-  passed to PAL as buffers for return parameters must be 8-byte aligned.  Unaligned addresses
-  may cause undefined results.  For those parameters defined as reserved or some fields
-  defined as reserved must be zero filled or the invalid argument return value may be
-  returned or undefined result may occur during the execution of the procedure.
-  This function is only available on Intel Itanium-based platforms.
-
-  @param Index  The PAL procedure Index number.
-  @param Arg2   The 2nd parameter for PAL procedure calls.
-  @param Arg3   The 3rd parameter for PAL procedure calls.
-  @param Arg4   The 4th parameter for PAL procedure calls.
-
-  @return Structure returned from the PAL Call procedure, including the status and return value.
-
-**/
-PAL_CALL_RETURN
-EFIAPI
-PalCall (
-  IN UINT64                  Index,
-  IN UINT64                  Arg2,
-  IN UINT64                  Arg3,
-  IN UINT64                  Arg4
-  );
-
-#endif
-
diff --git a/MdePkg/Include/Library/PcdLib.h b/MdePkg/Include/Library/PcdLib.h
index fdb2df87aa0f..7a4a1bdaa3d8 100644
--- a/MdePkg/Include/Library/PcdLib.h
+++ b/MdePkg/Include/Library/PcdLib.h
@@ -8,20 +8,14 @@
   LibPatchPcdSetPtr() interface. For FeatureFlag/Fixed PCD, the macro interface is
   translated to a variable or macro that is auto-generated by build tool in
   module's autogen.h/autogen.c.
-  The PcdGetXX(), PcdSetXX(), PcdToken(), and PcdGetNextTokenSpace() operations are 
-  only available prior to ExitBootServices().  If access to PCD values are required 
+  The PcdGetXX(), PcdSetXX(), PcdToken(), and PcdGetNextTokenSpace() operations are
+  only available prior to ExitBootServices().  If access to PCD values are required
   at runtime, then their values must be collected prior to ExitBootServices().
   There are no restrictions on the use of FeaturePcd(), FixedPcdGetXX(),
   PatchPcdGetXX(), and PatchPcdSetXX().
 
-Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -127,7 +121,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
   @param   TokenName  The name of the PCD token to retrieve a current value for.
 
-  @return  The Boolean value for the token. 
+  @return  The Boolean value for the token.
 
 **/
 #define FixedPcdGetBool(TokenName)          _PCD_VALUE_##TokenName
@@ -142,7 +136,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
   @param   TokenName  The name of the PCD token to retrieve a current value for.
 
-  @return  A pointer to the buffer. 
+  @return  A pointer to the buffer.
 
 **/
 #define FixedPcdGetPtr(TokenName)           ((VOID *)_PCD_VALUE_##TokenName)
@@ -246,7 +240,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
   @param   TokenName  The name of the binary patchable PCD token to set the current value for.
   @param   Value      The 8-bit value to set.
-  
+
   @return Return the Value that was set.
 
 **/
@@ -320,17 +314,17 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 /**
   Sets a pointer to a binary patchable PCD token buffer based on a token name.
 
-  Sets the buffer for the token specified by TokenName.  Buffer is returned.  
+  Sets the buffer for the token specified by TokenName.  Buffer is returned.
   If SizeOfBuffer is greater than the maximum size supported by TokenName, then set SizeOfBuffer
-  to the maximum size supported by TokenName and return NULL to indicate that the set operation 
-  was not actually performed.  If SizeOfBuffer is set to MAX_ADDRESS, then SizeOfBuffer must be 
+  to the maximum size supported by TokenName and return NULL to indicate that the set operation
+  was not actually performed.  If SizeOfBuffer is set to MAX_ADDRESS, then SizeOfBuffer must be
   set to the maximum size supported by TokenName and NULL must be returned.
   If TokenName is not a valid token in the token space, then the module will not build.
   If TokenName is not a patchable in module PCD, then the module will not build.
-  
+
   If SizeOfBuffer is NULL, then ASSERT().
   If SizeOfBuffer > 0 and Buffer is NULL, then ASSERT().
-  
+
   @param   TokenName      The name of the binary patchable PCD token to set the current value for.
   @param   SizeOfBuffer   A pointer to the size, in bytes, of Buffer.
   @param   Buffer         Pointer to the value to set.
@@ -348,10 +342,10 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
                                               )
 /**
   Retrieves an 8-bit PCD token value based on a token name.
-  
+
   Returns the 8-bit value for the token specified by TokenName.
   If TokenName is not a valid token in the token space, then the module will not build.
-  
+
   @param   TokenName  The name of the PCD token to retrieve a current value for.
 
   @return  8-bit value for the token specified by TokenName.
@@ -460,10 +454,10 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
 /**
   Retrieves the size of the PCD token based on a token name.
-  
+
   Returns the size of the token specified by TokenName.
   If TokenName is not a valid token in the token space, then the module will not build.
-  
+
   @param[in]   TokenName  The name of the PCD token to retrieve a current value size for.
 
   @return      Return the size
@@ -474,11 +468,11 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
 /**
   Retrieve the size of a given PCD token.
-  
-  Returns the size of the token specified by TokenNumber and Guid. 
-  If Guid is NULL, then ASSERT(). 
 
-  @param[in]  Guid          Pointer to a 128-bit unique value that designates 
+  Returns the size of the token specified by TokenNumber and Guid.
+  If Guid is NULL, then ASSERT().
+
+  @param[in]  Guid          Pointer to a 128-bit unique value that designates
                             which namespace to retrieve a value from.
   @param[in]  TokenNumber   The PCD token number to retrieve a current value size for.
 
@@ -496,7 +490,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
   @param   TokenName  The name of the PCD token to retrieve a current value for.
   @param   Value      The 8-bit value to set.
-  
+
   @return Return the Value that was set.
 
 **/
@@ -551,17 +545,17 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 /**
   Sets a pointer to a PCD token buffer based on a token name.
 
-  Sets the buffer for the token specified by TokenName. Buffer is returned.  
-  If SizeOfBuffer is greater than the maximum size supported by TokenName, 
-  then set SizeOfBuffer to the maximum size supported by TokenName and return NULL 
-  to indicate that the set operation was not actually performed.  If SizeOfBuffer 
-  is set to MAX_ADDRESS, then SizeOfBuffer must be set to the maximum size supported 
+  Sets the buffer for the token specified by TokenName. Buffer is returned.
+  If SizeOfBuffer is greater than the maximum size supported by TokenName,
+  then set SizeOfBuffer to the maximum size supported by TokenName and return NULL
+  to indicate that the set operation was not actually performed.  If SizeOfBuffer
+  is set to MAX_ADDRESS, then SizeOfBuffer must be set to the maximum size supported
   by TokenName and NULL must be returned.
   If TokenName is not a valid token in the token space, then the module will not build.
-  
+
   If SizeOfBuffer is NULL, then ASSERT().
   If SizeOfBuffer > 0 and Buffer is NULL, then ASSERT().
-  
+
   @param   TokenName      The name of the PCD token to set the current value for.
   @param   SizeOfBuffer   A pointer to the size, in bytes, of Buffer.
   @param   Buffer         A pointer to the buffer to set.
@@ -571,11 +565,11 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 **/
 #define PcdSetPtr(TokenName, SizeOfBuffer, Buffer) \
                                             _PCD_SET_MODE_PTR_##TokenName   ((SizeOfBuffer), (Buffer))
-                                            
+
 /**
   Sets a Boolean PCD token value based on a token name.
 
-  Sets the Boolean value for the token specified by TokenName. Value is returned. 
+  Sets the Boolean value for the token specified by TokenName. Value is returned.
   If TokenName is not a valid token in the token space, then the module will not build.
 
   @param   TokenName      The name of the PCD token to set the current value for.
@@ -689,9 +683,9 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   Returns the token number for the token specified by Guid and TokenName.
   If TokenName is not a valid token in the token space, then the module will not build.
 
-  @param   Guid        Pointer to a 128-bit unique value that designates 
+  @param   Guid        Pointer to a 128-bit unique value that designates
                        which namespace to retrieve a value from.
-  @param   TokenName   The name of the PCD token to retrieve a current value for.                 
+  @param   TokenName   The name of the PCD token to retrieve a current value for.
 
   @return  Return the token number.
 
@@ -702,14 +696,14 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   Retrieves an 8-bit PCD token value based on a GUID and a token name.
 
   Returns the 8-bit value for the token specified by Guid and TokenName.
-  If TokenName is not a valid token in the token space specified by Guid, 
+  If TokenName is not a valid token in the token space specified by Guid,
   then the module will not build.
-  
+
   If Guid is NULL, then ASSERT().
 
-  @param   Guid        Pointer to a 128-bit unique value that designates 
+  @param   Guid        Pointer to a 128-bit unique value that designates
                        which namespace to retrieve a value from.
-  @param   TokenName   The name of the PCD token to retrieve a current value for.                 
+  @param   TokenName   The name of the PCD token to retrieve a current value for.
 
   @return  An 8-bit PCD token value.
 
@@ -720,14 +714,14 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   Retrieves a 16-bit PCD token value based on a GUID and a token name.
 
   Returns the 16-bit value for the token specified by Guid and TokenName.
-  If TokenName is not a valid token in the token space specified by Guid, 
+  If TokenName is not a valid token in the token space specified by Guid,
   then the module will not build.
 
   If Guid is NULL, then ASSERT().
 
-  @param   Guid        Pointer to a 128-bit unique value that designates 
+  @param   Guid        Pointer to a 128-bit unique value that designates
                        which namespace to retrieve a value from.
-  @param   TokenName   The name of the PCD token to retrieve a current value for.                 
+  @param   TokenName   The name of the PCD token to retrieve a current value for.
 
   @return  A 16-bit PCD token value.
 
@@ -739,14 +733,14 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   Retrieves a 32-bit PCD token value based on a GUID and a token name.
 
   Returns the 32-bit value for the token specified by Guid and TokenName.
-  If TokenName is not a valid token in the token space specified by Guid, 
+  If TokenName is not a valid token in the token space specified by Guid,
   then the module will not build.
 
   If Guid is NULL, then ASSERT().
 
-  @param   Guid        Pointer to a 128-bit unique value that designates 
+  @param   Guid        Pointer to a 128-bit unique value that designates
                        which namespace to retrieve a value from.
-  @param   TokenName   The name of the PCD token to retrieve a current value for.                 
+  @param   TokenName   The name of the PCD token to retrieve a current value for.
 
   @return  A 32-bit PCD token value.
 
@@ -758,14 +752,14 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   Retrieves a 64-bit PCD token value based on a GUID and a token name.
 
   Returns the 64-bit value for the token specified by Guid and TokenName.
-  If TokenName is not a valid token in the token space specified by Guid, 
+  If TokenName is not a valid token in the token space specified by Guid,
   then the module will not build.
 
   If Guid is NULL, then ASSERT().
 
-  @param   Guid        Pointer to a 128-bit unique value that designates 
+  @param   Guid        Pointer to a 128-bit unique value that designates
                        which namespace to retrieve a value from.
-  @param   TokenName   The name of the PCD token to retrieve a current value for.                 
+  @param   TokenName   The name of the PCD token to retrieve a current value for.
 
   @return  A 64-bit PCD token value.
 
@@ -777,14 +771,14 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   Retrieves a pointer to a PCD token buffer based on a GUID and a token name.
 
   Returns a pointer to the buffer for the token specified by Guid and TokenName.
-  If TokenName is not a valid token in the token space specified by Guid, 
+  If TokenName is not a valid token in the token space specified by Guid,
   then the module will not build.
 
   If Guid is NULL, then ASSERT().
 
-  @param   Guid        Pointer to a 128-bit unique value that designates 
+  @param   Guid        Pointer to a 128-bit unique value that designates
                        which namespace to retrieve a value from.
-  @param   TokenName   The name of the PCD token to retrieve a current value for.                 
+  @param   TokenName   The name of the PCD token to retrieve a current value for.
 
   @return  A pointer to a PCD token buffer.
 
@@ -796,14 +790,14 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   Retrieves a Boolean PCD token value based on a GUID and a token name.
 
   Returns the Boolean value for the token specified by Guid and TokenName.
-  If TokenName is not a valid token in the token space specified by Guid, 
+  If TokenName is not a valid token in the token space specified by Guid,
   then the module will not build.
 
   If Guid is NULL, then ASSERT().
 
-  @param   Guid        Pointer to a 128-bit unique value that designates 
+  @param   Guid        Pointer to a 128-bit unique value that designates
                        which namespace to retrieve a value from.
-  @param   TokenName   The name of the PCD token to retrieve a current value for.                 
+  @param   TokenName   The name of the PCD token to retrieve a current value for.
 
   @return  A Boolean PCD token value.
 
@@ -817,15 +811,15 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   Sets an 8-bit PCD token value based on a GUID and a token name.
 
   Sets the 8-bit value for the token specified by Guid and TokenName. Value is returned.
-  If TokenName is not a valid token in the token space specified by Guid, 
+  If TokenName is not a valid token in the token space specified by Guid,
   then the module will not build.
 
   If Guid is NULL, then ASSERT().
 
-  @param   Guid        Pointer to a 128-bit unique value that designates 
+  @param   Guid        Pointer to a 128-bit unique value that designates
                        which namespace to retrieve a value from.
   @param   TokenName   The name of the PCD token to set the current value for.
-  @param   Value       The 8-bit value to set.                   
+  @param   Value       The 8-bit value to set.
 
   @return Return the Value that was set.
 
@@ -837,15 +831,15 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   Sets a 16-bit PCD token value based on a GUID and a token name.
 
   Sets the 16-bit value for the token specified by Guid and TokenName. Value is returned.
-  If TokenName is not a valid token in the token space specified by Guid, 
+  If TokenName is not a valid token in the token space specified by Guid,
   then the module will not build.
 
   If Guid is NULL, then ASSERT().
 
-  @param   Guid        Pointer to a 128-bit unique value that designates 
+  @param   Guid        Pointer to a 128-bit unique value that designates
                        which namespace to retrieve a value from.
   @param   TokenName   The name of the PCD token to set the current value for.
-  @param   Value       The 16-bit value to set.                   
+  @param   Value       The 16-bit value to set.
 
   @return Return the Value that was set.
 
@@ -857,15 +851,15 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   Sets a 32-bit PCD token value based on a GUID and a token name.
 
   Sets the 32-bit value for the token specified by Guid and TokenName. Value is returned.
-  If TokenName is not a valid token in the token space specified by Guid, 
+  If TokenName is not a valid token in the token space specified by Guid,
   then the module will not build.
 
   If Guid is NULL, then ASSERT().
 
-  @param   Guid        Pointer to a 128-bit unique value that designates 
+  @param   Guid        Pointer to a 128-bit unique value that designates
                        which namespace to retrieve a value from.
   @param   TokenName   The name of the PCD token to set the current value for.
-  @param   Value       The 32-bit value to set.                   
+  @param   Value       The 32-bit value to set.
 
   @return Return the Value that was set.
 
@@ -877,15 +871,15 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   Sets a 64-bit PCD token value based on a GUID and a token name.
 
   Sets the 64-bit value for the token specified by Guid and TokenName. Value is returned.
-  If TokenName is not a valid token in the token space specified by Guid, 
+  If TokenName is not a valid token in the token space specified by Guid,
   then the module will not build.
 
   If Guid is NULL, then ASSERT().
 
-  @param   Guid        Pointer to a 128-bit unique value that designates 
+  @param   Guid        Pointer to a 128-bit unique value that designates
   which namespace to retrieve a value from.
   @param   TokenName   The name of the PCD token to set the current value for.
-  @param   Value       The 64-bit value to set.                   
+  @param   Value       The 64-bit value to set.
 
   @return Return the Value that was set.
 
@@ -896,25 +890,25 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 /**
   Sets a pointer to a PCD token buffer based on a GUID and a token name.
 
-  Sets the buffer for the token specified by Guid and TokenName. Buffer is returned.  
-  If SizeOfBuffer is greater than the maximum size supported by Guid and TokenName, 
-  then set SizeOfBuffer to the maximum size supported by Guid and TokenName and return 
-  NULL to indicate that the set operation was not actually performed. If SizeOfBuffer 
+  Sets the buffer for the token specified by Guid and TokenName. Buffer is returned.
+  If SizeOfBuffer is greater than the maximum size supported by Guid and TokenName,
+  then set SizeOfBuffer to the maximum size supported by Guid and TokenName and return
+  NULL to indicate that the set operation was not actually performed. If SizeOfBuffer
   is set to MAX_ADDRESS, then SizeOfBuffer must be set to the maximum size supported by
   Guid and TokenName and NULL must be returned.
-  If TokenName is not a valid token in the token space specified by Guid, 
+  If TokenName is not a valid token in the token space specified by Guid,
   then the module will not build.
-  
+
   If Guid is NULL, then ASSERT().
   If SizeOfBuffer is NULL, then ASSERT().
   If SizeOfBuffer > 0 and Buffer is NULL, then ASSERT().
 
-  @param   Guid           Pointer to a 128-bit unique value that designates 
+  @param   Guid           Pointer to a 128-bit unique value that designates
                           which namespace to retrieve a value from.
   @param   TokenName      The name of the PCD token to set the current value for.
-  @param   SizeOfBuffer   A pointer to the size, in bytes, of Buffer.                  
+  @param   SizeOfBuffer   A pointer to the size, in bytes, of Buffer.
   @param   Buffer         Pointer to the buffer to set.
-    
+
   @return Return the pointer to the Buffer that was set.
 
 **/
@@ -925,20 +919,20 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 /**
   Sets a Boolean PCD token value based on a GUID and a token name.
 
-  Sets the Boolean value for the token specified by Guid and TokenName. Value is returned. 
-  If TokenName is not a valid token in the token space specified by Guid, 
+  Sets the Boolean value for the token specified by Guid and TokenName. Value is returned.
+  If TokenName is not a valid token in the token space specified by Guid,
   then the module will not build.
 
   If Guid is NULL, then ASSERT().
 
-  @param   Guid           Pointer to a 128-bit unique value that designates 
+  @param   Guid           Pointer to a 128-bit unique value that designates
                           which namespace to retrieve a value from.
-  @param   TokenName      The name of the PCD token to set the current value for.              
+  @param   TokenName      The name of the PCD token to set the current value for.
   @param   Value          The Boolean value to set.
 
   @return Return the Value that was set.
 
-**/                                         
+**/
 #define PcdSetExBool(Guid, TokenName, Value) \
                                             LibPcdSetExBool((Guid), PcdTokenEx(Guid,TokenName), (Value))
 #endif
@@ -1088,12 +1082,12 @@ LibPcdSetSku (
 
 /**
   This function provides a means by which to retrieve a value for a given PCD token.
-  
-  Returns the 8-bit value for the token specified by TokenNumber. 
+
+  Returns the 8-bit value for the token specified by TokenNumber.
 
   @param[in]  TokenNumber The PCD token number to retrieve a current value for.
 
-  @return Returns the 8-bit value for the token specified by TokenNumber. 
+  @return Returns the 8-bit value for the token specified by TokenNumber.
 
 **/
 UINT8
@@ -1105,12 +1099,12 @@ LibPcdGet8 (
 
 /**
   This function provides a means by which to retrieve a value for a given PCD token.
-  
-  Returns the 16-bit value for the token specified by TokenNumber. 
+
+  Returns the 16-bit value for the token specified by TokenNumber.
 
   @param[in]  TokenNumber The PCD token number to retrieve a current value for.
 
-  @return Returns the 16-bit value for the token specified by TokenNumber. 
+  @return Returns the 16-bit value for the token specified by TokenNumber.
 
 **/
 UINT16
@@ -1122,8 +1116,8 @@ LibPcdGet16 (
 
 /**
   This function provides a means by which to retrieve a value for a given PCD token.
-  
-  Returns the 32-bit value for the token specified by TokenNumber. 
+
+  Returns the 32-bit value for the token specified by TokenNumber.
 
   @param[in]  TokenNumber The PCD token number to retrieve a current value for.
 
@@ -1139,7 +1133,7 @@ LibPcdGet32 (
 
 /**
   This function provides a means by which to retrieve a value for a given PCD token.
-  
+
   Returns the 64-bit value for the token specified by TokenNumber.
 
   @param[in]  TokenNumber The PCD token number to retrieve a current value for.
@@ -1156,7 +1150,7 @@ LibPcdGet64 (
 
 /**
   This function provides a means by which to retrieve a value for a given PCD token.
-  
+
   Returns the pointer to the buffer of the token specified by TokenNumber.
 
   @param[in]  TokenNumber The PCD token number to retrieve a current value for.
@@ -1173,15 +1167,15 @@ LibPcdGetPtr (
 
 /**
   This function provides a means by which to retrieve a value for a given PCD token.
-  
-  Returns the Boolean value of the token specified by TokenNumber. 
+
+  Returns the Boolean value of the token specified by TokenNumber.
 
   @param[in]  TokenNumber The PCD token number to retrieve a current value for.
 
-  @return Returns the Boolean value of the token specified by TokenNumber. 
+  @return Returns the Boolean value of the token specified by TokenNumber.
 
 **/
-BOOLEAN 
+BOOLEAN
 EFIAPI
 LibPcdGetBool (
   IN UINTN             TokenNumber
@@ -1193,7 +1187,7 @@ LibPcdGetBool (
 
   @param[in]  TokenNumber The PCD token number to retrieve a current value for.
 
-  @return Returns the size of the token specified by TokenNumber. 
+  @return Returns the size of the token specified by TokenNumber.
 
 **/
 UINTN
@@ -1205,12 +1199,12 @@ LibPcdGetSize (
 
 /**
   This function provides a means by which to retrieve a value for a given PCD token.
-  
+
   Returns the 8-bit value for the token specified by TokenNumber and Guid.
-  
-  If Guid is NULL, then ASSERT(). 
 
-  @param[in]  Guid         Pointer to a 128-bit unique value that designates 
+  If Guid is NULL, then ASSERT().
+
+  @param[in]  Guid         Pointer to a 128-bit unique value that designates
                            which namespace to retrieve a value from.
   @param[in]  TokenNumber  The PCD token number to retrieve a current value for.
 
@@ -1229,10 +1223,10 @@ LibPcdGetEx8 (
   This function provides a means by which to retrieve a value for a given PCD token.
 
   Returns the 16-bit value for the token specified by TokenNumber and Guid.
-  
-  If Guid is NULL, then ASSERT(). 
 
-  @param[in]  Guid         Pointer to a 128-bit unique value that designates 
+  If Guid is NULL, then ASSERT().
+
+  @param[in]  Guid         Pointer to a 128-bit unique value that designates
                            which namespace to retrieve a value from.
   @param[in]  TokenNumber  The PCD token number to retrieve a current value for.
 
@@ -1249,9 +1243,9 @@ LibPcdGetEx16 (
 
 /**
   Returns the 32-bit value for the token specified by TokenNumber and Guid.
-  If Guid is NULL, then ASSERT(). 
+  If Guid is NULL, then ASSERT().
 
-  @param[in]  Guid         Pointer to a 128-bit unique value that designates 
+  @param[in]  Guid         Pointer to a 128-bit unique value that designates
                            which namespace to retrieve a value from.
   @param[in]  TokenNumber  The PCD token number to retrieve a current value for.
 
@@ -1268,12 +1262,12 @@ LibPcdGetEx32 (
 
 /**
   This function provides a means by which to retrieve a value for a given PCD token.
-  
+
   Returns the 64-bit value for the token specified by TokenNumber and Guid.
-  
-  If Guid is NULL, then ASSERT(). 
 
-  @param[in]  Guid          Pointer to a 128-bit unique value that designates 
+  If Guid is NULL, then ASSERT().
+
+  @param[in]  Guid          Pointer to a 128-bit unique value that designates
                             which namespace to retrieve a value from.
   @param[in]  TokenNumber   The PCD token number to retrieve a current value for.
 
@@ -1290,12 +1284,12 @@ LibPcdGetEx64 (
 
 /**
   This function provides a means by which to retrieve a value for a given PCD token.
-  
+
   Returns the pointer to the buffer of token specified by TokenNumber and Guid.
-  
-  If Guid is NULL, then ASSERT(). 
 
-  @param[in]  Guid          Pointer to a 128-bit unique value that designates 
+  If Guid is NULL, then ASSERT().
+
+  @param[in]  Guid          Pointer to a 128-bit unique value that designates
                             which namespace to retrieve a value from.
   @param[in]  TokenNumber   The PCD token number to retrieve a current value for.
 
@@ -1312,12 +1306,12 @@ LibPcdGetExPtr (
 
 /**
   This function provides a means by which to retrieve a value for a given PCD token.
-  
-  Returns the Boolean value of the token specified by TokenNumber and Guid. 
-  
-  If Guid is NULL, then ASSERT(). 
 
-  @param[in]  Guid          Pointer to a 128-bit unique value that designates 
+  Returns the Boolean value of the token specified by TokenNumber and Guid.
+
+  If Guid is NULL, then ASSERT().
+
+  @param[in]  Guid          Pointer to a 128-bit unique value that designates
                             which namespace to retrieve a value from.
   @param[in]  TokenNumber   The PCD token number to retrieve a current value for.
 
@@ -1334,12 +1328,12 @@ LibPcdGetExBool (
 
 /**
   This function provides a means by which to retrieve the size of a given PCD token.
-  
-  Returns the size of the token specified by TokenNumber and Guid. 
-  
-  If Guid is NULL, then ASSERT(). 
 
-  @param[in]  Guid          Pointer to a 128-bit unique value that designates 
+  Returns the size of the token specified by TokenNumber and Guid.
+
+  If Guid is NULL, then ASSERT().
+
+  @param[in]  Guid          Pointer to a 128-bit unique value that designates
                             which namespace to retrieve a value from.
   @param[in]  TokenNumber   The PCD token number to retrieve a current value for.
 
@@ -1357,8 +1351,8 @@ LibPcdGetExSize (
 #ifndef DISABLE_NEW_DEPRECATED_INTERFACES
 /**
   This function provides a means by which to set a value for a given PCD token.
-  
-  Sets the 8-bit value for the token specified by TokenNumber 
+
+  Sets the 8-bit value for the token specified by TokenNumber
   to the value specified by Value.  Value is returned.
 
   @param[in]  TokenNumber   The PCD token number to set a current value for.
@@ -1377,8 +1371,8 @@ LibPcdSet8 (
 
 /**
   This function provides a means by which to set a value for a given PCD token.
-  
-  Sets the 16-bit value for the token specified by TokenNumber 
+
+  Sets the 16-bit value for the token specified by TokenNumber
   to the value specified by Value.  Value is returned.
 
   @param[in]  TokenNumber   The PCD token number to set a current value for.
@@ -1397,8 +1391,8 @@ LibPcdSet16 (
 
 /**
   This function provides a means by which to set a value for a given PCD token.
-  
-  Sets the 32-bit value for the token specified by TokenNumber 
+
+  Sets the 32-bit value for the token specified by TokenNumber
   to the value specified by Value.  Value is returned.
 
   @param[in]  TokenNumber   The PCD token number to set a current value for.
@@ -1417,8 +1411,8 @@ LibPcdSet32 (
 
 /**
   This function provides a means by which to set a value for a given PCD token.
-  
-  Sets the 64-bit value for the token specified by TokenNumber 
+
+  Sets the 64-bit value for the token specified by TokenNumber
   to the value specified by Value.  Value is returned.
 
   @param[in]  TokenNumber   The PCD token number to set a current value for.
@@ -1437,19 +1431,19 @@ LibPcdSet64 (
 
 /**
   This function provides a means by which to set a value for a given PCD token.
-  
-  Sets a buffer for the token specified by TokenNumber to the value 
-  specified by Buffer and SizeOfBuffer.  Buffer is returned.  
-  If SizeOfBuffer is greater than the maximum size support by TokenNumber, 
-  then set SizeOfBuffer to the maximum size supported by TokenNumber and 
+
+  Sets a buffer for the token specified by TokenNumber to the value
+  specified by Buffer and SizeOfBuffer.  Buffer is returned.
+  If SizeOfBuffer is greater than the maximum size support by TokenNumber,
+  then set SizeOfBuffer to the maximum size supported by TokenNumber and
   return NULL to indicate that the set operation was not actually performed.
 
-  If SizeOfBuffer is set to MAX_ADDRESS, then SizeOfBuffer must be set to the 
+  If SizeOfBuffer is set to MAX_ADDRESS, then SizeOfBuffer must be set to the
   maximum size supported by TokenName and NULL must be returned.
-  
+
   If SizeOfBuffer is NULL, then ASSERT().
   If SizeOfBuffer > 0 and Buffer is NULL, then ASSERT().
-  
+
   @param[in]      TokenNumber   The PCD token number to set a current value for.
   @param[in, out] SizeOfBuffer  The size, in bytes, of Buffer.
   @param[in]      Buffer        A pointer to the buffer to set.
@@ -1468,8 +1462,8 @@ LibPcdSetPtr (
 
 /**
   This function provides a means by which to set a value for a given PCD token.
-  
-  Sets the Boolean value for the token specified by TokenNumber 
+
+  Sets the Boolean value for the token specified by TokenNumber
   to the value specified by Value.  Value is returned.
 
   @param[in]  TokenNumber   The PCD token number to set a current value for.
@@ -1488,13 +1482,13 @@ LibPcdSetBool (
 
 /**
   This function provides a means by which to set a value for a given PCD token.
-  
-  Sets the 8-bit value for the token specified by TokenNumber and 
+
+  Sets the 8-bit value for the token specified by TokenNumber and
   Guid to the value specified by Value. Value is returned.
 
   If Guid is NULL, then ASSERT().
 
-  @param[in]  Guid          Pointer to a 128-bit unique value that 
+  @param[in]  Guid          Pointer to a 128-bit unique value that
                             designates which namespace to set a value from.
   @param[in]  TokenNumber   The PCD token number to set a current value for.
   @param[in]  Value         The 8-bit value to set.
@@ -1513,13 +1507,13 @@ LibPcdSetEx8 (
 
 /**
   This function provides a means by which to set a value for a given PCD token.
-  
-  Sets the 16-bit value for the token specified by TokenNumber and 
+
+  Sets the 16-bit value for the token specified by TokenNumber and
   Guid to the value specified by Value. Value is returned.
 
   If Guid is NULL, then ASSERT().
 
-  @param[in]  Guid          Pointer to a 128-bit unique value that 
+  @param[in]  Guid          Pointer to a 128-bit unique value that
                             designates which namespace to set a value from.
   @param[in]  TokenNumber   The PCD token number to set a current value for.
   @param[in]  Value         The 16-bit value to set.
@@ -1538,13 +1532,13 @@ LibPcdSetEx16 (
 
 /**
   This function provides a means by which to set a value for a given PCD token.
-  
-  Sets the 32-bit value for the token specified by TokenNumber and 
+
+  Sets the 32-bit value for the token specified by TokenNumber and
   Guid to the value specified by Value. Value is returned.
 
   If Guid is NULL, then ASSERT().
 
-  @param[in]  Guid          Pointer to a 128-bit unique value that 
+  @param[in]  Guid          Pointer to a 128-bit unique value that
                             designates which namespace to set a value from.
   @param[in]  TokenNumber   The PCD token number to set a current value for.
   @param[in]  Value         The 32-bit value to set.
@@ -1563,13 +1557,13 @@ LibPcdSetEx32 (
 
 /**
   This function provides a means by which to set a value for a given PCD token.
-  
-  Sets the 64-bit value for the token specified by TokenNumber and 
+
+  Sets the 64-bit value for the token specified by TokenNumber and
   Guid to the value specified by Value. Value is returned.
 
   If Guid is NULL, then ASSERT().
 
-  @param[in]  Guid          Pointer to a 128-bit unique value that 
+  @param[in]  Guid          Pointer to a 128-bit unique value that
                             designates which namespace to set a value from.
   @param[in]  TokenNumber   The PCD token number to set a current value for.
   @param[in]  Value         The 64-bit value to set.
@@ -1588,18 +1582,18 @@ LibPcdSetEx64 (
 
 /**
   This function provides a means by which to set a value for a given PCD token.
-  
-  Sets a buffer for the token specified by TokenNumber to the value specified by 
-  Buffer and SizeOfBuffer.  Buffer is returned.  If SizeOfBuffer is greater than 
-  the maximum size support by TokenNumber, then set SizeOfBuffer to the maximum size 
-  supported by TokenNumber and return NULL to indicate that the set operation 
+
+  Sets a buffer for the token specified by TokenNumber to the value specified by
+  Buffer and SizeOfBuffer.  Buffer is returned.  If SizeOfBuffer is greater than
+  the maximum size support by TokenNumber, then set SizeOfBuffer to the maximum size
+  supported by TokenNumber and return NULL to indicate that the set operation
   was not actually performed.
-  
+
   If Guid is NULL, then ASSERT().
   If SizeOfBuffer is NULL, then ASSERT().
   If SizeOfBuffer > 0 and Buffer is NULL, then ASSERT().
-  
-  @param[in]  Guid              Pointer to a 128-bit unique value that 
+
+  @param[in]  Guid              Pointer to a 128-bit unique value that
                                 designates which namespace to set a value from.
   @param[in]  TokenNumber       The PCD token number to set a current value for.
   @param[in, out] SizeOfBuffer  The size, in bytes, of Buffer.
@@ -1620,13 +1614,13 @@ LibPcdSetExPtr (
 
 /**
   This function provides a means by which to set a value for a given PCD token.
-  
-  Sets the Boolean value for the token specified by TokenNumber and 
+
+  Sets the Boolean value for the token specified by TokenNumber and
   Guid to the value specified by Value. Value is returned.
 
   If Guid is NULL, then ASSERT().
 
-  @param[in]  Guid          Pointer to a 128-bit unique value that 
+  @param[in]  Guid          Pointer to a 128-bit unique value that
                             designates which namespace to set a value from.
   @param[in]  TokenNumber   The PCD token number to set a current value for.
   @param[in]  Value         The Boolean value to set.
@@ -1927,7 +1921,7 @@ LibPcdSetExBoolS (
   Secondly, it provides a mechanism for the module that did the registration to intercept
   the set operation and override the value been set if necessary. After the invocation of
   the callback function, TokenData will be used by PCD service PEIM or driver to modify th
-  internal data in PCD database. 
+  internal data in PCD database.
 
   @param[in]      CallBackGuid    The PCD token GUID being set.
   @param[in]      CallBackToken   The PCD token number being set.
@@ -1947,17 +1941,17 @@ VOID
 
 /**
   Set up a notification function that is called when a specified token is set.
-  
-  When the token specified by TokenNumber and Guid is set, 
-  then notification function specified by NotificationFunction is called.  
+
+  When the token specified by TokenNumber and Guid is set,
+  then notification function specified by NotificationFunction is called.
   If Guid is NULL, then the default token space is used.
   If NotificationFunction is NULL, then ASSERT().
 
-  @param[in]  Guid                  Pointer to a 128-bit unique value that designates which 
-                                    namespace to set a value from.  If NULL, then the default 
+  @param[in]  Guid                  Pointer to a 128-bit unique value that designates which
+                                    namespace to set a value from.  If NULL, then the default
                                     token space is used.
   @param[in]  TokenNumber           The PCD token number to monitor.
-  @param[in]  NotificationFunction  The function to call when the token 
+  @param[in]  NotificationFunction  The function to call when the token
                                     specified by Guid and TokenNumber is set.
 
 **/
@@ -1972,12 +1966,12 @@ LibPcdCallbackOnSet (
 
 /**
   Disable a notification function that was established with LibPcdCallbackonSet().
-  
+
   Disable a notification function that was previously established with LibPcdCallbackOnSet().
   If NotificationFunction is NULL, then ASSERT().
-  If LibPcdCallbackOnSet() was not previously called with Guid, TokenNumber, 
+  If LibPcdCallbackOnSet() was not previously called with Guid, TokenNumber,
   and NotificationFunction, then ASSERT().
-  
+
   @param[in]  Guid                 Specify the GUID token space.
   @param[in]  TokenNumber          Specify the token number.
   @param[in]  NotificationFunction The callback function to be unregistered.
@@ -1994,24 +1988,24 @@ LibPcdCancelCallback (
 
 /**
   Retrieves the next token in a token space.
-  
-  Retrieves the next PCD token number from the token space specified by Guid.  
-  If Guid is NULL, then the default token space is used.  If TokenNumber is 0, 
-  then the first token number is returned.  Otherwise, the token number that 
-  follows TokenNumber in the token space is returned.  If TokenNumber is the last 
-  token number in the token space, then 0 is returned.  
-  
+
+  Retrieves the next PCD token number from the token space specified by Guid.
+  If Guid is NULL, then the default token space is used.  If TokenNumber is 0,
+  then the first token number is returned.  Otherwise, the token number that
+  follows TokenNumber in the token space is returned.  If TokenNumber is the last
+  token number in the token space, then 0 is returned.
+
   If TokenNumber is not 0 and is not in the token space specified by Guid, then ASSERT().
 
-  @param[in]  Guid        Pointer to a 128-bit unique value that designates which namespace 
+  @param[in]  Guid        Pointer to a 128-bit unique value that designates which namespace
                           to set a value from.  If NULL, then the default token space is used.
-  @param[in]  TokenNumber The previous PCD token number.  If 0, then retrieves the first PCD 
+  @param[in]  TokenNumber The previous PCD token number.  If 0, then retrieves the first PCD
                           token number.
 
   @return The next valid token number.
 
 **/
-UINTN           
+UINTN
 EFIAPI
 LibPcdGetNextToken (
   IN CONST GUID               *Guid,       OPTIONAL
@@ -2022,12 +2016,12 @@ LibPcdGetNextToken (
 
 /**
   Used to retrieve the list of available PCD token space GUIDs.
-  
+
   Returns the PCD token space GUID that follows TokenSpaceGuid in the list of token spaces
   in the platform.
   If TokenSpaceGuid is NULL, then a pointer to the first PCD token spaces returned.
   If TokenSpaceGuid is the last PCD token space GUID in the list, then NULL is returned.
-  
+
   @param  TokenSpaceGuid  Pointer to the a PCD token space GUID
 
   @return The next valid token namespace.
@@ -2042,24 +2036,24 @@ LibPcdGetNextTokenSpace (
 
 /**
   Sets a value of a patchable PCD entry that is type pointer.
-  
-  Sets the PCD entry specified by PatchVariable to the value specified by Buffer 
-  and SizeOfBuffer.  Buffer is returned.  If SizeOfBuffer is greater than 
-  MaximumDatumSize, then set SizeOfBuffer to MaximumDatumSize and return 
-  NULL to indicate that the set operation was not actually performed.  
-  If SizeOfBuffer is set to MAX_ADDRESS, then SizeOfBuffer must be set to 
+
+  Sets the PCD entry specified by PatchVariable to the value specified by Buffer
+  and SizeOfBuffer.  Buffer is returned.  If SizeOfBuffer is greater than
+  MaximumDatumSize, then set SizeOfBuffer to MaximumDatumSize and return
+  NULL to indicate that the set operation was not actually performed.
+  If SizeOfBuffer is set to MAX_ADDRESS, then SizeOfBuffer must be set to
   MaximumDatumSize and NULL must be returned.
-  
+
   If PatchVariable is NULL, then ASSERT().
   If SizeOfBuffer is NULL, then ASSERT().
   If SizeOfBuffer > 0 and Buffer is NULL, then ASSERT().
 
-  @param[out] PatchVariable     A pointer to the global variable in a module that is 
+  @param[out] PatchVariable     A pointer to the global variable in a module that is
                                 the target of the set operation.
   @param[in] MaximumDatumSize   The maximum size allowed for the PCD entry specified by PatchVariable.
   @param[in, out] SizeOfBuffer  A pointer to the size, in bytes, of Buffer.
   @param[in] Buffer             A pointer to the buffer to used to set the target variable.
-  
+
   @return Return the pointer to the Buffer that was set.
 
 **/
@@ -2091,7 +2085,7 @@ LibPatchPcdSetPtr (
   @param[in] MaximumDatumSize   The maximum size allowed for the PCD entry specified by PatchVariable.
   @param[in, out] SizeOfBuffer  A pointer to the size, in bytes, of Buffer.
   @param[in] Buffer             A pointer to the buffer to used to set the target variable.
-  
+
   @return The status of the set operation.
 
 **/
@@ -2106,26 +2100,26 @@ LibPatchPcdSetPtrS (
 
 /**
   Sets a value and size of a patchable PCD entry that is type pointer.
-  
-  Sets the PCD entry specified by PatchVariable to the value specified by Buffer 
-  and SizeOfBuffer. Buffer is returned.  If SizeOfBuffer is greater than 
-  MaximumDatumSize, then set SizeOfBuffer to MaximumDatumSize and return 
-  NULL to indicate that the set operation was not actually performed.  
-  If SizeOfBuffer is set to MAX_ADDRESS, then SizeOfBuffer must be set to 
+
+  Sets the PCD entry specified by PatchVariable to the value specified by Buffer
+  and SizeOfBuffer. Buffer is returned.  If SizeOfBuffer is greater than
+  MaximumDatumSize, then set SizeOfBuffer to MaximumDatumSize and return
+  NULL to indicate that the set operation was not actually performed.
+  If SizeOfBuffer is set to MAX_ADDRESS, then SizeOfBuffer must be set to
   MaximumDatumSize and NULL must be returned.
-  
+
   If PatchVariable is NULL, then ASSERT().
   If SizeOfPatchVariable is NULL, then ASSERT().
   If SizeOfBuffer is NULL, then ASSERT().
   If SizeOfBuffer > 0 and Buffer is NULL, then ASSERT().
 
-  @param[out] PatchVariable     A pointer to the global variable in a module that is 
+  @param[out] PatchVariable     A pointer to the global variable in a module that is
                                 the target of the set operation.
   @param[out] SizeOfPatchVariable A pointer to the size, in bytes, of PatchVariable.
   @param[in] MaximumDatumSize   The maximum size allowed for the PCD entry specified by PatchVariable.
   @param[in, out] SizeOfBuffer  A pointer to the size, in bytes, of Buffer.
   @param[in] Buffer             A pointer to the buffer to used to set the target variable.
-  
+
   @return Return the pointer to the Buffer that was set.
 
 **/
@@ -2160,7 +2154,7 @@ LibPatchPcdSetPtrAndSize (
   @param[in] MaximumDatumSize   The maximum size allowed for the PCD entry specified by PatchVariable.
   @param[in, out] SizeOfBuffer  A pointer to the size, in bytes, of Buffer.
   @param[in] Buffer             A pointer to the buffer to used to set the target variable.
-  
+
   @return The status of the set operation.
 
 **/
diff --git a/MdePkg/Include/Library/PciCf8Lib.h b/MdePkg/Include/Library/PciCf8Lib.h
index d77f406ebd16..41324e5b60b9 100644
--- a/MdePkg/Include/Library/PciCf8Lib.h
+++ b/MdePkg/Include/Library/PciCf8Lib.h
@@ -1,18 +1,12 @@
 /** @file
   Provides services to access PCI Configuration Space using the I/O ports 0xCF8 and 0xCFC.
-  
-  This library is identical to the PCI Library, except the access method for performing PCI 
-  configuration cycles must be through I/O ports 0xCF8 and 0xCFC.  This library only allows 
-  access to PCI Segment #0.
 
-Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
+  This library is identical to the PCI Library, except the access method for performing PCI
+  configuration cycles must be through I/O ports 0xCF8 and 0xCFC.  This library only allows
+  access to PCI Segment #0.
 
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -40,20 +34,20 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
 
 /**
-  Registers a PCI device so PCI configuration registers may be accessed after 
+  Registers a PCI device so PCI configuration registers may be accessed after
   SetVirtualAddressMap().
-  
-  Registers the PCI device specified by Address so all the PCI configuration registers 
+
+  Registers the PCI device specified by Address so all the PCI configuration registers
   associated with that PCI device may be accessed after SetVirtualAddressMap() is called.
-  
+
   If Address > 0x0FFFFFFF, then ASSERT().
   If the register specified by Address >= 0x100, then ASSERT().
 
   @param  Address Address that encodes the PCI Bus, Device, Function and
                   Register.
-  
+
   @retval RETURN_SUCCESS           The PCI device was registered for runtime access.
-  @retval RETURN_UNSUPPORTED       An attempt was made to call this function 
+  @retval RETURN_UNSUPPORTED       An attempt was made to call this function
                                    after ExitBootServices().
   @retval RETURN_UNSUPPORTED       The resources required to access the PCI device
                                    at runtime could not be mapped.
@@ -1033,7 +1027,7 @@ PciCf8BitFieldAndThenOr32 (
   Size into the buffer specified by Buffer. This function only allows the PCI
   configuration registers from a single PCI function to be read. Size is
   returned. When possible 32-bit PCI configuration read cycles are used to read
-  from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
+  from StartAddress to StartAddress + Size. Due to alignment restrictions, 8-bit
   and 16-bit PCI configuration read cycles may be used at the beginning and the
   end of the range.
 
@@ -1066,7 +1060,7 @@ PciCf8ReadBuffer (
   Size from the buffer specified by Buffer. This function only allows the PCI
   configuration registers from a single PCI function to be written. Size is
   returned. When possible 32-bit PCI configuration write cycles are used to
-  write from StartAdress to StartAddress + Size. Due to alignment restrictions,
+  write from StartAddress to StartAddress + Size. Due to alignment restrictions,
   8-bit and 16-bit PCI configuration write cycles may be used at the beginning
   and the end of the range.
 
diff --git a/MdePkg/Include/Library/PciExpressLib.h b/MdePkg/Include/Library/PciExpressLib.h
index 80e9d1279cfd..59bb8100e2d7 100644
--- a/MdePkg/Include/Library/PciExpressLib.h
+++ b/MdePkg/Include/Library/PciExpressLib.h
@@ -1,24 +1,20 @@
 /** @file
   Provides services to access PCI Configuration Space using the MMIO PCI Express window.
-  
-  This library is identical to the PCI Library, except the access method for performing PCI 
+
+  This library is identical to the PCI Library, except the access method for performing PCI
   configuration cycles must be through the 256 MB PCI Express MMIO window whose base address
   is defined by PcdPciExpressBaseAddress.
 
-Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
 #ifndef __PCI_EXPRESS_LIB_H__
 #define __PCI_EXPRESS_LIB_H__
 
+#include <IndustryStandard/PciExpress21.h>
+
 /**
   Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
   address that can be passed to the PCI Library functions.
@@ -35,24 +31,23 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   @return The encode PCI address.
 
 **/
-#define PCI_EXPRESS_LIB_ADDRESS(Bus,Device,Function,Offset) \
-  (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
+#define PCI_EXPRESS_LIB_ADDRESS(Bus,Device,Function,Offset) PCI_ECAM_ADDRESS ((Bus), (Device), (Function), (Offset))
 
 /**
-  Registers a PCI device so PCI configuration registers may be accessed after 
+  Registers a PCI device so PCI configuration registers may be accessed after
   SetVirtualAddressMap().
-  
-  Registers the PCI device specified by Address so all the PCI configuration 
-  registers associated with that PCI device may be accessed after SetVirtualAddressMap() 
+
+  Registers the PCI device specified by Address so all the PCI configuration
+  registers associated with that PCI device may be accessed after SetVirtualAddressMap()
   is called.
-  
+
   If Address > 0x0FFFFFFF, then ASSERT().
 
   @param  Address Address that encodes the PCI Bus, Device, Function and
                   Register.
-  
+
   @retval RETURN_SUCCESS           The PCI device was registered for runtime access.
-  @retval RETURN_UNSUPPORTED       An attempt was made to call this function 
+  @retval RETURN_UNSUPPORTED       An attempt was made to call this function
                                    after ExitBootServices().
   @retval RETURN_UNSUPPORTED       The resources required to access the PCI device
                                    at runtime could not be mapped.
@@ -1002,7 +997,7 @@ PciExpressBitFieldAndThenOr32 (
   Size into the buffer specified by Buffer. This function only allows the PCI
   configuration registers from a single PCI function to be read. Size is
   returned. When possible 32-bit PCI configuration read cycles are used to read
-  from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
+  from StartAddress to StartAddress + Size. Due to alignment restrictions, 8-bit
   and 16-bit PCI configuration read cycles may be used at the beginning and the
   end of the range.
 
@@ -1034,7 +1029,7 @@ PciExpressReadBuffer (
   Size from the buffer specified by Buffer. This function only allows the PCI
   configuration registers from a single PCI function to be written. Size is
   returned. When possible 32-bit PCI configuration write cycles are used to
-  write from StartAdress to StartAddress + Size. Due to alignment restrictions,
+  write from StartAddress to StartAddress + Size. Due to alignment restrictions,
   8-bit and 16-bit PCI configuration write cycles may be used at the beginning
   and the end of the range.
 
diff --git a/MdePkg/Include/Library/PciLib.h b/MdePkg/Include/Library/PciLib.h
index 1b1de2904d81..1b3c13eb2f1d 100644
--- a/MdePkg/Include/Library/PciLib.h
+++ b/MdePkg/Include/Library/PciLib.h
@@ -1,23 +1,17 @@
 /** @file
   Provides services to access PCI Configuration Space.
-  
-  These functions perform PCI configuration cycles using the default PCI configuration 
-  access method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, 
-  or it may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some 
-  alternate access method.  Modules will typically use the PCI Library for its PCI configuration 
-  accesses.  However, if a module requires a mix of PCI access methods, the PCI CF8 Library or 
-  PCI Express Library may be used in conjunction with the PCI Library.  The functionality of 
-  these three libraries is identical.  The PCI CF8 Library and PCI Express Library simply use 
-  explicit access methods.
 
-Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
+  These functions perform PCI configuration cycles using the default PCI configuration
+  access method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses,
+  or it may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some
+  alternate access method.  Modules will typically use the PCI Library for its PCI configuration
+  accesses.  However, if a module requires a mix of PCI access methods, the PCI CF8 Library or
+  PCI Express Library may be used in conjunction with the PCI Library.  The functionality of
+  these three libraries is identical.  The PCI CF8 Library and PCI Express Library simply use
+  explicit access methods.
 
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -41,19 +35,19 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   (((Register) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
 
 /**
-  Registers a PCI device so PCI configuration registers may be accessed after 
+  Registers a PCI device so PCI configuration registers may be accessed after
   SetVirtualAddressMap().
-  
-  Registers the PCI device specified by Address so all the PCI configuration registers 
+
+  Registers the PCI device specified by Address so all the PCI configuration registers
   associated with that PCI device may be accessed after SetVirtualAddressMap() is called.
-  
+
   If Address > 0x0FFFFFFF, then ASSERT().
 
   @param  Address Address that encodes the PCI Bus, Device, Function and
                   Register.
-  
+
   @retval RETURN_SUCCESS           The PCI device was registered for runtime access.
-  @retval RETURN_UNSUPPORTED       An attempt was made to call this function 
+  @retval RETURN_UNSUPPORTED       An attempt was made to call this function
                                    after ExitBootServices().
   @retval RETURN_UNSUPPORTED       The resources required to access the PCI device
                                    at runtime could not be mapped.
@@ -1003,7 +997,7 @@ PciBitFieldAndThenOr32 (
   Size into the buffer specified by Buffer. This function only allows the PCI
   configuration registers from a single PCI function to be read. Size is
   returned. When possible 32-bit PCI configuration read cycles are used to read
-  from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
+  from StartAddress to StartAddress + Size. Due to alignment restrictions, 8-bit
   and 16-bit PCI configuration read cycles may be used at the beginning and the
   end of the range.
 
@@ -1035,7 +1029,7 @@ PciReadBuffer (
   Size from the buffer specified by Buffer. This function only allows the PCI
   configuration registers from a single PCI function to be written. Size is
   returned. When possible 32-bit PCI configuration write cycles are used to
-  write from StartAdress to StartAddress + Size. Due to alignment restrictions,
+  write from StartAddress to StartAddress + Size. Due to alignment restrictions,
   8-bit and 16-bit PCI configuration write cycles may be used at the beginning
   and the end of the range.
 
diff --git a/MdePkg/Include/Library/PciSegmentInfoLib.h b/MdePkg/Include/Library/PciSegmentInfoLib.h
new file mode 100644
index 000000000000..228d75793b19
--- /dev/null
+++ b/MdePkg/Include/Library/PciSegmentInfoLib.h
@@ -0,0 +1,35 @@
+/** @file
+  Provides services to return segment information on a platform with multiple PCI segments.
+
+  This library is consumed by PciSegmentLib to support multiple segment PCI configuration access.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __PCI_SEGMENT_INFO_LIB__
+#define __PCI_SEGMENT_INFO_LIB__
+
+typedef struct {
+  UINT16               SegmentNumber;   ///< Segment number.
+  UINT64               BaseAddress;     ///< ECAM Base address.
+  UINT8                StartBusNumber;  ///< Start BUS number, for verifying the PCI Segment address.
+  UINT8                EndBusNumber;    ///< End BUS number, for verifying the PCI Segment address.
+} PCI_SEGMENT_INFO;
+
+/**
+  Return an array of PCI_SEGMENT_INFO holding the segment information.
+
+  Note: The returned array/buffer is owned by callee.
+
+  @param  Count  Return the count of segments.
+
+  @retval A callee owned array holding the segment information.
+**/
+PCI_SEGMENT_INFO *
+GetPciSegmentInfo (
+  UINTN  *Count
+  );
+
+#endif
diff --git a/MdePkg/Include/Library/PciSegmentLib.h b/MdePkg/Include/Library/PciSegmentLib.h
index aad95ca31455..1054a7c46564 100644
--- a/MdePkg/Include/Library/PciSegmentLib.h
+++ b/MdePkg/Include/Library/PciSegmentLib.h
@@ -1,11 +1,11 @@
 /** @file
   Provides services to access PCI Configuration Space on a platform with multiple PCI segments.
-  
+
   The PCI Segment Library function provide services to read, write, and modify the PCI configuration
-  registers on PCI root bridges on any supported PCI segment.  These library services take a single 
-  address parameter that encodes the PCI Segment, PCI Bus, PCI Device, PCI Function, and PCI Register.  
+  registers on PCI root bridges on any supported PCI segment.  These library services take a single
+  address parameter that encodes the PCI Segment, PCI Bus, PCI Device, PCI Function, and PCI Register.
   The layout of this address parameter is as follows:
-  
+
             PCI Register: Bits 0..11
             PCI Function  Bits 12..14
             PCI Device  Bits 15..19
@@ -13,24 +13,18 @@
             Reserved  Bits 28..31.  Must be 0.
             PCI Segment Bits 32..47
             Reserved  Bits 48..63.  Must be 0.
-            
+
   | Reserved (MBZ) | Segment | Reserved (MBZ) |     Bus     | Device | Function | Register |
   63             48  47    32  31           28 27         20 19    15 14      12 11         0
 
-  These functions perform PCI configuration cycles using the default PCI configuration access 
-  method.  This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, or it 
-  may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some alternate 
-  access method.  Modules will typically use the PCI Segment Library for its PCI configuration 
-  accesses when PCI Segments other than Segment #0 must be accessed.  
-
-Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
+  These functions perform PCI configuration cycles using the default PCI configuration access
+  method.  This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, or it
+  may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some alternate
+  access method.  Modules will typically use the PCI Segment Library for its PCI configuration
+  accesses when PCI Segments other than Segment #0 must be accessed.
 
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -71,16 +65,16 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   )
 
 /**
-  Register a PCI device so PCI configuration registers may be accessed after 
+  Register a PCI device so PCI configuration registers may be accessed after
   SetVirtualAddressMap().
-  
+
   If any reserved bits in Address are set, then ASSERT().
 
   @param  Address Address that encodes the PCI Bus, Device, Function and
                   Register.
-  
+
   @retval RETURN_SUCCESS           The PCI device was registered for runtime access.
-  @retval RETURN_UNSUPPORTED       An attempt was made to call this function 
+  @retval RETURN_UNSUPPORTED       An attempt was made to call this function
                                    after ExitBootServices().
   @retval RETURN_UNSUPPORTED       The resources required to access the PCI device
                                    at runtime could not be mapped.
@@ -99,9 +93,9 @@ PciSegmentRegisterForRuntimeAccess (
 
   Reads and returns the 8-bit PCI configuration register specified by Address.
   This function must guarantee that all PCI read and write operations are serialized.
-  
+
   If any reserved bits in Address are set, then ASSERT().
-  
+
   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 
   @return The 8-bit PCI configuration register specified by Address.
@@ -118,7 +112,7 @@ PciSegmentRead8 (
 
   Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
   Value is returned.  This function must guarantee that all PCI read and write operations are serialized.
-  
+
   If any reserved bits in Address are set, then ASSERT().
 
   @param  Address     Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@@ -142,7 +136,7 @@ PciSegmentWrite8 (
   and writes the result to the 8-bit PCI configuration register specified by Address.
   The value written to the PCI configuration register is returned.
   This function must guarantee that all PCI read and write operations are serialized.
-  
+
   If any reserved bits in Address are set, then ASSERT().
 
   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
@@ -184,18 +178,18 @@ PciSegmentAnd8 (
 /**
   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,
   followed a  bitwise OR with another 8-bit value.
-  
+
   Reads the 8-bit PCI configuration register specified by Address,
   performs a bitwise AND between the read result and the value specified by AndData,
   performs a bitwise OR between the result of the AND operation and the value specified by OrData,
   and writes the result to the 8-bit PCI configuration register specified by Address.
   The value written to the PCI configuration register is returned.
   This function must guarantee that all PCI read and write operations are serialized.
-  
+
   If any reserved bits in Address are set, then ASSERT().
 
   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
-  @param  AndData    The value to AND with the PCI configuration register.
+  @param  AndData   The value to AND with the PCI configuration register.
   @param  OrData    The value to OR with the PCI configuration register.
 
   @return The value written to the PCI configuration register.
@@ -345,8 +339,7 @@ PciSegmentBitFieldAnd8 (
 
 /**
   Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
-  bitwise OR, and writes the result back to the bit field in the
-  8-bit port.
+  bitwise OR, and writes the result back to the bit field in the 8-bit port.
 
   Reads the 8-bit PCI configuration register specified by Address, performs a
   bitwise AND followed by a bitwise OR between the read result and
@@ -389,10 +382,10 @@ PciSegmentBitFieldAndThenOr8 (
 
   Reads and returns the 16-bit PCI configuration register specified by Address.
   This function must guarantee that all PCI read and write operations are serialized.
-  
+
   If any reserved bits in Address are set, then ASSERT().
   If Address is not aligned on a 16-bit boundary, then ASSERT().
-  
+
   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 
   @return The 16-bit PCI configuration register specified by Address.
@@ -409,7 +402,7 @@ PciSegmentRead16 (
 
   Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.
   Value is returned.  This function must guarantee that all PCI read and write operations are serialized.
-  
+
   If any reserved bits in Address are set, then ASSERT().
   If Address is not aligned on a 16-bit boundary, then ASSERT().
 
@@ -431,11 +424,10 @@ PciSegmentWrite16 (
   a 16-bit value.
 
   Reads the 16-bit PCI configuration register specified by Address, performs a
-  bitwise OR between the read result and the value specified by
-  OrData, and writes the result to the 16-bit PCI configuration register
-  specified by Address. The value written to the PCI configuration register is
-  returned. This function must guarantee that all PCI read and write operations
-  are serialized.
+  bitwise OR between the read result and the value specified by OrData, and
+  writes the result to the 16-bit PCI configuration register specified by Address.
+  The value written to the PCI configuration register is returned. This function
+  must guarantee that all PCI read and write operations are serialized.
 
   If any reserved bits in Address are set, then ASSERT().
   If Address is not aligned on a 16-bit boundary, then ASSERT().
@@ -462,10 +454,10 @@ PciSegmentOr16 (
   and writes the result to the 16-bit PCI configuration register specified by Address.
   The value written to the PCI configuration register is returned.
   This function must guarantee that all PCI read and write operations are serialized.
-  
+
   If any reserved bits in Address are set, then ASSERT().
   If Address is not aligned on a 16-bit boundary, then ASSERT().
-  
+
   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
   @param  AndData   The value to AND with the PCI configuration register.
 
@@ -482,19 +474,19 @@ PciSegmentAnd16 (
 /**
   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,
   followed a  bitwise OR with another 16-bit value.
-  
+
   Reads the 16-bit PCI configuration register specified by Address,
   performs a bitwise AND between the read result and the value specified by AndData,
   performs a bitwise OR between the result of the AND operation and the value specified by OrData,
   and writes the result to the 16-bit PCI configuration register specified by Address.
   The value written to the PCI configuration register is returned.
   This function must guarantee that all PCI read and write operations are serialized.
-  
+
   If any reserved bits in Address are set, then ASSERT().
   If Address is not aligned on a 16-bit boundary, then ASSERT().
 
   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
-  @param  AndData    The value to AND with the PCI configuration register.
+  @param  AndData   The value to AND with the PCI configuration register.
   @param  OrData    The value to OR with the PCI configuration register.
 
   @return The value written to the PCI configuration register.
@@ -573,9 +565,15 @@ PciSegmentBitFieldWrite16 (
   );
 
 /**
-  Reads the 16-bit PCI configuration register specified by Address,
-  performs a bitwise OR between the read result and the value specified by OrData,
-  and writes the result to the 16-bit PCI configuration register specified by Address. 
+  Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, writes
+  the result back to the bit field in the 16-bit port.
+
+  Reads the 16-bit PCI configuration register specified by Address, performs a
+  bitwise OR between the read result and the value specified by
+  OrData, and writes the result to the 16-bit PCI configuration register
+  specified by Address. The value written to the PCI configuration register is
+  returned. This function must guarantee that all PCI read and write operations
+  are serialized. Extra left bits in OrData are stripped.
 
   If any reserved bits in Address are set, then ASSERT().
   If Address is not aligned on a 16-bit boundary, then ASSERT().
@@ -604,31 +602,31 @@ PciSegmentBitFieldOr16 (
   );
 
 /**
-  Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,
-  and writes the result back to the bit field in the 16-bit port.
+  Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
+  AND, writes the result back to the bit field in the 16-bit register.
+
+  Reads the 16-bit PCI configuration register specified by Address, performs a
+  bitwise AND between the read result and the value specified by AndData, and
+  writes the result to the 16-bit PCI configuration register specified by
+  Address. The value written to the PCI configuration register is returned.
+  This function must guarantee that all PCI read and write operations are
+  serialized. Extra left bits in AndData are stripped.
 
-  Reads the 16-bit PCI configuration register specified by Address,
-  performs a bitwise OR between the read result and the value specified by OrData,
-  and writes the result to the 16-bit PCI configuration register specified by Address.
-  The value written to the PCI configuration register is returned.
-  This function must guarantee that all PCI read and write operations are serialized.
-  Extra left bits in OrData are stripped.
-  
   If any reserved bits in Address are set, then ASSERT().
   If Address is not aligned on a 16-bit boundary, then ASSERT().
-  If StartBit is greater than 7, then ASSERT().
-  If EndBit is greater than 7, then ASSERT().
+  If StartBit is greater than 15, then ASSERT().
+  If EndBit is greater than 15, then ASSERT().
   If EndBit is less than StartBit, then ASSERT().
   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 
   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
   @param  StartBit  The ordinal of the least significant bit in the bit field.
-                    The ordinal of the least significant bit in a byte is bit 0.
+                    Range 0..15.
   @param  EndBit    The ordinal of the most significant bit in the bit field.
-                    The ordinal of the most significant bit in a byte is bit 7.
-  @param  AndData   The value to AND with the read value from the PCI configuration register.
+                    Range 0..15.
+  @param  AndData   The value to AND with the PCI configuration register.
 
-  @return The value written to the PCI configuration register.
+  @return The value written back to the PCI configuration register.
 
 **/
 UINT16
@@ -686,7 +684,7 @@ PciSegmentBitFieldAndThenOr16 (
 
   Reads and returns the 32-bit PCI configuration register specified by Address.
   This function must guarantee that all PCI read and write operations are serialized.
-  
+
   If any reserved bits in Address are set, then ASSERT().
   If Address is not aligned on a 32-bit boundary, then ASSERT().
 
@@ -706,7 +704,7 @@ PciSegmentRead32 (
 
   Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.
   Value is returned.  This function must guarantee that all PCI read and write operations are serialized.
-  
+
   If any reserved bits in Address are set, then ASSERT().
   If Address is not aligned on a 32-bit boundary, then ASSERT().
 
@@ -731,7 +729,7 @@ PciSegmentWrite32 (
   and writes the result to the 32-bit PCI configuration register specified by Address.
   The value written to the PCI configuration register is returned.
   This function must guarantee that all PCI read and write operations are serialized.
-  
+
   If any reserved bits in Address are set, then ASSERT().
   If Address is not aligned on a 32-bit boundary, then ASSERT().
 
@@ -756,7 +754,7 @@ PciSegmentOr32 (
   and writes the result to the 32-bit PCI configuration register specified by Address.
   The value written to the PCI configuration register is returned.
   This function must guarantee that all PCI read and write operations are serialized.
-  
+
   If any reserved bits in Address are set, then ASSERT().
   If Address is not aligned on a 32-bit boundary, then ASSERT().
 
@@ -776,14 +774,14 @@ PciSegmentAnd32 (
 /**
   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,
   followed a  bitwise OR with another 32-bit value.
-  
+
   Reads the 32-bit PCI configuration register specified by Address,
   performs a bitwise AND between the read result and the value specified by AndData,
   performs a bitwise OR between the result of the AND operation and the value specified by OrData,
   and writes the result to the 32-bit PCI configuration register specified by Address.
   The value written to the PCI configuration register is returned.
   This function must guarantee that all PCI read and write operations are serialized.
-  
+
   If any reserved bits in Address are set, then ASSERT().
   If Address is not aligned on a 32-bit boundary, then ASSERT().
 
@@ -906,7 +904,7 @@ PciSegmentBitFieldOr32 (
   Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
   AND, and writes the result back to the bit field in the 32-bit register.
 
-  
+
   Reads the 32-bit PCI configuration register specified by Address, performs a bitwise
   AND between the read result and the value specified by AndData, and writes the result
   to the 32-bit PCI configuration register specified by Address. The value written to
@@ -919,7 +917,7 @@ PciSegmentBitFieldOr32 (
   If EndBit is less than StartBit, then ASSERT().
   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 
-  @param  Address   PCI configuration register to write.
+  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
   @param  StartBit  The ordinal of the least significant bit in the bit field.
                     Range 0..31.
   @param  EndBit    The ordinal of the most significant bit in the bit field.
@@ -986,7 +984,7 @@ PciSegmentBitFieldAndThenOr32 (
   Size into the buffer specified by Buffer. This function only allows the PCI
   configuration registers from a single PCI function to be read. Size is
   returned. When possible 32-bit PCI configuration read cycles are used to read
-  from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
+  from StartAddress to StartAddress + Size. Due to alignment restrictions, 8-bit
   and 16-bit PCI configuration read cycles may be used at the beginning and the
   end of the range.
 
@@ -1018,7 +1016,7 @@ PciSegmentReadBuffer (
   Size from the buffer specified by Buffer. This function only allows the PCI
   configuration registers from a single PCI function to be written. Size is
   returned. When possible 32-bit PCI configuration write cycles are used to
-  write from StartAdress to StartAddress + Size. Due to alignment restrictions,
+  write from StartAddress to StartAddress + Size. Due to alignment restrictions,
   8-bit and 16-bit PCI configuration write cycles may be used at the beginning
   and the end of the range.
 
diff --git a/MdePkg/Include/Library/PeCoffExtraActionLib.h b/MdePkg/Include/Library/PeCoffExtraActionLib.h
index 1b73fc184ed1..97599d9a4783 100644
--- a/MdePkg/Include/Library/PeCoffExtraActionLib.h
+++ b/MdePkg/Include/Library/PeCoffExtraActionLib.h
@@ -1,16 +1,10 @@
 /** @file
   Provides services to perform additional actions when a PE/COFF image is loaded
-  or unloaded.  This is useful for environment where symbols need to be loaded 
+  or unloaded.  This is useful for environment where symbols need to be loaded
   and unloaded to support source level debugging.
 
-  Copyright (c) 2009, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -37,9 +31,9 @@ PeCoffLoaderRelocateImageExtraAction (
 /**
   Performs additional actions just before a PE/COFF image is unloaded.  Any resources
   that were allocated by PeCoffLoaderRelocateImageExtraAction() must be freed.
-  
+
   If ImageContext is NULL, then ASSERT().
-  
+
   @param  ImageContext  Pointer to the image context structure that describes the
                         PE/COFF image that is being unloaded.
 
diff --git a/MdePkg/Include/Library/PeCoffGetEntryPointLib.h b/MdePkg/Include/Library/PeCoffGetEntryPointLib.h
index 053d139c3366..99f69a989b25 100644
--- a/MdePkg/Include/Library/PeCoffGetEntryPointLib.h
+++ b/MdePkg/Include/Library/PeCoffGetEntryPointLib.h
@@ -1,14 +1,8 @@
 /** @file
   Provides a service to retrieve the PE/COFF entry point from a PE/COFF image.
 
-Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                            
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -59,7 +53,7 @@ PeCoffLoaderGetMachineType (
 
 /**
   Returns a pointer to the PDB file name for a PE/COFF image that has been
-  loaded into system memory with the PE/COFF Loader Library functions. 
+  loaded into system memory with the PE/COFF Loader Library functions.
 
   Returns the PDB file name for the PE/COFF image specified by Pe32Data.  If
   the PE/COFF image specified by Pe32Data is not a valid, then NULL is
@@ -101,4 +95,22 @@ PeCoffGetSizeOfHeaders (
   IN VOID     *Pe32Data
   );
 
+/**
+  Returns PE/COFF image base specified by the address in this PE/COFF image.
+
+  On DEBUG build, searches the PE/COFF image base forward the address in this
+  PE/COFF image and returns it.
+
+  @param  Address    Address located in one PE/COFF image.
+
+  @retval 0          RELEASE build or cannot find the PE/COFF image base.
+  @retval others     PE/COFF image base found.
+
+**/
+UINTN
+EFIAPI
+PeCoffSearchImageBase (
+  IN UINTN    Address
+  );
+
 #endif
diff --git a/MdePkg/Include/Library/PeCoffLib.h b/MdePkg/Include/Library/PeCoffLib.h
index 78b8b10ddefd..54fe513ed5d0 100644
--- a/MdePkg/Include/Library/PeCoffLib.h
+++ b/MdePkg/Include/Library/PeCoffLib.h
@@ -2,17 +2,11 @@
   Provides services to load and relocate a PE/COFF image.
 
   The PE/COFF Loader Library abstracts the implementation of a PE/COFF loader for
-  IA-32, x86, IPF, and EBC processor types. The library functions are memory-based 
+  IA-32, x86, IPF, and EBC processor types. The library functions are memory-based
   and can be ported easily to any environment.
-  
-Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                            
 
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -24,7 +18,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 // Return status codes from the PE/COFF Loader services
 //
 #define IMAGE_ERROR_SUCCESS                      0
-#define IMAGE_ERROR_IMAGE_READ                   1  
+#define IMAGE_ERROR_IMAGE_READ                   1
 #define IMAGE_ERROR_INVALID_PE_HEADER_SIGNATURE  2
 #define IMAGE_ERROR_INVALID_MACHINE_TYPE         3
 #define IMAGE_ERROR_INVALID_SUBSYSTEM            4
@@ -39,30 +33,30 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 /**
   Reads contents of a PE/COFF image.
 
-  A function of this type reads contents of the PE/COFF image specified by FileHandle. The read 
-  operation copies ReadSize bytes from the PE/COFF image starting at byte offset FileOffset into 
-  the buffer specified by Buffer. The size of the buffer actually read is returned in ReadSize.  
+  A function of this type reads contents of the PE/COFF image specified by FileHandle. The read
+  operation copies ReadSize bytes from the PE/COFF image starting at byte offset FileOffset into
+  the buffer specified by Buffer. The size of the buffer actually read is returned in ReadSize.
   If FileOffset specifies an offset past the end of the PE/COFF image, a ReadSize of 0 is returned.
-  A function of this type must be registered in the ImageRead field of a PE_COFF_LOADER_IMAGE_CONTEXT 
-  structure for the PE/COFF Loader Library service to function correctly.  This function abstracts access 
-  to a PE/COFF image so it can be implemented in an environment specific manner.  For example, SEC and PEI 
-  environments may access memory directly to read the contents of a PE/COFF image, and DXE or UEFI 
-  environments may require protocol services to read the contents of PE/COFF image 
+  A function of this type must be registered in the ImageRead field of a PE_COFF_LOADER_IMAGE_CONTEXT
+  structure for the PE/COFF Loader Library service to function correctly.  This function abstracts access
+  to a PE/COFF image so it can be implemented in an environment specific manner.  For example, SEC and PEI
+  environments may access memory directly to read the contents of a PE/COFF image, and DXE or UEFI
+  environments may require protocol services to read the contents of PE/COFF image
   stored on FLASH, disk, or network devices.
-  
+
   If FileHandle is not a valid handle, then ASSERT().
   If ReadSize is NULL, then ASSERT().
   If Buffer is NULL, then ASSERT().
 
   @param  FileHandle      Pointer to the file handle to read the PE/COFF image.
   @param  FileOffset      Offset into the PE/COFF image to begin the read operation.
-  @param  ReadSize        On input, the size in bytes of the requested read operation.  
+  @param  ReadSize        On input, the size in bytes of the requested read operation.
                           On output, the number of bytes actually read.
   @param  Buffer          Output buffer that contains the data read from the PE/COFF image.
-  
-  @retval RETURN_SUCCESS            The specified portion of the PE/COFF image was 
+
+  @retval RETURN_SUCCESS            The specified portion of the PE/COFF image was
                                     read and the size return in ReadSize.
-  @retval RETURN_DEVICE_ERROR       The specified portion of the PE/COFF image 
+  @retval RETURN_DEVICE_ERROR       The specified portion of the PE/COFF image
                                     could not be read due to a device error.
 
 **/
@@ -110,8 +104,8 @@ typedef struct {
   VOID                              *Handle;
   ///
   /// Caller allocated buffer of size FixupDataSize that can be optionally allocated
-  /// prior to calling PeCoffLoaderRelocateImage(). 
-  /// This buffer is filled with the information used to fix up the image. 
+  /// prior to calling PeCoffLoaderRelocateImage().
+  /// This buffer is filled with the information used to fix up the image.
   /// The fixups have been applied to the image and this entry is just for information.
   ///
   VOID                              *FixupData;
@@ -122,7 +116,7 @@ typedef struct {
   UINT32                            SectionAlignment;
   ///
   /// Set by PeCoffLoaderGetImageInfo() to offset to the PE/COFF header.
-  /// If the PE/COFF image does not start with a DOS header, this value is zero. 
+  /// If the PE/COFF image does not start with a DOS header, this value is zero.
   /// Otherwise, it's the offset to the PE/COFF header.
   ///
   UINT32                            PeCoffHeaderOffset;
@@ -137,7 +131,7 @@ typedef struct {
   VOID                              *CodeView;
   ///
   /// Set by PeCoffLoaderLoadImage() to point to the PDB entry contained in the CodeView area.
-  /// The PdbPointer points to the filename of the PDB file used for source-level debug of 
+  /// The PdbPointer points to the filename of the PDB file used for source-level debug of
   /// the image by a debugger.
   ///
   CHAR8                             *PdbPointer;
@@ -147,20 +141,20 @@ typedef struct {
   UINTN                             SizeOfHeaders;
   ///
   /// Not used by this library class. Other library classes that layer on  top of this library
-  /// class fill in this value as part of their GetImageInfo call. 
+  /// class fill in this value as part of their GetImageInfo call.
   /// This allows the caller of the library to know what type of memory needs to be allocated
   /// to load and relocate the image.
   ///
   UINT32                            ImageCodeMemoryType;
   ///
-  /// Not used by this library class. Other library classes that layer on top of this library 
+  /// Not used by this library class. Other library classes that layer on top of this library
   /// class fill in this value as part of their GetImageInfo call.
   /// This allows the caller of the library to know what type of memory needs to be allocated
   /// to load and relocate the image.
   ///
   UINT32                            ImageDataMemoryType;
   ///
-  /// Set by any of the library functions if they encounter an error. 
+  /// Set by any of the library functions if they encounter an error.
   ///
   UINT32                            ImageError;
   ///
@@ -182,7 +176,7 @@ typedef struct {
   ///
   BOOLEAN                           RelocationsStripped;
   ///
-  /// Set by PeCoffLoaderGetImageInfo() to TRUE if the image is a TE image. 
+  /// Set by PeCoffLoaderGetImageInfo() to TRUE if the image is a TE image.
   /// For a definition of the TE Image format, see the Platform Initialization Pre-EFI
   /// Initialization Core Interface Specification.
   ///
@@ -194,28 +188,28 @@ typedef struct {
   ///
   PHYSICAL_ADDRESS                  HiiResourceData;
   ///
-  /// Private storage for implementation specific data. 
+  /// Private storage for implementation specific data.
   ///
-  UINT64                            Context;      
+  UINT64                            Context;
 } PE_COFF_LOADER_IMAGE_CONTEXT;
 
 /**
   Retrieves information about a PE/COFF image.
 
-  Computes the PeCoffHeaderOffset, IsTeImage, ImageType, ImageAddress, ImageSize, 
-  DestinationAddress, RelocationsStripped, SectionAlignment, SizeOfHeaders, and 
-  DebugDirectoryEntryRva fields of the ImageContext structure.  
-  If ImageContext is NULL, then return RETURN_INVALID_PARAMETER.  
-  If the PE/COFF image accessed through the ImageRead service in the ImageContext 
-  structure is not a supported PE/COFF image type, then return RETURN_UNSUPPORTED.  
-  If any errors occur while computing the fields of ImageContext, 
-  then the error status is returned in the ImageError field of ImageContext.  
+  Computes the PeCoffHeaderOffset, IsTeImage, ImageType, ImageAddress, ImageSize,
+  DestinationAddress, RelocationsStripped, SectionAlignment, SizeOfHeaders, and
+  DebugDirectoryEntryRva fields of the ImageContext structure.
+  If ImageContext is NULL, then return RETURN_INVALID_PARAMETER.
+  If the PE/COFF image accessed through the ImageRead service in the ImageContext
+  structure is not a supported PE/COFF image type, then return RETURN_UNSUPPORTED.
+  If any errors occur while computing the fields of ImageContext,
+  then the error status is returned in the ImageError field of ImageContext.
   If the image is a TE image, then SectionAlignment is set to 0.
-  The ImageRead and Handle fields of ImageContext structure must be valid prior 
+  The ImageRead and Handle fields of ImageContext structure must be valid prior
   to invoking this service.
 
-  @param  ImageContext              The pointer to the image context structure that 
-                                    describes the PE/COFF image that needs to be 
+  @param  ImageContext              The pointer to the image context structure that
+                                    describes the PE/COFF image that needs to be
                                     examined by this function.
 
   @retval RETURN_SUCCESS            The information on the PE/COFF image was collected.
@@ -236,12 +230,12 @@ PeCoffLoaderGetImageInfo (
   ImageContext as the relocation base address.  Otherwise, use the DestinationAddress field
   of ImageContext as the relocation base address.  The caller must allocate the relocation
   fixup log buffer and fill in the FixupData field of ImageContext prior to calling this function.
-  
-  The ImageRead, Handle, PeCoffHeaderOffset, IsTeImage, Machine, ImageType, ImageAddress, 
-  ImageSize, DestinationAddress, RelocationsStripped, SectionAlignment, SizeOfHeaders, 
-  DebugDirectoryEntryRva, EntryPoint, FixupDataSize, CodeView, PdbPointer, and FixupData of 
+
+  The ImageRead, Handle, PeCoffHeaderOffset, IsTeImage, Machine, ImageType, ImageAddress,
+  ImageSize, DestinationAddress, RelocationsStripped, SectionAlignment, SizeOfHeaders,
+  DebugDirectoryEntryRva, EntryPoint, FixupDataSize, CodeView, PdbPointer, and FixupData of
   the ImageContext structure must be valid prior to invoking this service.
-    
+
   If ImageContext is NULL, then ASSERT().
 
   Note that if the platform does not maintain coherency between the instruction cache(s) and the data
@@ -272,10 +266,10 @@ PeCoffLoaderRelocateImage (
   specified by the ImageAddress and ImageSize fields of ImageContext.  The caller must allocate
   the load buffer and fill in the ImageAddress and ImageSize fields prior to calling this function.
   The EntryPoint, FixupDataSize, CodeView, PdbPointer and HiiResourceData fields of ImageContext are computed.
-  The ImageRead, Handle, PeCoffHeaderOffset, IsTeImage, Machine, ImageType, ImageAddress, ImageSize, 
-  DestinationAddress, RelocationsStripped, SectionAlignment, SizeOfHeaders, and DebugDirectoryEntryRva 
+  The ImageRead, Handle, PeCoffHeaderOffset, IsTeImage, Machine, ImageType, ImageAddress, ImageSize,
+  DestinationAddress, RelocationsStripped, SectionAlignment, SizeOfHeaders, and DebugDirectoryEntryRva
   fields of the ImageContext structure must be valid prior to invoking this service.
-  
+
   If ImageContext is NULL, then ASSERT().
 
   Note that if the platform does not maintain coherency between the instruction cache(s) and the data
@@ -305,25 +299,25 @@ PeCoffLoaderLoadImage (
 
 /**
   Reads contents of a PE/COFF image from a buffer in system memory.
-   
-  This is the default implementation of a PE_COFF_LOADER_READ_FILE function 
-  that assumes FileHandle pointer to the beginning of a PE/COFF image.   
-  This function reads contents of the PE/COFF image that starts at the system memory 
-  address specified by FileHandle. The read operation copies ReadSize bytes from the 
-  PE/COFF image starting at byte offset FileOffset into the buffer specified by Buffer.  
+
+  This is the default implementation of a PE_COFF_LOADER_READ_FILE function
+  that assumes FileHandle pointer to the beginning of a PE/COFF image.
+  This function reads contents of the PE/COFF image that starts at the system memory
+  address specified by FileHandle. The read operation copies ReadSize bytes from the
+  PE/COFF image starting at byte offset FileOffset into the buffer specified by Buffer.
   The size of the buffer actually read is returned in ReadSize.
-  
+
   If FileHandle is NULL, then ASSERT().
   If ReadSize is NULL, then ASSERT().
   If Buffer is NULL, then ASSERT().
 
   @param  FileHandle        The pointer to base of the input stream
   @param  FileOffset        Offset into the PE/COFF image to begin the read operation.
-  @param  ReadSize          On input, the size in bytes of the requested read operation.  
+  @param  ReadSize          On input, the size in bytes of the requested read operation.
                             On output, the number of bytes actually read.
   @param  Buffer            Output buffer that contains the data read from the PE/COFF image.
 
-  @retval RETURN_SUCCESS    The data is read from FileOffset from the Handle into 
+  @retval RETURN_SUCCESS    The data is read from FileOffset from the Handle into
                             the buffer.
 **/
 RETURN_STATUS
@@ -338,26 +332,26 @@ PeCoffLoaderImageReadFromMemory (
 
 /**
   Reapply fixups on a fixed up PE32/PE32+ image to allow virtual calling at EFI
-  runtime. 
-  
-  This function reapplies relocation fixups to the PE/COFF image specified by ImageBase 
-  and ImageSize so the image will execute correctly when the PE/COFF image is mapped 
-  to the address specified by VirtualImageBase. RelocationData must be identical 
-  to the FiuxupData buffer from the PE_COFF_LOADER_IMAGE_CONTEXT structure 
+  runtime.
+
+  This function reapplies relocation fixups to the PE/COFF image specified by ImageBase
+  and ImageSize so the image will execute correctly when the PE/COFF image is mapped
+  to the address specified by VirtualImageBase. RelocationData must be identical
+  to the FiuxupData buffer from the PE_COFF_LOADER_IMAGE_CONTEXT structure
   after this PE/COFF image was relocated with PeCoffLoaderRelocateImage().
 
   Note that if the platform does not maintain coherency between the instruction cache(s) and the data
   cache(s) in hardware, then the caller is responsible for performing cache maintenance operations
   prior to transferring control to a PE/COFF image that is loaded using this library.
 
-  @param  ImageBase          The base address of a PE/COFF image that has been loaded 
+  @param  ImageBase          The base address of a PE/COFF image that has been loaded
                              and relocated into system memory.
   @param  VirtImageBase      The request virtual address that the PE/COFF image is to
                              be fixed up for.
   @param  ImageSize          The size, in bytes, of the PE/COFF image.
-  @param  RelocationData     A pointer to the relocation data that was collected when the PE/COFF 
+  @param  RelocationData     A pointer to the relocation data that was collected when the PE/COFF
                              image was relocated using PeCoffLoaderRelocateImage().
-  
+
 **/
 VOID
 EFIAPI
@@ -370,15 +364,15 @@ PeCoffLoaderRelocateImageForRuntime (
 
 /**
   Unloads a loaded PE/COFF image from memory and releases its taken resource.
-  Releases any environment specific resources that were allocated when the image 
-  specified by ImageContext was loaded using PeCoffLoaderLoadImage(). 
- 
+  Releases any environment specific resources that were allocated when the image
+  specified by ImageContext was loaded using PeCoffLoaderLoadImage().
+
   For NT32 emulator, the PE/COFF image loaded by system needs to release.
-  For real platform, the PE/COFF image loaded by Core doesn't needs to be unloaded, 
+  For real platform, the PE/COFF image loaded by Core doesn't needs to be unloaded,
   this function can simply return RETURN_SUCCESS.
-  
+
   If ImageContext is NULL, then ASSERT().
-  
+
   @param  ImageContext              Pointer to the image context structure that describes the PE/COFF
                                     image to be unloaded.
 
diff --git a/MdePkg/Include/Library/PeiCoreEntryPoint.h b/MdePkg/Include/Library/PeiCoreEntryPoint.h
index 11c68bae675e..35b52f7375a6 100644
--- a/MdePkg/Include/Library/PeiCoreEntryPoint.h
+++ b/MdePkg/Include/Library/PeiCoreEntryPoint.h
@@ -1,14 +1,8 @@
 /** @file
   Module entry point library for PEI core.
 
-Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -34,7 +28,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
   @param SecCoreData  Points to a data structure containing information about the PEI
                       core's operating environment, such as the size and location of
-                      temporary RAM, the stack location and the BFV location. 
+                      temporary RAM, the stack location and the BFV location.
 
   @param PpiList      Points to a list of one or more PPI descriptors to be installed
                       initially by the PEI core. An empty PPI list consists of a single
@@ -46,7 +40,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
 **/
 VOID
-EFIAPI 
+EFIAPI
 _ModuleEntryPoint(
   IN CONST  EFI_SEC_PEI_HAND_OFF    *SecCoreData,
   IN CONST  EFI_PEI_PPI_DESCRIPTOR  *PpiList
@@ -59,7 +53,7 @@ _ModuleEntryPoint(
 
   @param SecCoreData  Points to a data structure containing information about the PEI core's
                       operating environment, such as the size and location of temporary RAM,
-                      the stack location and the BFV location. 
+                      the stack location and the BFV location.
 
   @param PpiList      Points to a list of one or more PPI descriptors to be installed
                       initially by the PEI core.  An empty PPI list consists of a single
@@ -84,7 +78,7 @@ EfiMain (
   This function must be called by the PEI Core once an initial PEI Services Table has been established.
   This function calls the set of library constructors for the set of library instances that a
   module depends on.  This include library instances that a module depends on directly and library
-  instances that a module depends on indirectly through other libraries.  
+  instances that a module depends on indirectly through other libraries.
   This function is autogenerated by build tools and those build tools are responsible for collecting
   the set of library instances, determining which ones have constructors, and calling the library
   constructors in the proper order based upon the dependencies of each of the library instances.
@@ -107,13 +101,13 @@ ProcessLibraryConstructorList (
   Autogenerated function that calls a set of module entry points.
 
   This function must be called by _ModuleEntryPoint().
-  This function calls the set of module entry points.  
+  This function calls the set of module entry points.
   This function is autogenerated by build tools and those build tools are responsible
   for collecting the module entry points and calling them in a specified order.
 
   @param SecCoreData    Points to a data structure containing information about the PEI
                         core's operating environment, such as the size and location of
-                        temporary RAM, the stack location and the BFV location. 
+                        temporary RAM, the stack location and the BFV location.
 
   @param PpiList        Points to a list of one or more PPI descriptors to be installed
                         initially by the PEI core. An empty PPI list consists of a single
@@ -121,7 +115,7 @@ ProcessLibraryConstructorList (
                         As part of its initialization phase, the PEI Foundation will add
                         these SEC-hosted PPIs to its PPI database such that both the PEI
                         Foundation and any modules can leverage the associated service calls
-                        and/or code in these early PPIs. 
+                        and/or code in these early PPIs.
   @param  Context       A pointer to a private context structure defined by the PEI Core
                         implementation. The implementation of _ModuleEntryPoint() must set
                         this parameter is NULL to indicate that this is the first PEI phase.
diff --git a/MdePkg/Include/Library/PeiServicesLib.h b/MdePkg/Include/Library/PeiServicesLib.h
index 5135834cc7c4..de14fb902ff4 100644
--- a/MdePkg/Include/Library/PeiServicesLib.h
+++ b/MdePkg/Include/Library/PeiServicesLib.h
@@ -1,14 +1,8 @@
 /** @file
   Provides library functions for all PEI Services.
 
-Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -73,7 +67,7 @@ EFIAPI
 PeiServicesLocatePpi (
   IN CONST EFI_GUID                   *Guid,
   IN UINTN                      Instance,
-  IN OUT EFI_PEI_PPI_DESCRIPTOR **PpiDescriptor,
+  IN OUT EFI_PEI_PPI_DESCRIPTOR **PpiDescriptor, OPTIONAL
   IN OUT VOID                   **Ppi
   );
 
@@ -225,7 +219,7 @@ PeiServicesFfsFindSectionData (
 
   @param  SectionType           The value of the section type to find.
   @param  SectionInstance       Section instance to find.
-  @param  FileHandle            A pointer to the file header that contains the set 
+  @param  FileHandle            A pointer to the file header that contains the set
                                 of sections to be searched.
   @param  SectionData           A pointer to the discovered section, if successful.
   @param  AuthenticationStatus  A pointer to the authentication status for this section.
@@ -264,16 +258,16 @@ PeiServicesInstallPeiMemory (
   );
 
 /**
-  This service enables PEIMs to allocate memory after the permanent memory has been installed by a
-  PEIM.
+  This service enables PEIMs to allocate memory.
 
   @param  MemoryType            Type of memory to allocate.
-  @param  Pages                 Number of pages to allocate.
+  @param  Pages                 The number of pages to allocate.
   @param  Memory                Pointer of memory allocated.
 
   @retval EFI_SUCCESS           The memory range was successfully allocated.
-  @retval EFI_INVALID_PARAMETER Type is not equal to AllocateAnyPages.
-  @retval EFI_NOT_AVAILABLE_YET Called with permanent memory not available.
+  @retval EFI_INVALID_PARAMETER Type is not equal to EfiLoaderCode, EfiLoaderData, EfiRuntimeServicesCode,
+                                EfiRuntimeServicesData, EfiBootServicesCode, EfiBootServicesData,
+                                EfiACPIReclaimMemory, EfiReservedMemoryType, or EfiACPIMemoryNVS.
   @retval EFI_OUT_OF_RESOURCES  The pages could not be allocated.
 
 **/
@@ -286,6 +280,25 @@ PeiServicesAllocatePages (
   );
 
 /**
+  This service enables PEIMs to free memory.
+
+  @param Memory                 Memory to be freed.
+  @param Pages                  The number of pages to free.
+
+  @retval EFI_SUCCESS           The requested pages were freed.
+  @retval EFI_INVALID_PARAMETER Memory is not a page-aligned address or Pages is invalid.
+  @retval EFI_NOT_FOUND         The requested memory pages were not allocated with
+                                AllocatePages().
+
+**/
+EFI_STATUS
+EFIAPI
+PeiServicesFreePages (
+  IN EFI_PHYSICAL_ADDRESS       Memory,
+  IN UINTN                      Pages
+  );
+
+/**
   This service allocates memory from the Hand-Off Block (HOB) heap.
 
   @param  Size                  The number of bytes to allocate from the pool.
@@ -318,9 +331,9 @@ PeiServicesResetSystem (
 
 
 /**
-  This service is a wrapper for the PEI Service FfsFindByName(), except the pointer to the PEI Services 
-  Table has been removed.  See the Platform Initialization Pre-EFI Initialization Core Interface 
-  Specification for details. 
+  This service is a wrapper for the PEI Service FfsFindByName(), except the pointer to the PEI Services
+  Table has been removed.  See the Platform Initialization Pre-EFI Initialization Core Interface
+  Specification for details.
 
   @param FileName       A pointer to the name of the file to
                         find within the firmware volume.
@@ -328,7 +341,7 @@ PeiServicesResetSystem (
   @param VolumeHandle   The firmware volume to search FileHandle
                         Upon exit, points to the found file's
                         handle or NULL if it could not be found.
-  @param FileHandle     Pointer to found file handle 
+  @param FileHandle     Pointer to found file handle
 
   @retval EFI_SUCCESS             File was found.
 
@@ -348,9 +361,9 @@ PeiServicesFfsFindFileByName (
 
 
 /**
-  This service is a wrapper for the PEI Service FfsGetFileInfo(), except the pointer to the PEI Services 
-  Table has been removed.  See the Platform Initialization Pre-EFI Initialization Core Interface 
-  Specification for details. 
+  This service is a wrapper for the PEI Service FfsGetFileInfo(), except the pointer to the PEI Services
+  Table has been removed.  See the Platform Initialization Pre-EFI Initialization Core Interface
+  Specification for details.
 
   @param FileHandle   Handle of the file.
 
@@ -358,15 +371,15 @@ PeiServicesFfsFindFileByName (
                       information.
 
   @retval EFI_SUCCESS             File information returned.
-  
+
   @retval EFI_INVALID_PARAMETER   If FileHandle does not
                                   represent a valid file.
-  
+
   @retval EFI_INVALID_PARAMETER   If FileInfo is NULL.
-  
+
 **/
 EFI_STATUS
-EFIAPI 
+EFIAPI
 PeiServicesFfsGetFileInfo (
   IN CONST  EFI_PEI_FILE_HANDLE   FileHandle,
   OUT EFI_FV_FILE_INFO            *FileInfo
@@ -383,12 +396,12 @@ PeiServicesFfsGetFileInfo (
                       information.
 
   @retval EFI_SUCCESS             File information returned.
-  
+
   @retval EFI_INVALID_PARAMETER   If FileHandle does not
                                   represent a valid file.
-  
+
   @retval EFI_INVALID_PARAMETER   If FileInfo is NULL.
-  
+
 **/
 EFI_STATUS
 EFIAPI
@@ -398,9 +411,9 @@ PeiServicesFfsGetFileInfo2 (
   );
 
 /**
-  This service is a wrapper for the PEI Service FfsGetVolumeInfo(), except the pointer to the PEI Services 
-  Table has been removed.  See the Platform Initialization Pre-EFI Initialization Core Interface 
-  Specification for details. 
+  This service is a wrapper for the PEI Service FfsGetVolumeInfo(), except the pointer to the PEI Services
+  Table has been removed.  See the Platform Initialization Pre-EFI Initialization Core Interface
+  Specification for details.
 
   @param VolumeHandle   Handle of the volume.
 
@@ -408,10 +421,10 @@ PeiServicesFfsGetFileInfo2 (
                         information.
 
   @retval EFI_SUCCESS             File information returned.
-  
+
   @retval EFI_INVALID_PARAMETER   If FileHandle does not
                                   represent a valid file.
-  
+
   @retval EFI_INVALID_PARAMETER   If FileInfo is NULL.
 
 **/
@@ -424,13 +437,13 @@ PeiServicesFfsGetVolumeInfo (
 
 
 /**
-  This service is a wrapper for the PEI Service RegisterForShadow(), except the pointer to the PEI Services 
-  Table has been removed.  See the Platform Initialization Pre-EFI Initialization Core Interface 
-  Specification for details. 
+  This service is a wrapper for the PEI Service RegisterForShadow(), except the pointer to the PEI Services
+  Table has been removed.  See the Platform Initialization Pre-EFI Initialization Core Interface
+  Specification for details.
 
   @param FileHandle   PEIM's file handle. Must be the currently
                       executing PEIM.
-  
+
   @retval EFI_SUCCESS   The PEIM was successfully registered for
                         shadowing.
 
@@ -448,25 +461,25 @@ PeiServicesRegisterForShadow (
 
 /**
   Install a EFI_PEI_FIRMWARE_VOLUME_INFO_PPI instance so the PEI Core will be notified about a new firmware volume.
-  
-  This function allocates, initializes, and installs a new EFI_PEI_FIRMWARE_VOLUME_INFO_PPI using 
+
+  This function allocates, initializes, and installs a new EFI_PEI_FIRMWARE_VOLUME_INFO_PPI using
   the parameters passed in to initialize the fields of the EFI_PEI_FIRMWARE_VOLUME_INFO_PPI instance.
   If the resources can not be allocated for EFI_PEI_FIRMWARE_VOLUME_INFO_PPI, then ASSERT().
   If the EFI_PEI_FIRMWARE_VOLUME_INFO_PPI can not be installed, then ASSERT().
 
-  
+
   @param  FvFormat             Unique identifier of the format of the memory-mapped firmware volume.
-                               This parameter is optional and may be NULL.  
+                               This parameter is optional and may be NULL.
                                If NULL is specified, the EFI_FIRMWARE_FILE_SYSTEM2_GUID format is assumed.
-  @param  FvInfo               Points to a buffer which allows the EFI_PEI_FIRMWARE_VOLUME_PPI to process the volume. 
-                               The format of this buffer is specific to the FvFormat. For memory-mapped firmware volumes, 
+  @param  FvInfo               Points to a buffer which allows the EFI_PEI_FIRMWARE_VOLUME_PPI to process the volume.
+                               The format of this buffer is specific to the FvFormat. For memory-mapped firmware volumes,
                                this typically points to the first byte of the firmware volume.
-  @param  FvInfoSize           The size, in bytes, of FvInfo. For memory-mapped firmware volumes, 
+  @param  FvInfoSize           The size, in bytes, of FvInfo. For memory-mapped firmware volumes,
                                this is typically the size of the firmware volume.
-  @param  ParentFvName         If the new firmware volume originated from a file in a different firmware volume, 
+  @param  ParentFvName         If the new firmware volume originated from a file in a different firmware volume,
                                then this parameter specifies the GUID name of the originating firmware volume.
                                Otherwise, this parameter must be NULL.
-  @param  ParentFileName       If the new firmware volume originated from a file in a different firmware volume, 
+  @param  ParentFileName       If the new firmware volume originated from a file in a different firmware volume,
                                then this parameter specifies the GUID file name of the originating firmware file.
                                Otherwise, this parameter must be NULL.
 **/
@@ -521,4 +534,26 @@ PeiServicesInstallFvInfo2Ppi (
   IN       UINT32                  AuthenticationStatus
   );
 
+/**
+  Resets the entire platform.
+
+  @param[in] ResetType      The type of reset to perform.
+  @param[in] ResetStatus    The status code for the reset.
+  @param[in] DataSize       The size, in bytes, of ResetData.
+  @param[in] ResetData      For a ResetType of EfiResetCold, EfiResetWarm, or EfiResetShutdown
+                            the data buffer starts with a Null-terminated string, optionally
+                            followed by additional binary data. The string is a description
+                            that the caller may use to further indicate the reason for the
+                            system reset.
+
+**/
+VOID
+EFIAPI
+PeiServicesResetSystem2 (
+  IN EFI_RESET_TYPE     ResetType,
+  IN EFI_STATUS         ResetStatus,
+  IN UINTN              DataSize,
+  IN VOID               *ResetData OPTIONAL
+  );
+
 #endif
diff --git a/MdePkg/Include/Library/PeiServicesTablePointerLib.h b/MdePkg/Include/Library/PeiServicesTablePointerLib.h
index f1aa0d4bf349..eb81338943c1 100644
--- a/MdePkg/Include/Library/PeiServicesTablePointerLib.h
+++ b/MdePkg/Include/Library/PeiServicesTablePointerLib.h
@@ -1,14 +1,8 @@
 /** @file
   Provides a service to retrieve a pointer to the PEI Services Table.
 
-Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -18,10 +12,10 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 /**
   Retrieves the cached value of the PEI Services Table pointer.
 
-  Returns the cached value of the PEI Services Table pointer in a CPU specific manner 
-  as specified in the CPU binding section of the Platform Initialization Pre-EFI 
+  Returns the cached value of the PEI Services Table pointer in a CPU specific manner
+  as specified in the CPU binding section of the Platform Initialization Pre-EFI
   Initialization Core Interface Specification.
-  
+
   If the cached PEI Services Table pointer is NULL, then ASSERT().
 
   @return  The pointer to PeiServices.
@@ -34,14 +28,14 @@ GetPeiServicesTablePointer (
   );
 
 /**
-  Caches a pointer PEI Services Table. 
- 
-  Caches the pointer to the PEI Services Table specified by PeiServicesTablePointer 
-  in a CPU specific manner as specified in the CPU binding section of the Platform Initialization 
-  Pre-EFI Initialization Core Interface Specification. 
-  
+  Caches a pointer PEI Services Table.
+
+  Caches the pointer to the PEI Services Table specified by PeiServicesTablePointer
+  in a CPU specific manner as specified in the CPU binding section of the Platform Initialization
+  Pre-EFI Initialization Core Interface Specification.
+
   If PeiServicesTablePointer is NULL, then ASSERT().
-  
+
   @param    PeiServicesTablePointer   The address of PeiServices pointer.
 **/
 VOID
@@ -51,16 +45,16 @@ SetPeiServicesTablePointer (
   );
 
 /**
-  Perform CPU specific actions required to migrate the PEI Services Table 
+  Perform CPU specific actions required to migrate the PEI Services Table
   pointer from temporary RAM to permanent RAM.
 
-  For IA32 CPUs, the PEI Services Table pointer is stored in the 4 bytes 
+  For IA32 CPUs, the PEI Services Table pointer is stored in the 4 bytes
   immediately preceding the Interrupt Descriptor Table (IDT) in memory.
-  For X64 CPUs, the PEI Services Table pointer is stored in the 8 bytes 
+  For X64 CPUs, the PEI Services Table pointer is stored in the 8 bytes
   immediately preceding the Interrupt Descriptor Table (IDT) in memory.
   For Itanium and ARM CPUs, a the PEI Services Table Pointer is stored in
-  a dedicated CPU register.  This means that there is no memory storage 
-  associated with storing the PEI Services Table pointer, so no additional 
+  a dedicated CPU register.  This means that there is no memory storage
+  associated with storing the PEI Services Table pointer, so no additional
   migration actions are required for Itanium or ARM CPUs.
 
 **/
diff --git a/MdePkg/Include/Library/PeimEntryPoint.h b/MdePkg/Include/Library/PeimEntryPoint.h
index 8364a0582e36..61473aafdd9d 100644
--- a/MdePkg/Include/Library/PeimEntryPoint.h
+++ b/MdePkg/Include/Library/PeimEntryPoint.h
@@ -1,14 +1,8 @@
 /** @file
   Module entry point library for PEIM.
 
-Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -16,7 +10,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #define __MODULE_ENTRY_POINT_H__
 
 ///
-/// Declare the EFI/UEFI Specification Revision to which this driver is implemented 
+/// Declare the EFI/UEFI Specification Revision to which this driver is implemented
 ///
 extern CONST UINT32       _gPeimRevision;
 
@@ -24,11 +18,11 @@ extern CONST UINT32       _gPeimRevision;
 /**
   The entry point of PE/COFF Image for a PEIM.
 
-  This function is the entry point for a PEIM.  This function must call ProcessLibraryConstructorList() 
+  This function is the entry point for a PEIM.  This function must call ProcessLibraryConstructorList()
   and ProcessModuleEntryPointList().  The return value from ProcessModuleEntryPointList() is returned.
   If _gPeimRevision is not zero and PeiServices->Hdr.Revision is less than _gPeimRevison, then ASSERT().
 
-  @param  FileHandle  Handle of the file being invoked. 
+  @param  FileHandle  Handle of the file being invoked.
   @param  PeiServices Describes the list of possible PEI Services.
 
   @retval  EFI_SUCCESS   The PEIM executed normally.
@@ -44,10 +38,10 @@ _ModuleEntryPoint (
 
 /**
   Required by the EBC compiler and identical in functionality to _ModuleEntryPoint().
-  
+
   This function is required to call _ModuleEntryPoint() passing in FileHandle and PeiServices.
 
-  @param  FileHandle  Handle of the file being invoked. 
+  @param  FileHandle  Handle of the file being invoked.
   @param  PeiServices Describes the list of possible PEI Services.
 
   @retval EFI_SUCCESS  The PEIM executed normally.
@@ -68,7 +62,7 @@ EfiMain (
   This function must be called by _ModuleEntryPoint().
   This function calls the set of library constructors for the set of library instances that a
   module depends on. This includes library instances that a module depends on directly and library
-  instances that a module depends on indirectly through other libraries.  
+  instances that a module depends on indirectly through other libraries.
   This function is autogenerated by build tools and those build tools are responsible for collecting
   the set of library instances, determine which ones have constructors, and calling the library
   constructors in the proper order based upon each of the library instances own dependencies.
@@ -88,16 +82,16 @@ ProcessLibraryConstructorList (
   Autogenerated function that calls a set of module entry points.
 
   This function must be called by _ModuleEntryPoint().
-  This function calls the set of module entry points.  
+  This function calls the set of module entry points.
   This function is autogenerated by build tools and those build tools are responsible
   for collecting the module entry points and calling them in a specified order.
 
-  @param  FileHandle  Handle of the file being invoked. 
+  @param  FileHandle  Handle of the file being invoked.
   @param  PeiServices Describes the list of possible PEI Services.
 
   @retval EFI_SUCCESS  The PEIM executed normally.
   @retval !EFI_SUCCESS The PEIM failed to execute normally.
- 
+
 **/
 EFI_STATUS
 EFIAPI
diff --git a/MdePkg/Include/Library/PerformanceLib.h b/MdePkg/Include/Library/PerformanceLib.h
index 28dfc6a8d40b..96b1e000f0e6 100644
--- a/MdePkg/Include/Library/PerformanceLib.h
+++ b/MdePkg/Include/Library/PerformanceLib.h
@@ -1,14 +1,8 @@
 /** @file
   Provides services to log the execution times and retrieve them later.
 
-Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -20,9 +14,48 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 ///
 #define PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED  0x00000001
 
+//
+// Public Progress Identifiers for Event Records.
+//
+#define PERF_EVENT_ID                   0x00
+
+#define MODULE_START_ID                 0x01
+#define MODULE_END_ID                   0x02
+#define MODULE_LOADIMAGE_START_ID       0x03
+#define MODULE_LOADIMAGE_END_ID         0x04
+#define MODULE_DB_START_ID              0x05
+#define MODULE_DB_END_ID                0x06
+#define MODULE_DB_SUPPORT_START_ID      0x07
+#define MODULE_DB_SUPPORT_END_ID        0x08
+#define MODULE_DB_STOP_START_ID         0x09
+#define MODULE_DB_STOP_END_ID           0x0A
+
+#define PERF_EVENTSIGNAL_START_ID       0x10
+#define PERF_EVENTSIGNAL_END_ID         0x11
+#define PERF_CALLBACK_START_ID          0x20
+#define PERF_CALLBACK_END_ID            0x21
+#define PERF_FUNCTION_START_ID          0x30
+#define PERF_FUNCTION_END_ID            0x31
+#define PERF_INMODULE_START_ID          0x40
+#define PERF_INMODULE_END_ID            0x41
+#define PERF_CROSSMODULE_START_ID       0x50
+#define PERF_CROSSMODULE_END_ID         0x51
+
+//
+// Declare bits for PcdPerformanceLibraryPropertyMask and
+// also used as the Type parameter of LogPerformanceMeasurementEnabled().
+//
+#define PERF_CORE_START_IMAGE            0x0002
+#define PERF_CORE_LOAD_IMAGE             0x0004
+#define PERF_CORE_DB_SUPPORT             0x0008
+#define PERF_CORE_DB_START               0x0010
+#define PERF_CORE_DB_STOP                0x0020
+
+#define PERF_GENERAL_TYPE                0x0040
+
 /**
-  Creates a record for the beginning of a performance measurement. 
-  
+  Creates a record for the beginning of a performance measurement.
+
   Creates a record that contains the Handle, Token, and Module.
   If TimeStamp is not zero, then TimeStamp is added to the record as the start time.
   If TimeStamp is zero, then this function reads the current time stamp
@@ -51,8 +84,8 @@ StartPerformanceMeasurement (
   );
 
 /**
-  Fills in the end time of a performance measurement. 
-  
+  Fills in the end time of a performance measurement.
+
   Looks up the record that matches Handle, Token, and Module.
   If the record can not be found then return RETURN_NOT_FOUND.
   If the record is found and TimeStamp is not zero,
@@ -83,7 +116,7 @@ EndPerformanceMeasurement (
   );
 
 /**
-  Attempts to retrieve a performance measurement log entry from the performance measurement log. 
+  Attempts to retrieve a performance measurement log entry from the performance measurement log.
   It can also retrieve the log created by StartPerformanceMeasurementEx and EndPerformanceMeasurementEx,
   and then eliminate the Identifier.
 
@@ -108,9 +141,9 @@ EndPerformanceMeasurement (
                                   0, then the first performance measurement log entry is retrieved.
                                   On exit, the key of the next performance lof entry entry.
   @param  Handle                  Pointer to environment specific context used to identify the component
-                                  being measured.  
+                                  being measured.
   @param  Token                   Pointer to a Null-terminated ASCII string that identifies the component
-                                  being measured. 
+                                  being measured.
   @param  Module                  Pointer to a Null-terminated ASCII string that identifies the module
                                   being measured.
   @param  StartTimeStamp          Pointer to the 64-bit time stamp that was recorded when the measurement
@@ -124,7 +157,7 @@ EndPerformanceMeasurement (
 UINTN
 EFIAPI
 GetPerformanceMeasurement (
-  IN  UINTN       LogEntryKey, 
+  IN  UINTN       LogEntryKey,
   OUT CONST VOID  **Handle,
   OUT CONST CHAR8 **Token,
   OUT CONST CHAR8 **Module,
@@ -244,7 +277,7 @@ EndPerformanceMeasurementEx (
 UINTN
 EFIAPI
 GetPerformanceMeasurementEx (
-  IN  UINTN       LogEntryKey, 
+  IN  UINTN       LogEntryKey,
   OUT CONST VOID  **Handle,
   OUT CONST CHAR8 **Token,
   OUT CONST CHAR8 **Module,
@@ -254,8 +287,8 @@ GetPerformanceMeasurementEx (
   );
 
 /**
-  Returns TRUE if the performance measurement macros are enabled. 
-  
+  Returns TRUE if the performance measurement macros are enabled.
+
   This function returns TRUE if the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of
   PcdPerformanceLibraryPropertyMask is set.  Otherwise FALSE is returned.
 
@@ -271,6 +304,373 @@ PerformanceMeasurementEnabled (
   VOID
   );
 
+
+/**
+  Check whether the specified performance measurement can be logged.
+
+  This function returns TRUE when the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set
+  and the Type disable bit in PcdPerformanceLibraryPropertyMask is not set.
+
+  @param Type        - Type of the performance measurement entry.
+
+  @retval TRUE         The performance measurement can be logged.
+  @retval FALSE        The performance measurement can NOT be logged.
+
+**/
+BOOLEAN
+EFIAPI
+LogPerformanceMeasurementEnabled (
+  IN  CONST UINTN        Type
+  );
+
+/**
+  Create performance record with event description.
+
+  @param CallerIdentifier - Image handle or pointer to caller ID GUID
+  @param Guid             - Pointer to a GUID.
+                            Used for event signal perf and callback perf to cache the event guid.
+  @param String           - Pointer to a string describing the measurement
+  @param Address          - Pointer to a location in memory relevant to the measurement.
+  @param Identifier       - Performance identifier describing the type of measurement.
+
+  @retval RETURN_SUCCESS           - Successfully created performance record
+  @retval RETURN_OUT_OF_RESOURCES  - Ran out of space to store the records
+  @retval RETURN_INVALID_PARAMETER - Invalid parameter passed to function - NULL
+                                     pointer or invalid Identifier.
+
+**/
+RETURN_STATUS
+EFIAPI
+LogPerformanceMeasurement (
+  IN CONST VOID   *CallerIdentifier, OPTIONAL
+  IN CONST VOID   *Guid,    OPTIONAL
+  IN CONST CHAR8  *String,  OPTIONAL
+  IN UINT64       Address,  OPTIONAL
+  IN UINT32       Identifier
+  );
+
+/**
+  Begin Macro to measure the performance of StartImage in core.
+
+  If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+  and the BIT1(dsiable PERF_CORE_START_IMAGE) of PcdPerformanceLibraryPropertyMask is not set.
+  then LogPerformanceMeasurement() is called.
+
+**/
+#define PERF_START_IMAGE_BEGIN(ModuleHandle) \
+  do { \
+    if (LogPerformanceMeasurementEnabled (PERF_CORE_START_IMAGE)) { \
+      LogPerformanceMeasurement (ModuleHandle, NULL, NULL, 0, MODULE_START_ID); \
+    } \
+  } while (FALSE)
+
+/**
+  End Macro to measure the performance of StartImage in core.
+
+  If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+  and the BIT1 (dsiable PERF_CORE_START_IMAGE)of PcdPerformanceLibraryPropertyMask is not set.
+  then LogPerformanceMeasurement() is called.
+
+**/
+#define PERF_START_IMAGE_END(ModuleHandle) \
+  do { \
+    if (LogPerformanceMeasurementEnabled (PERF_CORE_START_IMAGE)) { \
+      LogPerformanceMeasurement (ModuleHandle, NULL, NULL, 0, MODULE_END_ID); \
+    } \
+  } while (FALSE)
+
+/**
+  Begin Macro to measure the performance of LoadImage in core.
+
+  If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+  and the BIT2 (dsiable PERF_CORE_LOAD_IAMGE) of PcdPerformanceLibraryPropertyMask is not set.
+  then LogPerformanceMeasurement() is called.
+
+**/
+#define PERF_LOAD_IMAGE_BEGIN(ModuleHandle) \
+  do { \
+    if (LogPerformanceMeasurementEnabled (PERF_CORE_LOAD_IMAGE)) { \
+      LogPerformanceMeasurement (ModuleHandle, NULL, NULL, 0, MODULE_LOADIMAGE_START_ID); \
+    } \
+  } while (FALSE)
+
+/**
+  End Macro to measure the performance of LoadImage in core.
+
+  If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+  and the BIT2 (dsiable PERF_CORE_LOAD_IAMGE) of PcdPerformanceLibraryPropertyMask is not set.
+  then LogPerformanceMeasurement() is called.
+
+**/
+#define PERF_LOAD_IMAGE_END(ModuleHandle) \
+  do { \
+    if (LogPerformanceMeasurementEnabled (PERF_CORE_LOAD_IMAGE)) { \
+      LogPerformanceMeasurement (ModuleHandle, NULL, NULL, 0, MODULE_LOADIMAGE_END_ID); \
+    } \
+  } while (FALSE)
+
+/**
+  Start Macro to measure the performance of DriverBinding Support in core.
+
+  If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+  and the BIT3 (dsiable PERF_CORE_DB_SUPPORT) of PcdPerformanceLibraryPropertyMask is not set.
+  then LogPerformanceMeasurement() is called.
+
+**/
+#define PERF_DRIVER_BINDING_SUPPORT_BEGIN(ModuleHandle, ControllerHandle) \
+  do { \
+    if (LogPerformanceMeasurementEnabled (PERF_CORE_DB_SUPPORT)) { \
+      LogPerformanceMeasurement (ModuleHandle, NULL, NULL, (UINT64)(UINTN)ControllerHandle, MODULE_DB_SUPPORT_START_ID); \
+    } \
+  } while (FALSE)
+
+/**
+  End Macro to measure the performance of DriverBinding Support in core.
+
+  If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+  and the BIT3 (dsiable PERF_CORE_DB_SUPPORT) of PcdPerformanceLibraryPropertyMask is not set.
+  then LogPerformanceMeasurement() is called.
+
+**/
+#define PERF_DRIVER_BINDING_SUPPORT_END(ModuleHandle, ControllerHandle) \
+  do { \
+    if (LogPerformanceMeasurementEnabled (PERF_CORE_DB_SUPPORT)) { \
+      LogPerformanceMeasurement (ModuleHandle, NULL, NULL, (UINT64)(UINTN)ControllerHandle, MODULE_DB_SUPPORT_END_ID); \
+    } \
+  } while (FALSE)
+
+/**
+  Begin Macro to measure the performance of DriverBinding Start in core.
+
+  If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+  and the BIT4 (dsiable PERF_CORE_DB_START) of PcdPerformanceLibraryPropertyMask is not set.
+  then LogPerformanceMeasurement() is called.
+
+**/
+#define PERF_DRIVER_BINDING_START_BEGIN(ModuleHandle, ControllerHandle) \
+  do { \
+    if (LogPerformanceMeasurementEnabled (PERF_CORE_DB_START)) { \
+      LogPerformanceMeasurement (ModuleHandle, NULL, NULL, (UINT64)(UINTN)ControllerHandle, MODULE_DB_START_ID); \
+    } \
+  } while (FALSE)
+
+/**
+  End Macro to measure the performance of DriverBinding Start in core.
+
+  If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+  and the BIT4 (dsiable PERF_CORE_DB_START) of PcdPerformanceLibraryPropertyMask is not set.
+  then LogPerformanceMeasurement() is called.
+
+**/
+#define PERF_DRIVER_BINDING_START_END(ModuleHandle, ControllerHandle) \
+  do { \
+    if (LogPerformanceMeasurementEnabled (PERF_CORE_DB_START)) { \
+      LogPerformanceMeasurement (ModuleHandle, NULL, NULL, (UINT64)(UINTN)ControllerHandle, MODULE_DB_END_ID); \
+    } \
+  } while (FALSE)
+
+/**
+  Start Macro to measure the performance of DriverBinding Stop in core.
+
+  If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+  and the BIT5 (dsiable PERF_CORE_DB_STOP) of PcdPerformanceLibraryPropertyMask is not set.
+  then LogPerformanceMeasurement() is called.
+
+**/
+#define PERF_DRIVER_BINDING_STOP_BEGIN(ModuleHandle, ControllerHandle) \
+  do { \
+    if (LogPerformanceMeasurementEnabled (PERF_CORE_DB_STOP)) { \
+      LogPerformanceMeasurement (ModuleHandle, NULL, NULL, (UINT64)(UINTN)ControllerHandle, MODULE_DB_STOP_START_ID); \
+    } \
+  } while (FALSE)
+
+/**
+  End Macro to measure the performance of DriverBinding Stop in core.
+
+  If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+  and the BIT5 (dsiable PERF_CORE_DB_STOP) of PcdPerformanceLibraryPropertyMask is not set.
+  then LogPerformanceMeasurement() is called.
+
+**/
+#define PERF_DRIVER_BINDING_STOP_END(ModuleHandle, ControllerHandle) \
+  do { \
+    if (LogPerformanceMeasurementEnabled (PERF_CORE_DB_STOP)) { \
+      LogPerformanceMeasurement (ModuleHandle, NULL, NULL, (UINT64)(UINTN)ControllerHandle, MODULE_DB_STOP_END_ID); \
+    } \
+  } while (FALSE)
+
+/**
+  Macro to measure the time from power-on to this macro execution.
+  It can be used to log a meaningful thing which happens at a time point.
+
+  If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+  and the BIT6 (dsiable PERF_GENERAL_TYPE) of PcdPerformanceLibraryPropertyMask is not set.
+  then LogPerformanceMeasurement() is called.
+
+**/
+#define PERF_EVENT(EventString) \
+  do { \
+    if (LogPerformanceMeasurementEnabled (PERF_GENERAL_TYPE)) { \
+      LogPerformanceMeasurement (&gEfiCallerIdGuid, NULL, EventString , 0, PERF_EVENT_ID); \
+    } \
+  } while (FALSE)
+
+/**
+  Begin Macro to measure the perofrmance of evnent signal behavior in any module.
+  The event guid will be passed with this macro.
+
+  If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+  and the BIT6 (dsiable PERF_GENERAL_TYPE) of PcdPerformanceLibraryPropertyMask is not set.
+  then LogPerformanceMeasurement() is called.
+
+**/
+#define PERF_EVENT_SIGNAL_BEGIN(EventGuid) \
+  do { \
+    if (LogPerformanceMeasurementEnabled (PERF_GENERAL_TYPE)) { \
+      LogPerformanceMeasurement (&gEfiCallerIdGuid, EventGuid, __FUNCTION__ , 0, PERF_EVENTSIGNAL_START_ID); \
+    } \
+  } while (FALSE)
+
+/**
+  End Macro to measure the perofrmance of evnent signal behavior in any module.
+  The event guid will be passed with this macro.
+
+  If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+  and the BIT6 (dsiable PERF_GENERAL_TYPE) of PcdPerformanceLibraryPropertyMask is not set.
+  then LogPerformanceMeasurement() is called.
+
+**/
+#define PERF_EVENT_SIGNAL_END(EventGuid) \
+  do { \
+    if (LogPerformanceMeasurementEnabled (PERF_GENERAL_TYPE)) { \
+      LogPerformanceMeasurement (&gEfiCallerIdGuid, EventGuid, __FUNCTION__ , 0, PERF_EVENTSIGNAL_END_ID); \
+    } \
+  } while (FALSE)
+
+/**
+  Begin Macro to measure the perofrmance of a callback function in any module.
+  The event guid which trigger the callback function will be passed with this macro.
+
+  If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+  and the BIT6 (dsiable PERF_GENERAL_TYPE) of PcdPerformanceLibraryPropertyMask is not set.
+  then LogPerformanceMeasurement() is called.
+
+**/
+#define PERF_CALLBACK_BEGIN(TriggerGuid) \
+  do { \
+    if (LogPerformanceMeasurementEnabled (PERF_GENERAL_TYPE)) { \
+      LogPerformanceMeasurement (&gEfiCallerIdGuid, TriggerGuid, __FUNCTION__ , 0, PERF_CALLBACK_START_ID); \
+    } \
+  } while (FALSE)
+
+/**
+  End Macro to measure the perofrmance of a callback function in any module.
+  The event guid which trigger the callback function will be passed with this macro.
+
+  If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+  and the BIT6 (dsiable PERF_GENERAL_TYPE) of PcdPerformanceLibraryPropertyMask is not set.
+  then LogPerformanceMeasurement() is called.
+
+**/
+#define PERF_CALLBACK_END(TriggerGuid) \
+  do { \
+    if (LogPerformanceMeasurementEnabled (PERF_GENERAL_TYPE)) { \
+      LogPerformanceMeasurement (&gEfiCallerIdGuid, TriggerGuid, __FUNCTION__ , 0, PERF_CALLBACK_END_ID); \
+    } \
+  } while (FALSE)
+
+/**
+  Begin Macro to measure the perofrmance of a general function in any module.
+
+  If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+  and the BIT6 (dsiable PERF_GENERAL_TYPE) of PcdPerformanceLibraryPropertyMask is not set.
+  then LogPerformanceMeasurement() is called.
+
+**/
+#define PERF_FUNCTION_BEGIN() \
+  do { \
+    if (LogPerformanceMeasurementEnabled (PERF_GENERAL_TYPE)) { \
+      LogPerformanceMeasurement (&gEfiCallerIdGuid, NULL, __FUNCTION__ , 0, PERF_FUNCTION_START_ID); \
+    } \
+  } while (FALSE)
+
+/**
+  End Macro to measure the perofrmance of a general function in any module.
+
+  If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+  and the BIT6 (dsiable PERF_GENERAL_TYPE) of PcdPerformanceLibraryPropertyMask is not set.
+  then LogPerformanceMeasurement() is called.
+
+**/
+#define PERF_FUNCTION_END() \
+  do { \
+    if (LogPerformanceMeasurementEnabled (PERF_GENERAL_TYPE)) { \
+      LogPerformanceMeasurement (&gEfiCallerIdGuid, NULL, __FUNCTION__ , 0, PERF_FUNCTION_END_ID); \
+    } \
+  } while (FALSE)
+
+/**
+  Begin Macro to measure the perofrmance of a behavior within one module.
+
+  If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+  and the BIT6 (dsiable PERF_GENERAL_TYPE) of PcdPerformanceLibraryPropertyMask is not set.
+  then LogPerformanceMeasurement() is called.
+
+**/
+#define PERF_INMODULE_BEGIN(MeasurementString) \
+  do { \
+    if (LogPerformanceMeasurementEnabled (PERF_GENERAL_TYPE)) { \
+      LogPerformanceMeasurement (&gEfiCallerIdGuid, NULL, MeasurementString, 0, PERF_INMODULE_START_ID); \
+    } \
+  } while (FALSE)
+
+/**
+  End Macro to measure the perofrmance of a behavior within one module.
+
+  If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+  and the BIT6 (dsiable PERF_GENERAL_TYPE) of PcdPerformanceLibraryPropertyMask is not set.
+  then LogPerformanceMeasurement() is called.
+
+**/
+#define PERF_INMODULE_END(MeasurementString) \
+  do { \
+    if (LogPerformanceMeasurementEnabled (PERF_GENERAL_TYPE)) { \
+      LogPerformanceMeasurement (&gEfiCallerIdGuid, NULL, MeasurementString, 0, PERF_INMODULE_END_ID); \
+    } \
+  } while (FALSE)
+
+/**
+  Begin Macro to measure the perofrmance of a behavior in different modules.
+  Such as the performance of PEI phase, DXE phase, BDS phase.
+
+  If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+  and the BIT6 (dsiable PERF_GENERAL_TYPE) of PcdPerformanceLibraryPropertyMask is not set.
+  then LogPerformanceMeasurement() is called.
+
+**/
+#define PERF_CROSSMODULE_BEGIN(MeasurementString) \
+  do { \
+    if (LogPerformanceMeasurementEnabled (PERF_GENERAL_TYPE)) { \
+      LogPerformanceMeasurement (&gEfiCallerIdGuid, NULL, MeasurementString, 0, PERF_CROSSMODULE_START_ID); \
+    } \
+  } while (FALSE)
+
+/**
+  End Macro to measure the perofrmance of a behavior in different modules.
+  Such as the performance of PEI phase, DXE phase, BDS phase.
+
+  If the PERFORMANCE_LIBRARY_PROPERTY_MEASUREMENT_ENABLED bit of PcdPerformanceLibraryPropertyMask is set,
+  and the BIT6 (dsiable PERF_GENERAL_TYPE) of PcdPerformanceLibraryPropertyMask is not set.
+  then LogPerformanceMeasurement() is called.
+
+**/
+#define PERF_CROSSMODULE_END(MeasurementString) \
+  do { \
+    if (LogPerformanceMeasurementEnabled (PERF_GENERAL_TYPE)) { \
+      LogPerformanceMeasurement (&gEfiCallerIdGuid, NULL, MeasurementString, 0, PERF_CROSSMODULE_END_ID); \
+    } \
+  } while (FALSE)
+
 /**
   Macro that calls EndPerformanceMeasurement().
 
diff --git a/MdePkg/Include/Library/PostCodeLib.h b/MdePkg/Include/Library/PostCodeLib.h
index bfc0b227079a..df43c06ad8ea 100644
--- a/MdePkg/Include/Library/PostCodeLib.h
+++ b/MdePkg/Include/Library/PostCodeLib.h
@@ -1,14 +1,8 @@
 /** @file
   Provides services to send progress/error codes to a POST card.
 
-Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -21,14 +15,14 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 /**
   Sends a 32-bit value to a POST card.
 
-  Sends the 32-bit value specified by Value to a POST card, and returns Value.  
-  Some implementations of this library function may perform I/O operations 
-  directly to a POST card device.  Other implementations may send Value to 
-  ReportStatusCode(), and the status code reporting mechanism will eventually 
+  Sends the 32-bit value specified by Value to a POST card, and returns Value.
+  Some implementations of this library function may perform I/O operations
+  directly to a POST card device.  Other implementations may send Value to
+  ReportStatusCode(), and the status code reporting mechanism will eventually
   display the 32-bit value on the status reporting device.
-  
-  PostCode() must actively prevent recursion.  If PostCode() is called while 
-  processing another Post Code Library function, then 
+
+  PostCode() must actively prevent recursion.  If PostCode() is called while
+  processing another Post Code Library function, then
   PostCode() must return Value immediately.
 
   @param  Value  The 32-bit value to write to the POST card.
@@ -47,21 +41,21 @@ PostCode (
   Sends a 32-bit value to a POST and associated ASCII string.
 
   Sends the 32-bit value specified by Value to a POST card, and returns Value.
-  If Description is not NULL, then the ASCII string specified by Description is 
-  also passed to the handler that displays the POST card value.  Some 
-  implementations of this library function may perform I/O operations directly 
-  to a POST card device.  Other implementations may send Value to ReportStatusCode(), 
-  and the status code reporting mechanism will eventually display the 32-bit 
-  value on the status reporting device.  
-
-  PostCodeWithDescription()must actively prevent recursion.  If 
-  PostCodeWithDescription() is called while processing another any other Post 
-  Code Library function, then PostCodeWithDescription() must return Value 
+  If Description is not NULL, then the ASCII string specified by Description is
+  also passed to the handler that displays the POST card value.  Some
+  implementations of this library function may perform I/O operations directly
+  to a POST card device.  Other implementations may send Value to ReportStatusCode(),
+  and the status code reporting mechanism will eventually display the 32-bit
+  value on the status reporting device.
+
+  PostCodeWithDescription()must actively prevent recursion.  If
+  PostCodeWithDescription() is called while processing another any other Post
+  Code Library function, then PostCodeWithDescription() must return Value
   immediately.
 
   @param  Value        The 32-bit value to write to the POST card.
-  @param  Description  Pointer to an ASCII string that is a description of the 
-                       POST code value.  This is an optional parameter that may 
+  @param  Description  Pointer to an ASCII string that is a description of the
+                       POST code value.  This is an optional parameter that may
                        be NULL.
 
   @return The 32-bit value to write to the POST card.
@@ -78,12 +72,12 @@ PostCodeWithDescription (
 /**
   Returns TRUE if POST Codes are enabled.
 
-  This function returns TRUE if the POST_CODE_PROPERTY_POST_CODE_ENABLED 
+  This function returns TRUE if the POST_CODE_PROPERTY_POST_CODE_ENABLED
   bit of PcdPostCodePropertyMask is set.  Otherwise FALSE is returned.
 
-  @retval  TRUE   The POST_CODE_PROPERTY_POST_CODE_ENABLED bit of 
+  @retval  TRUE   The POST_CODE_PROPERTY_POST_CODE_ENABLED bit of
                   PcdPostCodeProperyMask is set.
-  @retval  FALSE  The POST_CODE_PROPERTY_POST_CODE_ENABLED bit of 
+  @retval  FALSE  The POST_CODE_PROPERTY_POST_CODE_ENABLED bit of
                   PcdPostCodeProperyMask is clear.
 
 **/
@@ -116,7 +110,7 @@ PostCodeDescriptionEnabled (
 /**
   Sends a 32-bit value to a POST card.
 
-  If POST codes are enabled in PcdPostCodeProperyMask, then call PostCode() 
+  If POST codes are enabled in PcdPostCodeProperyMask, then call PostCode()
   passing in Value.  Value is returned.
 
   @param  Value  The 32-bit value to write to the POST card.
@@ -129,13 +123,13 @@ PostCodeDescriptionEnabled (
 /**
   Sends a 32-bit value to a POST and associated ASCII string.
 
-  If POST codes and POST code descriptions are enabled in 
-  PcdPostCodeProperyMask, then call PostCodeWithDescription() passing in 
-  Value and Description.  If only POST codes are enabled, then call PostCode() 
+  If POST codes and POST code descriptions are enabled in
+  PcdPostCodeProperyMask, then call PostCodeWithDescription() passing in
+  Value and Description.  If only POST codes are enabled, then call PostCode()
   passing in Value.  Value is returned.
 
   @param  Value        The 32-bit value to write to the POST card.
-  @param  Description  Pointer to an ASCII string that is a description of the 
+  @param  Description  Pointer to an ASCII string that is a description of the
                        POST code value.
 
   @return Value        The 32-bit value to write to the POST card.
diff --git a/MdePkg/Include/Library/PrintLib.h b/MdePkg/Include/Library/PrintLib.h
index e9cd0842979d..8548e1ce5b62 100644
--- a/MdePkg/Include/Library/PrintLib.h
+++ b/MdePkg/Include/Library/PrintLib.h
@@ -2,45 +2,39 @@
   Provides services to print a formatted string to a buffer. All combinations of
   Unicode and ASCII strings are supported.
 
-Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-  The Print Library functions provide a simple means to produce formatted output 
-  strings.  Many of the output functions use a format string to describe how to 
-  format the output of variable arguments.  The format string consists of normal 
-  text and argument descriptors.  There are no restrictions for how the normal 
-  text and argument descriptors can be mixed.  The following end of line(EOL) 
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  The Print Library functions provide a simple means to produce formatted output
+  strings.  Many of the output functions use a format string to describe how to
+  format the output of variable arguments.  The format string consists of normal
+  text and argument descriptors.  There are no restrictions for how the normal
+  text and argument descriptors can be mixed.  The following end of line(EOL)
   translations must be performed on the contents of the format string:
-  
+
      - '\\r' is translated to '\\r'
      - '\\r\\n' is translated to '\\r\\n'
-     - '\\n' is translated to '\\r\\n' 
+     - '\\n' is translated to '\\r\\n'
      - '\\n\\r' is translated to '\\r\\n'
-  
-  This does not follow the ANSI C standard for sprint().  The format of argument 
-  descriptors is described below.  The ANSI C standard for sprint() has been 
-  followed for some of the format types, and has not been followed for others.  
+
+  This does not follow the ANSI C standard for sprint().  The format of argument
+  descriptors is described below.  The ANSI C standard for sprint() has been
+  followed for some of the format types, and has not been followed for others.
   The exceptions are noted below.
 
     %[flags][width][.precision]type
 
   [flags]:
-    - -       
-      - The field is left justified.  If not flag is not specified, then the 
+    - -
+      - The field is left justified.  If not flag is not specified, then the
         field is right justified.
-    - space   
+    - space
       - Prefix a space character to a number.  Only valid for types X, x, and d.
-    - + 
-      - Prefix a plus character to a number.  Only valid for types X, x, and d.  
+    - +
+      - Prefix a plus character to a number.  Only valid for types X, x, and d.
         If both space and + are specified, then space is ignored.
     - 0
-      - Pad with 0 characters to the left of a number.  Only valid for types 
+      - Pad with 0 characters to the left of a number.  Only valid for types
         X, x, and d.
     - ,
       - Place a comma every 3rd digit of the number.  Only valid for type d.
@@ -53,20 +47,20 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   [width]:
 
     - *
-      - The width of the field is specified by a UINTN argument in the 
+      - The width of the field is specified by a UINTN argument in the
         argument list.
     - number
-      - The number specified as a decimal value represents the width of 
+      - The number specified as a decimal value represents the width of
         the field.
     - NOTE: If [width] is not specified, then a field width of 0 is assumed.
 
   [.precision]:
 
     - *
-      - The precision of the field is specified by a UINTN argument in the 
+      - The precision of the field is specified by a UINTN argument in the
         argument list.
     - number
-      - The number specified as a decimal value represents the precision of 
+      - The number specified as a decimal value represents the precision of
         the field.
     - NOTE: If [.precision] is not specified, then a precision of 0 is assumed.
 
@@ -75,102 +69,102 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
     - %
       - Print a %%.
     - c
-      - The argument is a Unicode character.  ASCII characters can be printed 
+      - The argument is a Unicode character.  ASCII characters can be printed
         using this type too by making sure bits 8..15 of the argument are set to 0.
     - x
-      - The argument is an unsigned hexadecimal number.  The characters used are 0..9 and 
-        A..F.  If the flag 'L' is not specified, then the argument is assumed 
+      - The argument is an unsigned hexadecimal number.  The characters used are 0..9 and
+        A..F.  If the flag 'L' is not specified, then the argument is assumed
         to be size int.  This does not follow ANSI C.
     - X
-      - The argument is an unsigned hexadecimal number and the number is padded with 
-        zeros.  This is equivalent to a format string of "0x". If the flag 
-        'L' is not specified, then the argument is assumed to be size int.  
+      - The argument is an unsigned hexadecimal number and the number is padded with
+        zeros.  This is equivalent to a format string of "0x". If the flag
+        'L' is not specified, then the argument is assumed to be size int.
         This does not follow ANSI C.
     - d
-      - The argument is a signed decimal number.  If the flag 'L' is not specified, 
-        then the argument is assumed to be size int.  
+      - The argument is a signed decimal number.  If the flag 'L' is not specified,
+        then the argument is assumed to be size int.
     - u
-      - The argument is a unsigned decimal number.  If the flag 'L' is not specified, 
+      - The argument is a unsigned decimal number.  If the flag 'L' is not specified,
         then the argument is assumed to be size int.
     - p
-      - The argument is a pointer that is a (VOID *), and it is printed as an 
+      - The argument is a pointer that is a (VOID *), and it is printed as an
         unsigned hexadecimal number  The characters used are 0..9 and A..F.
     - a
-      - The argument is a pointer to an ASCII string.  
+      - The argument is a pointer to an ASCII string.
         This does not follow ANSI C.
     - S, s
-      - The argument is a pointer to a Unicode string.  
+      - The argument is a pointer to a Unicode string.
         This does not follow ANSI C.
     - g
-      - The argument is a pointer to a GUID structure.  The GUID is printed 
-        in the format XXXXXXXX-XXXX-XXXX-XXXX-XXXXXXXXXXXX.  
+      - The argument is a pointer to a GUID structure.  The GUID is printed
+        in the format XXXXXXXX-XXXX-XXXX-XXXX-XXXXXXXXXXXX.
         This does not follow ANSI C.
     - t
-      - The argument is a pointer to an EFI_TIME structure.  The time and 
-        date are printed in the format "mm/dd/yyyy hh:mm" where mm is the 
-        month zero padded, dd is the day zero padded, yyyy is the year zero 
-        padded, hh is the hour zero padded, and mm is minutes zero padded.  
-        This does not follow ANSI C. 
+      - The argument is a pointer to an EFI_TIME structure.  The time and
+        date are printed in the format "mm/dd/yyyy hh:mm" where mm is the
+        month zero padded, dd is the day zero padded, yyyy is the year zero
+        padded, hh is the hour zero padded, and mm is minutes zero padded.
+        This does not follow ANSI C.
     - r
-      - The argument is a RETURN_STATUS value.  This value is converted to 
-        a string following the table below.  This does not follow ANSI C. 
-      - RETURN_SUCCESS               
+      - The argument is a RETURN_STATUS value.  This value is converted to
+        a string following the table below.  This does not follow ANSI C.
+      - RETURN_SUCCESS
         - "Success"
-      - RETURN_LOAD_ERROR            
+      - RETURN_LOAD_ERROR
         - "Load Error"
-      - RETURN_INVALID_PARAMETER     
+      - RETURN_INVALID_PARAMETER
         - "Invalid Parameter"
-      - RETURN_UNSUPPORTED           
+      - RETURN_UNSUPPORTED
         - "Unsupported"
-      - RETURN_BAD_BUFFER_SIZE       
+      - RETURN_BAD_BUFFER_SIZE
         - "Bad Buffer Size"
-      - RETURN_BUFFER_TOO_SMALL      
+      - RETURN_BUFFER_TOO_SMALL
         - "Buffer Too Small"
-      - RETURN_NOT_READY             
+      - RETURN_NOT_READY
         - "Not Ready"
-      - RETURN_DEVICE_ERROR          
+      - RETURN_DEVICE_ERROR
         - "Device Error"
-      - RETURN_WRITE_PROTECTED       
+      - RETURN_WRITE_PROTECTED
         - "Write Protected"
-      - RETURN_OUT_OF_RESOURCES      
+      - RETURN_OUT_OF_RESOURCES
         - "Out of Resources"
-      - RETURN_VOLUME_CORRUPTED      
+      - RETURN_VOLUME_CORRUPTED
         - "Volume Corrupt"
-      - RETURN_VOLUME_FULL           
+      - RETURN_VOLUME_FULL
         - "Volume Full"
-      - RETURN_NO_MEDIA              
+      - RETURN_NO_MEDIA
         - "No Media"
-      - RETURN_MEDIA_CHANGED         
+      - RETURN_MEDIA_CHANGED
         - "Media changed"
-      - RETURN_NOT_FOUND             
+      - RETURN_NOT_FOUND
         - "Not Found"
-      - RETURN_ACCESS_DENIED         
+      - RETURN_ACCESS_DENIED
         - "Access Denied"
-      - RETURN_NO_RESPONSE           
+      - RETURN_NO_RESPONSE
         - "No Response"
-      - RETURN_NO_MAPPING            
+      - RETURN_NO_MAPPING
         - "No mapping"
-      - RETURN_TIMEOUT               
+      - RETURN_TIMEOUT
         - "Time out"
-      - RETURN_NOT_STARTED           
+      - RETURN_NOT_STARTED
         - "Not started"
-      - RETURN_ALREADY_STARTED       
+      - RETURN_ALREADY_STARTED
         - "Already started"
-      - RETURN_ABORTED               
+      - RETURN_ABORTED
         - "Aborted"
-      - RETURN_ICMP_ERROR            
+      - RETURN_ICMP_ERROR
         - "ICMP Error"
-      - RETURN_TFTP_ERROR            
+      - RETURN_TFTP_ERROR
         - "TFTP Error"
-      - RETURN_PROTOCOL_ERROR        
+      - RETURN_PROTOCOL_ERROR
         - "Protocol Error"
-      - RETURN_WARN_UNKNOWN_GLYPH    
+      - RETURN_WARN_UNKNOWN_GLYPH
         - "Warning Unknown Glyph"
-      - RETURN_WARN_DELETE_FAILURE   
+      - RETURN_WARN_DELETE_FAILURE
         - "Warning Delete Failure"
-      - RETURN_WARN_WRITE_FAILURE    
+      - RETURN_WARN_WRITE_FAILURE
         - "Warning Write Failure"
-      - RETURN_WARN_BUFFER_TOO_SMALL 
+      - RETURN_WARN_BUFFER_TOO_SMALL
         - "Warning Buffer Too Small"
 
 **/
@@ -180,9 +174,9 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
 ///
 /// Define the maximum number of characters that are required to
-/// encode with a NULL terminator a decimal, hexadecimal, GUID,   
+/// encode with a NULL terminator a decimal, hexadecimal, GUID,
 /// or TIME value.
-///  
+///
 ///  Maximum Length Decimal String     = 28
 ///    "-9,223,372,036,854,775,808"
 ///  Maximum Length Hexadecimal String = 17
@@ -195,7 +189,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #define MAXIMUM_VALUE_CHARACTERS  38
 
 ///
-/// Flags bitmask values use in UnicodeValueToString() and 
+/// Flags bitmask values use in UnicodeValueToString() and
 /// AsciiValueToString()
 ///
 #define LEFT_JUSTIFY      0x01
@@ -497,26 +491,26 @@ UnicodeSPrintAsciiFormat (
   [ATTENTION] This function is deprecated for security reason.
 
   Converts a decimal value to a Null-terminated Unicode string.
-  
-  Converts the decimal number specified by Value to a Null-terminated Unicode 
-  string specified by Buffer containing at most Width characters. No padding of spaces 
+
+  Converts the decimal number specified by Value to a Null-terminated Unicode
+  string specified by Buffer containing at most Width characters. No padding of spaces
   is ever performed. If Width is 0 then a width of MAXIMUM_VALUE_CHARACTERS is assumed.
   The number of Unicode characters in Buffer is returned, not including the Null-terminator.
   If the conversion contains more than Width characters, then only the first
-  Width characters are returned, and the total number of characters 
+  Width characters are returned, and the total number of characters
   required to perform the conversion is returned.
-  Additional conversion parameters are specified in Flags.  
-  
+  Additional conversion parameters are specified in Flags.
+
   The Flags bit LEFT_JUSTIFY is always ignored.
   All conversions are left justified in Buffer.
   If Width is 0, PREFIX_ZERO is ignored in Flags.
   If COMMA_TYPE is set in Flags, then PREFIX_ZERO is ignored in Flags, and commas
   are inserted every 3rd digit starting from the right.
-  If RADIX_HEX is set in Flags, then the output buffer will be 
+  If RADIX_HEX is set in Flags, then the output buffer will be
   formatted in hexadecimal format.
   If Value is < 0 and RADIX_HEX is not set in Flags, then the fist character in Buffer is a '-'.
-  If PREFIX_ZERO is set in Flags and PREFIX_ZERO is not being ignored, 
-  then Buffer is padded with '0' characters so the combination of the optional '-' 
+  If PREFIX_ZERO is set in Flags and PREFIX_ZERO is not being ignored,
+  then Buffer is padded with '0' characters so the combination of the optional '-'
   sign character, '0' characters, digit characters for Value, and the Null-terminator
   add up to Width characters.
   If both COMMA_TYPE and RADIX_HEX are set in Flags, then ASSERT().
@@ -532,7 +526,7 @@ UnicodeSPrintAsciiFormat (
   @param  Value   The 64-bit signed value to convert to a string.
   @param  Width   The maximum number of Unicode characters to place in Buffer, not including
                   the Null-terminator.
-  
+
   @return The number of Unicode characters in Buffer, not including the Null-terminator.
 
 **/
@@ -894,29 +888,29 @@ AsciiSPrintUnicodeFormat (
   [ATTENTION] This function is deprecated for security reason.
 
   Converts a decimal value to a Null-terminated ASCII string.
-  
-  Converts the decimal number specified by Value to a Null-terminated ASCII string 
-  specified by Buffer containing at most Width characters. No padding of spaces 
+
+  Converts the decimal number specified by Value to a Null-terminated ASCII string
+  specified by Buffer containing at most Width characters. No padding of spaces
   is ever performed.
   If Width is 0 then a width of  MAXIMUM_VALUE_CHARACTERS is assumed.
   The number of ASCII characters in Buffer is returned, not including the Null-terminator.
   If the conversion contains more than Width characters, then only the first Width
   characters are returned, and the total number of characters required to perform
   the conversion is returned.
-  Additional conversion parameters are specified in Flags.  
+  Additional conversion parameters are specified in Flags.
   The Flags bit LEFT_JUSTIFY is always ignored.
   All conversions are left justified in Buffer.
   If Width is 0, PREFIX_ZERO is ignored in Flags.
   If COMMA_TYPE is set in Flags, then PREFIX_ZERO is ignored in Flags, and commas
   are inserted every 3rd digit starting from the right.
-  If RADIX_HEX is set in Flags, then the output buffer will be 
+  If RADIX_HEX is set in Flags, then the output buffer will be
   formatted in hexadecimal format.
   If Value is < 0 and RADIX_HEX is not set in Flags, then the fist character in Buffer is a '-'.
-  If PREFIX_ZERO is set in Flags and PREFIX_ZERO is not being ignored, 
-  then Buffer is padded with '0' characters so the combination of the optional '-' 
+  If PREFIX_ZERO is set in Flags and PREFIX_ZERO is not being ignored,
+  then Buffer is padded with '0' characters so the combination of the optional '-'
   sign character, '0' characters, digit characters for Value, and the Null-terminator
   add up to Width characters.
-  
+
   If Buffer is NULL, then ASSERT().
   If unsupported bits are set in Flags, then ASSERT().
   If both COMMA_TYPE and RADIX_HEX are set in Flags, then ASSERT().
@@ -928,7 +922,7 @@ AsciiSPrintUnicodeFormat (
   @param  Value   The 64-bit signed value to convert to a string.
   @param  Width   The maximum number of ASCII characters to place in Buffer, not including
                   the Null-terminator.
-  
+
   @return The number of ASCII characters in Buffer, not including the Null-terminator.
 
 **/
@@ -967,8 +961,7 @@ AsciiValueToString (
   sign character, '0' characters, digit characters for Value, and the
   Null-terminator add up to Width characters.
 
-  If Buffer is not aligned on a 16-bit boundary, then ASSERT().
-  If an error would be returned, then the function will also ASSERT().
+  If an error would be returned, then the function will ASSERT().
 
   @param  Buffer      The pointer to the output buffer for the produced
                       Null-terminated Ascii string.
@@ -1004,7 +997,7 @@ AsciiValueToStringS (
   );
 
 /**
-  Returns the number of characters that would be produced by if the formatted 
+  Returns the number of characters that would be produced by if the formatted
   output were produced not including the Null-terminator.
 
   If FormatString is not aligned on a 16-bit boundary, then ASSERT().
@@ -1017,7 +1010,7 @@ AsciiValueToStringS (
   @param[in]  FormatString    A Null-terminated Unicode format string.
   @param[in]  Marker          VA_LIST marker for the variable argument list.
 
-  @return The number of characters that would be produced, not including the 
+  @return The number of characters that would be produced, not including the
           Null-terminator.
 **/
 UINTN
@@ -1028,7 +1021,7 @@ SPrintLength (
   );
 
 /**
-  Returns the number of characters that would be produced by if the formatted 
+  Returns the number of characters that would be produced by if the formatted
   output were produced not including the Null-terminator.
 
   If FormatString is NULL, then ASSERT() and 0 is returned.
@@ -1039,7 +1032,7 @@ SPrintLength (
   @param[in]  FormatString    A Null-terminated ASCII format string.
   @param[in]  Marker          VA_LIST marker for the variable argument list.
 
-  @return The number of characters that would be produced, not including the 
+  @return The number of characters that would be produced, not including the
           Null-terminator.
 **/
 UINTN
diff --git a/MdePkg/Include/Library/ReportStatusCodeLib.h b/MdePkg/Include/Library/ReportStatusCodeLib.h
index 0fe55ca7d0db..0b77d78a043a 100644
--- a/MdePkg/Include/Library/ReportStatusCodeLib.h
+++ b/MdePkg/Include/Library/ReportStatusCodeLib.h
@@ -1,14 +1,8 @@
 /** @file
   Provides services to log status code records.
 
-Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -29,21 +23,21 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 /**
   Converts a status code to an 8-bit POST code value.
 
-  Converts the status code specified by CodeType and Value to an 8-bit POST code 
-  and returns the 8-bit POST code in PostCode.  If CodeType is an 
-  EFI_PROGRESS_CODE or CodeType is an EFI_ERROR_CODE, then bits 0..4 of PostCode 
-  are set to bits 16..20 of Value, and bits 5..7 of PostCode are set to bits 
-  24..26 of Value., and TRUE is returned.  Otherwise, FALSE is returned.  
+  Converts the status code specified by CodeType and Value to an 8-bit POST code
+  and returns the 8-bit POST code in PostCode.  If CodeType is an
+  EFI_PROGRESS_CODE or CodeType is an EFI_ERROR_CODE, then bits 0..4 of PostCode
+  are set to bits 16..20 of Value, and bits 5..7 of PostCode are set to bits
+  24..26 of Value., and TRUE is returned.  Otherwise, FALSE is returned.
 
   If PostCode is NULL, then ASSERT().
 
   @param  CodeType  The type of status code being converted.
   @param  Value     The status code value being converted.
-  @param  PostCode  A pointer to the 8-bit POST code value to return. 
+  @param  PostCode  A pointer to the 8-bit POST code value to return.
 
-  @retval  TRUE   The status code specified by CodeType and Value was converted 
+  @retval  TRUE   The status code specified by CodeType and Value was converted
                   to an 8-bit POST code and returned in PostCode.
-  @retval  FALSE  The status code specified by CodeType and Value could not be 
+  @retval  FALSE  The status code specified by CodeType and Value could not be
                   converted to an 8-bit POST code value.
 
 **/
@@ -60,15 +54,15 @@ CodeTypeToPostCode (
   Extracts ASSERT() information from a status code structure.
 
   Converts the status code specified by CodeType, Value, and Data to the ASSERT()
-  arguments specified by Filename, Description, and LineNumber.  If CodeType is 
-  an EFI_ERROR_CODE, and CodeType has a severity of EFI_ERROR_UNRECOVERED, and 
-  Value has an operation mask of EFI_SW_EC_ILLEGAL_SOFTWARE_STATE, extract 
-  Filename, Description, and LineNumber from the optional data area of the 
-  status code buffer specified by Data.  The optional data area of Data contains 
-  a Null-terminated ASCII string for the FileName, followed by a Null-terminated 
-  ASCII string for the Description, followed by a 32-bit LineNumber.  If the 
-  ASSERT() information could be extracted from Data, then return TRUE.  
-  Otherwise, FALSE is returned.  
+  arguments specified by Filename, Description, and LineNumber.  If CodeType is
+  an EFI_ERROR_CODE, and CodeType has a severity of EFI_ERROR_UNRECOVERED, and
+  Value has an operation mask of EFI_SW_EC_ILLEGAL_SOFTWARE_STATE, extract
+  Filename, Description, and LineNumber from the optional data area of the
+  status code buffer specified by Data.  The optional data area of Data contains
+  a Null-terminated ASCII string for the FileName, followed by a Null-terminated
+  ASCII string for the Description, followed by a 32-bit LineNumber.  If the
+  ASSERT() information could be extracted from Data, then return TRUE.
+  Otherwise, FALSE is returned.
 
   If Data is NULL, then ASSERT().
   If Filename is NULL, then ASSERT().
@@ -77,15 +71,15 @@ CodeTypeToPostCode (
 
   @param  CodeType     The type of status code being converted.
   @param  Value        The status code value being converted.
-  @param  Data         The pointer to status code data buffer. 
+  @param  Data         The pointer to status code data buffer.
   @param  Filename     The pointer to the source file name that generated the ASSERT().
   @param  Description  The pointer to the description of the ASSERT().
   @param  LineNumber   The pointer to source line number that generated the ASSERT().
 
-  @retval  TRUE   The status code specified by CodeType, Value, and Data was 
-                  converted ASSERT() arguments specified by Filename, Description, 
+  @retval  TRUE   The status code specified by CodeType, Value, and Data was
+                  converted ASSERT() arguments specified by Filename, Description,
                   and LineNumber.
-  @retval  FALSE  The status code specified by CodeType, Value, and Data could 
+  @retval  FALSE  The status code specified by CodeType, Value, and Data could
                   not be converted to ASSERT() arguments.
 
 **/
@@ -93,8 +87,8 @@ BOOLEAN
 EFIAPI
 ReportStatusCodeExtractAssertInfo (
   IN EFI_STATUS_CODE_TYPE        CodeType,
-  IN EFI_STATUS_CODE_VALUE       Value,  
-  IN CONST EFI_STATUS_CODE_DATA  *Data, 
+  IN EFI_STATUS_CODE_VALUE       Value,
+  IN CONST EFI_STATUS_CODE_DATA  *Data,
   OUT CHAR8                      **Filename,
   OUT CHAR8                      **Description,
   OUT UINT32                     *LineNumber
@@ -104,13 +98,13 @@ ReportStatusCodeExtractAssertInfo (
 /**
   Extracts DEBUG() information from a status code structure.
 
-  Converts the status code specified by Data to the DEBUG() arguments specified 
-  by ErrorLevel, Marker, and Format.  If type GUID in Data is 
-  EFI_STATUS_CODE_DATA_TYPE_DEBUG_GUID, then extract ErrorLevel, Marker, and 
-  Format from the optional data area of the status code buffer specified by Data.  
-  The optional data area of Data contains a 32-bit ErrorLevel followed by Marker 
-  which is 12 UINTN parameters, followed by a Null-terminated ASCII string for 
-  the Format.  If the DEBUG() information could be extracted from Data, then 
+  Converts the status code specified by Data to the DEBUG() arguments specified
+  by ErrorLevel, Marker, and Format.  If type GUID in Data is
+  EFI_STATUS_CODE_DATA_TYPE_DEBUG_GUID, then extract ErrorLevel, Marker, and
+  Format from the optional data area of the status code buffer specified by Data.
+  The optional data area of Data contains a 32-bit ErrorLevel followed by Marker
+  which is 12 UINTN parameters, followed by a Null-terminated ASCII string for
+  the Format.  If the DEBUG() information could be extracted from Data, then
   return TRUE.  Otherwise, FALSE is returned.
 
   If Data is NULL, then ASSERT().
@@ -118,22 +112,22 @@ ReportStatusCodeExtractAssertInfo (
   If Marker is NULL, then ASSERT().
   If Format is NULL, then ASSERT().
 
-  @param  Data        The pointer to status code data buffer. 
+  @param  Data        The pointer to status code data buffer.
   @param  ErrorLevel  The pointer to error level mask for a debug message.
   @param  Marker      The pointer to the variable argument list associated with Format.
-  @param  Format      The pointer to a Null-terminated ASCII format string of a 
+  @param  Format      The pointer to a Null-terminated ASCII format string of a
                       debug message.
 
-  @retval  TRUE   The status code specified by Data was converted DEBUG() arguments 
+  @retval  TRUE   The status code specified by Data was converted DEBUG() arguments
                   specified by ErrorLevel, Marker, and Format.
-  @retval  FALSE  The status code specified by Data could not be converted to 
+  @retval  FALSE  The status code specified by Data could not be converted to
                   DEBUG() arguments.
 
 **/
 BOOLEAN
 EFIAPI
 ReportStatusCodeExtractDebugInfo (
-  IN CONST EFI_STATUS_CODE_DATA  *Data, 
+  IN CONST EFI_STATUS_CODE_DATA  *Data,
   OUT UINT32                     *ErrorLevel,
   OUT BASE_LIST                  *Marker,
   OUT CHAR8                      **Format
@@ -143,20 +137,20 @@ ReportStatusCodeExtractDebugInfo (
 /**
   Reports a status code.
 
-  Reports the status code specified by the parameters Type and Value.  Status 
-  code also require an instance, caller ID, and extended data.  This function 
-  passed in a zero instance, NULL extended data, and a caller ID of 
-  gEfiCallerIdGuid, which is the GUID for the module.  
-  
-  ReportStatusCode()must actively prevent recursion.  If ReportStatusCode() 
+  Reports the status code specified by the parameters Type and Value.  Status
+  code also require an instance, caller ID, and extended data.  This function
+  passed in a zero instance, NULL extended data, and a caller ID of
+  gEfiCallerIdGuid, which is the GUID for the module.
+
+  ReportStatusCode()must actively prevent recursion.  If ReportStatusCode()
   is called while processing another any other Report Status Code Library function,
   then ReportStatusCode() must return immediately.
 
-  @param  Type   Status code type. 
+  @param  Type   Status code type.
   @param  Value  Status code value.
 
   @retval  EFI_SUCCESS       The status code was reported.
-  @retval  EFI_DEVICE_ERROR  There status code could not be reported due to a 
+  @retval  EFI_DEVICE_ERROR  There status code could not be reported due to a
                              device error.
   @retval  EFI_UNSUPPORTED   The report status code is not supported.
 
@@ -172,26 +166,26 @@ ReportStatusCode (
 /**
   Reports a status code with a Device Path Protocol as the extended data.
 
-  Allocates and fills in the extended data section of a status code with the 
-  Device Path Protocol specified by DevicePath.  This function is responsible 
-  for allocating a buffer large enough for the standard header and the device 
+  Allocates and fills in the extended data section of a status code with the
+  Device Path Protocol specified by DevicePath.  This function is responsible
+  for allocating a buffer large enough for the standard header and the device
   path.  The standard header is filled in with an implementation dependent GUID.
   The status code is reported with a zero instance and a caller ID of gEfiCallerIdGuid.
 
-  ReportStatusCodeWithDevicePath()must actively prevent recursion.  If 
-  ReportStatusCodeWithDevicePath() is called while processing another any other 
-  Report Status Code Library function, then ReportStatusCodeWithDevicePath() 
+  ReportStatusCodeWithDevicePath()must actively prevent recursion.  If
+  ReportStatusCodeWithDevicePath() is called while processing another any other
+  Report Status Code Library function, then ReportStatusCodeWithDevicePath()
   must return EFI_DEVICE_ERROR immediately.
 
   If DevicePath is NULL, then ASSERT().
 
-  @param  Type        The status code type. 
+  @param  Type        The status code type.
   @param  Value       The status code value.
   @param  DevicePath  The pointer to the Device Path Protocol to be reported.
 
-  @retval  EFI_SUCCESS           The status code was reported with the extended 
+  @retval  EFI_SUCCESS           The status code was reported with the extended
                                  data specified by DevicePath.
-  @retval  EFI_OUT_OF_RESOURCES  There were not enough resources to allocate the 
+  @retval  EFI_OUT_OF_RESOURCES  There were not enough resources to allocate the
                                  extended data section.
   @retval  EFI_UNSUPPORTED       The report status code is not supported.
   @retval  EFI_DEVICE_ERROR      A call to a Report Status Code Library function
@@ -210,32 +204,32 @@ ReportStatusCodeWithDevicePath (
 /**
   Reports a status code with an extended data buffer.
 
-  Allocates and fills in the extended data section of a status code with the 
-  extended data specified by ExtendedData and ExtendedDataSize.  ExtendedData 
-  is assumed to be one of the data structures specified in Related Definitions.  
-  These data structure do not have the standard header, so this function is 
-  responsible for allocating a buffer large enough for the standard header and 
-  the extended data passed into this function.  The standard header is filled 
-  in with an implementation dependent GUID.  The status code is reported 
+  Allocates and fills in the extended data section of a status code with the
+  extended data specified by ExtendedData and ExtendedDataSize.  ExtendedData
+  is assumed to be one of the data structures specified in Related Definitions.
+  These data structure do not have the standard header, so this function is
+  responsible for allocating a buffer large enough for the standard header and
+  the extended data passed into this function.  The standard header is filled
+  in with an implementation dependent GUID.  The status code is reported
   with a zero instance and a caller ID of gEfiCallerIdGuid.
 
-  ReportStatusCodeWithExtendedData()must actively prevent recursion.  If 
-  ReportStatusCodeWithExtendedData() is called while processing another any other 
-  Report Status Code Library function, then ReportStatusCodeWithExtendedData() 
+  ReportStatusCodeWithExtendedData()must actively prevent recursion.  If
+  ReportStatusCodeWithExtendedData() is called while processing another any other
+  Report Status Code Library function, then ReportStatusCodeWithExtendedData()
   must return EFI_DEVICE_ERROR immediately.
 
   If ExtendedData is NULL, then ASSERT().
   If ExtendedDataSize is 0, then ASSERT().
 
-  @param  Type              The status code type. 
+  @param  Type              The status code type.
   @param  Value             The status code value.
   @param  ExtendedData      The pointer to the extended data buffer to be reported.
-  @param  ExtendedDataSize  The size, in bytes, of the extended data buffer to 
+  @param  ExtendedDataSize  The size, in bytes, of the extended data buffer to
                             be reported.
 
-  @retval  EFI_SUCCESS           The status code was reported with the extended 
+  @retval  EFI_SUCCESS           The status code was reported with the extended
                                  data specified by ExtendedData and ExtendedDataSize.
-  @retval  EFI_OUT_OF_RESOURCES  There were not enough resources to allocate the 
+  @retval  EFI_OUT_OF_RESOURCES  There were not enough resources to allocate the
                                  extended data section.
   @retval  EFI_UNSUPPORTED       The report status code is not supported.
   @retval  EFI_DEVICE_ERROR      A call to a Report Status Code Library function
@@ -255,39 +249,39 @@ ReportStatusCodeWithExtendedData (
 /**
   Reports a status code with full parameters.
 
-  The function reports a status code.  If ExtendedData is NULL and ExtendedDataSize 
-  is 0, then an extended data buffer is not reported.  If ExtendedData is not 
-  NULL and ExtendedDataSize is not 0, then an extended data buffer is allocated.  
-  ExtendedData is assumed not have the standard status code header, so this function 
-  is responsible for allocating a buffer large enough for the standard header and 
-  the extended data passed into this function.  The standard header is filled in 
-  with a GUID specified by ExtendedDataGuid.  If ExtendedDataGuid is NULL, then a 
-  GUID of gEfiStatusCodeSpecificDataGuid is used.  The status code is reported with 
-  an instance specified by Instance and a caller ID specified by CallerId.  If 
+  The function reports a status code.  If ExtendedData is NULL and ExtendedDataSize
+  is 0, then an extended data buffer is not reported.  If ExtendedData is not
+  NULL and ExtendedDataSize is not 0, then an extended data buffer is allocated.
+  ExtendedData is assumed not have the standard status code header, so this function
+  is responsible for allocating a buffer large enough for the standard header and
+  the extended data passed into this function.  The standard header is filled in
+  with a GUID specified by ExtendedDataGuid.  If ExtendedDataGuid is NULL, then a
+  GUID of gEfiStatusCodeSpecificDataGuid is used.  The status code is reported with
+  an instance specified by Instance and a caller ID specified by CallerId.  If
   CallerId is NULL, then a caller ID of gEfiCallerIdGuid is used.
 
-  ReportStatusCodeEx()must actively prevent recursion.  If ReportStatusCodeEx() 
-  is called while processing another any other Report Status Code Library function, 
+  ReportStatusCodeEx()must actively prevent recursion.  If ReportStatusCodeEx()
+  is called while processing another any other Report Status Code Library function,
   then ReportStatusCodeEx() must return EFI_DEVICE_ERROR immediately.
 
   If ExtendedData is NULL and ExtendedDataSize is not zero, then ASSERT().
   If ExtendedData is not NULL and ExtendedDataSize is zero, then ASSERT().
 
-  @param  Type              The status code type. 
+  @param  Type              The status code type.
   @param  Value             The status code value.
   @param  Instance          The status code instance number.
-  @param  CallerId          The pointer to a GUID that identifies the caller of this 
-                            function.  If this parameter is NULL, then a caller 
+  @param  CallerId          The pointer to a GUID that identifies the caller of this
+                            function.  If this parameter is NULL, then a caller
                             ID of gEfiCallerIdGuid is used.
-  @param  ExtendedDataGuid  The pointer to the GUID for the extended data buffer.  
-                            If this parameter is NULL, then a the status code 
+  @param  ExtendedDataGuid  The pointer to the GUID for the extended data buffer.
+                            If this parameter is NULL, then a the status code
                             standard header is filled in with an implementation dependent GUID.
-  @param  ExtendedData      The pointer to the extended data buffer.  This is an 
+  @param  ExtendedData      The pointer to the extended data buffer.  This is an
                             optional parameter that may be NULL.
   @param  ExtendedDataSize  The size, in bytes, of the extended data buffer.
 
   @retval  EFI_SUCCESS           The status code was reported.
-  @retval  EFI_OUT_OF_RESOURCES  There were not enough resources to allocate 
+  @retval  EFI_OUT_OF_RESOURCES  There were not enough resources to allocate
                                  the extended data section if it was specified.
   @retval  EFI_UNSUPPORTED       The report status code is not supported.
   @retval  EFI_DEVICE_ERROR      A call to a Report Status Code Library function
@@ -310,12 +304,12 @@ ReportStatusCodeEx (
 /**
   Returns TRUE if status codes of type EFI_PROGRESS_CODE are enabled
 
-  This function returns TRUE if the REPORT_STATUS_CODE_PROPERTY_PROGRESS_CODE_ENABLED 
+  This function returns TRUE if the REPORT_STATUS_CODE_PROPERTY_PROGRESS_CODE_ENABLED
   bit of PcdReportStatusCodeProperyMask is set.  Otherwise FALSE is returned.
 
-  @retval  TRUE   The REPORT_STATUS_CODE_PROPERTY_PROGRESS_CODE_ENABLED bit of 
+  @retval  TRUE   The REPORT_STATUS_CODE_PROPERTY_PROGRESS_CODE_ENABLED bit of
                   PcdReportStatusCodeProperyMask is set.
-  @retval  FALSE  The REPORT_STATUS_CODE_PROPERTY_PROGRESS_CODE_ENABLED bit of 
+  @retval  FALSE  The REPORT_STATUS_CODE_PROPERTY_PROGRESS_CODE_ENABLED bit of
                   PcdReportStatusCodeProperyMask is clear.
 
 **/
@@ -329,12 +323,12 @@ ReportProgressCodeEnabled (
 /**
   Returns TRUE if status codes of type EFI_ERROR_CODE are enabled
 
-  This function returns TRUE if the REPORT_STATUS_CODE_PROPERTY_ERROR_CODE_ENABLED 
+  This function returns TRUE if the REPORT_STATUS_CODE_PROPERTY_ERROR_CODE_ENABLED
   bit of PcdReportStatusCodeProperyMask is set.  Otherwise, FALSE is returned.
 
-  @retval  TRUE   The REPORT_STATUS_CODE_PROPERTY_ERROR_CODE_ENABLED bit of 
+  @retval  TRUE   The REPORT_STATUS_CODE_PROPERTY_ERROR_CODE_ENABLED bit of
                   PcdReportStatusCodeProperyMask is set.
-  @retval  FALSE  The REPORT_STATUS_CODE_PROPERTY_ERROR_CODE_ENABLED bit of 
+  @retval  FALSE  The REPORT_STATUS_CODE_PROPERTY_ERROR_CODE_ENABLED bit of
                   PcdReportStatusCodeProperyMask is clear.
 
 **/
@@ -348,12 +342,12 @@ ReportErrorCodeEnabled (
 /**
   Returns TRUE if status codes of type EFI_DEBUG_CODE are enabled
 
-  This function returns TRUE if the REPORT_STATUS_CODE_PROPERTY_DEBUG_CODE_ENABLED 
+  This function returns TRUE if the REPORT_STATUS_CODE_PROPERTY_DEBUG_CODE_ENABLED
   bit of PcdReportStatusCodeProperyMask is set.  Otherwise FALSE is returned.
 
-  @retval  TRUE   The REPORT_STATUS_CODE_PROPERTY_DEBUG_CODE_ENABLED bit of 
+  @retval  TRUE   The REPORT_STATUS_CODE_PROPERTY_DEBUG_CODE_ENABLED bit of
                   PcdReportStatusCodeProperyMask is set.
-  @retval  FALSE  The REPORT_STATUS_CODE_PROPERTY_DEBUG_CODE_ENABLED bit of 
+  @retval  FALSE  The REPORT_STATUS_CODE_PROPERTY_DEBUG_CODE_ENABLED bit of
                   PcdReportStatusCodeProperyMask is clear.
 
 **/
@@ -367,11 +361,11 @@ ReportDebugCodeEnabled (
 /**
   Reports a status code with minimal parameters if the status code type is enabled.
 
-  If the status code type specified by Type is enabled in 
-  PcdReportStatusCodeProperyMask, then call ReportStatusCode() passing in Type 
+  If the status code type specified by Type is enabled in
+  PcdReportStatusCodeProperyMask, then call ReportStatusCode() passing in Type
   and Value.
 
-  @param  Type   The status code type. 
+  @param  Type   The status code type.
   @param  Value  The status code value.
 
   @retval  EFI_SUCCESS       The status code was reported.
@@ -390,20 +384,20 @@ ReportDebugCodeEnabled (
 
 
 /**
-  Reports a status code with a Device Path Protocol as the extended data if the 
+  Reports a status code with a Device Path Protocol as the extended data if the
   status code type is enabled.
 
-  If the status code type specified by Type is enabled in 
-  PcdReportStatusCodeProperyMask, then call ReportStatusCodeWithDevicePath() 
+  If the status code type specified by Type is enabled in
+  PcdReportStatusCodeProperyMask, then call ReportStatusCodeWithDevicePath()
   passing in Type, Value, and DevicePath.
 
-  @param  Type        The status code type. 
+  @param  Type        The status code type.
   @param  Value       The status code value.
   @param  DevicePath  Pointer to the Device Path Protocol to be reported.
 
-  @retval  EFI_SUCCESS           The status code was reported with the extended 
+  @retval  EFI_SUCCESS           The status code was reported with the extended
                                  data specified by DevicePath.
-  @retval  EFI_OUT_OF_RESOURCES  There were not enough resources to allocate the 
+  @retval  EFI_OUT_OF_RESOURCES  There were not enough resources to allocate the
                                  extended data section.
   @retval  EFI_UNSUPPORTED       The report status code is not supported.
   @retval  EFI_DEVICE_ERROR      A call to a Report Status Code Library function
@@ -421,22 +415,22 @@ ReportDebugCodeEnabled (
 
 
 /**
-  Reports a status code with an extended data buffer if the status code type 
+  Reports a status code with an extended data buffer if the status code type
   is enabled.
 
-  If the status code type specified by Type is enabled in 
-  PcdReportStatusCodeProperyMask, then call ReportStatusCodeWithExtendedData() 
+  If the status code type specified by Type is enabled in
+  PcdReportStatusCodeProperyMask, then call ReportStatusCodeWithExtendedData()
   passing in Type, Value, ExtendedData, and ExtendedDataSize.
 
-  @param  Type              The status code type. 
+  @param  Type              The status code type.
   @param  Value             The status code value.
   @param  ExtendedData      The pointer to the extended data buffer to be reported.
   @param  ExtendedDataSize  The size, in bytes, of the extended data buffer to
                             be reported.
 
-  @retval  EFI_SUCCESS           The status code was reported with the extended 
+  @retval  EFI_SUCCESS           The status code was reported with the extended
                                  data specified by ExtendedData and ExtendedDataSize.
-  @retval  EFI_OUT_OF_RESOURCES  There were not enough resources to allocate the 
+  @retval  EFI_OUT_OF_RESOURCES  There were not enough resources to allocate the
                                  extended data section.
   @retval  EFI_UNSUPPORTED       The report status code is not supported.
   @retval  EFI_DEVICE_ERROR      A call to a Report Status Code Library function
@@ -455,25 +449,25 @@ ReportDebugCodeEnabled (
 /**
   Reports a status code specifying all parameters if the status code type is enabled.
 
-  If the status code type specified by Type is enabled in 
-  PcdReportStatusCodeProperyMask, then call ReportStatusCodeEx() passing in Type, 
+  If the status code type specified by Type is enabled in
+  PcdReportStatusCodeProperyMask, then call ReportStatusCodeEx() passing in Type,
   Value, Instance, CallerId, ExtendedDataGuid, ExtendedData, and ExtendedDataSize.
 
-  @param  Type              The status code type. 
+  @param  Type              The status code type.
   @param  Value             The status code value.
   @param  Instance          The status code instance number.
-  @param  CallerId          The pointer to a GUID that identifies the caller of this 
-                            function.  If this parameter is NULL, then a caller 
+  @param  CallerId          The pointer to a GUID that identifies the caller of this
+                            function.  If this parameter is NULL, then a caller
                             ID of gEfiCallerIdGuid is used.
-  @param  ExtendedDataGuid  Pointer to the GUID for the extended data buffer.  
-                            If this parameter is NULL, then a the status code 
+  @param  ExtendedDataGuid  Pointer to the GUID for the extended data buffer.
+                            If this parameter is NULL, then a the status code
                             standard header is filled in with an implementation dependent GUID.
-  @param  ExtendedData      Pointer to the extended data buffer.  This is an 
+  @param  ExtendedData      Pointer to the extended data buffer.  This is an
                             optional parameter that may be NULL.
   @param  ExtendedDataSize  The size, in bytes, of the extended data buffer.
 
   @retval  EFI_SUCCESS           The status code was reported.
-  @retval  EFI_OUT_OF_RESOURCES  There were not enough resources to allocate the 
+  @retval  EFI_OUT_OF_RESOURCES  There were not enough resources to allocate the
                                  extended data section if it was specified.
   @retval  EFI_UNSUPPORTED       The report status code is not supported.
   @retval  EFI_DEVICE_ERROR      A call to a Report Status Code Library function
diff --git a/MdePkg/Include/Library/ResourcePublicationLib.h b/MdePkg/Include/Library/ResourcePublicationLib.h
index c15f58f48ebc..3e2a810e4280 100644
--- a/MdePkg/Include/Library/ResourcePublicationLib.h
+++ b/MdePkg/Include/Library/ResourcePublicationLib.h
@@ -1,14 +1,8 @@
 /** @file
   Provides a service to publish discovered system resources.
 
-Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -21,9 +15,9 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   Declares that the system memory buffer specified by MemoryBegin and MemoryLength
   as permanent memory that may be used for general purpose use by software.
   The amount of memory available to software may be less than MemoryLength
-  if published memory has alignment restrictions. 
+  if published memory has alignment restrictions.
   If MemoryLength is 0, then ASSERT().
-  If MemoryLength is greater than (MAX_ADDRESS - MemoryBegin + 1), then ASSERT(). 
+  If MemoryLength is greater than (MAX_ADDRESS - MemoryBegin + 1), then ASSERT().
 
   @param  MemoryBegin               The start address of the memory being declared.
   @param  MemoryLength              The number of bytes of memory being declared.
diff --git a/MdePkg/Include/Library/RngLib.h b/MdePkg/Include/Library/RngLib.h
index 4b0b90cd346d..bed9d8e5beba 100644
--- a/MdePkg/Include/Library/RngLib.h
+++ b/MdePkg/Include/Library/RngLib.h
@@ -2,13 +2,7 @@
   Provides random number generator services.
 
 Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/Library/S3BootScriptLib.h b/MdePkg/Include/Library/S3BootScriptLib.h
index 160a6d869adb..4e8e4b3ffaac 100644
--- a/MdePkg/Include/Library/S3BootScriptLib.h
+++ b/MdePkg/Include/Library/S3BootScriptLib.h
@@ -1,20 +1,13 @@
-/** @file 
-  Defines library APIs used by modules to save EFI Boot Script Opcodes.  
-  These OpCode will be restored by S3 related modules. 
-  Note that some of the API defined in the Library class may not 
-  be provided in the Framework version library instance, which means some of these 
+/** @file
+  Defines library APIs used by modules to save EFI Boot Script Opcodes.
+  These OpCode will be restored by S3 related modules.
+  Note that some of the API defined in the Library class may not
+  be provided in the Framework version library instance, which means some of these
   APIs cannot be used if the underlying firmware is Framework and not PI.
 
-  Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
 
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions
-  of the BSD License which accompanies this distribution.  The
-  full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -43,14 +36,14 @@
   (((UINTN) Device) << 16) | \
   (((UINTN) Function) << 8) | \
   (((UINTN) (Register)) < 256 ? ((UINTN) (Register)) : (UINT64) (LShiftU64 ((UINT64) (Register), 32))))
- 
+
 ///
 /// S3 Boot Script Width.
 ///
 typedef enum {
   S3BootScriptWidthUint8,        ///< 8-bit operation.
   S3BootScriptWidthUint16,       ///< 16-bit operation.
-  S3BootScriptWidthUint32,       ///< 32-bit operation.  
+  S3BootScriptWidthUint32,       ///< 32-bit operation.
   S3BootScriptWidthUint64,       ///< 64-bit operation.
   S3BootScriptWidthFifoUint8,    ///< 8-bit FIFO operation.
   S3BootScriptWidthFifoUint16,   ///< 16-bit FIFO operation.
@@ -71,7 +64,7 @@ typedef enum {
   @param[in] Count     The number of I/O operations to perform.
   @param[in] Buffer    The source buffer from which to write data.
 
-  @retval RETURN_OUT_OF_RESOURCES   Not enough memory for the table to perform 
+  @retval RETURN_OUT_OF_RESOURCES   Not enough memory for the table to perform
                                     the operation.
   @retval RETURN_SUCCESS            The opcode was added.
 
@@ -94,7 +87,7 @@ S3BootScriptSaveIoWrite (
   @param[in] DataMask   A pointer to the data mask to be AND-ed with the data
                         read from the register.
 
-  @retval RETURN_OUT_OF_RESOURCES   Not enough memory for the table to perform 
+  @retval RETURN_OUT_OF_RESOURCES   Not enough memory for the table to perform
                                     the operation.
   @retval RETURN_SUCCESS            The opcode was added.
 
@@ -116,7 +109,7 @@ S3BootScriptSaveIoReadWrite (
   @param[in] Count     The number of memory operations to perform.
   @param[in] Buffer    The source buffer from which to write the data.
 
-  @retval RETURN_OUT_OF_RESOURCES   Not enough memory for the table to perform 
+  @retval RETURN_OUT_OF_RESOURCES   Not enough memory for the table to perform
                                     the operation.
   @retval RETURN_SUCCESS            The opcode was added.
 **/
@@ -133,13 +126,13 @@ S3BootScriptSaveMemWrite (
   Adds a record for a memory modify operation into a specified boot script table.
 
   @param[in] Width      The width of the I/O operations.
-  @param[in] Address    The base address of the memory operations. Address needs 
+  @param[in] Address    The base address of the memory operations. Address needs
                         alignment, if required
   @param[in] Data       A pointer to the data to be OR-ed.
-  @param[in] DataMask   A pointer to the data mask to be AND-ed with the data 
+  @param[in] DataMask   A pointer to the data mask to be AND-ed with the data
                         read from the register.
 
-  @retval RETURN_OUT_OF_RESOURCES   Not enough memory for the table to perform 
+  @retval RETURN_OUT_OF_RESOURCES   Not enough memory for the table to perform
                                     the operation.
   @retval RETURN_SUCCESS            The opcode was added.
 **/
@@ -160,7 +153,7 @@ S3BootScriptSaveMemReadWrite (
   @param[in] Count     The number of PCI operations to perform.
   @param[in] Buffer    The source buffer from which to write the data.
 
-  @retval RETURN_OUT_OF_RESOURCES  Not enough memory for the table to perform 
+  @retval RETURN_OUT_OF_RESOURCES  Not enough memory for the table to perform
                                    the operation.
   @retval RETURN_SUCCESS           The opcode was added.
 **/
@@ -181,7 +174,7 @@ S3BootScriptSavePciCfgWrite (
   @param[in] Data       A pointer to the data to be OR-ed.The size depends on Width.
   @param[in] DataMask   A pointer to the data mask to be AND-ed.
 
-  @retval RETURN_OUT_OF_RESOURCES   Not enough memory for the table to perform 
+  @retval RETURN_OUT_OF_RESOURCES   Not enough memory for the table to perform
                                     the operation.
   @retval RETURN__SUCCESS           The opcode was added.
 **/
@@ -203,7 +196,7 @@ S3BootScriptSavePciCfgReadWrite (
   @param[in] Count     The number of PCI operations to perform.
   @param[in] Buffer    The source buffer from which to write the data.
 
-  @retval RETURN_OUT_OF_RESOURCES   Not enough memory for the table to perform 
+  @retval RETURN_OUT_OF_RESOURCES   Not enough memory for the table to perform
                                     the operation.
   @retval RETURN_SUCCESS            The opcode was added.
 **/
@@ -226,7 +219,7 @@ S3BootScriptSavePciCfg2Write (
   @param[in] Data       A pointer to the data to be OR-ed. The size depends on Width.
   @param[in] DataMask   A pointer to the data mask to be AND-ed.
 
-  @retval RETURN_OUT_OF_RESOURCES   Not enough memory for the table to perform 
+  @retval RETURN_OUT_OF_RESOURCES   Not enough memory for the table to perform
                                     the operation.
   @retval RETURN_SUCCESS            The opcode was added.
 **/
@@ -243,23 +236,23 @@ S3BootScriptSavePciCfg2ReadWrite (
 /**
   Adds a record for an SMBus command execution into a specified boot script table.
 
-  @param[in] SmBusAddress   Address that encodes the SMBUS Slave Address, SMBUS 
+  @param[in] SmBusAddress   Address that encodes the SMBUS Slave Address, SMBUS
                             Command, SMBUS Data Length, and PEC.
-  @param[in] Operation      Indicates which particular SMBus protocol it will use 
+  @param[in] Operation      Indicates which particular SMBus protocol it will use
                             to execute the SMBus transactions.
-  @param[in] Length         A pointer to signify the number of bytes that this 
+  @param[in] Length         A pointer to signify the number of bytes that this
                             operation will do.
-  @param[in] Buffer         Contains the value of data to execute to the SMBUS 
+  @param[in] Buffer         Contains the value of data to execute to the SMBUS
                             slave device.
-  
-  @retval RETURN_OUT_OF_RESOURCES   Not enough memory for the table to perform 
+
+  @retval RETURN_OUT_OF_RESOURCES   Not enough memory for the table to perform
                                     the operation.
   @retval RETURN_SUCCESS            The opcode was added.
 **/
 RETURN_STATUS
 EFIAPI
 S3BootScriptSaveSmbusExecute (
-  IN  UINTN                SmBusAddress, 
+  IN  UINTN                SmBusAddress,
   IN  EFI_SMBUS_OPERATION  Operation,
   IN  UINTN                *Length,
   IN  VOID                 *Buffer
@@ -269,8 +262,8 @@ S3BootScriptSaveSmbusExecute (
   Adds a record for an execution stall on the processor into a specified boot script table.
 
   @param[in] Duration   The duration in microseconds of the stall.
-  
-  @retval RETURN_OUT_OF_RESOURCES   Not enough memory for the table to perform 
+
+  @retval RETURN_OUT_OF_RESOURCES   Not enough memory for the table to perform
                                     the operation.
   @retval RETURN_SUCCESS            The opcode was added.
 **/
@@ -284,10 +277,10 @@ S3BootScriptSaveStall (
   Adds a record for dispatching specified arbitrary code into a specified boot script table.
 
   @param[in] EntryPoint   The entry point of the code to be dispatched.
-  @param[in] Context      The argument to be passed into the EntryPoint of the code 
+  @param[in] Context      The argument to be passed into the EntryPoint of the code
                           to be dispatched.
-  
-  @retval RETURN_OUT_OF_RESOURCES   Not enough memory for the table to perform 
+
+  @retval RETURN_OUT_OF_RESOURCES   Not enough memory for the table to perform
                                     the operation.
   @retval RETURN_SUCCESS            The opcode was added.
 **/
@@ -302,8 +295,8 @@ S3BootScriptSaveDispatch2 (
   Adds a record for dispatching specified arbitrary code into a specified boot script table.
 
   @param[in] EntryPoint   The entry point of the code to be dispatched.
-  
-  @retval RETURN_OUT_OF_RESOURCES   Not enough memory for the table to perform 
+
+  @retval RETURN_OUT_OF_RESOURCES   Not enough memory for the table to perform
                                     the operation.
   @retval RETURN_SUCCESS            The opcode was added.
 **/
@@ -314,7 +307,7 @@ S3BootScriptSaveDispatch (
   );
 
 /**
-  Adds a record for memory reads of the memory location and continues when the exit 
+  Adds a record for memory reads of the memory location and continues when the exit
   criteria is satisfied, or after a defined duration.
 
   Please aware, below interface is different with PI specification, Vol 5:
@@ -324,13 +317,13 @@ S3BootScriptSaveDispatch (
 
   @param[in] Width       The width of the memory operations.
   @param[in] Address     The base address of the memory operations.
-  @param[in] BitMask     A pointer to the bit mask to be AND-ed with the data read 
+  @param[in] BitMask     A pointer to the bit mask to be AND-ed with the data read
                          from the register.
   @param[in] BitValue    A pointer to the data value after to be Masked.
   @param[in] Duration    The duration in microseconds of the stall.
   @param[in] LoopTimes   The times of the register polling.
 
-  @retval RETURN_OUT_OF_RESOURCES   Not enough memory for the table to perform 
+  @retval RETURN_OUT_OF_RESOURCES   Not enough memory for the table to perform
                                     the operation.
   @retval RETURN_SUCCESS            The opcode was added.
 
@@ -347,13 +340,13 @@ S3BootScriptSaveMemPoll (
   );
 
 /**
-  Store arbitrary information in the boot script table. This opcode is a no-op on 
+  Store arbitrary information in the boot script table. This opcode is a no-op on
   dispatch and is only used for debugging script issues.
-  
+
   @param[in] InformationLength   Length of the data in bytes
   @param[in] Information        Information to be logged in the boot scrpit
- 
-  @retval RETURN_OUT_OF_RESOURCES   Not enough memory for the table to perform 
+
+  @retval RETURN_OUT_OF_RESOURCES   Not enough memory for the table to perform
                                     the operation.
   @retval RETURN_SUCCESS            The opcode was added.
 
@@ -361,27 +354,27 @@ S3BootScriptSaveMemPoll (
 RETURN_STATUS
 EFIAPI
 S3BootScriptSaveInformation (
-  IN  UINT32  InformationLength, 
+  IN  UINT32  InformationLength,
   IN  VOID    *Information
   );
 /**
   Adds a record for I/O reads the I/O location and continues when the exit criteria
    is satisfied, or after a defined duration.
-  
-  @param  Width                 The width of the I/O operations. 
+
+  @param  Width                 The width of the I/O operations.
   @param  Address               The base address of the I/O operations.
   @param  Data                  The comparison value used for the polling exit criteria.
-  @param  DataMask              The mask used for the polling criteria. The bits in 
-                                the bytes below Width which are zero in Data are 
+  @param  DataMask              The mask used for the polling criteria. The bits in
+                                the bytes below Width which are zero in Data are
                                 ignored when polling the memory address.
-  @param  Delay                 The number of 100ns units to poll. Note that timer 
-                                available may be of insufficient granularity, so the 
+  @param  Delay                 The number of 100ns units to poll. Note that timer
+                                available may be of insufficient granularity, so the
                                 delay may be longer.
 
- @retval RETURN_OUT_OF_RESOURCES  Not enough memory for the table to perform the 
+ @retval RETURN_OUT_OF_RESOURCES  Not enough memory for the table to perform the
                                   operation.
  @retval RETURN_SUCCESS           The opcode was added.
- @note   The FRAMEWORK version implementation does not support this API 
+ @note   The FRAMEWORK version implementation does not support this API
 **/
 RETURN_STATUS
 EFIAPI
@@ -389,29 +382,29 @@ S3BootScriptSaveIoPoll (
   IN S3_BOOT_SCRIPT_LIB_WIDTH       Width,
   IN UINT64                     Address,
   IN VOID                      *Data,
-  IN VOID                      *DataMask, 
-  IN UINT64                     Delay   
+  IN VOID                      *DataMask,
+  IN UINT64                     Delay
   );
 
 /**
-  Adds a record for PCI configuration space reads and continues when the exit 
+  Adds a record for PCI configuration space reads and continues when the exit
   criteria is satisfied ,or after a defined duration.
 
-  @param  Width                 The width of the I/O operations. 
+  @param  Width                 The width of the I/O operations.
   @param  Address               The address within the PCI configuration space.
-  @param  Data                  The comparison value used for the polling exit 
+  @param  Data                  The comparison value used for the polling exit
                                 criteria.
-  @param  DataMask              Mask used for the polling criteria. The bits in 
+  @param  DataMask              Mask used for the polling criteria. The bits in
                                 the bytes below Width which are zero in Data are
                                 ignored when polling the memory address.
-  @param  Delay                 The number of 100ns units to poll. Note that timer 
-                                available may be of insufficient granularity, so the 
+  @param  Delay                 The number of 100ns units to poll. Note that timer
+                                available may be of insufficient granularity, so the
                                 delay may be longer.
 
- @retval RETURN_OUT_OF_RESOURCES  Not enough memory for the table to perform the 
+ @retval RETURN_OUT_OF_RESOURCES  Not enough memory for the table to perform the
                                  operation.
  @retval RETURN_SUCCESS           The opcode was added.
- @note   The FRAMEWORK version implementation does not support this API 
+ @note   The FRAMEWORK version implementation does not support this API
 **/
 RETURN_STATUS
 EFIAPI
@@ -423,27 +416,27 @@ S3BootScriptSavePciPoll (
    IN UINT64                     Delay
   );
 /**
-  Adds a record for PCI configuration space reads and continues when the exit criteria 
+  Adds a record for PCI configuration space reads and continues when the exit criteria
   is satisfied, or after a defined duration.
 
-  @param  Width                 The width of the I/O operations. 
+  @param  Width                 The width of the I/O operations.
   @param  Segment               The PCI segment number for Address.
   @param  Address               The address within the PCI configuration space.
-  @param  Data                  The comparison value used for the polling exit 
+  @param  Data                  The comparison value used for the polling exit
                                 criteria.
-  @param  DataMask              Mask used for the polling criteria. The bits in 
+  @param  DataMask              Mask used for the polling criteria. The bits in
                                 the bytes below Width which are zero
                                 in Data are ignored when polling the memory address
-  @param  Delay                 The number of 100ns units to poll. Note that timer 
-                                available may be of insufficient granularity so the delay 
+  @param  Delay                 The number of 100ns units to poll. Note that timer
+                                available may be of insufficient granularity so the delay
                                 may be longer.
 
-  @retval RETURN_OUT_OF_RESOURCES  Not enough memory for the table to perform the 
+  @retval RETURN_OUT_OF_RESOURCES  Not enough memory for the table to perform the
                                    operation.
   @retval RETURN_SUCCESS           The opcode was added.
-  @note  A known Limitations in the implementation: When interpreting the opcode  
+  @note  A known Limitations in the implementation: When interpreting the opcode
          EFI_BOOT_SCRIPT_PCI_CONFIG2_WRITE_OPCODE, EFI_BOOT_SCRIPT_PCI_CONFIG2_READ_WRITE_OPCODE
-         and EFI_BOOT_SCRIPT_PCI_CONFIG2_POLL_OPCODE, the 'Segment' parameter is assumed as 
+         and EFI_BOOT_SCRIPT_PCI_CONFIG2_POLL_OPCODE, the 'Segment' parameter is assumed as
          Zero, or else, assert.
          The FRAMEWORK version implementation does not support this API.
 
@@ -459,13 +452,13 @@ S3BootScriptSavePci2Poll (
    IN UINT64                        Delay
   );
 /**
-  Save ASCII string information specified by Buffer to boot script with opcode 
+  Save ASCII string information specified by Buffer to boot script with opcode
   EFI_BOOT_SCRIPT_INFORMATION_OPCODE.
 
-  @param[in] String   The Null-terminated ASCII string to store into the S3 boot 
+  @param[in] String   The Null-terminated ASCII string to store into the S3 boot
                       script table.
 
-  @retval RETURN_OUT_OF_RESOURCES   Not enough memory for the table to perform 
+  @retval RETURN_OUT_OF_RESOURCES   Not enough memory for the table to perform
                                     the operation.
   @retval RETURN_SUCCESS            The opcode was added.
 
@@ -477,27 +470,27 @@ S3BootScriptSaveInformationAsciiString (
   );
 
 /**
-  This is an function to close the S3 boot script table. The function could only 
-  be called in BOOT time phase. To comply with the Framework spec definition on 
+  This is an function to close the S3 boot script table. The function could only
+  be called in BOOT time phase. To comply with the Framework spec definition on
   EFI_BOOT_SCRIPT_SAVE_PROTOCOL.CloseTable(), this function will fulfill following things:
   1. Closes the specified boot script table
-  2. It allocates a new memory pool to duplicate all the boot scripts in the specified table. 
-     Once this function is called, the table maintained by the library will be destroyed 
+  2. It allocates a new memory pool to duplicate all the boot scripts in the specified table.
+     Once this function is called, the table maintained by the library will be destroyed
      after it is copied into the allocated pool.
-  3. Any attempts to add a script record after calling this function will cause a 
+  3. Any attempts to add a script record after calling this function will cause a
      new table to be created by the library.
-  4. The base address of the allocated pool will be returned in Address. Note that 
-     after using the boot script table, the CALLER is responsible for freeing the 
-     pool that is allocated by this function. 
+  4. The base address of the allocated pool will be returned in Address. Note that
+     after using the boot script table, the CALLER is responsible for freeing the
+     pool that is allocated by this function.
 
-  In Spec PI1.1, this EFI_BOOT_SCRIPT_SAVE_PROTOCOL.CloseTable() is retired. This 
+  In Spec PI1.1, this EFI_BOOT_SCRIPT_SAVE_PROTOCOL.CloseTable() is retired. This
   API is supplied here to meet the requirements of the Framework Spec.
-  
+
   If anyone does call CloseTable() on a real platform, then the caller is responsible
-  for figuring out how to get the script to run on an S3 resume because the boot script 
+  for figuring out how to get the script to run on an S3 resume because the boot script
   maintained by the lib will be destroyed.
- 
-  @return the base address of the new copy of the boot script table.   
+
+  @return the base address of the new copy of the boot script table.
 
 **/
 UINT8*
@@ -510,7 +503,7 @@ S3BootScriptCloseTable (
   Executes the S3 boot script table.
 
   @retval RETURN_SUCCESS       The boot script table was executed successfully.
-  @retval RETURN_UNSUPPORTED   Invalid script table or opcode.  
+  @retval RETURN_UNSUPPORTED   Invalid script table or opcode.
 
 **/
 RETURN_STATUS
@@ -519,25 +512,25 @@ S3BootScriptExecute (
   VOID
   );
 /**
-  Move the last boot script entry to the position 
+  Move the last boot script entry to the position
 
-  @param  BeforeOrAfter         Specifies whether the opcode is stored before 
-                                (TRUE) or after (FALSE) the positionin the boot 
-                                script table specified by Position. If Position 
-                                is NULL or points to NULL then the new opcode is 
-                                inserted at the beginning of the table (if TRUE) 
+  @param  BeforeOrAfter         Specifies whether the opcode is stored before
+                                (TRUE) or after (FALSE) the positionin the boot
+                                script table specified by Position. If Position
+                                is NULL or points to NULL then the new opcode is
+                                inserted at the beginning of the table (if TRUE)
                                 or end of the table (if FALSE).
-  @param  Position              On entry, specifies the position in the boot script 
-                                table where the opcode will be inserted, either 
-                                before or after, depending on BeforeOrAfter. On 
-                                exit, specifies the position of the inserted opcode 
+  @param  Position              On entry, specifies the position in the boot script
+                                table where the opcode will be inserted, either
+                                before or after, depending on BeforeOrAfter. On
+                                exit, specifies the position of the inserted opcode
                                 in the boot script table.
 
   @retval RETURN_OUT_OF_RESOURCES  The table is not available.
-  @retval RETURN_INVALID_PARAMETER The Position is not a valid position in the 
+  @retval RETURN_INVALID_PARAMETER The Position is not a valid position in the
                                    boot script table.
   @retval RETURN_SUCCESS           The opcode was inserted.
-  @note   The FRAMEWORK version implementation does not support this API. 
+  @note   The FRAMEWORK version implementation does not support this API.
 **/
 RETURN_STATUS
 EFIAPI
@@ -549,28 +542,28 @@ S3BootScriptMoveLastOpcode (
   Find a label within the boot script table and, if not present, optionally create it.
 
   @param  BeforeOrAfter         Specifies whether the opcode is stored before (TRUE)
-                                or after (FALSE) the position in the boot script table 
+                                or after (FALSE) the position in the boot script table
                                 specified by Position.
-  @param  CreateIfNotFound      Specifies whether the label will be created if the  
+  @param  CreateIfNotFound      Specifies whether the label will be created if the
                                 label does not exists (TRUE) or not (FALSE).
-  @param  Position              On entry, specifies the position in the boot script 
-                                table where the opcode will be inserted, either 
-                                before or after, depending on BeforeOrAfter. On exit, 
-                                specifies the positionof the inserted opcode in 
+  @param  Position              On entry, specifies the position in the boot script
+                                table where the opcode will be inserted, either
+                                before or after, depending on BeforeOrAfter. On exit,
+                                specifies the positionof the inserted opcode in
                                 the boot script table.
-  @param  Label                 Points to the label which will be inserted in the 
+  @param  Label                 Points to the label which will be inserted in the
                                 boot script table.
-  @retval EFI_SUCCESS           The operation succeeded. A record was added into 
+  @retval EFI_SUCCESS           The operation succeeded. A record was added into
                                 the specified script table.
-  @retval EFI_INVALID_PARAMETER The parameter is illegal or the given boot script 
-                                is not supported. If the opcode is unknow or not 
+  @retval EFI_INVALID_PARAMETER The parameter is illegal or the given boot script
+                                is not supported. If the opcode is unknow or not
                                 supported because of the PCD Feature Flags.
   @retval EFI_OUT_OF_RESOURCES  There is insufficient memory to store the boot script.
-  @note   The FRAMEWORK version implementation does not support this API 
+  @note   The FRAMEWORK version implementation does not support this API
 
 **/
 RETURN_STATUS
-EFIAPI 
+EFIAPI
 S3BootScriptLabel (
   IN       BOOLEAN                      BeforeOrAfter,
   IN       BOOLEAN                      CreateIfNotFound,
@@ -585,14 +578,14 @@ S3BootScriptLabel (
 
   @retval EFI_SUCCESS           The operation succeeded. A record was added into the
                                 specified script table.
-  @retval EFI_INVALID_PARAMETER The parameter is illegal or the given boot script 
+  @retval EFI_INVALID_PARAMETER The parameter is illegal or the given boot script
                                 is not supported. If the opcode is unknow or not s
                                 upported because of the PCD Feature Flags.
   @retval EFI_OUT_OF_RESOURCES  There is insufficient memory to store the boot script.
-  @note   The FRAMEWORK version implementation does not support this API 
+  @note   The FRAMEWORK version implementation does not support this API
 **/
 RETURN_STATUS
-EFIAPI 
+EFIAPI
 S3BootScriptCompare (
   IN  UINT8                       *Position1,
   IN  UINT8                       *Position2,
diff --git a/MdePkg/Include/Library/S3IoLib.h b/MdePkg/Include/Library/S3IoLib.h
index 5905eaf7191d..f276050d09b8 100644
--- a/MdePkg/Include/Library/S3IoLib.h
+++ b/MdePkg/Include/Library/S3IoLib.h
@@ -1,18 +1,11 @@
 /** @file
   I/O and MMIO Library Services that do I/O and also enable the I/O operation
   to be replayed during an S3 resume. This library class maps directly on top
-  of the IoLib class. 
+  of the IoLib class.
 
-  Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
 
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions
-  of the BSD License which accompanies this distribution.  The
-  full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -117,7 +110,7 @@ S3IoAnd8 (
 
 /**
   Reads an 8-bit I/O port, performs a bitwise AND followed by a bitwise
-  inclusive OR, writes the result back to the 8-bit I/O port, and saves 
+  inclusive OR, writes the result back to the 8-bit I/O port, and saves
   the value in the S3 script to be replayed on S3 resume.
 
   Reads the 8-bit I/O port specified by Port, performs a bitwise AND between
@@ -179,7 +172,7 @@ S3IoBitFieldRead8 (
 
   Writes Value to the bit field of the I/O register. The bit field is specified
   by the StartBit and the EndBit. All other bits in the destination I/O
-  register are preserved. The value written to the I/O port is returned. 
+  register are preserved. The value written to the I/O port is returned.
   Remaining bits in Value are stripped.
 
   If 8-bit I/O port operations are not supported, then ASSERT().
@@ -209,7 +202,7 @@ S3IoBitFieldWrite8 (
 
 /**
   Reads a bit field in an 8-bit port, performs a bitwise OR, writes the
-  result back to the bit field in the 8-bit port, and saves the value in the 
+  result back to the bit field in the 8-bit port, and saves the value in the
   S3 script to be replayed on S3 resume.
 
   Reads the 8-bit I/O port specified by Port, performs a bitwise OR
@@ -245,7 +238,7 @@ S3IoBitFieldOr8 (
 
 /**
   Reads a bit field in an 8-bit port, performs a bitwise AND, writes the
-  result back to the bit field in the 8-bit port, and saves the value in the 
+  result back to the bit field in the 8-bit port, and saves the value in the
   S3 script to be replayed on S3 resume.
 
   Reads the 8-bit I/O port specified by Port, performs a bitwise AND between
@@ -365,7 +358,7 @@ S3IoWrite16 (
 
 /**
   Reads a 16-bit I/O port, performs a bitwise OR, writes the
-  result back to the 16-bit I/O port, and saves the value in the S3 script to 
+  result back to the 16-bit I/O port, and saves the value in the S3 script to
   be replayed on S3 resume.
 
   Reads the 16-bit I/O port specified by Port, performs a bitwise OR
@@ -474,7 +467,7 @@ S3IoBitFieldRead16 (
   );
 
 /**
-  Writes a bit field to an I/O register, and saves the value in the S3 script 
+  Writes a bit field to an I/O register, and saves the value in the S3 script
   to be replayed on S3 resume.
 
   Writes Value to the bit field of the I/O register. The bit field is specified
@@ -509,7 +502,7 @@ S3IoBitFieldWrite16 (
 
 /**
   Reads a bit field in a 16-bit port, performs a bitwise OR, writes the
-  result back to the bit field in the 16-bit port, and saves the value in the 
+  result back to the bit field in the 16-bit port, and saves the value in the
   S3 script to be replayed on S3 resume.
 
   Reads the 16-bit I/O port specified by Port, performs a bitwise OR
@@ -545,7 +538,7 @@ S3IoBitFieldOr16 (
 
 /**
   Reads a bit field in a 16-bit port, performs a bitwise AND, writes the
-  result back to the bit field in the 16-bit port, and saves the value in the 
+  result back to the bit field in the 16-bit port, and saves the value in the
   S3 script to be replayed on S3 resume.
 
   Reads the 16-bit I/O port specified by Port, performs a bitwise AND between
@@ -582,7 +575,7 @@ S3IoBitFieldAnd16 (
 /**
   Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
   bitwise OR, writes the result back to the bit field in the
-  16-bit port, and saves the value in the S3 script to be replayed on S3 
+  16-bit port, and saves the value in the S3 script to be replayed on S3
   resume.
 
   Reads the 16-bit I/O port specified by Port, performs a bitwise AND followed
@@ -666,7 +659,7 @@ S3IoWrite32 (
 
 /**
   Reads a 32-bit I/O port, performs a bitwise OR, writes the
-  result back to the 32-bit I/O port, and saves the value in the S3 script to 
+  result back to the 32-bit I/O port, and saves the value in the S3 script to
   be replayed on S3 resume.
 
   Reads the 32-bit I/O port specified by Port, performs a bitwise OR
@@ -718,7 +711,7 @@ S3IoAnd32 (
 
 /**
   Reads a 32-bit I/O port, performs a bitwise AND followed by a bitwise
-  inclusive OR, writes the result back to the 32-bit I/O port, and saves 
+  inclusive OR, writes the result back to the 32-bit I/O port, and saves
   the value in the S3 script to be replayed on S3 resume.
 
   Reads the 32-bit I/O port specified by Port, performs a bitwise AND between
@@ -810,7 +803,7 @@ S3IoBitFieldWrite32 (
 
 /**
   Reads a bit field in a 32-bit port, performs a bitwise OR, writes the
-  result back to the bit field in the 32-bit port, and saves the value in the 
+  result back to the bit field in the 32-bit port, and saves the value in the
   S3 script to be replayed on S3 resume.
 
   Reads the 32-bit I/O port specified by Port, performs a bitwise OR
@@ -846,7 +839,7 @@ S3IoBitFieldOr32 (
 
 /**
   Reads a bit field in a 32-bit port, performs a bitwise AND, writes the
-  result back to the bit field in the 32-bit port, and saves the value in the 
+  result back to the bit field in the 32-bit port, and saves the value in the
   S3 script to be replayed on S3 resume.
 
   Reads the 32-bit I/O port specified by Port, performs a bitwise AND between
@@ -883,7 +876,7 @@ S3IoBitFieldAnd32 (
 /**
   Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
   bitwise OR, writes the result back to the bit field in the
-  32-bit port, and saves the value in the S3 script to be replayed on S3 
+  32-bit port, and saves the value in the S3 script to be replayed on S3
   resume.
 
   Reads the 32-bit I/O port specified by Port, performs a bitwise AND followed
@@ -967,7 +960,7 @@ S3IoWrite64 (
 
 /**
   Reads a 64-bit I/O port, performs a bitwise OR, writes the
-  result back to the 64-bit I/O port, and saves the value in the S3 script to 
+  result back to the 64-bit I/O port, and saves the value in the S3 script to
   be replayed on S3 resume.
 
   Reads the 64-bit I/O port specified by Port, performs a bitwise OR
@@ -1111,7 +1104,7 @@ S3IoBitFieldWrite64 (
 
 /**
   Reads a bit field in a 64-bit port, performs a bitwise OR, writes the
-  result back to the bit field in the 64-bit port, and saves the value in the 
+  result back to the bit field in the 64-bit port, and saves the value in the
   S3 script to be replayed on S3 resume.
 
   Reads the 64-bit I/O port specified by Port, performs a bitwise OR
@@ -1147,7 +1140,7 @@ S3IoBitFieldOr64 (
 
 /**
   Reads a bit field in a 64-bit port, performs a bitwise AND, writes the
-  result back to the bit field in the 64-bit port, and saves the value in the 
+  result back to the bit field in the 64-bit port, and saves the value in the
   S3 script to be replayed on S3 resume.
 
   Reads the 64-bit I/O port specified by Port, performs a bitwise AND between
@@ -1184,7 +1177,7 @@ S3IoBitFieldAnd64 (
 /**
   Reads a bit field in a 64-bit port, performs a bitwise AND followed by a
   bitwise OR, writes the result back to the bit field in the
-  64-bit port, and saves the value in the S3 script to be replayed on S3 
+  64-bit port, and saves the value in the S3 script to be replayed on S3
   resume.
 
   Reads the 64-bit I/O port specified by Port, performs a bitwise AND followed
@@ -1223,7 +1216,7 @@ S3IoBitFieldAndThenOr64 (
   );
 
 /**
-  Reads an 8-bit MMIO register, and saves the value in the S3 script to be 
+  Reads an 8-bit MMIO register, and saves the value in the S3 script to be
   replayed on S3 resume.
 
   Reads the 8-bit MMIO register specified by Address. The 8-bit read value is
@@ -1244,7 +1237,7 @@ S3MmioRead8 (
   );
 
 /**
-  Writes an 8-bit MMIO register, and saves the value in the S3 script to be 
+  Writes an 8-bit MMIO register, and saves the value in the S3 script to be
   replayed on S3 resume.
 
   Writes the 8-bit MMIO register specified by Address with the value specified
@@ -1268,7 +1261,7 @@ S3MmioWrite8 (
 
 /**
   Reads an 8-bit MMIO register, performs a bitwise OR, writes the
-  result back to the 8-bit MMIO register, and saves the value in the S3 script 
+  result back to the 8-bit MMIO register, and saves the value in the S3 script
   to be replayed on S3 resume.
 
   Reads the 8-bit MMIO register specified by Address, performs a bitwise
@@ -1294,7 +1287,7 @@ S3MmioOr8 (
 
 /**
   Reads an 8-bit MMIO register, performs a bitwise AND, writes the result
-  back to the 8-bit MMIO register, and saves the value in the S3 script to be 
+  back to the 8-bit MMIO register, and saves the value in the S3 script to be
   replayed on S3 resume.
 
   Reads the 8-bit MMIO register specified by Address, performs a bitwise AND
@@ -1320,7 +1313,7 @@ S3MmioAnd8 (
 
 /**
   Reads an 8-bit MMIO register, performs a bitwise AND followed by a bitwise
-  inclusive OR, writes the result back to the 8-bit MMIO register, and saves 
+  inclusive OR, writes the result back to the 8-bit MMIO register, and saves
   the value in the S3 script to be replayed on S3 resume.
 
   Reads the 8-bit MMIO register specified by Address, performs a bitwise AND
@@ -1410,7 +1403,7 @@ S3MmioBitFieldWrite8 (
   );
 
 /**
-  Reads a bit field in an 8-bit MMIO register, performs a bitwise OR, 
+  Reads a bit field in an 8-bit MMIO register, performs a bitwise OR,
   writes the result back to the bit field in the 8-bit MMIO register, and saves
   the value in the S3 script to be replayed on S3 resume.
 
@@ -1571,7 +1564,7 @@ S3MmioWrite16 (
 
 /**
   Reads a 16-bit MMIO register, performs a bitwise OR, writes the
-  result back to the 16-bit MMIO register, and saves the value in the S3 script 
+  result back to the 16-bit MMIO register, and saves the value in the S3 script
   to be replayed on S3 resume.
 
   Reads the 16-bit MMIO register specified by Address, performs a bitwise
@@ -1597,7 +1590,7 @@ S3MmioOr16 (
 
 /**
   Reads a 16-bit MMIO register, performs a bitwise AND, writes the result
-  back to the 16-bit MMIO register, and saves the value in the S3 script to be 
+  back to the 16-bit MMIO register, and saves the value in the S3 script to be
   replayed on S3 resume.
 
   Reads the 16-bit MMIO register specified by Address, performs a bitwise AND
@@ -1623,7 +1616,7 @@ S3MmioAnd16 (
 
 /**
   Reads a 16-bit MMIO register, performs a bitwise AND followed by a bitwise
-  inclusive OR, writes the result back to the 16-bit MMIO register, and 
+  inclusive OR, writes the result back to the 16-bit MMIO register, and
   saves the value in the S3 script to be replayed on S3 resume.
 
   Reads the 16-bit MMIO register specified by Address, performs a bitwise AND
@@ -1713,8 +1706,8 @@ S3MmioBitFieldWrite16 (
   );
 
 /**
-  Reads a bit field in a 16-bit MMIO register, performs a bitwise OR, 
-  writes the result back to the bit field in the 16-bit MMIO register, and 
+  Reads a bit field in a 16-bit MMIO register, performs a bitwise OR,
+  writes the result back to the bit field in the 16-bit MMIO register, and
   saves the value in the S3 script to be replayed on S3 resume.
 
   Reads the 16-bit MMIO register specified by Address, performs a bitwise
@@ -1751,7 +1744,7 @@ S3MmioBitFieldOr16 (
 
 /**
   Reads a bit field in a 16-bit MMIO register, performs a bitwise AND, and
-  writes the result back to the bit field in the 16-bit MMIO register and 
+  writes the result back to the bit field in the 16-bit MMIO register and
   saves the value in the S3 script to be replayed on S3 resume.
 
   Reads the 16-bit MMIO register specified by Address, performs a bitwise AND
@@ -1828,7 +1821,7 @@ S3MmioBitFieldAndThenOr16 (
   );
 
 /**
-  Reads a 32-bit MMIO register saves the value in the S3 script to be 
+  Reads a 32-bit MMIO register saves the value in the S3 script to be
   replayed on S3 resume.
 
   Reads the 32-bit MMIO register specified by Address. The 32-bit read value is
@@ -1849,7 +1842,7 @@ S3MmioRead32 (
   );
 
 /**
-  Writes a 32-bit MMIO register, and saves the value in the S3 script to be 
+  Writes a 32-bit MMIO register, and saves the value in the S3 script to be
   replayed on S3 resume.
 
   Writes the 32-bit MMIO register specified by Address with the value specified
@@ -1873,7 +1866,7 @@ S3MmioWrite32 (
 
 /**
   Reads a 32-bit MMIO register, performs a bitwise OR, writes the
-  result back to the 32-bit MMIO register, and saves the value in the S3 script 
+  result back to the 32-bit MMIO register, and saves the value in the S3 script
   to be replayed on S3 resume.
 
   Reads the 32-bit MMIO register specified by Address, performs a bitwise
@@ -1899,7 +1892,7 @@ S3MmioOr32 (
 
 /**
   Reads a 32-bit MMIO register, performs a bitwise AND, writes the result
-  back to the 32-bit MMIO register, and saves the value in the S3 script to be 
+  back to the 32-bit MMIO register, and saves the value in the S3 script to be
   replayed on S3 resume.
 
   Reads the 32-bit MMIO register specified by Address, performs a bitwise AND
@@ -1925,7 +1918,7 @@ S3MmioAnd32 (
 
 /**
   Reads a 32-bit MMIO register, performs a bitwise AND followed by a bitwise
-  inclusive OR, writes the result back to the 32-bit MMIO register, and 
+  inclusive OR, writes the result back to the 32-bit MMIO register, and
   saves the value in the S3 script to be replayed on S3 resume.
 
   Reads the 32-bit MMIO register specified by Address, performs a bitwise AND
@@ -1953,7 +1946,7 @@ S3MmioAndThenOr32 (
   );
 
 /**
-  Reads a bit field of a MMIO register, and saves the value in the S3 script 
+  Reads a bit field of a MMIO register, and saves the value in the S3 script
   to be replayed on S3 resume.
 
   Reads the bit field in a 32-bit MMIO register. The bit field is specified by
@@ -1982,7 +1975,7 @@ S3MmioBitFieldRead32 (
   );
 
 /**
-  Writes a bit field to a MMIO register, and saves the value in the S3 script 
+  Writes a bit field to a MMIO register, and saves the value in the S3 script
   to be replayed on S3 resume.
 
   Writes Value to the bit field of the MMIO register. The bit field is
@@ -2015,8 +2008,8 @@ S3MmioBitFieldWrite32 (
   );
 
 /**
-  Reads a bit field in a 32-bit MMIO register, performs a bitwise OR, 
-  writes the result back to the bit field in the 32-bit MMIO register, and 
+  Reads a bit field in a 32-bit MMIO register, performs a bitwise OR,
+  writes the result back to the bit field in the 32-bit MMIO register, and
   saves the value in the S3 script to be replayed on S3 resume.
 
   Reads the 32-bit MMIO register specified by Address, performs a bitwise
@@ -2053,7 +2046,7 @@ S3MmioBitFieldOr32 (
 
 /**
   Reads a bit field in a 32-bit MMIO register, performs a bitwise AND, and
-  writes the result back to the bit field in the 32-bit MMIO register and 
+  writes the result back to the bit field in the 32-bit MMIO register and
   saves the value in the S3 script to be replayed on S3 resume.
 
   Reads the 32-bit MMIO register specified by Address, performs a bitwise AND
@@ -2130,7 +2123,7 @@ S3MmioBitFieldAndThenOr32 (
   );
 
 /**
-  Reads a 64-bit MMIO register, and saves the value in the S3 script to be 
+  Reads a 64-bit MMIO register, and saves the value in the S3 script to be
   replayed on S3 resume.
 
   Reads the 64-bit MMIO register specified by Address. The 64-bit read value is
@@ -2151,7 +2144,7 @@ S3MmioRead64 (
   );
 
 /**
-  Writes a 64-bit MMIO register, and saves the value in the S3 script to be 
+  Writes a 64-bit MMIO register, and saves the value in the S3 script to be
   replayed on S3 resume.
 
   Writes the 64-bit MMIO register specified by Address with the value specified
@@ -2175,7 +2168,7 @@ S3MmioWrite64 (
 
 /**
   Reads a 64-bit MMIO register, performs a bitwise OR, writes the
-  result back to the 64-bit MMIO register, and saves the value in the S3 script 
+  result back to the 64-bit MMIO register, and saves the value in the S3 script
   to be replayed on S3 resume.
 
   Reads the 64-bit MMIO register specified by Address, performs a bitwise
@@ -2201,7 +2194,7 @@ S3MmioOr64 (
 
 /**
   Reads a 64-bit MMIO register, performs a bitwise AND, writes the result
-  back to the 64-bit MMIO register, and saves the value in the S3 script to be 
+  back to the 64-bit MMIO register, and saves the value in the S3 script to be
   replayed on S3 resume.
 
   Reads the 64-bit MMIO register specified by Address, performs a bitwise AND
@@ -2227,7 +2220,7 @@ S3MmioAnd64 (
 
 /**
   Reads a 64-bit MMIO register, performs a bitwise AND followed by a bitwise
-  inclusive OR, writes the result back to the 64-bit MMIO register, and 
+  inclusive OR, writes the result back to the 64-bit MMIO register, and
   saves the value in the S3 script to be replayed on S3 resume.
 
   Reads the 64-bit MMIO register specified by Address, performs a bitwise AND
@@ -2317,8 +2310,8 @@ S3MmioBitFieldWrite64 (
   );
 
 /**
-  Reads a bit field in a 64-bit MMIO register, performs a bitwise OR, 
-  writes the result back to the bit field in the 64-bit MMIO register, and 
+  Reads a bit field in a 64-bit MMIO register, performs a bitwise OR,
+  writes the result back to the bit field in the 64-bit MMIO register, and
   saves the value in the S3 script to be replayed on S3 resume.
 
   Reads the 64-bit MMIO register specified by Address, performs a bitwise
@@ -2435,11 +2428,11 @@ S3MmioBitFieldAndThenOr64 (
   Copies data from MMIO region to system memory by using 8-bit access,
   and saves the value in the S3 script to be replayed on S3 resume.
 
-  Copy data from MMIO region specified by starting address StartAddress 
-  to system memory specified by Buffer by using 8-bit access. The total 
+  Copy data from MMIO region specified by starting address StartAddress
+  to system memory specified by Buffer by using 8-bit access. The total
   number of bytes to be copied is specified by Length. Buffer is returned.
-  
-  If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT(). 
+
+  If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
   If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
 
 
@@ -2462,13 +2455,13 @@ S3MmioReadBuffer8 (
   Copies data from MMIO region to system memory by using 16-bit access,
   and saves the value in the S3 script to be replayed on S3 resume.
 
-  Copy data from MMIO region specified by starting address StartAddress 
-  to system memory specified by Buffer by using 16-bit access. The total 
+  Copy data from MMIO region specified by starting address StartAddress
+  to system memory specified by Buffer by using 16-bit access. The total
   number of bytes to be copied is specified by Length. Buffer is returned.
-  
+
   If StartAddress is not aligned on a 16-bit boundary, then ASSERT().
 
-  If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT(). 
+  If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
   If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
 
   If Length is not aligned on a 16-bit boundary, then ASSERT().
@@ -2493,13 +2486,13 @@ S3MmioReadBuffer16 (
   Copies data from MMIO region to system memory by using 32-bit access,
   and saves the value in the S3 script to be replayed on S3 resume.
 
-  Copy data from MMIO region specified by starting address StartAddress 
-  to system memory specified by Buffer by using 32-bit access. The total 
+  Copy data from MMIO region specified by starting address StartAddress
+  to system memory specified by Buffer by using 32-bit access. The total
   number of byte to be copied is specified by Length. Buffer is returned.
-  
+
   If StartAddress is not aligned on a 32-bit boundary, then ASSERT().
 
-  If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT(). 
+  If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
   If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
 
   If Length is not aligned on a 32-bit boundary, then ASSERT().
@@ -2524,13 +2517,13 @@ S3MmioReadBuffer32 (
   Copies data from MMIO region to system memory by using 64-bit access,
   and saves the value in the S3 script to be replayed on S3 resume.
 
-  Copy data from MMIO region specified by starting address StartAddress 
-  to system memory specified by Buffer by using 64-bit access. The total 
+  Copy data from MMIO region specified by starting address StartAddress
+  to system memory specified by Buffer by using 64-bit access. The total
   number of byte to be copied is specified by Length. Buffer is returned.
-  
+
   If StartAddress is not aligned on a 64-bit boundary, then ASSERT().
 
-  If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT(). 
+  If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
   If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
 
   If Length is not aligned on a 64-bit boundary, then ASSERT().
@@ -2555,11 +2548,11 @@ S3MmioReadBuffer64 (
   Copies data from system memory to MMIO region by using 8-bit access,
   and saves the value in the S3 script to be replayed on S3 resume.
 
-  Copy data from system memory specified by Buffer to MMIO region specified 
-  by starting address StartAddress by using 8-bit access. The total number 
+  Copy data from system memory specified by Buffer to MMIO region specified
+  by starting address StartAddress by using 8-bit access. The total number
   of byte to be copied is specified by Length. Buffer is returned.
-  
-  If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT(). 
+
+  If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
   If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().
 
 
@@ -2582,13 +2575,13 @@ S3MmioWriteBuffer8 (
   Copies data from system memory to MMIO region by using 16-bit access,
   and saves the value in the S3 script to be replayed on S3 resume.
 
-  Copy data from system memory specified by Buffer to MMIO region specified 
-  by starting address StartAddress by using 16-bit access. The total number 
+  Copy data from system memory specified by Buffer to MMIO region specified
+  by starting address StartAddress by using 16-bit access. The total number
   of bytes to be copied is specified by Length. Buffer is returned.
-  
+
   If StartAddress is not aligned on a 16-bit boundary, then ASSERT().
 
-  If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT(). 
+  If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
   If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().
 
   If Length is not aligned on a 16-bit boundary, then ASSERT().
@@ -2614,13 +2607,13 @@ S3MmioWriteBuffer16 (
   Copies data from system memory to MMIO region by using 32-bit access,
   and saves the value in the S3 script to be replayed on S3 resume.
 
-  Copy data from system memory specified by Buffer to MMIO region specified 
-  by starting address StartAddress by using 32-bit access. The total number 
+  Copy data from system memory specified by Buffer to MMIO region specified
+  by starting address StartAddress by using 32-bit access. The total number
   of bytes to be copied is specified by Length. Buffer is returned.
-  
+
   If StartAddress is not aligned on a 32-bit boundary, then ASSERT().
 
-  If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT(). 
+  If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
   If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().
 
   If Length is not aligned on a 32-bit boundary, then ASSERT().
@@ -2643,16 +2636,16 @@ S3MmioWriteBuffer32 (
   );
 
 /**
-  Copies data from system memory to MMIO region by using 64-bit access, 
+  Copies data from system memory to MMIO region by using 64-bit access,
   and saves the value in the S3 script to be replayed on S3 resume.
 
-  Copy data from system memory specified by Buffer to MMIO region specified 
-  by starting address StartAddress by using 64-bit access. The total number 
+  Copy data from system memory specified by Buffer to MMIO region specified
+  by starting address StartAddress by using 64-bit access. The total number
   of bytes to be copied is specified by Length. Buffer is returned.
-  
+
   If StartAddress is not aligned on a 64-bit boundary, then ASSERT().
 
-  If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT(). 
+  If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
   If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().
 
   If Length is not aligned on a 64-bit boundary, then ASSERT().
diff --git a/MdePkg/Include/Library/S3PciLib.h b/MdePkg/Include/Library/S3PciLib.h
index 3d8f497f9930..2d9ddc317c4c 100644
--- a/MdePkg/Include/Library/S3PciLib.h
+++ b/MdePkg/Include/Library/S3PciLib.h
@@ -1,18 +1,11 @@
 /** @file
   The PCI configuration Library Services that carry out PCI configuration and enable
   the PCI operations to be replayed during an S3 resume. This library class
-  maps directly on top of the PciLib class. 
+  maps directly on top of the PciLib class.
 
-  Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
 
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions
-  of the BSD License which accompanies this distribution.  The
-  full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -36,8 +29,8 @@
   (((Register) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
 
 /**
- 
-  Reads and returns the 8-bit PCI configuration register specified by Address, 
+
+  Reads and returns the 8-bit PCI configuration register specified by Address,
   and saves the value in the S3 script to be replayed on S3 resume.
   This function must guarantee that all PCI read and write operations are
   serialized.
@@ -813,7 +806,7 @@ S3PciAndThenOr32 (
   If StartBit is greater than 31, then ASSERT().
   If EndBit is greater than 31, then ASSERT().
   If EndBit is less than StartBit, then ASSERT().
- 
+
   @param[in] Address    The PCI configuration register to read.
   @param[in] StartBit   The ordinal of the least significant bit in the bit field.
                         Range 0..31.
diff --git a/MdePkg/Include/Library/S3PciSegmentLib.h b/MdePkg/Include/Library/S3PciSegmentLib.h
new file mode 100644
index 000000000000..5e8d70b4b05b
--- /dev/null
+++ b/MdePkg/Include/Library/S3PciSegmentLib.h
@@ -0,0 +1,1031 @@
+/** @file
+  The multiple segments PCI configuration Library Services that carry out
+  PCI configuration and enable the PCI operations to be replayed during an
+  S3 resume. This library class maps directly on top of the PciSegmentLib class.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __S3_PCI_SEGMENT_LIB__
+#define __S3_PCI_SEGMENT_LIB__
+
+
+/**
+  Macro that converts PCI Segment, PCI Bus, PCI Device, PCI Function,
+  and PCI Register to an address that can be passed to the S3 PCI Segment Library functions.
+
+  Computes an address that is compatible with the PCI Segment Library functions.
+  The unused upper bits of Segment, Bus, Device, Function,
+  and Register are stripped prior to the generation of the address.
+
+  @param  Segment   PCI Segment number.  Range 0..65535.
+  @param  Bus       PCI Bus number.  Range 0..255.
+  @param  Device    PCI Device number.  Range 0..31.
+  @param  Function  PCI Function number.  Range 0..7.
+  @param  Register  PCI Register number.  Range 0..255 for PCI.  Range 0..4095 for PCI Express.
+
+  @return The address that is compatible with the PCI Segment Library functions.
+
+**/
+#define S3_PCI_SEGMENT_LIB_ADDRESS(Segment,Bus,Device,Function,Register) \
+  ((Segment != 0) ? \
+    ( ((Register) & 0xfff)                 | \
+      (((Function) & 0x07) << 12)          | \
+      (((Device) & 0x1f) << 15)            | \
+      (((Bus) & 0xff) << 20)               | \
+      (LShiftU64 ((Segment) & 0xffff, 32))   \
+    ) :                                      \
+    ( ((Register) & 0xfff)                 | \
+      (((Function) & 0x07) << 12)          | \
+      (((Device) & 0x1f) << 15)            | \
+      (((Bus) & 0xff) << 20)                 \
+    )                                        \
+  )
+
+/**
+  Reads an 8-bit PCI configuration register, and saves the value in the S3 script to
+  be replayed on S3 resume.
+
+  Reads and returns the 8-bit PCI configuration register specified by Address.
+  This function must guarantee that all PCI read and write operations are serialized.
+
+  If any reserved bits in Address are set, then ASSERT().
+
+  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+
+  @return The 8-bit PCI configuration register specified by Address.
+
+**/
+UINT8
+EFIAPI
+S3PciSegmentRead8 (
+  IN UINT64                    Address
+  );
+
+/**
+  Writes an 8-bit PCI configuration register, and saves the value in the S3 script to
+  be replayed on S3 resume.
+
+  Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
+  Value is returned.  This function must guarantee that all PCI read and write operations are serialized.
+
+  If any reserved bits in Address are set, then ASSERT().
+
+  @param  Address     Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+  @param  Value       The value to write.
+
+  @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciSegmentWrite8 (
+  IN UINT64                    Address,
+  IN UINT8                     Value
+  );
+
+/**
+  Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value, and saves
+  the value in the S3 script to be replayed on S3 resume.
+
+  Reads the 8-bit PCI configuration register specified by Address,
+  performs a bitwise OR between the read result and the value specified by OrData,
+  and writes the result to the 8-bit PCI configuration register specified by Address.
+  The value written to the PCI configuration register is returned.
+  This function must guarantee that all PCI read and write operations are serialized.
+
+  If any reserved bits in Address are set, then ASSERT().
+
+  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+  @param  OrData    The value to OR with the PCI configuration register.
+
+  @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciSegmentOr8 (
+  IN UINT64                    Address,
+  IN UINT8                     OrData
+  );
+
+/**
+  Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value, and
+  saves the value in the S3 script to be replayed on S3 resume.
+
+  Reads the 8-bit PCI configuration register specified by Address,
+  performs a bitwise AND between the read result and the value specified by AndData,
+  and writes the result to the 8-bit PCI configuration register specified by Address.
+  The value written to the PCI configuration register is returned.
+  This function must guarantee that all PCI read and write operations are serialized.
+  If any reserved bits in Address are set, then ASSERT().
+
+  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+  @param  AndData   The value to AND with the PCI configuration register.
+
+  @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciSegmentAnd8 (
+  IN UINT64                    Address,
+  IN UINT8                     AndData
+  );
+
+/**
+  Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,
+  followed a bitwise OR with another 8-bit value, and saves the value in the S3 script to
+  be replayed on S3 resume.
+
+  Reads the 8-bit PCI configuration register specified by Address,
+  performs a bitwise AND between the read result and the value specified by AndData,
+  performs a bitwise OR between the result of the AND operation and the value specified by OrData,
+  and writes the result to the 8-bit PCI configuration register specified by Address.
+  The value written to the PCI configuration register is returned.
+  This function must guarantee that all PCI read and write operations are serialized.
+
+  If any reserved bits in Address are set, then ASSERT().
+
+  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+  @param  AndData    The value to AND with the PCI configuration register.
+  @param  OrData    The value to OR with the PCI configuration register.
+
+  @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciSegmentAndThenOr8 (
+  IN UINT64                    Address,
+  IN UINT8                     AndData,
+  IN UINT8                     OrData
+  );
+
+/**
+  Reads a bit field of a PCI configuration register, and saves the value in the
+  S3 script to be replayed on S3 resume.
+
+  Reads the bit field in an 8-bit PCI configuration register. The bit field is
+  specified by the StartBit and the EndBit. The value of the bit field is
+  returned.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If StartBit is greater than 7, then ASSERT().
+  If EndBit is greater than 7, then ASSERT().
+  If EndBit is less than StartBit, then ASSERT().
+
+  @param  Address   PCI configuration register to read.
+  @param  StartBit  The ordinal of the least significant bit in the bit field.
+                    Range 0..7.
+  @param  EndBit    The ordinal of the most significant bit in the bit field.
+                    Range 0..7.
+
+  @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciSegmentBitFieldRead8 (
+  IN UINT64                    Address,
+  IN UINTN                     StartBit,
+  IN UINTN                     EndBit
+  );
+
+/**
+  Writes a bit field to a PCI configuration register, and saves the value in
+  the S3 script to be replayed on S3 resume.
+
+  Writes Value to the bit field of the PCI configuration register. The bit
+  field is specified by the StartBit and the EndBit. All other bits in the
+  destination PCI configuration register are preserved. The new value of the
+  8-bit register is returned.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If StartBit is greater than 7, then ASSERT().
+  If EndBit is greater than 7, then ASSERT().
+  If EndBit is less than StartBit, then ASSERT().
+  If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+  @param  Address   PCI configuration register to write.
+  @param  StartBit  The ordinal of the least significant bit in the bit field.
+                    Range 0..7.
+  @param  EndBit    The ordinal of the most significant bit in the bit field.
+                    Range 0..7.
+  @param  Value     New value of the bit field.
+
+  @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciSegmentBitFieldWrite8 (
+  IN UINT64                    Address,
+  IN UINTN                     StartBit,
+  IN UINTN                     EndBit,
+  IN UINT8                     Value
+  );
+
+/**
+  Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, writes
+  the result back to the bit field in the 8-bit port, and saves the value in the
+  S3 script to be replayed on S3 resume.
+
+  Reads the 8-bit PCI configuration register specified by Address, performs a
+  bitwise OR between the read result and the value specified by
+  OrData, and writes the result to the 8-bit PCI configuration register
+  specified by Address. The value written to the PCI configuration register is
+  returned. This function must guarantee that all PCI read and write operations
+  are serialized. Extra left bits in OrData are stripped.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If StartBit is greater than 7, then ASSERT().
+  If EndBit is greater than 7, then ASSERT().
+  If EndBit is less than StartBit, then ASSERT().
+  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+  @param  Address   PCI configuration register to write.
+  @param  StartBit  The ordinal of the least significant bit in the bit field.
+                    Range 0..7.
+  @param  EndBit    The ordinal of the most significant bit in the bit field.
+                    Range 0..7.
+  @param  OrData    The value to OR with the PCI configuration register.
+
+  @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciSegmentBitFieldOr8 (
+  IN UINT64                    Address,
+  IN UINTN                     StartBit,
+  IN UINTN                     EndBit,
+  IN UINT8                     OrData
+  );
+
+/**
+  Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
+  AND, writes the result back to the bit field in the 8-bit register, and
+  saves the value in the S3 script to be replayed on S3 resume.
+
+  Reads the 8-bit PCI configuration register specified by Address, performs a
+  bitwise AND between the read result and the value specified by AndData, and
+  writes the result to the 8-bit PCI configuration register specified by
+  Address. The value written to the PCI configuration register is returned.
+  This function must guarantee that all PCI read and write operations are
+  serialized. Extra left bits in AndData are stripped.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If StartBit is greater than 7, then ASSERT().
+  If EndBit is greater than 7, then ASSERT().
+  If EndBit is less than StartBit, then ASSERT().
+  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+  @param  Address   PCI configuration register to write.
+  @param  StartBit  The ordinal of the least significant bit in the bit field.
+                    Range 0..7.
+  @param  EndBit    The ordinal of the most significant bit in the bit field.
+                    Range 0..7.
+  @param  AndData   The value to AND with the PCI configuration register.
+
+  @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciSegmentBitFieldAnd8 (
+  IN UINT64                    Address,
+  IN UINTN                     StartBit,
+  IN UINTN                     EndBit,
+  IN UINT8                     AndData
+  );
+
+/**
+  Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
+  bitwise OR, writes the result back to the bit field in the 8-bit port,
+  and saves the value in the S3 script to be replayed on S3 resume.
+
+  Reads the 8-bit PCI configuration register specified by Address, performs a
+  bitwise AND followed by a bitwise OR between the read result and
+  the value specified by AndData, and writes the result to the 8-bit PCI
+  configuration register specified by Address. The value written to the PCI
+  configuration register is returned. This function must guarantee that all PCI
+  read and write operations are serialized. Extra left bits in both AndData and
+  OrData are stripped.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If StartBit is greater than 7, then ASSERT().
+  If EndBit is greater than 7, then ASSERT().
+  If EndBit is less than StartBit, then ASSERT().
+  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+  @param  Address   PCI configuration register to write.
+  @param  StartBit  The ordinal of the least significant bit in the bit field.
+                    Range 0..7.
+  @param  EndBit    The ordinal of the most significant bit in the bit field.
+                    Range 0..7.
+  @param  AndData   The value to AND with the PCI configuration register.
+  @param  OrData    The value to OR with the result of the AND operation.
+
+  @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+S3PciSegmentBitFieldAndThenOr8 (
+  IN UINT64                    Address,
+  IN UINTN                     StartBit,
+  IN UINTN                     EndBit,
+  IN UINT8                     AndData,
+  IN UINT8                     OrData
+  );
+
+/**
+  Reads a 16-bit PCI configuration register, and saves the value in the S3 script
+  to be replayed on S3 resume.
+
+  Reads and returns the 16-bit PCI configuration register specified by Address.
+  This function must guarantee that all PCI read and write operations are serialized.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+
+  @return The 16-bit PCI configuration register specified by Address.
+
+**/
+UINT16
+EFIAPI
+S3PciSegmentRead16 (
+  IN UINT64                    Address
+  );
+
+/**
+  Writes a 16-bit PCI configuration register, and saves the value in the S3 script to
+  be replayed on S3 resume.
+
+  Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.
+  Value is returned.  This function must guarantee that all PCI read and write operations are serialized.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+  @param  Address     Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+  @param  Value       The value to write.
+
+  @return The parameter of Value.
+
+**/
+UINT16
+EFIAPI
+S3PciSegmentWrite16 (
+  IN UINT64                    Address,
+  IN UINT16                    Value
+  );
+
+/**
+  Performs a bitwise OR of a 16-bit PCI configuration register with a 16-bit
+  value, and saves the value in the S3 script to be replayed on S3 resume.
+
+  Reads the 16-bit PCI configuration register specified by Address, performs a
+  bitwise OR between the read result and the value specified by OrData, and
+  writes the result to the 16-bit PCI configuration register specified by Address.
+  The value written to the PCI configuration register is returned. This function
+  must guarantee that all PCI read and write operations are serialized.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+  @param  Address Address that encodes the PCI Segment, Bus, Device, Function and
+                  Register.
+  @param  OrData  The value to OR with the PCI configuration register.
+
+  @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+S3PciSegmentOr16 (
+  IN UINT64                    Address,
+  IN UINT16                    OrData
+  );
+
+/**
+  Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value, and
+  saves the value in the S3 script to be replayed on S3 resume.
+
+  Reads the 16-bit PCI configuration register specified by Address,
+  performs a bitwise AND between the read result and the value specified by AndData,
+  and writes the result to the 16-bit PCI configuration register specified by Address.
+  The value written to the PCI configuration register is returned.
+  This function must guarantee that all PCI read and write operations are serialized.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+  @param  AndData   The value to AND with the PCI configuration register.
+
+  @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+S3PciSegmentAnd16 (
+  IN UINT64                    Address,
+  IN UINT16                    AndData
+  );
+
+/**
+  Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,
+  followed a bitwise OR with another 16-bit value, and saves the value in the S3 script to
+  be replayed on S3 resume.
+
+  Reads the 16-bit PCI configuration register specified by Address,
+  performs a bitwise AND between the read result and the value specified by AndData,
+  performs a bitwise OR between the result of the AND operation and the value specified by OrData,
+  and writes the result to the 16-bit PCI configuration register specified by Address.
+  The value written to the PCI configuration register is returned.
+  This function must guarantee that all PCI read and write operations are serialized.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+  @param  AndData   The value to AND with the PCI configuration register.
+  @param  OrData    The value to OR with the PCI configuration register.
+
+  @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+S3PciSegmentAndThenOr16 (
+  IN UINT64                    Address,
+  IN UINT16                    AndData,
+  IN UINT16                    OrData
+  );
+
+/**
+  Reads a bit field of a PCI configuration register, and saves the value in the
+  S3 script to be replayed on S3 resume.
+
+  Reads the bit field in a 16-bit PCI configuration register. The bit field is
+  specified by the StartBit and the EndBit. The value of the bit field is
+  returned.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If Address is not aligned on a 16-bit boundary, then ASSERT().
+  If StartBit is greater than 15, then ASSERT().
+  If EndBit is greater than 15, then ASSERT().
+  If EndBit is less than StartBit, then ASSERT().
+
+  @param  Address   PCI configuration register to read.
+  @param  StartBit  The ordinal of the least significant bit in the bit field.
+                    Range 0..15.
+  @param  EndBit    The ordinal of the most significant bit in the bit field.
+                    Range 0..15.
+
+  @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+S3PciSegmentBitFieldRead16 (
+  IN UINT64                    Address,
+  IN UINTN                     StartBit,
+  IN UINTN                     EndBit
+  );
+
+/**
+  Writes a bit field to a PCI configuration register, and saves the value in
+  the S3 script to be replayed on S3 resume.
+
+  Writes Value to the bit field of the PCI configuration register. The bit
+  field is specified by the StartBit and the EndBit. All other bits in the
+  destination PCI configuration register are preserved. The new value of the
+  16-bit register is returned.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If Address is not aligned on a 16-bit boundary, then ASSERT().
+  If StartBit is greater than 15, then ASSERT().
+  If EndBit is greater than 15, then ASSERT().
+  If EndBit is less than StartBit, then ASSERT().
+  If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+  @param  Address   PCI configuration register to write.
+  @param  StartBit  The ordinal of the least significant bit in the bit field.
+                    Range 0..15.
+  @param  EndBit    The ordinal of the most significant bit in the bit field.
+                    Range 0..15.
+  @param  Value     New value of the bit field.
+
+  @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+S3PciSegmentBitFieldWrite16 (
+  IN UINT64                    Address,
+  IN UINTN                     StartBit,
+  IN UINTN                     EndBit,
+  IN UINT16                    Value
+  );
+
+/**
+  Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, writes
+  the result back to the bit field in the 16-bit port, and saves the value in the
+  S3 script to be replayed on S3 resume.
+
+  Reads the 16-bit PCI configuration register specified by Address, performs a
+  bitwise OR between the read result and the value specified by
+  OrData, and writes the result to the 16-bit PCI configuration register
+  specified by Address. The value written to the PCI configuration register is
+  returned. This function must guarantee that all PCI read and write operations
+  are serialized. Extra left bits in OrData are stripped.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If Address is not aligned on a 16-bit boundary, then ASSERT().
+  If StartBit is greater than 15, then ASSERT().
+  If EndBit is greater than 15, then ASSERT().
+  If EndBit is less than StartBit, then ASSERT().
+  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+  @param  Address   PCI configuration register to write.
+  @param  StartBit  The ordinal of the least significant bit in the bit field.
+                    Range 0..15.
+  @param  EndBit    The ordinal of the most significant bit in the bit field.
+                    Range 0..15.
+  @param  OrData    The value to OR with the PCI configuration register.
+
+  @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+S3PciSegmentBitFieldOr16 (
+  IN UINT64                    Address,
+  IN UINTN                     StartBit,
+  IN UINTN                     EndBit,
+  IN UINT16                    OrData
+  );
+
+/**
+  Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
+  AND, writes the result back to the bit field in the 16-bit register, and
+  saves the value in the S3 script to be replayed on S3 resume.
+
+  Reads the 16-bit PCI configuration register specified by Address, performs a
+  bitwise AND between the read result and the value specified by AndData, and
+  writes the result to the 16-bit PCI configuration register specified by
+  Address. The value written to the PCI configuration register is returned.
+  This function must guarantee that all PCI read and write operations are
+  serialized. Extra left bits in AndData are stripped.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If Address is not aligned on a 16-bit boundary, then ASSERT().
+  If StartBit is greater than 15, then ASSERT().
+  If EndBit is greater than 15, then ASSERT().
+  If EndBit is less than StartBit, then ASSERT().
+  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+  @param  StartBit  The ordinal of the least significant bit in the bit field.
+                    Range 0..15.
+  @param  EndBit    The ordinal of the most significant bit in the bit field.
+                    Range 0..15.
+  @param  AndData   The value to AND with the PCI configuration register.
+
+  @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+S3PciSegmentBitFieldAnd16 (
+  IN UINT64                    Address,
+  IN UINTN                     StartBit,
+  IN UINTN                     EndBit,
+  IN UINT16                    AndData
+  );
+
+/**
+  Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
+  bitwise OR, writes the result back to the bit field in the 16-bit port,
+  and saves the value in the S3 script to be replayed on S3 resume.
+
+  Reads the 16-bit PCI configuration register specified by Address, performs a
+  bitwise AND followed by a bitwise OR between the read result and
+  the value specified by AndData, and writes the result to the 16-bit PCI
+  configuration register specified by Address. The value written to the PCI
+  configuration register is returned. This function must guarantee that all PCI
+  read and write operations are serialized. Extra left bits in both AndData and
+  OrData are stripped.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If StartBit is greater than 15, then ASSERT().
+  If EndBit is greater than 15, then ASSERT().
+  If EndBit is less than StartBit, then ASSERT().
+  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+  @param  Address   PCI configuration register to write.
+  @param  StartBit  The ordinal of the least significant bit in the bit field.
+                    Range 0..15.
+  @param  EndBit    The ordinal of the most significant bit in the bit field.
+                    Range 0..15.
+  @param  AndData   The value to AND with the PCI configuration register.
+  @param  OrData    The value to OR with the result of the AND operation.
+
+  @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+S3PciSegmentBitFieldAndThenOr16 (
+  IN UINT64                    Address,
+  IN UINTN                     StartBit,
+  IN UINTN                     EndBit,
+  IN UINT16                    AndData,
+  IN UINT16                    OrData
+  );
+
+/**
+  Reads a 32-bit PCI configuration register, and saves the value in the S3 script
+  to be replayed on S3 resume.
+
+  Reads and returns the 32-bit PCI configuration register specified by Address.
+  This function must guarantee that all PCI read and write operations are serialized.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+
+  @return The 32-bit PCI configuration register specified by Address.
+
+**/
+UINT32
+EFIAPI
+S3PciSegmentRead32 (
+  IN UINT64                    Address
+  );
+
+/**
+  Writes a 32-bit PCI configuration register, and saves the value in the S3 script to
+  be replayed on S3 resume.
+
+  Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.
+  Value is returned.  This function must guarantee that all PCI read and write operations are serialized.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+  @param  Address     Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+  @param  Value       The value to write.
+
+  @return The parameter of Value.
+
+**/
+UINT32
+EFIAPI
+S3PciSegmentWrite32 (
+  IN UINT64                    Address,
+  IN UINT32                    Value
+  );
+
+/**
+  Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit
+  value, and saves the value in the S3 script to be replayed on S3 resume.
+
+  Reads the 32-bit PCI configuration register specified by Address, performs a
+  bitwise OR between the read result and the value specified by OrData, and
+  writes the result to the 32-bit PCI configuration register specified by Address.
+  The value written to the PCI configuration register is returned. This function
+  must guarantee that all PCI read and write operations are serialized.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and
+                    Register.
+  @param  OrData    The value to OR with the PCI configuration register.
+
+  @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+S3PciSegmentOr32 (
+  IN UINT64                    Address,
+  IN UINT32                    OrData
+  );
+
+/**
+  Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value, and
+  saves the value in the S3 script to be replayed on S3 resume.
+
+  Reads the 32-bit PCI configuration register specified by Address,
+  performs a bitwise AND between the read result and the value specified by AndData,
+  and writes the result to the 32-bit PCI configuration register specified by Address.
+  The value written to the PCI configuration register is returned.
+  This function must guarantee that all PCI read and write operations are serialized.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+  @param  AndData   The value to AND with the PCI configuration register.
+
+  @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+S3PciSegmentAnd32 (
+  IN UINT64                    Address,
+  IN UINT32                    AndData
+  );
+
+/**
+  Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,
+  followed a bitwise OR with another 32-bit value, and saves the value in the S3 script to
+  be replayed on S3 resume.
+
+  Reads the 32-bit PCI configuration register specified by Address,
+  performs a bitwise AND between the read result and the value specified by AndData,
+  performs a bitwise OR between the result of the AND operation and the value specified by OrData,
+  and writes the result to the 32-bit PCI configuration register specified by Address.
+  The value written to the PCI configuration register is returned.
+  This function must guarantee that all PCI read and write operations are serialized.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+  @param  AndData   The value to AND with the PCI configuration register.
+  @param  OrData    The value to OR with the PCI configuration register.
+
+  @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+S3PciSegmentAndThenOr32 (
+  IN UINT64                    Address,
+  IN UINT32                    AndData,
+  IN UINT32                    OrData
+  );
+
+/**
+  Reads a bit field of a PCI configuration register, and saves the value in the
+  S3 script to be replayed on S3 resume.
+
+  Reads the bit field in a 32-bit PCI configuration register. The bit field is
+  specified by the StartBit and the EndBit. The value of the bit field is
+  returned.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If Address is not aligned on a 32-bit boundary, then ASSERT().
+  If StartBit is greater than 31, then ASSERT().
+  If EndBit is greater than 31, then ASSERT().
+  If EndBit is less than StartBit, then ASSERT().
+
+  @param  Address   PCI configuration register to read.
+  @param  StartBit  The ordinal of the least significant bit in the bit field.
+                    Range 0..31.
+  @param  EndBit    The ordinal of the most significant bit in the bit field.
+                    Range 0..31.
+
+  @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+S3PciSegmentBitFieldRead32 (
+  IN UINT64                    Address,
+  IN UINTN                     StartBit,
+  IN UINTN                     EndBit
+  );
+
+/**
+  Writes a bit field to a PCI configuration register, and saves the value in
+  the S3 script to be replayed on S3 resume.
+
+  Writes Value to the bit field of the PCI configuration register. The bit
+  field is specified by the StartBit and the EndBit. All other bits in the
+  destination PCI configuration register are preserved. The new value of the
+  32-bit register is returned.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If Address is not aligned on a 32-bit boundary, then ASSERT().
+  If StartBit is greater than 31, then ASSERT().
+  If EndBit is greater than 31, then ASSERT().
+  If EndBit is less than StartBit, then ASSERT().
+  If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+  @param  Address   PCI configuration register to write.
+  @param  StartBit  The ordinal of the least significant bit in the bit field.
+                    Range 0..31.
+  @param  EndBit    The ordinal of the most significant bit in the bit field.
+                    Range 0..31.
+  @param  Value     New value of the bit field.
+
+  @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+S3PciSegmentBitFieldWrite32 (
+  IN UINT64                    Address,
+  IN UINTN                     StartBit,
+  IN UINTN                     EndBit,
+  IN UINT32                    Value
+  );
+
+/**
+  Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, writes
+  the result back to the bit field in the 32-bit port, and saves the value in the
+  S3 script to be replayed on S3 resume.
+
+  Reads the 32-bit PCI configuration register specified by Address, performs a
+  bitwise OR between the read result and the value specified by
+  OrData, and writes the result to the 32-bit PCI configuration register
+  specified by Address. The value written to the PCI configuration register is
+  returned. This function must guarantee that all PCI read and write operations
+  are serialized. Extra left bits in OrData are stripped.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If Address is not aligned on a 32-bit boundary, then ASSERT().
+  If StartBit is greater than 31, then ASSERT().
+  If EndBit is greater than 31, then ASSERT().
+  If EndBit is less than StartBit, then ASSERT().
+  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+  @param  Address   PCI configuration register to write.
+  @param  StartBit  The ordinal of the least significant bit in the bit field.
+                    Range 0..31.
+  @param  EndBit    The ordinal of the most significant bit in the bit field.
+                    Range 0..31.
+  @param  OrData    The value to OR with the PCI configuration register.
+
+  @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+S3PciSegmentBitFieldOr32 (
+  IN UINT64                    Address,
+  IN UINTN                     StartBit,
+  IN UINTN                     EndBit,
+  IN UINT32                    OrData
+  );
+
+/**
+  Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
+  AND, and writes the result back to the bit field in the 32-bit register, and
+  saves the value in the S3 script to be replayed on S3 resume.
+
+  Reads the 32-bit PCI configuration register specified by Address, performs a
+  bitwise AND between the read result and the value specified by AndData, and
+  writes the result to the 32-bit PCI configuration register specified by
+  Address. The value written to the PCI configuration register is returned.
+  This function must guarantee that all PCI read and write operations are
+  serialized. Extra left bits in AndData are stripped.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If Address is not aligned on a 32-bit boundary, then ASSERT().
+  If StartBit is greater than 31, then ASSERT().
+  If EndBit is greater than 31, then ASSERT().
+  If EndBit is less than StartBit, then ASSERT().
+  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
+  @param  StartBit  The ordinal of the least significant bit in the bit field.
+                    Range 0..31.
+  @param  EndBit    The ordinal of the most significant bit in the bit field.
+                    Range 0..31.
+  @param  AndData   The value to AND with the PCI configuration register.
+
+  @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+S3PciSegmentBitFieldAnd32 (
+  IN UINT64                    Address,
+  IN UINTN                     StartBit,
+  IN UINTN                     EndBit,
+  IN UINT32                    AndData
+  );
+
+/**
+  Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
+  bitwise OR, writes the result back to the bit field in the 32-bit port,
+  and saves the value in the S3 script to be replayed on S3 resume.
+
+  Reads the 32-bit PCI configuration register specified by Address, performs a
+  bitwise AND followed by a bitwise OR between the read result and
+  the value specified by AndData, and writes the result to the 32-bit PCI
+  configuration register specified by Address. The value written to the PCI
+  configuration register is returned. This function must guarantee that all PCI
+  read and write operations are serialized. Extra left bits in both AndData and
+  OrData are stripped.
+
+  If any reserved bits in Address are set, then ASSERT().
+  If StartBit is greater than 31, then ASSERT().
+  If EndBit is greater than 31, then ASSERT().
+  If EndBit is less than StartBit, then ASSERT().
+  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
+
+  @param  Address   PCI configuration register to write.
+  @param  StartBit  The ordinal of the least significant bit in the bit field.
+                    Range 0..31.
+  @param  EndBit    The ordinal of the most significant bit in the bit field.
+                    Range 0..31.
+  @param  AndData   The value to AND with the PCI configuration register.
+  @param  OrData    The value to OR with the result of the AND operation.
+
+  @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+S3PciSegmentBitFieldAndThenOr32 (
+  IN UINT64                    Address,
+  IN UINTN                     StartBit,
+  IN UINTN                     EndBit,
+  IN UINT32                    AndData,
+  IN UINT32                    OrData
+  );
+
+/**
+  Reads a range of PCI configuration registers into a caller supplied buffer,
+  and saves the value in the S3 script to be replayed on S3 resume.
+
+  Reads the range of PCI configuration registers specified by StartAddress and
+  Size into the buffer specified by Buffer. This function only allows the PCI
+  configuration registers from a single PCI function to be read. Size is
+  returned. When possible 32-bit PCI configuration read cycles are used to read
+  from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
+  and 16-bit PCI configuration read cycles may be used at the beginning and the
+  end of the range.
+
+  If any reserved bits in StartAddress are set, then ASSERT().
+  If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+  If Size > 0 and Buffer is NULL, then ASSERT().
+
+  @param  StartAddress  Starting address that encodes the PCI Segment, Bus, Device,
+                        Function and Register.
+  @param  Size          Size in bytes of the transfer.
+  @param  Buffer        Pointer to a buffer receiving the data read.
+
+  @return Size
+
+**/
+UINTN
+EFIAPI
+S3PciSegmentReadBuffer (
+  IN  UINT64                   StartAddress,
+  IN  UINTN                    Size,
+  OUT VOID                     *Buffer
+  );
+
+/**
+  Copies the data in a caller supplied buffer to a specified range of PCI
+  configuration space, and saves the value in the S3 script to be replayed on S3
+  resume.
+
+  Writes the range of PCI configuration registers specified by StartAddress and
+  Size from the buffer specified by Buffer. This function only allows the PCI
+  configuration registers from a single PCI function to be written. Size is
+  returned. When possible 32-bit PCI configuration write cycles are used to
+  write from StartAdress to StartAddress + Size. Due to alignment restrictions,
+  8-bit and 16-bit PCI configuration write cycles may be used at the beginning
+  and the end of the range.
+
+  If any reserved bits in StartAddress are set, then ASSERT().
+  If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+  If Size > 0 and Buffer is NULL, then ASSERT().
+
+  @param  StartAddress  Starting address that encodes the PCI Segment, Bus, Device,
+                        Function and Register.
+  @param  Size          Size in bytes of the transfer.
+  @param  Buffer        Pointer to a buffer containing the data to write.
+
+  @return The parameter of Size.
+
+**/
+UINTN
+EFIAPI
+S3PciSegmentWriteBuffer (
+  IN UINT64                    StartAddress,
+  IN UINTN                     Size,
+  IN VOID                      *Buffer
+  );
+
+#endif
diff --git a/MdePkg/Include/Library/S3SmbusLib.h b/MdePkg/Include/Library/S3SmbusLib.h
index 2f24378d2d58..471725641e41 100644
--- a/MdePkg/Include/Library/S3SmbusLib.h
+++ b/MdePkg/Include/Library/S3SmbusLib.h
@@ -3,16 +3,9 @@
   to be replayed during an S3 resume. This library class maps directly on top
   of the SmbusLib class.
 
-  Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
 
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions
-  of the BSD License which accompanies this distribution.  The
-  full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -35,13 +28,13 @@
                              SMBUS Command, SMBUS Data Length, and PEC.
   @param[out] Status         The return status for the executed command.
                              This is an optional parameter and may be NULL.
-                             RETURN_SUCCESS  		 The SMBUS command was executed.
-                             RETURN_TIMEOUT  		 A timeout occurred while executing the SMBUS command.
+                             RETURN_SUCCESS       The SMBUS command was executed.
+                             RETURN_TIMEOUT       A timeout occurred while executing the SMBUS command.
                              RETURN_DEVICE_ERROR The request was not completed because a failure
                               was recorded in the Host Status Register bit.  Device errors are a result
                               of a transaction collision, illegal command field, unclaimed cycle
                               (host initiated), or bus error (collision).
-                             RETURN_UNSUPPORTED  	The SMBus operation is not supported.
+                             RETURN_UNSUPPORTED    The SMBus operation is not supported.
 
 **/
 VOID
@@ -67,13 +60,13 @@ S3SmBusQuickRead (
                              SMBUS Command, SMBUS Data Length, and PEC.
   @param[out] Status         The return status for the executed command.
                              This is an optional parameter and may be NULL.
-                             RETURN_SUCCESS  		The SMBUS command was executed.
-                             RETURN_TIMEOUT  		A timeout occurred while executing the SMBUS command.
+                             RETURN_SUCCESS      The SMBUS command was executed.
+                             RETURN_TIMEOUT      A timeout occurred while executing the SMBUS command.
                              RETURN_DEVICE_ERROR The request was not completed because a failure
                              was recorded in the Host Status Register bit.  Device errors are a result
                              of a transaction collision, illegal command field, unclaimed cycle
                              (host initiated), or bus error (collision).
-                             RETURN_UNSUPPORTED  	The SMBus operation is not supported.
+                             RETURN_UNSUPPORTED    The SMBus operation is not supported.
 
 **/
 VOID
@@ -99,14 +92,14 @@ S3SmBusQuickWrite (
                              SMBUS Command, SMBUS Data Length, and PEC.
   @param[out] Status         The return status for the executed command.
                              This is an optional parameter and may be NULL.
-                             RETURN_SUCCESS  		The SMBUS command was executed.
-                             RETURN_TIMEOUT  		A timeout occurred while executing the SMBUS command.
+                             RETURN_SUCCESS      The SMBUS command was executed.
+                             RETURN_TIMEOUT      A timeout occurred while executing the SMBUS command.
                              RETURN_DEVICE_ERROR The request was not completed because a failure
                              was recorded in the Host Status Register bit.  Device errors are a result
                              of a transaction collision, illegal command field, unclaimed cycle
                              (host initiated), or bus error (collision).
                              RETURN_CRC_ERROR  The checksum is not correct (PEC is incorrect).
-                             RETURN_UNSUPPORTED  	The SMBus operation is not supported.
+                             RETURN_UNSUPPORTED    The SMBus operation is not supported.
 
   @return   The byte received from the SMBUS.
 
diff --git a/MdePkg/Include/Library/S3StallLib.h b/MdePkg/Include/Library/S3StallLib.h
index e723d18bda01..aab86679dc8b 100644
--- a/MdePkg/Include/Library/S3StallLib.h
+++ b/MdePkg/Include/Library/S3StallLib.h
@@ -1,18 +1,11 @@
 /** @file
   Stall Services that perform stalls and also enable the Stall operatation
   to be replayed during an S3 resume. This library class maps directly on top
-  of the Timer class. 
+  of the Timer class.
 
-  Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
 
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions
-  of the BSD License which accompanies this distribution.  The
-  full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/Library/SafeIntLib.h b/MdePkg/Include/Library/SafeIntLib.h
new file mode 100644
index 000000000000..e2f376f79f6f
--- /dev/null
+++ b/MdePkg/Include/Library/SafeIntLib.h
@@ -0,0 +1,3013 @@
+/** @file
+  This library provides helper functions to prevent integer overflow during
+  type conversion, addition, subtraction, and multiplication.
+
+  Copyright (c) 2017, Microsoft Corporation
+
+  All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef __INT_SAFE_LIB_H__
+#define __INT_SAFE_LIB_H__
+
+//
+// It is common for -1 to be used as an error value
+//
+#define INT8_ERROR    ((INT8) -1)
+#define UINT8_ERROR   MAX_UINT8
+#define CHAR8_ERROR   ((CHAR8)(MAX_INT8))
+#define INT16_ERROR   ((INT16) -1)
+#define UINT16_ERROR  MAX_UINT16
+#define CHAR16_ERROR  MAX_UINT16
+#define INT32_ERROR   ((INT32) -1)
+#define UINT32_ERROR  MAX_UINT32
+#define INT64_ERROR   ((INT64) -1)
+#define UINT64_ERROR  MAX_UINT64
+#define INTN_ERROR    ((INTN) -1)
+#define UINTN_ERROR   MAX_UINTN
+
+//
+// CHAR16 is defined to be the same as UINT16, so for CHAR16
+// operations redirect to the UINT16 ones:
+//
+#define SafeInt8ToChar16    SafeInt8ToUint16
+#define SafeInt16ToChar16   SafeInt16ToUint16
+#define SafeInt32ToChar16   SafeInt32ToUint16
+#define SafeUint32ToChar16  SafeUint32ToUint16
+#define SafeInt64ToChar16   SafeInt64ToUint16
+#define SafeUint64ToChar16  SafeUint64ToUint16
+#define SafeIntnToChar16    SafeIntnToUint16
+#define SafeUintnToChar16   SafeUintnToUint16
+
+#define SafeChar16ToInt8    SafeUint16ToInt8
+#define SafeChar16ToUint8   SafeUint16ToUint8
+#define SafeChar16ToChar8   SafeUint16ToChar8
+#define SafeChar16ToInt16   SafeUint16ToInt16
+
+#define SafeChar16Mult      SafeUint16Mult
+#define SafeChar16Sub       SafeUint16Sub
+#define SafeChar16Add       SafeUint16Add
+
+//
+// Conversion functions
+//
+// There are three reasons for having conversion functions:
+//
+// 1. We are converting from a signed type to an unsigned type of the same
+//    size, or vice-versa.
+//
+// 2. We are converting to a smaller type, and we could therefore possibly
+//    overflow.
+//
+// 3. We are converting to a bigger type, and we are signed and the type we are
+//    converting to is unsigned.
+//
+
+/**
+  INT8 -> UINT8 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to UINT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt8ToUint8 (
+  IN  INT8   Operand,
+  OUT UINT8  *Result
+  );
+
+/**
+  INT8 -> CHAR8 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to CHAR8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt8ToChar8 (
+  IN  INT8   Operand,
+  OUT CHAR8  *Result
+  );
+
+/**
+  INT8 -> UINT16 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to UINT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt8ToUint16 (
+  IN  INT8    Operand,
+  OUT UINT16  *Result
+  );
+
+/**
+  INT8 -> UINT32 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to UINT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt8ToUint32 (
+  IN  INT8    Operand,
+  OUT UINT32  *Result
+  );
+
+/**
+  INT8 -> UINTN conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to UINTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt8ToUintn (
+  IN  INT8   Operand,
+  OUT UINTN  *Result
+  );
+
+/**
+  INT8 -> UINT64 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to UINT64_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt8ToUint64 (
+  IN  INT8    Operand,
+  OUT UINT64  *Result
+  );
+
+/**
+  UINT8 -> INT8 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to INT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint8ToInt8 (
+  IN  UINT8  Operand,
+  OUT INT8   *Result
+  );
+
+/**
+  UINT8 -> CHAR8 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to CHAR8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint8ToChar8 (
+  IN  UINT8  Operand,
+  OUT CHAR8  *Result
+  );
+
+/**
+  INT16 -> INT8 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to INT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt16ToInt8 (
+  IN  INT16  Operand,
+  OUT INT8   *Result
+  );
+
+/**
+  INT16 -> CHAR8 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to CHAR8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt16ToChar8 (
+  IN  INT16  Operand,
+  OUT CHAR8  *Result
+  );
+
+/**
+  INT16 -> UINT8 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to UINT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt16ToUint8 (
+  IN INT16 Operand,
+  OUT UINT8 *Result
+  );
+
+/**
+  INT16 -> UINT16 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to UINT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt16ToUint16 (
+  IN  INT16   Operand,
+  OUT UINT16  *Result
+  );
+
+/**
+  INT16 -> UINT32 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to UINT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt16ToUint32 (
+  IN  INT16   Operand,
+  OUT UINT32  *Result
+  );
+
+/**
+  INT16 -> UINTN conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to UINTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt16ToUintn (
+  IN  INT16  Operand,
+  OUT UINTN  *Result
+  );
+
+/**
+  INT16 -> UINT64 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to UINT64_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt16ToUint64 (
+  IN  INT16   Operand,
+  OUT UINT64  *Result
+  );
+
+/**
+  UINT16 -> INT8 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to INT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint16ToInt8 (
+  IN  UINT16  Operand,
+  OUT INT8    *Result
+  );
+
+/**
+  UINT16 -> CHAR8 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to CHAR8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint16ToChar8 (
+  IN  UINT16  Operand,
+  OUT CHAR8   *Result
+  );
+
+/**
+  UINT16 -> UINT8 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to UINT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint16ToUint8 (
+  IN UINT16 Operand,
+  OUT UINT8 *Result
+  );
+
+/**
+  UINT16 -> INT16 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to INT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint16ToInt16 (
+  IN  UINT16  Operand,
+  OUT INT16   *Result
+  );
+
+/**
+  INT32 -> INT8 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to INT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt32ToInt8 (
+  IN  INT32  Operand,
+  OUT INT8   *Result
+  );
+
+/**
+  INT32 -> CHAR8 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to CHAR8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt32ToChar8 (
+  IN  INT32  Operand,
+  OUT CHAR8  *Result
+  );
+
+/**
+  INT32 -> UINT8 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to UINT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt32ToUint8 (
+  IN INT32 Operand,
+  OUT UINT8 *Result
+  );
+
+/**
+  INT32 -> INT16 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to INT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt32ToInt16 (
+  IN  INT32  Operand,
+  OUT INT16  *Result
+  );
+
+/**
+  INT32 -> UINT16 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to UINT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt32ToUint16 (
+  IN  INT32   Operand,
+  OUT UINT16  *Result
+  );
+
+
+/**
+  INT32 -> UINT32 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to UINT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt32ToUint32 (
+  IN  INT32   Operand,
+  OUT UINT32  *Result
+  );
+
+/**
+  INT32 -> UINTN conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to UINTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt32ToUintn (
+  IN  INT32  Operand,
+  OUT UINTN  *Result
+  );
+
+/**
+  INT32 -> UINT64 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to UINT64_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt32ToUint64 (
+  IN  INT32   Operand,
+  OUT UINT64  *Result
+  );
+
+/**
+  UINT32 -> INT8 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to INT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint32ToInt8 (
+  IN  UINT32  Operand,
+  OUT INT8    *Result
+  );
+
+/**
+  UINT32 -> CHAR8 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to CHAR8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint32ToChar8 (
+  IN  UINT32  Operand,
+  OUT CHAR8   *Result
+  );
+
+/**
+  UINT32 -> UINT8 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to UINT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint32ToUint8 (
+  IN UINT32 Operand,
+  OUT UINT8 *Result
+  );
+
+/**
+  UINT32 -> INT16 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to INT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint32ToInt16 (
+  IN  UINT32  Operand,
+  OUT INT16   *Result
+  );
+
+/**
+  UINT32 -> UINT16 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to UINT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint32ToUint16 (
+  IN  UINT32  Operand,
+  OUT UINT16  *Result
+  );
+
+/**
+  UINT32 -> INT32 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to INT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint32ToInt32 (
+  IN  UINT32  Operand,
+  OUT INT32   *Result
+  );
+
+/**
+  UINT32 -> INTN conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to INTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint32ToIntn (
+  IN  UINT32  Operand,
+  OUT INTN    *Result
+  );
+
+/**
+  INTN -> INT8 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to INT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeIntnToInt8 (
+  IN  INTN  Operand,
+  OUT INT8  *Result
+  );
+
+/**
+  INTN -> CHAR8 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to CHAR8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeIntnToChar8 (
+  IN  INTN   Operand,
+  OUT CHAR8  *Result
+  );
+
+/**
+  INTN -> UINT8 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to UINT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeIntnToUint8 (
+  IN INTN Operand,
+  OUT UINT8 *Result
+  );
+
+/**
+  INTN -> INT16 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to INT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeIntnToInt16 (
+  IN  INTN   Operand,
+  OUT INT16  *Result
+  );
+
+/**
+  INTN -> UINT16 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to UINT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeIntnToUint16 (
+  IN  INTN    Operand,
+  OUT UINT16  *Result
+  );
+
+/**
+  INTN -> INT32 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to INT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeIntnToInt32 (
+  IN  INTN   Operand,
+  OUT INT32  *Result
+  );
+
+/**
+  INTN -> UINT32 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to UINT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeIntnToUint32 (
+  IN  INTN    Operand,
+  OUT UINT32  *Result
+  );
+
+/**
+  INTN -> UINTN conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to UINTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeIntnToUintn (
+  IN  INTN   Operand,
+  OUT UINTN  *Result
+  );
+
+/**
+  INTN -> UINT64 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to UINT64_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeIntnToUint64 (
+  IN  INTN    Operand,
+  OUT UINT64  *Result
+  );
+
+/**
+  UINTN -> INT8 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to INT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUintnToInt8 (
+  IN  UINTN  Operand,
+  OUT INT8   *Result
+  );
+
+/**
+  UINTN -> CHAR8 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to CHAR8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUintnToChar8 (
+  IN  UINTN  Operand,
+  OUT CHAR8  *Result
+  );
+
+/**
+  UINTN -> UINT8 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to UINT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUintnToUint8 (
+  IN UINTN Operand,
+  OUT UINT8 *Result
+  );
+
+/**
+  UINTN -> INT16 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to INT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUintnToInt16 (
+  IN  UINTN  Operand,
+  OUT INT16  *Result
+  );
+
+/**
+  UINTN -> UINT16 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to UINT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUintnToUint16 (
+  IN  UINTN   Operand,
+  OUT UINT16  *Result
+  );
+
+/**
+  UINTN -> INT32 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to INT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUintnToInt32 (
+  IN  UINTN  Operand,
+  OUT INT32  *Result
+  );
+
+/**
+  UINTN -> UINT32 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to UINT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUintnToUint32 (
+  IN  UINTN   Operand,
+  OUT UINT32  *Result
+  );
+
+/**
+  UINTN -> INTN conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to INTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUintnToIntn (
+  IN  UINTN  Operand,
+  OUT INTN   *Result
+  );
+
+/**
+  UINTN -> INT64 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to INT64_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUintnToInt64 (
+  IN  UINTN  Operand,
+  OUT INT64  *Result
+  );
+
+/**
+  INT64 -> INT8 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to INT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt64ToInt8 (
+  IN  INT64  Operand,
+  OUT INT8   *Result
+  );
+
+/**
+  INT64 -> CHAR8 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to CHAR8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt64ToChar8 (
+  IN  INT64  Operand,
+  OUT CHAR8  *Result
+  );
+
+/**
+  INT64 -> UINT8 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to UINT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt64ToUint8 (
+  IN  INT64  Operand,
+  OUT UINT8  *Result
+  );
+
+/**
+  INT64 -> INT16 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to INT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt64ToInt16 (
+  IN  INT64  Operand,
+  OUT INT16  *Result
+  );
+
+/**
+  INT64 -> UINT16 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to UINT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt64ToUint16 (
+  IN  INT64   Operand,
+  OUT UINT16  *Result
+  );
+
+/**
+  INT64 -> INT32 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to INT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt64ToInt32 (
+  IN  INT64  Operand,
+  OUT INT32  *Result
+  );
+
+/**
+  INT64 -> UINT32 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to UINT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt64ToUint32 (
+  IN  INT64   Operand,
+  OUT UINT32  *Result
+  );
+
+/**
+  INT64 -> INTN conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to INTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt64ToIntn (
+  IN  INT64  Operand,
+  OUT INTN   *Result
+  );
+
+/**
+  INT64 -> UINTN conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to UINTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt64ToUintn (
+  IN  INT64  Operand,
+  OUT UINTN  *Result
+  );
+
+/**
+  INT64 -> UINT64 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to UINT64_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt64ToUint64 (
+  IN  INT64   Operand,
+  OUT UINT64  *Result
+  );
+
+/**
+  UINT64 -> INT8 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to INT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint64ToInt8 (
+  IN  UINT64  Operand,
+  OUT INT8    *Result
+  );
+
+/**
+  UINT64 -> CHAR8 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to CHAR8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint64ToChar8 (
+  IN  UINT64  Operand,
+  OUT CHAR8   *Result
+  );
+
+/**
+  UINT64 -> UINT8 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to UINT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint64ToUint8 (
+  IN  UINT64  Operand,
+  OUT UINT8   *Result
+  );
+
+/**
+  UINT64 -> INT16 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to INT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint64ToInt16 (
+  IN  UINT64  Operand,
+  OUT INT16   *Result
+  );
+
+/**
+  UINT64 -> UINT16 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to UINT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint64ToUint16 (
+  IN  UINT64  Operand,
+  OUT UINT16  *Result
+  );
+
+/**
+  UINT64 -> INT32 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to INT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint64ToInt32 (
+  IN  UINT64  Operand,
+  OUT INT32   *Result
+  );
+
+/**
+  UINT64 -> UINT32 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to UINT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint64ToUint32 (
+  IN  UINT64  Operand,
+  OUT UINT32  *Result
+  );
+
+/**
+  UINT64 -> INTN conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to INTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint64ToIntn (
+  IN  UINT64  Operand,
+  OUT INTN    *Result
+  );
+
+/**
+  UINT64 -> UINTN conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to UINTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint64ToUintn (
+  IN  UINT64  Operand,
+  OUT UINTN   *Result
+  );
+
+/**
+  UINT64 -> INT64 conversion
+
+  Converts the value specified by Operand to a value specified by Result type
+  and stores the converted value into the caller allocated output buffer
+  specified by Result.  The caller must pass in a Result buffer that is at
+  least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the conversion results in an overflow or an underflow condition, then
+  Result is set to INT64_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Operand  Operand to be converted to new type
+  @param[out]  Result   Pointer to the result of conversion
+
+  @retval  RETURN_SUCCESS            Successful conversion
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint64ToInt64 (
+  IN  UINT64  Operand,
+  OUT INT64   *Result
+  );
+
+//
+// Addition functions
+//
+
+/**
+  UINT8 addition
+
+  Performs the requested operation using the input parameters into a value
+  specified by Result type and stores the converted value into the caller
+  allocated output buffer specified by Result.  The caller must pass in a
+  Result buffer that is at least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the requested operation results in an overflow or an underflow condition,
+  then Result is set to UINT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Augend  A number to which addend will be added
+  @param[in]   Addend  A number to be added to another
+  @param[out]  Result  Pointer to the result of addition
+
+  @retval  RETURN_SUCCESS            Successful addition
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint8Add (
+  IN  UINT8  Augend,
+  IN  UINT8  Addend,
+  OUT UINT8  *Result
+  );
+
+/**
+  UINT16 addition
+
+  Performs the requested operation using the input parameters into a value
+  specified by Result type and stores the converted value into the caller
+  allocated output buffer specified by Result.  The caller must pass in a
+  Result buffer that is at least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the requested operation results in an overflow or an underflow condition,
+  then Result is set to UINT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Augend  A number to which addend will be added
+  @param[in]   Addend  A number to be added to another
+  @param[out]  Result  Pointer to the result of addition
+
+  @retval  RETURN_SUCCESS            Successful addition
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint16Add (
+  IN  UINT16  Augend,
+  IN  UINT16  Addend,
+  OUT UINT16  *Result
+  );
+
+/**
+  UINT32 addition
+
+  Performs the requested operation using the input parameters into a value
+  specified by Result type and stores the converted value into the caller
+  allocated output buffer specified by Result.  The caller must pass in a
+  Result buffer that is at least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the requested operation results in an overflow or an underflow condition,
+  then Result is set to UINT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Augend  A number to which addend will be added
+  @param[in]   Addend  A number to be added to another
+  @param[out]  Result  Pointer to the result of addition
+
+  @retval  RETURN_SUCCESS            Successful addition
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint32Add (
+  IN  UINT32  Augend,
+  IN  UINT32  Addend,
+  OUT UINT32  *Result
+  );
+
+/**
+  UINTN addition
+
+  Performs the requested operation using the input parameters into a value
+  specified by Result type and stores the converted value into the caller
+  allocated output buffer specified by Result.  The caller must pass in a
+  Result buffer that is at least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the requested operation results in an overflow or an underflow condition,
+  then Result is set to UINTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Augend  A number to which addend will be added
+  @param[in]   Addend  A number to be added to another
+  @param[out]  Result  Pointer to the result of addition
+
+  @retval  RETURN_SUCCESS            Successful addition
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUintnAdd (
+  IN  UINTN  Augend,
+  IN  UINTN  Addend,
+  OUT UINTN  *Result
+  );
+
+/**
+  UINT64 addition
+
+  Performs the requested operation using the input parameters into a value
+  specified by Result type and stores the converted value into the caller
+  allocated output buffer specified by Result.  The caller must pass in a
+  Result buffer that is at least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the requested operation results in an overflow or an underflow condition,
+  then Result is set to UINT64_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Augend  A number to which addend will be added
+  @param[in]   Addend  A number to be added to another
+  @param[out]  Result  Pointer to the result of addition
+
+  @retval  RETURN_SUCCESS            Successful addition
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint64Add (
+  IN  UINT64  Augend,
+  IN  UINT64  Addend,
+  OUT UINT64  *Result
+  );
+
+//
+// Subtraction functions
+//
+
+/**
+  UINT8 subtraction
+
+  Performs the requested operation using the input parameters into a value
+  specified by Result type and stores the converted value into the caller
+  allocated output buffer specified by Result.  The caller must pass in a
+  Result buffer that is at least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the requested operation results in an overflow or an underflow condition,
+  then Result is set to UINT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Minuend     A number from which another is to be subtracted.
+  @param[in]   Subtrahend  A number to be subtracted from another
+  @param[out]  Result      Pointer to the result of subtraction
+
+  @retval  RETURN_SUCCESS            Successful subtraction
+  @retval  RETURN_BUFFER_TOO_SMALL   Underflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint8Sub (
+  IN  UINT8  Minuend,
+  IN  UINT8  Subtrahend,
+  OUT UINT8  *Result
+  );
+
+/**
+  UINT16 subtraction
+
+  Performs the requested operation using the input parameters into a value
+  specified by Result type and stores the converted value into the caller
+  allocated output buffer specified by Result.  The caller must pass in a
+  Result buffer that is at least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the requested operation results in an overflow or an underflow condition,
+  then Result is set to UINT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Minuend     A number from which another is to be subtracted.
+  @param[in]   Subtrahend  A number to be subtracted from another
+  @param[out]  Result      Pointer to the result of subtraction
+
+  @retval  RETURN_SUCCESS            Successful subtraction
+  @retval  RETURN_BUFFER_TOO_SMALL   Underflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint16Sub (
+  IN  UINT16  Minuend,
+  IN  UINT16  Subtrahend,
+  OUT UINT16  *Result
+  );
+
+/**
+  UINT32 subtraction
+
+  Performs the requested operation using the input parameters into a value
+  specified by Result type and stores the converted value into the caller
+  allocated output buffer specified by Result.  The caller must pass in a
+  Result buffer that is at least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the requested operation results in an overflow or an underflow condition,
+  then Result is set to UINT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Minuend     A number from which another is to be subtracted.
+  @param[in]   Subtrahend  A number to be subtracted from another
+  @param[out]  Result      Pointer to the result of subtraction
+
+  @retval  RETURN_SUCCESS            Successful subtraction
+  @retval  RETURN_BUFFER_TOO_SMALL   Underflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint32Sub (
+  IN  UINT32  Minuend,
+  IN  UINT32  Subtrahend,
+  OUT UINT32  *Result
+  );
+
+/**
+  UINTN subtraction
+
+  Performs the requested operation using the input parameters into a value
+  specified by Result type and stores the converted value into the caller
+  allocated output buffer specified by Result.  The caller must pass in a
+  Result buffer that is at least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the requested operation results in an overflow or an underflow condition,
+  then Result is set to UINTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Minuend     A number from which another is to be subtracted.
+  @param[in]   Subtrahend  A number to be subtracted from another
+  @param[out]  Result      Pointer to the result of subtraction
+
+  @retval  RETURN_SUCCESS            Successful subtraction
+  @retval  RETURN_BUFFER_TOO_SMALL   Underflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUintnSub (
+  IN  UINTN  Minuend,
+  IN  UINTN  Subtrahend,
+  OUT UINTN  *Result
+  );
+
+/**
+  UINT64 subtraction
+
+  Performs the requested operation using the input parameters into a value
+  specified by Result type and stores the converted value into the caller
+  allocated output buffer specified by Result.  The caller must pass in a
+  Result buffer that is at least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the requested operation results in an overflow or an underflow condition,
+  then Result is set to UINT64_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Minuend     A number from which another is to be subtracted.
+  @param[in]   Subtrahend  A number to be subtracted from another
+  @param[out]  Result      Pointer to the result of subtraction
+
+  @retval  RETURN_SUCCESS            Successful subtraction
+  @retval  RETURN_BUFFER_TOO_SMALL   Underflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint64Sub (
+  IN  UINT64  Minuend,
+  IN  UINT64  Subtrahend,
+  OUT UINT64  *Result
+  );
+
+//
+// Multiplication functions
+//
+
+/**
+  UINT8 multiplication
+
+  Performs the requested operation using the input parameters into a value
+  specified by Result type and stores the converted value into the caller
+  allocated output buffer specified by Result.  The caller must pass in a
+  Result buffer that is at least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the requested operation results in an overflow or an underflow condition,
+  then Result is set to UINT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Multiplicand  A number that is to be multiplied by another
+  @param[in]   Multiplier    A number by which the multiplicand is to be multiplied
+  @param[out]  Result        Pointer to the result of multiplication
+
+  @retval  RETURN_SUCCESS            Successful multiplication
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint8Mult (
+  IN  UINT8  Multiplicand,
+  IN  UINT8  Multiplier,
+  OUT UINT8  *Result
+  );
+
+/**
+  UINT16 multiplication
+
+  Performs the requested operation using the input parameters into a value
+  specified by Result type and stores the converted value into the caller
+  allocated output buffer specified by Result.  The caller must pass in a
+  Result buffer that is at least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the requested operation results in an overflow or an underflow condition,
+  then Result is set to UINT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Multiplicand  A number that is to be multiplied by another
+  @param[in]   Multiplier    A number by which the multiplicand is to be multiplied
+  @param[out]  Result        Pointer to the result of multiplication
+
+  @retval  RETURN_SUCCESS            Successful multiplication
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint16Mult (
+  IN  UINT16  Multiplicand,
+  IN  UINT16  Multiplier,
+  OUT UINT16  *Result
+  );
+
+/**
+  UINT32 multiplication
+
+  Performs the requested operation using the input parameters into a value
+  specified by Result type and stores the converted value into the caller
+  allocated output buffer specified by Result.  The caller must pass in a
+  Result buffer that is at least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the requested operation results in an overflow or an underflow condition,
+  then Result is set to UINT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Multiplicand  A number that is to be multiplied by another
+  @param[in]   Multiplier    A number by which the multiplicand is to be multiplied
+  @param[out]  Result        Pointer to the result of multiplication
+
+  @retval  RETURN_SUCCESS            Successful multiplication
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint32Mult (
+  IN  UINT32  Multiplicand,
+  IN  UINT32  Multiplier,
+  OUT UINT32  *Result
+  );
+
+/**
+  UINTN multiplication
+
+  Performs the requested operation using the input parameters into a value
+  specified by Result type and stores the converted value into the caller
+  allocated output buffer specified by Result.  The caller must pass in a
+  Result buffer that is at least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the requested operation results in an overflow or an underflow condition,
+  then Result is set to UINTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Multiplicand  A number that is to be multiplied by another
+  @param[in]   Multiplier    A number by which the multiplicand is to be multiplied
+  @param[out]  Result        Pointer to the result of multiplication
+
+  @retval  RETURN_SUCCESS            Successful multiplication
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUintnMult (
+  IN  UINTN  Multiplicand,
+  IN  UINTN  Multiplier,
+  OUT UINTN  *Result
+  );
+
+/**
+  UINT64 multiplication
+
+  Performs the requested operation using the input parameters into a value
+  specified by Result type and stores the converted value into the caller
+  allocated output buffer specified by Result.  The caller must pass in a
+  Result buffer that is at least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the requested operation results in an overflow or an underflow condition,
+  then Result is set to UINT64_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Multiplicand  A number that is to be multiplied by another
+  @param[in]   Multiplier    A number by which the multiplicand is to be multiplied
+  @param[out]  Result        Pointer to the result of multiplication
+
+  @retval  RETURN_SUCCESS            Successful multiplication
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeUint64Mult (
+  IN  UINT64  Multiplicand,
+  IN  UINT64  Multiplier,
+  OUT UINT64  *Result
+  );
+
+//
+// Signed operations
+//
+// Strongly consider using unsigned numbers.
+//
+// Signed numbers are often used where unsigned numbers should be used.
+// For example file sizes and array indices should always be unsigned.
+// Subtracting a larger positive signed number from a smaller positive
+// signed number with SafeInt32Sub will succeed, producing a negative number,
+// that then must not be used as an array index (but can occasionally be
+// used as a pointer index.) Similarly for adding a larger magnitude
+// negative number to a smaller magnitude positive number.
+//
+// This library does not protect you from such errors. It tells you if your
+// integer operations overflowed, not if you are doing the right thing
+// with your non-overflowed integers.
+//
+// Likewise you can overflow a buffer with a non-overflowed unsigned index.
+//
+
+//
+// Signed addition functions
+//
+
+/**
+  INT8 Addition
+
+  Performs the requested operation using the input parameters into a value
+  specified by Result type and stores the converted value into the caller
+  allocated output buffer specified by Result.  The caller must pass in a
+  Result buffer that is at least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the requested operation results in an overflow or an underflow condition,
+  then Result is set to INT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Augend  A number to which addend will be added
+  @param[in]   Addend  A number to be added to another
+  @param[out]  Result  Pointer to the result of addition
+
+  @retval  RETURN_SUCCESS            Successful addition
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt8Add (
+  IN  INT8  Augend,
+  IN  INT8  Addend,
+  OUT INT8  *Result
+  );
+
+/**
+  CHAR8 Addition
+
+  Performs the requested operation using the input parameters into a value
+  specified by Result type and stores the converted value into the caller
+  allocated output buffer specified by Result.  The caller must pass in a
+  Result buffer that is at least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the requested operation results in an overflow or an underflow condition,
+  then Result is set to CHAR8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Augend  A number to which addend will be added
+  @param[in]   Addend  A number to be added to another
+  @param[out]  Result  Pointer to the result of addition
+
+  @retval  RETURN_SUCCESS            Successful addition
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeChar8Add (
+  IN  CHAR8  Augend,
+  IN  CHAR8  Addend,
+  OUT CHAR8  *Result
+  );
+
+/**
+  INT16 Addition
+
+  Performs the requested operation using the input parameters into a value
+  specified by Result type and stores the converted value into the caller
+  allocated output buffer specified by Result.  The caller must pass in a
+  Result buffer that is at least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the requested operation results in an overflow or an underflow condition,
+  then Result is set to INT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Augend  A number to which addend will be added
+  @param[in]   Addend  A number to be added to another
+  @param[out]  Result  Pointer to the result of addition
+
+  @retval  RETURN_SUCCESS            Successful addition
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt16Add (
+  IN  INT16  Augend,
+  IN  INT16  Addend,
+  OUT INT16  *Result
+  );
+
+/**
+  INT32 Addition
+
+  Performs the requested operation using the input parameters into a value
+  specified by Result type and stores the converted value into the caller
+  allocated output buffer specified by Result.  The caller must pass in a
+  Result buffer that is at least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the requested operation results in an overflow or an underflow condition,
+  then Result is set to INT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Augend  A number to which addend will be added
+  @param[in]   Addend  A number to be added to another
+  @param[out]  Result  Pointer to the result of addition
+
+  @retval  RETURN_SUCCESS            Successful addition
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt32Add (
+  IN  INT32  Augend,
+  IN  INT32  Addend,
+  OUT INT32  *Result
+  );
+
+/**
+  INTN Addition
+
+  Performs the requested operation using the input parameters into a value
+  specified by Result type and stores the converted value into the caller
+  allocated output buffer specified by Result.  The caller must pass in a
+  Result buffer that is at least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the requested operation results in an overflow or an underflow condition,
+  then Result is set to INTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Augend  A number to which addend will be added
+  @param[in]   Addend  A number to be added to another
+  @param[out]  Result  Pointer to the result of addition
+
+  @retval  RETURN_SUCCESS            Successful addition
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeIntnAdd (
+  IN  INTN  Augend,
+  IN  INTN  Addend,
+  OUT INTN  *Result
+  );
+
+/**
+  INT64 Addition
+
+  Performs the requested operation using the input parameters into a value
+  specified by Result type and stores the converted value into the caller
+  allocated output buffer specified by Result.  The caller must pass in a
+  Result buffer that is at least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the requested operation results in an overflow or an underflow condition,
+  then Result is set to INT64_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Augend  A number to which addend will be added
+  @param[in]   Addend  A number to be added to another
+  @param[out]  Result  Pointer to the result of addition
+
+  @retval  RETURN_SUCCESS            Successful addition
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt64Add (
+  IN  INT64  Augend,
+  IN  INT64  Addend,
+  OUT INT64  *Result
+  );
+
+//
+// Signed subtraction functions
+//
+
+/**
+  INT8 Subtraction
+
+  Performs the requested operation using the input parameters into a value
+  specified by Result type and stores the converted value into the caller
+  allocated output buffer specified by Result.  The caller must pass in a
+  Result buffer that is at least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the requested operation results in an overflow or an underflow condition,
+  then Result is set to INT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Minuend     A number from which another is to be subtracted.
+  @param[in]   Subtrahend  A number to be subtracted from another
+  @param[out]  Result      Pointer to the result of subtraction
+
+  @retval  RETURN_SUCCESS            Successful subtraction
+  @retval  RETURN_BUFFER_TOO_SMALL   Underflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt8Sub (
+  IN  INT8  Minuend,
+  IN  INT8  Subtrahend,
+  OUT INT8  *Result
+  );
+
+/**
+  CHAR8 Subtraction
+
+  Performs the requested operation using the input parameters into a value
+  specified by Result type and stores the converted value into the caller
+  allocated output buffer specified by Result.  The caller must pass in a
+  Result buffer that is at least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the requested operation results in an overflow or an underflow condition,
+  then Result is set to CHAR8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Minuend     A number from which another is to be subtracted.
+  @param[in]   Subtrahend  A number to be subtracted from another
+  @param[out]  Result      Pointer to the result of subtraction
+
+  @retval  RETURN_SUCCESS            Successful subtraction
+  @retval  RETURN_BUFFER_TOO_SMALL   Underflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeChar8Sub (
+  IN  CHAR8  Minuend,
+  IN  CHAR8  Subtrahend,
+  OUT CHAR8  *Result
+  );
+
+/**
+  INT16 Subtraction
+
+  Performs the requested operation using the input parameters into a value
+  specified by Result type and stores the converted value into the caller
+  allocated output buffer specified by Result.  The caller must pass in a
+  Result buffer that is at least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the requested operation results in an overflow or an underflow condition,
+  then Result is set to INT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Minuend     A number from which another is to be subtracted.
+  @param[in]   Subtrahend  A number to be subtracted from another
+  @param[out]  Result      Pointer to the result of subtraction
+
+  @retval  RETURN_SUCCESS            Successful subtraction
+  @retval  RETURN_BUFFER_TOO_SMALL   Underflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt16Sub (
+  IN  INT16  Minuend,
+  IN  INT16  Subtrahend,
+  OUT INT16  *Result
+  );
+
+/**
+  INT32 Subtraction
+
+  Performs the requested operation using the input parameters into a value
+  specified by Result type and stores the converted value into the caller
+  allocated output buffer specified by Result.  The caller must pass in a
+  Result buffer that is at least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the requested operation results in an overflow or an underflow condition,
+  then Result is set to INT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Minuend     A number from which another is to be subtracted.
+  @param[in]   Subtrahend  A number to be subtracted from another
+  @param[out]  Result      Pointer to the result of subtraction
+
+  @retval  RETURN_SUCCESS            Successful subtraction
+  @retval  RETURN_BUFFER_TOO_SMALL   Underflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt32Sub (
+  IN  INT32  Minuend,
+  IN  INT32  Subtrahend,
+  OUT INT32  *Result
+  );
+
+/**
+  INTN Subtraction
+
+  Performs the requested operation using the input parameters into a value
+  specified by Result type and stores the converted value into the caller
+  allocated output buffer specified by Result.  The caller must pass in a
+  Result buffer that is at least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the requested operation results in an overflow or an underflow condition,
+  then Result is set to INTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Minuend     A number from which another is to be subtracted.
+  @param[in]   Subtrahend  A number to be subtracted from another
+  @param[out]  Result      Pointer to the result of subtraction
+
+  @retval  RETURN_SUCCESS            Successful subtraction
+  @retval  RETURN_BUFFER_TOO_SMALL   Underflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeIntnSub (
+  IN  INTN  Minuend,
+  IN  INTN  Subtrahend,
+  OUT INTN  *Result
+  );
+
+/**
+  INT64 Subtraction
+
+  Performs the requested operation using the input parameters into a value
+  specified by Result type and stores the converted value into the caller
+  allocated output buffer specified by Result.  The caller must pass in a
+  Result buffer that is at least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the requested operation results in an overflow or an underflow condition,
+  then Result is set to INT64_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Minuend     A number from which another is to be subtracted.
+  @param[in]   Subtrahend  A number to be subtracted from another
+  @param[out]  Result      Pointer to the result of subtraction
+
+  @retval  RETURN_SUCCESS            Successful subtraction
+  @retval  RETURN_BUFFER_TOO_SMALL   Underflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt64Sub (
+  IN  INT64  Minuend,
+  IN  INT64  Subtrahend,
+  OUT INT64  *Result
+  );
+
+//
+// Signed multiplication functions
+//
+
+/**
+  INT8 multiplication
+
+  Performs the requested operation using the input parameters into a value
+  specified by Result type and stores the converted value into the caller
+  allocated output buffer specified by Result.  The caller must pass in a
+  Result buffer that is at least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the requested operation results in an overflow or an underflow condition,
+  then Result is set to INT8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Multiplicand  A number that is to be multiplied by another
+  @param[in]   Multiplier    A number by which the multiplicand is to be multiplied
+  @param[out]  Result        Pointer to the result of multiplication
+
+  @retval  RETURN_SUCCESS            Successful multiplication
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt8Mult (
+  IN  INT8  Multiplicand,
+  IN  INT8  Multiplier,
+  OUT INT8  *Result
+  );
+
+/**
+  CHAR8 multiplication
+
+  Performs the requested operation using the input parameters into a value
+  specified by Result type and stores the converted value into the caller
+  allocated output buffer specified by Result.  The caller must pass in a
+  Result buffer that is at least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the requested operation results in an overflow or an underflow condition,
+  then Result is set to CHAR8_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Multiplicand  A number that is to be multiplied by another
+  @param[in]   Multiplier    A number by which the multiplicand is to be multiplied
+  @param[out]  Result        Pointer to the result of multiplication
+
+  @retval  RETURN_SUCCESS            Successful multiplication
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeChar8Mult (
+  IN  CHAR8  Multiplicand,
+  IN  CHAR8  Multiplier,
+  OUT CHAR8  *Result
+  );
+
+/**
+  INT16 multiplication
+
+  Performs the requested operation using the input parameters into a value
+  specified by Result type and stores the converted value into the caller
+  allocated output buffer specified by Result.  The caller must pass in a
+  Result buffer that is at least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the requested operation results in an overflow or an underflow condition,
+  then Result is set to INT16_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Multiplicand  A number that is to be multiplied by another
+  @param[in]   Multiplier    A number by which the multiplicand is to be multiplied
+  @param[out]  Result        Pointer to the result of multiplication
+
+  @retval  RETURN_SUCCESS            Successful multiplication
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt16Mult (
+  IN  INT16  Multiplicand,
+  IN  INT16  Multiplier,
+  OUT INT16  *Result
+  );
+
+/**
+  INT32 multiplication
+
+  Performs the requested operation using the input parameters into a value
+  specified by Result type and stores the converted value into the caller
+  allocated output buffer specified by Result.  The caller must pass in a
+  Result buffer that is at least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the requested operation results in an overflow or an underflow condition,
+  then Result is set to INT32_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Multiplicand  A number that is to be multiplied by another
+  @param[in]   Multiplier    A number by which the multiplicand is to be multiplied
+  @param[out]  Result        Pointer to the result of multiplication
+
+  @retval  RETURN_SUCCESS            Successful multiplication
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt32Mult (
+  IN  INT32  Multiplicand,
+  IN  INT32  Multiplier,
+  OUT INT32  *Result
+  );
+
+/**
+  INTN multiplication
+
+  Performs the requested operation using the input parameters into a value
+  specified by Result type and stores the converted value into the caller
+  allocated output buffer specified by Result.  The caller must pass in a
+  Result buffer that is at least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the requested operation results in an overflow or an underflow condition,
+  then Result is set to INTN_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Multiplicand  A number that is to be multiplied by another
+  @param[in]   Multiplier    A number by which the multiplicand is to be multiplied
+  @param[out]  Result        Pointer to the result of multiplication
+
+  @retval  RETURN_SUCCESS            Successful multiplication
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeIntnMult (
+  IN  INTN  Multiplicand,
+  IN  INTN  Multiplier,
+  OUT INTN  *Result
+  );
+
+/**
+  INT64 multiplication
+
+  Performs the requested operation using the input parameters into a value
+  specified by Result type and stores the converted value into the caller
+  allocated output buffer specified by Result.  The caller must pass in a
+  Result buffer that is at least as large as the Result type.
+
+  If Result is NULL, RETURN_INVALID_PARAMETER is returned.
+
+  If the requested operation results in an overflow or an underflow condition,
+  then Result is set to INT64_ERROR and RETURN_BUFFER_TOO_SMALL is returned.
+
+  @param[in]   Multiplicand  A number that is to be multiplied by another
+  @param[in]   Multiplier    A number by which the multiplicand is to be multiplied
+  @param[out]  Result        Pointer to the result of multiplication
+
+  @retval  RETURN_SUCCESS            Successful multiplication
+  @retval  RETURN_BUFFER_TOO_SMALL   Overflow
+  @retval  RETURN_INVALID_PARAMETER  Result is NULL
+**/
+RETURN_STATUS
+EFIAPI
+SafeInt64Mult (
+  IN  INT64  Multiplicand,
+  IN  INT64  Multiplier,
+  OUT INT64  *Result
+  );
+
+#endif // __INT_SAFE_LIB_H__
diff --git a/MdePkg/Include/Library/SalLib.h b/MdePkg/Include/Library/SalLib.h
deleted file mode 100644
index 94e4af8e591c..000000000000
--- a/MdePkg/Include/Library/SalLib.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/** @file
-  Provides library services to make SAL Calls.
-
-Copyright (c) 2007 - 2008, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __SAL_LIB__
-#define __SAL_LIB__
-
-#include <IndustryStandard/Sal.h>
-
-/**
-  Makes a SAL procedure call.
-  
-  This is a wrapper function to make a SAL procedure call.  
-  No parameter checking is performed on the 8 input parameters,
-  but there are some common rules that the caller should follow
-  when making a SAL call.  Any address passed to SAL as buffers
-  for return parameters must be 8-byte aligned.  Unaligned
-  addresses may cause undefined results.  For those parameters
-  defined as reserved or some fields defined as reserved must be
-  zero filled or the invalid argument return value may be returned
-  or undefined result may occur during the execution of the procedure.
-  This function is only available on Intel Itanium-based platforms.
-
-  @param  Index       The SAL procedure Index number
-  @param  Arg2        The 2nd parameter for SAL procedure calls
-  @param  Arg3        The 3rd parameter for SAL procedure calls
-  @param  Arg4        The 4th parameter for SAL procedure calls
-  @param  Arg5        The 5th parameter for SAL procedure calls
-  @param  Arg6        The 6th parameter for SAL procedure calls
-  @param  Arg7        The 7th parameter for SAL procedure calls
-  @param  Arg8        The 8th parameter for SAL procedure calls
-
-  @return SAL returned registers.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-SalCall (
-  IN UINT64  Index,
-  IN UINT64  Arg2,
-  IN UINT64  Arg3,
-  IN UINT64  Arg4,
-  IN UINT64  Arg5,
-  IN UINT64  Arg6,
-  IN UINT64  Arg7,
-  IN UINT64  Arg8
-  );
-
-#endif
diff --git a/MdePkg/Include/Library/SerialPortLib.h b/MdePkg/Include/Library/SerialPortLib.h
index f56b76debd8b..1cd57656f28d 100644
--- a/MdePkg/Include/Library/SerialPortLib.h
+++ b/MdePkg/Include/Library/SerialPortLib.h
@@ -1,15 +1,9 @@
 /** @file
   This library class provides common serial I/O port functions.
 
-Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
 Copyright (c) 2012 - 2014, ARM Ltd. All rights reserved.
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -21,11 +15,11 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
 /**
   Initialize the serial device hardware.
-  
+
   If no initialization is required, then return RETURN_SUCCESS.
   If the serial device was successfully initialized, then return RETURN_SUCCESS.
   If the serial device could not be initialized, then return RETURN_DEVICE_ERROR.
-  
+
   @retval RETURN_SUCCESS        The serial device was initialized.
   @retval RETURN_DEVICE_ERROR   The serial device could not be initialized.
 
@@ -37,19 +31,19 @@ SerialPortInitialize (
   );
 
 /**
-  Write data from buffer to serial device. 
- 
-  Writes NumberOfBytes data bytes from Buffer to the serial device.  
+  Write data from buffer to serial device.
+
+  Writes NumberOfBytes data bytes from Buffer to the serial device.
   The number of bytes actually written to the serial device is returned.
   If the return value is less than NumberOfBytes, then the write operation failed.
-  If Buffer is NULL, then ASSERT(). 
+  If Buffer is NULL, then ASSERT().
   If NumberOfBytes is zero, then return 0.
 
   @param  Buffer           Pointer to the data buffer to be written.
   @param  NumberOfBytes    Number of bytes to written to the serial device.
 
   @retval 0                NumberOfBytes is 0.
-  @retval >0               The number of bytes written to the serial device.  
+  @retval >0               The number of bytes written to the serial device.
                            If this value is less than NumberOfBytes, then the write operation failed.
 
 **/
@@ -63,11 +57,11 @@ SerialPortWrite (
 
 /**
   Read data from serial device and save the datas in buffer.
- 
+
   Reads NumberOfBytes data bytes from a serial device into the buffer
-  specified by Buffer. The number of bytes actually read is returned. 
+  specified by Buffer. The number of bytes actually read is returned.
   If the return value is less than NumberOfBytes, then the rest operation failed.
-  If Buffer is NULL, then ASSERT(). 
+  If Buffer is NULL, then ASSERT().
   If NumberOfBytes is zero, then return 0.
 
   @param  Buffer           Pointer to the data buffer to store the data read from the serial device.
diff --git a/MdePkg/Include/Library/SmbusLib.h b/MdePkg/Include/Library/SmbusLib.h
index 35bf932ac690..ac747bc7470f 100644
--- a/MdePkg/Include/Library/SmbusLib.h
+++ b/MdePkg/Include/Library/SmbusLib.h
@@ -2,14 +2,8 @@
   Provides library functions to access SMBUS devices. Libraries of this class
   must be ported to a specific SMBUS controller.
 
-Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -23,7 +17,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   Computes an address that is compatible with the SMBUS Library functions.
   The unused upper bits of SlaveAddress, Command, and Length are stripped
   prior to the generation of the address.
-  
+
   @param  SlaveAddress    SMBUS Slave Address.  Range 0..127.
   @param  Command         SMBUS Command.  Range 0..255.
   @param  Length          SMBUS Data Length.  Range 0..32.
@@ -39,36 +33,36 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
 /**
   Macro that returns the SMBUS Slave Address value from an SmBusAddress Parameter value.
-  
-  @param SmBusAddress   Address that encodes the SMBUS Slave Address, SMBUS Command, SMBUS Data Length, and PEC 
+
+  @param SmBusAddress   Address that encodes the SMBUS Slave Address, SMBUS Command, SMBUS Data Length, and PEC
 **/
 #define SMBUS_LIB_SLAVE_ADDRESS(SmBusAddress)      (((SmBusAddress) >> 1)  & 0x7f)
 
 /**
   Macro that returns the SMBUS Command value from an SmBusAddress Parameter value.
-  
+
   @param SmBusAddress   Address that encodes the SMBUS Slave Address, SMBUS Command, SMBUS Data Length, and PEC
 **/
 #define SMBUS_LIB_COMMAND(SmBusAddress)            (((SmBusAddress) >> 8)  & 0xff)
 
 /**
   Macro that returns the SMBUS Data Length value from an SmBusAddress Parameter value.
-  
-  @param SmBusAddress Address that encodes the SMBUS Slave Address, SMBUS Command, SMBUS Data Length, and PEC 
+
+  @param SmBusAddress Address that encodes the SMBUS Slave Address, SMBUS Command, SMBUS Data Length, and PEC
 **/
 #define SMBUS_LIB_LENGTH(SmBusAddress)             (((SmBusAddress) >> 16) & 0x3f)
 
 /**
   Macro that returns the SMBUS PEC value from an SmBusAddress Parameter value.
-  
-  @param SmBusAddress Address that encodes the SMBUS Slave Address, SMBUS Command, SMBUS Data Length, and PEC   
+
+  @param SmBusAddress Address that encodes the SMBUS Slave Address, SMBUS Command, SMBUS Data Length, and PEC
 **/
 #define SMBUS_LIB_PEC(SmBusAddress)                ((BOOLEAN) (((SmBusAddress) & BIT22) != 0))
 
 /**
   Macro that returns the set of reserved bits from an SmBusAddress Parameter value.
-  
-  @param SmBusAddress Address that encodes the SMBUS Slave Address, SMBUS Command, SMBUS Data Length, and PEC   
+
+  @param SmBusAddress Address that encodes the SMBUS Slave Address, SMBUS Command, SMBUS Data Length, and PEC
 **/
 #define SMBUS_LIB_RESERVED(SmBusAddress)           ((SmBusAddress) & ~(BIT23 - 2))
 
@@ -282,7 +276,7 @@ SmBusWriteDataByte (
   If Status is not NULL, then the status of the executed command is returned in Status.
   If Length in SmBusAddress is not zero, then ASSERT().
   If any reserved bits of SmBusAddress are set, then ASSERT().
-  
+
   @param  SmBusAddress  Address that encodes the SMBUS Slave Address,
                         SMBUS Command, SMBUS Data Length, and PEC.
   @param  Status        Return status for the executed command.
@@ -424,7 +418,7 @@ SmBusReadBlock (
   The SMBUS slave address, SMBUS command, and SMBUS length fields of SmBusAddress are required.
   Bytes are written to the SMBUS from Buffer.
   The number of bytes written is returned, and will never return a value larger than 32-bytes.
-  If Status is not NULL, then the status of the executed command is returned in Status.  
+  If Status is not NULL, then the status of the executed command is returned in Status.
   If Length in SmBusAddress is zero or greater than 32, then ASSERT().
   If Buffer is NULL, then ASSERT().
   If any reserved bits of SmBusAddress are set, then ASSERT().
diff --git a/MdePkg/Include/Library/SmiHandlerProfileLib.h b/MdePkg/Include/Library/SmiHandlerProfileLib.h
index a544addd133b..3db65f9e356b 100644
--- a/MdePkg/Include/Library/SmiHandlerProfileLib.h
+++ b/MdePkg/Include/Library/SmiHandlerProfileLib.h
@@ -13,13 +13,7 @@
   be responsible to call the services to register information to SMM Core.
 
 Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -66,6 +60,10 @@ SmiHandlerProfileRegisterHandler (
                          For the SmmChildDispatch protocol, the HandlerGuid
                          must be the GUID of SmmChildDispatch protocol.
   @param Handler         The SMI handler.
+  @param Context         The context of the SMI handler.
+                         If it is NOT NULL, it will be used to check what is registered.
+  @param ContextSize     The size of the context in bytes.
+                         If Context is NOT NULL, it will be used to check what is registered.
 
   @retval EFI_SUCCESS           The original record is removed.
   @retval EFI_UNSUPPORTED       The feature is unsupported.
@@ -75,7 +73,9 @@ EFI_STATUS
 EFIAPI
 SmiHandlerProfileUnregisterHandler (
   IN EFI_GUID                       *HandlerGuid,
-  IN EFI_SMM_HANDLER_ENTRY_POINT2   Handler
+  IN EFI_SMM_HANDLER_ENTRY_POINT2   Handler,
+  IN VOID                           *Context, OPTIONAL
+  IN UINTN                          ContextSize OPTIONAL
   );
 
 #endif
diff --git a/MdePkg/Include/Library/SmmIoLib.h b/MdePkg/Include/Library/SmmIoLib.h
new file mode 100644
index 000000000000..49b45f8890a8
--- /dev/null
+++ b/MdePkg/Include/Library/SmmIoLib.h
@@ -0,0 +1,36 @@
+/** @file
+  Provides services for SMM IO Operation.
+
+  The SMM IO Library provides function for checking if IO resource is accessible inside of SMM.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _SMM_IO_LIB_H_
+#define _SMM_IO_LIB_H_
+
+/**
+  This function check if the MMIO resource is valid per processor architecture and
+  valid per platform design.
+
+  @param BaseAddress  The MMIO start address to be checked.
+  @param Length       The MMIO length to be checked.
+  @param Owner        A GUID representing the owner of the resource.
+                      This GUID may be used by producer to correlate the device ownership of the resource.
+                      NULL means no specific owner.
+
+  @retval TRUE  This MMIO resource is valid per processor architecture and valid per platform design.
+  @retval FALSE This MMIO resource is not valid per processor architecture or valid per platform design.
+**/
+BOOLEAN
+EFIAPI
+SmmIsMmioValid (
+  IN EFI_PHYSICAL_ADDRESS  BaseAddress,
+  IN UINT64                Length,
+  IN EFI_GUID              *Owner  OPTIONAL
+  );
+
+#endif
+
diff --git a/MdePkg/Include/Library/SmmLib.h b/MdePkg/Include/Library/SmmLib.h
index 999c41038428..7623ce2e1c17 100644
--- a/MdePkg/Include/Library/SmmLib.h
+++ b/MdePkg/Include/Library/SmmLib.h
@@ -1,16 +1,10 @@
 /** @file
   Library class name: SmmLib
-  
-  SMM Library Services that abstracts both S/W SMI generation and detection. 
 
-  Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
+  SMM Library Services that abstracts both S/W SMI generation and detection.
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.        
+  Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -19,7 +13,7 @@
 
 
 /**
-  Triggers an SMI at boot time.  
+  Triggers an SMI at boot time.
 
   This function triggers a software SMM interrupt at boot time.
 
@@ -32,7 +26,7 @@ TriggerBootServiceSoftwareSmi (
 
 
 /**
-  Triggers an SMI at run time.  
+  Triggers an SMI at run time.
 
   This function triggers a software SMM interrupt at run time.
 
@@ -45,13 +39,13 @@ TriggerRuntimeSoftwareSmi (
 
 
 /**
-  Test if a boot time software SMI happened.  
+  Test if a boot time software SMI happened.
 
   This function tests if a software SMM interrupt happened. If a software SMM interrupt happened and
   it was triggered at boot time, it returns TRUE. Otherwise, it returns FALSE.
 
   @retval TRUE   A software SMI triggered at boot time happened.
-  @retval FLASE  No software SMI happened, or the software SMI was triggered at run time.
+  @retval FALSE  No software SMI happened, or the software SMI was triggered at run time.
 
 **/
 BOOLEAN
@@ -62,13 +56,13 @@ IsBootServiceSoftwareSmi (
 
 
 /**
-  Test if a run time software SMI happened.  
+  Test if a run time software SMI happened.
 
   This function tests if a software SMM interrupt happened. If a software SMM interrupt happened and
   it was triggered at run time, it returns TRUE. Otherwise, it returns FALSE.
 
   @retval TRUE   A software SMI triggered at run time happened.
-  @retval FLASE  No software SMI happened or the software SMI was triggered at boot time.
+  @retval FALSE  No software SMI happened or the software SMI was triggered at boot time.
 
 **/
 BOOLEAN
@@ -78,8 +72,8 @@ IsRuntimeSoftwareSmi (
   );
 
 /**
-  Clear APM SMI Status Bit; Set the EOS bit. 
-  
+  Clear APM SMI Status Bit; Set the EOS bit.
+
 **/
 VOID
 EFIAPI
diff --git a/MdePkg/Include/Library/SmmMemLib.h b/MdePkg/Include/Library/SmmMemLib.h
index d460ae9577b8..feb81d11c922 100644
--- a/MdePkg/Include/Library/SmmMemLib.h
+++ b/MdePkg/Include/Library/SmmMemLib.h
@@ -4,15 +4,9 @@
   The SMM Mem Library provides function for checking if buffer is outside SMRAM and valid.
   It also provides functions for copy data from SMRAM to non-SMRAM, from non-SMRAM to SMRAM,
   from non-SMRAM to non-SMRAM, or set data in non-SMRAM.
-  
-  Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -68,12 +62,12 @@ SmmCopyMemToSmram (
   If the check passes, it copies memory and returns EFI_SUCCESS.
   If the check fails, it returns EFI_SECURITY_VIOLATION.
   The implementation must be reentrant.
-  
+
   @param  DestinationBuffer   The pointer to the destination buffer of the memory copy.
   @param  SourceBuffer        The pointer to the source buffer of the memory copy.
   @param  Length              The number of bytes to copy from SourceBuffer to DestinationBuffer.
 
-  @retval EFI_SECURITY_VIOLATION The DesinationBuffer is invalid per processor architecture or overlap with SMRAM.
+  @retval EFI_SECURITY_VIOLATION The DestinationBuffer is invalid per processor architecture or overlap with SMRAM.
   @retval EFI_SUCCESS            Memory is copied.
 
 **/
@@ -93,12 +87,12 @@ SmmCopyMemFromSmram (
   If the check passes, it copies memory and returns EFI_SUCCESS.
   If the check fails, it returns EFI_SECURITY_VIOLATION.
   The implementation must be reentrant, and it must handle the case where source buffer overlaps destination buffer.
-  
+
   @param  DestinationBuffer   The pointer to the destination buffer of the memory copy.
   @param  SourceBuffer        The pointer to the source buffer of the memory copy.
   @param  Length              The number of bytes to copy from SourceBuffer to DestinationBuffer.
 
-  @retval EFI_SECURITY_VIOLATION The DesinationBuffer is invalid per processor architecture or overlap with SMRAM.
+  @retval EFI_SECURITY_VIOLATION The DestinationBuffer is invalid per processor architecture or overlap with SMRAM.
   @retval EFI_SECURITY_VIOLATION The SourceBuffer is invalid per processor architecture or overlap with SMRAM.
   @retval EFI_SUCCESS            Memory is copied.
 
@@ -118,11 +112,11 @@ SmmCopyMem (
   It checks if target buffer is valid per processor architecture and not overlap with SMRAM.
   If the check passes, it fills memory and returns EFI_SUCCESS.
   If the check fails, it returns EFI_SECURITY_VIOLATION.
-  
+
   @param  Buffer    The memory to set.
   @param  Length    The number of bytes to set.
   @param  Value     The value with which to fill Length bytes of Buffer.
-  
+
   @retval EFI_SECURITY_VIOLATION The Buffer is invalid per processor architecture or overlap with SMRAM.
   @retval EFI_SUCCESS            Memory is set.
 
@@ -135,4 +129,4 @@ SmmSetMem (
   IN UINT8  Value
   );
 
-#endif
\ No newline at end of file
+#endif
diff --git a/MdePkg/Include/Library/SmmPeriodicSmiLib.h b/MdePkg/Include/Library/SmmPeriodicSmiLib.h
index dee4d98f55d6..c9682be2c8c6 100644
--- a/MdePkg/Include/Library/SmmPeriodicSmiLib.h
+++ b/MdePkg/Include/Library/SmmPeriodicSmiLib.h
@@ -1,14 +1,8 @@
 /** @file
   Provides services to enable and disable periodic SMI handlers.
 
-Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -19,15 +13,15 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
 /**
   This function returns a pointer to a table of supported periodic
-  SMI tick periods in 100 ns units sorted from largest to smallest.  
-  The table contains a array of UINT64 values terminated by a tick 
+  SMI tick periods in 100 ns units sorted from largest to smallest.
+  The table contains a array of UINT64 values terminated by a tick
   period value of 0.  The returned table must be treated as read-only
   data and must not be freed.
-  
-  @return  A pointer to a table of UINT64 tick period values in 
-           100ns units sorted from largest to smallest terminated 
+
+  @return  A pointer to a table of UINT64 tick period values in
+           100ns units sorted from largest to smallest terminated
            by a tick period of 0.
-  
+
 **/
 UINT64 *
 EFIAPI
@@ -53,30 +47,30 @@ PeriodicSmiExecutionTime (
   );
 
 /**
-  This function returns control back to the SMM Foundation.  When the next 
+  This function returns control back to the SMM Foundation.  When the next
   periodic SMI for the currently executing handler is triggered, the periodic
   SMI handler will restarted from its registered DispatchFunction entry point.
-  If this function is not called from within an enabled periodic SMI handler, 
+  If this function is not called from within an enabled periodic SMI handler,
   then control is returned to the calling function.
 
 **/
 VOID
-EFIAPI  
+EFIAPI
 PeriodicSmiExit (
   VOID
   );
 
 /**
-  This function yields control back to the SMM Foundation.  When the next 
+  This function yields control back to the SMM Foundation.  When the next
   periodic SMI for the currently executing handler is triggered, the periodic
-  SMI handler will be resumed and this function will return.  Use of this 
-  function requires a seperate stack for the periodic SMI handler.  A non zero
-  stack size must be specified in PeriodicSmiEnable() for this function to be 
-  used.  
-  
+  SMI handler will be resumed and this function will return.  Use of this
+  function requires a separate stack for the periodic SMI handler.  A non zero
+  stack size must be specified in PeriodicSmiEnable() for this function to be
+  used.
+
   If the stack size passed into PeriodicSmiEnable() was zero, the 0 is returned.
-  
-  If this function is not called from within an enabled periodic SMI handler, 
+
+  If this function is not called from within an enabled periodic SMI handler,
   then 0 is returned.
 
   @return  The actual time in 100ns units elapsed since this function was
@@ -84,21 +78,21 @@ PeriodicSmiExit (
 
 **/
 UINT64
-EFIAPI  
+EFIAPI
 PeriodicSmiYield (
   VOID
   );
 
 /**
-  This function is a prototype for a periodic SMI handler function 
+  This function is a prototype for a periodic SMI handler function
   that may be enabled with PeriodicSmiEnable() and disabled with
   PeriodicSmiDisable().
 
   @param[in] Context      Content registered with PeriodicSmiEnable().
   @param[in] ElapsedTime  The actual time in 100ns units elapsed since
-                          this function was called.  A value of 0 indicates 
+                          this function was called.  A value of 0 indicates
                           an unknown amount of time.
-                            
+
 **/
 typedef
 VOID
@@ -106,48 +100,48 @@ VOID
   IN CONST VOID  *Context OPTIONAL,
   IN UINT64      ElapsedTime
   );
-  
+
 /**
   This function enables a periodic SMI handler.
-  
-  @param[in, out] DispatchHandle   A pointer to the handle associated with the 
-                                   enabled periodic SMI handler.  This is an 
-                                   optional parameter that may be NULL.  If it is 
-                                   NULL, then the handle will not be returned, 
-                                   which means that the periodic SMI handler can 
+
+  @param[in, out] DispatchHandle   A pointer to the handle associated with the
+                                   enabled periodic SMI handler.  This is an
+                                   optional parameter that may be NULL.  If it is
+                                   NULL, then the handle will not be returned,
+                                   which means that the periodic SMI handler can
                                    never be disabled.
   @param[in]     DispatchFunction  A pointer to a periodic SMI handler function.
   @param[in]     Context           Optional content to pass into DispatchFunction.
-  @param[in]     TickPeriod        The requested tick period in 100ns units that 
-                                   control should be givien to the periodic SMI
+  @param[in]     TickPeriod        The requested tick period in 100ns units that
+                                   control should be given to the periodic SMI
                                    handler.  Must be one of the supported values
                                    returned by PeriodicSmiSupportedPickPeriod().
   @param[in]     Cpu               Specifies the CPU that is required to execute
-                                   the periodic SMI handler.  If Cpu is 
-                                   PERIODIC_SMI_LIBRARY_ANY_CPU, then the periodic 
-                                   SMI handler will always be executed on the SMST 
-                                   CurrentlyExecutingCpu, which may vary across 
-                                   periodic SMIs.  If Cpu is between 0 and the SMST 
+                                   the periodic SMI handler.  If Cpu is
+                                   PERIODIC_SMI_LIBRARY_ANY_CPU, then the periodic
+                                   SMI handler will always be executed on the SMST
+                                   CurrentlyExecutingCpu, which may vary across
+                                   periodic SMIs.  If Cpu is between 0 and the SMST
                                    NumberOfCpus, then the periodic SMI will always
                                    be executed on the requested CPU.
   @param[in]     StackSize         The size, in bytes, of the stack to allocate for
                                    use by the periodic SMI handler.  If 0, then the
                                    default stack will be used.
-                            
+
   @retval EFI_INVALID_PARAMETER  DispatchFunction is NULL.
-  @retval EFI_UNSUPPORTED        TickPeriod is not a supported tick period.  The 
-                                 supported tick periods can be retrieved using 
+  @retval EFI_UNSUPPORTED        TickPeriod is not a supported tick period.  The
+                                 supported tick periods can be retrieved using
                                  PeriodicSmiSupportedTickPeriod().
-  @retval EFI_INVALID_PARAMETER  Cpu is not PERIODIC_SMI_LIBRARY_ANY_CPU or in 
+  @retval EFI_INVALID_PARAMETER  Cpu is not PERIODIC_SMI_LIBRARY_ANY_CPU or in
                                  the range 0 to SMST NumberOfCpus.
-  @retval EFI_OUT_OF_RESOURCES   There are not enough resources to enable the 
+  @retval EFI_OUT_OF_RESOURCES   There are not enough resources to enable the
                                  periodic SMI handler.
-  @retval EFI_OUT_OF_RESOURCES   There are not enough resources to allocate the 
-                                 stack speficied by StackSize.
+  @retval EFI_OUT_OF_RESOURCES   There are not enough resources to allocate the
+                                 stack specified by StackSize.
   @retval EFI_SUCCESS            The periodic SMI handler was enabled.
-  
+
 **/
-EFI_STATUS 
+EFI_STATUS
 EFIAPI
 PeriodicSmiEnable (
   IN OUT EFI_HANDLE                    *DispatchHandle,    OPTIONAL
@@ -161,24 +155,24 @@ PeriodicSmiEnable (
 /**
   This function disables a periodic SMI handler that has been previously
   enabled with PeriodicSmiEnable().
-  
-  @param[in] DispatchHandle  A handle associated with a previously enabled periodic 
+
+  @param[in] DispatchHandle  A handle associated with a previously enabled periodic
                              SMI handler.  This is an optional parameter that may
                              be NULL.  If it is NULL, then the active periodic SMI
                              handlers is disabled.
 
   @retval FALSE  DispatchHandle is NULL and there is no active periodic SMI handler.
-  @retval FALSE  The periodic SMI handler specified by DispatchHandle has 
+  @retval FALSE  The periodic SMI handler specified by DispatchHandle has
                  not been enabled with PeriodicSmiEnable().
-  @retval TRUE   The periodic SMI handler specified by DispatchHandle has 
+  @retval TRUE   The periodic SMI handler specified by DispatchHandle has
                  been disabled.  If DispatchHandle is NULL, then the active
                  periodic SMI handler has been disabled.
-  
+
 **/
-BOOLEAN 
+BOOLEAN
 EFIAPI
 PeriodicSmiDisable (
   IN EFI_HANDLE  DispatchHandle    OPTIONAL
   );
-  
+
 #endif
diff --git a/MdePkg/Include/Library/SmmServicesTableLib.h b/MdePkg/Include/Library/SmmServicesTableLib.h
index b8c0d5660fc3..110d70b89c0f 100644
--- a/MdePkg/Include/Library/SmmServicesTableLib.h
+++ b/MdePkg/Include/Library/SmmServicesTableLib.h
@@ -2,14 +2,8 @@
   Provides a service to retrieve a pointer to the SMM Services Table.
   Only available to SMM module types.
 
-Copyright (c) 2009, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -24,14 +18,14 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 extern EFI_SMM_SYSTEM_TABLE2   *gSmst;
 
 /**
-  This function allows the caller to determine if the driver is executing in 
+  This function allows the caller to determine if the driver is executing in
   System Management Mode(SMM).
 
-  This function returns TRUE if the driver is executing in SMM and FALSE if the 
+  This function returns TRUE if the driver is executing in SMM and FALSE if the
   driver is not executing in SMM.
 
   @retval  TRUE  The driver is executing in System Management Mode (SMM).
-  @retval  FALSE The driver is not executing in System Management Mode (SMM). 
+  @retval  FALSE The driver is not executing in System Management Mode (SMM).
 
 **/
 BOOLEAN
diff --git a/MdePkg/Include/Library/StandaloneMmDriverEntryPoint.h b/MdePkg/Include/Library/StandaloneMmDriverEntryPoint.h
new file mode 100644
index 000000000000..9de5f362837b
--- /dev/null
+++ b/MdePkg/Include/Library/StandaloneMmDriverEntryPoint.h
@@ -0,0 +1,125 @@
+/** @file
+  Module entry point library for Standalone MM Drivers.
+
+Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2016 - 2018, ARM Limited. All rights reserved.<BR>
+Copyright (c) 2018, Linaro, Limited. All rights reserved.<BR>
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __MODULE_ENTRY_POINT_H__
+#define __MODULE_ENTRY_POINT_H__
+
+///
+/// Declare the PI Specification Revision that this driver requires to execute
+/// correctly.
+///
+extern CONST UINT32                   _gMmRevision;
+
+/**
+  The entry point of PE/COFF Image for a Standalone MM Driver.
+
+  This function is the entry point for a Standalone MM Driver.
+  This function must call ProcessLibraryConstructorList() and
+  ProcessModuleEntryPointList().
+  If the return status from ProcessModuleEntryPointList()
+  is an error status, then ProcessLibraryDestructorList() must be called.
+  The return value from ProcessModuleEntryPointList() is returned.
+  If _gMmRevision is not zero and MmSystemTable->Hdr.Revision is
+  less than _gMmRevision, then return EFI_INCOMPATIBLE_VERSION.
+
+  @param  ImageHandle    The image handle of the Standalone MM Driver.
+  @param  MmSystemTable  A pointer to the MM System Table.
+
+  @retval  EFI_SUCCESS               The Standalone MM Driver exited normally.
+  @retval  EFI_INCOMPATIBLE_VERSION  _gMmRevision is greater than
+                                     MmSystemTable->Hdr.Revision.
+  @retval  Other                     Return value from
+                                     ProcessModuleEntryPointList().
+
+**/
+EFI_STATUS
+EFIAPI
+_ModuleEntryPoint (
+  IN EFI_HANDLE             ImageHandle,
+  IN EFI_MM_SYSTEM_TABLE    *MmSystemTable
+  );
+
+
+/**
+  Auto generated function that calls the library constructors for all of the
+  module's dependent libraries.
+
+  This function must be called by _ModuleEntryPoint().
+  This function calls the set of library constructors for the set of library
+  instances that a module depends on.  This includes library instances that a
+  module depends on directly and library instances that a module depends on
+  indirectly through other libraries. This function is auto generated by build
+  tools and those build tools are responsible for collecting the set of library
+  instances, determine which ones have constructors, and calling the library
+  constructors in the proper order based upon each of the library instances own
+  dependencies.
+
+  @param  ImageHandle    The image handle of the Standalone MM Driver.
+  @param  MmSystemTable  A pointer to the MM System Table.
+
+**/
+VOID
+EFIAPI
+ProcessLibraryConstructorList (
+  IN EFI_HANDLE             ImageHandle,
+  IN EFI_MM_SYSTEM_TABLE    *MmSystemTable
+  );
+
+
+/**
+  Auto generated function that calls the library descructors for all of the
+  module's dependent libraries.
+
+  This function may be called by _ModuleEntryPoint().
+  This function calls the set of library destructors for the set of library
+  instances that a module depends on. This includes library instances that a
+  module depends on directly and library instances that a module depends on
+  indirectly through other libraries.
+  This function is auto generated by build tools and those build tools are
+  responsible for collecting the set of library instances, determine which ones
+  have destructors, and calling the library destructors in the proper order
+  based upon each of the library instances own dependencies.
+
+  @param  ImageHandle    The image handle of the Standalone MM Driver.
+  @param  MmSystemTable  A pointer to the MM System Table.
+
+**/
+VOID
+EFIAPI
+ProcessLibraryDestructorList (
+  IN EFI_HANDLE             ImageHandle,
+  IN EFI_MM_SYSTEM_TABLE    *MmSystemTable
+  );
+
+
+/**
+  Auto generated function that calls a set of module entry points.
+
+  This function must be called by _ModuleEntryPoint().
+  This function calls the set of module entry points.
+  This function is auto generated by build tools and those build tools are
+  responsible for collecting the module entry points and calling them in a
+  specified order.
+
+  @param  ImageHandle    The image handle of the Standalone MM Driver.
+  @param  MmSystemTable  A pointer to the MM System Table.
+
+  @retval  EFI_SUCCESS   The Standalone MM Driver executed normally.
+  @retval  !EFI_SUCCESS  The Standalone MM Driver failed to execute normally.
+**/
+EFI_STATUS
+EFIAPI
+ProcessModuleEntryPointList (
+  IN EFI_HANDLE             ImageHandle,
+  IN EFI_MM_SYSTEM_TABLE    *MmSystemTable
+  );
+
+#endif
diff --git a/MdePkg/Include/Library/SynchronizationLib.h b/MdePkg/Include/Library/SynchronizationLib.h
index bfdf6f4222ed..fc01b10cd4b7 100644
--- a/MdePkg/Include/Library/SynchronizationLib.h
+++ b/MdePkg/Include/Library/SynchronizationLib.h
@@ -1,14 +1,8 @@
 /** @file
   Provides synchronization functions.
 
-Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -26,7 +20,7 @@ typedef volatile UINTN              SPIN_LOCK;
   optimal spin lock performance.
 
   This function retrieves the spin lock alignment requirements for optimal
-  performance on a given CPU architecture. The spin lock alignment is byte alignment. 
+  performance on a given CPU architecture. The spin lock alignment is byte alignment.
   It must be a power of two and is returned by this function. If there are no alignment
   requirements, then 1 must be returned. The spin lock synchronization
   functions must function correctly if the spin lock size and alignment values
@@ -144,8 +138,7 @@ ReleaseSpinLock (
 
   Performs an atomic increment of the 32-bit unsigned integer specified by
   Value and returns the incremented value. The increment operation must be
-  performed using MP safe mechanisms. The state of the return value is not
-  guaranteed to be MP safe.
+  performed using MP safe mechanisms.
 
   If Value is NULL, then ASSERT().
 
@@ -166,8 +159,7 @@ InterlockedIncrement (
 
   Performs an atomic decrement of the 32-bit unsigned integer specified by
   Value and returns the decremented value. The decrement operation must be
-  performed using MP safe mechanisms. The state of the return value is not
-  guaranteed to be MP safe.
+  performed using MP safe mechanisms.
 
   If Value is NULL, then ASSERT().
 
diff --git a/MdePkg/Include/Library/TimerLib.h b/MdePkg/Include/Library/TimerLib.h
index f0d898a9894f..a4c2d8818b78 100644
--- a/MdePkg/Include/Library/TimerLib.h
+++ b/MdePkg/Include/Library/TimerLib.h
@@ -2,13 +2,7 @@
   Provides calibrated delay and performance counter services.
 
 Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/Library/UefiApplicationEntryPoint.h b/MdePkg/Include/Library/UefiApplicationEntryPoint.h
index c84282397c73..b5c00c1457bc 100644
--- a/MdePkg/Include/Library/UefiApplicationEntryPoint.h
+++ b/MdePkg/Include/Library/UefiApplicationEntryPoint.h
@@ -1,14 +1,8 @@
 /** @file
   Module entry point library for UEFI Applications.
 
-Copyright (c) 2007 - 2008, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -16,7 +10,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #define __UEFI_APPLICATION_ENTRY_POINT_H__
 
 ///
-/// Declare the EFI/UEFI Specification Revision to which this driver is implemented 
+/// Declare the EFI/UEFI Specification Revision to which this driver is implemented
 ///
 extern CONST UINT32        _gUefiDriverRevision;
 
@@ -47,7 +41,7 @@ _ModuleEntryPoint (
 
 
 /**
-  Required by the EBC compiler and identical in functionality to _ModuleEntryPoint(). 
+  Required by the EBC compiler and identical in functionality to _ModuleEntryPoint().
 
   @param  ImageHandle  The image handle of the UEFI Application.
   @param  SystemTable  A pointer to the EFI System Table.
@@ -67,13 +61,13 @@ EfiMain (
 
 /**
   Invokes the library destructors for all dependent libraries and terminates
-  the UEFI Application. 
+  the UEFI Application.
 
   This function calls ProcessLibraryDestructorList() and the EFI Boot Service Exit()
   with a status specified by Status.
 
   @param  Status  Status returned by the application that is exiting.
-  
+
 **/
 VOID
 EFIAPI
@@ -89,7 +83,7 @@ Exit (
   This function must be called by _ModuleEntryPoint().
   This function calls the set of library constructors for the set of library instances
   that a module depends on. This includes library instances that a module depends on
-  directly and library instances that a module depends on indirectly through other libraries.  
+  directly and library instances that a module depends on indirectly through other libraries.
   This function is autogenerated by build tools and those build tools are responsible for
   collecting the set of library instances, determine which ones have constructors, and
   calling the library constructors in the proper order based upon each of the library
@@ -97,7 +91,7 @@ Exit (
 
   @param  ImageHandle  The image handle of the UEFI Application.
   @param  SystemTable  A pointer to the EFI System Table.
-  
+
 **/
 VOID
 EFIAPI
@@ -114,7 +108,7 @@ ProcessLibraryConstructorList (
   This function may be called by _ModuleEntryPoint()or Exit().
   This function calls the set of library destructors for the set of library instances
   that a module depends on.  This includes library instances that a module depends on
-  directly and library instances that a module depends on indirectly through other libraries.  
+  directly and library instances that a module depends on indirectly through other libraries.
   This function is autogenerated by build tools and those build tools are responsible
   for collecting the set of library instances, determine which ones have destructors,
   and calling the library destructors in the proper order based upon each of the library
@@ -134,7 +128,7 @@ ProcessLibraryDestructorList (
 /**
   This function calls the set of module entry points. It must be called by _ModuleEntryPoint().
 
-  This function is autogenerated by build tools and those build tools are 
+  This function is autogenerated by build tools and those build tools are
   responsible for collecting the module entry points and calling them in a specified order.
 
   @param  ImageHandle    The image handle of the UEFI Application.
diff --git a/MdePkg/Include/Library/UefiBootServicesTableLib.h b/MdePkg/Include/Library/UefiBootServicesTableLib.h
index b382a8d51ed7..499071bc04b9 100644
--- a/MdePkg/Include/Library/UefiBootServicesTableLib.h
+++ b/MdePkg/Include/Library/UefiBootServicesTableLib.h
@@ -3,13 +3,7 @@
   Only available to DXE and UEFI module types.
 
 Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/Library/UefiDecompressLib.h b/MdePkg/Include/Library/UefiDecompressLib.h
index 2a7a91e5c1d9..510e80aa9c3b 100644
--- a/MdePkg/Include/Library/UefiDecompressLib.h
+++ b/MdePkg/Include/Library/UefiDecompressLib.h
@@ -1,19 +1,13 @@
 /** @file
   Provides services to decompress a buffer using the UEFI Decompress algorithm.
 
-  The UEFI Decompress Library enables the decompression of objects that 
-  were compressed using the UEFI compression scheme. The UEFI Decompress 
-  Library is independent of environment and requires the caller to allocate 
+  The UEFI Decompress Library enables the decompression of objects that
+  were compressed using the UEFI compression scheme. The UEFI Decompress
+  Library is independent of environment and requires the caller to allocate
   all required memory buffers.
 
-Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -21,18 +15,18 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #define __UEFI_DECPOMPRESS_LIB_H__
 
 /**
-  Given a compressed source buffer, this function retrieves the size of 
-  the uncompressed buffer and the size of the scratch buffer required 
+  Given a compressed source buffer, this function retrieves the size of
+  the uncompressed buffer and the size of the scratch buffer required
   to decompress the compressed source buffer.
 
-  Retrieves the size of the uncompressed buffer and the temporary scratch buffer 
+  Retrieves the size of the uncompressed buffer and the temporary scratch buffer
   required to decompress the buffer specified by Source and SourceSize.
   If the size of the uncompressed buffer or the size of the scratch buffer cannot
-  be determined from the compressed data specified by Source and SourceData, 
+  be determined from the compressed data specified by Source and SourceData,
   then RETURN_INVALID_PARAMETER is returned.  Otherwise, the size of the uncompressed
   buffer is returned in DestinationSize, the size of the scratch buffer is returned
   in ScratchSize, and RETURN_SUCCESS is returned.
-  This function does not have scratch buffer available to perform a thorough 
+  This function does not have scratch buffer available to perform a thorough
   checking of the validity of the source data.  It just retrieves the "Original Size"
   field from the beginning bytes of the source data and output it as DestinationSize.
   And ScratchSize is specific to the decompression implementation.
@@ -47,16 +41,16 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
                           that will be generated when the compressed buffer specified
                           by Source and SourceSize is decompressed.
   @param  ScratchSize     A pointer to the size, in bytes, of the scratch buffer that
-                          is required to decompress the compressed buffer specified 
+                          is required to decompress the compressed buffer specified
                           by Source and SourceSize.
 
-  @retval  RETURN_SUCCESS The size of the uncompressed data was returned 
-                          in DestinationSize and the size of the scratch 
+  @retval  RETURN_SUCCESS The size of the uncompressed data was returned
+                          in DestinationSize and the size of the scratch
                           buffer was returned in ScratchSize.
-  @retval  RETURN_INVALID_PARAMETER 
-                          The size of the uncompressed data or the size of 
-                          the scratch buffer cannot be determined from 
-                          the compressed data specified by Source 
+  @retval  RETURN_INVALID_PARAMETER
+                          The size of the uncompressed data or the size of
+                          the scratch buffer cannot be determined from
+                          the compressed data specified by Source
                           and SourceSize.
 **/
 RETURN_STATUS
@@ -74,10 +68,10 @@ UefiDecompressGetInfo (
   Extracts decompressed data to its original form.
   This function is designed so that the decompression algorithm can be implemented
   without using any memory services.  As a result, this function is not allowed to
-  call any memory allocation services in its implementation.  It is the caller's 
+  call any memory allocation services in its implementation.  It is the caller's
   responsibility to allocate and free the Destination and Scratch buffers.
-  If the compressed source data specified by Source is successfully decompressed 
-  into Destination, then RETURN_SUCCESS is returned.  If the compressed source data 
+  If the compressed source data specified by Source is successfully decompressed
+  into Destination, then RETURN_SUCCESS is returned.  If the compressed source data
   specified by Source is not in a valid compressed data format,
   then RETURN_INVALID_PARAMETER is returned.
 
@@ -88,13 +82,13 @@ UefiDecompressGetInfo (
   @param  Source      The source buffer containing the compressed data.
   @param  Destination The destination buffer to store the decompressed data
   @param  Scratch     A temporary scratch buffer that is used to perform the decompression.
-                      This is an optional parameter that may be NULL if the 
+                      This is an optional parameter that may be NULL if the
                       required scratch buffer size is 0.
-                     
-  @retval  RETURN_SUCCESS Decompression completed successfully, and 
+
+  @retval  RETURN_SUCCESS Decompression completed successfully, and
                           the uncompressed buffer is returned in Destination.
-  @retval  RETURN_INVALID_PARAMETER 
-                          The source buffer specified by Source is corrupted 
+  @retval  RETURN_INVALID_PARAMETER
+                          The source buffer specified by Source is corrupted
                           (not in a valid compressed format).
 **/
 RETURN_STATUS
diff --git a/MdePkg/Include/Library/UefiDriverEntryPoint.h b/MdePkg/Include/Library/UefiDriverEntryPoint.h
index f0812bc2722a..9eb0adf35f9d 100644
--- a/MdePkg/Include/Library/UefiDriverEntryPoint.h
+++ b/MdePkg/Include/Library/UefiDriverEntryPoint.h
@@ -2,14 +2,8 @@
   Module entry point library for UEFI drivers, DXE Drivers, DXE Runtime Drivers,
   and DXE SMM Drivers.
 
-Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -22,18 +16,18 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 extern CONST UINT32                   _gDxeRevision;
 
 ///
-/// Declare the EFI/UEFI Specification Revision to which this driver is implemented 
+/// Declare the EFI/UEFI Specification Revision to which this driver is implemented
 ///
 extern CONST UINT32                   _gUefiDriverRevision;
 
 ///
-/// Declare the number of unload handler in the image. 
+/// Declare the number of unload handler in the image.
 ///
 extern CONST UINT8                    _gDriverUnloadImageCount;
 
 
 /**
-  The entry point of PE/COFF Image for a DXE Driver, DXE Runtime Driver, DXE SMM Driver, or UEFI Driver. 
+  The entry point of PE/COFF Image for a DXE Driver, DXE Runtime Driver, DXE SMM Driver, or UEFI Driver.
 
   This function is the entry point for a DXE Driver, DXE Runtime Driver, DXE SMM Driver,
   or UEFI Driver.  This function must call ProcessLibraryConstructorList() and
@@ -64,7 +58,7 @@ _ModuleEntryPoint (
 
 
 /**
-  Required by the EBC compiler and identical in functionality to _ModuleEntryPoint(). 
+  Required by the EBC compiler and identical in functionality to _ModuleEntryPoint().
 
   This function is required to call _ModuleEntryPoint() passing in ImageHandle, and SystemTable.
 
@@ -86,7 +80,7 @@ EfiMain (
 
 /**
   Invokes the library destructors for all dependent libraries and terminates the
-  DXE Driver, DXE Runtime Driver, DXE SMM Driver, or UEFI Driver. 
+  DXE Driver, DXE Runtime Driver, DXE SMM Driver, or UEFI Driver.
 
   This function calls ProcessLibraryDestructorList() and the EFI Boot Service Exit()
   with a status specified by Status.
@@ -108,7 +102,7 @@ ExitDriver (
   This function must be called by _ModuleEntryPoint().
   This function calls the set of library constructors for the set of library instances
   that a module depends on.  This includes library instances that a module depends on
-  directly and library instances that a module depends on indirectly through other libraries.  
+  directly and library instances that a module depends on indirectly through other libraries.
   This function is autogenerated by build tools and those build tools are responsible
   for collecting the set of library instances, determine which ones have constructors,
   and calling the library constructors in the proper order based upon each of the library
@@ -133,7 +127,7 @@ ProcessLibraryConstructorList (
   This function may be called by _ModuleEntryPoint() or ExitDriver().
   This function calls the set of library destructors for the set of library instances
   that a module depends on. This includes library instances that a module depends on
-  directly and library instances that a module depends on indirectly through other libraries.  
+  directly and library instances that a module depends on indirectly through other libraries.
   This function is autogenerated by build tools and those build tools are responsible for
   collecting the set of library instances, determine which ones have destructors, and calling
   the library destructors in the proper order based upon each of the library instances own dependencies.
@@ -154,7 +148,7 @@ ProcessLibraryDestructorList (
   Autogenerated function that calls a set of module entry points.
 
   This function must be called by _ModuleEntryPoint().
-  This function calls the set of module entry points.  
+  This function calls the set of module entry points.
   This function is autogenerated by build tools and those build tools are responsible
   for collecting the module entry points and calling them in a specified order.
 
@@ -176,7 +170,7 @@ ProcessModuleEntryPointList (
   Autogenerated function that calls a set of module unload handlers.
 
   This function must be called from the unload handler registered by _ModuleEntryPoint().
-  This function calls the set of module unload handlers.  
+  This function calls the set of module unload handlers.
   This function is autogenerated by build tools and those build tools are responsible
   for collecting the module unload handlers and calling them in a specified order.
 
diff --git a/MdePkg/Include/Library/UefiLib.h b/MdePkg/Include/Library/UefiLib.h
index d91bcf83954f..fb39f5f0d487 100644
--- a/MdePkg/Include/Library/UefiLib.h
+++ b/MdePkg/Include/Library/UefiLib.h
@@ -2,30 +2,27 @@
   Provides library functions for common UEFI operations. Only available to DXE
   and UEFI module types.
 
-  The UEFI Library provides functions and macros that simplify the development of 
-  UEFI Drivers and UEFI Applications.  These functions and macros help manage EFI 
-  events, build simple locks utilizing EFI Task Priority Levels (TPLs), install 
-  EFI Driver Model related protocols, manage Unicode string tables for UEFI Drivers, 
+  The UEFI Library provides functions and macros that simplify the development of
+  UEFI Drivers and UEFI Applications.  These functions and macros help manage EFI
+  events, build simple locks utilizing EFI Task Priority Levels (TPLs), install
+  EFI Driver Model related protocols, manage Unicode string tables for UEFI Drivers,
   and print messages on the console output and standard error devices.
 
   Note that a reserved macro named MDEPKG_NDEBUG is introduced for the intention
   of size reduction when compiler optimization is disabled. If MDEPKG_NDEBUG is
   defined, then debug and assert related macros wrapped by it are the NULL implementations.
 
-Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2019, NVIDIA Corporation. All rights reserved.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
 #ifndef __UEFI_LIB_H__
 #define __UEFI_LIB_H__
 
+#include <IndustryStandard/Acpi.h>
+
 #include <Protocol/DriverBinding.h>
 #include <Protocol/DriverConfiguration.h>
 #include <Protocol/ComponentName.h>
@@ -33,6 +30,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #include <Protocol/DriverDiagnostics.h>
 #include <Protocol/DriverDiagnostics2.h>
 #include <Protocol/GraphicsOutput.h>
+#include <Protocol/DevicePath.h>
+#include <Protocol/SimpleFileSystem.h>
 
 #include <Library/BaseLib.h>
 
@@ -54,7 +53,7 @@ typedef enum {
 } EFI_LOCK_STATE;
 
 ///
-/// EFI Lock 
+/// EFI Lock
 ///
 typedef struct {
   EFI_TPL         Tpl;
@@ -99,8 +98,8 @@ typedef struct {
 #define EFI_TIMER_PERIOD_SECONDS(Seconds)           MultU64x32((UINT64)(Seconds), 10000000)
 
 /**
-  Macro that returns the a pointer to the next EFI_MEMORY_DESCRIPTOR in an array 
-  returned from GetMemoryMap().  
+  Macro that returns the a pointer to the next EFI_MEMORY_DESCRIPTOR in an array
+  returned from GetMemoryMap().
 
   @param  MemoryDescriptor  A pointer to an EFI_MEMORY_DESCRIPTOR.
 
@@ -115,7 +114,7 @@ typedef struct {
 /**
   Retrieves a pointer to the system configuration table from the EFI System Table
   based on a specified GUID.
-  
+
   This function searches the list of configuration tables stored in the EFI System Table
   for a table with a GUID that matches TableGuid. If a match is found, then a pointer to
   the configuration table is returned in Table, and EFI_SUCCESS is returned. If a matching GUID
@@ -132,7 +131,7 @@ typedef struct {
 **/
 EFI_STATUS
 EFIAPI
-EfiGetSystemConfigurationTable (  
+EfiGetSystemConfigurationTable (
   IN  EFI_GUID  *TableGuid,
   OUT VOID      **Table
   );
@@ -146,7 +145,7 @@ EfiGetSystemConfigurationTable (
   no instances of ProtocolGuid in the handle database at the time this function is invoked,
   then the notification function is still executed one time. In addition, every time a protocol
   of type ProtocolGuid instance is installed or reinstalled, the notification function is also
-  executed. This function returns the notification event that was created. 
+  executed. This function returns the notification event that was created.
   If ProtocolGuid is NULL, then ASSERT().
   If NotifyTpl is not a legal TPL value, then ASSERT().
   If NotifyFunction is NULL, then ASSERT().
@@ -159,7 +158,7 @@ EfiGetSystemConfigurationTable (
   @param  NotifyContext   The context parameter to pass to NotifyFunction.
   @param  Registration    A pointer to a memory location to receive the registration value.
                           This value is passed to LocateHandle() to obtain new handles that
-                          have been added that support the ProtocolGuid-specified protocol. 
+                          have been added that support the ProtocolGuid-specified protocol.
 
   @return The notification event that was created.
 
@@ -179,7 +178,7 @@ EfiCreateProtocolNotifyEvent(
 
   This function creates an event using NotifyTpl, NoifyFunction, and NotifyContext.
   This event is signaled with EfiNamedEventSignal(). This provides the ability for one or more
-  listeners on the same event named by the GUID specified by Name. 
+  listeners on the same event named by the GUID specified by Name.
   If Name is NULL, then ASSERT().
   If NotifyTpl is not a legal TPL value, then ASSERT().
   If NotifyFunction is NULL, then ASSERT().
@@ -187,7 +186,7 @@ EfiCreateProtocolNotifyEvent(
   @param  Name                  Supplies GUID name of the event.
   @param  NotifyTpl             Supplies the task priority level of the event notifications.
   @param  NotifyFunction        Supplies the function to notify when the event is signaled.
-  @param  NotifyContext         The context parameter to pass to NotifyFunction. 
+  @param  NotifyContext         The context parameter to pass to NotifyFunction.
   @param  Registration          A pointer to a memory location to receive the registration value.
 
   @retval EFI_SUCCESS           A named event was created.
@@ -257,13 +256,13 @@ EfiEventEmptyFunction (
   IN VOID                   *Context
   );
 
-/** 
+/**
   Returns the current TPL.
 
-  This function returns the current TPL.  There is no EFI service to directly 
-  retrieve the current TPL. Instead, the RaiseTPL() function is used to raise 
-  the TPL to TPL_HIGH_LEVEL.  This will return the current TPL.  The TPL level 
-  can then immediately be restored back to the current TPL level with a call 
+  This function returns the current TPL.  There is no EFI service to directly
+  retrieve the current TPL. Instead, the RaiseTPL() function is used to raise
+  the TPL to TPL_HIGH_LEVEL.  This will return the current TPL.  The TPL level
+  can then immediately be restored back to the current TPL level with a call
   to RestoreTPL().
 
   @return The current TPL.
@@ -278,8 +277,8 @@ EfiGetCurrentTpl (
 /**
   Initializes a basic mutual exclusion lock.
 
-  This function initializes a basic mutual exclusion lock to the released state 
-  and returns the lock.  Each lock provides mutual exclusion access at its task 
+  This function initializes a basic mutual exclusion lock to the released state
+  and returns the lock.  Each lock provides mutual exclusion access at its task
   priority level.  Since there is no preemption or multiprocessor support in EFI,
   acquiring the lock only consists of raising to the locks TPL.
   If Lock is NULL, then ASSERT().
@@ -301,8 +300,8 @@ EfiInitializeLock (
 /**
   Initializes a basic mutual exclusion lock.
 
-  This macro initializes the contents of a basic mutual exclusion lock to the 
-  released state.  Each lock provides mutual exclusion access at its task 
+  This macro initializes the contents of a basic mutual exclusion lock to the
+  released state.  Each lock provides mutual exclusion access at its task
   priority level.  Since there is no preemption or multiprocessor support in EFI,
   acquiring the lock only consists of raising to the locks TPL.
 
@@ -318,10 +317,10 @@ EfiInitializeLock (
 /**
   Macro that calls DebugAssert() if an EFI_LOCK structure is not in the locked state.
 
-  If MDEPKG_NDEBUG is not defined and the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED 
-  bit of PcdDebugProperyMask is set, then this macro evaluates the EFI_LOCK 
+  If MDEPKG_NDEBUG is not defined and the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED
+  bit of PcdDebugProperyMask is set, then this macro evaluates the EFI_LOCK
   structure specified by Lock.  If Lock is not in the locked state, then
-  DebugAssert() is called passing in the source filename, source line number, 
+  DebugAssert() is called passing in the source filename, source line number,
   and Lock.
 
   If Lock is NULL, then ASSERT().
@@ -329,7 +328,7 @@ EfiInitializeLock (
   @param  LockParameter  A pointer to the lock to acquire.
 
 **/
-#if !defined(MDEPKG_NDEBUG)       
+#if !defined(MDEPKG_NDEBUG)
   #define ASSERT_LOCKED(LockParameter)                  \
     do {                                                \
       if (DebugAssertEnabled ()) {                      \
@@ -347,8 +346,8 @@ EfiInitializeLock (
 /**
   Acquires ownership of a lock.
 
-  This function raises the system's current task priority level to the task 
-  priority level of the mutual exclusion lock.  Then, it places the lock in the 
+  This function raises the system's current task priority level to the task
+  priority level of the mutual exclusion lock.  Then, it places the lock in the
   acquired state.
   If Lock is NULL, then ASSERT().
   If Lock is not initialized, then ASSERT().
@@ -388,8 +387,8 @@ EfiAcquireLockOrFail (
 /**
   Releases ownership of a lock.
 
-  This function transitions a mutual exclusion lock from the acquired state to 
-  the released state, and restores the system's task priority level to its 
+  This function transitions a mutual exclusion lock from the acquired state to
+  the released state, and restores the system's task priority level to its
   previous level.
   If Lock is NULL, then ASSERT().
   If Lock is not initialized, then ASSERT().
@@ -411,7 +410,7 @@ EfiReleaseLock (
   currently managing the controller specified by ControllerHandle.  This test
   is performed by evaluating if the the protocol specified by ProtocolGuid is
   present on ControllerHandle and is was opened by DriverBindingHandle with an
-  attribute of EFI_OPEN_PROTOCOL_BY_DRIVER. 
+  attribute of EFI_OPEN_PROTOCOL_BY_DRIVER.
   If ProtocolGuid is NULL, then ASSERT().
 
   @param  ControllerHandle     A handle for a controller to test.
@@ -444,10 +443,10 @@ EfiTestManagedDevice (
   ChildHandle with an attribute of EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER.
   If ProtocolGuid is NULL, then ASSERT().
 
-  @param  ControllerHandle     A handle for a (parent) controller to test. 
+  @param  ControllerHandle     A handle for a (parent) controller to test.
   @param  ChildHandle          A child handle to test.
   @param  ProtocolGuid         Supplies the protocol that the child controller
-                               opens on its parent controller. 
+                               opens on its parent controller.
 
   @retval EFI_SUCCESS          ChildHandle is a child of the ControllerHandle.
   @retval EFI_UNSUPPORTED      ChildHandle is not a child of the
@@ -463,32 +462,50 @@ EfiTestChildHandle (
   );
 
 /**
+  This function checks the supported languages list for a target language,
+  This only supports RFC 4646 Languages.
+
+  @param  SupportedLanguages  The supported languages
+  @param  TargetLanguage      The target language
+
+  @retval Returns EFI_SUCCESS if the language is supported,
+          EFI_UNSUPPORTED otherwise
+
+**/
+EFI_STATUS
+EFIAPI
+IsLanguageSupported (
+  IN CONST CHAR8 *SupportedLanguages,
+  IN CONST CHAR8 *TargetLanguage
+  );
+
+/**
   This function looks up a Unicode string in UnicodeStringTable.
 
   If Language is a member of SupportedLanguages and a Unicode string is found in
   UnicodeStringTable that matches the language code specified by Language, then it
   is returned in UnicodeString.
 
-  @param  Language                A pointer to the ISO 639-2 language code for the 
+  @param  Language                A pointer to the ISO 639-2 language code for the
                                   Unicode string to look up and return.
-  @param  SupportedLanguages      A pointer to the set of ISO 639-2 language codes 
-                                  that the Unicode string table supports.  Language 
+  @param  SupportedLanguages      A pointer to the set of ISO 639-2 language codes
+                                  that the Unicode string table supports.  Language
                                   must be a member of this set.
   @param  UnicodeStringTable      A pointer to the table of Unicode strings.
   @param  UnicodeString           A pointer to the Unicode string from UnicodeStringTable
                                   that matches the language specified by Language.
 
-  @retval EFI_SUCCESS             The Unicode string that matches the language 
+  @retval EFI_SUCCESS             The Unicode string that matches the language
                                   specified by Language was found
-                                  in the table of Unicode strings UnicodeStringTable, 
+                                  in the table of Unicode strings UnicodeStringTable,
                                   and it was returned in UnicodeString.
   @retval EFI_INVALID_PARAMETER   Language is NULL.
   @retval EFI_INVALID_PARAMETER   UnicodeString is NULL.
   @retval EFI_UNSUPPORTED         SupportedLanguages is NULL.
   @retval EFI_UNSUPPORTED         UnicodeStringTable is NULL.
-  @retval EFI_UNSUPPORTED         The language specified by Language is not a 
+  @retval EFI_UNSUPPORTED         The language specified by Language is not a
                                   member of SupportedLanguages.
-  @retval EFI_UNSUPPORTED         The language specified by Language is not 
+  @retval EFI_UNSUPPORTED         The language specified by Language is not
                                   supported by UnicodeStringTable.
 
 **/
@@ -513,7 +530,7 @@ LookupUnicodeString (
                                return. If Iso639Language is TRUE, then this ASCII string is
                                not assumed to be Null-terminated, and only the first three
                                characters are used. If Iso639Language is FALSE, then this ASCII
-                               string must be Null-terminated. 
+                               string must be Null-terminated.
   @param  SupportedLanguages   A pointer to a Null-terminated ASCII string that contains a
                                set of ISO 639-2 or RFC 4646 language codes that the Unicode
                                string table supports.  Language must be a member of this set.
@@ -533,11 +550,11 @@ LookupUnicodeString (
   @retval  EFI_SUCCESS            The Unicode string that matches the language specified by Language
                                   was found in the table of Unicode strings UnicodeStringTable, and
                                   it was returned in UnicodeString.
-  @retval  EFI_INVALID_PARAMETER  Language is NULL.  
-  @retval  EFI_INVALID_PARAMETER  UnicodeString is NULL.  
-  @retval  EFI_UNSUPPORTED        SupportedLanguages is NULL.  
-  @retval  EFI_UNSUPPORTED        UnicodeStringTable is NULL.  
-  @retval  EFI_UNSUPPORTED        The language specified by Language is not a member of SupportedLanguages.  
+  @retval  EFI_INVALID_PARAMETER  Language is NULL.
+  @retval  EFI_INVALID_PARAMETER  UnicodeString is NULL.
+  @retval  EFI_UNSUPPORTED        SupportedLanguages is NULL.
+  @retval  EFI_UNSUPPORTED        UnicodeStringTable is NULL.
+  @retval  EFI_UNSUPPORTED        The language specified by Language is not a member of SupportedLanguages.
   @retval  EFI_UNSUPPORTED        The language specified by Language is not supported by UnicodeStringTable.
 
 **/
@@ -554,13 +571,13 @@ LookupUnicodeString2 (
 /**
   This function adds a Unicode string to UnicodeStringTable.
 
-  If Language is a member of SupportedLanguages then UnicodeString is added to 
-  UnicodeStringTable.  New buffers are allocated for both Language and 
-  UnicodeString.  The contents of Language and UnicodeString are copied into 
-  these new buffers.  These buffers are automatically freed when 
+  If Language is a member of SupportedLanguages then UnicodeString is added to
+  UnicodeStringTable.  New buffers are allocated for both Language and
+  UnicodeString.  The contents of Language and UnicodeString are copied into
+  these new buffers.  These buffers are automatically freed when
   FreeUnicodeStringTable() is called.
 
-  @param  Language                A pointer to the ISO 639-2 language code for the Unicode 
+  @param  Language                A pointer to the ISO 639-2 language code for the Unicode
                                   string to add.
   @param  SupportedLanguages      A pointer to the set of ISO 639-2 language codes
                                   that the Unicode string table supports.
@@ -568,29 +585,29 @@ LookupUnicodeString2 (
   @param  UnicodeStringTable      A pointer to the table of Unicode strings.
   @param  UnicodeString           A pointer to the Unicode string to add.
 
-  @retval EFI_SUCCESS             The Unicode string that matches the language 
-                                  specified by Language was found in the table of 
-                                  Unicode strings UnicodeStringTable, and it was 
+  @retval EFI_SUCCESS             The Unicode string that matches the language
+                                  specified by Language was found in the table of
+                                  Unicode strings UnicodeStringTable, and it was
                                   returned in UnicodeString.
   @retval EFI_INVALID_PARAMETER   Language is NULL.
   @retval EFI_INVALID_PARAMETER   UnicodeString is NULL.
   @retval EFI_INVALID_PARAMETER   UnicodeString is an empty string.
   @retval EFI_UNSUPPORTED         SupportedLanguages is NULL.
-  @retval EFI_ALREADY_STARTED     A Unicode string with language Language is 
+  @retval EFI_ALREADY_STARTED     A Unicode string with language Language is
                                   already present in UnicodeStringTable.
-  @retval EFI_OUT_OF_RESOURCES    There is not enough memory to add another 
+  @retval EFI_OUT_OF_RESOURCES    There is not enough memory to add another
                                   Unicode string to UnicodeStringTable.
-  @retval EFI_UNSUPPORTED         The language specified by Language is not a 
+  @retval EFI_UNSUPPORTED         The language specified by Language is not a
                                   member of SupportedLanguages.
 
 **/
 EFI_STATUS
 EFIAPI
 AddUnicodeString (
-  IN CONST CHAR8               *Language,
-  IN CONST CHAR8               *SupportedLanguages,
-  IN EFI_UNICODE_STRING_TABLE  **UnicodeStringTable,
-  IN CONST CHAR16              *UnicodeString
+  IN     CONST CHAR8               *Language,
+  IN     CONST CHAR8               *SupportedLanguages,
+  IN OUT EFI_UNICODE_STRING_TABLE  **UnicodeStringTable,
+  IN     CONST CHAR16              *UnicodeString
   );
 
 /**
@@ -617,39 +634,39 @@ AddUnicodeString (
                               RFC 4646 language codes separated by ';'.
   @param  UnicodeStringTable  A pointer to the table of Unicode strings. Type EFI_UNICODE_STRING_TABLE
                               is defined in "Related Definitions".
-  @param  UnicodeString       A pointer to the Unicode string to add.  
+  @param  UnicodeString       A pointer to the Unicode string to add.
   @param  Iso639Language      Specifies the supported language code format. If it is TRUE,
                               then Language and SupportedLanguages follow ISO 639-2 language code format.
                               Otherwise, they follow RFC 4646 language code format.
 
   @retval EFI_SUCCESS            The Unicode string that matches the language specified by
                                  Language was found in the table of Unicode strings UnicodeStringTable,
-                                 and it was returned in UnicodeString.  
-  @retval EFI_INVALID_PARAMETER  Language is NULL.  
-  @retval EFI_INVALID_PARAMETER  UnicodeString is NULL.  
-  @retval EFI_INVALID_PARAMETER  UnicodeString is an empty string.  
-  @retval EFI_UNSUPPORTED        SupportedLanguages is NULL.  
+                                 and it was returned in UnicodeString.
+  @retval EFI_INVALID_PARAMETER  Language is NULL.
+  @retval EFI_INVALID_PARAMETER  UnicodeString is NULL.
+  @retval EFI_INVALID_PARAMETER  UnicodeString is an empty string.
+  @retval EFI_UNSUPPORTED        SupportedLanguages is NULL.
   @retval EFI_ALREADY_STARTED    A Unicode string with language Language is already present in
-                                 UnicodeStringTable.  
-  @retval EFI_OUT_OF_RESOURCES   There is not enough memory to add another Unicode string UnicodeStringTable.  
+                                 UnicodeStringTable.
+  @retval EFI_OUT_OF_RESOURCES   There is not enough memory to add another Unicode string UnicodeStringTable.
   @retval EFI_UNSUPPORTED        The language specified by Language is not a member of SupportedLanguages.
 
 **/
 EFI_STATUS
 EFIAPI
 AddUnicodeString2 (
-  IN CONST CHAR8               *Language,
-  IN CONST CHAR8               *SupportedLanguages,
-  IN EFI_UNICODE_STRING_TABLE  **UnicodeStringTable,
-  IN CONST CHAR16              *UnicodeString,
-  IN BOOLEAN                   Iso639Language
+  IN     CONST CHAR8               *Language,
+  IN     CONST CHAR8               *SupportedLanguages,
+  IN OUT EFI_UNICODE_STRING_TABLE  **UnicodeStringTable,
+  IN     CONST CHAR16              *UnicodeString,
+  IN     BOOLEAN                   Iso639Language
   );
 
 /**
   This function frees the table of Unicode strings in UnicodeStringTable.
 
   If UnicodeStringTable is NULL, then EFI_SUCCESS is returned.
-  Otherwise, each language code, and each Unicode string in the Unicode string 
+  Otherwise, each language code, and each Unicode string in the Unicode string
   table are freed, and EFI_SUCCESS is returned.
 
   @param  UnicodeStringTable  A pointer to the table of Unicode strings.
@@ -668,8 +685,8 @@ FreeUnicodeStringTable (
 /**
   [ATTENTION] This function will be deprecated for security reason.
 
-  Returns a pointer to an allocated buffer that contains the contents of a 
-  variable retrieved through the UEFI Runtime Service GetVariable().  The 
+  Returns a pointer to an allocated buffer that contains the contents of a
+  variable retrieved through the UEFI Runtime Service GetVariable().  The
   returned buffer is allocated using AllocatePool().  The caller is responsible
   for freeing this buffer with FreePool().
 
@@ -694,10 +711,10 @@ GetVariable (
 /**
   [ATTENTION] This function will be deprecated for security reason.
 
-  Returns a pointer to an allocated buffer that contains the contents of a 
-  variable retrieved through the UEFI Runtime Service GetVariable().  This 
+  Returns a pointer to an allocated buffer that contains the contents of a
+  variable retrieved through the UEFI Runtime Service GetVariable().  This
   function always uses the EFI_GLOBAL_VARIABLE GUID to retrieve variables.
-  The returned buffer is allocated using AllocatePool().  The caller is 
+  The returned buffer is allocated using AllocatePool().  The caller is
   responsible for freeing this buffer with FreePool().
 
   If Name is NULL, then ASSERT().
@@ -718,8 +735,8 @@ GetEfiGlobalVariable (
 
 
 /**
-  Returns the status whether get the variable success. The function retrieves 
-  variable  through the UEFI Runtime Service GetVariable().  The 
+  Returns the status whether get the variable success. The function retrieves
+  variable  through the UEFI Runtime Service GetVariable().  The
   returned buffer is allocated using AllocatePool().  The caller is responsible
   for freeing this buffer with FreePool().
 
@@ -732,9 +749,9 @@ GetEfiGlobalVariable (
   @param[out] Value The buffer point saved the variable info.
   @param[out] Size  The buffer size of the variable.
 
-  @return EFI_OUT_OF_RESOURCES      Allocate buffer failed.
-  @return EFI_SUCCESS               Find the specified variable.
-  @return Others Errors             Return errors from call to gRT->GetVariable.
+  @retval EFI_OUT_OF_RESOURCES      Allocate buffer failed.
+  @retval EFI_SUCCESS               Find the specified variable.
+  @retval Others Errors             Return errors from call to gRT->GetVariable.
 
 **/
 EFI_STATUS
@@ -747,10 +764,10 @@ GetVariable2 (
   );
 
 /**
-  Returns a pointer to an allocated buffer that contains the contents of a 
-  variable retrieved through the UEFI Runtime Service GetVariable().  This 
+  Returns a pointer to an allocated buffer that contains the contents of a
+  variable retrieved through the UEFI Runtime Service GetVariable().  This
   function always uses the EFI_GLOBAL_VARIABLE GUID to retrieve variables.
-  The returned buffer is allocated using AllocatePool().  The caller is 
+  The returned buffer is allocated using AllocatePool().  The caller is
   responsible for freeing this buffer with FreePool().
 
   If Name  is NULL, then ASSERT().
@@ -760,9 +777,9 @@ GetVariable2 (
   @param[out] Value The buffer point saved the variable info.
   @param[out] Size  The buffer size of the variable.
 
-  @return EFI_OUT_OF_RESOURCES      Allocate buffer failed.
-  @return EFI_SUCCESS               Find the specified variable.
-  @return Others Errors             Return errors from call to gRT->GetVariable.
+  @retval EFI_OUT_OF_RESOURCES      Allocate buffer failed.
+  @retval EFI_SUCCESS               Find the specified variable.
+  @retval Others Errors             Return errors from call to gRT->GetVariable.
 
 **/
 EFI_STATUS
@@ -773,77 +790,110 @@ GetEfiGlobalVariable2 (
   OUT UINTN          *Size OPTIONAL
   );
 
+/** Return the attributes of the variable.
+
+  Returns the status whether get the variable success. The function retrieves
+  variable  through the UEFI Runtime Service GetVariable().  The
+  returned buffer is allocated using AllocatePool().  The caller is responsible
+  for freeing this buffer with FreePool().  The attributes are returned if
+  the caller provides a valid Attribute parameter.
+
+  If Name  is NULL, then ASSERT().
+  If Guid  is NULL, then ASSERT().
+  If Value is NULL, then ASSERT().
+
+  @param[in]  Name  The pointer to a Null-terminated Unicode string.
+  @param[in]  Guid  The pointer to an EFI_GUID structure
+  @param[out] Value The buffer point saved the variable info.
+  @param[out] Size  The buffer size of the variable.
+  @param[out] Attr  The pointer to the variable attributes as found in var store
+
+  @retval EFI_OUT_OF_RESOURCES      Allocate buffer failed.
+  @retval EFI_SUCCESS               Find the specified variable.
+  @retval Others Errors             Return errors from call to gRT->GetVariable.
+
+**/
+EFI_STATUS
+EFIAPI
+GetVariable3(
+  IN CONST CHAR16       *Name,
+  IN CONST EFI_GUID     *Guid,
+     OUT VOID           **Value,
+     OUT UINTN          *Size OPTIONAL,
+     OUT UINT32         *Attr OPTIONAL
+  );
+
 /**
-  Returns a pointer to an allocated buffer that contains the best matching language 
-  from a set of supported languages.  
-  
-  This function supports both ISO 639-2 and RFC 4646 language codes, but language 
-  code types may not be mixed in a single call to this function.  The language 
-  code returned is allocated using AllocatePool().  The caller is responsible for 
+  Returns a pointer to an allocated buffer that contains the best matching language
+  from a set of supported languages.
+
+  This function supports both ISO 639-2 and RFC 4646 language codes, but language
+  code types may not be mixed in a single call to this function.  The language
+  code returned is allocated using AllocatePool().  The caller is responsible for
   freeing the allocated buffer using FreePool().  This function supports a variable
-  argument list that allows the caller to pass in a prioritized list of language 
-  codes to test against all the language codes in SupportedLanguages. 
+  argument list that allows the caller to pass in a prioritized list of language
+  codes to test against all the language codes in SupportedLanguages.
 
   If SupportedLanguages is NULL, then ASSERT().
 
   @param[in]  SupportedLanguages  A pointer to a Null-terminated ASCII string that
-                                  contains a set of language codes in the format 
+                                  contains a set of language codes in the format
                                   specified by Iso639Language.
-  @param[in]  Iso639Language      If TRUE, then all language codes are assumed to be
-                                  in ISO 639-2 format.  If FALSE, then all language
+  @param[in]  Iso639Language      If not zero, then all language codes are assumed to be
+                                  in ISO 639-2 format.  If zero, then all language
                                   codes are assumed to be in RFC 4646 language format
-  @param[in]  ...                 A variable argument list that contains pointers to 
+  @param[in]  ...                 A variable argument list that contains pointers to
                                   Null-terminated ASCII strings that contain one or more
                                   language codes in the format specified by Iso639Language.
                                   The first language code from each of these language
                                   code lists is used to determine if it is an exact or
-                                  close match to any of the language codes in 
+                                  close match to any of the language codes in
                                   SupportedLanguages.  Close matches only apply to RFC 4646
                                   language codes, and the matching algorithm from RFC 4647
-                                  is used to determine if a close match is present.  If 
+                                  is used to determine if a close match is present.  If
                                   an exact or close match is found, then the matching
                                   language code from SupportedLanguages is returned.  If
                                   no matches are found, then the next variable argument
-                                  parameter is evaluated.  The variable argument list 
+                                  parameter is evaluated.  The variable argument list
                                   is terminated by a NULL.
 
   @retval NULL   The best matching language could not be found in SupportedLanguages.
-  @retval NULL   There are not enough resources available to return the best matching 
+  @retval NULL   There are not enough resources available to return the best matching
                  language.
-  @retval Other  A pointer to a Null-terminated ASCII string that is the best matching 
+  @retval Other  A pointer to a Null-terminated ASCII string that is the best matching
                  language in SupportedLanguages.
 
 **/
 CHAR8 *
 EFIAPI
 GetBestLanguage (
-  IN CONST CHAR8  *SupportedLanguages, 
-  IN BOOLEAN      Iso639Language,
+  IN CONST CHAR8  *SupportedLanguages,
+  IN UINTN        Iso639Language,
   ...
   );
 
 /**
-  Draws a dialog box to the console output device specified by 
+  Draws a dialog box to the console output device specified by
   ConOut defined in the EFI_SYSTEM_TABLE and waits for a keystroke
-  from the console input device specified by ConIn defined in the 
+  from the console input device specified by ConIn defined in the
   EFI_SYSTEM_TABLE.
 
   If there are no strings in the variable argument list, then ASSERT().
   If all the strings in the variable argument list are empty, then ASSERT().
 
   @param[in]   Attribute  Specifies the foreground and background color of the popup.
-  @param[out]  Key        A pointer to the EFI_KEY value of the key that was 
+  @param[out]  Key        A pointer to the EFI_KEY value of the key that was
                           pressed.  This is an optional parameter that may be NULL.
                           If it is NULL then no wait for a keypress will be performed.
   @param[in]  ...         The variable argument list that contains pointers to Null-
-                          terminated Unicode strings to display in the dialog box.  
+                          terminated Unicode strings to display in the dialog box.
                           The variable argument list is terminated by a NULL.
 
 **/
 VOID
 EFIAPI
 CreatePopUp (
-  IN  UINTN          Attribute,                
+  IN  UINTN          Attribute,
   OUT EFI_INPUT_KEY  *Key,      OPTIONAL
   ...
   );
@@ -875,13 +925,13 @@ GetGlyphWidth (
   of the Unicode characters in String can not be determined, then 0 is returned. The display
   width of String can be computed by summing the display widths of each Unicode character
   in String.  Unicode characters that are narrow glyphs have a width of 1, and Unicode
-  characters that are width glyphs have a width of 2. 
+  characters that are width glyphs have a width of 2.
   If String is not aligned on a 16-bit boundary, then ASSERT().
 
   @param  String      A pointer to a Null-terminated Unicode string.
 
   @return The display length of the Null-terminated Unicode string specified by String.
-  
+
 **/
 UINTN
 EFIAPI
@@ -894,7 +944,7 @@ UnicodeStringDisplayLength (
 //
 /**
   Create, Signal, and Close the Ready to Boot event using EfiSignalEventReadyToBoot().
-  
+
   This function abstracts the signaling of the Ready to Boot Event. The Framework moved
   from a proprietary to UEFI 2.0 based mechanism. This library abstracts the caller
   from how this event is created to prevent to code form having to change with the
@@ -947,8 +997,8 @@ EfiCreateEventLegacyBoot (
 
 /**
   Create an EFI event in the Legacy Boot Event Group and allows
-  the caller to specify a notification function.  
-  
+  the caller to specify a notification function.
+
   This function abstracts the creation of the Legacy Boot Event.
   The Framework moved from a proprietary to UEFI 2.0 based mechanism.
   This library abstracts the caller from how this event is created to prevent
@@ -977,10 +1027,10 @@ EfiCreateEventLegacyBootEx (
   Create an EFI event in the Ready To Boot Event Group.
 
   Prior to UEFI 2.0 this was done via a non-standard UEFI extension, and this library
-  abstracts the implementation mechanism of this event from the caller.   
-  This function abstracts the creation of the Ready to Boot Event.  The Framework 
-  moved from a proprietary to UEFI 2.0-based mechanism.  This library abstracts 
-  the caller from how this event is created to prevent the code form having to 
+  abstracts the implementation mechanism of this event from the caller.
+  This function abstracts the creation of the Ready to Boot Event.  The Framework
+  moved from a proprietary to UEFI 2.0-based mechanism.  This library abstracts
+  the caller from how this event is created to prevent the code form having to
   change with the version of the specification supported.
   If ReadyToBootEvent is NULL, then ASSERT().
 
@@ -998,8 +1048,8 @@ EfiCreateEventReadyToBoot (
 
 /**
   Create an EFI event in the Ready To Boot Event Group and allows
-  the caller to specify a notification function.  
-  
+  the caller to specify a notification function.
+
   This function abstracts the creation of the Ready to Boot Event.
   The Framework moved from a proprietary to UEFI 2.0 based mechanism.
   This library abstracts the caller from how this event is created to prevent
@@ -1026,16 +1076,16 @@ EfiCreateEventReadyToBootEx (
 
 /**
   Initialize a Firmware Volume (FV) Media Device Path node.
-  
-  The Framework FwVol Device Path changed to conform to the UEFI 2.0 specification.  
-  This library function abstracts initializing a device path node.  
-  Initialize the MEDIA_FW_VOL_FILEPATH_DEVICE_PATH data structure.  This device 
-  path changed in the DXE CIS version 0.92 in a non back ward compatible way to 
-  not conflict with the UEFI 2.0 specification.  This function abstracts the 
+
+  The Framework FwVol Device Path changed to conform to the UEFI 2.0 specification.
+  This library function abstracts initializing a device path node.
+  Initialize the MEDIA_FW_VOL_FILEPATH_DEVICE_PATH data structure.  This device
+  path changed in the DXE CIS version 0.92 in a non back ward compatible way to
+  not conflict with the UEFI 2.0 specification.  This function abstracts the
   differences from the caller.
   If FvDevicePathNode is NULL, then ASSERT().
   If NameGuid is NULL, then ASSERT().
-  
+
   @param  FvDevicePathNode  The pointer to a FV device path node to initialize
   @param  NameGuid          FV file name to use in FvDevicePathNode
 
@@ -1048,14 +1098,14 @@ EfiInitializeFwVolDevicepathNode (
   );
 
 /**
-  Check to see if the Firmware Volume (FV) Media Device Path is valid 
-  
-  The Framework FwVol Device Path changed to conform to the UEFI 2.0 specification.  
+  Check to see if the Firmware Volume (FV) Media Device Path is valid
+
+  The Framework FwVol Device Path changed to conform to the UEFI 2.0 specification.
   This library function abstracts validating a device path node.
-  Check the MEDIA_FW_VOL_FILEPATH_DEVICE_PATH data structure to see if it's valid.  
-  If it is valid, then return the GUID file name from the device path node.  Otherwise, 
-  return NULL.  This device path changed in the DXE CIS version 0.92 in a non backward 
-  compatible way to not conflict with the UEFI 2.0 specification.  This function abstracts 
+  Check the MEDIA_FW_VOL_FILEPATH_DEVICE_PATH data structure to see if it's valid.
+  If it is valid, then return the GUID file name from the device path node.  Otherwise,
+  return NULL.  This device path changed in the DXE CIS version 0.92 in a non backward
+  compatible way to not conflict with the UEFI 2.0 specification.  This function abstracts
   the differences from the caller.
   If FvDevicePathNode is NULL, then ASSERT().
 
@@ -1071,23 +1121,23 @@ EfiGetNameGuidFromFwVolDevicePathNode (
   IN CONST MEDIA_FW_VOL_FILEPATH_DEVICE_PATH  *FvDevicePathNode
   );
 
-/** 
-  Prints a formatted Unicode string to the console output device specified by 
+/**
+  Prints a formatted Unicode string to the console output device specified by
   ConOut defined in the EFI_SYSTEM_TABLE.
 
-  This function prints a formatted Unicode string to the console output device 
-  specified by ConOut in EFI_SYSTEM_TABLE and returns the number of Unicode 
-  characters that printed to ConOut.  If the length of the formatted Unicode 
-  string is greater than PcdUefiLibMaxPrintBufferSize, then only the first 
+  This function prints a formatted Unicode string to the console output device
+  specified by ConOut in EFI_SYSTEM_TABLE and returns the number of Unicode
+  characters that printed to ConOut.  If the length of the formatted Unicode
+  string is greater than PcdUefiLibMaxPrintBufferSize, then only the first
   PcdUefiLibMaxPrintBufferSize characters are sent to ConOut.
   If Format is NULL, then ASSERT().
   If Format is not aligned on a 16-bit boundary, then ASSERT().
   If gST->ConOut is NULL, then ASSERT().
 
   @param Format   A null-terminated Unicode format string.
-  @param ...      The variable argument list whose contents are accessed based 
+  @param ...      The variable argument list whose contents are accessed based
                   on the format string specified by Format.
-  
+
   @return Number of Unicode characters printed to ConOut.
 
 **/
@@ -1098,23 +1148,23 @@ Print (
   ...
   );
 
-/** 
-  Prints a formatted Unicode string to the console output device specified by 
+/**
+  Prints a formatted Unicode string to the console output device specified by
   StdErr defined in the EFI_SYSTEM_TABLE.
 
-  This function prints a formatted Unicode string to the console output device 
-  specified by StdErr in EFI_SYSTEM_TABLE and returns the number of Unicode 
-  characters that printed to StdErr.  If the length of the formatted Unicode 
-  string is greater than PcdUefiLibMaxPrintBufferSize, then only the first 
+  This function prints a formatted Unicode string to the console output device
+  specified by StdErr in EFI_SYSTEM_TABLE and returns the number of Unicode
+  characters that printed to StdErr.  If the length of the formatted Unicode
+  string is greater than PcdUefiLibMaxPrintBufferSize, then only the first
   PcdUefiLibMaxPrintBufferSize characters are sent to StdErr.
   If Format is NULL, then ASSERT().
   If Format is not aligned on a 16-bit boundary, then ASSERT().
   If gST->StdErr is NULL, then ASSERT().
 
   @param Format   A null-terminated Unicode format string.
-  @param ...      The variable argument list whose contents are accessed based 
+  @param ...      The variable argument list whose contents are accessed based
                   on the format string specified by Format.
-  
+
   @return Number of Unicode characters printed to StdErr.
 
 **/
@@ -1125,22 +1175,22 @@ ErrorPrint (
   ...
   );
 
-/** 
-  Prints a formatted ASCII string to the console output device specified by 
+/**
+  Prints a formatted ASCII string to the console output device specified by
   ConOut defined in the EFI_SYSTEM_TABLE.
 
-  This function prints a formatted ASCII string to the console output device 
-  specified by ConOut in EFI_SYSTEM_TABLE and returns the number of ASCII 
-  characters that printed to ConOut.  If the length of the formatted ASCII 
-  string is greater than PcdUefiLibMaxPrintBufferSize, then only the first 
+  This function prints a formatted ASCII string to the console output device
+  specified by ConOut in EFI_SYSTEM_TABLE and returns the number of ASCII
+  characters that printed to ConOut.  If the length of the formatted ASCII
+  string is greater than PcdUefiLibMaxPrintBufferSize, then only the first
   PcdUefiLibMaxPrintBufferSize characters are sent to ConOut.
   If Format is NULL, then ASSERT().
   If gST->ConOut is NULL, then ASSERT().
 
   @param Format   A null-terminated ASCII format string.
-  @param ...      The variable argument list whose contents are accessed based 
+  @param ...      The variable argument list whose contents are accessed based
                   on the format string specified by Format.
-  
+
   @return Number of ASCII characters printed to ConOut.
 
 **/
@@ -1151,22 +1201,22 @@ AsciiPrint (
   ...
   );
 
-/** 
-  Prints a formatted ASCII string to the console output device specified by 
+/**
+  Prints a formatted ASCII string to the console output device specified by
   StdErr defined in the EFI_SYSTEM_TABLE.
 
-  This function prints a formatted ASCII string to the console output device 
-  specified by StdErr in EFI_SYSTEM_TABLE and returns the number of ASCII 
-  characters that printed to StdErr.  If the length of the formatted ASCII 
-  string is greater than PcdUefiLibMaxPrintBufferSize, then only the first 
+  This function prints a formatted ASCII string to the console output device
+  specified by StdErr in EFI_SYSTEM_TABLE and returns the number of ASCII
+  characters that printed to StdErr.  If the length of the formatted ASCII
+  string is greater than PcdUefiLibMaxPrintBufferSize, then only the first
   PcdUefiLibMaxPrintBufferSize characters are sent to StdErr.
   If Format is NULL, then ASSERT().
   If gST->StdErr is NULL, then ASSERT().
 
   @param Format   A null-terminated ASCII format string.
-  @param ...      The variable argument list whose contents are accessed based 
+  @param ...      The variable argument list whose contents are accessed based
                   on the format string specified by Format.
-  
+
   @return Number of ASCII characters printed to ConErr.
 
 **/
@@ -1179,22 +1229,22 @@ AsciiErrorPrint (
 
 
 /**
-  Prints a formatted Unicode string to a graphics console device specified by 
+  Prints a formatted Unicode string to a graphics console device specified by
   ConsoleOutputHandle defined in the EFI_SYSTEM_TABLE at the given (X,Y) coordinates.
 
-  This function prints a formatted Unicode string to the graphics console device 
-  specified by ConsoleOutputHandle in EFI_SYSTEM_TABLE and returns the number of 
-  Unicode characters displayed, not including partial characters that may be clipped 
+  This function prints a formatted Unicode string to the graphics console device
+  specified by ConsoleOutputHandle in EFI_SYSTEM_TABLE and returns the number of
+  Unicode characters displayed, not including partial characters that may be clipped
   by the right edge of the display.  If the length of the formatted Unicode string is
-  greater than PcdUefiLibMaxPrintBufferSize, then at most the first 
+  greater than PcdUefiLibMaxPrintBufferSize, then at most the first
   PcdUefiLibMaxPrintBufferSize characters are printed.  The EFI_HII_FONT_PROTOCOL
-  is used to convert the string to a bitmap using the glyphs registered with the 
+  is used to convert the string to a bitmap using the glyphs registered with the
   HII database.  No wrapping is performed, so any portions of the string the fall
   outside the active display region will not be displayed.
 
-  If a graphics console device is not associated with the ConsoleOutputHandle 
+  If a graphics console device is not associated with the ConsoleOutputHandle
   defined in the EFI_SYSTEM_TABLE then no string is printed, and 0 is returned.
-  If the EFI_HII_FONT_PROTOCOL is not present in the handle database, then no 
+  If the EFI_HII_FONT_PROTOCOL is not present in the handle database, then no
   string is printed, and 0 is returned.
   If Format is NULL, then ASSERT().
   If Format is not aligned on a 16-bit boundary, then ASSERT().
@@ -1207,13 +1257,13 @@ AsciiErrorPrint (
                        then the foreground color of the current ConOut device
                        in the EFI_SYSTEM_TABLE is used.
   @param  BackGround   The background color of the string being printed.  This is
-                       an optional parameter that may be NULL.  If it is NULL, 
+                       an optional parameter that may be NULL.  If it is NULL,
                        then the background color of the current ConOut device
                        in the EFI_SYSTEM_TABLE is used.
-  @param  Format       A null-terminated Unicode format string.  See Print Library 
+  @param  Format       A null-terminated Unicode format string.  See Print Library
                        for the supported format string syntax.
-  @param  ...          Variable argument list whose contents are accessed based on 
-                       the format string specified by Format.         
+  @param  ...          Variable argument list whose contents are accessed based on
+                       the format string specified by Format.
 
   @return  The number of Unicode characters printed.
 
@@ -1230,22 +1280,22 @@ PrintXY (
   );
 
 /**
-  Prints a formatted ASCII string to a graphics console device specified by 
+  Prints a formatted ASCII string to a graphics console device specified by
   ConsoleOutputHandle defined in the EFI_SYSTEM_TABLE at the given (X,Y) coordinates.
 
-  This function prints a formatted ASCII string to the graphics console device 
-  specified by ConsoleOutputHandle in EFI_SYSTEM_TABLE and returns the number of 
-  ASCII characters displayed, not including partial characters that may be clipped 
+  This function prints a formatted ASCII string to the graphics console device
+  specified by ConsoleOutputHandle in EFI_SYSTEM_TABLE and returns the number of
+  ASCII characters displayed, not including partial characters that may be clipped
   by the right edge of the display.  If the length of the formatted ASCII string is
-  greater than PcdUefiLibMaxPrintBufferSize, then at most the first 
+  greater than PcdUefiLibMaxPrintBufferSize, then at most the first
   PcdUefiLibMaxPrintBufferSize characters are printed.  The EFI_HII_FONT_PROTOCOL
-  is used to convert the string to a bitmap using the glyphs registered with the 
+  is used to convert the string to a bitmap using the glyphs registered with the
   HII database.  No wrapping is performed, so any portions of the string the fall
   outside the active display region will not be displayed.
 
-  If a graphics console device is not associated with the ConsoleOutputHandle 
+  If a graphics console device is not associated with the ConsoleOutputHandle
   defined in the EFI_SYSTEM_TABLE then no string is printed, and 0 is returned.
-  If the EFI_HII_FONT_PROTOCOL is not present in the handle database, then no 
+  If the EFI_HII_FONT_PROTOCOL is not present in the handle database, then no
   string is printed, and 0 is returned.
   If Format is NULL, then ASSERT().
   If gST->ConsoleOutputHandle is NULL, then ASSERT().
@@ -1257,13 +1307,13 @@ PrintXY (
                        then the foreground color of the current ConOut device
                        in the EFI_SYSTEM_TABLE is used.
   @param  BackGround   The background color of the string being printed.  This is
-                       an optional parameter that may be NULL.  If it is NULL, 
+                       an optional parameter that may be NULL.  If it is NULL,
                        then the background color of the current ConOut device
                        in the EFI_SYSTEM_TABLE is used.
-  @param  Format       A null-terminated ASCII format string.  See Print Library 
+  @param  Format       A null-terminated ASCII format string.  See Print Library
                        for the supported format string syntax.
-  @param  ...          The variable argument list whose contents are accessed based on 
-                       the format string specified by Format.         
+  @param  ...          The variable argument list whose contents are accessed based on
+                       the format string specified by Format.
 
   @return  The number of ASCII characters printed.
 
@@ -1279,15 +1329,16 @@ AsciiPrintXY (
   ...
   );
 
+
 /**
   Installs and completes the initialization of a Driver Binding Protocol instance.
-  
+
   Installs the Driver Binding Protocol specified by DriverBinding onto the handle
   specified by DriverBindingHandle. If DriverBindingHandle is NULL, then DriverBinding
   is installed onto a newly created handle. DriverBindingHandle is typically the same
   as the driver's ImageHandle, but it can be different if the driver produces multiple
-  Driver Binding Protocols. 
-  If DriverBinding is NULL, then ASSERT(). 
+  Driver Binding Protocols.
+  If DriverBinding is NULL, then ASSERT().
   If DriverBinding can not be installed onto a handle, then ASSERT().
 
   @param  ImageHandle          The image handle of the driver.
@@ -1312,6 +1363,25 @@ EfiLibInstallDriverBinding (
 
 
 /**
+  Uninstalls a Driver Binding Protocol instance.
+
+  If DriverBinding is NULL, then ASSERT().
+  If DriverBinding can not be uninstalled, then ASSERT().
+
+  @param  DriverBinding        A Driver Binding Protocol instance that this driver produced.
+
+  @retval EFI_SUCCESS           The protocol uninstallation successfully completed.
+  @retval Others                Status from gBS->UninstallMultipleProtocolInterfaces().
+
+**/
+EFI_STATUS
+EFIAPI
+EfiLibUninstallDriverBinding (
+  IN EFI_DRIVER_BINDING_PROTOCOL  *DriverBinding
+  );
+
+
+/**
   Installs and completes the initialization of a Driver Binding Protocol instance and
   optionally installs the Component Name, Driver Configuration and Driver Diagnostics Protocols.
 
@@ -1320,10 +1390,10 @@ EfiLibInstallDriverBinding (
   Protocols onto the driver's DriverBindingHandle. If DriverBindingHandle is NULL,
   then the protocols are installed onto a newly created handle. DriverBindingHandle
   is typically the same as the driver's ImageHandle, but it can be different if the
-  driver produces multiple Driver Binding Protocols. 
-  If DriverBinding is NULL, then ASSERT(). 
+  driver produces multiple Driver Binding Protocols.
+  If DriverBinding is NULL, then ASSERT().
   If the installation fails, then ASSERT().
-  
+
   @param  ImageHandle          The image handle of the driver.
   @param  SystemTable          The EFI System Table that was passed to the driver's entry point.
   @param  DriverBinding        A Driver Binding Protocol instance that this driver is producing.
@@ -1350,6 +1420,31 @@ EfiLibInstallAllDriverProtocols (
   );
 
 
+/**
+  Uninstalls a Driver Binding Protocol instance and optionally uninstalls the
+  Component Name, Driver Configuration and Driver Diagnostics Protocols.
+
+  If DriverBinding is NULL, then ASSERT().
+  If the uninstallation fails, then ASSERT().
+
+  @param  DriverBinding        A Driver Binding Protocol instance that this driver produced.
+  @param  ComponentName        A Component Name Protocol instance that this driver produced.
+  @param  DriverConfiguration  A Driver Configuration Protocol instance that this driver produced.
+  @param  DriverDiagnostics    A Driver Diagnostics Protocol instance that this driver produced.
+
+  @retval EFI_SUCCESS           The protocol uninstallation successfully completed.
+  @retval Others                Status from gBS->UninstallMultipleProtocolInterfaces().
+
+**/
+EFI_STATUS
+EFIAPI
+EfiLibUninstallAllDriverProtocols (
+  IN EFI_DRIVER_BINDING_PROTOCOL              *DriverBinding,
+  IN CONST EFI_COMPONENT_NAME_PROTOCOL        *ComponentName,       OPTIONAL
+  IN CONST EFI_DRIVER_CONFIGURATION_PROTOCOL  *DriverConfiguration, OPTIONAL
+  IN CONST EFI_DRIVER_DIAGNOSTICS_PROTOCOL    *DriverDiagnostics    OPTIONAL
+  );
+
 
 /**
   Installs Driver Binding Protocol with optional Component Name and Component Name 2 Protocols.
@@ -1358,8 +1453,8 @@ EfiLibInstallAllDriverProtocols (
   optional Component Name and optional Component Name 2 protocols onto the driver's
   DriverBindingHandle.  If DriverBindingHandle is NULL, then the protocols are installed
   onto a newly created handle.  DriverBindingHandle is typically the same as the driver's
-  ImageHandle, but it can be different if the driver produces multiple Driver Binding Protocols. 
-  If DriverBinding is NULL, then ASSERT(). 
+  ImageHandle, but it can be different if the driver produces multiple Driver Binding Protocols.
+  If DriverBinding is NULL, then ASSERT().
   If the installation fails, then ASSERT().
 
   @param  ImageHandle          The image handle of the driver.
@@ -1387,6 +1482,29 @@ EfiLibInstallDriverBindingComponentName2 (
 
 
 /**
+  Uninstalls Driver Binding Protocol with optional Component Name and Component Name 2 Protocols.
+
+  If DriverBinding is NULL, then ASSERT().
+  If the uninstallation fails, then ASSERT().
+
+  @param  DriverBinding        A Driver Binding Protocol instance that this driver produced.
+  @param  ComponentName        A Component Name Protocol instance that this driver produced.
+  @param  ComponentName2       A Component Name 2 Protocol instance that this driver produced.
+
+  @retval EFI_SUCCESS           The protocol installation successfully completed.
+  @retval Others                Status from gBS->UninstallMultipleProtocolInterfaces().
+
+**/
+EFI_STATUS
+EFIAPI
+EfiLibUninstallDriverBindingComponentName2 (
+  IN EFI_DRIVER_BINDING_PROTOCOL              *DriverBinding,
+  IN CONST EFI_COMPONENT_NAME_PROTOCOL        *ComponentName,       OPTIONAL
+  IN CONST EFI_COMPONENT_NAME2_PROTOCOL       *ComponentName2       OPTIONAL
+  );
+
+
+/**
   Installs Driver Binding Protocol with optional Component Name, Component Name 2, Driver
   Configuration, Driver Configuration 2, Driver Diagnostics, and Driver Diagnostics 2 Protocols.
 
@@ -1394,8 +1512,8 @@ EfiLibInstallDriverBindingComponentName2 (
   Component Name, optional Component Name 2, optional Driver Configuration, optional Driver Configuration 2,
   optional Driver Diagnostic, and optional Driver Diagnostic 2 Protocols onto the driver's DriverBindingHandle.
   DriverBindingHandle is typically the same as the driver's ImageHandle, but it can be different if the driver
-  produces multiple Driver Binding Protocols. 
-  If DriverBinding is NULL, then ASSERT(). 
+  produces multiple Driver Binding Protocols.
+  If DriverBinding is NULL, then ASSERT().
   If the installation fails, then ASSERT().
 
 
@@ -1430,25 +1548,59 @@ EfiLibInstallAllDriverProtocols2 (
   IN CONST EFI_DRIVER_DIAGNOSTICS2_PROTOCOL   *DriverDiagnostics2    OPTIONAL
   );
 
-/** 
+
+/**
+  Uninstalls Driver Binding Protocol with optional Component Name, Component Name 2, Driver
+  Configuration, Driver Configuration 2, Driver Diagnostics, and Driver Diagnostics 2 Protocols.
+
+  If DriverBinding is NULL, then ASSERT().
+  If the installation fails, then ASSERT().
+
+
+  @param  DriverBinding         A Driver Binding Protocol instance that this driver produced.
+  @param  ComponentName         A Component Name Protocol instance that this driver produced.
+  @param  ComponentName2        A Component Name 2 Protocol instance that this driver produced.
+  @param  DriverConfiguration   A Driver Configuration Protocol instance that this driver produced.
+  @param  DriverConfiguration2  A Driver Configuration Protocol 2 instance that this driver produced.
+  @param  DriverDiagnostics     A Driver Diagnostics Protocol instance that this driver produced.
+  @param  DriverDiagnostics2    A Driver Diagnostics Protocol 2 instance that this driver produced.
+
+  @retval EFI_SUCCESS           The protocol uninstallation successfully completed.
+  @retval Others                Status from gBS->UninstallMultipleProtocolInterfaces().
+
+**/
+EFI_STATUS
+EFIAPI
+EfiLibUninstallAllDriverProtocols2 (
+  IN EFI_DRIVER_BINDING_PROTOCOL              *DriverBinding,
+  IN CONST EFI_COMPONENT_NAME_PROTOCOL        *ComponentName,        OPTIONAL
+  IN CONST EFI_COMPONENT_NAME2_PROTOCOL       *ComponentName2,       OPTIONAL
+  IN CONST EFI_DRIVER_CONFIGURATION_PROTOCOL  *DriverConfiguration,  OPTIONAL
+  IN CONST EFI_DRIVER_CONFIGURATION2_PROTOCOL *DriverConfiguration2, OPTIONAL
+  IN CONST EFI_DRIVER_DIAGNOSTICS_PROTOCOL    *DriverDiagnostics,    OPTIONAL
+  IN CONST EFI_DRIVER_DIAGNOSTICS2_PROTOCOL   *DriverDiagnostics2    OPTIONAL
+  );
+
+
+/**
   Appends a formatted Unicode string to a Null-terminated Unicode string
- 
-  This function appends a formatted Unicode string to the Null-terminated 
+
+  This function appends a formatted Unicode string to the Null-terminated
   Unicode string specified by String.   String is optional and may be NULL.
-  Storage for the formatted Unicode string returned is allocated using 
+  Storage for the formatted Unicode string returned is allocated using
   AllocatePool().  The pointer to the appended string is returned.  The caller
   is responsible for freeing the returned string.
- 
+
   If String is not NULL and not aligned on a 16-bit boundary, then ASSERT().
   If FormatString is NULL, then ASSERT().
   If FormatString is not aligned on a 16-bit boundary, then ASSERT().
- 
+
   @param[in] String         A Null-terminated Unicode string.
   @param[in] FormatString   A Null-terminated Unicode format string.
   @param[in]  Marker        VA_LIST marker for the variable argument list.
 
   @retval NULL    There was not enough available memory.
-  @return         Null-terminated Unicode string is that is the formatted 
+  @return         Null-terminated Unicode string is that is the formatted
                   string appended to String.
 **/
 CHAR16*
@@ -1459,27 +1611,27 @@ CatVSPrint (
   IN  VA_LIST       Marker
   );
 
-/** 
+/**
   Appends a formatted Unicode string to a Null-terminated Unicode string
- 
-  This function appends a formatted Unicode string to the Null-terminated 
+
+  This function appends a formatted Unicode string to the Null-terminated
   Unicode string specified by String.   String is optional and may be NULL.
-  Storage for the formatted Unicode string returned is allocated using 
+  Storage for the formatted Unicode string returned is allocated using
   AllocatePool().  The pointer to the appended string is returned.  The caller
   is responsible for freeing the returned string.
- 
+
   If String is not NULL and not aligned on a 16-bit boundary, then ASSERT().
   If FormatString is NULL, then ASSERT().
   If FormatString is not aligned on a 16-bit boundary, then ASSERT().
- 
+
   @param[in] String         A Null-terminated Unicode string.
   @param[in] FormatString   A Null-terminated Unicode format string.
-  @param[in] ...            The variable argument list whose contents are 
-                            accessed based on the format string specified by 
+  @param[in] ...            The variable argument list whose contents are
+                            accessed based on the format string specified by
                             FormatString.
 
   @retval NULL    There was not enough available memory.
-  @return         Null-terminated Unicode string is that is the formatted 
+  @return         Null-terminated Unicode string is that is the formatted
                   string appended to String.
 **/
 CHAR16 *
@@ -1490,4 +1642,173 @@ CatSPrint (
   ...
   );
 
+/**
+  Returns an array of protocol instance that matches the given protocol.
+
+  @param[in]  Protocol      Provides the protocol to search for.
+  @param[out] NoProtocols   The number of protocols returned in Buffer.
+  @param[out] Buffer        A pointer to the buffer to return the requested
+                            array of protocol instances that match Protocol.
+                            The returned buffer is allocated using
+                            EFI_BOOT_SERVICES.AllocatePool().  The caller is
+                            responsible for freeing this buffer with
+                            EFI_BOOT_SERVICES.FreePool().
+
+  @retval EFI_SUCCESS            The array of protocols was returned in Buffer,
+                                 and the number of protocols in Buffer was
+                                 returned in NoProtocols.
+  @retval EFI_NOT_FOUND          No protocols found.
+  @retval EFI_OUT_OF_RESOURCES   There is not enough pool memory to store the
+                                 matching results.
+  @retval EFI_INVALID_PARAMETER  Protocol is NULL.
+  @retval EFI_INVALID_PARAMETER  NoProtocols is NULL.
+  @retval EFI_INVALID_PARAMETER  Buffer is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+EfiLocateProtocolBuffer (
+  IN  EFI_GUID  *Protocol,
+  OUT UINTN     *NoProtocols,
+  OUT VOID      ***Buffer
+  );
+
+/**
+  Open or create a file or directory, possibly creating the chain of
+  directories leading up to the directory.
+
+  EfiOpenFileByDevicePath() first locates EFI_SIMPLE_FILE_SYSTEM_PROTOCOL on
+  FilePath, and opens the root directory of that filesystem with
+  EFI_SIMPLE_FILE_SYSTEM_PROTOCOL.OpenVolume().
+
+  On the remaining device path, the longest initial sequence of
+  FILEPATH_DEVICE_PATH nodes is node-wise traversed with
+  EFI_FILE_PROTOCOL.Open().
+
+  (As a consequence, if OpenMode includes EFI_FILE_MODE_CREATE, and Attributes
+  includes EFI_FILE_DIRECTORY, and each FILEPATH_DEVICE_PATH specifies a single
+  pathname component, then EfiOpenFileByDevicePath() ensures that the specified
+  series of subdirectories exist on return.)
+
+  The EFI_FILE_PROTOCOL identified by the last FILEPATH_DEVICE_PATH node is
+  output to the caller; intermediate EFI_FILE_PROTOCOL instances are closed. If
+  there are no FILEPATH_DEVICE_PATH nodes past the node that identifies the
+  filesystem, then the EFI_FILE_PROTOCOL of the root directory of the
+  filesystem is output to the caller. If a device path node that is different
+  from FILEPATH_DEVICE_PATH is encountered relative to the filesystem, the
+  traversal is stopped with an error, and a NULL EFI_FILE_PROTOCOL is output.
+
+  @param[in,out] FilePath  On input, the device path to the file or directory
+                           to open or create. The caller is responsible for
+                           ensuring that the device path pointed-to by FilePath
+                           is well-formed. On output, FilePath points one past
+                           the last node in the original device path that has
+                           been successfully processed. FilePath is set on
+                           output even if EfiOpenFileByDevicePath() returns an
+                           error.
+
+  @param[out] File         On error, File is set to NULL. On success, File is
+                           set to the EFI_FILE_PROTOCOL of the root directory
+                           of the filesystem, if there are no
+                           FILEPATH_DEVICE_PATH nodes in FilePath; otherwise,
+                           File is set to the EFI_FILE_PROTOCOL identified by
+                           the last node in FilePath.
+
+  @param[in] OpenMode      The OpenMode parameter to pass to
+                           EFI_FILE_PROTOCOL.Open().
+
+  @param[in] Attributes    The Attributes parameter to pass to
+                           EFI_FILE_PROTOCOL.Open().
+
+  @retval EFI_SUCCESS            The file or directory has been opened or
+                                 created.
+
+  @retval EFI_INVALID_PARAMETER  FilePath is NULL; or File is NULL; or FilePath
+                                 contains a device path node, past the node
+                                 that identifies
+                                 EFI_SIMPLE_FILE_SYSTEM_PROTOCOL, that is not a
+                                 FILEPATH_DEVICE_PATH node.
+
+  @retval EFI_OUT_OF_RESOURCES   Memory allocation failed.
+
+  @return                        Error codes propagated from the
+                                 LocateDevicePath() and OpenProtocol() boot
+                                 services, and from the
+                                 EFI_SIMPLE_FILE_SYSTEM_PROTOCOL.OpenVolume()
+                                 and EFI_FILE_PROTOCOL.Open() member functions.
+**/
+EFI_STATUS
+EFIAPI
+EfiOpenFileByDevicePath (
+  IN OUT EFI_DEVICE_PATH_PROTOCOL  **FilePath,
+  OUT    EFI_FILE_PROTOCOL         **File,
+  IN     UINT64                    OpenMode,
+  IN     UINT64                    Attributes
+  );
+
+/**
+  This function locates next ACPI table in XSDT/RSDT based on Signature and
+  previous returned Table.
+
+  If PreviousTable is NULL:
+  This function will locate the first ACPI table in XSDT/RSDT based on
+  Signature in gEfiAcpi20TableGuid system configuration table first, and then
+  gEfiAcpi10TableGuid system configuration table.
+  This function will locate in XSDT first, and then RSDT.
+  For DSDT, this function will locate XDsdt in FADT first, and then Dsdt in
+  FADT.
+  For FACS, this function will locate XFirmwareCtrl in FADT first, and then
+  FirmwareCtrl in FADT.
+
+  If PreviousTable is not NULL:
+  1. If it could be located in XSDT in gEfiAcpi20TableGuid system configuration
+     table, then this function will just locate next table in XSDT in
+     gEfiAcpi20TableGuid system configuration table.
+  2. If it could be located in RSDT in gEfiAcpi20TableGuid system configuration
+     table, then this function will just locate next table in RSDT in
+     gEfiAcpi20TableGuid system configuration table.
+  3. If it could be located in RSDT in gEfiAcpi10TableGuid system configuration
+     table, then this function will just locate next table in RSDT in
+     gEfiAcpi10TableGuid system configuration table.
+
+  It's not supported that PreviousTable is not NULL but PreviousTable->Signature
+  is not same with Signature, NULL will be returned.
+
+  @param Signature          ACPI table signature.
+  @param PreviousTable      Pointer to previous returned table to locate next
+                            table, or NULL to locate first table.
+
+  @return Next ACPI table or NULL if not found.
+
+**/
+EFI_ACPI_COMMON_HEADER *
+EFIAPI
+EfiLocateNextAcpiTable (
+  IN UINT32                     Signature,
+  IN EFI_ACPI_COMMON_HEADER     *PreviousTable OPTIONAL
+  );
+
+/**
+  This function locates first ACPI table in XSDT/RSDT based on Signature.
+
+  This function will locate the first ACPI table in XSDT/RSDT based on
+  Signature in gEfiAcpi20TableGuid system configuration table first, and then
+  gEfiAcpi10TableGuid system configuration table.
+  This function will locate in XSDT first, and then RSDT.
+  For DSDT, this function will locate XDsdt in FADT first, and then Dsdt in
+  FADT.
+  For FACS, this function will locate XFirmwareCtrl in FADT first, and then
+  FirmwareCtrl in FADT.
+
+  @param Signature          ACPI table signature.
+
+  @return First ACPI table or NULL if not found.
+
+**/
+EFI_ACPI_COMMON_HEADER *
+EFIAPI
+EfiLocateFirstAcpiTable (
+  IN UINT32                     Signature
+  );
+
 #endif
diff --git a/MdePkg/Include/Library/UefiRuntimeLib.h b/MdePkg/Include/Library/UefiRuntimeLib.h
index 03d7fb768f20..dd2576bb7d5c 100644
--- a/MdePkg/Include/Library/UefiRuntimeLib.h
+++ b/MdePkg/Include/Library/UefiRuntimeLib.h
@@ -2,14 +2,8 @@
   Provides library functions for each of the UEFI Runtime Services.
   Only available to DXE and UEFI module types.
 
-Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
 #ifndef __UEFI_RUNTIME_LIB__
@@ -34,7 +28,7 @@ EfiAtRuntime (
   );
 
 /**
-  This function allows the caller to determine if UEFI SetVirtualAddressMap() has been called. 
+  This function allows the caller to determine if UEFI SetVirtualAddressMap() has been called.
 
   This function returns TRUE after all the EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE functions have
   executed as a result of the OS calling SetVirtualAddressMap(). Prior to this time FALSE
@@ -329,9 +323,8 @@ EfiGetNextHighMonotonicCount (
                       Null-terminated Unicode string, optionally followed by additional binary data. The string is a
                       description that the caller may use to further indicate the reason for the system reset. ResetData
                       is only valid if ResetStatus is something other then EFI_SUCCESS. This pointer must be a physical
-                      address. For a ResetType of EfiRestUpdate the data buffer also starts with a Null-terminated string
-                      that is followed by a physical VOID * to an EFI_CAPSULE_HEADER.
-
+                      address. For a ResetType of EfiResetPlatformSpecific the data buffer also starts with a Null-terminated
+                      string that is followed by an EFI_GUID that describes the specific type of reset to perform.
 **/
 VOID
 EFIAPI
@@ -343,7 +336,7 @@ EfiResetSystem (
   );
 
 /**
-  This service is a wrapper for the UEFI Runtime Service ConvertPointer().  
+  This service is a wrapper for the UEFI Runtime Service ConvertPointer().
 
   The ConvertPointer() function is used by an EFI component during the SetVirtualAddressMap() operation.
   ConvertPointer()must be called using physical address pointers during the execution of SetVirtualAddressMap().
@@ -371,7 +364,7 @@ EfiConvertPointer (
   Determines the new virtual address that is to be used on subsequent memory accesses.
 
   For IA32, x64, and EBC, this service is a wrapper for the UEFI Runtime Service
-  ConvertPointer().  See the UEFI Specification for details. 
+  ConvertPointer().  See the UEFI Specification for details.
   For IPF, this function interprets Address as a pointer to an EFI_PLABEL structure
   and both the EntryPoint and GP fields of an EFI_PLABEL are converted from physical
   to virtiual addressing.  Since IPF allows the GP to point to an address outside
diff --git a/MdePkg/Include/Library/UefiRuntimeServicesTableLib.h b/MdePkg/Include/Library/UefiRuntimeServicesTableLib.h
index 609f2abeea72..daacc2a9e712 100644
--- a/MdePkg/Include/Library/UefiRuntimeServicesTableLib.h
+++ b/MdePkg/Include/Library/UefiRuntimeServicesTableLib.h
@@ -11,13 +11,7 @@
   Only available to DXE and UEFI module types.
 
 Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/Library/UefiScsiLib.h b/MdePkg/Include/Library/UefiScsiLib.h
index 5257f765845b..d35ee6b097d8 100644
--- a/MdePkg/Include/Library/UefiScsiLib.h
+++ b/MdePkg/Include/Library/UefiScsiLib.h
@@ -5,14 +5,8 @@
   for hard drive, CD and DVD devices that are the most common SCSI boot targets used by UEFI platforms.
   This library class depends on SCSI I/O Protocol defined in UEFI Specification and SCSI-2 industry standard.
 
-Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials                          
-are licensed and made available under the terms and conditions of the BSD License         
-which accompanies this distribution.  The full text of the license may be found at        
-http://opensource.org/licenses/bsd-license.php                                            
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -52,7 +46,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
                                     optional and may be NULL.
   @param[in, out] SenseDataLength   On input, a pointer to the length in bytes of
                                     the SenseData buffer. On output, a pointer to
-                                    the number of bytes written to the SenseData buffer. 
+                                    the number of bytes written to the SenseData buffer.
   @param[out]     HostAdapterStatus The status of the SCSI Host Controller that produces
                                     the SCSI bus containing the SCSI target specified by
                                     ScsiIo when the SCSI Request Packet was executed.
@@ -62,7 +56,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
                                     by ScsiIo when the SCSI Request Packet was executed
                                     on the SCSI Host Controller. See the EFI SCSI I/O
                                     Protocol in the UEFI Specification for details on
-                                    the possible return values. 
+                                    the possible return values.
 
   @retval EFI_SUCCESS               The command was executed successfully.
                                     See HostAdapterStatus, TargetStatus, SenseDataLength,
@@ -135,7 +129,7 @@ ScsiTestUnitReadyCommand (
                                          If SenseDataLength is 0, then this parameter
                                          is optional and may be NULL.
   @param[in, out] SenseDataLength        On input, the length in bytes of the SenseData buffer.
-                                         On output, the number of bytes written to the SenseData buffer. 
+                                         On output, the number of bytes written to the SenseData buffer.
   @param[out]     HostAdapterStatus      The status of the SCSI Host Controller that
                                          produces the SCSI bus containing the SCSI
                                          target specified by ScsiIo when the SCSI
@@ -147,12 +141,12 @@ ScsiTestUnitReadyCommand (
                                          executed on the SCSI Host Controller.
                                          See the EFI SCSI I/O Protocol in the UEFI
                                          Specification for details on the possible
-                                         return values. 
+                                         return values.
   @param[in, out] InquiryDataBuffer      A pointer to inquiry data that was generated
                                          by the execution of the SCSI Request Packet.
                                          This buffer must be allocated by the caller.
                                          If InquiryDataLength is 0, then this parameter
-                                         is optional and may be NULL. 
+                                         is optional and may be NULL.
   @param[in, out] InquiryDataLength      On input, a pointer to the length in bytes
                                          of the InquiryDataBuffer buffer.
                                          On output, a pointer to the number of bytes
@@ -160,7 +154,7 @@ ScsiTestUnitReadyCommand (
   @param[in]      EnableVitalProductData If TRUE, then the supported vital product
                                          data is returned in InquiryDataBuffer.
                                          If FALSE, then the standard inquiry data is
-                                         returned in InquiryDataBuffer. 
+                                         returned in InquiryDataBuffer.
 
   @retval EFI_SUCCESS                    The command was executed successfully. See HostAdapterStatus,
                                          TargetStatus, SenseDataLength, and SenseData in that order
@@ -237,7 +231,7 @@ ScsiInquiryCommand (
                                          If SenseDataLength is 0, then this parameter
                                          is optional and may be NULL.
   @param[in, out] SenseDataLength        On input, the length in bytes of the SenseData buffer.
-                                         On output, the number of bytes written to the SenseData buffer. 
+                                         On output, the number of bytes written to the SenseData buffer.
   @param[out]     HostAdapterStatus      The status of the SCSI Host Controller that
                                          produces the SCSI bus containing the SCSI
                                          target specified by ScsiIo when the SCSI
@@ -249,12 +243,12 @@ ScsiInquiryCommand (
                                          executed on the SCSI Host Controller.
                                          See the EFI SCSI I/O Protocol in the UEFI
                                          Specification for details on the possible
-                                         return values. 
+                                         return values.
   @param[in, out] InquiryDataBuffer      A pointer to inquiry data that was generated
                                          by the execution of the SCSI Request Packet.
                                          This buffer must be allocated by the caller.
                                          If InquiryDataLength is 0, then this parameter
-                                         is optional and may be NULL. 
+                                         is optional and may be NULL.
   @param[in, out] InquiryDataLength      On input, a pointer to the length in bytes
                                          of the InquiryDataBuffer buffer.
                                          On output, a pointer to the number of bytes
@@ -344,7 +338,7 @@ ScsiInquiryCommandEx (
                                      If SenseDataLength is 0, then this parameter
                                      is optional and may be NULL.
   @param[in, out]  SenseDataLength   On input, the length in bytes of the SenseData buffer.
-                                     On output, the number of bytes written to the SenseData buffer. 
+                                     On output, the number of bytes written to the SenseData buffer.
   @param[out]     HostAdapterStatus  The status of the SCSI Host Controller that
                                      produces the SCSI bus containing the SCSI target
                                      specified by ScsiIo when the SCSI Request Packet
@@ -360,14 +354,14 @@ ScsiInquiryCommandEx (
                                      execution of the SCSI Request Packet.  This
                                      buffer must be allocated by the caller. If
                                      DataLength is 0, then this parameter is optional
-                                     and may be NULL. 
+                                     and may be NULL.
   @param[in, out]  DataLength        On input, a pointer to the length in bytes of
                                      the DataBuffer buffer.  On output, a pointer
                                      to the number of bytes written to the DataBuffer
-                                     buffer. 
+                                     buffer.
   @param[in]      DBDField           Specifies the DBD field of the CDB for this SCSI Command.
-  @param[in]      PageControl        Specifies the PC field of the CDB for this SCSI Command. 
-  @param[in]      PageCode           Specifies the Page Control field of the CDB for this SCSI Command. 
+  @param[in]      PageControl        Specifies the PC field of the CDB for this SCSI Command.
+  @param[in]      PageCode           Specifies the Page Control field of the CDB for this SCSI Command.
 
   @retval EFI_SUCCESS                The command was executed successfully.
                                      See HostAdapterStatus, TargetStatus, SenseDataLength,
@@ -820,6 +814,134 @@ ScsiWrite16Command (
 
 
 /**
+  Execute Security Protocol In SCSI command on a specific SCSI target.
+
+  Executes the SCSI Security Protocol In command on the SCSI target specified by ScsiIo.
+  If Timeout is zero, then this function waits indefinitely for the command to complete.
+  If Timeout is greater than zero, then the command is executed and will timeout after
+  Timeout 100 ns units.
+  If ScsiIo is NULL, then ASSERT().
+  If SenseDataLength is NULL, then ASSERT().
+  If HostAdapterStatus is NULL, then ASSERT().
+  If TargetStatus is NULL, then ASSERT().
+  If TransferLength is NULL, then ASSERT().
+
+  If SenseDataLength is non-zero and SenseData is not NULL, SenseData must meet buffer
+  alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER
+  gets returned.
+
+  If DataLength is non-zero and DataBuffer is not NULL, DataBuffer must meet buffer
+  alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER
+  gets returned.
+
+  @param[in]      ScsiIo                    SCSI IO Protocol to use.
+  @param[in]      Timeout                   The length of timeout period.
+  @param[in, out] SenseData                 A pointer to output sense data.
+  @param[in, out] SenseDataLength           The length of output sense data.
+  @param[out]     HostAdapterStatus         The status of Host Adapter.
+  @param[out]     TargetStatus              The status of the target.
+  @param[in]      SecurityProtocol          The Security Protocol to use.
+  @param[in]      SecurityProtocolSpecific  The Security Protocol Specific data.
+  @param[in]      Inc512                    If TRUE, 512 increment (INC_512) bit will be set for the
+                                            SECURITY PROTOCOL IN command.
+  @param[in]      DataLength                The size in bytes of the data buffer.
+  @param[in, out] DataBuffer                A pointer to a data buffer.
+  @param[out]     TransferLength            A pointer to a buffer to store the size in
+                                            bytes of the data written to the data buffer.
+
+  @retval  EFI_SUCCESS                 Command is executed successfully.
+  @retval  EFI_BAD_BUFFER_SIZE         The SCSI Request Packet was executed, but the entire DataBuffer could
+                                       not be transferred. The actual number of bytes transferred is returned in TransferLength.
+  @retval  EFI_NOT_READY               The SCSI Request Packet could not be sent because there are too many
+                                       SCSI Command Packets already queued.
+  @retval  EFI_DEVICE_ERROR            A device error occurred while attempting to send SCSI Request Packet.
+  @retval  EFI_UNSUPPORTED             The command described by the SCSI Request Packet is not supported by
+                                       the SCSI initiator(i.e., SCSI  Host Controller)
+  @retval  EFI_TIMEOUT                 A timeout occurred while waiting for the SCSI Request Packet to execute.
+  @retval  EFI_INVALID_PARAMETER       The contents of the SCSI Request Packet are invalid.
+
+**/
+EFI_STATUS
+EFIAPI
+ScsiSecurityProtocolInCommand (
+  IN     EFI_SCSI_IO_PROTOCOL  *ScsiIo,
+  IN     UINT64                Timeout,
+  IN OUT VOID                  *SenseData,   OPTIONAL
+  IN OUT UINT8                 *SenseDataLength,
+     OUT UINT8                 *HostAdapterStatus,
+     OUT UINT8                 *TargetStatus,
+  IN     UINT8                 SecurityProtocol,
+  IN     UINT16                SecurityProtocolSpecific,
+  IN     BOOLEAN               Inc512,
+  IN     UINTN                 DataLength,
+  IN OUT VOID                  *DataBuffer,  OPTIONAL
+     OUT UINTN                 *TransferLength
+  );
+
+
+/**
+  Execute Security Protocol Out SCSI command on a specific SCSI target.
+
+  Executes the SCSI Security Protocol Out command on the SCSI target specified by ScsiIo.
+  If Timeout is zero, then this function waits indefinitely for the command to complete.
+  If Timeout is greater than zero, then the command is executed and will timeout after
+  Timeout 100 ns units.
+  If ScsiIo is NULL, then ASSERT().
+  If SenseDataLength is NULL, then ASSERT().
+  If HostAdapterStatus is NULL, then ASSERT().
+  If TargetStatus is NULL, then ASSERT().
+
+  If SenseDataLength is non-zero and SenseData is not NULL, SenseData must meet buffer
+  alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER
+  gets returned.
+
+  If DataLength is non-zero and DataBuffer is not NULL, DataBuffer must meet buffer
+  alignment requirement defined in EFI_SCSI_IO_PROTOCOL. Otherwise EFI_INVALID_PARAMETER
+  gets returned.
+
+  @param[in]      ScsiIo                    SCSI IO Protocol to use.
+  @param[in]      Timeout                   The length of timeout period.
+  @param[in, out] SenseData                 A pointer to output sense data.
+  @param[in, out] SenseDataLength           The length of output sense data.
+  @param[out]     HostAdapterStatus         The status of Host Adapter.
+  @param[out]     TargetStatus              The status of the target.
+  @param[in]      SecurityProtocol          The Security Protocol to use.
+  @param[in]      SecurityProtocolSpecific  The Security Protocol Specific data.
+  @param[in]      Inc512                    If TRUE, 512 increment (INC_512) bit will be set for the
+                                            SECURITY PROTOCOL OUT command.
+  @param[in]      DataLength                The size in bytes of the transfer data.
+  @param[in, out] DataBuffer                A pointer to a data buffer.
+
+  @retval  EFI_SUCCESS                 Command is executed successfully.
+  @retval  EFI_BAD_BUFFER_SIZE         The SCSI Request Packet was executed, but the entire DataBuffer could
+                                       not be transferred. The actual number of bytes transferred is returned in DataLength.
+  @retval  EFI_NOT_READY               The SCSI Request Packet could not be sent because there are too many
+                                       SCSI Command Packets already queued.
+  @retval  EFI_DEVICE_ERROR            A device error occurred while attempting to send SCSI Request Packet.
+  @retval  EFI_UNSUPPORTED             The command described by the SCSI Request Packet is not supported by
+                                       the SCSI initiator(i.e., SCSI  Host Controller)
+  @retval  EFI_TIMEOUT                 A timeout occurred while waiting for the SCSI Request Packet to execute.
+  @retval  EFI_INVALID_PARAMETER       The contents of the SCSI Request Packet are invalid.
+
+**/
+EFI_STATUS
+EFIAPI
+ScsiSecurityProtocolOutCommand (
+  IN     EFI_SCSI_IO_PROTOCOL  *ScsiIo,
+  IN     UINT64                Timeout,
+  IN OUT VOID                  *SenseData,   OPTIONAL
+  IN OUT UINT8                 *SenseDataLength,
+     OUT UINT8                 *HostAdapterStatus,
+     OUT UINT8                 *TargetStatus,
+  IN     UINT8                 SecurityProtocol,
+  IN     UINT16                SecurityProtocolSpecific,
+  IN     BOOLEAN               Inc512,
+  IN     UINTN                 DataLength,
+  IN OUT VOID                  *DataBuffer   OPTIONAL
+  );
+
+
+/**
   Execute blocking/non-blocking Read(10) SCSI command on a specific SCSI
   target.
 
diff --git a/MdePkg/Include/Library/UefiUsbLib.h b/MdePkg/Include/Library/UefiUsbLib.h
index a2eab6961125..256c060ea7c3 100644
--- a/MdePkg/Include/Library/UefiUsbLib.h
+++ b/MdePkg/Include/Library/UefiUsbLib.h
@@ -3,13 +3,7 @@
   and the standard requests defined in USB 1.1 spec.
 
 Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/Library/UnitTestLib.h b/MdePkg/Include/Library/UnitTestLib.h
new file mode 100644
index 000000000000..b176a9556335
--- /dev/null
+++ b/MdePkg/Include/Library/UnitTestLib.h
@@ -0,0 +1,757 @@
+/** @file
+  Provides a unit test framework.  This allows tests to focus on testing logic
+  and the framework to focus on runnings, reporting, statistics, etc.
+
+  Copyright (c) Microsoft Corporation.<BR>
+  Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __UNIT_TEST_LIB_H__
+#define __UNIT_TEST_LIB_H__
+
+///
+/// Unit Test Status
+///
+typedef UINT32  UNIT_TEST_STATUS;
+#define UNIT_TEST_PASSED                      (0)
+#define UNIT_TEST_ERROR_PREREQUISITE_NOT_MET  (1)
+#define UNIT_TEST_ERROR_TEST_FAILED           (2)
+#define UNIT_TEST_ERROR_CLEANUP_FAILED        (3)
+#define UNIT_TEST_SKIPPED                     (0xFFFFFFFD)
+#define UNIT_TEST_RUNNING                     (0xFFFFFFFE)
+#define UNIT_TEST_PENDING                     (0xFFFFFFFF)
+
+///
+/// Declare PcdUnitTestLogLevel bits and UnitTestLog() ErrorLevel parameter.
+///
+#define UNIT_TEST_LOG_LEVEL_ERROR    BIT0
+#define UNIT_TEST_LOG_LEVEL_WARN     BIT1
+#define UNIT_TEST_LOG_LEVEL_INFO     BIT2
+#define UNIT_TEST_LOG_LEVEL_VERBOSE  BIT3
+
+///
+/// Unit Test Framework Handle
+///
+struct UNIT_TEST_FRAMEWORK_OBJECT;
+typedef struct UNIT_TEST_FRAMEWORK_OBJECT  *UNIT_TEST_FRAMEWORK_HANDLE;
+
+///
+/// Unit Test Suite Handle
+///
+struct UNIT_TEST_SUITE_OBJECT;
+typedef struct UNIT_TEST_SUITE_OBJECT  *UNIT_TEST_SUITE_HANDLE;
+
+///
+/// Unit Test Handle
+///
+struct UNIT_TEST_OBJECT;
+typedef struct UNIT_TEST_OBJECT  *UNIT_TEST_HANDLE;
+
+///
+/// Unit Test Context
+///
+typedef VOID*  UNIT_TEST_CONTEXT;
+
+/**
+  The prototype for a single UnitTest case function.
+
+  Functions with this prototype are registered to be dispatched by the
+  UnitTest framework, and results are recorded as test Pass or Fail.
+
+  @param[in]  Context    [Optional] An optional parameter that enables:
+                         1) test-case reuse with varied parameters and
+                         2) test-case re-entry for Target tests that need a
+                         reboot.  This parameter is a VOID* and it is the
+                         responsibility of the test author to ensure that the
+                         contents are well understood by all test cases that may
+                         consume it.
+
+  @retval  UNIT_TEST_PASSED             The Unit test has completed and the test
+                                        case was successful.
+  @retval  UNIT_TEST_ERROR_TEST_FAILED  A test case assertion has failed.
+
+**/
+typedef
+UNIT_TEST_STATUS
+(EFIAPI *UNIT_TEST_FUNCTION)(
+  IN UNIT_TEST_CONTEXT  Context
+  );
+
+/**
+  Unit-Test Prerequisite Function pointer type.
+
+  Functions with this prototype are registered to be dispatched by the unit test
+  framework prior to a given test case. If this prereq function returns
+  UNIT_TEST_ERROR_PREREQUISITE_NOT_MET, the test case will be skipped.
+
+  @param[in]  Context    [Optional] An optional parameter that enables:
+                         1) test-case reuse with varied parameters and
+                         2) test-case re-entry for Target tests that need a
+                         reboot.  This parameter is a VOID* and it is the
+                         responsibility of the test author to ensure that the
+                         contents are well understood by all test cases that may
+                         consume it.
+
+  @retval  UNIT_TEST_PASSED                      Unit test case prerequisites
+                                                 are met.
+  @retval  UNIT_TEST_ERROR_PREREQUISITE_NOT_MET  Test case should be skipped.
+
+**/
+typedef
+UNIT_TEST_STATUS
+(EFIAPI *UNIT_TEST_PREREQUISITE)(
+  IN UNIT_TEST_CONTEXT  Context
+  );
+
+/**
+  Unit-Test Cleanup (after) function pointer type.
+
+  Functions with this prototype are registered to be dispatched by the
+  unit test framework after a given test case. This will be called even if the
+  test case returns an error, but not if the prerequisite fails and the test is
+  skipped.  The purpose of this function is to clean up any global state or
+  test data.
+
+  @param[in]  Context    [Optional] An optional parameter that enables:
+                         1) test-case reuse with varied parameters and
+                         2) test-case re-entry for Target tests that need a
+                         reboot.  This parameter is a VOID* and it is the
+                         responsibility of the test author to ensure that the
+                         contents are well understood by all test cases that may
+                         consume it.
+
+  @retval  UNIT_TEST_PASSED                Test case cleanup succeeded.
+  @retval  UNIT_TEST_ERROR_CLEANUP_FAILED  Test case cleanup failed.
+
+**/
+typedef
+VOID
+(EFIAPI *UNIT_TEST_CLEANUP)(
+  IN UNIT_TEST_CONTEXT  Context
+  );
+
+/**
+  Unit-Test Test Suite Setup (before) function pointer type. Functions with this
+  prototype are registered to be dispatched by the UnitTest framework prior to
+  running any of the test cases in a test suite.  It will only be run once at
+  the beginning of the suite (not prior to each case).
+
+  The purpose of this function is to set up any global state or test data.
+**/
+typedef
+VOID
+(EFIAPI *UNIT_TEST_SUITE_SETUP)(
+  VOID
+  );
+
+/**
+  Unit-Test Test Suite Teardown (after) function pointer type.  Functions with
+  this prototype are registered to be dispatched by the UnitTest framework after
+  running all of the test cases in a test suite.  It will only be run once at
+  the end of the suite.
+
+  The purpose of this function is to clean up any global state or test data.
+**/
+typedef
+VOID
+(EFIAPI *UNIT_TEST_SUITE_TEARDOWN)(
+  VOID
+  );
+
+/**
+  Method to Initialize the Unit Test framework.  This function registers the
+  test name and also initializes the internal state of the test framework to
+  receive any new suites and tests.
+
+  @param[out]  FrameworkHandle  Unit test framework to be created.
+  @param[in]   Title            Null-terminated ASCII string that is the user
+                                friendly name of the framework. String is
+                                copied.
+  @param[in]   ShortTitle       Null-terminated ASCII short string that is the
+                                short name of the framework with no spaces.
+                                String is copied.
+  @param[in]   VersionString    Null-terminated ASCII version string for the
+                                framework. String is copied.
+
+  @retval  EFI_SUCCESS            The unit test framework was initialized.
+  @retval  EFI_INVALID_PARAMETER  FrameworkHandle is NULL.
+  @retval  EFI_INVALID_PARAMETER  Title is NULL.
+  @retval  EFI_INVALID_PARAMETER  ShortTitle is NULL.
+  @retval  EFI_INVALID_PARAMETER  VersionString is NULL.
+  @retval  EFI_INVALID_PARAMETER  ShortTitle is invalid.
+  @retval  EFI_OUT_OF_RESOURCES   There are not enough resources available to
+                                  initialize the unit test framework.
+**/
+EFI_STATUS
+EFIAPI
+InitUnitTestFramework (
+  OUT UNIT_TEST_FRAMEWORK_HANDLE  *FrameworkHandle,
+  IN  CHAR8                       *Title,
+  IN  CHAR8                       *ShortTitle,
+  IN  CHAR8                       *VersionString
+  );
+
+/**
+  Registers a Unit Test Suite in the Unit Test Framework.
+  At least one test suite must be registered, because all test cases must be
+  within a unit test suite.
+
+  @param[out]  SuiteHandle      Unit test suite to create
+  @param[in]   FrameworkHandle  Unit test framework to add unit test suite to
+  @param[in]   Title            Null-terminated ASCII string that is the user
+                                friendly name of the test suite.  String is
+                                copied.
+  @param[in]   Name             Null-terminated ASCII string that is the short
+                                name of the test suite with no spaces.  String
+                                is copied.
+  @param[in]   Setup            Setup function, runs before suite.  This is an
+                                optional parameter that may be NULL.
+  @param[in]   Teardown         Teardown function, runs after suite.  This is an
+                                optional parameter that may be NULL.
+
+  @retval  EFI_SUCCESS            The unit test suite was created.
+  @retval  EFI_INVALID_PARAMETER  SuiteHandle is NULL.
+  @retval  EFI_INVALID_PARAMETER  FrameworkHandle is NULL.
+  @retval  EFI_INVALID_PARAMETER  Title is NULL.
+  @retval  EFI_INVALID_PARAMETER  Name is NULL.
+  @retval  EFI_OUT_OF_RESOURCES   There are not enough resources available to
+                                  initialize the unit test suite.
+**/
+EFI_STATUS
+EFIAPI
+CreateUnitTestSuite (
+  OUT UNIT_TEST_SUITE_HANDLE      *SuiteHandle,
+  IN  UNIT_TEST_FRAMEWORK_HANDLE  FrameworkHandle,
+  IN  CHAR8                       *Title,
+  IN  CHAR8                       *Name,
+  IN  UNIT_TEST_SUITE_SETUP       Setup     OPTIONAL,
+  IN  UNIT_TEST_SUITE_TEARDOWN    Teardown  OPTIONAL
+  );
+
+/**
+  Adds test case to Suite
+
+  @param[in]  SuiteHandle   Unit test suite to add test to.
+  @param[in]  Description   Null-terminated ASCII string that is the user
+                            friendly description of a test.  String is copied.
+  @param[in]  Name          Null-terminated ASCII string that is the short name
+                            of the test with no spaces.  String is copied.
+  @param[in]  Function      Unit test function.
+  @param[in]  Prerequisite  Prerequisite function, runs before test.  This is
+                            an optional parameter that may be NULL.
+  @param[in]  CleanUp       Clean up function, runs after test.  This is an
+                            optional parameter that may be NULL.
+  @param[in]  Context       Pointer to context.    This is an optional parameter
+                            that may be NULL.
+
+  @retval  EFI_SUCCESS            The unit test case was added to Suite.
+  @retval  EFI_INVALID_PARAMETER  SuiteHandle is NULL.
+  @retval  EFI_INVALID_PARAMETER  Description is NULL.
+  @retval  EFI_INVALID_PARAMETER  Name is NULL.
+  @retval  EFI_INVALID_PARAMETER  Function is NULL.
+  @retval  EFI_OUT_OF_RESOURCES   There are not enough resources available to
+                                  add the unit test case to Suite.
+**/
+EFI_STATUS
+EFIAPI
+AddTestCase (
+  IN UNIT_TEST_SUITE_HANDLE  SuiteHandle,
+  IN CHAR8                   *Description,
+  IN CHAR8                   *Name,
+  IN UNIT_TEST_FUNCTION      Function,
+  IN UNIT_TEST_PREREQUISITE  Prerequisite  OPTIONAL,
+  IN UNIT_TEST_CLEANUP       CleanUp       OPTIONAL,
+  IN UNIT_TEST_CONTEXT       Context       OPTIONAL
+  );
+
+/**
+  Execute all unit test cases in all unit test suites added to a Framework.
+
+  Once a unit test framework is initialized and all unit test suites and unit
+  test cases are registered, this function will cause the unit test framework to
+  dispatch all unit test cases in sequence and record the results for reporting.
+
+  @param[in]  FrameworkHandle  A handle to the current running framework that
+                               dispatched the test.  Necessary for recording
+                               certain test events with the framework.
+
+  @retval  EFI_SUCCESS            All test cases were dispatched.
+  @retval  EFI_INVALID_PARAMETER  FrameworkHandle is NULL.
+**/
+EFI_STATUS
+EFIAPI
+RunAllTestSuites (
+  IN UNIT_TEST_FRAMEWORK_HANDLE  FrameworkHandle
+  );
+
+/**
+  Cleanup a test framework.
+
+  After tests are run, this will teardown the entire framework and free all
+  allocated data within.
+
+  @param[in]  FrameworkHandle  A handle to the current running framework that
+                               dispatched the test.  Necessary for recording
+                               certain test events with the framework.
+
+  @retval  EFI_SUCCESS            All resources associated with framework were
+                                  freed.
+  @retval  EFI_INVALID_PARAMETER  FrameworkHandle is NULL.
+**/
+EFI_STATUS
+EFIAPI
+FreeUnitTestFramework (
+  IN UNIT_TEST_FRAMEWORK_HANDLE  FrameworkHandle
+  );
+
+/**
+  Leverages a framework-specific mechanism (see UnitTestPersistenceLib if you're
+  a framework author) to save the state of the executing framework along with
+  any allocated data so that the test may be resumed upon reentry. A test case
+  should pass any needed context (which, to prevent an infinite loop, should be
+  at least the current execution count) which will be saved by the framework and
+  passed to the test case upon resume.
+
+  Generally called from within a test case prior to quitting or rebooting.
+
+  @param[in]  FrameworkHandle    A handle to the current running framework that
+                                 dispatched the test.  Necessary for recording
+                                 certain test events with the framework.
+  @param[in]  ContextToSave      A buffer of test case-specific data to be saved
+                                 along with framework state.  Will be passed as
+                                 "Context" to the test case upon resume.  This
+                                 is an optional parameter that may be NULL.
+  @param[in]  ContextToSaveSize  Size of the ContextToSave buffer.
+
+  @retval  EFI_SUCCESS            The framework state and context were saved.
+  @retval  EFI_INVALID_PARAMETER  FrameworkHandle is NULL.
+  @retval  EFI_INVALID_PARAMETER  ContextToSave is not NULL and
+                                  ContextToSaveSize is 0.
+  @retval  EFI_INVALID_PARAMETER  ContextToSave is >= 4GB.
+  @retval  EFI_OUT_OF_RESOURCES   There are not enough resources available to
+                                  save the framework and context state.
+  @retval  EFI_DEVICE_ERROR       The framework and context state could not be
+                                  saved to a persistent storage device due to a
+                                  device error.
+**/
+EFI_STATUS
+EFIAPI
+SaveFrameworkState (
+  IN UNIT_TEST_FRAMEWORK_HANDLE  FrameworkHandle,
+  IN UNIT_TEST_CONTEXT           ContextToSave     OPTIONAL,
+  IN UINTN                       ContextToSaveSize
+  );
+
+/**
+  This macro uses the framework assertion logic to check an expression for
+  "TRUE". If the expression evaluates to TRUE, execution continues.
+  Otherwise, the test case immediately returns UNIT_TEST_ERROR_TEST_FAILED.
+
+  @param[in]  Expression  Expression to be evaluated for TRUE.
+**/
+#define UT_ASSERT_TRUE(Expression)                                                        \
+  if(!UnitTestAssertTrue ((Expression), __FUNCTION__, __LINE__, __FILE__, #Expression)) { \
+    return UNIT_TEST_ERROR_TEST_FAILED;                                                   \
+  }
+
+/**
+  This macro uses the framework assertion logic to check an expression for
+  "FALSE". If the expression evaluates to FALSE, execution continues.
+  Otherwise, the test case immediately returns UNIT_TEST_ERROR_TEST_FAILED.
+
+  @param[in]  Expression  Expression to be evaluated for FALSE.
+**/
+#define UT_ASSERT_FALSE(Expression)                                                        \
+  if(!UnitTestAssertFalse ((Expression), __FUNCTION__, __LINE__, __FILE__, #Expression)) { \
+    return UNIT_TEST_ERROR_TEST_FAILED;                                                    \
+  }
+
+/**
+  This macro uses the framework assertion logic to check whether two simple
+  values are equal.  If the values are equal, execution continues.
+  Otherwise, the test case immediately returns UNIT_TEST_ERROR_TEST_FAILED.
+
+  @param[in]  ValueA  Value to be compared for equality (64-bit comparison).
+  @param[in]  ValueB  Value to be compared for equality (64-bit comparison).
+**/
+#define UT_ASSERT_EQUAL(ValueA, ValueB)                                                                           \
+  if(!UnitTestAssertEqual ((UINT64)(ValueA), (UINT64)(ValueB), __FUNCTION__, __LINE__, __FILE__, #ValueA, #ValueB)) { \
+    return UNIT_TEST_ERROR_TEST_FAILED;                                                                           \
+  }
+
+/**
+  This macro uses the framework assertion logic to check whether two memory
+  buffers are equal.  If the buffers are equal, execution continues.
+  Otherwise, the test case immediately returns UNIT_TEST_ERROR_TEST_FAILED.
+
+  @param[in]  BufferA  Pointer to a buffer for comparison.
+  @param[in]  BufferB  Pointer to a buffer for comparison.
+  @param[in]  Length   Number of bytes to compare in BufferA and BufferB.
+**/
+#define UT_ASSERT_MEM_EQUAL(BufferA, BufferB, Length)                                                                               \
+  if(!UnitTestAssertMemEqual ((VOID *)(UINTN)(BufferA), (VOID *)(UINTN)(BufferB), (UINTN)Length, __FUNCTION__, __LINE__, __FILE__, #BufferA, #BufferB)) { \
+    return UNIT_TEST_ERROR_TEST_FAILED;                                                                                           \
+  }
+
+/**
+  This macro uses the framework assertion logic to check whether two simple
+  values are non-equal.  If the values are non-equal, execution continues.
+  Otherwise, the test case immediately returns UNIT_TEST_ERROR_TEST_FAILED.
+
+  @param[in]  ValueA  Value to be compared for inequality (64-bit comparison).
+  @param[in]  ValueB  Value to be compared for inequality (64-bit comparison).
+**/
+#define UT_ASSERT_NOT_EQUAL(ValueA, ValueB)                                                                          \
+  if(!UnitTestAssertNotEqual ((UINT64)(ValueA), (UINT64)(ValueB), __FUNCTION__, __LINE__, __FILE__, #ValueA, #ValueB)) { \
+    return UNIT_TEST_ERROR_TEST_FAILED;                                                                              \
+  }
+
+/**
+  This macro uses the framework assertion logic to check whether an EFI_STATUS
+  value is !EFI_ERROR().  If the status is !EFI_ERROR(), execution continues.
+  Otherwise, the test case immediately returns UNIT_TEST_ERROR_TEST_FAILED.
+
+  @param[in]  Status  EFI_STATUS value to check.
+**/
+#define UT_ASSERT_NOT_EFI_ERROR(Status)                                                \
+  if(!UnitTestAssertNotEfiError ((Status), __FUNCTION__, __LINE__, __FILE__, #Status)) { \
+    return UNIT_TEST_ERROR_TEST_FAILED;                                                \
+  }
+
+/**
+  This macro uses the framework assertion logic to check whether two EFI_STATUS
+  values are equal.  If the values are equal, execution continues.
+  Otherwise, the test case immediately returns UNIT_TEST_ERROR_TEST_FAILED.
+
+  @param[in]  Status    EFI_STATUS values to compare for equality.
+  @param[in]  Expected  EFI_STATUS values to compare for equality.
+**/
+#define UT_ASSERT_STATUS_EQUAL(Status, Expected)                                                 \
+  if(!UnitTestAssertStatusEqual ((Status), (Expected), __FUNCTION__, __LINE__, __FILE__, #Status)) { \
+    return UNIT_TEST_ERROR_TEST_FAILED;                                                          \
+  }
+
+/**
+  This macro uses the framework assertion logic to check whether a pointer is
+  not NULL.  If the pointer is not NULL, execution continues. Otherwise, the
+  test case immediately returns UNIT_TEST_ERROR_TEST_FAILED.
+
+  @param[in]  Pointer  Pointer to be checked against NULL.
+**/
+#define UT_ASSERT_NOT_NULL(Pointer)                                                  \
+  if(!UnitTestAssertNotNull ((Pointer), __FUNCTION__, __LINE__, __FILE__, #Pointer)) { \
+    return UNIT_TEST_ERROR_TEST_FAILED;                                              \
+  }
+
+/**
+  If Expression is TRUE, then TRUE is returned.
+  If Expression is FALSE, then an assert is triggered and the location of the
+  assert provided by FunctionName, LineNumber, FileName, and Description are
+  recorded and FALSE is returned.
+
+  @param[in]  Expression    The BOOLEAN result of the expression evaluation.
+  @param[in]  FunctionName  Null-terminated ASCII string of the function
+                            executing the assert macro.
+  @param[in]  LineNumber    The source file line number of the assert macro.
+  @param[in]  FileName      Null-terminated ASCII string of the filename
+                            executing the assert macro.
+  @param[in]  Description   Null-terminated ASCII string of the expression being
+                            evaluated.
+
+  @retval  TRUE   Expression is TRUE.
+  @retval  FALSE  Expression is FALSE.
+**/
+BOOLEAN
+EFIAPI
+UnitTestAssertTrue (
+  IN BOOLEAN      Expression,
+  IN CONST CHAR8  *FunctionName,
+  IN UINTN        LineNumber,
+  IN CONST CHAR8  *FileName,
+  IN CONST CHAR8  *Description
+  );
+
+/**
+  If Expression is FALSE, then TRUE is returned.
+  If Expression is TRUE, then an assert is triggered and the location of the
+  assert provided by FunctionName, LineNumber, FileName, and Description are
+  recorded and FALSE is returned.
+
+  @param[in]  Expression    The BOOLEAN result of the expression evaluation.
+  @param[in]  FunctionName  Null-terminated ASCII string of the function
+                            executing the assert macro.
+  @param[in]  LineNumber    The source file line number of the assert macro.
+  @param[in]  FileName      Null-terminated ASCII string of the filename
+                            executing the assert macro.
+  @param[in]  Description   Null-terminated ASCII string of the expression being
+                            evaluated.
+
+  @retval  TRUE   Expression is FALSE.
+  @retval  FALSE  Expression is TRUE.
+**/
+BOOLEAN
+EFIAPI
+UnitTestAssertFalse (
+  IN BOOLEAN      Expression,
+  IN CONST CHAR8  *FunctionName,
+  IN UINTN        LineNumber,
+  IN CONST CHAR8  *FileName,
+  IN CONST CHAR8  *Description
+  );
+
+/**
+  If Status is not an EFI_ERROR(), then TRUE is returned.
+  If Status is an EFI_ERROR(), then an assert is triggered and the location of
+  the assert provided by FunctionName, LineNumber, FileName, and Description are
+  recorded and FALSE is returned.
+
+  @param[in]  Status        The EFI_STATUS value to evaluate.
+  @param[in]  FunctionName  Null-terminated ASCII string of the function
+                            executing the assert macro.
+  @param[in]  LineNumber    The source file line number of the assert macro.
+  @param[in]  FileName      Null-terminated ASCII string of the filename
+                            executing the assert macro.
+  @param[in]  Description   Null-terminated ASCII string of the status
+                            expression being evaluated.
+
+  @retval  TRUE   Status is not an EFI_ERROR().
+  @retval  FALSE  Status is an EFI_ERROR().
+**/
+BOOLEAN
+EFIAPI
+UnitTestAssertNotEfiError (
+  IN EFI_STATUS   Status,
+  IN CONST CHAR8  *FunctionName,
+  IN UINTN        LineNumber,
+  IN CONST CHAR8  *FileName,
+  IN CONST CHAR8  *Description
+  );
+
+/**
+  If ValueA is equal ValueB, then TRUE is returned.
+  If ValueA is not equal to ValueB, then an assert is triggered and the location
+  of the assert provided by FunctionName, LineNumber, FileName, DescriptionA,
+  and DescriptionB are recorded and FALSE is returned.
+
+  @param[in]  ValueA        64-bit value.
+  @param[in]  ValueB        64-bit value.
+  @param[in]  FunctionName  Null-terminated ASCII string of the function
+                            executing the assert macro.
+  @param[in]  LineNumber    The source file line number of the assert macro.
+  @param[in]  FileName      Null-terminated ASCII string of the filename
+                            executing the assert macro.
+  @param[in]  DescriptionA  Null-terminated ASCII string that is a description
+                            of ValueA.
+  @param[in]  DescriptionB  Null-terminated ASCII string that is a description
+                            of ValueB.
+
+  @retval  TRUE   ValueA is equal to ValueB.
+  @retval  FALSE  ValueA is not equal to ValueB.
+**/
+BOOLEAN
+EFIAPI
+UnitTestAssertEqual (
+  IN UINT64       ValueA,
+  IN UINT64       ValueB,
+  IN CONST CHAR8  *FunctionName,
+  IN UINTN        LineNumber,
+  IN CONST CHAR8  *FileName,
+  IN CONST CHAR8  *DescriptionA,
+  IN CONST CHAR8  *DescriptionB
+  );
+
+/**
+  If the contents of BufferA are identical to the contents of BufferB, then TRUE
+  is returned.  If the contents of BufferA are not identical to the contents of
+  BufferB, then an assert is triggered and the location of the assert provided
+  by FunctionName, LineNumber, FileName, DescriptionA, and DescriptionB are
+  recorded and FALSE is returned.
+
+  @param[in]  BufferA       Pointer to a buffer for comparison.
+  @param[in]  BufferB       Pointer to a buffer for comparison.
+  @param[in]  Length        Number of bytes to compare in BufferA and BufferB.
+  @param[in]  FunctionName  Null-terminated ASCII string of the function
+                            executing the assert macro.
+  @param[in]  LineNumber    The source file line number of the assert macro.
+  @param[in]  FileName      Null-terminated ASCII string of the filename
+                            executing the assert macro.
+  @param[in]  DescriptionA  Null-terminated ASCII string that is a description
+                            of BufferA.
+  @param[in]  DescriptionB  Null-terminated ASCII string that is a description
+                            of BufferB.
+
+  @retval  TRUE   The contents of BufferA are identical to the contents of
+                  BufferB.
+  @retval  FALSE  The contents of BufferA are not identical to the contents of
+                  BufferB.
+**/
+BOOLEAN
+EFIAPI
+UnitTestAssertMemEqual (
+  IN VOID         *BufferA,
+  IN VOID         *BufferB,
+  IN UINTN        Length,
+  IN CONST CHAR8  *FunctionName,
+  IN UINTN        LineNumber,
+  IN CONST CHAR8  *FileName,
+  IN CONST CHAR8  *DescriptionA,
+  IN CONST CHAR8  *DescriptionB
+  );
+
+/**
+  If ValueA is not equal ValueB, then TRUE is returned.
+  If ValueA is equal to ValueB, then an assert is triggered and the location
+  of the assert provided by FunctionName, LineNumber, FileName, DescriptionA
+  and DescriptionB are recorded and FALSE is returned.
+
+  @param[in]  ValueA        64-bit value.
+  @param[in]  ValueB        64-bit value.
+  @param[in]  FunctionName  Null-terminated ASCII string of the function
+                            executing the assert macro.
+  @param[in]  LineNumber    The source file line number of the assert macro.
+  @param[in]  FileName      Null-terminated ASCII string of the filename
+                            executing the assert macro.
+  @param[in]  DescriptionA  Null-terminated ASCII string that is a description
+                            of ValueA.
+  @param[in]  DescriptionB  Null-terminated ASCII string that is a description
+                            of ValueB.
+
+  @retval  TRUE   ValueA is not equal to ValueB.
+  @retval  FALSE  ValueA is equal to ValueB.
+**/
+BOOLEAN
+EFIAPI
+UnitTestAssertNotEqual (
+  IN UINT64       ValueA,
+  IN UINT64       ValueB,
+  IN CONST CHAR8  *FunctionName,
+  IN UINTN        LineNumber,
+  IN CONST CHAR8  *FileName,
+  IN CONST CHAR8  *DescriptionA,
+  IN CONST CHAR8  *DescriptionB
+  );
+
+/**
+  If Status is equal to Expected, then TRUE is returned.
+  If Status is not equal to Expected, then an assert is triggered and the
+  location of the assert provided by FunctionName, LineNumber, FileName, and
+  Description are recorded and FALSE is returned.
+
+  @param[in]  Status        EFI_STATUS value returned from an API under test.
+  @param[in]  Expected      The expected EFI_STATUS return value from an API
+                            under test.
+  @param[in]  FunctionName  Null-terminated ASCII string of the function
+                            executing the assert macro.
+  @param[in]  LineNumber    The source file line number of the assert macro.
+  @param[in]  FileName      Null-terminated ASCII string of the filename
+                            executing the assert macro.
+  @param[in]  Description   Null-terminated ASCII string that is a description
+                            of Status.
+
+  @retval  TRUE   Status is equal to Expected.
+  @retval  FALSE  Status is not equal to Expected.
+**/
+BOOLEAN
+EFIAPI
+UnitTestAssertStatusEqual (
+  IN EFI_STATUS   Status,
+  IN EFI_STATUS   Expected,
+  IN CONST CHAR8  *FunctionName,
+  IN UINTN        LineNumber,
+  IN CONST CHAR8  *FileName,
+  IN CONST CHAR8  *Description
+  );
+
+/**
+  If Pointer is not equal to NULL, then TRUE is returned.
+  If Pointer is equal to NULL, then an assert is triggered and the location of
+  the assert provided by FunctionName, LineNumber, FileName, and PointerName
+  are recorded and FALSE is returned.
+
+  @param[in]  Pointer       Pointer value to be checked against NULL.
+  @param[in]  Expected      The expected EFI_STATUS return value from a function
+                            under test.
+  @param[in]  FunctionName  Null-terminated ASCII string of the function
+                            executing the assert macro.
+  @param[in]  LineNumber    The source file line number of the assert macro.
+  @param[in]  FileName      Null-terminated ASCII string of the filename
+                            executing the assert macro.
+  @param[in]  PointerName   Null-terminated ASCII string that is a description
+                            of Pointer.
+
+  @retval  TRUE   Pointer is not equal to NULL.
+  @retval  FALSE  Pointer is equal to NULL.
+**/
+BOOLEAN
+EFIAPI
+UnitTestAssertNotNull (
+  IN VOID         *Pointer,
+  IN CONST CHAR8  *FunctionName,
+  IN UINTN        LineNumber,
+  IN CONST CHAR8  *FileName,
+  IN CONST CHAR8  *PointerName
+  );
+
+/**
+  Test logging macro that records an ERROR message in the test framework log.
+  Record is associated with the currently executing test case.
+
+  @param[in]  Format  Formatting string following the format defined in
+                      MdePkg/Include/Library/PrintLib.h.
+  @param[in]  ...     Print args.
+**/
+#define UT_LOG_ERROR(Format, ...)  \
+  UnitTestLog (UNIT_TEST_LOG_LEVEL_ERROR, Format, ##__VA_ARGS__)
+
+/**
+  Test logging macro that records a WARNING message in the test framework log.
+  Record is associated with the currently executing test case.
+
+  @param[in]  Format  Formatting string following the format defined in
+                      MdePkg/Include/Library/PrintLib.h.
+  @param[in]  ...     Print args.
+**/
+#define UT_LOG_WARNING(Format, ...)  \
+  UnitTestLog (UNIT_TEST_LOG_LEVEL_WARN, Format, ##__VA_ARGS__)
+
+/**
+  Test logging macro that records an INFO message in the test framework log.
+  Record is associated with the currently executing test case.
+
+  @param[in]  Format  Formatting string following the format defined in
+                      MdePkg/Include/Library/PrintLib.h.
+  @param[in]  ...     Print args.
+**/
+#define UT_LOG_INFO(Format, ...)  \
+  UnitTestLog (UNIT_TEST_LOG_LEVEL_INFO, Format, ##__VA_ARGS__)
+
+/**
+  Test logging macro that records a VERBOSE message in the test framework log.
+  Record is associated with the currently executing test case.
+
+  @param[in]  Format  Formatting string following the format defined in
+                      MdePkg/Include/Library/PrintLib.h.
+  @param[in]  ...     Print args.
+**/
+#define UT_LOG_VERBOSE(Format, ...)  \
+  UnitTestLog (UNIT_TEST_LOG_LEVEL_VERBOSE, Format, ##__VA_ARGS__)
+
+/**
+  Test logging function that records a messages in the test framework log.
+  Record is associated with the currently executing test case.
+
+  @param[in]  ErrorLevel  The error level of the unit test log message.
+  @param[in]  Format      Formatting string following the format defined in the
+                          MdePkg/Include/Library/PrintLib.h.
+  @param[in]  ...         Print args.
+**/
+VOID
+EFIAPI
+UnitTestLog (
+  IN  UINTN        ErrorLevel,
+  IN  CONST CHAR8  *Format,
+  ...
+  );
+
+#endif
diff --git a/MdePkg/Include/Pi/PiBootMode.h b/MdePkg/Include/Pi/PiBootMode.h
index 793833bccd4e..74b499a60427 100644
--- a/MdePkg/Include/Pi/PiBootMode.h
+++ b/MdePkg/Include/Pi/PiBootMode.h
@@ -2,13 +2,7 @@
   Present the boot mode values in PI.
 
   Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   PI Version 1.2.1A
diff --git a/MdePkg/Include/Pi/PiDependency.h b/MdePkg/Include/Pi/PiDependency.h
index da2cfee5f50b..82d59175abe7 100644
--- a/MdePkg/Include/Pi/PiDependency.h
+++ b/MdePkg/Include/Pi/PiDependency.h
@@ -1,14 +1,8 @@
 /** @file
   Present the dependency expression values in PI.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   PI Version 1.0
@@ -17,16 +11,16 @@
 #ifndef __PI_DEPENDENCY_H__
 #define __PI_DEPENDENCY_H__
 
-/// 
+///
 /// If present, this must be the first and only opcode,
 /// EFI_DEP_BEFORE may be used by DXE and SMM drivers.
-/// 
+///
 #define EFI_DEP_BEFORE        0x00
 
-/// 
+///
 /// If present, this must be the first and only opcode,
 /// EFI_DEP_AFTER may be used by DXE and SMM drivers.
-/// 
+///
 #define EFI_DEP_AFTER         0x01
 
 #define EFI_DEP_PUSH          0x02
@@ -38,10 +32,10 @@
 #define EFI_DEP_END           0x08
 
 
-/// 
+///
 /// If present, this must be the first opcode,
 /// EFI_DEP_SOR is only used by DXE driver.
-/// 
+///
 #define EFI_DEP_SOR           0x09
 
-#endif 
+#endif
diff --git a/MdePkg/Include/Pi/PiDxeCis.h b/MdePkg/Include/Pi/PiDxeCis.h
index 5c157a8179e0..d69ec896357c 100644
--- a/MdePkg/Include/Pi/PiDxeCis.h
+++ b/MdePkg/Include/Pi/PiDxeCis.h
@@ -1,17 +1,11 @@
 /** @file
   Include file matches things in PI.
 
-Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                            
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
-  PI Version 1.4
+  PI Version 1.7
 
 **/
 
@@ -49,10 +43,14 @@ typedef enum {
   ///
   EfiGcdMemoryTypeMemoryMappedIo,
   ///
-  /// A memory region that is visible to the boot processor. 
-  /// This memory supports byte-addressable non-volatility. 
+  /// A memory region that is visible to the boot processor.
+  /// This memory supports byte-addressable non-volatility.
   ///
-  EfiGcdMemoryTypePersistentMemory,
+  EfiGcdMemoryTypePersistent,
+  //
+  // Keep original one for the compatibility.
+  //
+  EfiGcdMemoryTypePersistentMemory = EfiGcdMemoryTypePersistent,
   ///
   /// A memory region that provides higher reliability relative to other memory in the
   /// system. If all memory has the same reliability, then this bit is not used.
@@ -85,7 +83,7 @@ typedef enum {
 
 ///
 /// The type of allocation to perform.
-/// 
+///
 typedef enum {
   ///
   /// The GCD memory space map is searched from the lowest address up to the highest address
@@ -93,22 +91,22 @@ typedef enum {
   ///
   EfiGcdAllocateAnySearchBottomUp,
   ///
-  /// The GCD memory space map is searched from the lowest address up 
+  /// The GCD memory space map is searched from the lowest address up
   /// to the specified MaxAddress looking for unallocated memory ranges.
   ///
   EfiGcdAllocateMaxAddressSearchBottomUp,
   ///
-  /// The GCD memory space map is checked to see if the memory range starting 
+  /// The GCD memory space map is checked to see if the memory range starting
   /// at the specified Address is available.
   ///
   EfiGcdAllocateAddress,
   ///
-  /// The GCD memory space map is searched from the highest address down to the lowest address 
+  /// The GCD memory space map is searched from the highest address down to the lowest address
   /// looking for unallocated memory ranges.
   ///
   EfiGcdAllocateAnySearchTopDown,
   ///
-  /// The GCD memory space map is searched from the specified MaxAddress 
+  /// The GCD memory space map is searched from the specified MaxAddress
   /// down to the lowest address looking for unallocated memory ranges.
   ///
   EfiGcdAllocateMaxAddressSearchTopDown,
@@ -117,35 +115,35 @@ typedef enum {
 
 ///
 /// EFI_GCD_MEMORY_SPACE_DESCRIPTOR.
-/// 
+///
 typedef struct {
   ///
   /// The physical address of the first byte in the memory region. Type
   /// EFI_PHYSICAL_ADDRESS is defined in the AllocatePages() function
   /// description in the UEFI 2.0 specification.
-  /// 
+  ///
   EFI_PHYSICAL_ADDRESS  BaseAddress;
 
   ///
   /// The number of bytes in the memory region.
-  /// 
+  ///
   UINT64                Length;
 
   ///
   /// The bit mask of attributes that the memory region is capable of supporting. The bit
   /// mask of available attributes is defined in the GetMemoryMap() function description
   /// in the UEFI 2.0 specification.
-  /// 
+  ///
   UINT64                Capabilities;
   ///
   /// The bit mask of attributes that the memory region is currently using. The bit mask of
   /// available attributes is defined in GetMemoryMap().
-  /// 
+  ///
   UINT64                Attributes;
   ///
   /// Type of the memory region. Type EFI_GCD_MEMORY_TYPE is defined in the
   /// AddMemorySpace() function description.
-  /// 
+  ///
   EFI_GCD_MEMORY_TYPE   GcdMemoryType;
 
   ///
@@ -153,7 +151,7 @@ typedef struct {
   /// PhysicalStart and NumberOfBytes. If this field is NULL, then the memory
   /// resource is not currently allocated. Type EFI_HANDLE is defined in
   /// InstallProtocolInterface() in the UEFI 2.0 specification.
-  /// 
+  ///
   EFI_HANDLE            ImageHandle;
 
   ///
@@ -162,19 +160,19 @@ typedef struct {
   /// field is NULL, then the memory resource is not associated with a device that is
   /// described by a device handle. Type EFI_HANDLE is defined in
   /// InstallProtocolInterface() in the UEFI 2.0 specification.
-  /// 
+  ///
   EFI_HANDLE            DeviceHandle;
 } EFI_GCD_MEMORY_SPACE_DESCRIPTOR;
 
 ///
 /// EFI_GCD_IO_SPACE_DESCRIPTOR.
-/// 
+///
 typedef struct {
   ///
   /// Physical address of the first byte in the I/O region. Type
   /// EFI_PHYSICAL_ADDRESS is defined in the AllocatePages() function
   /// description in the UEFI 2.0 specification.
-  /// 
+  ///
   EFI_PHYSICAL_ADDRESS  BaseAddress;
 
   ///
@@ -182,18 +180,18 @@ typedef struct {
   ///
   UINT64                Length;
 
-  /// 
+  ///
   /// Type of the I/O region. Type EFI_GCD_IO_TYPE is defined in the
   /// AddIoSpace() function description.
-  /// 
+  ///
   EFI_GCD_IO_TYPE       GcdIoType;
 
-  /// 
+  ///
   /// The image handle of the agent that allocated the I/O resource described by
   /// PhysicalStart and NumberOfBytes. If this field is NULL, then the I/O
   /// resource is not currently allocated. Type EFI_HANDLE is defined in
   /// InstallProtocolInterface() in the UEFI 2.0 specification.
-  /// 
+  ///
   EFI_HANDLE            ImageHandle;
 
   ///
@@ -202,7 +200,7 @@ typedef struct {
   /// the I/O resource is not associated with a device that is described by a device handle.
   /// Type EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI
   /// 2.0 specification.
-  /// 
+  ///
   EFI_HANDLE            DeviceHandle;
 } EFI_GCD_IO_SPACE_DESCRIPTOR;
 
@@ -216,7 +214,7 @@ typedef struct {
                            of the memory resource being added.
   @param  Length           The size, in bytes, of the memory resource that
                            is being added.
-  @param  Capabilities     The bit mask of attributes that the memory 
+  @param  Capabilities     The bit mask of attributes that the memory
                            resource region supports.
 
   @retval EFI_SUCCESS            The memory resource was added to the global
@@ -224,13 +222,13 @@ typedef struct {
   @retval EFI_INVALID_PARAMETER  GcdMemoryType is invalid.
   @retval EFI_INVALID_PARAMETER  Length is zero.
   @retval EFI_OUT_OF_RESOURCES   There are not enough system resources to add
-                                 the memory resource to the global coherency 
+                                 the memory resource to the global coherency
                                  domain of the processor.
   @retval EFI_UNSUPPORTED        The processor does not support one or more bytes
-                                 of the memory resource range specified by 
+                                 of the memory resource range specified by
                                  BaseAddress and Length.
   @retval EFI_ACCESS_DENIED      One or more bytes of the memory resource range
-                                 specified by BaseAddress and Length conflicts 
+                                 specified by BaseAddress and Length conflicts
                                  with a memory resource range that was previously
                                  added to the global coherency domain of the processor.
   @retval EFI_ACCESS_DENIED      One or more bytes of the memory resource range
@@ -258,7 +256,7 @@ EFI_STATUS
   @param  Length           The size in bytes of the memory resource range that
                            is being allocated.
   @param  BaseAddress      A pointer to a physical address to allocate.
-  @param  Imagehandle      The image handle of the agent that is allocating 
+  @param  Imagehandle      The image handle of the agent that is allocating
                            the memory resource.
   @param  DeviceHandle     The device handle for which the memory resource
                            is being allocated.
@@ -298,7 +296,7 @@ EFI_STATUS
 
   @retval EFI_SUCCESS           The memory resource was freed from the global coherency domain of
                                 the processor.
-  @retval EFI_INVALID_PARAMETER Length is zero.   
+  @retval EFI_INVALID_PARAMETER Length is zero.
   @retval EFI_UNSUPPORTED       The processor does not support one or more bytes of the memory
                                 resource range specified by BaseAddress and Length.
   @retval EFI_NOT_FOUND         The memory resource range specified by BaseAddress and
@@ -323,7 +321,7 @@ EFI_STATUS
 
   @retval EFI_SUCCESS           The memory resource was removed from the global coherency
                                 domain of the processor.
-  @retval EFI_INVALID_PARAMETER Length is zero. 
+  @retval EFI_INVALID_PARAMETER Length is zero.
   @retval EFI_UNSUPPORTED       The processor does not support one or more bytes of the memory
                                 resource range specified by BaseAddress and Length.
   @retval EFI_NOT_FOUND         One or more bytes of the memory resource range specified by
@@ -370,7 +368,7 @@ EFI_STATUS
   @param  Attributes       The bit mask of attributes to set for the memory region.
 
   @retval EFI_SUCCESS           The attributes were set for the memory region.
-  @retval EFI_INVALID_PARAMETER Length is zero. 
+  @retval EFI_INVALID_PARAMETER Length is zero.
   @retval EFI_UNSUPPORTED       The processor does not support one or more bytes of the memory
                                 resource range specified by BaseAddress and Length.
   @retval EFI_UNSUPPORTED       The bit mask of attributes is not support for the memory resource
@@ -606,8 +604,8 @@ EFI_STATUS
 /**
   Loads and executed DXE drivers from firmware volumes.
 
-  The Dispatch() function searches for DXE drivers in firmware volumes that have been 
-  installed since the last time the Dispatch() service was called. It then evaluates 
+  The Dispatch() function searches for DXE drivers in firmware volumes that have been
+  installed since the last time the Dispatch() service was called. It then evaluates
   the dependency expressions of all the DXE drivers and loads and executes those DXE
   drivers whose dependency expression evaluate to TRUE. This service must interact with
   the Security Architectural Protocol to authenticate DXE drivers before they are executed.
@@ -675,7 +673,7 @@ EFI_STATUS
   @retval EFI_VOLUME_CORRUPTED The firmware volume described by FirmwareVolumeHeader
                                and Size is corrupted.
   @retval EFI_OUT_OF_RESOURCES There are not enough system resources available to produce the
-                               EFI_FIRMWARE_VOLUME_PROTOCOL and EFI_DEVICE_PATH_PROTOCOL 
+                               EFI_FIRMWARE_VOLUME_PROTOCOL and EFI_DEVICE_PATH_PROTOCOL
                                for the firmware volume described by FirmwareVolumeHeader and Size.
 
 **/
@@ -692,7 +690,7 @@ EFI_STATUS
 //
 #define DXE_SERVICES_SIGNATURE            0x565245535f455844ULL
 #define DXE_SPECIFICATION_MAJOR_REVISION  1
-#define DXE_SPECIFICATION_MINOR_REVISION  40
+#define DXE_SPECIFICATION_MINOR_REVISION  70
 #define DXE_SERVICES_REVISION             ((DXE_SPECIFICATION_MAJOR_REVISION<<16) | (DXE_SPECIFICATION_MINOR_REVISION))
 
 typedef struct {
diff --git a/MdePkg/Include/Pi/PiFirmwareFile.h b/MdePkg/Include/Pi/PiFirmwareFile.h
index 5591608baf1c..bfb8fe3695e5 100644
--- a/MdePkg/Include/Pi/PiFirmwareFile.h
+++ b/MdePkg/Include/Pi/PiFirmwareFile.h
@@ -1,17 +1,11 @@
 /** @file
   The firmware file related definitions in PI.
 
-Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under
-the terms and conditions of the BSD License that accompanies this distribution.
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
-  PI Version 1.4.
+  PI Version 1.6.
 
 **/
 
@@ -71,10 +65,15 @@ typedef UINT8 EFI_FFS_FILE_STATE;
 #define EFI_FV_FILETYPE_DRIVER                0x07
 #define EFI_FV_FILETYPE_COMBINED_PEIM_DRIVER  0x08
 #define EFI_FV_FILETYPE_APPLICATION           0x09
-#define EFI_FV_FILETYPE_SMM                   0x0A
+#define EFI_FV_FILETYPE_MM                    0x0A
+#define EFI_FV_FILETYPE_SMM                   EFI_FV_FILETYPE_MM
 #define EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE 0x0B
-#define EFI_FV_FILETYPE_COMBINED_SMM_DXE      0x0C
-#define EFI_FV_FILETYPE_SMM_CORE              0x0D
+#define EFI_FV_FILETYPE_COMBINED_MM_DXE       0x0C
+#define EFI_FV_FILETYPE_COMBINED_SMM_DXE      EFI_FV_FILETYPE_COMBINED_MM_DXE
+#define EFI_FV_FILETYPE_MM_CORE               0x0D
+#define EFI_FV_FILETYPE_SMM_CORE              EFI_FV_FILETYPE_MM_CORE
+#define EFI_FV_FILETYPE_MM_STANDALONE         0x0E
+#define EFI_FV_FILETYPE_MM_CORE_STANDALONE    0x0F
 #define EFI_FV_FILETYPE_OEM_MIN               0xc0
 #define EFI_FV_FILETYPE_OEM_MAX               0xdf
 #define EFI_FV_FILETYPE_DEBUG_MIN             0xe0
@@ -86,6 +85,7 @@ typedef UINT8 EFI_FFS_FILE_STATE;
 /// FFS File Attributes.
 ///
 #define FFS_ATTRIB_LARGE_FILE         0x01
+#define FFS_ATTRIB_DATA_ALIGNMENT_2   0x02
 #define FFS_ATTRIB_FIXED              0x04
 #define FFS_ATTRIB_DATA_ALIGNMENT     0x38
 #define FFS_ATTRIB_CHECKSUM           0x40
@@ -179,8 +179,15 @@ typedef struct {
 #define IS_FFS_FILE2(FfsFileHeaderPtr) \
     (((((EFI_FFS_FILE_HEADER *) (UINTN) FfsFileHeaderPtr)->Attributes) & FFS_ATTRIB_LARGE_FILE) == FFS_ATTRIB_LARGE_FILE)
 
-#define FFS_FILE_SIZE(FfsFileHeaderPtr) \
-    ((UINT32) (*((UINT32 *) ((EFI_FFS_FILE_HEADER *) (UINTN) FfsFileHeaderPtr)->Size) & 0x00ffffff))
+///
+/// The argument passed as the FfsFileHeaderPtr parameter to the
+/// FFS_FILE_SIZE() function-like macro below must not have side effects:
+/// FfsFileHeaderPtr is evaluated multiple times.
+///
+#define FFS_FILE_SIZE(FfsFileHeaderPtr) ((UINT32) ( \
+    (((EFI_FFS_FILE_HEADER *) (UINTN) (FfsFileHeaderPtr))->Size[0]      ) | \
+    (((EFI_FFS_FILE_HEADER *) (UINTN) (FfsFileHeaderPtr))->Size[1] <<  8) | \
+    (((EFI_FFS_FILE_HEADER *) (UINTN) (FfsFileHeaderPtr))->Size[2] << 16)))
 
 #define FFS_FILE2_SIZE(FfsFileHeaderPtr) \
     ((UINT32) (((EFI_FFS_FILE_HEADER2 *) (UINTN) FfsFileHeaderPtr)->ExtendedSize))
@@ -216,7 +223,8 @@ typedef UINT8 EFI_SECTION_TYPE;
 #define EFI_SECTION_FREEFORM_SUBTYPE_GUID 0x18
 #define EFI_SECTION_RAW                   0x19
 #define EFI_SECTION_PEI_DEPEX             0x1B
-#define EFI_SECTION_SMM_DEPEX             0x1C
+#define EFI_SECTION_MM_DEPEX              0x1C
+#define EFI_SECTION_SMM_DEPEX             EFI_SECTION_MM_DEPEX
 
 ///
 /// Common section header.
@@ -479,11 +487,18 @@ typedef struct {
   CHAR16                        VersionString[1];
 } EFI_VERSION_SECTION2;
 
-#define IS_SECTION2(SectionHeaderPtr) \
-    ((UINT32) (*((UINT32 *) ((EFI_COMMON_SECTION_HEADER *) (UINTN) SectionHeaderPtr)->Size) & 0x00ffffff) == 0x00ffffff)
+///
+/// The argument passed as the SectionHeaderPtr parameter to the SECTION_SIZE()
+/// and IS_SECTION2() function-like macros below must not have side effects:
+/// SectionHeaderPtr is evaluated multiple times.
+///
+#define SECTION_SIZE(SectionHeaderPtr) ((UINT32) ( \
+    (((EFI_COMMON_SECTION_HEADER *) (UINTN) (SectionHeaderPtr))->Size[0]      ) | \
+    (((EFI_COMMON_SECTION_HEADER *) (UINTN) (SectionHeaderPtr))->Size[1] <<  8) | \
+    (((EFI_COMMON_SECTION_HEADER *) (UINTN) (SectionHeaderPtr))->Size[2] << 16)))
 
-#define SECTION_SIZE(SectionHeaderPtr) \
-    ((UINT32) (*((UINT32 *) ((EFI_COMMON_SECTION_HEADER *) (UINTN) SectionHeaderPtr)->Size) & 0x00ffffff))
+#define IS_SECTION2(SectionHeaderPtr) \
+    (SECTION_SIZE (SectionHeaderPtr) == 0x00ffffff)
 
 #define SECTION2_SIZE(SectionHeaderPtr) \
     (((EFI_COMMON_SECTION_HEADER2 *) (UINTN) SectionHeaderPtr)->ExtendedSize)
diff --git a/MdePkg/Include/Pi/PiFirmwareVolume.h b/MdePkg/Include/Pi/PiFirmwareVolume.h
index 6ef2f1fc33f3..ca13075b77d9 100644
--- a/MdePkg/Include/Pi/PiFirmwareVolume.h
+++ b/MdePkg/Include/Pi/PiFirmwareVolume.h
@@ -1,17 +1,11 @@
 /** @file
   The firmware volume related definitions in PI.
 
-  Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
-  PI Version 1.3
+  PI Version 1.6
 
 **/
 
@@ -231,4 +225,23 @@ typedef struct {
   ///
 } EFI_FIRMWARE_VOLUME_EXT_ENTRY_GUID_TYPE;
 
+#define EFI_FV_EXT_TYPE_USED_SIZE_TYPE 0x03
+
+///
+/// The EFI_FIRMWARE_VOLUME_EXT_ENTRY_USED_SIZE_TYPE can be used to find
+/// out how many EFI_FVB2_ERASE_POLARITY bytes are at the end of the FV.
+///
+typedef struct {
+  ///
+  /// Standard extension entry, with the type EFI_FV_EXT_TYPE_USED_SIZE_TYPE.
+  ///
+  EFI_FIRMWARE_VOLUME_EXT_ENTRY     Hdr;
+  ///
+  /// The number of bytes of the FV that are in uses. The remaining
+  /// EFI_FIRMWARE_VOLUME_HEADER FvLength minus UsedSize bytes in
+  /// the FV must contain the value implied by EFI_FVB2_ERASE_POLARITY.
+  ///
+  UINT32                            UsedSize;
+} EFI_FIRMWARE_VOLUME_EXT_ENTRY_USED_SIZE_TYPE;
+
 #endif
diff --git a/MdePkg/Include/Pi/PiHob.h b/MdePkg/Include/Pi/PiHob.h
index d7dad133a70a..b38b15aee650 100644
--- a/MdePkg/Include/Pi/PiHob.h
+++ b/MdePkg/Include/Pi/PiHob.h
@@ -1,17 +1,11 @@
 /** @file
   HOB related definitions in PI.
 
-Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under
-the terms and conditions of the BSD License that accompanies this distribution.
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
-  PI Version 1.4a
+  PI Version 1.6
 
 **/
 
@@ -31,6 +25,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #define EFI_HOB_TYPE_FV2                  0x0009
 #define EFI_HOB_TYPE_LOAD_PEIM_UNUSED     0x000A
 #define EFI_HOB_TYPE_UEFI_CAPSULE         0x000B
+#define EFI_HOB_TYPE_FV3                  0x000C
 #define EFI_HOB_TYPE_UNUSED               0xFFFE
 #define EFI_HOB_TYPE_END_OF_HOB_LIST      0xFFFF
 
@@ -399,6 +394,43 @@ typedef struct {
   EFI_GUID                FileName;
 } EFI_HOB_FIRMWARE_VOLUME2;
 
+///
+/// Details the location of a firmware volume that was extracted
+/// from a file within another firmware volume.
+///
+typedef struct {
+  ///
+  /// The HOB generic header. Header.HobType = EFI_HOB_TYPE_FV3.
+  ///
+  EFI_HOB_GENERIC_HEADER  Header;
+  ///
+  /// The physical memory-mapped base address of the firmware volume.
+  ///
+  EFI_PHYSICAL_ADDRESS    BaseAddress;
+  ///
+  /// The length in bytes of the firmware volume.
+  ///
+  UINT64                  Length;
+  ///
+  /// The authentication status.
+  ///
+  UINT32                  AuthenticationStatus;
+  ///
+  /// TRUE if the FV was extracted as a file within another firmware volume.
+  /// FALSE otherwise.
+  ///
+  BOOLEAN                 ExtractedFv;
+  ///
+  /// The name of the firmware volume.
+  /// Valid only if IsExtractedFv is TRUE.
+  ///
+  EFI_GUID                FvName;
+  ///
+  /// The name of the firmware file that contained this firmware volume.
+  /// Valid only if IsExtractedFv is TRUE.
+  ///
+  EFI_GUID                FileName;
+} EFI_HOB_FIRMWARE_VOLUME3;
 
 ///
 /// Describes processor information, such as address space and I/O space capabilities.
@@ -469,6 +501,7 @@ typedef union {
   EFI_HOB_GUID_TYPE                   *Guid;
   EFI_HOB_FIRMWARE_VOLUME             *FirmwareVolume;
   EFI_HOB_FIRMWARE_VOLUME2            *FirmwareVolume2;
+  EFI_HOB_FIRMWARE_VOLUME3            *FirmwareVolume3;
   EFI_HOB_CPU                         *Cpu;
   EFI_HOB_MEMORY_POOL                 *Pool;
   EFI_HOB_UEFI_CAPSULE                *Capsule;
diff --git a/MdePkg/Include/Pi/PiI2c.h b/MdePkg/Include/Pi/PiI2c.h
index 4aa55f5e3e6d..45f0917aee0a 100644
--- a/MdePkg/Include/Pi/PiI2c.h
+++ b/MdePkg/Include/Pi/PiI2c.h
@@ -1,14 +1,8 @@
 /** @file
   Include file matches things in PI.
 
-Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                            
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   PI Version 1.3
diff --git a/MdePkg/Include/Pi/PiMmCis.h b/MdePkg/Include/Pi/PiMmCis.h
new file mode 100644
index 000000000000..a802ad076af9
--- /dev/null
+++ b/MdePkg/Include/Pi/PiMmCis.h
@@ -0,0 +1,345 @@
+/** @file
+  Common definitions in the Platform Initialization Specification version 1.5
+  VOLUME 4 Management Mode Core Interface version.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PI_MMCIS_H_
+#define _PI_MMCIS_H_
+
+#include <Pi/PiMultiPhase.h>
+#include <Protocol/MmCpuIo.h>
+
+typedef struct _EFI_MM_SYSTEM_TABLE  EFI_MM_SYSTEM_TABLE;
+
+///
+/// The Management Mode System Table (MMST) signature
+///
+#define MM_MMST_SIGNATURE            SIGNATURE_32 ('S', 'M', 'S', 'T')
+///
+/// The Management Mode System Table (MMST) revision is 1.6
+///
+#define MM_SPECIFICATION_MAJOR_REVISION  1
+#define MM_SPECIFICATION_MINOR_REVISION  60
+#define EFI_MM_SYSTEM_TABLE_REVISION    ((MM_SPECIFICATION_MAJOR_REVISION<<16) | (MM_SPECIFICATION_MINOR_REVISION))
+
+/**
+  Adds, updates, or removes a configuration table entry from the Management Mode System Table.
+
+  The MmInstallConfigurationTable() function is used to maintain the list
+  of configuration tables that are stored in the Management Mode System
+  Table.  The list is stored as an array of (GUID, Pointer) pairs.  The list
+  must be allocated from pool memory with PoolType set to EfiRuntimeServicesData.
+
+  @param[in] SystemTable         A pointer to the MM System Table (MMST).
+  @param[in] Guid                A pointer to the GUID for the entry to add, update, or remove.
+  @param[in] Table               A pointer to the buffer of the table to add.
+  @param[in] TableSize           The size of the table to install.
+
+  @retval EFI_SUCCESS            The (Guid, Table) pair was added, updated, or removed.
+  @retval EFI_INVALID_PARAMETER  Guid is not valid.
+  @retval EFI_NOT_FOUND          An attempt was made to delete a non-existent entry.
+  @retval EFI_OUT_OF_RESOURCES   There is not enough memory available to complete the operation.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_INSTALL_CONFIGURATION_TABLE)(
+  IN CONST EFI_MM_SYSTEM_TABLE    *SystemTable,
+  IN CONST EFI_GUID               *Guid,
+  IN VOID                         *Table,
+  IN UINTN                        TableSize
+  );
+
+/**
+  This service lets the caller to get one distinct application processor (AP) to execute
+  a caller-provided code stream while in MM.
+
+  @param[in]     Procedure       A pointer to the code stream to be run on the designated
+                                 AP of the system.
+  @param[in]     CpuNumber       The zero-based index of the processor number of the AP
+                                 on which the code stream is supposed to run.
+  @param[in,out] ProcArguments   Allows the caller to pass a list of parameters to the code
+                                 that is run by the AP.
+
+  @retval EFI_SUCCESS            The call was successful and the return parameters are valid.
+  @retval EFI_INVALID_PARAMETER  The input arguments are out of range.
+  @retval EFI_INVALID_PARAMETER  The CPU requested is not available on this SMI invocation.
+  @retval EFI_INVALID_PARAMETER  The CPU cannot support an additional service invocation.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_STARTUP_THIS_AP)(
+  IN EFI_AP_PROCEDURE  Procedure,
+  IN UINTN             CpuNumber,
+  IN OUT VOID          *ProcArguments OPTIONAL
+  );
+
+/**
+  Function prototype for protocol install notification.
+
+  @param[in] Protocol   Points to the protocol's unique identifier.
+  @param[in] Interface  Points to the interface instance.
+  @param[in] Handle     The handle on which the interface was installed.
+
+  @return Status Code
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_NOTIFY_FN)(
+  IN CONST EFI_GUID  *Protocol,
+  IN VOID            *Interface,
+  IN EFI_HANDLE      Handle
+  );
+
+/**
+  Register a callback function be called when a particular protocol interface is installed.
+
+  The MmRegisterProtocolNotify() function creates a registration Function that is to be
+  called whenever a protocol interface is installed for Protocol by
+  MmInstallProtocolInterface().
+  If Function == NULL and Registration is an existing registration, then the callback is unhooked.
+
+  @param[in]  Protocol          The unique ID of the protocol for which the event is to be registered.
+  @param[in]  Function          Points to the notification function.
+  @param[out] Registration      A pointer to a memory location to receive the registration value.
+
+  @retval EFI_SUCCESS           Successfully returned the registration record
+                                that has been added or unhooked.
+  @retval EFI_INVALID_PARAMETER Protocol is NULL or Registration is NULL.
+  @retval EFI_OUT_OF_RESOURCES  Not enough memory resource to finish the request.
+  @retval EFI_NOT_FOUND         If the registration is not found when Function == NULL.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_REGISTER_PROTOCOL_NOTIFY)(
+  IN  CONST EFI_GUID     *Protocol,
+  IN  EFI_MM_NOTIFY_FN   Function,
+  OUT VOID               **Registration
+  );
+
+/**
+  Manage MMI of a particular type.
+
+  @param[in]     HandlerType     Points to the handler type or NULL for root MMI handlers.
+  @param[in]     Context         Points to an optional context buffer.
+  @param[in,out] CommBuffer      Points to the optional communication buffer.
+  @param[in,out] CommBufferSize  Points to the size of the optional communication buffer.
+
+  @retval EFI_WARN_INTERRUPT_SOURCE_PENDING  Interrupt source was processed successfully but not quiesced.
+  @retval EFI_INTERRUPT_PENDING              One or more SMI sources could not be quiesced.
+  @retval EFI_NOT_FOUND                      Interrupt source was not handled or quiesced.
+  @retval EFI_SUCCESS                        Interrupt source was handled and quiesced.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_INTERRUPT_MANAGE)(
+  IN CONST EFI_GUID  *HandlerType,
+  IN CONST VOID      *Context         OPTIONAL,
+  IN OUT VOID        *CommBuffer      OPTIONAL,
+  IN OUT UINTN       *CommBufferSize  OPTIONAL
+  );
+
+/**
+  Main entry point for an MM handler dispatch or communicate-based callback.
+
+  @param[in]     DispatchHandle  The unique handle assigned to this handler by MmiHandlerRegister().
+  @param[in]     Context         Points to an optional handler context which was specified when the
+                                 handler was registered.
+  @param[in,out] CommBuffer      A pointer to a collection of data in memory that will
+                                 be conveyed from a non-MM environment into an MM environment.
+  @param[in,out] CommBufferSize  The size of the CommBuffer.
+
+  @retval EFI_SUCCESS                         The interrupt was handled and quiesced. No other handlers
+                                              should still be called.
+  @retval EFI_WARN_INTERRUPT_SOURCE_QUIESCED  The interrupt has been quiesced but other handlers should
+                                              still be called.
+  @retval EFI_WARN_INTERRUPT_SOURCE_PENDING   The interrupt is still pending and other handlers should still
+                                              be called.
+  @retval EFI_INTERRUPT_PENDING               The interrupt could not be quiesced.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_HANDLER_ENTRY_POINT)(
+  IN EFI_HANDLE  DispatchHandle,
+  IN CONST VOID  *Context         OPTIONAL,
+  IN OUT VOID    *CommBuffer      OPTIONAL,
+  IN OUT UINTN   *CommBufferSize  OPTIONAL
+  );
+
+/**
+  Registers a handler to execute within MM.
+
+  @param[in]  Handler            Handler service function pointer.
+  @param[in]  HandlerType        Points to the handler type or NULL for root MMI handlers.
+  @param[out] DispatchHandle     On return, contains a unique handle which can be used to later
+                                 unregister the handler function.
+
+  @retval EFI_SUCCESS            MMI handler added successfully.
+  @retval EFI_INVALID_PARAMETER  Handler is NULL or DispatchHandle is NULL.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_INTERRUPT_REGISTER)(
+  IN  EFI_MM_HANDLER_ENTRY_POINT    Handler,
+  IN  CONST EFI_GUID                *HandlerType OPTIONAL,
+  OUT EFI_HANDLE                    *DispatchHandle
+  );
+
+/**
+  Unregister a handler in MM.
+
+  @param[in] DispatchHandle      The handle that was specified when the handler was registered.
+
+  @retval EFI_SUCCESS            Handler function was successfully unregistered.
+  @retval EFI_INVALID_PARAMETER  DispatchHandle does not refer to a valid handle.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_INTERRUPT_UNREGISTER)(
+  IN EFI_HANDLE  DispatchHandle
+  );
+
+///
+/// Processor information and functionality needed by MM Foundation.
+///
+typedef struct _EFI_MM_ENTRY_CONTEXT {
+  EFI_MM_STARTUP_THIS_AP   MmStartupThisAp;
+  ///
+  /// A number between zero and the NumberOfCpus field. This field designates which
+  /// processor is executing the MM Foundation.
+  ///
+  UINTN                    CurrentlyExecutingCpu;
+  ///
+  /// The number of possible processors in the platform.  This is a 1 based
+  /// counter.  This does not indicate the number of processors that entered MM.
+  ///
+  UINTN                    NumberOfCpus;
+  ///
+  /// Points to an array, where each element describes the number of bytes in the
+  /// corresponding save state specified by CpuSaveState. There are always
+  /// NumberOfCpus entries in the array.
+  ///
+  UINTN                    *CpuSaveStateSize;
+  ///
+  /// Points to an array, where each element is a pointer to a CPU save state. The
+  /// corresponding element in CpuSaveStateSize specifies the number of bytes in the
+  /// save state area. There are always NumberOfCpus entries in the array.
+  ///
+  VOID                     **CpuSaveState;
+} EFI_MM_ENTRY_CONTEXT;
+
+/**
+  This function is the main entry point to the MM Foundation.
+
+  @param[in] MmEntryContext  Processor information and functionality needed by MM Foundation.
+**/
+typedef
+VOID
+(EFIAPI *EFI_MM_ENTRY_POINT)(
+  IN CONST EFI_MM_ENTRY_CONTEXT  *MmEntryContext
+  );
+
+///
+/// Management Mode System Table (MMST)
+///
+/// The Management Mode System Table (MMST) is a table that contains a collection of common
+/// services for managing MMRAM allocation and providing basic I/O services. These services are
+/// intended for both preboot and runtime usage.
+///
+struct _EFI_MM_SYSTEM_TABLE {
+  ///
+  /// The table header for the SMST.
+  ///
+  EFI_TABLE_HEADER                     Hdr;
+  ///
+  /// A pointer to a NULL-terminated Unicode string containing the vendor name.
+  /// It is permissible for this pointer to be NULL.
+  ///
+  CHAR16                               *MmFirmwareVendor;
+  ///
+  /// The particular revision of the firmware.
+  ///
+  UINT32                               MmFirmwareRevision;
+
+  EFI_MM_INSTALL_CONFIGURATION_TABLE   MmInstallConfigurationTable;
+
+  ///
+  /// I/O Service
+  ///
+  EFI_MM_CPU_IO_PROTOCOL               MmIo;
+
+  ///
+  /// Runtime memory services
+  ///
+  EFI_ALLOCATE_POOL                    MmAllocatePool;
+  EFI_FREE_POOL                        MmFreePool;
+  EFI_ALLOCATE_PAGES                   MmAllocatePages;
+  EFI_FREE_PAGES                       MmFreePages;
+
+  ///
+  /// MP service
+  ///
+  EFI_MM_STARTUP_THIS_AP               MmStartupThisAp;
+
+  ///
+  /// CPU information records
+  ///
+
+  ///
+  /// A number between zero and and the NumberOfCpus field. This field designates
+  /// which processor is executing the MM infrastructure.
+  ///
+  UINTN                                CurrentlyExecutingCpu;
+  ///
+  /// The number of possible processors in the platform.  This is a 1 based counter.
+  ///
+  UINTN                                NumberOfCpus;
+  ///
+  /// Points to an array, where each element describes the number of bytes in the
+  /// corresponding save state specified by CpuSaveState. There are always
+  /// NumberOfCpus entries in the array.
+  ///
+  UINTN                                *CpuSaveStateSize;
+  ///
+  /// Points to an array, where each element is a pointer to a CPU save state. The
+  /// corresponding element in CpuSaveStateSize specifies the number of bytes in the
+  /// save state area. There are always NumberOfCpus entries in the array.
+  ///
+  VOID                                 **CpuSaveState;
+
+  ///
+  /// Extensibility table
+  ///
+
+  ///
+  /// The number of UEFI Configuration Tables in the buffer MmConfigurationTable.
+  ///
+  UINTN                                NumberOfTableEntries;
+  ///
+  /// A pointer to the UEFI Configuration Tables. The number of entries in the table is
+  /// NumberOfTableEntries.
+  ///
+  EFI_CONFIGURATION_TABLE              *MmConfigurationTable;
+
+  ///
+  /// Protocol services
+  ///
+  EFI_INSTALL_PROTOCOL_INTERFACE       MmInstallProtocolInterface;
+  EFI_UNINSTALL_PROTOCOL_INTERFACE     MmUninstallProtocolInterface;
+  EFI_HANDLE_PROTOCOL                  MmHandleProtocol;
+  EFI_MM_REGISTER_PROTOCOL_NOTIFY      MmRegisterProtocolNotify;
+  EFI_LOCATE_HANDLE                    MmLocateHandle;
+  EFI_LOCATE_PROTOCOL                  MmLocateProtocol;
+
+  ///
+  /// MMI Management functions
+  ///
+  EFI_MM_INTERRUPT_MANAGE              MmiManage;
+  EFI_MM_INTERRUPT_REGISTER            MmiHandlerRegister;
+  EFI_MM_INTERRUPT_UNREGISTER          MmiHandlerUnRegister;
+};
+
+#endif
diff --git a/MdePkg/Include/Pi/PiMultiPhase.h b/MdePkg/Include/Pi/PiMultiPhase.h
index 3561254b337f..e4f2f00c27db 100644
--- a/MdePkg/Include/Pi/PiMultiPhase.h
+++ b/MdePkg/Include/Pi/PiMultiPhase.h
@@ -1,14 +1,8 @@
 /** @file
   Include file matches things in PI for multiple module types.
 
-Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                                                                    
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   These elements are defined in UEFI Platform Initialization Specification 1.2.
@@ -30,10 +24,10 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   Produces an error code in the range reserved for use by the Platform Initialization
   Architecture Specification.
 
-  The supported 32-bit range is 0xA0000000-0xBFFFFFFF 
-  The supported 64-bit range is 0xA000000000000000-0xBFFFFFFFFFFFFFFF 
+  The supported 32-bit range is 0xA0000000-0xBFFFFFFF
+  The supported 64-bit range is 0xA000000000000000-0xBFFFFFFFFFFFFFFF
 
-  @param  StatusCode    The status code value to convert into a warning code.  
+  @param  StatusCode    The status code value to convert into a warning code.
                         StatusCode must be in the range 0x00000000..0x1FFFFFFF.
 
   @return The value specified by StatusCode in the PI reserved range.
@@ -47,7 +41,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #define EFI_REQUEST_UNLOAD_IMAGE  DXE_ERROR (1)
 
 ///
-/// If this value is returned by an API, it means the capability is not yet 
+/// If this value is returned by an API, it means the capability is not yet
 /// installed/available/ready to use.
 ///
 #define EFI_NOT_AVAILABLE_YET     DXE_ERROR (2)
@@ -66,9 +60,9 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 ///
 #define PI_ENCODE_ERROR(a)                  (MAX_BIT | (MAX_BIT >> 2) | (a))
 
-/// 
+///
 /// Return status codes defined in SMM CIS.
-/// 
+///
 #define EFI_INTERRUPT_PENDING               PI_ENCODE_ERROR (0)
 
 #define EFI_WARN_INTERRUPT_SOURCE_PENDING   PI_ENCODE_WARNING (0)
@@ -76,7 +70,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
 ///
 /// Bitmask of values for Authentication Status.
-/// Authentication Status is returned from EFI_GUIDED_SECTION_EXTRACTION_PROTOCOL 
+/// Authentication Status is returned from EFI_GUIDED_SECTION_EXTRACTION_PROTOCOL
 /// and the EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI
 ///
 /// xx00 Image was not signed.
@@ -95,43 +89,49 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 ///@}
 
 ///
-/// SMRAM states and capabilities
+/// MMRAM states and capabilities
 ///
-#define EFI_SMRAM_OPEN                  0x00000001
-#define EFI_SMRAM_CLOSED                0x00000002
-#define EFI_SMRAM_LOCKED                0x00000004
+#define EFI_MMRAM_OPEN                  0x00000001
+#define EFI_MMRAM_CLOSED                0x00000002
+#define EFI_MMRAM_LOCKED                0x00000004
 #define EFI_CACHEABLE                   0x00000008
 #define EFI_ALLOCATED                   0x00000010
 #define EFI_NEEDS_TESTING               0x00000020
 #define EFI_NEEDS_ECC_INITIALIZATION    0x00000040
 
+#define EFI_SMRAM_OPEN                  EFI_MMRAM_OPEN
+#define EFI_SMRAM_CLOSED                EFI_MMRAM_CLOSED
+#define EFI_SMRAM_LOCKED                EFI_MMRAM_LOCKED
+
 ///
-/// Structure describing a SMRAM region and its accessibility attributes.
+/// Structure describing a MMRAM region and its accessibility attributes.
 ///
 typedef struct {
   ///
-  /// Designates the physical address of the SMRAM in memory. This view of memory is 
-  /// the same as seen by I/O-based agents, for example, but it may not be the address seen 
+  /// Designates the physical address of the MMRAM in memory. This view of memory is
+  /// the same as seen by I/O-based agents, for example, but it may not be the address seen
   /// by the processors.
   ///
   EFI_PHYSICAL_ADDRESS  PhysicalStart;
   ///
-  /// Designates the address of the SMRAM, as seen by software executing on the 
+  /// Designates the address of the MMRAM, as seen by software executing on the
   /// processors. This address may or may not match PhysicalStart.
   ///
-  EFI_PHYSICAL_ADDRESS  CpuStart;       
+  EFI_PHYSICAL_ADDRESS  CpuStart;
   ///
-  /// Describes the number of bytes in the SMRAM region.
+  /// Describes the number of bytes in the MMRAM region.
   ///
   UINT64                PhysicalSize;
   ///
-  /// Describes the accessibility attributes of the SMRAM.  These attributes include the 
-  /// hardware state (e.g., Open/Closed/Locked), capability (e.g., cacheable), logical 
-  /// allocation (e.g., allocated), and pre-use initialization (e.g., needs testing/ECC 
+  /// Describes the accessibility attributes of the MMRAM.  These attributes include the
+  /// hardware state (e.g., Open/Closed/Locked), capability (e.g., cacheable), logical
+  /// allocation (e.g., allocated), and pre-use initialization (e.g., needs testing/ECC
   /// initialization).
   ///
   UINT64                RegionState;
-} EFI_SMRAM_DESCRIPTOR;
+} EFI_MMRAM_DESCRIPTOR;
+
+typedef EFI_MMRAM_DESCRIPTOR  EFI_SMRAM_DESCRIPTOR;
 
 typedef enum {
   EFI_PCD_TYPE_8,
@@ -176,4 +176,20 @@ VOID
   IN OUT VOID  *Buffer
   );
 
+/**
+  The function prototype for invoking a function on an Application Processor.
+
+  This definition is used by the UEFI MM MP Serices Protocol.
+
+  @param[in] ProcedureArgument    The pointer to private data buffer.
+
+  @retval EFI_SUCCESS             Excutive the procedure successfully
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_AP_PROCEDURE2)(
+  IN VOID  *ProcedureArgument
+);
+
 #endif
diff --git a/MdePkg/Include/Pi/PiPeiCis.h b/MdePkg/Include/Pi/PiPeiCis.h
index 3963aa030d27..3f25f58c957e 100644
--- a/MdePkg/Include/Pi/PiPeiCis.h
+++ b/MdePkg/Include/Pi/PiPeiCis.h
@@ -1,18 +1,11 @@
 /** @file
   PI PEI master include file. This file should match the PI spec.
 
-Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                            
-                                           
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
-  PI Version 1.4a.
+  PI Version 1.7.
 
 **/
 
@@ -24,22 +17,22 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
 ///
 /// The handles of EFI FV.
-/// 
+///
 typedef VOID    *EFI_PEI_FV_HANDLE;
 
 ///
 /// The handles of EFI FFS.
-/// 
+///
 typedef VOID    *EFI_PEI_FILE_HANDLE;
 
 ///
 /// Declare the forward reference data structure for EFI_PEI_SERVICE.
-/// 
+///
 typedef struct _EFI_PEI_SERVICES          EFI_PEI_SERVICES;
 
 ///
 /// Declare the forward reference data structure for EFI_PEI_NOTIFY_DESCRIPTOR.
-/// 
+///
 typedef struct _EFI_PEI_NOTIFY_DESCRIPTOR EFI_PEI_NOTIFY_DESCRIPTOR;
 
 
@@ -48,8 +41,8 @@ typedef struct _EFI_PEI_NOTIFY_DESCRIPTOR EFI_PEI_NOTIFY_DESCRIPTOR;
 
 
 /**
-  The PEI Dispatcher will invoke each PEIM one time.  During this pass, the PEI 
-  Dispatcher will pass control to the PEIM at the AddressOfEntryPoint in the PE Header. 
+  The PEI Dispatcher will invoke each PEIM one time.  During this pass, the PEI
+  Dispatcher will pass control to the PEIM at the AddressOfEntryPoint in the PE Header.
 
   @param  FileHandle       Pointer to the FFS file header.
   @param  PeiServices      Describes the list of possible PEI Services.
@@ -95,7 +88,7 @@ EFI_STATUS
 
 ///
 /// The data structure through which a PEIM describes available services to the PEI Foundation.
-/// 
+///
 typedef struct {
   ///
   /// This field is a set of flags describing the characteristics of this imported table entry.
@@ -112,10 +105,10 @@ typedef struct {
   VOID      *Ppi;
 } EFI_PEI_PPI_DESCRIPTOR;
 
-/// 
-/// The data structure in a given PEIM that tells the PEI 
+///
+/// The data structure in a given PEIM that tells the PEI
 /// Foundation where to invoke the notification service.
-/// 
+///
 struct _EFI_PEI_NOTIFY_DESCRIPTOR {
   ///
   /// Details if the type of notification are callback or dispatch.
@@ -147,9 +140,9 @@ typedef union {
 } EFI_PEI_DESCRIPTOR;
 
 /**
-  This service is the first one provided by the PEI Foundation.  This function 
-  installs an interface in the PEI PPI database by GUID.  The purpose of the 
-  service is to publish an interface that other parties can use to call 
+  This service is the first one provided by the PEI Foundation.  This function
+  installs an interface in the PEI PPI database by GUID.  The purpose of the
+  service is to publish an interface that other parties can use to call
   additional PEIMs.
 
   @param  PeiServices      An indirect pointer to the EFI_PEI_SERVICES table
@@ -157,8 +150,8 @@ typedef union {
   @param  PpiList          A pointer to the list of interfaces that the caller shall install.
 
   @retval EFI_SUCCESS           The interface was successfully installed.
-  @retval EFI_INVALID_PARAMETER The PpiList pointer is NULL or Any of the PEI PPI 
-                                descriptors in the list do not have the 
+  @retval EFI_INVALID_PARAMETER The PpiList pointer is NULL or Any of the PEI PPI
+                                descriptors in the list do not have the
                                 EFI_PEI_PPI_DESCRIPTOR_PPI bit set in the Flags field.
   @retval EFI_OUT_OF_RESOURCES  There is no additional space in the PPI database.
 
@@ -171,10 +164,10 @@ EFI_STATUS
   );
 
 /**
-  This function reinstalls an interface in the PEI PPI database by GUID. 
-  The purpose of the service is to publish an interface that other parties 
-  can use to replace a same-named interface in the protocol database 
-  with a different interface. 
+  This function reinstalls an interface in the PEI PPI database by GUID.
+  The purpose of the service is to publish an interface that other parties
+  can use to replace a same-named interface in the protocol database
+  with a different interface.
 
   @param  PeiServices      An indirect pointer to the EFI_PEI_SERVICES table
                            published by the PEI Foundation.
@@ -182,7 +175,7 @@ EFI_STATUS
   @param  NewPpi           A pointer to the new interfaces that the caller shall install.
 
   @retval EFI_SUCCESS           The interface was successfully installed.
-  @retval EFI_INVALID_PARAMETER The PpiList pointer is NULL or Any of the PEI PPI descriptors in the 
+  @retval EFI_INVALID_PARAMETER The PpiList pointer is NULL or Any of the PEI PPI descriptors in the
                                 list do not have the EFI_PEI_PPI_DESCRIPTOR_PPI bit set in the Flags field.
   @retval EFI_OUT_OF_RESOURCES  There is no additional space in the PPI database.
   @retval EFI_NOT_FOUND         The PPI for which the reinstallation was requested has not been installed.
@@ -197,7 +190,7 @@ EFI_STATUS
   );
 
 /**
-  This function locates an interface in the PEI PPI database by GUID. 
+  This function locates an interface in the PEI PPI database by GUID.
 
   @param  PeiServices      An indirect pointer to the EFI_PEI_SERVICES published by the PEI Foundation.
   @param  Guid             A pointer to the GUID whose corresponding interface needs to be found.
@@ -220,17 +213,17 @@ EFI_STATUS
   );
 
 /**
-  This function installs a notification service to be called back when a 
-  given interface is installed or reinstalled.  The purpose of the service 
-  is to publish an interface that other parties can use to call additional PPIs 
+  This function installs a notification service to be called back when a
+  given interface is installed or reinstalled.  The purpose of the service
+  is to publish an interface that other parties can use to call additional PPIs
   that may materialize later.
 
   @param  PeiServices      An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation
   @param  NotifyList       A pointer to the list of notification interfaces that the caller shall install.
 
   @retval EFI_SUCCESS           The interface was successfully installed.
-  @retval EFI_INVALID_PARAMETER The PpiList pointer is NULL, or any of the PEI PPI descriptors in the 
-                                list do not have the EFI_PEI_PPI_DESCRIPTOR_PPI bit set in the Flags field.
+  @retval EFI_INVALID_PARAMETER The PpiList pointer is NULL, or any of the PEI PPI descriptors in the
+                                list do not have the EFI_PEI_PPI_DESCRIPTOR_NOTIFY_TYPES bit set in the Flags field.
   @retval EFI_OUT_OF_RESOURCES  There is no additional space in the PPI database.
 
 **/
@@ -274,7 +267,7 @@ EFI_STATUS
   );
 
 /**
-  This function returns the pointer to the list of Hand-Off Blocks (HOBs) in memory. 
+  This function returns the pointer to the list of Hand-Off Blocks (HOBs) in memory.
 
   @param  PeiServices      An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation
   @param  HobList          A pointer to the list of HOBs that the PEI Foundation will initialize
@@ -312,8 +305,8 @@ EFI_STATUS
   );
 
 /**
-  The purpose of the service is to abstract the capability of the PEI 
-  Foundation to discover instances of firmware volumes in the system. 
+  The purpose of the service is to abstract the capability of the PEI
+  Foundation to discover instances of firmware volumes in the system.
 
   This service enables PEIMs to discover additional firmware volumes. The PEI Foundation uses this
   service to abstract the locations and formats of various firmware volumes. These volumes include
@@ -449,18 +442,23 @@ EFI_STATUS
   );
 
 /**
-  The purpose of the service is to publish an interface that allows 
+  The purpose of the service is to publish an interface that allows
   PEIMs to allocate memory ranges that are managed by the PEI Foundation.
 
+  Prior to InstallPeiMemory() being called, PEI will allocate pages from the heap.
+  After InstallPeiMemory() is called, PEI will allocate pages within the region
+  of memory provided by InstallPeiMemory() service in a best-effort fashion.
+  Location-specific allocations are not managed by the PEI foundation code.
+
   @param  PeiServices      An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation.
   @param  MemoryType       The type of memory to allocate.
   @param  Pages            The number of contiguous 4 KB pages to allocate.
-  @param  Memory           A pointer to a physical address. On output, the address is set to the base 
+  @param  Memory           A pointer to a physical address. On output, the address is set to the base
                            of the page range that was allocated.
 
   @retval EFI_SUCCESS           The memory range was successfully allocated.
   @retval EFI_OUT_OF_RESOURCES  The pages could not be allocated.
-  @retval EFI_INVALID_PARAMETER The type is not equal to EfiLoaderCode, EfiLoaderData, EfiRuntimeServicesCode, 
+  @retval EFI_INVALID_PARAMETER The type is not equal to EfiLoaderCode, EfiLoaderData, EfiRuntimeServicesCode,
                                 EfiRuntimeServicesData, EfiBootServicesCode, EfiBootServicesData,
                                 EfiACPIReclaimMemory, EfiReservedMemoryType, or EfiACPIMemoryNVS.
 
@@ -475,7 +473,28 @@ EFI_STATUS
   );
 
 /**
-  The purpose of this service is to publish an interface that 
+  Frees memory pages.
+
+  @param[in] PeiServices        An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation.
+  @param[in] Memory             The base physical address of the pages to be freed.
+  @param[in] Pages              The number of contiguous 4 KB pages to free.
+
+  @retval EFI_SUCCESS           The requested pages were freed.
+  @retval EFI_INVALID_PARAMETER Memory is not a page-aligned address or Pages is invalid.
+  @retval EFI_NOT_FOUND         The requested memory pages were not allocated with
+                                AllocatePages().
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_FREE_PAGES) (
+  IN CONST EFI_PEI_SERVICES     **PeiServices,
+  IN EFI_PHYSICAL_ADDRESS       Memory,
+  IN UINTN                      Pages
+  );
+
+/**
+  The purpose of this service is to publish an interface that
   allows PEIMs to allocate memory ranges that are managed by the PEI Foundation.
 
   @param  PeiServices      An indirect pointer to the EFI_PEI_SERVICES table published by the PEI Foundation.
@@ -571,7 +590,7 @@ EFI_STATUS
 
   This service resets the entire platform, including all processors
   and devices, and reboots the system.
-  This service will never return EFI_SUCCESS.  
+  This service will never return EFI_SUCCESS.
 
   @param  PeiServices      An indirect pointer to the EFI_PEI_SERVICES
                            table published by the PEI Foundation.
@@ -590,14 +609,12 @@ EFI_STATUS
 
   @param[in] ResetType      The type of reset to perform.
   @param[in] ResetStatus    The status code for the reset.
-  @param[in] DataSize       The size, in bytes, of WatchdogData.
+  @param[in] DataSize       The size, in bytes, of ResetData.
   @param[in] ResetData      For a ResetType of EfiResetCold, EfiResetWarm, or EfiResetShutdown
                             the data buffer starts with a Null-terminated string, optionally
                             followed by additional binary data. The string is a description
                             that the caller may use to further indicate the reason for the
-                            system reset. ResetData is only valid if ResetStatus is something
-                            other than EFI_SUCCESS unless the ResetType is EfiResetPlatformSpecific
-                            where a minimum amount of ResetData is always required.
+                            system reset.
 
 **/
 typedef
@@ -713,7 +730,7 @@ typedef struct {
   @retval EFI_INVALID_PARAMETER   FileHandle does not
                                   represent a valid file.
   @retval EFI_INVALID_PARAMETER   FileInfo is NULL.
-  
+
 **/
 typedef
 EFI_STATUS
@@ -813,7 +830,7 @@ EFI_STATUS
 
   @param  FileHandle            PEIM's file handle. Must be the currently
                                 executing PEIM.
-  
+
   @retval EFI_SUCCESS           The PEIM was successfully registered for
                                 shadowing.
   @retval EFI_ALREADY_STARTED   The PEIM was previously
@@ -833,10 +850,10 @@ EFI_STATUS
 // PEI Specification Revision information
 //
 #define PEI_SPECIFICATION_MAJOR_REVISION  1
-#define PEI_SPECIFICATION_MINOR_REVISION  40
+#define PEI_SPECIFICATION_MINOR_REVISION  70
 ///
-/// Specification inconsistency here: 
-/// In the PI1.0 spec, PEI_SERVICES_SIGNATURE is defined as 0x5652455320494550. But 
+/// Specification inconsistency here:
+/// In the PI1.0 spec, PEI_SERVICES_SIGNATURE is defined as 0x5652455320494550. But
 /// to pass a multiple tool chain, it appends an ULL.
 ///
 //
@@ -844,14 +861,14 @@ EFI_STATUS
 //
 #define PEI_SERVICES_SIGNATURE  0x5652455320494550ULL
 ///
-/// Specification inconsistency here: 
-/// In the PI1.0 specification, there is a typo error in PEI_SERVICES_REVISION. In the specification the defintion is 
+/// Specification inconsistency here:
+/// In the PI1.0 specification, there is a typo error in PEI_SERVICES_REVISION. In the specification the defintion is
 /// #define ((PEI_SPECIFICATION_MAJOR_REVISION<<16) |(PEI_SPECIFICATION_MINOR_REVISION))
 /// and it should be as follows:
 ///
 #define PEI_SERVICES_REVISION   ((PEI_SPECIFICATION_MAJOR_REVISION<<16) | (PEI_SPECIFICATION_MINOR_REVISION))
 
-/// 
+///
 /// EFI_PEI_SERVICES is a collection of functions whose implementation is provided by the PEI
 /// Foundation. These services fall into various classes, including the following:
 /// - Managing the boot mode
@@ -929,6 +946,7 @@ struct _EFI_PEI_SERVICES {
   EFI_PEI_FFS_FIND_SECTION_DATA3  FindSectionData3;
   EFI_PEI_FFS_GET_FILE_INFO2      FfsGetFileInfo2;
   EFI_PEI_RESET2_SYSTEM           ResetSystem2;
+  EFI_PEI_FREE_PAGES              FreePages;
 };
 
 
@@ -936,63 +954,63 @@ struct _EFI_PEI_SERVICES {
 /// EFI_SEC_PEI_HAND_OFF structure holds information about
 /// PEI core's operating environment, such as the size of location of
 /// temporary RAM, the stack location and BFV location.
-/// 
+///
 typedef struct _EFI_SEC_PEI_HAND_OFF {
   ///
   /// Size of the data structure.
-  /// 
+  ///
   UINT16  DataSize;
 
   ///
-  /// Points to the first byte of the boot firmware volume, 
-  /// which the PEI Dispatcher should search for 
+  /// Points to the first byte of the boot firmware volume,
+  /// which the PEI Dispatcher should search for
   /// PEI modules.
-  /// 
+  ///
   VOID    *BootFirmwareVolumeBase;
 
   ///
   /// Size of the boot firmware volume, in bytes.
-  /// 
+  ///
   UINTN   BootFirmwareVolumeSize;
 
   ///
   /// Points to the first byte of the temporary RAM.
-  /// 
+  ///
   VOID    *TemporaryRamBase;
 
   ///
   /// Size of the temporary RAM, in bytes.
-  /// 
+  ///
   UINTN   TemporaryRamSize;
 
   ///
-  /// Points to the first byte of the temporary RAM 
-  /// available for use by the PEI Foundation. The area 
-  /// described by PeiTemporaryRamBase and PeiTemporaryRamSize 
+  /// Points to the first byte of the temporary RAM
+  /// available for use by the PEI Foundation. The area
+  /// described by PeiTemporaryRamBase and PeiTemporaryRamSize
   /// must not extend outside beyond the area described by
   /// TemporaryRamBase & TemporaryRamSize. This area should not
-  /// overlap with the area reported by StackBase and 
+  /// overlap with the area reported by StackBase and
   /// StackSize.
   ///
   VOID    *PeiTemporaryRamBase;
 
   ///
-  /// The size of the available temporary RAM available for 
+  /// The size of the available temporary RAM available for
   /// use by the PEI Foundation, in bytes.
-  /// 
+  ///
   UINTN   PeiTemporaryRamSize;
 
   ///
-  /// Points to the first byte of the stack. 
-  /// This are may be part of the memory described by 
-  /// TemporaryRamBase and TemporaryRamSize 
+  /// Points to the first byte of the stack.
+  /// This are may be part of the memory described by
+  /// TemporaryRamBase and TemporaryRamSize
   /// or may be an entirely separate area.
-  /// 
+  ///
   VOID    *StackBase;
 
   ///
   /// Size of the stack, in bytes.
-  /// 
+  ///
   UINTN   StackSize;
 } EFI_SEC_PEI_HAND_OFF;
 
@@ -1004,13 +1022,14 @@ typedef struct _EFI_SEC_PEI_HAND_OFF {
   allows the SEC phase to pass information about the stack,
   temporary RAM and the Boot Firmware Volume. In addition, it also
   allows the SEC phase to pass services and data forward for use
-  during the PEI phase in the form of one or more PPIs. There is
-  no limit to the number of additional PPIs that can be passed
-  from SEC into the PEI Foundation. As part of its initialization
-  phase, the PEI Foundation will add these SEC-hosted PPIs to its
-  PPI database such that both the PEI Foundation and any modules
-  can leverage the associated service calls and/or code in these
-  early PPIs.
+  during the PEI phase in the form of one or more PPIs. These PPI's
+  will be installed and/or immediately signaled if they are
+  notification type. There is no limit to the number of additional
+  PPIs that can be passed from SEC into the PEI Foundation. As part
+  of its initialization phase, the PEI Foundation will add these
+  SEC-hosted PPIs to its PPI database such that both the PEI
+  Foundation and any modules can leverage the associated service
+  calls and/or code in these early PPIs.
 
   @param SecCoreData    Points to a data structure containing
                         information about the PEI core's
diff --git a/MdePkg/Include/Pi/PiS3BootScript.h b/MdePkg/Include/Pi/PiS3BootScript.h
index 466f084ee0e5..b1c4de28596d 100644
--- a/MdePkg/Include/Pi/PiS3BootScript.h
+++ b/MdePkg/Include/Pi/PiS3BootScript.h
@@ -1,15 +1,9 @@
 /** @file
-  This file contains the boot script defintions that are shared between the 
+  This file contains the boot script defintions that are shared between the
   Boot Script Executor PPI and the Boot Script Save Protocol.
 
-  Copyright (c) 2009, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/Pi/PiSmmCis.h b/MdePkg/Include/Pi/PiSmmCis.h
index 7e8cd5f54500..f081dc2aaf8d 100644
--- a/MdePkg/Include/Pi/PiSmmCis.h
+++ b/MdePkg/Include/Pi/PiSmmCis.h
@@ -2,35 +2,25 @@
   Common definitions in the Platform Initialization Specification version 1.4a
   VOLUME 4 System Management Mode Core Interface version.
 
-  Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
 #ifndef _PI_SMMCIS_H_
 #define _PI_SMMCIS_H_
 
-#include <Pi/PiMultiPhase.h>
+#include <Pi/PiMmCis.h>
 #include <Protocol/SmmCpuIo2.h>
 
 typedef struct _EFI_SMM_SYSTEM_TABLE2  EFI_SMM_SYSTEM_TABLE2;
-
-///
-/// The System Management System Table (SMST) signature
-///
-#define SMM_SMST_SIGNATURE            SIGNATURE_32 ('S', 'M', 'S', 'T')
-///
-/// The System Management System Table (SMST) revision is 1.4
-///
-#define SMM_SPECIFICATION_MAJOR_REVISION  1
-#define SMM_SPECIFICATION_MINOR_REVISION  40
-#define EFI_SMM_SYSTEM_TABLE2_REVISION    ((SMM_SPECIFICATION_MAJOR_REVISION<<16) | (SMM_SPECIFICATION_MINOR_REVISION))
+//
+// Define new MM related definition introduced by PI 1.5.
+//
+#define  SMM_SMST_SIGNATURE                MM_MMST_SIGNATURE
+#define  SMM_SPECIFICATION_MAJOR_REVISION  MM_SPECIFICATION_MAJOR_REVISION
+#define  SMM_SPECIFICATION_MINOR_REVISION  MM_SPECIFICATION_MINOR_REVISION
+#define  EFI_SMM_SYSTEM_TABLE2_REVISION    EFI_MM_SYSTEM_TABLE_REVISION
 
 /**
   Adds, updates, or removes a configuration table entry from the System Management System Table.
@@ -53,160 +43,19 @@ typedef struct _EFI_SMM_SYSTEM_TABLE2  EFI_SMM_SYSTEM_TABLE2;
 typedef
 EFI_STATUS
 (EFIAPI *EFI_SMM_INSTALL_CONFIGURATION_TABLE2)(
-  IN CONST EFI_SMM_SYSTEM_TABLE2  *SystemTable,
-  IN CONST EFI_GUID               *Guid,
-  IN VOID                         *Table,
-  IN UINTN                        TableSize
-  );
-
-/**
-  This service lets the caller to get one distinct application processor (AP) to execute
-  a caller-provided code stream while in SMM.
-
-  @param[in]     Procedure       A pointer to the code stream to be run on the designated
-                                 AP of the system.
-  @param[in]     CpuNumber       The zero-based index of the processor number of the AP
-                                 on which the code stream is supposed to run.
-  @param[in,out] ProcArguments   Allows the caller to pass a list of parameters to the code
-                                 that is run by the AP.
-
-  @retval EFI_SUCCESS            The call was successful and the return parameters are valid.
-  @retval EFI_INVALID_PARAMETER  The input arguments are out of range.
-  @retval EFI_INVALID_PARAMETER  The CPU requested is not available on this SMI invocation.
-  @retval EFI_INVALID_PARAMETER  The CPU cannot support an additional service invocation.
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_SMM_STARTUP_THIS_AP)(
-  IN EFI_AP_PROCEDURE  Procedure,
-  IN UINTN             CpuNumber,
-  IN OUT VOID          *ProcArguments OPTIONAL
-  );
-
-/**
-  Function prototype for protocol install notification.
-
-  @param[in] Protocol   Points to the protocol's unique identifier.
-  @param[in] Interface  Points to the interface instance.
-  @param[in] Handle     The handle on which the interface was installed.
-
-  @return Status Code
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_SMM_NOTIFY_FN)(
-  IN CONST EFI_GUID  *Protocol,
-  IN VOID            *Interface,
-  IN EFI_HANDLE      Handle
-  );
-
-/**
-  Register a callback function be called when a particular protocol interface is installed.
-
-  The SmmRegisterProtocolNotify() function creates a registration Function that is to be 
-  called whenever a protocol interface is installed for Protocol by 
-  SmmInstallProtocolInterface().
-  If Function == NULL and Registration is an existing registration, then the callback is unhooked.
-
-  @param[in]  Protocol          The unique ID of the protocol for which the event is to be registered.
-  @param[in]  Function          Points to the notification function.
-  @param[out] Registration      A pointer to a memory location to receive the registration value.
-
-  @retval EFI_SUCCESS           Successfully returned the registration record
-                                that has been added or unhooked.
-  @retval EFI_INVALID_PARAMETER Protocol is NULL or Registration is NULL.
-  @retval EFI_OUT_OF_RESOURCES  Not enough memory resource to finish the request.
-  @retval EFI_NOT_FOUND         If the registration is not found when Function == NULL.
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_SMM_REGISTER_PROTOCOL_NOTIFY)(
-  IN  CONST EFI_GUID     *Protocol,
-  IN  EFI_SMM_NOTIFY_FN  Function,
-  OUT VOID               **Registration
+  IN CONST EFI_SMM_SYSTEM_TABLE2    *SystemTable,
+  IN CONST EFI_GUID                 *Guid,
+  IN VOID                           *Table,
+  IN UINTN                          TableSize
   );
 
-/**
-  Manage SMI of a particular type.
-
-  @param[in]     HandlerType     Points to the handler type or NULL for root SMI handlers.
-  @param[in]     Context         Points to an optional context buffer.
-  @param[in,out] CommBuffer      Points to the optional communication buffer.
-  @param[in,out] CommBufferSize  Points to the size of the optional communication buffer.
-
-  @retval EFI_WARN_INTERRUPT_SOURCE_PENDING  Interrupt source was processed successfully but not quiesced.
-  @retval EFI_INTERRUPT_PENDING              One or more SMI sources could not be quiesced.
-  @retval EFI_NOT_FOUND                      Interrupt source was not handled or quiesced.
-  @retval EFI_SUCCESS                        Interrupt source was handled and quiesced.
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_SMM_INTERRUPT_MANAGE)(
-  IN CONST EFI_GUID  *HandlerType,
-  IN CONST VOID      *Context         OPTIONAL,
-  IN OUT VOID        *CommBuffer      OPTIONAL,
-  IN OUT UINTN       *CommBufferSize  OPTIONAL
-  );
-
-/**
-  Main entry point for an SMM handler dispatch or communicate-based callback.
-
-  @param[in]     DispatchHandle  The unique handle assigned to this handler by SmiHandlerRegister().
-  @param[in]     Context         Points to an optional handler context which was specified when the
-                                 handler was registered.
-  @param[in,out] CommBuffer      A pointer to a collection of data in memory that will
-                                 be conveyed from a non-SMM environment into an SMM environment.
-  @param[in,out] CommBufferSize  The size of the CommBuffer.
-
-  @retval EFI_SUCCESS                         The interrupt was handled and quiesced. No other handlers 
-                                              should still be called.
-  @retval EFI_WARN_INTERRUPT_SOURCE_QUIESCED  The interrupt has been quiesced but other handlers should 
-                                              still be called.
-  @retval EFI_WARN_INTERRUPT_SOURCE_PENDING   The interrupt is still pending and other handlers should still 
-                                              be called.
-  @retval EFI_INTERRUPT_PENDING               The interrupt could not be quiesced.
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_SMM_HANDLER_ENTRY_POINT2)(
-  IN EFI_HANDLE  DispatchHandle,
-  IN CONST VOID  *Context         OPTIONAL,
-  IN OUT VOID    *CommBuffer      OPTIONAL,
-  IN OUT UINTN   *CommBufferSize  OPTIONAL
-  );
-
-/**
-  Registers a handler to execute within SMM.
-
-  @param[in]  Handler            Handler service function pointer.
-  @param[in]  HandlerType        Points to the handler type or NULL for root SMI handlers.
-  @param[out] DispatchHandle     On return, contains a unique handle which can be used to later
-                                 unregister the handler function.
-
-  @retval EFI_SUCCESS            SMI handler added successfully.
-  @retval EFI_INVALID_PARAMETER  Handler is NULL or DispatchHandle is NULL.
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_SMM_INTERRUPT_REGISTER)(
-  IN  EFI_SMM_HANDLER_ENTRY_POINT2  Handler,
-  IN  CONST EFI_GUID                *HandlerType OPTIONAL,
-  OUT EFI_HANDLE                    *DispatchHandle
-  );
-
-/**
-  Unregister a handler in SMM.
-
-  @param[in] DispatchHandle      The handle that was specified when the handler was registered.
-
-  @retval EFI_SUCCESS            Handler function was successfully unregistered.
-  @retval EFI_INVALID_PARAMETER  DispatchHandle does not refer to a valid handle.
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_SMM_INTERRUPT_UNREGISTER)(
-  IN EFI_HANDLE  DispatchHandle
-  );
+typedef  EFI_MM_STARTUP_THIS_AP                EFI_SMM_STARTUP_THIS_AP;
+typedef  EFI_MM_NOTIFY_FN                      EFI_SMM_NOTIFY_FN;
+typedef  EFI_MM_REGISTER_PROTOCOL_NOTIFY       EFI_SMM_REGISTER_PROTOCOL_NOTIFY;
+typedef  EFI_MM_INTERRUPT_MANAGE               EFI_SMM_INTERRUPT_MANAGE;
+typedef  EFI_MM_HANDLER_ENTRY_POINT            EFI_SMM_HANDLER_ENTRY_POINT2;
+typedef  EFI_MM_INTERRUPT_REGISTER             EFI_SMM_INTERRUPT_REGISTER;
+typedef  EFI_MM_INTERRUPT_UNREGISTER           EFI_SMM_INTERRUPT_UNREGISTER;
 
 ///
 /// Processor information and functionality needed by SMM Foundation.
@@ -214,24 +63,24 @@ EFI_STATUS
 typedef struct _EFI_SMM_ENTRY_CONTEXT {
   EFI_SMM_STARTUP_THIS_AP  SmmStartupThisAp;
   ///
-  /// A number between zero and the NumberOfCpus field. This field designates which 
+  /// A number between zero and the NumberOfCpus field. This field designates which
   /// processor is executing the SMM Foundation.
   ///
   UINTN                    CurrentlyExecutingCpu;
   ///
-  /// The number of possible processors in the platform.  This is a 1 based 
+  /// The number of possible processors in the platform.  This is a 1 based
   /// counter.  This does not indicate the number of processors that entered SMM.
   ///
   UINTN                    NumberOfCpus;
   ///
-  /// Points to an array, where each element describes the number of bytes in the 
-  /// corresponding save state specified by CpuSaveState. There are always 
-  /// NumberOfCpus entries in the array. 
+  /// Points to an array, where each element describes the number of bytes in the
+  /// corresponding save state specified by CpuSaveState. There are always
+  /// NumberOfCpus entries in the array.
   ///
   UINTN                    *CpuSaveStateSize;
   ///
-  /// Points to an array, where each element is a pointer to a CPU save state. The 
-  /// corresponding element in CpuSaveStateSize specifies the number of bytes in the 
+  /// Points to an array, where each element is a pointer to a CPU save state. The
+  /// corresponding element in CpuSaveStateSize specifies the number of bytes in the
   /// save state area. There are always NumberOfCpus entries in the array.
   ///
   VOID                     **CpuSaveState;
@@ -251,8 +100,8 @@ VOID
 ///
 /// System Management System Table (SMST)
 ///
-/// The System Management System Table (SMST) is a table that contains a collection of common 
-/// services for managing SMRAM allocation and providing basic I/O services. These services are 
+/// The System Management System Table (SMST) is a table that contains a collection of common
+/// services for managing SMRAM allocation and providing basic I/O services. These services are
 /// intended for both preboot and runtime usage.
 ///
 struct _EFI_SMM_SYSTEM_TABLE2 {
@@ -295,7 +144,7 @@ struct _EFI_SMM_SYSTEM_TABLE2 {
   ///
 
   ///
-  /// A number between zero and and the NumberOfCpus field. This field designates 
+  /// A number between zero and and the NumberOfCpus field. This field designates
   /// which processor is executing the SMM infrastructure.
   ///
   UINTN                                CurrentlyExecutingCpu;
@@ -304,14 +153,14 @@ struct _EFI_SMM_SYSTEM_TABLE2 {
   ///
   UINTN                                NumberOfCpus;
   ///
-  /// Points to an array, where each element describes the number of bytes in the 
-  /// corresponding save state specified by CpuSaveState. There are always 
-  /// NumberOfCpus entries in the array. 
+  /// Points to an array, where each element describes the number of bytes in the
+  /// corresponding save state specified by CpuSaveState. There are always
+  /// NumberOfCpus entries in the array.
   ///
   UINTN                                *CpuSaveStateSize;
   ///
-  /// Points to an array, where each element is a pointer to a CPU save state. The 
-  /// corresponding element in CpuSaveStateSize specifies the number of bytes in the 
+  /// Points to an array, where each element is a pointer to a CPU save state. The
+  /// corresponding element in CpuSaveStateSize specifies the number of bytes in the
   /// save state area. There are always NumberOfCpus entries in the array.
   ///
   VOID                                 **CpuSaveState;
@@ -325,8 +174,8 @@ struct _EFI_SMM_SYSTEM_TABLE2 {
   ///
   UINTN                                NumberOfTableEntries;
   ///
-  /// A pointer to the UEFI Configuration Tables. The number of entries in the table is 
-  /// NumberOfTableEntries. 
+  /// A pointer to the UEFI Configuration Tables. The number of entries in the table is
+  /// NumberOfTableEntries.
   ///
   EFI_CONFIGURATION_TABLE              *SmmConfigurationTable;
 
diff --git a/MdePkg/Include/Pi/PiSmmCommunicationAcpiTable.h b/MdePkg/Include/Pi/PiSmmCommunicationAcpiTable.h
deleted file mode 100644
index a683299b6abb..000000000000
--- a/MdePkg/Include/Pi/PiSmmCommunicationAcpiTable.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/** @file
-  PI SMM Communication ACPI Table Definition.
-
-Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __PI_SMM_COMMUNICATION_ACPI_TABLE__
-#define __PI_SMM_COMMUNICATION_ACPI_TABLE__
-
-#include <Uefi/UefiAcpiDataTable.h>
-
-#endif
diff --git a/MdePkg/Include/Pi/PiStatusCode.h b/MdePkg/Include/Pi/PiStatusCode.h
index adb70ca2050f..e484f2027f5c 100644
--- a/MdePkg/Include/Pi/PiStatusCode.h
+++ b/MdePkg/Include/Pi/PiStatusCode.h
@@ -1,17 +1,11 @@
 /** @file
   StatusCode related definitions in PI.
 
-Copyright (c) 2009 - 2013, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                            
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
-  These status codes are defined in UEFI Platform Initialization Specification 1.2, 
+  These status codes are defined in UEFI Platform Initialization Specification 1.2,
   Volume 3: Shared Architectural Elements.
 
 **/
@@ -133,7 +127,7 @@ typedef struct {
 #define EFI_SOFTWARE        0x03000000
 ///@}
 
-/// 
+///
 /// Computing Unit Subclass definitions.
 /// Values of 8-127 are reserved for future use by this specification.
 /// Values of 128-255 are reserved for OEM use.
@@ -346,6 +340,7 @@ typedef struct {
 #define EFI_CHIPSET_EC_BAD_BATTERY      (EFI_SUBCLASS_SPECIFIC | 0x00000000)
 #define EFI_CHIPSET_EC_DXE_NB_ERROR     (EFI_SUBCLASS_SPECIFIC | 0x00000001)
 #define EFI_CHIPSET_EC_DXE_SB_ERROR     (EFI_SUBCLASS_SPECIFIC | 0x00000002)
+#define EFI_CHIPSET_EC_INTRUDER_DETECT  (EFI_SUBCLASS_SPECIFIC | 0x00000003)
 ///@}
 
 ///
@@ -367,6 +362,7 @@ typedef struct {
 #define EFI_PERIPHERAL_AUDIO_OUTPUT     (EFI_PERIPHERAL | 0x000A0000)
 #define EFI_PERIPHERAL_LCD_DEVICE       (EFI_PERIPHERAL | 0x000B0000)
 #define EFI_PERIPHERAL_NETWORK          (EFI_PERIPHERAL | 0x000C0000)
+#define EFI_PERIPHERAL_DOCKING          (EFI_PERIPHERAL | 0x000D0000)
 ///@}
 
 ///
@@ -381,6 +377,7 @@ typedef struct {
 #define EFI_P_PC_ENABLE           0x00000004
 #define EFI_P_PC_RECONFIG         0x00000005
 #define EFI_P_PC_DETECTED         0x00000006
+#define EFI_P_PC_REMOVED          0x00000007
 ///@}
 
 //
@@ -470,8 +467,9 @@ typedef struct {
 /// Peripheral Class Keyboard Subclass Error Code definitions.
 ///
 ///@{
-#define EFI_P_KEYBOARD_EC_LOCKED    (EFI_SUBCLASS_SPECIFIC | 0x00000000)
-#define EFI_P_KEYBOARD_EC_STUCK_KEY (EFI_SUBCLASS_SPECIFIC | 0x00000001)
+#define EFI_P_KEYBOARD_EC_LOCKED      (EFI_SUBCLASS_SPECIFIC | 0x00000000)
+#define EFI_P_KEYBOARD_EC_STUCK_KEY   (EFI_SUBCLASS_SPECIFIC | 0x00000001)
+#define EFI_P_KEYBOARD_EC_BUFFER_FULL (EFI_SUBCLASS_SPECIFIC | 0x00000002)
 ///@}
 
 ///
@@ -768,6 +766,7 @@ typedef struct {
 #define EFI_SW_PEI_PC_RECOVERY_AUTO   (EFI_SUBCLASS_SPECIFIC | 0x00000004)
 #define EFI_SW_PEI_PC_S3_BOOT_SCRIPT  (EFI_SUBCLASS_SPECIFIC | 0x00000005)
 #define EFI_SW_PEI_PC_OS_WAKE         (EFI_SUBCLASS_SPECIFIC | 0x00000006)
+#define EFI_SW_PEI_PC_S3_STARTED      (EFI_SUBCLASS_SPECIFIC | 0x00000007)
 ///@}
 
 ///
@@ -790,6 +789,11 @@ typedef struct {
 #define EFI_SW_DXE_BS_PC_LEGACY_BOOT_EVENT            (EFI_SUBCLASS_SPECIFIC | 0x00000002)
 #define EFI_SW_DXE_BS_PC_EXIT_BOOT_SERVICES_EVENT     (EFI_SUBCLASS_SPECIFIC | 0x00000003)
 #define EFI_SW_DXE_BS_PC_VIRTUAL_ADDRESS_CHANGE_EVENT (EFI_SUBCLASS_SPECIFIC | 0x00000004)
+#define EFI_SW_DXE_BS_PC_VARIABLE_SERVICES_INIT       (EFI_SUBCLASS_SPECIFIC | 0x00000005)
+#define EFI_SW_DXE_BS_PC_VARIABLE_RECLAIM             (EFI_SUBCLASS_SPECIFIC | 0x00000006)
+#define EFI_SW_DXE_BS_PC_ATTEMPT_BOOT_ORDER_EVENT     (EFI_SUBCLASS_SPECIFIC | 0x00000007)
+#define EFI_SW_DXE_BS_PC_CONFIG_RESET                 (EFI_SUBCLASS_SPECIFIC | 0x00000008)
+#define EFI_SW_DXE_BS_PC_CSM_INIT                     (EFI_SUBCLASS_SPECIFIC | 0x00000009)
 ///@}
 
 //
@@ -979,6 +983,8 @@ typedef struct {
 #define EFI_SW_EC_PWD_CLR_REQUEST         0x0000000F
 #define EFI_SW_EC_PWD_CLEARED             0x00000010
 #define EFI_SW_EC_EVENT_LOG_FULL          0x00000011
+#define EFI_SW_EC_WRITE_PROTECTED         0x00000012
+#define EFI_SW_EC_FV_CORRUPTED            0x00000013
 ///@}
 
 //
@@ -1010,6 +1016,8 @@ typedef struct {
 #define EFI_SW_PEI_EC_S3_RESUME_FAILED             (EFI_SUBCLASS_SPECIFIC | 0x00000005)
 #define EFI_SW_PEI_EC_RECOVERY_PPI_NOT_FOUND       (EFI_SUBCLASS_SPECIFIC | 0x00000006)
 #define EFI_SW_PEI_EC_RECOVERY_FAILED              (EFI_SUBCLASS_SPECIFIC | 0x00000007)
+#define EFI_SW_PEI_EC_S3_RESUME_ERROR              (EFI_SUBCLASS_SPECIFIC | 0x00000008)
+#define EFI_SW_PEI_EC_INVALID_CAPSULE              (EFI_SUBCLASS_SPECIFIC | 0x00000009)
 ///@}
 
 ///
@@ -1186,9 +1194,9 @@ typedef struct {
 /// definitions in the EFI specification.
 ///
 ///@{
-#define EFI_SW_EC_ARM_RESET                          EXCEPT_ARM_RESET 
-#define EFI_SW_EC_ARM_UNDEFINED_INSTRUCTION          EXCEPT_ARM_UNDEFINED_INSTRUCTION 
-#define EFI_SW_EC_ARM_SOFTWARE_INTERRUPT             EXCEPT_ARM_SOFTWARE_INTERRUPT 
+#define EFI_SW_EC_ARM_RESET                          EXCEPT_ARM_RESET
+#define EFI_SW_EC_ARM_UNDEFINED_INSTRUCTION          EXCEPT_ARM_UNDEFINED_INSTRUCTION
+#define EFI_SW_EC_ARM_SOFTWARE_INTERRUPT             EXCEPT_ARM_SOFTWARE_INTERRUPT
 #define EFI_SW_EC_ARM_PREFETCH_ABORT                 EXCEPT_ARM_PREFETCH_ABORT
 #define EFI_SW_EC_ARM_DATA_ABORT                     EXCEPT_ARM_DATA_ABORT
 #define EFI_SW_EC_ARM_RESERVED                       EXCEPT_ARM_RESERVED
diff --git a/MdePkg/Include/PiDxe.h b/MdePkg/Include/PiDxe.h
index 57ac130d4522..32aa1083c7de 100644
--- a/MdePkg/Include/PiDxe.h
+++ b/MdePkg/Include/PiDxe.h
@@ -2,14 +2,8 @@
 
   Root include file for Mde Package DXE_CORE, DXE, RUNTIME, SMM, SAL type modules.
 
-Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/PiMm.h b/MdePkg/Include/PiMm.h
new file mode 100644
index 000000000000..006c285fce3b
--- /dev/null
+++ b/MdePkg/Include/PiMm.h
@@ -0,0 +1,19 @@
+/** @file
+
+  Root include file for Mde Package MM modules.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __PI_MM_H__
+#define __PI_MM_H__
+
+#include <Uefi/UefiBaseType.h>
+#include <Uefi/UefiSpec.h>
+
+#include <Pi/PiMmCis.h>
+
+#endif
+
diff --git a/MdePkg/Include/PiPei.h b/MdePkg/Include/PiPei.h
index d35341251e63..277d8c85f365 100644
--- a/MdePkg/Include/PiPei.h
+++ b/MdePkg/Include/PiPei.h
@@ -4,16 +4,10 @@
 
   This is the include file for any module of type PEIM. PEIM
   modules only use types defined via this include file and can
-  be ported easily to any environment. 
-
-Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  be ported easily to any environment.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/PiSmm.h b/MdePkg/Include/PiSmm.h
index bc7129ac5062..3db3c41c083e 100644
--- a/MdePkg/Include/PiSmm.h
+++ b/MdePkg/Include/PiSmm.h
@@ -2,14 +2,8 @@
 
   Root include file for Mde Package SMM modules.
 
-Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -20,7 +14,6 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #include <Uefi/UefiSpec.h>
 
 #include <Pi/PiSmmCis.h>
-#include <Pi/PiSmmCommunicationAcpiTable.h>
 
 #endif
 
diff --git a/MdePkg/Include/Ppi/BlockIo.h b/MdePkg/Include/Ppi/BlockIo.h
index 7331855f5742..220c5ba1371e 100644
--- a/MdePkg/Include/Ppi/BlockIo.h
+++ b/MdePkg/Include/Ppi/BlockIo.h
@@ -1,27 +1,21 @@
 /** @file
-  Provides the services required to access a block I/O device during PEI recovery 
+  Provides the services required to access a block I/O device during PEI recovery
   boot mode.
 
-  The Recovery Module PPI and the Device Recovery Module PPI are device neutral. 
-  This PPI is device specific and addresses the most common form of recovery 
+  The Recovery Module PPI and the Device Recovery Module PPI are device neutral.
+  This PPI is device specific and addresses the most common form of recovery
   media-block I/O devices such as legacy floppy, CD-ROM, or IDE devices.
 
-  The Recovery Block I/O PPI is used to access block devices. Because the Recovery 
-  Block I/O PPIs that are provided by the PEI ATAPI driver and PEI legacy floppy 
+  The Recovery Block I/O PPI is used to access block devices. Because the Recovery
+  Block I/O PPIs that are provided by the PEI ATAPI driver and PEI legacy floppy
   driver are the same, here we define a set of general PPIs for both drivers to use.
-  
-Copyright (c) 2007 - 2015, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                            
 
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
-  This PPI is defined in UEFI Platform Initialization Specification 1.2 Volume 1: 
-  Pre-EFI Initalization Core Interface.
+  This PPI is defined in UEFI Platform Initialization Specification 1.2 Volume 1:
+  Pre-EFI Initialization Core Interface.
 
 **/
 
@@ -50,7 +44,7 @@ typedef UINT64  EFI_PEI_LBA;
 /// EFI_PEI_BLOCK_DEVICE_TYPE
 ///
 typedef enum {
-  LegacyFloppy  = 0,   ///< The recovery device is a floppy. 
+  LegacyFloppy  = 0,   ///< The recovery device is a floppy.
   IdeCDROM      = 1,   ///< The recovery device is an IDE CD-ROM
   IdeLS120      = 2,   ///< The recovery device is an IDE LS-120
   UsbMassStorage= 3,   ///< The recovery device is a USB Mass Storage device
@@ -61,22 +55,22 @@ typedef enum {
 } EFI_PEI_BLOCK_DEVICE_TYPE;
 
 ///
-/// Specification inconsistency here: 
+/// Specification inconsistency here:
 /// PEI_BLOCK_IO_MEDIA has been changed to EFI_PEI_BLOCK_IO_MEDIA.
-/// Inconsistency exists in UEFI Platform Initialization Specification 1.2 
-/// Volume 1: Pre-EFI Initalization Core Interface, where all referrences to 
-/// this structure name are with the "EFI_" prefix, except for the definition 
-/// which is without "EFI_".  So the name of PEI_BLOCK_IO_MEDIA is taken as the 
-/// exception, and EFI_PEI_BLOCK_IO_MEDIA is used to comply with most of 
+/// Inconsistency exists in UEFI Platform Initialization Specification 1.2
+/// Volume 1: Pre-EFI Initialization Core Interface, where all references to
+/// this structure name are with the "EFI_" prefix, except for the definition
+/// which is without "EFI_".  So the name of PEI_BLOCK_IO_MEDIA is taken as the
+/// exception, and EFI_PEI_BLOCK_IO_MEDIA is used to comply with most of
 /// the specification.
 ///
 typedef struct {
   ///
-  /// The type of media device being referenced by DeviceIndex. 
+  /// The type of media device being referenced by DeviceIndex.
   ///
   EFI_PEI_BLOCK_DEVICE_TYPE  DeviceType;
   ///
-  /// A flag that indicates if media is present. This flag is always set for 
+  /// A flag that indicates if media is present. This flag is always set for
   /// nonremovable media devices.
   ///
   BOOLEAN                    MediaPresent;
@@ -93,16 +87,16 @@ typedef struct {
 /**
   Gets the count of block I/O devices that one specific block driver detects.
 
-  This function is used for getting the count of block I/O devices that one 
+  This function is used for getting the count of block I/O devices that one
   specific block driver detects.  To the PEI ATAPI driver, it returns the number
-  of all the detected ATAPI devices it detects during the enumeration process. 
-  To the PEI legacy floppy driver, it returns the number of all the legacy 
-  devices it finds during its enumeration process. If no device is detected, 
-  then the function will return zero.  
-  
-  @param[in]  PeiServices          General-purpose services that are available 
+  of all the detected ATAPI devices it detects during the enumeration process.
+  To the PEI legacy floppy driver, it returns the number of all the legacy
+  devices it finds during its enumeration process. If no device is detected,
+  then the function will return zero.
+
+  @param[in]  PeiServices          General-purpose services that are available
                                    to every PEIM.
-  @param[in]  This                 Indicates the EFI_PEI_RECOVERY_BLOCK_IO_PPI 
+  @param[in]  This                 Indicates the EFI_PEI_RECOVERY_BLOCK_IO_PPI
                                    instance.
   @param[out] NumberBlockDevices   The number of block I/O devices discovered.
 
@@ -120,41 +114,41 @@ EFI_STATUS
 /**
   Gets a block device's media information.
 
-  This function will provide the caller with the specified block device's media 
-  information. If the media changes, calling this function will update the media 
+  This function will provide the caller with the specified block device's media
+  information. If the media changes, calling this function will update the media
   information accordingly.
 
   @param[in]  PeiServices   General-purpose services that are available to every
                             PEIM
   @param[in]  This          Indicates the EFI_PEI_RECOVERY_BLOCK_IO_PPI instance.
-  @param[in]  DeviceIndex   Specifies the block device to which the function wants 
-                            to talk. Because the driver that implements Block I/O 
-                            PPIs will manage multiple block devices, the PPIs that 
-                            want to talk to a single device must specify the 
+  @param[in]  DeviceIndex   Specifies the block device to which the function wants
+                            to talk. Because the driver that implements Block I/O
+                            PPIs will manage multiple block devices, the PPIs that
+                            want to talk to a single device must specify the
                             device index that was assigned during the enumeration
-                            process. This index is a number from one to 
+                            process. This index is a number from one to
                             NumberBlockDevices.
-  @param[out] MediaInfo     The media information of the specified block media.  
-                            The caller is responsible for the ownership of this 
+  @param[out] MediaInfo     The media information of the specified block media.
+                            The caller is responsible for the ownership of this
                             data structure.
 
-  @par Note: 
-      The MediaInfo structure describes an enumeration of possible block device 
-      types.  This enumeration exists because no device paths are actually passed 
-      across interfaces that describe the type or class of hardware that is publishing 
+  @par Note:
+      The MediaInfo structure describes an enumeration of possible block device
+      types.  This enumeration exists because no device paths are actually passed
+      across interfaces that describe the type or class of hardware that is publishing
       the block I/O interface. This enumeration will allow for policy decisions
-      in the Recovery PEIM, such as "Try to recover from legacy floppy first, 
-      LS-120 second, CD-ROM third." If there are multiple partitions abstracted 
-      by a given device type, they should be reported in ascending order; this 
-      order also applies to nested partitions, such as legacy MBR, where the 
-      outermost partitions would have precedence in the reporting order. The 
-      same logic applies to systems such as IDE that have precedence relationships 
-      like "Master/Slave" or "Primary/Secondary". The master device should be 
+      in the Recovery PEIM, such as "Try to recover from legacy floppy first,
+      LS-120 second, CD-ROM third." If there are multiple partitions abstracted
+      by a given device type, they should be reported in ascending order; this
+      order also applies to nested partitions, such as legacy MBR, where the
+      outermost partitions would have precedence in the reporting order. The
+      same logic applies to systems such as IDE that have precedence relationships
+      like "Master/Slave" or "Primary/Secondary". The master device should be
       reported first, the slave second.
-  
-  @retval EFI_SUCCESS        Media information about the specified block device 
+
+  @retval EFI_SUCCESS        Media information about the specified block device
                              was obtained successfully.
-  @retval EFI_DEVICE_ERROR   Cannot get the media information due to a hardware 
+  @retval EFI_DEVICE_ERROR   Cannot get the media information due to a hardware
                              error.
 
 **/
@@ -170,31 +164,31 @@ EFI_STATUS
 /**
   Reads the requested number of blocks from the specified block device.
 
-  The function reads the requested number of blocks from the device. All the 
+  The function reads the requested number of blocks from the device. All the
   blocks are read, or an error is returned. If there is no media in the device,
   the function returns EFI_NO_MEDIA.
 
-  @param[in]  PeiServices   General-purpose services that are available to 
+  @param[in]  PeiServices   General-purpose services that are available to
                             every PEIM.
   @param[in]  This          Indicates the EFI_PEI_RECOVERY_BLOCK_IO_PPI instance.
-  @param[in]  DeviceIndex   Specifies the block device to which the function wants 
-                            to talk. Because the driver that implements Block I/O 
-                            PPIs will manage multiple block devices, PPIs that 
-                            want to talk to a single device must specify the device 
-                            index that was assigned during the enumeration process. 
+  @param[in]  DeviceIndex   Specifies the block device to which the function wants
+                            to talk. Because the driver that implements Block I/O
+                            PPIs will manage multiple block devices, PPIs that
+                            want to talk to a single device must specify the device
+                            index that was assigned during the enumeration process.
                             This index is a number from one to NumberBlockDevices.
   @param[in]  StartLBA      The starting logical block address (LBA) to read from
                             on the device
   @param[in]  BufferSize    The size of the Buffer in bytes. This number must be
                             a multiple of the intrinsic block size of the device.
   @param[out] Buffer        A pointer to the destination buffer for the data.
-                            The caller is responsible for the ownership of the 
+                            The caller is responsible for the ownership of the
                             buffer.
-                         
+
   @retval EFI_SUCCESS             The data was read correctly from the device.
-  @retval EFI_DEVICE_ERROR        The device reported an error while attempting 
+  @retval EFI_DEVICE_ERROR        The device reported an error while attempting
                                   to perform the read operation.
-  @retval EFI_INVALID_PARAMETER   The read request contains LBAs that are not 
+  @retval EFI_INVALID_PARAMETER   The read request contains LBAs that are not
                                   valid, or the buffer is not properly aligned.
   @retval EFI_NO_MEDIA            There is no media in the device.
   @retval EFI_BAD_BUFFER_SIZE     The BufferSize parameter is not a multiple of
@@ -221,12 +215,12 @@ struct _EFI_PEI_RECOVERY_BLOCK_IO_PPI {
   /// Gets the number of block I/O devices that the specific block driver manages.
   ///
   EFI_PEI_GET_NUMBER_BLOCK_DEVICES      GetNumberOfBlockDevices;
-  
+
   ///
   /// Gets the specified media information.
   ///
   EFI_PEI_GET_DEVICE_MEDIA_INFORMATION  GetBlockDeviceMediaInfo;
-  
+
   ///
   /// Reads the requested number of blocks from the specified block device.
   ///
diff --git a/MdePkg/Include/Ppi/BlockIo2.h b/MdePkg/Include/Ppi/BlockIo2.h
index c76b7033e65d..992429488dfa 100644
--- a/MdePkg/Include/Ppi/BlockIo2.h
+++ b/MdePkg/Include/Ppi/BlockIo2.h
@@ -3,17 +3,11 @@
   boot mode.
 
 Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under
-the terms and conditions of the BSD License that accompanies this distribution.
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This PPI is defined in UEFI Platform Initialization Specification 1.4 Volume 1:
-  Pre-EFI Initalization Core Interface.
+  Pre-EFI Initialization Core Interface.
 
 **/
 
diff --git a/MdePkg/Include/Ppi/BootInRecoveryMode.h b/MdePkg/Include/Ppi/BootInRecoveryMode.h
index 8671d5141d80..11b463e8abe8 100644
--- a/MdePkg/Include/Ppi/BootInRecoveryMode.h
+++ b/MdePkg/Include/Ppi/BootInRecoveryMode.h
@@ -1,15 +1,9 @@
 /** @file
-  This PPI is installed by the platform PEIM to designate that a recovery boot 
+  This PPI is installed by the platform PEIM to designate that a recovery boot
   is in progress.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This PPI is introduced in PI Version 1.0.
diff --git a/MdePkg/Include/Ppi/Capsule.h b/MdePkg/Include/Ppi/Capsule.h
index 2cc64c514243..34b3e9bb19e0 100644
--- a/MdePkg/Include/Ppi/Capsule.h
+++ b/MdePkg/Include/Ppi/Capsule.h
@@ -1,15 +1,9 @@
 /** @file
-  Defines the APIs that enable PEI services to work with 
+  Defines the APIs that enable PEI services to work with
   the underlying capsule capabilities of the platform.
 
-Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.      
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This PPI is introduced in PI Version 1.4.
@@ -38,23 +32,23 @@ typedef struct _EFI_PEI_CAPSULE_PPI EFI_PEI_CAPSULE_PPI;
 typedef struct _EFI_PEI_CAPSULE_PPI PEI_CAPSULE_PPI;
 
 /**
-  Upon determining that there is a capsule to operate on, this service 
-  will use a series of EFI_CAPSULE_BLOCK_DESCRIPTOR entries to determine 
-  the current location of the various capsule fragments and coalesce them 
-  into a contiguous region of system memory.   
+  Upon determining that there is a capsule to operate on, this service
+  will use a series of EFI_CAPSULE_BLOCK_DESCRIPTOR entries to determine
+  the current location of the various capsule fragments and coalesce them
+  into a contiguous region of system memory.
 
   @param[in]  PeiServices   Pointer to the PEI Services Table.
   @param[out] MemoryBase    Pointer to the base of a block of memory into which the buffers will be coalesced.
-                            On output, this variable will hold the base address 
+                            On output, this variable will hold the base address
                             of a coalesced capsule.
   @param[out] MemorySize    Size of the memory region pointed to by MemoryBase.
                             On output, this variable will contain the size of the
                             coalesced capsule.
 
-  @retval EFI_NOT_FOUND          If: boot modecould not be determined, or the 
-                                 boot mode is not flash-update, or the capsule descriptors were not found. 
-  @retval EFI_BUFFER_TOO_SMALL   The capsule could not be coalesced in the provided memory region. 
-  @retval EFI_SUCCESS            There was no capsule, or the capsule was processed successfully. 
+  @retval EFI_NOT_FOUND          If: boot mode could not be determined, or the
+                                 boot mode is not flash-update, or the capsule descriptors were not found.
+  @retval EFI_BUFFER_TOO_SMALL   The capsule could not be coalesced in the provided memory region.
+  @retval EFI_SUCCESS            There was no capsule, or the capsule was processed successfully.
 
 **/
 typedef
@@ -66,12 +60,12 @@ EFI_STATUS
   );
 
 /**
-  Determine if a capsule needs to be processed. 
+  Determine if a capsule needs to be processed.
   The means by which the presence of a capsule is determined is platform
-  specific. For example, an implementation could be driven by the presence 
-  of a Capsule EFI Variable containing a list of EFI_CAPSULE_BLOCK_DESCRIPTOR 
+  specific. For example, an implementation could be driven by the presence
+  of a Capsule EFI Variable containing a list of EFI_CAPSULE_BLOCK_DESCRIPTOR
   entries. If present, return EFI_SUCCESS, otherwise return EFI_NOT_FOUND.
-    
+
   @param[in] PeiServices   Pointer to the PEI Services Table.
 
   @retval EFI_SUCCESS     If a capsule is available.
@@ -87,9 +81,9 @@ EFI_STATUS
 /**
   The Capsule PPI service that gets called after memory is available. The
   capsule coalesce function, which must be called first, returns a base
-  address and size. Once the memory init PEIM has discovered memory, 
-  it should call this function and pass in the base address and size 
-  returned by the Coalesce() function. Then this function can create a 
+  address and size. Once the memory init PEIM has discovered memory,
+  it should call this function and pass in the base address and size
+  returned by the Coalesce() function. Then this function can create a
   capsule HOB and return.
 
   @par Notes:
@@ -97,7 +91,7 @@ EFI_STATUS
     actual capsule update.
 
   @param[in] PeiServices   Pointer to the PEI Services Table.
-  @param[in] CapsuleBase   Address returned by the capsule coalesce function. 
+  @param[in] CapsuleBase   Address returned by the capsule coalesce function.
   @param[in] CapsuleSize   Value returned by the capsule coalesce function.
 
   @retval EFI_VOLUME_CORRUPTED   CapsuleBase does not appear to point to a
@@ -110,13 +104,13 @@ EFI_STATUS
 (EFIAPI *EFI_PEI_CAPSULE_CREATE_STATE)(
   IN EFI_PEI_SERVICES  **PeiServices,
   IN VOID              *CapsuleBase,
-  IN UINTN             CapsuleSize  
+  IN UINTN             CapsuleSize
   );
 
 ///
 /// This PPI provides several services in PEI to work with the underlying
-/// capsule capabilities of the platform.  These services include the ability 
-/// for PEI to coalesce a capsule from a scattered set of memory locations 
+/// capsule capabilities of the platform.  These services include the ability
+/// for PEI to coalesce a capsule from a scattered set of memory locations
 /// into a contiguous space in memory, detect if a capsule is present for
 /// processing, and once memory is available, create a HOB for the capsule.
 ///
diff --git a/MdePkg/Include/Ppi/CpuIo.h b/MdePkg/Include/Ppi/CpuIo.h
index 410a75b27b08..fe700d38ced2 100644
--- a/MdePkg/Include/Ppi/CpuIo.h
+++ b/MdePkg/Include/Ppi/CpuIo.h
@@ -1,19 +1,13 @@
 /** @file
-  This PPI provides a set of memory and I/O-based services. 
+  This PPI provides a set of memory and I/O-based services.
   The perspective of the services is that of the processor, not the bus or system.
 
-Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                            
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This PPI is introduced in PI Version 1.0.
-  
+
 **/
 
 #ifndef __PEI_CPUIO_PPI_H__
@@ -86,7 +80,7 @@ typedef struct {
 /**
   8-bit I/O read operations.
 
-  @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
+  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
                           by the PEI Foundation.
   @param[in] This         The pointer to local data for the interface.
   @param[in] Address      The physical address of the access.
@@ -105,7 +99,7 @@ UINT8
 /**
   16-bit I/O read operations.
 
-  @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
+  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
                           by the PEI Foundation.
   @param[in] This         The pointer to local data for the interface.
   @param[in] Address      The physical address of the access.
@@ -124,7 +118,7 @@ UINT16
 /**
   32-bit I/O read operations.
 
-  @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
+  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
                           by the PEI Foundation.
   @param[in] This         The pointer to local data for the interface.
   @param[in] Address      The physical address of the access.
@@ -143,7 +137,7 @@ UINT32
 /**
   64-bit I/O read operations.
 
-  @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
+  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
                           by the PEI Foundation.
   @param[in] This         The pointer to local data for the interface.
   @param[in] Address      The physical address of the access.
@@ -162,7 +156,7 @@ UINT64
 /**
   8-bit I/O write operations.
 
-  @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
+  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
                           by the PEI Foundation.
   @param[in] This         The pointer to local data for the interface.
   @param[in] Address      The physical address of the access.
@@ -181,7 +175,7 @@ VOID
 /**
   16-bit I/O write operations.
 
-  @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
+  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
                           by the PEI Foundation.
   @param[in] This         The pointer to local data for the interface.
   @param[in] Address      The physical address of the access.
@@ -200,7 +194,7 @@ VOID
 /**
   32-bit I/O write operations.
 
-  @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
+  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
                           by the PEI Foundation.
   @param[in] This         The pointer to local data for the interface.
   @param[in] Address      The physical address of the access.
@@ -219,7 +213,7 @@ VOID
 /**
   64-bit I/O write operations.
 
-  @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
+  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
                           by the PEI Foundation.
   @param[in] This         The pointer to local data for the interface.
   @param[in] Address      The physical address of the access.
@@ -238,7 +232,7 @@ VOID
 /**
   8-bit memory read operations.
 
-  @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
+  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
                           by the PEI Foundation.
   @param[in] This         The pointer to local data for the interface.
   @param[in] Address      The physical address of the access.
@@ -257,7 +251,7 @@ UINT8
 /**
   16-bit memory read operations.
 
-  @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
+  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
                           by the PEI Foundation.
   @param[in] This         The pointer to local data for the interface.
   @param[in] Address      The physical address of the access.
@@ -276,7 +270,7 @@ UINT16
 /**
   32-bit memory read operations.
 
-  @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
+  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
                           by the PEI Foundation.
   @param[in] This         The pointer to local data for the interface.
   @param[in] Address      The physical address of the access.
@@ -295,7 +289,7 @@ UINT32
 /**
   64-bit memory read operations.
 
-  @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
+  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
                           by the PEI Foundation.
   @param[in] This         The pointer to local data for the interface.
   @param[in] Address      The physical address of the access.
@@ -314,7 +308,7 @@ UINT64
 /**
   8-bit memory write operations.
 
-  @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
+  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
                           by the PEI Foundation.
   @param[in] This         The pointer to local data for the interface.
   @param[in] Address      The physical address of the access.
@@ -333,7 +327,7 @@ VOID
 /**
   16-bit memory write operations.
 
-  @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
+  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
                           by the PEI Foundation.
   @param[in] This         The pointer to local data for the interface.
   @param[in] Address      The physical address of the access.
@@ -352,7 +346,7 @@ VOID
 /**
   32-bit memory write operations.
 
-  @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
+  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
                           by the PEI Foundation.
   @param[in] This         The pointer to local data for the interface.
   @param[in] Address      The physical address of the access.
@@ -371,7 +365,7 @@ VOID
 /**
   64-bit memory write operations.
 
-  @param[in] PeiServices  An indirect pointer to the PEI Services Table published 
+  @param[in] PeiServices  An indirect pointer to the PEI Services Table published
                           by the PEI Foundation.
   @param[in] This         The pointer to local data for the interface.
   @param[in] Address      The physical address of the access.
@@ -389,7 +383,7 @@ VOID
 
 ///
 /// EFI_PEI_CPU_IO_PPI provides a set of memory and I/O-based services.
-/// The perspective of the services is that of the processor, not that of the 
+/// The perspective of the services is that of the processor, not that of the
 /// bus or system.
 ///
 struct _EFI_PEI_CPU_IO_PPI {
diff --git a/MdePkg/Include/Ppi/Decompress.h b/MdePkg/Include/Ppi/Decompress.h
index 49678e9dbe08..adbe11f57ed4 100644
--- a/MdePkg/Include/Ppi/Decompress.h
+++ b/MdePkg/Include/Ppi/Decompress.h
@@ -1,14 +1,8 @@
 /** @file
-  Provides decompression services to the PEI Foundatoin.
+  Provides decompression services to the PEI Foundation.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This PPI is introduced in PI Version 1.0.
@@ -23,9 +17,9 @@
 
 typedef struct _EFI_PEI_DECOMPRESS_PPI  EFI_PEI_DECOMPRESS_PPI;
 
-/** 
+/**
   Decompress a single compression section in a firmware file.
-                                                               
+
   Decompresses the data in a compressed section and returns it
   as a series of standard PI Firmware File Sections. The
   required memory is allocated from permanent memory.
diff --git a/MdePkg/Include/Ppi/DelayedDispatch.h b/MdePkg/Include/Ppi/DelayedDispatch.h
new file mode 100644
index 000000000000..a51da027b8d9
--- /dev/null
+++ b/MdePkg/Include/Ppi/DelayedDispatch.h
@@ -0,0 +1,85 @@
+/** @file
+    EFI Delayed Dispatch PPI as defined in the PI 1.7 Specification
+
+    Provide timed event service in PEI
+
+    Copyright (c) 2020, American Megatrends International LLC. All rights reserved.
+    SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __DELAYED_DISPATCH_PPI_H__
+#define __DELAYED_DISPATCH_PPI_H__
+
+///
+/// Global ID for EFI_DELAYED_DISPATCH_PPI_GUID
+///
+#define EFI_DELAYED_DISPATCH_PPI_GUID \
+  { \
+    0x869c711d, 0x649c, 0x44fe, { 0x8b, 0x9e, 0x2c, 0xbb, 0x29, 0x11, 0xc3, 0xe6} } \
+  }
+
+
+/**
+  Delayed Dispatch function.  This routine is called sometime after the required
+  delay.  Upon return, if NewDelay is 0, the function is unregistered.  If NewDelay
+  is not zero, this routine will be called again after the new delay period.
+
+  @param[in,out] Context         Pointer to Context. Can be updated by routine.
+  @param[out]    NewDelay        The new delay in us.  Leave at 0 to unregister callback.
+
+**/
+
+typedef
+VOID
+(EFIAPI *EFI_DELAYED_DISPATCH_FUNCTION) (
+  IN OUT UINT64 *Context,
+     OUT UINT32 *NewDelay
+  );
+
+
+///
+/// The forward declaration for EFI_DELAYED_DISPATCH_PPI
+///
+
+typedef  struct _EFI_DELAYED_DISPATCH_PPI  EFI_DELAYED_DISPATCH_PPI;
+
+
+/**
+Register a callback to be called after a minimum delay has occurred.
+
+This service is the single member function of the EFI_DELAYED_DISPATCH_PPI
+
+  @param This           Pointer to the EFI_DELAYED_DISPATCH_PPI instance
+  @param Function       Function to call back
+  @param Context        Context data
+  @param Delay          Delay interval
+
+  @retval EFI_SUCCESS               Function successfully loaded
+  @retval EFI_INVALID_PARAMETER     One of the Arguments is not supported
+  @retval EFI_OUT_OF_RESOURCES      No more entries
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_DELAYED_DISPATCH_REGISTER)(
+  IN  EFI_DELAYED_DISPATCH_PPI      *This,
+  IN  EFI_DELAYED_DISPATCH_FUNCTION  Function,
+  IN  UINT64                     Context,
+  OUT UINT32                     Delay
+  );
+
+
+///
+/// This PPI is a pointer to the Delayed Dispatch Service.
+/// This service will be published by the Pei Foundation. The PEI Foundation
+/// will use this service to relaunch a known function that requests a delayed
+/// execution.
+///
+struct _EFI_DELAYED_DISPATCH_PPI {
+  EFI_DELAYED_DISPATCH_REGISTER      Register;
+};
+
+
+extern EFI_GUID gEfiPeiDelayedDispatchPpiGuid;
+
+#endif
diff --git a/MdePkg/Include/Ppi/DeviceRecoveryModule.h b/MdePkg/Include/Ppi/DeviceRecoveryModule.h
index 6f3a2174ca85..24fcc20d6694 100644
--- a/MdePkg/Include/Ppi/DeviceRecoveryModule.h
+++ b/MdePkg/Include/Ppi/DeviceRecoveryModule.h
@@ -10,18 +10,12 @@
   The module determines the internal search order, with capsule number 1 as the highest load
   priority and number N as the lowest priority.
 
-  Copyright (c) 2007 - 2011, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
-  This PPI is defined in UEFI Platform Initialization Specification 1.2 Volume 1: 
-  Pre-EFI Initalization Core Interface
+  This PPI is defined in UEFI Platform Initialization Specification 1.2 Volume 1:
+  Pre-EFI Initialization Core Interface
 
 **/
 
@@ -39,18 +33,18 @@ typedef struct _EFI_PEI_DEVICE_RECOVERY_MODULE_PPI EFI_PEI_DEVICE_RECOVERY_MODUL
   Returns the number of DXE capsules residing on the device.
 
   This function searches for DXE capsules from the associated device and returns
-  the number and maximum size in bytes of the capsules discovered. Entry 1 is 
-  assumed to be the highest load priority and entry N is assumed to be the lowest 
+  the number and maximum size in bytes of the capsules discovered. Entry 1 is
+  assumed to be the highest load priority and entry N is assumed to be the lowest
   priority.
 
-  @param[in]  PeiServices              General-purpose services that are available 
+  @param[in]  PeiServices              General-purpose services that are available
                                        to every PEIM
   @param[in]  This                     Indicates the EFI_PEI_DEVICE_RECOVERY_MODULE_PPI
                                        instance.
-  @param[out] NumberRecoveryCapsules   Pointer to a caller-allocated UINTN. On 
-                                       output, *NumberRecoveryCapsules contains 
-                                       the number of recovery capsule images 
-                                       available for retrieval from this PEIM 
+  @param[out] NumberRecoveryCapsules   Pointer to a caller-allocated UINTN. On
+                                       output, *NumberRecoveryCapsules contains
+                                       the number of recovery capsule images
+                                       available for retrieval from this PEIM
                                        instance.
 
   @retval EFI_SUCCESS        One or more capsules were discovered.
@@ -72,18 +66,18 @@ EFI_STATUS
   This function gets the size and type of the capsule specified by CapsuleInstance.
 
   @param[in]  PeiServices       General-purpose services that are available to every PEIM
-  @param[in]  This              Indicates the EFI_PEI_DEVICE_RECOVERY_MODULE_PPI 
+  @param[in]  This              Indicates the EFI_PEI_DEVICE_RECOVERY_MODULE_PPI
                                 instance.
-  @param[in]  CapsuleInstance   Specifies for which capsule instance to retrieve 
-                                the information.  This parameter must be between 
-                                one and the value returned by GetNumberRecoveryCapsules() 
+  @param[in]  CapsuleInstance   Specifies for which capsule instance to retrieve
+                                the information.  This parameter must be between
+                                one and the value returned by GetNumberRecoveryCapsules()
                                 in NumberRecoveryCapsules.
-  @param[out] Size              A pointer to a caller-allocated UINTN in which 
-                                the size of the requested recovery module is 
+  @param[out] Size              A pointer to a caller-allocated UINTN in which
+                                the size of the requested recovery module is
                                 returned.
-  @param[out] CapsuleType       A pointer to a caller-allocated EFI_GUID in which 
-                                the type of the requested recovery capsule is 
-                                returned.  The semantic meaning of the value 
+  @param[out] CapsuleType       A pointer to a caller-allocated EFI_GUID in which
+                                the type of the requested recovery capsule is
+                                returned.  The semantic meaning of the value
                                 returned is defined by the implementation.
 
   @retval EFI_SUCCESS        One or more capsules were discovered.
@@ -107,12 +101,12 @@ EFI_STATUS
   This function, by whatever mechanism, retrieves a DXE capsule from some device
   and loads it into memory. Note that the published interface is device neutral.
 
-  @param[in]     PeiServices       General-purpose services that are available 
+  @param[in]     PeiServices       General-purpose services that are available
                                    to every PEIM
   @param[in]     This              Indicates the EFI_PEI_DEVICE_RECOVERY_MODULE_PPI
                                    instance.
   @param[in]     CapsuleInstance   Specifies which capsule instance to retrieve.
-  @param[out]    Buffer            Specifies a caller-allocated buffer in which 
+  @param[out]    Buffer            Specifies a caller-allocated buffer in which
                                    the requested recovery capsule will be returned.
 
   @retval EFI_SUCCESS        The capsule was loaded correctly.
diff --git a/MdePkg/Include/Ppi/DxeIpl.h b/MdePkg/Include/Ppi/DxeIpl.h
index 3d3d1f3c4db1..512a0f63241d 100644
--- a/MdePkg/Include/Ppi/DxeIpl.h
+++ b/MdePkg/Include/Ppi/DxeIpl.h
@@ -2,14 +2,8 @@
   This file declares DXE Initial Program Load PPI.
   When the PEI core is done it calls the DXE IPL PPI to load the DXE Foundation.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This PPI is introduced in PI Version 1.0.
@@ -27,7 +21,7 @@
 typedef struct _EFI_DXE_IPL_PPI EFI_DXE_IPL_PPI;
 
 /**
-  The architectural PPI that the PEI Foundation invokes when 
+  The architectural PPI that the PEI Foundation invokes when
   there are no additional PEIMs to invoke.
 
   This function is invoked by the PEI Foundation.
@@ -46,7 +40,7 @@ typedef struct _EFI_DXE_IPL_PPI EFI_DXE_IPL_PPI;
   @param  HobList        Pointer to the list of Hand-Off Block (HOB) entries.
 
   @retval EFI_SUCCESS    Upon this return code, the PEI Foundation should enter
-                         some exception handling.Under normal circumstances, 
+                         some exception handling.Under normal circumstances,
                          the DXE IPL PPI should not return.
 
 **/
diff --git a/MdePkg/Include/Ppi/EndOfPeiPhase.h b/MdePkg/Include/Ppi/EndOfPeiPhase.h
index b123c79dcd9f..99b4cbee7618 100644
--- a/MdePkg/Include/Ppi/EndOfPeiPhase.h
+++ b/MdePkg/Include/Ppi/EndOfPeiPhase.h
@@ -1,17 +1,11 @@
 /** @file
-  This PPI will be installed at the end of PEI for all boot paths, including 
-  normal, recovery, and S3. It allows for PEIMs to possibly quiesce hardware, 
-  build handoff information for the next phase of execution, 
+  This PPI will be installed at the end of PEI for all boot paths, including
+  normal, recovery, and S3. It allows for PEIMs to possibly quiesce hardware,
+  build handoff information for the next phase of execution,
   or provide some terminal processing behavior.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This PPI is introduced in PI Version 1.0.
diff --git a/MdePkg/Include/Ppi/FirmwareVolume.h b/MdePkg/Include/Ppi/FirmwareVolume.h
index 37eaa2129e8f..296686589ed2 100644
--- a/MdePkg/Include/Ppi/FirmwareVolume.h
+++ b/MdePkg/Include/Ppi/FirmwareVolume.h
@@ -1,14 +1,8 @@
 /** @file
   This file provides functions for accessing a memory-mapped firmware volume of a specific format.
 
-  Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This PPI is from PI Version 1.0 errata.
@@ -22,7 +16,7 @@
 /// The GUID for this PPI is the same as the firmware volume format GUID.
 /// The FV format can be EFI_FIRMWARE_FILE_SYSTEM2_GUID or the GUID for a user-defined
 /// format. The EFI_FIRMWARE_FILE_SYSTEM2_GUID is the PI Firmware Volume format.
-/// 
+///
 typedef struct _EFI_PEI_FIRMWARE_VOLUME_PPI   EFI_PEI_FIRMWARE_VOLUME_PPI;
 
 
@@ -36,15 +30,15 @@ typedef struct _EFI_PEI_FIRMWARE_VOLUME_PPI   EFI_PEI_FIRMWARE_VOLUME_PPI;
   buffer which contains the necessary information for creating
   the firmware volume handle. Normally, these values are derived
   from the EFI_FIRMWARE_VOLUME_INFO_PPI.
-  
-  
+
+
   @param This                   Points to this instance of the
                                 EFI_PEI_FIRMWARE_VOLUME_PPI.
   @param Buffer                 Points to the start of the buffer.
   @param BufferSize             Size of the buffer.
   @param FvHandle               Points to the returned firmware volume
                                 handle. The firmware volume handle must
-                                be unique within the system. 
+                                be unique within the system.
 
   @retval EFI_SUCCESS           Firmware volume handle created.
   @retval EFI_VOLUME_CORRUPTED  Volume was corrupt.
@@ -62,7 +56,7 @@ EFI_STATUS
 /**
   Finds the next file of the specified type.
 
-  This service enables PEI modules to discover additional firmware files. 
+  This service enables PEI modules to discover additional firmware files.
   The FileHandle must be unique within the system.
 
   @param This           Points to this instance of the
@@ -80,20 +74,20 @@ EFI_STATUS
   @retval EFI_SUCCESS   The file was found.
   @retval EFI_NOT_FOUND The file was not found. FileHandle contains NULL.
 
-**/ 
+**/
 typedef
 EFI_STATUS
-(EFIAPI *EFI_PEI_FV_FIND_FILE_TYPE)( 
-  IN     CONST EFI_PEI_FIRMWARE_VOLUME_PPI   *This, 
-  IN     EFI_FV_FILETYPE                     SearchType, 
+(EFIAPI *EFI_PEI_FV_FIND_FILE_TYPE)(
+  IN     CONST EFI_PEI_FIRMWARE_VOLUME_PPI   *This,
+  IN     EFI_FV_FILETYPE                     SearchType,
   IN     EFI_PEI_FV_HANDLE                   FvHandle,
-  IN OUT EFI_PEI_FILE_HANDLE                 *FileHandle 
+  IN OUT EFI_PEI_FILE_HANDLE                 *FileHandle
 );
 
 
 /**
-  Find a file within a volume by its name. 
-  
+  Find a file within a volume by its name.
+
   This service searches for files with a specific name, within
   either the specified firmware volume or all firmware volumes.
 
@@ -131,8 +125,8 @@ EFI_STATUS
 
   This function returns information about a specific
   file, including its file name, type, attributes, starting
-  address and size. 
-   
+  address and size.
+
   @param This                     Points to this instance of the
                                   EFI_PEI_FIRMWARE_VOLUME_PPI.
   @param FileHandle               Handle of the file.
@@ -143,13 +137,13 @@ EFI_STATUS
   @retval EFI_INVALID_PARAMETER   If FileHandle does not
                                   represent a valid file.
   @retval EFI_INVALID_PARAMETER   If FileInfo is NULL.
-  
-**/ 
+
+**/
 typedef
 EFI_STATUS
 (EFIAPI *EFI_PEI_FV_GET_FILE_INFO)(
-  IN  CONST EFI_PEI_FIRMWARE_VOLUME_PPI   *This, 
-  IN  EFI_PEI_FILE_HANDLE                 FileHandle, 
+  IN  CONST EFI_PEI_FIRMWARE_VOLUME_PPI   *This,
+  IN  EFI_PEI_FILE_HANDLE                 FileHandle,
   OUT EFI_FV_FILE_INFO                    *FileInfo
 );
 
@@ -158,7 +152,7 @@ EFI_STATUS
 
   This function returns information about a specific
   file, including its file name, type, attributes, starting
-  address, size and authentication status. 
+  address, size and authentication status.
 
   @param This                     Points to this instance of the
                                   EFI_PEI_FIRMWARE_VOLUME_PPI.
@@ -175,14 +169,14 @@ EFI_STATUS
 typedef
 EFI_STATUS
 (EFIAPI *EFI_PEI_FV_GET_FILE_INFO2)(
-  IN  CONST EFI_PEI_FIRMWARE_VOLUME_PPI   *This, 
+  IN  CONST EFI_PEI_FIRMWARE_VOLUME_PPI   *This,
   IN  EFI_PEI_FILE_HANDLE                 FileHandle,
   OUT EFI_FV_FILE_INFO2                   *FileInfo
 );
 
 /**
   This function returns information about the firmware volume.
-  
+
   @param This                     Points to this instance of the
                                   EFI_PEI_FIRMWARE_VOLUME_PPI.
   @param FvHandle                 Handle to the firmware handle.
@@ -193,21 +187,21 @@ EFI_STATUS
   @retval EFI_INVALID_PARAMETER   FvHandle does not indicate a valid
                                   firmware volume or VolumeInfo is NULL.
 
-**/ 
+**/
 typedef
 EFI_STATUS
 (EFIAPI *EFI_PEI_FV_GET_INFO)(
-  IN  CONST  EFI_PEI_FIRMWARE_VOLUME_PPI   *This, 
-  IN  EFI_PEI_FV_HANDLE                    FvHandle, 
+  IN  CONST  EFI_PEI_FIRMWARE_VOLUME_PPI   *This,
+  IN  EFI_PEI_FV_HANDLE                    FvHandle,
   OUT EFI_FV_INFO                          *VolumeInfo
 );
 
 /**
   Find the next matching section in the firmware file.
-  
+
   This service enables PEI modules to discover sections
   of a given type within a valid file.
-  
+
   @param This             Points to this instance of the
                           EFI_PEI_FIRMWARE_VOLUME_PPI.
   @param SearchType       A filter to find only sections of this
@@ -216,7 +210,7 @@ EFI_STATUS
                           search.
   @param SectionData      Updated upon  return to point to the
                           section found.
-  
+
   @retval EFI_SUCCESS     Section was found.
   @retval EFI_NOT_FOUND   Section of the specified type was not
                           found. SectionData contains NULL.
@@ -291,4 +285,4 @@ struct _EFI_PEI_FIRMWARE_VOLUME_PPI {
 
 extern EFI_GUID gEfiPeiFirmwareVolumePpiGuid;
 
-#endif 
+#endif
diff --git a/MdePkg/Include/Ppi/FirmwareVolumeInfo.h b/MdePkg/Include/Ppi/FirmwareVolumeInfo.h
index b26685519ed3..e10b9c4afc80 100644
--- a/MdePkg/Include/Ppi/FirmwareVolumeInfo.h
+++ b/MdePkg/Include/Ppi/FirmwareVolumeInfo.h
@@ -1,14 +1,8 @@
 /** @file
   This file provides location and format of a firmware volume.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This PPI is introduced in PI Version 1.0.
@@ -26,9 +20,9 @@
 typedef struct _EFI_PEI_FIRMWARE_VOLUME_INFO_PPI  EFI_PEI_FIRMWARE_VOLUME_INFO_PPI;
 
 ///
-///  This PPI describes the location and format of a firmware volume. 
-///  The FvFormat can be EFI_FIRMWARE_FILE_SYSTEM2_GUID or the GUID for 
-///  a user-defined format. The  EFI_FIRMWARE_FILE_SYSTEM2_GUID is 
+///  This PPI describes the location and format of a firmware volume.
+///  The FvFormat can be EFI_FIRMWARE_FILE_SYSTEM2_GUID or the GUID for
+///  a user-defined format. The  EFI_FIRMWARE_FILE_SYSTEM2_GUID is
 ///  the PI Firmware Volume format.
 ///
 struct _EFI_PEI_FIRMWARE_VOLUME_INFO_PPI {
diff --git a/MdePkg/Include/Ppi/FirmwareVolumeInfo2.h b/MdePkg/Include/Ppi/FirmwareVolumeInfo2.h
index 4e2259299a0e..f7b9cde994d8 100644
--- a/MdePkg/Include/Ppi/FirmwareVolumeInfo2.h
+++ b/MdePkg/Include/Ppi/FirmwareVolumeInfo2.h
@@ -1,14 +1,8 @@
 /** @file
   This file provides location, format and authentication status of a firmware volume.
 
-  Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This PPI is introduced in PI Version 1.3 errata.
@@ -26,9 +20,9 @@
 typedef struct _EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI  EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI;
 
 ///
-///  This PPI describes the location and format of a firmware volume. 
-///  The FvFormat can be EFI_FIRMWARE_FILE_SYSTEM2_GUID or the GUID for 
-///  a user-defined format. The  EFI_FIRMWARE_FILE_SYSTEM2_GUID is 
+///  This PPI describes the location and format of a firmware volume.
+///  The FvFormat can be EFI_FIRMWARE_FILE_SYSTEM2_GUID or the GUID for
+///  a user-defined format. The  EFI_FIRMWARE_FILE_SYSTEM2_GUID is
 ///  the PI Firmware Volume format.
 ///
 struct _EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI {
diff --git a/MdePkg/Include/Ppi/Graphics.h b/MdePkg/Include/Ppi/Graphics.h
index 3ae6bef9dfef..d1fca7896bb8 100644
--- a/MdePkg/Include/Ppi/Graphics.h
+++ b/MdePkg/Include/Ppi/Graphics.h
@@ -4,13 +4,7 @@
   other firmware modules.
 
   Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution. The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This PPI is introduced in PI Version 1.4.
diff --git a/MdePkg/Include/Ppi/GuidedSectionExtraction.h b/MdePkg/Include/Ppi/GuidedSectionExtraction.h
index 6eb16daa9543..3ac6503833cd 100644
--- a/MdePkg/Include/Ppi/GuidedSectionExtraction.h
+++ b/MdePkg/Include/Ppi/GuidedSectionExtraction.h
@@ -1,17 +1,11 @@
 /** @file
-  If a GUID-defined section is encountered when doing section extraction, 
-  the PEI Foundation or the EFI_PEI_FILE_LOADER_PPI instance 
-  calls the appropriate instance of the GUIDed Section Extraction PPI 
-  to extract the section stream contained therein. 
+  If a GUID-defined section is encountered when doing section extraction,
+  the PEI Foundation or the EFI_PEI_FILE_LOADER_PPI instance
+  calls the appropriate instance of the GUIDed Section Extraction PPI
+  to extract the section stream contained therein.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This PPI is introduced in PI Version 1.0.
@@ -22,15 +16,15 @@
 #define __EFI_GUIDED_SECTION_EXTRACTION_PPI_H__
 
 //
-// Typically, protocol interface structures are identified 
-// by associating them with a GUID. Each instance of 
-// a protocol with a given GUID must have 
-// the same interface structure. While all instances of 
-// the GUIDed Section Extraction PPI must have 
-// the same interface structure, they do not all have 
-// te same GUID. The GUID that is associated with 
-// an instance of the GUIDed Section Extraction Protocol 
-// is used to correlate it with the GUIDed section type 
+// Typically, protocol interface structures are identified
+// by associating them with a GUID. Each instance of
+// a protocol with a given GUID must have
+// the same interface structure. While all instances of
+// the GUIDed Section Extraction PPI must have
+// the same interface structure, they do not all have
+// te same GUID. The GUID that is associated with
+// an instance of the GUIDed Section Extraction Protocol
+// is used to correlate it with the GUIDed section type
 // that it is intended to process.
 //
 
@@ -39,7 +33,7 @@ typedef struct _EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI   EFI_PEI_GUIDED_SECTION_E
 
 
 /**
-  Processes the input section and returns the data contained therein 
+  Processes the input section and returns the data contained therein
   along with the authentication status.
 
   The ExtractSection() function processes the input section and
@@ -70,7 +64,7 @@ typedef struct _EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI   EFI_PEI_GUIDED_SECTION_E
                                 reflect the status of the extraction operation.
                                 If the function returns anything other than EFI_SUCCESS,
                                 the value of *AuthenticationStatus is undefined.
-  
+
   @retval EFI_SUCCESS           The InputSection was successfully processed and the
                                 section contents were returned.
   @retval EFI_OUT_OF_RESOURCES  The system has insufficient resources to process the request.
@@ -93,7 +87,7 @@ EFI_STATUS
 /// calls the appropriate instance of the GUIDed Section
 /// Extraction PPI to extract the section stream contained
 /// therein.
-///  
+///
 struct _EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI {
   EFI_PEI_EXTRACT_GUIDED_SECTION ExtractSection;
 };
diff --git a/MdePkg/Include/Ppi/I2cMaster.h b/MdePkg/Include/Ppi/I2cMaster.h
index acc4405f746e..e6d14503ecbb 100644
--- a/MdePkg/Include/Ppi/I2cMaster.h
+++ b/MdePkg/Include/Ppi/I2cMaster.h
@@ -1,15 +1,9 @@
 /** @file
-  This PPI manipulates the I2C host controller to perform transactions as a master 
+  This PPI manipulates the I2C host controller to perform transactions as a master
   on the I2C bus using the current state of any switches or multiplexers in the I2C bus.
 
-  Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This PPI is introduced in PI Version 1.3.
@@ -28,16 +22,16 @@ typedef struct _EFI_PEI_I2C_MASTER_PPI EFI_PEI_I2C_MASTER_PPI;
 
 /**
   Set the frequency for the I2C clock line.
-  
+
   @param This                   Pointer to an EFI_PEI_I2C_MASTER_PPI structure.
   @param BusClockHertz          Pointer to the requested I2C bus clock frequency in Hertz.
-                                Upon return this value contains the actual frequency 
+                                Upon return this value contains the actual frequency
                                 in use by the I2C controller.
 
   @retval EFI_SUCCESS           The bus frequency was set successfully.
   @retval EFI_INVALID_PARAMETER BusClockHertz is NULL
   @retval EFI_UNSUPPORTED       The controller does not support this frequency.
-   
+
 **/
 typedef
 EFI_STATUS
@@ -48,12 +42,12 @@ EFI_STATUS
 
 /**
   Reset the I2C controller and configure it for use.
-  
+
   @param  This                  Pointer to an EFI_PEI_I2C_MASTER_PPI structure.
 
   @retval EFI_SUCCESS           The reset completed successfully.
   @retval EFI_DEVICE_ERROR      The reset operation failed.
-   
+
 **/
 typedef
 EFI_STATUS
@@ -63,25 +57,25 @@ EFI_STATUS
 
 /**
   Start an I2C transaction on the host controller.
-  
+
   @param  This                   Pointer to an EFI_PEI_I2C_MASTER_PPI structure.
   @param  SlaveAddress           Address of the device on the I2C bus.
-                                 Set the I2C_ADDRESSING_10_BIT when using 10-bit addresses, 
+                                 Set the I2C_ADDRESSING_10_BIT when using 10-bit addresses,
                                  clear this bit for 7-bit addressing.
-                                 Bits 0-6 are used for 7-bit I2C slave addresses and 
+                                 Bits 0-6 are used for 7-bit I2C slave addresses and
                                  bits 0-9 are used for 10-bit I2C slave addresses.
   @param  RequestPacket          Pointer to an EFI_I2C_REQUEST_PACKET structure describing the I2C transaction.
 
-  @retval EFI_SUCCESS	           The transaction completed successfully.
-  @retval EFI_BAD_BUFFER_SIZE	   The RequestPacket->LengthInBytes value is too large.
-  @retval EFI_DEVICE_ERROR	     There was an I2C error (NACK) during the transaction.
-  @retval EFI_INVALID_PARAMETER	 RequestPacket is NULL
-  @retval EFI_NO_RESPONSE	       The I2C device is not responding to the slave address.
+  @retval EFI_SUCCESS             The transaction completed successfully.
+  @retval EFI_BAD_BUFFER_SIZE     The RequestPacket->LengthInBytes value is too large.
+  @retval EFI_DEVICE_ERROR       There was an I2C error (NACK) during the transaction.
+  @retval EFI_INVALID_PARAMETER   RequestPacket is NULL
+  @retval EFI_NO_RESPONSE         The I2C device is not responding to the slave address.
                                  EFI_DEVICE_ERROR will be returned if the controller cannot distinguish when the NACK occurred.
-  @retval EFI_NOT_FOUND	         Reserved bit set in the SlaveAddress parameter
-  @retval EFI_OUT_OF_RESOURCES	 Insufficient memory for I2C transaction
-  @retval EFI_UNSUPPORTED	       The controller does not support the requested transaction.
-   
+  @retval EFI_NOT_FOUND           Reserved bit set in the SlaveAddress parameter
+  @retval EFI_OUT_OF_RESOURCES   Insufficient memory for I2C transaction
+  @retval EFI_UNSUPPORTED         The controller does not support the requested transaction.
+
 **/
 typedef
 EFI_STATUS
diff --git a/MdePkg/Include/Ppi/IsaHc.h b/MdePkg/Include/Ppi/IsaHc.h
index 16be828ec509..2cbcce28544e 100644
--- a/MdePkg/Include/Ppi/IsaHc.h
+++ b/MdePkg/Include/Ppi/IsaHc.h
@@ -1,14 +1,8 @@
 /** @file
   This PPI opens or closes an I/O aperture in a ISA HOST controller.
 
-  Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This PPI is from PI Version 1.2.1.
@@ -33,10 +27,10 @@ typedef struct _EFI_ISA_HC_PPI *PEFI_ISA_HC_PPI;
   addresses specified by IoAddress to IoAddress + IoLength - 1. It is possible
   that more than one caller may be assigned to the same aperture.
   It may be possible that a single hardware aperture may be used for more than
-  one device. This function tracks the number of times that each aperture is 
-  referenced, and doesa not close the hardware aperture (via CloseIoAperture())
+  one device. This function tracks the number of times that each aperture is
+  referenced, and does not close the hardware aperture (via CloseIoAperture())
   until there are no more references to it.
- 
+
   @param This             A pointer to this instance of the EFI_ISA_HC_PPI.
   @param IoAddress        An unsigned integer that specifies the first byte of
                           the I/O space required.
@@ -74,7 +68,7 @@ EFI_STATUS
                           call to OpenIoAperture().
 
   @retval EFI_SUCCESS   The I/O aperture was closed successfully.
-**/ 
+**/
 typedef
 EFI_STATUS
 (EFIAPI *EFI_PEI_ISA_HC_CLOSE_IO) (
@@ -116,4 +110,4 @@ struct _EFI_ISA_HC_PPI {
 
 extern EFI_GUID gEfiIsaHcPpiGuid;
 
-#endif 
+#endif
diff --git a/MdePkg/Include/Ppi/LoadFile.h b/MdePkg/Include/Ppi/LoadFile.h
index 243976c3c406..3bedf9ab37fa 100644
--- a/MdePkg/Include/Ppi/LoadFile.h
+++ b/MdePkg/Include/Ppi/LoadFile.h
@@ -1,14 +1,8 @@
 /** @file
-  Load image file from fv to memory. 
+  Load image file from fv to memory.
 
-  Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This PPI is introduced in PI Version 1.0.
@@ -29,7 +23,7 @@ typedef struct _EFI_PEI_LOAD_FILE_PPI EFI_PEI_LOAD_FILE_PPI;
 
   This service is the single member function of EFI_LOAD_FILE_PPI.
   This service separates image loading and relocating from the PEI Foundation.
-  
+
   @param This                   Interface pointer that implements
                                 the Load File PPI instance.
   @param FileHandle             File handle of the file to load.
@@ -47,7 +41,7 @@ typedef struct _EFI_PEI_LOAD_FILE_PPI EFI_PEI_LOAD_FILE_PPI;
   @retval EFI_INVALID_PARAMETER EntryPoint was NULL.
   @retval EFI_UNSUPPORTED       An image requires relocations or is not
                                 memory mapped.
-  @retval EFI_WARN_BUFFER_TOO_SMALL 
+  @retval EFI_WARN_BUFFER_TOO_SMALL
                                 There is not enough heap to allocate the requested size.
                                 This will not prevent the XIP image from being invoked.
 
diff --git a/MdePkg/Include/Ppi/LoadImage.h b/MdePkg/Include/Ppi/LoadImage.h
index 59966e068ff1..4077eb422455 100644
--- a/MdePkg/Include/Ppi/LoadImage.h
+++ b/MdePkg/Include/Ppi/LoadImage.h
@@ -1,15 +1,9 @@
 /** @file
-  The file describes the PPI which notifies other drivers 
+  The file describes the PPI which notifies other drivers
   of the PEIM being initialized by the PEI Dispatcher.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This PPI is introduced in PI Version 1.0.
@@ -27,7 +21,7 @@ typedef struct _EFI_PEI_LOADED_IMAGE_PPI  EFI_PEI_LOADED_IMAGE_PPI;
 
 ///
 /// This interface is installed by the PEI Dispatcher after the image has been
-/// loaded and after all security checks have been performed, 
+/// loaded and after all security checks have been performed,
 /// to notify other PEIMs of the files which are being loaded.
 ///
 struct _EFI_PEI_LOADED_IMAGE_PPI {
diff --git a/MdePkg/Include/Ppi/MasterBootMode.h b/MdePkg/Include/Ppi/MasterBootMode.h
index 2d071fa3342b..d3d4b7e712cf 100644
--- a/MdePkg/Include/Ppi/MasterBootMode.h
+++ b/MdePkg/Include/Ppi/MasterBootMode.h
@@ -1,18 +1,12 @@
 /** @file
   This file declares Boot Mode PPI.
 
-  The Master Boot Mode PPI is installed by a PEIM to signal that a final 
-  boot has been determined and set. This signal is useful in that PEIMs 
+  The Master Boot Mode PPI is installed by a PEIM to signal that a final
+  boot has been determined and set. This signal is useful in that PEIMs
   with boot-mode-specific behavior can put this PPI in their dependency expression.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This PPI is introduced in PI Version 1.0.
diff --git a/MdePkg/Include/Ppi/MemoryDiscovered.h b/MdePkg/Include/Ppi/MemoryDiscovered.h
index df7a3d81b615..0109a215cb4f 100644
--- a/MdePkg/Include/Ppi/MemoryDiscovered.h
+++ b/MdePkg/Include/Ppi/MemoryDiscovered.h
@@ -1,18 +1,12 @@
 /** @file
   This file declares Memory Discovered PPI.
 
-  This PPI is published by the PEI Foundation when the main memory is installed. 
+  This PPI is published by the PEI Foundation when the main memory is installed.
   It is essentially a PPI with no associated interface. Its purpose is to be used
-  as a signal for other PEIMs who can register for a notification on its installation. 
+  as a signal for other PEIMs who can register for a notification on its installation.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This PPI is introduced in PI Version 1.0.
diff --git a/MdePkg/Include/Ppi/MmAccess.h b/MdePkg/Include/Ppi/MmAccess.h
new file mode 100644
index 000000000000..6335872ef695
--- /dev/null
+++ b/MdePkg/Include/Ppi/MmAccess.h
@@ -0,0 +1,155 @@
+/** @file
+  EFI MM Access PPI definition.
+
+  This PPI is used to control the visibility of the MMRAM on the platform.
+  The EFI_PEI_MM_ACCESS_PPI abstracts the location and characteristics of MMRAM. The
+  principal functionality found in the memory controller includes the following:
+  - Exposing the MMRAM to all non-MM agents, or the "open" state
+  - Shrouding the MMRAM to all but the MM agents, or the "closed" state
+  - Preserving the system integrity, or "locking" the MMRAM, such that the settings cannot be
+    perturbed by either boot service or runtime agents
+
+  Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  This PPI is introduced in PI Version 1.5.
+
+**/
+
+#ifndef _MM_ACCESS_PPI_H_
+#define _MM_ACCESS_PPI_H_
+
+#define EFI_PEI_MM_ACCESS_PPI_GUID \
+  { 0x268f33a9, 0xcccd, 0x48be, { 0x88, 0x17, 0x86, 0x5, 0x3a, 0xc3, 0x2e, 0xd6 }}
+
+typedef struct _EFI_PEI_MM_ACCESS_PPI  EFI_PEI_MM_ACCESS_PPI;
+
+/**
+  Opens the MMRAM area to be accessible by a PEIM.
+
+  This function "opens" MMRAM so that it is visible while not inside of MM. The function should
+  return EFI_UNSUPPORTED if the hardware does not support hiding of MMRAM. The function
+  should return EFI_DEVICE_ERROR if the MMRAM configuration is locked.
+
+  @param  PeiServices            An indirect pointer to the PEI Services Table published by the PEI Foundation.
+  @param  This                   The EFI_PEI_MM_ACCESS_PPI instance.
+  @param  DescriptorIndex        The region of MMRAM to Open.
+
+  @retval EFI_SUCCESS            The operation was successful.
+  @retval EFI_UNSUPPORTED        The system does not support opening and closing of MMRAM.
+  @retval EFI_DEVICE_ERROR       MMRAM cannot be opened, perhaps because it is locked.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_MM_OPEN)(
+  IN EFI_PEI_SERVICES                **PeiServices,
+  IN EFI_PEI_MM_ACCESS_PPI           *This,
+  IN UINTN                           DescriptorIndex
+  );
+
+/**
+  Inhibits access to the MMRAM.
+
+  This function "closes" MMRAM so that it is not visible while outside of MM. The function should
+  return EFI_UNSUPPORTED if the hardware does not support hiding of MMRAM.
+
+  @param  PeiServices            An indirect pointer to the PEI Services Table published by the PEI Foundation.
+  @param  This                   The EFI_PEI_MM_ACCESS_PPI instance.
+  @param  DescriptorIndex        The region of MMRAM to Close.
+
+  @retval EFI_SUCCESS            The operation was successful.
+  @retval EFI_UNSUPPORTED        The system does not support opening and closing of MMRAM.
+  @retval EFI_DEVICE_ERROR       MMRAM cannot be closed.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_MM_CLOSE)(
+  IN EFI_PEI_SERVICES                **PeiServices,
+  IN EFI_PEI_MM_ACCESS_PPI           *This,
+  IN UINTN                           DescriptorIndex
+  );
+
+/**
+  This function prohibits access to the MMRAM region. This function is usually implemented such
+  that it is a write-once operation.
+
+  @param  PeiServices            An indirect pointer to the PEI Services Table published by the PEI Foundation.
+  @param  This                   The EFI_PEI_MM_ACCESS_PPI instance.
+  @param  DescriptorIndex        The region of MMRAM to Lock.
+
+  @retval EFI_SUCCESS            The operation was successful.
+  @retval EFI_UNSUPPORTED        The system does not support opening and closing of MMRAM.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_MM_LOCK)(
+  IN EFI_PEI_SERVICES                **PeiServices,
+  IN EFI_PEI_MM_ACCESS_PPI           *This,
+  IN UINTN                           DescriptorIndex
+  );
+
+/**
+  Queries the memory controller for the possible regions that will support MMRAM.
+
+  This function describes the MMRAM regions.
+  This data structure forms the contract between the MM_ACCESS and MM_IPL drivers. There is an
+  ambiguity when any MMRAM region is remapped. For example, on some chipsets, some MMRAM
+  regions can be initialized at one physical address but is later accessed at another processor address.
+  There is currently no way for the MM IPL driver to know that it must use two different addresses
+  depending on what it is trying to do. As a result, initial configuration and loading can use the
+  physical address PhysicalStart while MMRAM is open. However, once the region has been
+  closed and needs to be accessed by agents in MM, the CpuStart address must be used.
+  This PPI publishes the available memory that the chipset can shroud for the use of installing code.
+  These regions serve the dual purpose of describing which regions have been open, closed, or locked.
+  In addition, these regions may include overlapping memory ranges, depending on the chipset
+  implementation. The latter might include a chipset that supports T-SEG, where memory near the top
+  of the physical DRAM can be allocated for MMRAM too.
+  The key thing to note is that the regions that are described by the PPI are a subset of the capabilities
+  of the hardware.
+
+  @param  PeiServices            An indirect pointer to the PEI Services Table published by the PEI Foundation.
+  @param  This                   The EFI_PEI_MM_ACCESS_PPI instance.
+  @param  MmramMapSize           A pointer to the size, in bytes, of the MmramMemoryMap buffer. On input, this value is
+                                 the size of the buffer that is allocated by the caller. On output, it is the size of the
+                                 buffer that was returned by the firmware if the buffer was large enough, or, if the
+                                 buffer was too small, the size of the buffer that is needed to contain the map.
+  @param MmramMap                A pointer to the buffer in which firmware places the current memory map. The map is
+                                 an array of EFI_MMRAM_DESCRIPTORs
+
+  @retval EFI_SUCCESS            The chipset supported the given resource.
+  @retval EFI_BUFFER_TOO_SMALL   The MmramMap parameter was too small. The current
+                                 buffer size needed to hold the memory map is returned in
+                                 MmramMapSize.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_MM_CAPABILITIES)(
+  IN EFI_PEI_SERVICES                **PeiServices,
+  IN EFI_PEI_MM_ACCESS_PPI           *This,
+  IN OUT UINTN                       *MmramMapSize,
+  IN OUT EFI_MMRAM_DESCRIPTOR        *MmramMap
+  );
+
+///
+///  EFI MM Access PPI is used to control the visibility of the MMRAM on the platform.
+///  It abstracts the location and characteristics of MMRAM. The platform should report
+///  all MMRAM via EFI_PEI_MM_ACCESS_PPI. The expectation is that the north bridge or
+///  memory controller would publish this PPI.
+///
+struct _EFI_PEI_MM_ACCESS_PPI {
+  EFI_PEI_MM_OPEN          Open;
+  EFI_PEI_MM_CLOSE         Close;
+  EFI_PEI_MM_LOCK          Lock;
+  EFI_PEI_MM_CAPABILITIES  GetCapabilities;
+  BOOLEAN                  LockState;
+  BOOLEAN                  OpenState;
+};
+
+extern EFI_GUID gEfiPeiMmAccessPpiGuid;
+
+#endif
diff --git a/MdePkg/Include/Ppi/MmControl.h b/MdePkg/Include/Ppi/MmControl.h
new file mode 100644
index 000000000000..ecf720d719d4
--- /dev/null
+++ b/MdePkg/Include/Ppi/MmControl.h
@@ -0,0 +1,90 @@
+/** @file
+  EFI MM Control PPI definition.
+
+  This PPI is used initiate synchronous MMI activations. This PPI could be published by a processor
+  driver to abstract the MMI IPI or a driver which abstracts the ASIC that is supporting the APM port.
+  Because of the possibility of performing MMI IPI transactions, the ability to generate this event
+  from a platform chipset agent is an optional capability for both IA-32 and x64-based systems.
+
+  Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  This PPI is introduced in PI Version 1.5.
+
+**/
+
+
+#ifndef _MM_CONTROL_PPI_H_
+#define _MM_CONTROL_PPI_H_
+
+#define EFI_PEI_MM_CONTROL_PPI_GUID \
+  { 0x61c68702, 0x4d7e, 0x4f43, 0x8d, 0xef, 0xa7, 0x43, 0x5, 0xce, 0x74, 0xc5 }
+
+typedef struct _EFI_PEI_MM_CONTROL_PPI  EFI_PEI_MM_CONTROL_PPI;
+
+/**
+  Invokes PPI activation from the PI PEI environment.
+
+  @param  PeiServices           An indirect pointer to the PEI Services Table published by the PEI Foundation.
+  @param  This                  The PEI_MM_CONTROL_PPI instance.
+  @param  ArgumentBuffer        The value passed to the MMI handler. This value corresponds to the
+                                SwMmiInputValue in the RegisterContext parameter for the Register()
+                                function in the EFI_MM_SW_DISPATCH_PROTOCOL and in the Context parameter
+                                in the call to the DispatchFunction
+  @param  ArgumentBufferSize    The size of the data passed in ArgumentBuffer or NULL if ArgumentBuffer is NULL.
+  @param  Periodic              An optional mechanism to periodically repeat activation.
+  @param  ActivationInterval    An optional parameter to repeat at this period one
+                                time or, if the Periodic Boolean is set, periodically.
+
+  @retval EFI_SUCCESS           The MMI has been engendered.
+  @retval EFI_DEVICE_ERROR      The timing is unsupported.
+  @retval EFI_INVALID_PARAMETER The activation period is unsupported.
+  @retval EFI_NOT_STARTED       The MM base service has not been initialized.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_PEI_MM_ACTIVATE) (
+  IN EFI_PEI_SERVICES                                **PeiServices,
+  IN EFI_PEI_MM_CONTROL_PPI                          * This,
+  IN OUT INT8                                        *ArgumentBuffer OPTIONAL,
+  IN OUT UINTN                                       *ArgumentBufferSize OPTIONAL,
+  IN BOOLEAN                                         Periodic OPTIONAL,
+  IN UINTN                                           ActivationInterval OPTIONAL
+  );
+
+/**
+  Clears any system state that was created in response to the Trigger() call.
+
+  @param  PeiServices           General purpose services available to every PEIM.
+  @param  This                  The PEI_MM_CONTROL_PPI instance.
+  @param  Periodic              Optional parameter to repeat at this period one
+                                time or, if the Periodic Boolean is set, periodically.
+
+  @retval EFI_SUCCESS           The MMI has been engendered.
+  @retval EFI_DEVICE_ERROR      The source could not be cleared.
+  @retval EFI_INVALID_PARAMETER The service did not support the Periodic input argument.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PEI_MM_DEACTIVATE) (
+  IN EFI_PEI_SERVICES                      **PeiServices,
+  IN EFI_PEI_MM_CONTROL_PPI                * This,
+  IN BOOLEAN                               Periodic OPTIONAL
+  );
+
+///
+///  The EFI_PEI_MM_CONTROL_PPI is produced by a PEIM. It provides an abstraction of the
+///  platform hardware that generates an MMI. There are often I/O ports that, when accessed, will
+///  generate the MMI. Also, the hardware optionally supports the periodic generation of these signals.
+///
+struct _PEI_MM_CONTROL_PPI {
+  PEI_MM_ACTIVATE    Trigger;
+  PEI_MM_DEACTIVATE  Clear;
+};
+
+extern EFI_GUID gEfiPeiMmControlPpiGuid;
+
+#endif
diff --git a/MdePkg/Include/Ppi/MpServices.h b/MdePkg/Include/Ppi/MpServices.h
index fce4d2dbb81c..b7dfb3bc5865 100644
--- a/MdePkg/Include/Ppi/MpServices.h
+++ b/MdePkg/Include/Ppi/MpServices.h
@@ -3,14 +3,8 @@
   This PPI is installed by some platform or chipset-specific PEIM that abstracts
   handling multiprocessor support.
 
-  Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution. The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This PPI is introduced in PI Version 1.4.
@@ -81,7 +75,7 @@ EFI_STATUS
   );
 
 /**
-  Activate all of the application proessors.
+  Activate all of the application processors.
 
   @param[in] PeiServices          An indirect pointer to the PEI Services Table
                                   published by the PEI Foundation.
@@ -187,7 +181,7 @@ EFI_STATUS
   @retval EFI_UNSUPPORTED         Switching the BSP cannot be completed prior to this
                                   service returning.
   @retval EFI_UNSUPPORTED         Switching the BSP is not supported.
-  @retval EFI_SUCCESS             The calling processor is an AP.
+  @retval EFI_DEVICE_ERROR        The calling processor is an AP.
   @retval EFI_NOT_FOUND           The processor with the handle specified by
                                   ProcessorNumber does not exist.
   @retval EFI_INVALID_PARAMETER   ProcessorNumber specifies the current BSP or a disabled
diff --git a/MdePkg/Include/Ppi/Pcd.h b/MdePkg/Include/Ppi/Pcd.h
index 05b59048d6ae..efd102e78a60 100644
--- a/MdePkg/Include/Ppi/Pcd.h
+++ b/MdePkg/Include/Ppi/Pcd.h
@@ -1,19 +1,13 @@
 /** @file
   Native Platform Configuration Database (PCD) PPI
-  
+
   Different with the EFI_PCD_PPI defined in PI 1.2 specification, the native
-  PCD PPI provide interfaces for dynamic and dynamic-ex type PCD. 
+  PCD PPI provide interfaces for dynamic and dynamic-ex type PCD.
   The interfaces for dynamic type PCD do not require the token space guid as parameter,
   but interfaces for dynamic-ex type PCD require token space guid as parameter.
 
-Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                            
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -29,27 +23,27 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 /**
   Sets the SKU value for subsequent calls to set or get PCD token values.
 
-  SetSku() sets the SKU Id to be used for subsequent calls to set or get PCD values. 
+  SetSku() sets the SKU Id to be used for subsequent calls to set or get PCD values.
   SetSku() is normally called only once by the system.
 
-  For each item (token), the database can hold a single value that applies to all SKUs, 
-  or multiple values, where each value is associated with a specific SKU Id. Items with multiple, 
-  SKU-specific values are called SKU enabled. 
-  
-  The SKU Id of zero is reserved as a default. The valid SkuId range is 1 to 255.  
-  For tokens that are not SKU enabled, the system ignores any set SKU Id and works with the 
-  single value for that token. For SKU-enabled tokens, the system will use the SKU Id set by the 
-  last call to SetSku(). If no SKU Id is set or the currently set SKU Id isn't valid for the specified token, 
-  the system uses the default SKU Id. If the system attempts to use the default SKU Id and no value has been 
+  For each item (token), the database can hold a single value that applies to all SKUs,
+  or multiple values, where each value is associated with a specific SKU Id. Items with multiple,
+  SKU-specific values are called SKU enabled.
+
+  The SKU Id of zero is reserved as a default. The valid SkuId range is 1 to 255.
+  For tokens that are not SKU enabled, the system ignores any set SKU Id and works with the
+  single value for that token. For SKU-enabled tokens, the system will use the SKU Id set by the
+  last call to SetSku(). If no SKU Id is set or the currently set SKU Id isn't valid for the specified token,
+  the system uses the default SKU Id. If the system attempts to use the default SKU Id and no value has been
   set for that Id, the results are unpredictable.
 
-  @param[in]  SkuId The SKU value that will be used when the PCD service will retrieve and 
+  @param[in]  SkuId The SKU value that will be used when the PCD service will retrieve and
               set values associated with a PCD token.
 
   @retval VOID
 
 **/
-typedef 
+typedef
 VOID
 (EFIAPI *PCD_PPI_SET_SKU)(
   IN  UINTN          SkuId
@@ -60,13 +54,13 @@ VOID
 /**
   Retrieves an 8-bit value for a given PCD token.
 
-  Retrieves the current byte-sized value for a PCD token number.  
+  Retrieves the current byte-sized value for a PCD token number.
   If the TokenNumber is invalid, the results are unpredictable.
-  
-  @param[in]  TokenNumber The PCD token number. 
+
+  @param[in]  TokenNumber The PCD token number.
 
   @return The UINT8 value.
-  
+
 **/
 typedef
 UINT8
@@ -79,13 +73,13 @@ UINT8
 /**
   Retrieves a 16-bit value for a given PCD token.
 
-  Retrieves the current 16-bit value for a PCD token number.  
+  Retrieves the current 16-bit value for a PCD token number.
   If the TokenNumber is invalid, the results are unpredictable.
-  
-  @param[in]  TokenNumber The PCD token number. 
+
+  @param[in]  TokenNumber The PCD token number.
 
   @return The UINT16 value.
-  
+
 **/
 typedef
 UINT16
@@ -98,13 +92,13 @@ UINT16
 /**
   Retrieves a 32-bit value for a given PCD token.
 
-  Retrieves the current 32-bit value for a PCD token number.  
+  Retrieves the current 32-bit value for a PCD token number.
   If the TokenNumber is invalid, the results are unpredictable.
-  
-  @param[in]  TokenNumber The PCD token number. 
+
+  @param[in]  TokenNumber The PCD token number.
 
   @return The UINT32 value.
-  
+
 **/
 typedef
 UINT32
@@ -117,13 +111,13 @@ UINT32
 /**
   Retrieves a 64-bit value for a given PCD token.
 
-  Retrieves the current 64-bit value for a PCD token number.  
+  Retrieves the current 64-bit value for a PCD token number.
   If the TokenNumber is invalid, the results are unpredictable.
-  
-  @param[in]  TokenNumber The PCD token number. 
+
+  @param[in]  TokenNumber The PCD token number.
 
   @return The UINT64 value.
-  
+
 **/
 typedef
 UINT64
@@ -136,15 +130,15 @@ UINT64
 /**
   Retrieves a pointer to a value for a given PCD token.
 
-  Retrieves the current pointer to the buffer for a PCD token number.  
-  Do not make any assumptions about the alignment of the pointer that 
-  is returned by this function call.  If the TokenNumber is invalid, 
+  Retrieves the current pointer to the buffer for a PCD token number.
+  Do not make any assumptions about the alignment of the pointer that
+  is returned by this function call.  If the TokenNumber is invalid,
   the results are unpredictable.
 
-  @param[in]  TokenNumber The PCD token number. 
+  @param[in]  TokenNumber The PCD token number.
+
+  @return The pointer to the buffer to be retrieved.
 
-  @return The pointer to the buffer to be retrived.
-  
 **/
 typedef
 VOID *
@@ -157,15 +151,15 @@ VOID *
 /**
   Retrieves a Boolean value for a given PCD token.
 
-  Retrieves the current boolean value for a PCD token number.  
-  Do not make any assumptions about the alignment of the pointer that 
-  is returned by this function call.  If the TokenNumber is invalid, 
+  Retrieves the current boolean value for a PCD token number.
+  Do not make any assumptions about the alignment of the pointer that
+  is returned by this function call.  If the TokenNumber is invalid,
   the results are unpredictable.
 
-  @param[in]  TokenNumber The PCD token number. 
+  @param[in]  TokenNumber The PCD token number.
 
   @return The Boolean value.
-  
+
 **/
 typedef
 BOOLEAN
@@ -178,13 +172,13 @@ BOOLEAN
 /**
   Retrieves the size of the value for a given PCD token.
 
-  Retrieves the current size of a particular PCD token.  
+  Retrieves the current size of a particular PCD token.
   If the TokenNumber is invalid, the results are unpredictable.
 
-  @param[in]  TokenNumber The PCD token number. 
+  @param[in]  TokenNumber The PCD token number.
 
   @return The size of the value for the PCD token.
-  
+
 **/
 typedef
 UINTN
@@ -197,16 +191,16 @@ UINTN
 /**
   Retrieves an 8-bit value for a given PCD token and token space.
 
-  Retrieves the 8-bit value of a particular PCD token.  
+  Retrieves the 8-bit value of a particular PCD token.
   If the TokenNumber is invalid or the token space
-  specified by Guid does not exist, the results are 
+  specified by Guid does not exist, the results are
   unpredictable.
 
   @param[in]  Guid        The token space for the token number.
-  @param[in]  TokenNumber The PCD token number. 
+  @param[in]  TokenNumber The PCD token number.
 
   @return The size 8-bit value for the PCD token.
-  
+
 **/
 typedef
 UINT8
@@ -220,16 +214,16 @@ UINT8
 /**
   Retrieves a 16-bit value for a given PCD token and token space.
 
-  Retrieves the 16-bit value of a particular PCD token.  
+  Retrieves the 16-bit value of a particular PCD token.
   If the TokenNumber is invalid or the token space
-  specified by Guid does not exist, the results are 
+  specified by Guid does not exist, the results are
   unpredictable.
 
   @param[in]  Guid        The token space for the token number.
-  @param[in]  TokenNumber The PCD token number. 
+  @param[in]  TokenNumber The PCD token number.
 
   @return The size 16-bit value for the PCD token.
-  
+
 **/
 typedef
 UINT16
@@ -243,16 +237,16 @@ UINT16
 /**
   Retrieves a 32-bit value for a given PCD token and token space.
 
-  Retrieves the 32-bit value of a particular PCD token.  
+  Retrieves the 32-bit value of a particular PCD token.
   If the TokenNumber is invalid or the token space
-  specified by Guid does not exist, the results are 
+  specified by Guid does not exist, the results are
   unpredictable.
 
   @param[in]  Guid        The token space for the token number.
-  @param[in]  TokenNumber The PCD token number. 
+  @param[in]  TokenNumber The PCD token number.
 
   @return The size 32-bit value for the PCD token.
-  
+
 **/
 typedef
 UINT32
@@ -266,16 +260,16 @@ UINT32
 /**
   Retrieves a 64-bit value for a given PCD token and token space.
 
-  Retrieves the 64-bit value of a particular PCD token.  
+  Retrieves the 64-bit value of a particular PCD token.
   If the TokenNumber is invalid or the token space
-  specified by Guid does not exist, the results are 
+  specified by Guid does not exist, the results are
   unpredictable.
 
   @param[in]  Guid        The token space for the token number.
-  @param[in]  TokenNumber The PCD token number. 
+  @param[in]  TokenNumber The PCD token number.
 
   @return The size 64-bit value for the PCD token.
-  
+
 **/
 typedef
 UINT64
@@ -289,16 +283,16 @@ UINT64
 /**
   Retrieves a pointer to a value for a given PCD token and token space.
 
-  Retrieves the current pointer to the buffer for a PCD token number.  
-  Do not make any assumptions about the alignment of the pointer that 
-  is returned by this function call.  If the TokenNumber is invalid, 
+  Retrieves the current pointer to the buffer for a PCD token number.
+  Do not make any assumptions about the alignment of the pointer that
+  is returned by this function call.  If the TokenNumber is invalid,
   the results are unpredictable.
 
   @param[in]  Guid        The token space for the token number.
-  @param[in]  TokenNumber The PCD token number. 
+  @param[in]  TokenNumber The PCD token number.
+
+  @return The pointer to the buffer to be retrieved.
 
-  @return The pointer to the buffer to be retrived.
-  
 **/
 typedef
 VOID *
@@ -312,16 +306,16 @@ VOID *
 /**
   Retrieves an Boolean value for a given PCD token and token space.
 
-  Retrieves the Boolean value of a particular PCD token.  
+  Retrieves the Boolean value of a particular PCD token.
   If the TokenNumber is invalid or the token space
-  specified by Guid does not exist, the results are 
+  specified by Guid does not exist, the results are
   unpredictable.
 
   @param[in]  Guid The token space for the token number.
-  @param[in]  TokenNumber The PCD token number. 
+  @param[in]  TokenNumber The PCD token number.
 
   @return The size Boolean value for the PCD token.
-  
+
 **/
 typedef
 BOOLEAN
@@ -335,14 +329,14 @@ BOOLEAN
 /**
   Retrieves the size of the value for a given PCD token and token space.
 
-  Retrieves the current size of a particular PCD token.  
+  Retrieves the current size of a particular PCD token.
   If the TokenNumber is invalid, the results are unpredictable.
 
   @param[in]  Guid        The token space for the token number.
-  @param[in]  TokenNumber The PCD token number. 
+  @param[in]  TokenNumber The PCD token number.
 
   @return The size of the value for the PCD token.
-  
+
 **/
 typedef
 UINTN
@@ -356,19 +350,19 @@ UINTN
 /**
   Sets an 8-bit value for a given PCD token.
 
-  When the PCD service sets a value, it will check to ensure that the 
-  size of the value being set is compatible with the Token's existing definition.  
+  When the PCD service sets a value, it will check to ensure that the
+  size of the value being set is compatible with the Token's existing definition.
   If it is not, an error will be returned.
 
-  @param[in]  TokenNumber The PCD token number. 
+  @param[in]  TokenNumber The PCD token number.
   @param[in]  Value       The value to set for the PCD token.
 
   @retval EFI_SUCCESS           The procedure returned successfully.
-  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data 
-                                being set was incompatible with a call to this function.  
+  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data
+                                being set was incompatible with a call to this function.
                                 Use GetSize() to retrieve the size of the target data.
   @retval EFI_NOT_FOUND         The PCD service could not find the requested token number.
-  
+
 **/
 typedef
 EFI_STATUS
@@ -382,19 +376,19 @@ EFI_STATUS
 /**
   Sets a 16-bit value for a given PCD token.
 
-  When the PCD service sets a value, it will check to ensure that the 
-  size of the value being set is compatible with the Token's existing definition.  
+  When the PCD service sets a value, it will check to ensure that the
+  size of the value being set is compatible with the Token's existing definition.
   If it is not, an error will be returned.
 
-  @param[in]  TokenNumber The PCD token number. 
+  @param[in]  TokenNumber The PCD token number.
   @param[in]  Value       The value to set for the PCD token.
 
   @retval EFI_SUCCESS           The procedure returned successfully.
-  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data 
-                                being set was incompatible with a call to this function.  
+  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data
+                                being set was incompatible with a call to this function.
                                 Use GetSize() to retrieve the size of the target data.
   @retval EFI_NOT_FOUND         The PCD service could not find the requested token number.
-  
+
 **/
 typedef
 EFI_STATUS
@@ -408,19 +402,19 @@ EFI_STATUS
 /**
   Sets a 32-bit value for a given PCD token.
 
-  When the PCD service sets a value, it will check to ensure that the 
-  size of the value being set is compatible with the Token's existing definition.  
+  When the PCD service sets a value, it will check to ensure that the
+  size of the value being set is compatible with the Token's existing definition.
   If it is not, an error will be returned.
 
-  @param[in]  TokenNumber The PCD token number. 
+  @param[in]  TokenNumber The PCD token number.
   @param[in]  Value       The value to set for the PCD token.
 
   @retval EFI_SUCCESS           The procedure returned successfully.
-  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data 
-                                being set was incompatible with a call to this function.  
+  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data
+                                being set was incompatible with a call to this function.
                                 Use GetSize() to retrieve the size of the target data.
   @retval EFI_NOT_FOUND         The PCD service could not find the requested token number.
-  
+
 **/
 typedef
 EFI_STATUS
@@ -434,19 +428,19 @@ EFI_STATUS
 /**
   Sets a 64-bit value for a given PCD token.
 
-  When the PCD service sets a value, it will check to ensure that the 
-  size of the value being set is compatible with the Token's existing definition.  
+  When the PCD service sets a value, it will check to ensure that the
+  size of the value being set is compatible with the Token's existing definition.
   If it is not, an error will be returned.
 
-  @param[in]  TokenNumber The PCD token number. 
+  @param[in]  TokenNumber The PCD token number.
   @param[in]  Value       The value to set for the PCD token.
 
   @retval EFI_SUCCESS           The procedure returned successfully.
-  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data 
-                                being set was incompatible with a call to this function.  
+  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data
+                                being set was incompatible with a call to this function.
                                 Use GetSize() to retrieve the size of the target data.
   @retval EFI_NOT_FOUND         The PCD service could not find the requested token number.
-  
+
 **/
 typedef
 EFI_STATUS
@@ -458,23 +452,23 @@ EFI_STATUS
 /**
   Sets a value of a specified size for a given PCD token.
 
-  When the PCD service sets a value, it will check to ensure that the 
-  size of the value being set is compatible with the Token's existing definition.  
+  When the PCD service sets a value, it will check to ensure that the
+  size of the value being set is compatible with the Token's existing definition.
   If it is not, an error will be returned.
 
-  @param[in]      TokenNumber  The PCD token number. 
-  @param[in, out] SizeOfValue  A pointer to the length of the value being set for the PCD token.  
-                               On input, if the SizeOfValue is greater than the maximum size supported 
-                               for this TokenNumber then the output value of SizeOfValue will reflect 
+  @param[in]      TokenNumber  The PCD token number.
+  @param[in, out] SizeOfValue  A pointer to the length of the value being set for the PCD token.
+                               On input, if the SizeOfValue is greater than the maximum size supported
+                               for this TokenNumber then the output value of SizeOfValue will reflect
                                the maximum size supported for this TokenNumber.
   @param[in]      Buffer       The buffer to set for the PCD token.
 
   @retval EFI_SUCCESS           The procedure returned successfully.
-  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data 
-                                being set was incompatible with a call to this function.  
+  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data
+                                being set was incompatible with a call to this function.
                                 Use GetSize() to retrieve the size of the target data.
   @retval EFI_NOT_FOUND         The PCD service could not find the requested token number.
-  
+
 **/
 typedef
 EFI_STATUS
@@ -487,19 +481,19 @@ EFI_STATUS
 /**
   Sets an Boolean value for a given PCD token.
 
-  When the PCD service sets a value, it will check to ensure that the 
-  size of the value being set is compatible with the Token's existing definition.  
+  When the PCD service sets a value, it will check to ensure that the
+  size of the value being set is compatible with the Token's existing definition.
   If it is not, an error will be returned.
 
-  @param[in]  TokenNumber The PCD token number. 
+  @param[in]  TokenNumber The PCD token number.
   @param[in]  Value       The value to set for the PCD token.
 
   @retval EFI_SUCCESS           The procedure returned successfully.
-  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data 
-                                being set was incompatible with a call to this function.  
+  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data
+                                being set was incompatible with a call to this function.
                                 Use GetSize() to retrieve the size of the target data.
   @retval EFI_NOT_FOUND         The PCD service could not find the requested token number.
-  
+
 **/
 typedef
 EFI_STATUS
@@ -513,20 +507,20 @@ EFI_STATUS
 /**
   Sets an 8-bit value for a given PCD token.
 
-  When the PCD service sets a value, it will check to ensure that the 
-  size of the value being set is compatible with the Token's existing definition.  
+  When the PCD service sets a value, it will check to ensure that the
+  size of the value being set is compatible with the Token's existing definition.
   If it is not, an error will be returned.
 
   @param[in]  Guid        The 128-bit unique value that designates the namespace from which to extract the value.
-  @param[in]  TokenNumber The PCD token number. 
+  @param[in]  TokenNumber The PCD token number.
   @param[in]  Value       The value to set for the PCD token.
 
   @retval EFI_SUCCESS           The procedure returned successfully.
-  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data 
-                                being set was incompatible with a call to this function.  
+  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data
+                                being set was incompatible with a call to this function.
                                 Use GetSize() to retrieve the size of the target data.
   @retval EFI_NOT_FOUND         The PCD service could not find the requested token number.
-  
+
 **/
 typedef
 EFI_STATUS
@@ -541,20 +535,20 @@ EFI_STATUS
 /**
   Sets a 16-bit value for a given PCD token.
 
-  When the PCD service sets a value, it will check to ensure that the 
-  size of the value being set is compatible with the Token's existing definition.  
+  When the PCD service sets a value, it will check to ensure that the
+  size of the value being set is compatible with the Token's existing definition.
   If it is not, an error will be returned.
 
   @param[in]  Guid        The 128-bit unique value that designates the namespace from which to extract the value.
-  @param[in]  TokenNumber The PCD token number. 
+  @param[in]  TokenNumber The PCD token number.
   @param[in]  Value       The value to set for the PCD token.
 
   @retval EFI_SUCCESS           The procedure returned successfully.
-  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data 
-                                being set was incompatible with a call to this function.  
+  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data
+                                being set was incompatible with a call to this function.
                                 Use GetSize() to retrieve the size of the target data.
   @retval EFI_NOT_FOUND         The PCD service could not find the requested token number.
-  
+
 **/
 typedef
 EFI_STATUS
@@ -569,20 +563,20 @@ EFI_STATUS
 /**
   Sets a 32-bit value for a given PCD token.
 
-  When the PCD service sets a value, it will check to ensure that the 
-  size of the value being set is compatible with the Token's existing definition.  
+  When the PCD service sets a value, it will check to ensure that the
+  size of the value being set is compatible with the Token's existing definition.
   If it is not, an error will be returned.
 
   @param[in]  Guid        The 128-bit unique value that designates the namespace from which to extract the value.
-  @param[in]  TokenNumber The PCD token number. 
+  @param[in]  TokenNumber The PCD token number.
   @param[in]  Value       The value to set for the PCD token.
 
   @retval EFI_SUCCESS           The procedure returned successfully.
-  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data 
-                                being set was incompatible with a call to this function.  
+  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data
+                                being set was incompatible with a call to this function.
                                 Use GetSize() to retrieve the size of the target data.
   @retval EFI_NOT_FOUND         The PCD service could not find the requested token number.
-  
+
 **/
 typedef
 EFI_STATUS
@@ -597,20 +591,20 @@ EFI_STATUS
 /**
   Sets a 64-bit value for a given PCD token.
 
-  When the PCD service sets a value, it will check to ensure that the 
-  size of the value being set is compatible with the Token's existing definition.  
+  When the PCD service sets a value, it will check to ensure that the
+  size of the value being set is compatible with the Token's existing definition.
   If it is not, an error will be returned.
 
   @param[in]  Guid        The 128-bit unique value that designates the namespace from which to extract the value.
-  @param[in]  TokenNumber The PCD token number. 
+  @param[in]  TokenNumber The PCD token number.
   @param[in]  Value       The value to set for the PCD token.
 
   @retval EFI_SUCCESS           The procedure returned successfully.
-  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data 
-                                being set was incompatible with a call to this function.  
+  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data
+                                being set was incompatible with a call to this function.
                                 Use GetSize() to retrieve the size of the target data.
   @retval EFI_NOT_FOUND         The PCD service could not find the requested token number.
-  
+
 **/
 typedef
 EFI_STATUS
@@ -625,24 +619,24 @@ EFI_STATUS
 /**
   Sets a value of a specified size for a given PCD token.
 
-  When the PCD service sets a value, it will check to ensure that the 
-  size of the value being set is compatible with the Token's existing definition.  
+  When the PCD service sets a value, it will check to ensure that the
+  size of the value being set is compatible with the Token's existing definition.
   If it is not, an error will be returned.
 
   @param[in]      Guid         The 128-bit unique value that designates the namespace from which to extract the value.
-  @param[in]      TokenNumber  The PCD token number. 
-  @param[in, out] SizeOfValue  A pointer to the length of the value being set for the PCD token.  
-                               On input, if the SizeOfValue is greater than the maximum size supported 
-                               for this TokenNumber then the output value of SizeOfValue will reflect 
+  @param[in]      TokenNumber  The PCD token number.
+  @param[in, out] SizeOfValue  A pointer to the length of the value being set for the PCD token.
+                               On input, if the SizeOfValue is greater than the maximum size supported
+                               for this TokenNumber then the output value of SizeOfValue will reflect
                                the maximum size supported for this TokenNumber.
   @param[in]      Buffer       The buffer to set for the PCD token.
 
   @retval EFI_SUCCESS           The procedure returned successfully.
-  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data 
-                                being set was incompatible with a call to this function.  
+  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data
+                                being set was incompatible with a call to this function.
                                 Use GetSize() to retrieve the size of the target data.
   @retval EFI_NOT_FOUND         The PCD service could not find the requested token number.
-  
+
 **/
 typedef
 EFI_STATUS
@@ -656,20 +650,20 @@ EFI_STATUS
 /**
   Sets an Boolean value for a given PCD token.
 
-  When the PCD service sets a value, it will check to ensure that the 
-  size of the value being set is compatible with the Token's existing definition.  
+  When the PCD service sets a value, it will check to ensure that the
+  size of the value being set is compatible with the Token's existing definition.
   If it is not, an error will be returned.
 
   @param[in]  Guid        The 128-bit unique value that designates the namespace from which to extract the value.
-  @param[in]  TokenNumber The PCD token number. 
+  @param[in]  TokenNumber The PCD token number.
   @param[in]  Value       The value to set for the PCD token.
 
   @retval EFI_SUCCESS           The procedure returned successfully.
-  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data 
-                                being set was incompatible with a call to this function.  
+  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data
+                                being set was incompatible with a call to this function.
                                 Use GetSize() to retrieve the size of the target data.
   @retval EFI_NOT_FOUND         The PCD service could not find the requested token number.
-  
+
 **/
 typedef
 EFI_STATUS
@@ -684,11 +678,11 @@ EFI_STATUS
 /**
   Callback on SET function prototype definition.
 
-  This notification function serves two purposes. Firstly, it notifies the module 
-  which did the registration that the value of this PCD token has been set. Secondly, 
-  it provides a mechanism for the module which did the registration to intercept the set 
-  operation and override the value been set if necessary. After the invocation of the 
-  callback function, TokenData will be used by PCD service PEIM to modify the internal data 
+  This notification function serves two purposes. Firstly, it notifies the module
+  which did the registration that the value of this PCD token has been set. Secondly,
+  it provides a mechanism for the module which did the registration to intercept the set
+  operation and override the value been set if necessary. After the invocation of the
+  callback function, TokenData will be used by PCD service PEIM to modify the internal data
   in PCD database.
 
   @param[in]      CallBackGuid  The PCD token GUID being set.
@@ -713,11 +707,11 @@ VOID
 /**
   Specifies a function to be called anytime the value of a designated token is changed.
 
-  @param[in]  TokenNumber The PCD token number. 
+  @param[in]  TokenNumber The PCD token number.
   @param[in]  Guid The 128-bit unique value that designates the namespace from which to extract the value.
-  @param[in]  CallBackFunction The function prototype called when the value associated with the CallBackToken is set.  
+  @param[in]  CallBackFunction The function prototype called when the value associated with the CallBackToken is set.
 
-  @retval EFI_SUCCESS  The PCD service has successfully established a call event 
+  @retval EFI_SUCCESS  The PCD service has successfully established a call event
                         for the CallBackToken requested.
   @retval EFI_NOT_FOUND The PCD service could not find the referenced token number.
 
@@ -735,11 +729,11 @@ EFI_STATUS
 /**
   Cancels a previously set callback function for a particular PCD token number.
 
-  @param[in]  TokenNumber The PCD token number. 
+  @param[in]  TokenNumber The PCD token number.
   @param[in]  Guid The 128-bit unique value that designates the namespace from which to extract the value.
-  @param[in]  CallBackFunction The function prototype called when the value associated with the CallBackToken is set.  
+  @param[in]  CallBackFunction The function prototype called when the value associated with the CallBackToken is set.
 
-  @retval EFI_SUCCESS  The PCD service has successfully established a call event 
+  @retval EFI_SUCCESS  The PCD service has successfully established a call event
                         for the CallBackToken requested.
   @retval EFI_NOT_FOUND The PCD service could not find the referenced token number.
 
@@ -755,31 +749,31 @@ EFI_STATUS
 
 
 /**
-  Retrieves the next valid token number in a given namespace.  
-  
-  This is useful since the PCD infrastructure contains a sparse list of token numbers, 
-  and one cannot a priori know what token numbers are valid in the database. 
-  
-  If TokenNumber is 0 and Guid is not NULL, then the first token from the token space specified by Guid is returned.  
-  If TokenNumber is not 0 and Guid is not NULL, then the next token in the token space specified by Guid is returned.  
-  If TokenNumber is 0 and Guid is NULL, then the first token in the default token space is returned.  
-  If TokenNumber is not 0 and Guid is NULL, then the next token in the default token space is returned.  
-  The token numbers in the default token space may not be related to token numbers in token spaces that are named by Guid.  
-  If the next token number can be retrieved, then it is returned in TokenNumber, and EFI_SUCCESS is returned.  
-  If TokenNumber represents the last token number in the token space specified by Guid, then EFI_NOT_FOUND is returned.  
+  Retrieves the next valid token number in a given namespace.
+
+  This is useful since the PCD infrastructure contains a sparse list of token numbers,
+  and one cannot a priori know what token numbers are valid in the database.
+
+  If TokenNumber is 0 and Guid is not NULL, then the first token from the token space specified by Guid is returned.
+  If TokenNumber is not 0 and Guid is not NULL, then the next token in the token space specified by Guid is returned.
+  If TokenNumber is 0 and Guid is NULL, then the first token in the default token space is returned.
+  If TokenNumber is not 0 and Guid is NULL, then the next token in the default token space is returned.
+  The token numbers in the default token space may not be related to token numbers in token spaces that are named by Guid.
+  If the next token number can be retrieved, then it is returned in TokenNumber, and EFI_SUCCESS is returned.
+  If TokenNumber represents the last token number in the token space specified by Guid, then EFI_NOT_FOUND is returned.
   If TokenNumber is not present in the token space specified by Guid, then EFI_NOT_FOUND is returned.
 
 
-  @param[in]       Guid        The 128-bit unique value that designates the namespace from which to extract the value.  
-                               This is an optional parameter that may be NULL.  If this parameter is NULL, then a request 
+  @param[in]       Guid        The 128-bit unique value that designates the namespace from which to extract the value.
+                               This is an optional parameter that may be NULL.  If this parameter is NULL, then a request
                                is being made to retrieve tokens from the default token space.
   @param[in, out]  TokenNumber A pointer to the PCD token number to use to find the subsequent token number.
-                   
+
   @retval EFI_SUCCESS   The PCD service has retrieved the next valid token number.
   @retval EFI_NOT_FOUND The PCD service could not find data from the requested token number.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *PCD_PPI_GET_NEXT_TOKEN)(
   IN CONST EFI_GUID           *Guid, OPTIONAL
@@ -799,7 +793,7 @@ EFI_STATUS
                             token namespace on the platform. If *Guid is NULL, then the GUID of the first token
                             space of the current platform is returned. If the search cannot locate the next valid
                             token namespace, an error is returned and the value of *Guid is undefined.
- 
+
   @retval  EFI_SUCCESS      The PCD service retrieved the value requested.
   @retval  EFI_NOT_FOUND    The PCD service could not find the next valid token namespace.
 
diff --git a/MdePkg/Include/Ppi/PcdInfo.h b/MdePkg/Include/Ppi/PcdInfo.h
index a06fff13fc76..c199c0063d28 100644
--- a/MdePkg/Include/Ppi/PcdInfo.h
+++ b/MdePkg/Include/Ppi/PcdInfo.h
@@ -2,20 +2,14 @@
   Native Platform Configuration Database (PCD) INFO PPI
 
   The PPI that provides additional information about items that reside in the PCD database.
-  
+
   Different with the EFI_GET_PCD_INFO_PPI defined in PI 1.2.1 specification,
-  the native PCD INFO PPI provide interfaces for dynamic and dynamic-ex type PCD. 
+  the native PCD INFO PPI provide interfaces for dynamic and dynamic-ex type PCD.
   The interfaces for dynamic type PCD do not require the token space guid as parameter,
   but interfaces for dynamic-ex type PCD require token space guid as parameter.
 
-  Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/Ppi/PciCfg2.h b/MdePkg/Include/Ppi/PciCfg2.h
index ea9547875476..17b67a7209a1 100644
--- a/MdePkg/Include/Ppi/PciCfg2.h
+++ b/MdePkg/Include/Ppi/PciCfg2.h
@@ -1,17 +1,11 @@
 /** @file
   This file declares PciCfg2 PPI.
 
-  This ppi Provides platform or chipset-specific access to 
+  This ppi Provides platform or chipset-specific access to
   the PCI configuration space for a specific PCI segment.
 
-  Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This PPI is introduced in PI Version 1.0.
@@ -124,7 +118,7 @@ EFI_STATUS
 
 
 /**
-  Performs a read-modify-write operation on the contents 
+  Performs a read-modify-write operation on the contents
   from a given location in the PCI configuration space.
 
   @param  PeiServices     An indirect pointer to the PEI Services Table
diff --git a/MdePkg/Include/Ppi/PeiCoreFvLocation.h b/MdePkg/Include/Ppi/PeiCoreFvLocation.h
new file mode 100644
index 000000000000..72a308eaf7af
--- /dev/null
+++ b/MdePkg/Include/Ppi/PeiCoreFvLocation.h
@@ -0,0 +1,42 @@
+/** @file
+  Header file for Pei Core FV Location PPI.
+
+  This PPI contains a pointer to the firmware volume which contains the PEI Foundation.
+  If the PEI Foundation does not reside in the BFV, then SEC must pass this PPI as a part
+  of the PPI list provided to the PEI Foundation Entry Point, otherwise the PEI Foundation
+  shall assume that it resides within the BFV.
+
+  Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  This PPI is defined in UEFI Platform Initialization Specification 1.7 Volume 1:
+  Standards
+
+**/
+
+
+#ifndef _EFI_PEI_CORE_FV_LOCATION_H_
+#define _EFI_PEI_CORE_FV_LOCATION_H_
+
+///
+/// Global ID for EFI_PEI_CORE_FV_LOCATION_PPI
+///
+#define EFI_PEI_CORE_FV_LOCATION_GUID \
+  { \
+    0x52888eae, 0x5b10, 0x47d0, {0xa8, 0x7f, 0xb8, 0x22, 0xab, 0xa0, 0xca, 0xf4 } \
+  }
+
+///
+/// This PPI provides location of EFI PeiCoreFv.
+///
+typedef struct {
+  ///
+  /// Pointer to the first byte of the firmware volume which contains the PEI Foundation.
+  ///
+  VOID    *PeiCoreFvLocation;
+} EFI_PEI_CORE_FV_LOCATION_PPI;
+
+extern EFI_GUID gEfiPeiCoreFvLocationPpiGuid;
+
+#endif // _EFI_PEI_CORE_FV_LOCATION_H_
diff --git a/MdePkg/Include/Ppi/PiPcd.h b/MdePkg/Include/Ppi/PiPcd.h
index 41b0c2e18a93..58c3be8fcb10 100644
--- a/MdePkg/Include/Ppi/PiPcd.h
+++ b/MdePkg/Include/Ppi/PiPcd.h
@@ -12,13 +12,7 @@
   firmware component to monitor specific settings and be alerted when a setting is changed.
 
   Copyright (c) 2009 - 2013, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   PI Version 1.2 Vol 3.
diff --git a/MdePkg/Include/Ppi/PiPcdInfo.h b/MdePkg/Include/Ppi/PiPcdInfo.h
index 20571f891b7a..0248b4607c4d 100644
--- a/MdePkg/Include/Ppi/PiPcdInfo.h
+++ b/MdePkg/Include/Ppi/PiPcdInfo.h
@@ -4,13 +4,7 @@
   The PPI that provides additional information about items that reside in the PCD database.
 
   Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   PI Version 1.2.1 Vol 3.
diff --git a/MdePkg/Include/Ppi/ReadOnlyVariable2.h b/MdePkg/Include/Ppi/ReadOnlyVariable2.h
index 6caee568263a..95e21a96a383 100644
--- a/MdePkg/Include/Ppi/ReadOnlyVariable2.h
+++ b/MdePkg/Include/Ppi/ReadOnlyVariable2.h
@@ -2,14 +2,8 @@
   This file declares Read-only Variable Service2 PPI.
   This ppi permits read-only access to the UEFI variable store during the PEI phase.
 
-Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                             
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This PPI is introduced in PI Version 1.0.
@@ -28,8 +22,8 @@ typedef struct _EFI_PEI_READ_ONLY_VARIABLE2_PPI  EFI_PEI_READ_ONLY_VARIABLE2_PPI
 /**
   This service retrieves a variable's value using its name and GUID.
 
-  Read the specified variable from the UEFI variable store. If the Data 
-  buffer is too small to hold the contents of the variable, 
+  Read the specified variable from the UEFI variable store. If the Data
+  buffer is too small to hold the contents of the variable,
   the error EFI_BUFFER_TOO_SMALL is returned and DataSize is set to the
   required buffer size to obtain the data.
 
@@ -41,11 +35,12 @@ typedef struct _EFI_PEI_READ_ONLY_VARIABLE2_PPI  EFI_PEI_READ_ONLY_VARIABLE2_PPI
   @param  DataSize              On entry, points to the size in bytes of the Data buffer.
                                 On return, points to the size of the data returned in Data.
   @param  Data                  Points to the buffer which will hold the returned variable value.
+                                May be NULL with a zero DataSize in order to determine the size of the buffer needed.
 
   @retval EFI_SUCCESS           The variable was read successfully.
-  @retval EFI_NOT_FOUND         The variable could not be found.
-  @retval EFI_BUFFER_TOO_SMALL  The DataSize is too small for the resulting data. 
-                                DataSize is updated with the size required for 
+  @retval EFI_NOT_FOUND         The variable was not found.
+  @retval EFI_BUFFER_TOO_SMALL  The DataSize is too small for the resulting data.
+                                DataSize is updated with the size required for
                                 the specified variable.
   @retval EFI_INVALID_PARAMETER VariableName, VariableGuid, DataSize or Data is NULL.
   @retval EFI_DEVICE_ERROR      The variable could not be retrieved because of a device error.
@@ -59,18 +54,18 @@ EFI_STATUS
   IN CONST  EFI_GUID                        *VariableGuid,
   OUT       UINT32                          *Attributes,
   IN OUT    UINTN                           *DataSize,
-  OUT       VOID                            *Data
+  OUT       VOID                            *Data OPTIONAL
   );
 
 
 /**
   Return the next variable name and GUID.
 
-  This function is called multiple times to retrieve the VariableName 
-  and VariableGuid of all variables currently available in the system. 
-  On each call, the previous results are passed into the interface, 
-  and, on return, the interface returns the data for the next 
-  interface. When the entire variable list has been returned, 
+  This function is called multiple times to retrieve the VariableName
+  and VariableGuid of all variables currently available in the system.
+  On each call, the previous results are passed into the interface,
+  and, on return, the interface returns the data for the next
+  interface. When the entire variable list has been returned,
   EFI_NOT_FOUND is returned.
 
   @param  This              A pointer to this instance of the EFI_PEI_READ_ONLY_VARIABLE2_PPI.
@@ -80,7 +75,7 @@ EFI_STATUS
   @param  VariableName      On entry, a pointer to a null-terminated string that is the variable's name.
                             On return, points to the next variable's null-terminated name string.
 
-  @param  VariableGuid      On entry, a pointer to an EFI_GUID that is the variable's GUID. 
+  @param  VariableGuid      On entry, a pointer to an EFI_GUID that is the variable's GUID.
                             On return, a pointer to the next variable's GUID.
 
   @retval EFI_SUCCESS           The variable was read successfully.
@@ -103,8 +98,8 @@ EFI_STATUS
   );
 
 ///
-/// This PPI provides a lightweight, read-only variant of the full EFI 
-/// variable services. 
+/// This PPI provides a lightweight, read-only variant of the full EFI
+/// variable services.
 ///
 struct _EFI_PEI_READ_ONLY_VARIABLE2_PPI {
   EFI_PEI_GET_VARIABLE2           GetVariable;
diff --git a/MdePkg/Include/Ppi/RecoveryModule.h b/MdePkg/Include/Ppi/RecoveryModule.h
index 2987facca8e7..5b7dde32c2bc 100644
--- a/MdePkg/Include/Ppi/RecoveryModule.h
+++ b/MdePkg/Include/Ppi/RecoveryModule.h
@@ -4,7 +4,7 @@
 
   A module that produces this PPI has many roles and is responsible for the following:
     -# Calling the driver recovery PPI EFI_PEI_DEVICE_RECOVERY_MODULE_PPI.
-       GetNumberRecoveryCapsules() to determine if one or more DXE recovery 
+       GetNumberRecoveryCapsules() to determine if one or more DXE recovery
        entities exist.
     -# If no capsules exist, then performing appropriate error handling.
     -# Allocating a buffer of MaxRecoveryCapsuleSize as determined by
@@ -16,33 +16,27 @@
     -# If the load failed, performing appropriate error handling.
     -# Performing security checks for a loaded DXE recovery capsule.
     -# If the security checks failed, then logging the failure in a data HOB.
-    -# If the security checks failed, then determining the next 
-       EFI_PEI_DEVICE_RECOVERY_MODULE_PPI.LoadRecoveryCapsule()capsule number; 
+    -# If the security checks failed, then determining the next
+       EFI_PEI_DEVICE_RECOVERY_MODULE_PPI.LoadRecoveryCapsule()capsule number;
        otherwise, go to step 11.
-    -# If more DXE recovery capsules exist, then go to step 5; otherwise, perform 
+    -# If more DXE recovery capsules exist, then go to step 5; otherwise, perform
        error handling.
     -# Decomposing the capsule loaded by EFI_PEI_DEVICE_RECOVERY_MODULE_PPI.
-       LoadRecoveryCapsule() into its components. It is assumed that the path 
-       parameters are redundant for recovery and Setup parameters are either 
+       LoadRecoveryCapsule() into its components. It is assumed that the path
+       parameters are redundant for recovery and Setup parameters are either
        redundant or canned.
-    -# Invalidating all HOB entries for updateable firmware volume entries. 
+    -# Invalidating all HOB entries for updateable firmware volume entries.
        This invalidation prevents possible errant drivers from being executed.
-    -# Updating the HOB table with the recovery DXE firmware volume information 
+    -# Updating the HOB table with the recovery DXE firmware volume information
        generated from the capsule decomposition.
-    -# Returning to the PEI Dispatcher.  
-  
-  Copyright (c) 2007 - 2011, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
+    -# Returning to the PEI Dispatcher.
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
-  This PPI is defined in UEFI Platform Initialization Specification 1.2 Errata B Volume 1: 
-  Pre-EFI Initalization Core Interface
+  This PPI is defined in UEFI Platform Initialization Specification 1.2 Errata B Volume 1:
+  Pre-EFI Initialization Core Interface
 
 **/
 
diff --git a/MdePkg/Include/Ppi/ReportStatusCodeHandler.h b/MdePkg/Include/Ppi/ReportStatusCodeHandler.h
index 40dfd2f72d22..89767a0912c9 100644
--- a/MdePkg/Include/Ppi/ReportStatusCodeHandler.h
+++ b/MdePkg/Include/Ppi/ReportStatusCodeHandler.h
@@ -1,14 +1,8 @@
 /** @file
   This PPI provides registering and unregistering services to status code consumers.
-  
-  Copyright (c) 2007 - 2009, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -33,19 +27,19 @@ EFI_STATUS
 
 /**
   Register the callback function for ReportStatusCode() notification.
-  
+
   When this function is called the function pointer is added to an internal list and any future calls to
   ReportStatusCode() will be forwarded to the Callback function.
 
   @param[in] Callback           A pointer to a function of type EFI_PEI_RSC_HANDLER_CALLBACK that is called
                                 when a call to ReportStatusCode() occurs.
-                        
+
   @retval EFI_SUCCESS           Function was successfully registered.
   @retval EFI_INVALID_PARAMETER The callback function was NULL.
   @retval EFI_OUT_OF_RESOURCES  The internal buffer ran out of space. No more functions can be
                                 registered.
   @retval EFI_ALREADY_STARTED   The function was already registered. It can't be registered again.
-                        
+
 **/
 typedef
 EFI_STATUS
@@ -55,16 +49,16 @@ EFI_STATUS
 
 /**
   Remove a previously registered callback function from the notification list.
-  
+
   ReportStatusCode() messages will no longer be forwarded to the Callback function.
-  
+
   @param[in] Callback           A pointer to a function of type EFI_PEI_RSC_HANDLER_CALLBACK that is to be
                                 unregistered.
 
   @retval EFI_SUCCESS           The function was successfully unregistered.
   @retval EFI_INVALID_PARAMETER The callback function was NULL.
   @retval EFI_NOT_FOUND         The callback function was not found to be unregistered.
-                        
+
 **/
 typedef
 EFI_STATUS
diff --git a/MdePkg/Include/Ppi/Reset.h b/MdePkg/Include/Ppi/Reset.h
index 9cafbdcdc511..db27cc320eef 100644
--- a/MdePkg/Include/Ppi/Reset.h
+++ b/MdePkg/Include/Ppi/Reset.h
@@ -1,17 +1,11 @@
 /** @file
   This file declares Reset PPI used to reset the platform.
-  
-  This PPI is installed by some platform- or chipset-specific PEIM that 
-  abstracts the Reset Service to other agents.
 
-  Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
+  This PPI is installed by some platform- or chipset-specific PEIM that
+  abstracts the Reset Service to other agents.
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This PPI is introduced in PI Version 1.0.
@@ -29,11 +23,11 @@
 //
 // EFI_PEI_RESET_PPI.ResetSystem() is equivalent to the
 // PEI Service ResetSystem().
-// It is introduced in PIPeiCis.h. 
+// It is introduced in PIPeiCis.h.
 //
 
 ///
-/// This PPI provides provide a simple reset service. 
+/// This PPI provides provide a simple reset service.
 ///
 typedef struct {
   EFI_PEI_RESET_SYSTEM  ResetSystem;
diff --git a/MdePkg/Include/Ppi/Reset2.h b/MdePkg/Include/Ppi/Reset2.h
index 8834ba8500c1..ae49d33ab4c5 100644
--- a/MdePkg/Include/Ppi/Reset2.h
+++ b/MdePkg/Include/Ppi/Reset2.h
@@ -5,13 +5,7 @@
   abstracts the Reset Service to other agents.
 
   Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This PPI is introduced in PI Version 1.4.
diff --git a/MdePkg/Include/Ppi/S3Resume2.h b/MdePkg/Include/Ppi/S3Resume2.h
index 2645c22975bc..eb051ae85c78 100644
--- a/MdePkg/Include/Ppi/S3Resume2.h
+++ b/MdePkg/Include/Ppi/S3Resume2.h
@@ -1,23 +1,17 @@
 /** @file
   This PPI produces functions to interpret and execute the PI boot script table.
-  
+
   This PPI is published by a PEIM and provides for the restoration of the platform's
-  configuration when resuming from the ACPI S3 power state. The ability to execute 
-  the boot script may depend on the availability of other PPIs. For example, if 
-  the boot script includes an SMBus command, this PEIM looks for the relevant PPI 
-  that is able to execute that command.  
-  
-  Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  configuration when resuming from the ACPI S3 power state. The ability to execute
+  the boot script may depend on the availability of other PPIs. For example, if
+  the boot script includes an SMBus command, this PEIM looks for the relevant PPI
+  that is able to execute that command.
+
+  Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
-  This PPI is defined in UEFI Platform Initialization Specification 1.2 Volume 5: 
+  This PPI is defined in UEFI Platform Initialization Specification 1.2 Volume 5:
   Standards
 
 **/
@@ -42,30 +36,30 @@ typedef struct _EFI_PEI_S3_RESUME2_PPI  EFI_PEI_S3_RESUME2_PPI;
   Restores the platform to its preboot configuration for an S3 resume and
   jumps to the OS waking vector.
 
-  This function will restore the platform to its pre-boot configuration that was 
+  This function will restore the platform to its pre-boot configuration that was
   pre-stored in the boot script table and transfer control to OS waking vector.
-  Upon invocation, this function is responsible for locating the following 
+  Upon invocation, this function is responsible for locating the following
   information before jumping to OS waking vector:
     - ACPI tables
     - boot script table
     - any other information that it needs
-    
-  The S3RestoreConfig() function then executes the pre-stored boot script table 
-  and transitions the platform to the pre-boot state. The boot script is recorded 
+
+  The S3RestoreConfig() function then executes the pre-stored boot script table
+  and transitions the platform to the pre-boot state. The boot script is recorded
   during regular boot using the EFI_S3_SAVE_STATE_PROTOCOL.Write() and
-  EFI_S3_SMM_SAVE_STATE_PROTOCOL.Write() functions.  Finally, this function 
-  transfers control to the OS waking vector. If the OS supports only a real-mode 
-  waking vector, this function will switch from flat mode to real mode before 
-  jumping to the waking vector.  If all platform pre-boot configurations are 
-  successfully restored and all other necessary information is ready, this 
-  function will never return and instead will directly jump to the OS waking 
-  vector. If this function returns, it indicates that the attempt to resume 
-  from the ACPI S3 sleep state failed.  
-  
+  EFI_S3_SMM_SAVE_STATE_PROTOCOL.Write() functions.  Finally, this function
+  transfers control to the OS waking vector. If the OS supports only a real-mode
+  waking vector, this function will switch from flat mode to real mode before
+  jumping to the waking vector.  If all platform pre-boot configurations are
+  successfully restored and all other necessary information is ready, this
+  function will never return and instead will directly jump to the OS waking
+  vector. If this function returns, it indicates that the attempt to resume
+  from the ACPI S3 sleep state failed.
+
   @param[in] This   Pointer to this instance of the PEI_S3_RESUME_PPI
 
   @retval EFI_ABORTED     Execution of the S3 resume boot script table failed.
-  @retval EFI_NOT_FOUND   Some necessary information that is used for the S3 
+  @retval EFI_NOT_FOUND   Some necessary information that is used for the S3
                           resume boot path could not be located.
 
 **/
diff --git a/MdePkg/Include/Ppi/SecHobData.h b/MdePkg/Include/Ppi/SecHobData.h
new file mode 100644
index 000000000000..85d966832de2
--- /dev/null
+++ b/MdePkg/Include/Ppi/SecHobData.h
@@ -0,0 +1,59 @@
+/** @file
+  This file declares Sec Hob Data PPI.
+
+  This PPI provides a way for the SEC code to pass zero or more HOBs in a HOB list.
+
+Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  This PPI is introduced in PI Version 1.5.
+
+**/
+
+#ifndef __SEC_HOB_DATA_PPI_H__
+#define __SEC_HOB_DATA_PPI_H__
+
+#include <Pi/PiHob.h>
+
+#define EFI_SEC_HOB_DATA_PPI_GUID \
+  { \
+    0x3ebdaf20, 0x6667, 0x40d8, {0xb4, 0xee, 0xf5, 0x99, 0x9a, 0xc1, 0xb7, 0x1f } \
+  }
+
+typedef struct _EFI_SEC_HOB_DATA_PPI EFI_SEC_HOB_DATA_PPI;
+
+/**
+  Return a pointer to a buffer containing zero or more HOBs that
+  will be installed into the PEI HOB List.
+
+  This function returns a pointer to a pointer to zero or more HOBs,
+  terminated with a HOB of type EFI_HOB_TYPE_END_OF_HOB_LIST.
+  Note: The HobList must not contain a EFI_HOB_HANDOFF_INFO_TABLE HOB (PHIT) HOB.
+
+  @param[in]  This          Pointer to this PPI structure.
+  @param[out] HobList       A pointer to a returned pointer to zero or more HOBs.
+                            If no HOBs are to be returned, then the returned pointer
+                            is a pointer to a HOB of type EFI_HOB_TYPE_END_OF_HOB_LIST.
+
+  @retval EFI_SUCCESS       This function completed successfully.
+  @retval EFI_NOT_FOUND     No HOBS are available.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SEC_HOB_DATA_GET) (
+  IN CONST EFI_SEC_HOB_DATA_PPI *This,
+  OUT EFI_HOB_GENERIC_HEADER    **HobList
+);
+
+///
+/// This PPI provides a way for the SEC code to pass zero or more HOBs in a HOB list.
+///
+struct _EFI_SEC_HOB_DATA_PPI {
+  EFI_SEC_HOB_DATA_GET          GetHobs;
+};
+
+extern EFI_GUID gEfiSecHobDataPpiGuid;
+
+#endif
diff --git a/MdePkg/Include/Ppi/SecPlatformInformation.h b/MdePkg/Include/Ppi/SecPlatformInformation.h
index eaf73ce9cf1b..5246d2ac35fe 100644
--- a/MdePkg/Include/Ppi/SecPlatformInformation.h
+++ b/MdePkg/Include/Ppi/SecPlatformInformation.h
@@ -7,13 +7,7 @@
   location of the Boot Firmware Volume (BFV).
 
 Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under
-the terms and conditions of the BSD License that accompanies this distribution.
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This PPI is introduced in PI Version 1.0.
diff --git a/MdePkg/Include/Ppi/SecPlatformInformation2.h b/MdePkg/Include/Ppi/SecPlatformInformation2.h
index 1a6a776169d8..a61ece7991de 100644
--- a/MdePkg/Include/Ppi/SecPlatformInformation2.h
+++ b/MdePkg/Include/Ppi/SecPlatformInformation2.h
@@ -5,13 +5,7 @@
   This service abstracts platform-specific information for many CPU's.
 
 Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under
-the terms and conditions of the BSD License that accompanies this distribution.
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This PPI is introduced from PI Version 1.4.
diff --git a/MdePkg/Include/Ppi/Security2.h b/MdePkg/Include/Ppi/Security2.h
index 026597492151..887f6ef5fa99 100644
--- a/MdePkg/Include/Ppi/Security2.h
+++ b/MdePkg/Include/Ppi/Security2.h
@@ -1,18 +1,12 @@
 /** @file
   This file declares Pei Security2 PPI.
 
-  This PPI is installed by some platform PEIM that abstracts the security 
-  policy to the PEI Foundation, namely the case of a PEIM's authentication 
+  This PPI is installed by some platform PEIM that abstracts the security
+  policy to the PEI Foundation, namely the case of a PEIM's authentication
   state being returned during the PEI section extraction process.
 
-  Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This PPI is introduced in PI Version 1.0.
@@ -29,7 +23,7 @@
 typedef struct _EFI_PEI_SECURITY2_PPI  EFI_PEI_SECURITY2_PPI;
 
 /**
-  Allows the platform builder to implement a security policy 
+  Allows the platform builder to implement a security policy
   in response to varying file authentication states.
 
   This service is published by some platform PEIM. The purpose of
@@ -48,13 +42,13 @@ typedef struct _EFI_PEI_SECURITY2_PPI  EFI_PEI_SECURITY2_PPI;
                                  particular EFI_PEI_SECURITY2_PPI instance.
   @param AuthenticationStatus    Authentication status of the file.
                                  xx00 Image was not signed.
-                                 xxx1 Platform security policy override. 
+                                 xxx1 Platform security policy override.
                                       Assumes same meaning as 0010 (the image was signed, the
                                       signature was tested, and the signature passed authentication test).
-                                 0010 Image was signed, the signature was tested, 
+                                 0010 Image was signed, the signature was tested,
                                       and the signature passed authentication test.
                                  0110 Image was signed and the signature was not tested.
-                                 1010 Image was signed, the signature was tested, 
+                                 1010 Image was signed, the signature was tested,
                                       and the signature failed the authentication test.
   @param FvHandle                Handle of the volume in which the file
                                  resides. This allows different policies
diff --git a/MdePkg/Include/Ppi/Smbus2.h b/MdePkg/Include/Ppi/Smbus2.h
index 633394faa1a7..69f9fa181a45 100644
--- a/MdePkg/Include/Ppi/Smbus2.h
+++ b/MdePkg/Include/Ppi/Smbus2.h
@@ -1,16 +1,10 @@
 /** @file
   This file declares Smbus2 PPI.
-  This PPI provides the basic I/O interfaces that a PEIM uses to access its 
+  This PPI provides the basic I/O interfaces that a PEIM uses to access its
   SMBus controller and the slave devices attached to it.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This PPI is introduced in PI Version 1.0.
@@ -29,28 +23,28 @@
 typedef struct _EFI_PEI_SMBUS2_PPI EFI_PEI_SMBUS2_PPI;
 
 /**
-  Executes an SMBus operation to an SMBus controller. Returns when either 
+  Executes an SMBus operation to an SMBus controller. Returns when either
   the command has been executed or an error is encountered in doing the operation.
 
   @param  This            A pointer to the EFI_PEI_SMBUS2_PPI instance.
   @param  SlaveAddress    The SMBUS hardware address to which the SMBUS device is preassigned or
                           allocated.
-  @param  Command         This command is transmitted by the SMBus host controller to the SMBus slave 
-                          device and the interpretation is SMBus slave device specific. 
-                          It can mean the offset to a list of functions inside 
+  @param  Command         This command is transmitted by the SMBus host controller to the SMBus slave
+                          device and the interpretation is SMBus slave device specific.
+                          It can mean the offset to a list of functions inside
                           an SMBus slave device. Not all operations or slave devices support
                           this command's registers.
-  @param  Operation       Signifies which particular SMBus hardware protocol instance that it 
-                          will use to execute the SMBus transactions. 
-                          This SMBus hardware protocol is defined by the System Management Bus (SMBus) 
+  @param  Operation       Signifies which particular SMBus hardware protocol instance that it
+                          will use to execute the SMBus transactions.
+                          This SMBus hardware protocol is defined by the System Management Bus (SMBus)
                           Specification and is not related to UEFI.
   @param  PecCheck        Defines if Packet Error Code (PEC) checking is required for this operation.
-  @param  Length          Signifies the number of bytes that this operation will do. 
+  @param  Length          Signifies the number of bytes that this operation will do.
                           The maximum number of bytes can be revision specific and operation specific.
                           This parameter will contain the actual number of bytes that are executed
                           for this operation. Not all operations require this argument.
-  @param  Buffer          Contains the value of data to execute to the SMBus slave device. 
-                          Not all operations require this argument. 
+  @param  Buffer          Contains the value of data to execute to the SMBus slave device.
+                          Not all operations require this argument.
                           The length of this buffer is identified by Length.
 
 
@@ -83,8 +77,8 @@ EFI_STATUS
 );
 
 /**
-  The ArpDevice() function enumerates the entire bus or enumerates a specific 
-  device that is identified by SmbusUdid. 
+  The ArpDevice() function enumerates the entire bus or enumerates a specific
+  device that is identified by SmbusUdid.
 
   @param  This           A pointer to the EFI_PEI_SMBUS2_PPI instance.
   @param  ArpAll         A Boolean expression that indicates if the host drivers need
@@ -116,8 +110,8 @@ EFI_STATUS
 );
 
 /**
-  The GetArpMap() function returns the mapping of all the SMBus devices 
-  that are enumerated by the SMBus host driver. 
+  The GetArpMap() function returns the mapping of all the SMBus devices
+  that are enumerated by the SMBus host driver.
 
   @param  This           A pointer to the EFI_PEI_SMBUS2_PPI instance.
   @param  Length         Size of the buffer that contains the SMBus device map.
@@ -159,7 +153,7 @@ EFI_STATUS
 );
 
 /**
-  The Notify() function registers all the callback functions to allow the 
+  The Notify() function registers all the callback functions to allow the
   bus driver to call these functions when the SlaveAddress/Data pair happens.
 
   @param  This           A pointer to the EFI_PEI_SMBUS2_PPI instance.
@@ -184,7 +178,7 @@ EFI_STATUS
 );
 
 ///
-///  Provides the basic I/O interfaces that a PEIM uses to access 
+///  Provides the basic I/O interfaces that a PEIM uses to access
 ///  its SMBus controller and the slave devices attached to it.
 ///
 struct _EFI_PEI_SMBUS2_PPI {
diff --git a/MdePkg/Include/Ppi/Stall.h b/MdePkg/Include/Ppi/Stall.h
index 94a68c2e392b..f0dc62a25d13 100644
--- a/MdePkg/Include/Ppi/Stall.h
+++ b/MdePkg/Include/Ppi/Stall.h
@@ -3,14 +3,8 @@
 
   This ppi abstracts the blocking stall service to other agents.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This PPI is introduced in PI Version 1.0.
@@ -26,7 +20,7 @@
 typedef struct _EFI_PEI_STALL_PPI EFI_PEI_STALL_PPI;
 
 /**
-  The Stall() function provides a blocking stall for at least the number 
+  The Stall() function provides a blocking stall for at least the number
   of microseconds stipulated in the final argument of the API.
 
   @param  PeiServices    An indirect pointer to the PEI Services Table
@@ -46,7 +40,7 @@ EFI_STATUS
   );
 
 ///
-/// This service provides a simple, blocking stall with platform-specific resolution. 
+/// This service provides a simple, blocking stall with platform-specific resolution.
 ///
 struct _EFI_PEI_STALL_PPI {
   ///
diff --git a/MdePkg/Include/Ppi/StatusCode.h b/MdePkg/Include/Ppi/StatusCode.h
index 30a53304fdc8..29de3fc48b0c 100644
--- a/MdePkg/Include/Ppi/StatusCode.h
+++ b/MdePkg/Include/Ppi/StatusCode.h
@@ -2,14 +2,8 @@
   This file declares Status Code PPI.
   This ppi provides a service that allows PEIMs to report status codes.
 
-  Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This PPI is introduced in PI Version 1.0.
@@ -25,7 +19,7 @@
 //
 // EFI_PEI_PROGRESS_CODE_PPI.ReportStatusCode() is equivalent to the
 // PEI Service ReportStatusCode().
-// It is introduced in PIPeiCis.h. 
+// It is introduced in PIPeiCis.h.
 //
 
 ///
diff --git a/MdePkg/Include/Ppi/SuperIo.h b/MdePkg/Include/Ppi/SuperIo.h
index 9f129ffc98e0..319155f5fe92 100644
--- a/MdePkg/Include/Ppi/SuperIo.h
+++ b/MdePkg/Include/Ppi/SuperIo.h
@@ -1,14 +1,8 @@
 /** @file
   This PPI provides the super I/O register access functionality.
 
-  Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This PPI is from PI Version 1.2.1.
@@ -34,7 +28,7 @@ typedef UINT16 EFI_SIO_REGISTER;
 
 /**
   Read a Super I/O register.
- 
+
   The register is specified as an 8-bit logical device number and an 8-bit
   register value. The logical device numbers for specific SIO devices can be
   determined using the Info member of the PPI structure.
@@ -47,8 +41,8 @@ typedef UINT16 EFI_SIO_REGISTER;
                       track the current state of the configuration mode (if any)
                       and turn on configuration mode (if necessary) prior to
                       register access.
-  @param Register     A value specifying the logical device number (bits 15:8) 
-                      and the register to read (bits 7:0). The logical device 
+  @param Register     A value specifying the logical device number (bits 15:8)
+                      and the register to read (bits 7:0). The logical device
                       number of EFI_SIO_LDN_GLOBAL indicates that global
                       registers will be used.
   @param IoData       A pointer to the returned register value.
@@ -85,8 +79,8 @@ EFI_STATUS
                       track the current state of the configuration mode (if any)
                       and turn on configuration mode (if necessary) prior to
                       register access.
-  @param Register     A value specifying the logical device number (bits 15:8) 
-                      and the register to read (bits 7:0). The logical device 
+  @param Register     A value specifying the logical device number (bits 15:8)
+                      and the register to read (bits 7:0). The logical device
                       number of EFI_SIO_LDN_GLOBAL indicates that global
                       registers will be used.
   @param IoData       A pointer to the returned register value.
@@ -97,7 +91,7 @@ EFI_STATUS
   @retval EFI_INVALID_PARAMETERS Register was out of range for this device.
   @retval EFI_INVALID_PARAMETERS IoData was NULL
   @retval EFI_DEVICE_ERROR       There was a device fault or the device was not present.
-**/ 
+**/
 typedef
 EFI_STATUS
 (EFIAPI *EFI_PEI_SIO_REGISTER_WRITE)(
@@ -129,7 +123,7 @@ EFI_STATUS
 
   @retval EFI_SUCCESS             The operation completed successfully.
   @retval EFI_INVALID_PARAMETERS  Command is NULL.
-**/ 
+**/
 typedef
 EFI_STATUS
 (EFIAPI *EFI_PEI_SIO_REGISTER_MODIFY)(
@@ -186,4 +180,4 @@ struct _EFI_SIO_PPI {
 
 extern EFI_GUID gEfiSioPpiGuid;
 
-#endif 
+#endif
diff --git a/MdePkg/Include/Ppi/TemporaryRamDone.h b/MdePkg/Include/Ppi/TemporaryRamDone.h
index 349dac88b52a..7af15586bd57 100644
--- a/MdePkg/Include/Ppi/TemporaryRamDone.h
+++ b/MdePkg/Include/Ppi/TemporaryRamDone.h
@@ -2,14 +2,8 @@
   This file declares Temporary RAM Done PPI.
   The PPI that provides a service to disable the use of Temporary RAM.
 
-  Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This PPI is introduced in PI Version 1.2.1.
@@ -24,7 +18,7 @@
 
 /**
   TemporaryRamDone() disables the use of Temporary RAM. If present, this service is invoked
-  by the PEI Foundation after the EFI_PEI_PERMANANT_MEMORY_INSTALLED_PPI is installed.
+  by the PEI Foundation after the EFI_PEI_PERMANENT_MEMORY_INSTALLED_PPI is installed.
 
   @retval EFI_SUCCESS           Use of Temporary RAM was disabled.
   @retval EFI_INVALID_PARAMETER Temporary RAM could not be disabled.
diff --git a/MdePkg/Include/Ppi/TemporaryRamSupport.h b/MdePkg/Include/Ppi/TemporaryRamSupport.h
index 87e5dbd1563d..e904d65671d9 100644
--- a/MdePkg/Include/Ppi/TemporaryRamSupport.h
+++ b/MdePkg/Include/Ppi/TemporaryRamSupport.h
@@ -2,14 +2,8 @@
   This file declares Temporary RAM Support PPI.
   This Ppi provides the service that migrates temporary RAM into permanent memory.
 
-  Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This PPI is introduced in PI Version 1.0.
diff --git a/MdePkg/Include/Ppi/VectorHandoffInfo.h b/MdePkg/Include/Ppi/VectorHandoffInfo.h
index fba0856bce0b..52c904a4e1e9 100644
--- a/MdePkg/Include/Ppi/VectorHandoffInfo.h
+++ b/MdePkg/Include/Ppi/VectorHandoffInfo.h
@@ -4,16 +4,10 @@
 
   This is an optional PPI that may be produced by SEC. If present, it provides
   a description of the interrupt and/or exception vectors that were established
-  in the SEC Phase and need to persist into PEI and DXE. 
+  in the SEC Phase and need to persist into PEI and DXE.
 
-  Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This PPI is introduced in PI Version 1.2.1.
@@ -49,11 +43,11 @@ typedef struct {
   //
   UINT32    VectorNumber;
   //
-  // A bitmask that describes the attributes ofthe interrupt or exception vector.
+  // A bitmask that describes the attributes of the interrupt or exception vector.
   //
   UINT32    Attribute;
   //
-  // The GUID identifies the party who created the entry. For the 
+  // The GUID identifies the party who created the entry. For the
   // EFI_VECTOR_HANDOFF_DO_NOT_HOOK case, this establishes the single owner.
   //
   EFI_GUID  Owner;
@@ -61,7 +55,7 @@ typedef struct {
 
 ///
 /// Provides a description of the interrupt and/or exception vectors that
-/// were established in the SEC Phase and need to persist into PEI and DXE.  
+/// were established in the SEC Phase and need to persist into PEI and DXE.
 ///
 typedef struct _EFI_PEI_VECTOR_HANDOFF_INFO_PPI {
   //
diff --git a/MdePkg/Include/Protocol/AbsolutePointer.h b/MdePkg/Include/Protocol/AbsolutePointer.h
index 42693ab20b65..ff8f37b27e80 100644
--- a/MdePkg/Include/Protocol/AbsolutePointer.h
+++ b/MdePkg/Include/Protocol/AbsolutePointer.h
@@ -1,15 +1,12 @@
 /** @file
   The file provides services that allow information about an
   absolute pointer device to be retrieved.
-  
-  Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  This Protocol was introduced in UEFI Specification 2.3.
 
 **/
 
@@ -38,25 +35,25 @@ typedef struct {
   UINT64 AbsoluteMinX; ///< The Absolute Minimum of the device on the x-axis
   UINT64 AbsoluteMinY; ///< The Absolute Minimum of the device on the y axis.
   UINT64 AbsoluteMinZ; ///< The Absolute Minimum of the device on the z-axis
-  UINT64 AbsoluteMaxX; ///< The Absolute Maximum of the device on the x-axis. If 0, and the 
+  UINT64 AbsoluteMaxX; ///< The Absolute Maximum of the device on the x-axis. If 0, and the
                        ///< AbsoluteMinX is 0, then the pointer device does not support a xaxis
-  UINT64 AbsoluteMaxY; ///< The Absolute Maximum of the device on the y -axis. If 0, and the 
+  UINT64 AbsoluteMaxY; ///< The Absolute Maximum of the device on the y -axis. If 0, and the
                        ///< AbsoluteMinX is 0, then the pointer device does not support a yaxis.
-  UINT64 AbsoluteMaxZ; ///< The Absolute Maximum of the device on the z-axis. If 0 , and the 
+  UINT64 AbsoluteMaxZ; ///< The Absolute Maximum of the device on the z-axis. If 0 , and the
                        ///< AbsoluteMinX is 0, then the pointer device does not support a zaxis
-  UINT32 Attributes;   ///< The following bits are set as needed (or'd together) to indicate the 
-                       ///< capabilities of the device supported. The remaining bits are undefined 
+  UINT32 Attributes;   ///< The following bits are set as needed (or'd together) to indicate the
+                       ///< capabilities of the device supported. The remaining bits are undefined
                        ///< and should be 0
 } EFI_ABSOLUTE_POINTER_MODE;
 
 ///
-/// If set, indicates this device supports an alternate button input. 
-/// 
+/// If set, indicates this device supports an alternate button input.
+///
 #define EFI_ABSP_SupportsAltActive    0x00000001
 
 ///
 /// If set, indicates this device returns pressure data in parameter CurrentZ.
-/// 
+///
 #define EFI_ABSP_SupportsPressureAsZ  0x00000002
 
 
@@ -80,7 +77,7 @@ typedef struct {
                               device during reset.
 
   @retval EFI_SUCCESS       The device was reset.
-  
+
   @retval EFI_DEVICE_ERROR  The device is not functioning
                             correctly and could not be reset.
 
@@ -95,11 +92,11 @@ EFI_STATUS
 ///
 /// This bit is set if the touch sensor is active.
 ///
-#define EFI_ABSP_TouchActive  0x00000001 
+#define EFI_ABSP_TouchActive  0x00000001
 
 ///
 /// This bit is set if the alt sensor, such as pen-side button, is active
-/// 
+///
 #define EFI_ABS_AltActive     0x00000002
 
 
@@ -108,29 +105,29 @@ EFI_STATUS
 **/
 typedef struct {
   ///
-  /// The unsigned position of the activation on the x axis. If the AboluteMinX 
-  /// and the AboluteMaxX fields of the EFI_ABSOLUTE_POINTER_MODE structure are 
+  /// The unsigned position of the activation on the x axis. If the AboluteMinX
+  /// and the AboluteMaxX fields of the EFI_ABSOLUTE_POINTER_MODE structure are
   /// both 0, then this pointer device does not support an x-axis, and this field
   /// must be ignored.
   ///
   UINT64 CurrentX;
-  
+
   ///
-  /// The unsigned position of the activation on the y axis. If the AboluteMinY 
-  /// and the AboluteMaxY fields of the EFI_ABSOLUTE_POINTER_MODE structure are 
+  /// The unsigned position of the activation on the y axis. If the AboluteMinY
+  /// and the AboluteMaxY fields of the EFI_ABSOLUTE_POINTER_MODE structure are
   /// both 0, then this pointer device does not support an y-axis, and this field
-  /// must be ignored.  
+  /// must be ignored.
   ///
   UINT64 CurrentY;
-  
+
   ///
-  /// The unsigned position of the activation on the z axis, or the pressure 
-  /// measurement. If the AboluteMinZ and the AboluteMaxZ fields of the 
-  /// EFI_ABSOLUTE_POINTER_MODE structure are both 0, then this pointer device 
-  /// does not support an z-axis, and this field must be ignored.  
+  /// The unsigned position of the activation on the z axis, or the pressure
+  /// measurement. If the AboluteMinZ and the AboluteMaxZ fields of the
+  /// EFI_ABSOLUTE_POINTER_MODE structure are both 0, then this pointer device
+  /// does not support an z-axis, and this field must be ignored.
   ///
   UINT64 CurrentZ;
-  
+
   ///
   /// Bits are set to 1 in this structure item to indicate that device buttons are
   /// active.
@@ -172,7 +169,7 @@ typedef
 EFI_STATUS
 (EFIAPI *EFI_ABSOLUTE_POINTER_GET_STATE)(
   IN      EFI_ABSOLUTE_POINTER_PROTOCOL  *This,
-  IN OUT  EFI_ABSOLUTE_POINTER_STATE     *State
+  OUT  EFI_ABSOLUTE_POINTER_STATE        *State
 );
 
 
@@ -188,7 +185,7 @@ struct _EFI_ABSOLUTE_POINTER_PROTOCOL {
   EFI_ABSOLUTE_POINTER_RESET      Reset;
   EFI_ABSOLUTE_POINTER_GET_STATE  GetState;
   ///
-  /// Event to use with WaitForEvent() to wait for input from the pointer device.  
+  /// Event to use with WaitForEvent() to wait for input from the pointer device.
   ///
   EFI_EVENT                       WaitForInput;
   ///
diff --git a/MdePkg/Include/Protocol/AcpiSystemDescriptionTable.h b/MdePkg/Include/Protocol/AcpiSystemDescriptionTable.h
index b98862f6d840..e837167605ff 100644
--- a/MdePkg/Include/Protocol/AcpiSystemDescriptionTable.h
+++ b/MdePkg/Include/Protocol/AcpiSystemDescriptionTable.h
@@ -1,14 +1,11 @@
 /** @file
   This protocol provides services for creating ACPI system description tables.
-  
-  Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  This Protocol was introduced in PI Specification 1.2.
 
 **/
 
@@ -17,7 +14,7 @@
 
 #define EFI_ACPI_SDT_PROTOCOL_GUID \
   { 0xeb97088e, 0xcfdf, 0x49c6, { 0xbe, 0x4b, 0xd9, 0x6, 0xa5, 0xb2, 0xe, 0x86 }}
-  
+
 typedef UINT32  EFI_ACPI_TABLE_VERSION;
 typedef VOID    *EFI_ACPI_HANDLE;
 
@@ -27,7 +24,7 @@ typedef VOID    *EFI_ACPI_HANDLE;
 #define EFI_ACPI_TABLE_VERSION_3_0  (1 << 3)
 #define EFI_ACPI_TABLE_VERSION_4_0  (1 << 4)
 #define EFI_ACPI_TABLE_VERSION_5_0  (1 << 5)
-  
+
 typedef UINT32 EFI_ACPI_DATA_TYPE;
 #define EFI_ACPI_DATA_TYPE_NONE         0
 #define EFI_ACPI_DATA_TYPE_OPCODE       1
@@ -36,7 +33,7 @@ typedef UINT32 EFI_ACPI_DATA_TYPE;
 #define EFI_ACPI_DATA_TYPE_UINT         4
 #define EFI_ACPI_DATA_TYPE_STRING       5
 #define EFI_ACPI_DATA_TYPE_CHILD        6
-  
+
 typedef struct {
   UINT32    Signature;
   UINT32    Length;
@@ -48,7 +45,7 @@ typedef struct {
   UINT32    CreatorId;
   UINT32    CreatorRevision;
 } EFI_ACPI_SDT_HEADER;
-  
+
 typedef
 EFI_STATUS
 (EFIAPI *EFI_ACPI_NOTIFICATION_FN)(
@@ -56,10 +53,10 @@ EFI_STATUS
   IN EFI_ACPI_TABLE_VERSION Version,    ///< The ACPI table's version.
   IN UINTN                  TableKey    ///< The table key for this ACPI table.
 );
-  
+
 /**
   Returns a requested ACPI table.
-  
+
   The GetAcpiTable() function returns a pointer to a buffer containing the ACPI table associated
   with the Index that was input. The following structures are not considered elements in the list of
   ACPI tables:
@@ -69,20 +66,20 @@ EFI_STATUS
   Version is updated with a bit map containing all the versions of ACPI of which the table is a
   member. For tables installed via the EFI_ACPI_TABLE_PROTOCOL.InstallAcpiTable() interface,
   the function returns the value of EFI_ACPI_STD_PROTOCOL.AcpiVersion.
-  
+
   @param[in]    Index       The zero-based index of the table to retrieve.
   @param[out]   Table       Pointer for returning the table buffer.
   @param[out]   Version     On return, updated with the ACPI versions to which this table belongs. Type
                             EFI_ACPI_TABLE_VERSION is defined in "Related Definitions" in the
-                            EFI_ACPI_SDT_PROTOCOL.    
+                            EFI_ACPI_SDT_PROTOCOL.
   @param[out]   TableKey    On return, points to the table key for the specified ACPI system definition table.
                             This is identical to the table key used in the EFI_ACPI_TABLE_PROTOCOL.
                             The TableKey can be passed to EFI_ACPI_TABLE_PROTOCOL.UninstallAcpiTable()
                             to uninstall the table.
 
   @retval EFI_SUCCESS       The function completed successfully.
-  @retval EFI_NOT_FOUND     The requested index is too large and a table was not found.                                  
-**/  
+  @retval EFI_NOT_FOUND     The requested index is too large and a table was not found.
+**/
 typedef
 EFI_STATUS
 (EFIAPI *EFI_ACPI_GET_ACPI_TABLE2)(
@@ -94,17 +91,17 @@ EFI_STATUS
 
 /**
   Register or unregister a callback when an ACPI table is installed.
-  
+
   This function registers or unregisters a function which will be called whenever a new ACPI table is
   installed.
-  
+
   @param[in]    Register        If TRUE, then the specified function will be registered. If FALSE, then the specified
                                 function will be unregistered.
   @param[in]    Notification    Points to the callback function to be registered or unregistered.
-  
+
   @retval EFI_SUCCESS           Callback successfully registered or unregistered.
   @retval EFI_INVALID_PARAMETER Notification is NULL
-  @retval EFI_INVALID_PARAMETER Register is FALSE and Notification does not match a known registration function.                        
+  @retval EFI_INVALID_PARAMETER Register is FALSE and Notification does not match a known registration function.
 **/
 typedef
 EFI_STATUS
@@ -115,30 +112,30 @@ EFI_STATUS
 
 /**
   Create a handle from an ACPI opcode
-  
+
   @param[in]  Buffer                 Points to the ACPI opcode.
   @param[out] Handle                 Upon return, holds the handle.
-  
+
   @retval   EFI_SUCCESS             Success
   @retval   EFI_INVALID_PARAMETER   Buffer is NULL or Handle is NULL or Buffer points to an
                                     invalid opcode.
-  
+
 **/
 typedef
 EFI_STATUS
 (EFIAPI *EFI_ACPI_OPEN)(
   IN    VOID            *Buffer,
-  OUT   EFI_ACPI_HANDLE *Handle 
+  OUT   EFI_ACPI_HANDLE *Handle
 );
 
 /**
   Create a handle for the first ACPI opcode in an ACPI system description table.
-  
+
   @param[in]    TableKey    The table key for the ACPI table, as returned by GetTable().
   @param[out]   Handle      On return, points to the newly created ACPI handle.
 
   @retval EFI_SUCCESS       Handle created successfully.
-  @retval EFI_NOT_FOUND     TableKey does not refer to a valid ACPI table.  
+  @retval EFI_NOT_FOUND     TableKey does not refer to a valid ACPI table.
 **/
 typedef
 EFI_STATUS
@@ -149,11 +146,11 @@ EFI_STATUS
 
 /**
   Close an ACPI handle.
-  
+
   @param[in] Handle Returns the handle.
-  
+
   @retval EFI_SUCCESS           Success
-  @retval EFI_INVALID_PARAMETER Handle is NULL or does not refer to a valid ACPI object.  
+  @retval EFI_INVALID_PARAMETER Handle is NULL or does not refer to a valid ACPI object.
 **/
 typedef
 EFI_STATUS
@@ -163,14 +160,14 @@ EFI_STATUS
 
 /**
   Return the child ACPI objects.
-  
+
   @param[in]        ParentHandle    Parent handle.
   @param[in, out]   Handle          On entry, points to the previously returned handle or NULL to start with the first
                                     handle. On return, points to the next returned ACPI handle or NULL if there are no
                                     child objects.
 
   @retval EFI_SUCCESS               Success
-  @retval EFI_INVALID_PARAMETER     ParentHandle is NULL or does not refer to a valid ACPI object.                                
+  @retval EFI_INVALID_PARAMETER     ParentHandle is NULL or does not refer to a valid ACPI object.
 **/
 typedef
 EFI_STATUS
@@ -181,7 +178,7 @@ EFI_STATUS
 
 /**
   Retrieve information about an ACPI object.
-  
+
   @param[in]    Handle      ACPI object handle.
   @param[in]    Index       Index of the data to retrieve from the object. In general, indexes read from left-to-right
                             in the ACPI encoding, with index 0 always being the ACPI opcode.
@@ -189,8 +186,8 @@ EFI_STATUS
                             for the specified index.
   @param[out]   Data        Upon return, points to the pointer to the data.
   @param[out]   DataSize    Upon return, points to the size of Data.
-  
-  @retval              
+
+  @retval
 **/
 typedef
 EFI_STATUS
@@ -204,7 +201,7 @@ EFI_STATUS
 
 /**
   Change information about an ACPI object.
-  
+
   @param[in]  Handle    ACPI object handle.
   @param[in]  Index     Index of the data to retrieve from the object. In general, indexes read from left-to-right
                         in the ACPI encoding, with index 0 always being the ACPI opcode.
@@ -228,14 +225,14 @@ EFI_STATUS
 
 /**
   Returns the handle of the ACPI object representing the specified ACPI path
-  
+
   @param[in]    HandleIn    Points to the handle of the object representing the starting point for the path search.
   @param[in]    AcpiPath    Points to the ACPI path, which conforms to the ACPI encoded path format.
   @param[out]   HandleOut   On return, points to the ACPI object which represents AcpiPath, relative to
                             HandleIn.
-                            
+
   @retval EFI_SUCCESS           Success
-  @retval EFI_INVALID_PARAMETER HandleIn is NULL or does not refer to a valid ACPI object.                            
+  @retval EFI_INVALID_PARAMETER HandleIn is NULL or does not refer to a valid ACPI object.
 **/
 typedef
 EFI_STATUS
diff --git a/MdePkg/Include/Protocol/AcpiTable.h b/MdePkg/Include/Protocol/AcpiTable.h
index c6081823268b..a428ea1b9db4 100644
--- a/MdePkg/Include/Protocol/AcpiTable.h
+++ b/MdePkg/Include/Protocol/AcpiTable.h
@@ -1,15 +1,12 @@
 /** @file
   The file provides the protocol to install or remove an ACPI
-  table from a platform. 
-  
-  Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
+  table from a platform.
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  This Protocol was introduced in UEFI Specification 2.3.
 
 **/
 
@@ -24,24 +21,24 @@ typedef struct _EFI_ACPI_TABLE_PROTOCOL EFI_ACPI_TABLE_PROTOCOL;
 
 /**
 
-  The InstallAcpiTable() function allows a caller to install an   
-  ACPI table. When successful, the table will be linked by the   
-  RSDT/XSDT. AcpiTableBuffer specifies the table to be installed.   
-  InstallAcpiTable() will make a copy of the table and insert the   
-  copy into the RSDT/XSDT. InstallAcpiTable() must insert the new   
-  table at the end of the RSDT/XSDT. To prevent namespace   
-  collision, ACPI tables may be created using UEFI ACPI table   
+  The InstallAcpiTable() function allows a caller to install an
+  ACPI table. When successful, the table will be linked by the
+  RSDT/XSDT. AcpiTableBuffer specifies the table to be installed.
+  InstallAcpiTable() will make a copy of the table and insert the
+  copy into the RSDT/XSDT. InstallAcpiTable() must insert the new
+  table at the end of the RSDT/XSDT. To prevent namespace
+  collision, ACPI tables may be created using UEFI ACPI table
   format. If this protocol is used to install a table with a
   signature already present in the system, the new table will not
   replace the existing table. It is a platform implementation
   decision to add a new table with a signature matching an
   existing table or disallow duplicate table signatures and
-  return EFI_ACCESS_DENIED. On successful output, TableKey is   
-  initialized with a unique key. Its value may be used in a   
-  subsequent call to UninstallAcpiTable to remove an ACPI table.   
-  If an EFI application is running at the time of this call, the   
-  relevant EFI_CONFIGURATION_TABLE pointer to the RSDT is no   
-  longer considered valid.   
+  return EFI_ACCESS_DENIED. On successful output, TableKey is
+  initialized with a unique key. Its value may be used in a
+  subsequent call to UninstallAcpiTable to remove an ACPI table.
+  If an EFI application is running at the time of this call, the
+  relevant EFI_CONFIGURATION_TABLE pointer to the RSDT is no
+  longer considered valid.
 
 
   @param This                 A pointer to a EFI_ACPI_TABLE_PROTOCOL.
@@ -54,16 +51,16 @@ typedef struct _EFI_ACPI_TABLE_PROTOCOL EFI_ACPI_TABLE_PROTOCOL;
 
 
   @param TableKey             Returns a key to refer to the ACPI table.
-  
+
   @retval EFI_SUCCESS           The table was successfully inserted
-  
+
   @retval EFI_INVALID_PARAMETER Either AcpiTableBuffer is NULL,
                                 TableKey is NULL, or
                                 AcpiTableBufferSize and the size
                                 field embedded in the ACPI table
                                 pointed to by AcpiTableBuffer
                                 are not in sync.
-  
+
   @retval EFI_OUT_OF_RESOURCES  Insufficient resources exist to
                                 complete the request.
   @retval EFI_ACCESS_DENIED     The table signature matches a table already
@@ -82,7 +79,7 @@ EFI_STATUS
 
 
 /**
-  
+
   The UninstallAcpiTable() function allows a caller to remove an
   ACPI table. The routine will remove its reference from the
   RSDT/XSDT. A table is referenced by the TableKey parameter
@@ -103,7 +100,7 @@ EFI_STATUS
 
   @retval EFI_OUT_OF_RESOURCES  Insufficient resources exist to
                                 complete the request.
-  
+
 **/
 typedef
 EFI_STATUS
diff --git a/MdePkg/Include/Protocol/AdapterInformation.h b/MdePkg/Include/Protocol/AdapterInformation.h
index 92fd11d7706c..c0cff5ae05b9 100644
--- a/MdePkg/Include/Protocol/AdapterInformation.h
+++ b/MdePkg/Include/Protocol/AdapterInformation.h
@@ -3,14 +3,8 @@
   The EFI Adapter Information Protocol is used to dynamically and quickly discover
   or set device information for an adapter.
 
-  Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution. The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This Protocol is introduced in UEFI Specification 2.4
@@ -46,6 +40,12 @@
     0x4bd56be3, 0x4975, 0x4d8a, {0xa0, 0xad, 0xc4, 0x91, 0x20, 0x4b, 0x5d, 0x4d} \
   }
 
+#define EFI_ADAPTER_INFO_MEDIA_TYPE_GUID \
+  { \
+    0x8484472f, 0x71ec, 0x411a, { 0xb3, 0x9c, 0x62, 0xcd, 0x94, 0xd9, 0x91, 0x6e } \
+  }
+
+
 typedef struct _EFI_ADAPTER_INFORMATION_PROTOCOL EFI_ADAPTER_INFORMATION_PROTOCOL;
 
 ///
@@ -53,15 +53,28 @@ typedef struct _EFI_ADAPTER_INFORMATION_PROTOCOL EFI_ADAPTER_INFORMATION_PROTOCO
 ///
 typedef struct {
   ///
-  /// Returns the current media state status. MediaState can have any of the following values: 
-  /// EFI_SUCCESS: There is media attached to the network adapter. EFI_NOT_READY: This detects a bounced state. 
-  /// There was media attached to the network adapter, but it was removed and reattached. EFI_NO_MEDIA: There is 
+  /// Returns the current media state status. MediaState can have any of the following values:
+  /// EFI_SUCCESS: There is media attached to the network adapter. EFI_NOT_READY: This detects a bounced state.
+  /// There was media attached to the network adapter, but it was removed and reattached. EFI_NO_MEDIA: There is
   /// not any media attached to the network.
   ///
   EFI_STATUS                    MediaState;
 } EFI_ADAPTER_INFO_MEDIA_STATE;
 
 ///
+/// EFI_ADAPTER_INFO_MEDIA_TYPE
+///
+typedef struct {
+  ///
+  /// Indicates the current media type. MediaType can have any of the following values:
+  /// 1: Ethernet Network Adapter
+  /// 2: Ethernet Wireless Network Adapter
+  /// 3~255: Reserved
+  ///
+  UINT8 MediaType;
+} EFI_ADAPTER_INFO_MEDIA_TYPE;
+
+///
 /// EFI_ADAPTER_INFO_NETWORK_BOOT
 ///
 typedef struct {
@@ -121,7 +134,7 @@ typedef struct {
   ///
   /// Returns capability of UNDI to support IPv6 traffic.
   ///
-  BOOLEAN                            Ipv6Support; 
+  BOOLEAN                            Ipv6Support;
 } EFI_ADAPTER_INFO_UNDI_IPV6_SUPPORT;
 
 /**
@@ -129,7 +142,7 @@ typedef struct {
 
   This function returns information of type InformationType from the adapter.
   If an adapter does not support the requested informational type, then
-  EFI_UNSUPPORTED is returned. 
+  EFI_UNSUPPORTED is returned.
 
   @param[in]  This                   A pointer to the EFI_ADAPTER_INFORMATION_PROTOCOL instance.
   @param[in]  InformationType        A pointer to an EFI_GUID that defines the contents of InformationBlock.
@@ -141,8 +154,8 @@ typedef struct {
   @retval EFI_UNSUPPORTED            The InformationType is not known.
   @retval EFI_DEVICE_ERROR           The device reported an error.
   @retval EFI_OUT_OF_RESOURCES       The request could not be completed due to a lack of resources.
-  @retval EFI_INVALID_PARAMETER      This is NULL. 
-  @retval EFI_INVALID_PARAMETER      InformationBlock is NULL. 
+  @retval EFI_INVALID_PARAMETER      This is NULL.
+  @retval EFI_INVALID_PARAMETER      InformationBlock is NULL.
   @retval EFI_INVALID_PARAMETER      InformationBlockSize is NULL.
 
 **/
diff --git a/MdePkg/Include/Protocol/Arp.h b/MdePkg/Include/Protocol/Arp.h
index 0295cc644ddc..d6b109e3ab33 100644
--- a/MdePkg/Include/Protocol/Arp.h
+++ b/MdePkg/Include/Protocol/Arp.h
@@ -1,22 +1,16 @@
-/** @file  
+/** @file
   EFI ARP Protocol Definition
-  
+
   The EFI ARP Service Binding Protocol is used to locate EFI
   ARP Protocol drivers to create and destroy child of the
   driver to communicate with other host using ARP protocol.
   The EFI ARP Protocol provides services to map IP network
   address to hardware address used by a data link protocol.
-  
-Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
-
-  @par Revision Reference:          
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
   This Protocol was introduced in UEFI Specification 2.0.
 
 **/
@@ -119,13 +113,13 @@ typedef struct {
 /**
   This function is used to assign a station address to the ARP cache for this instance
   of the ARP driver.
-  
-  Each ARP instance has one station address. The EFI_ARP_PROTOCOL driver will 
-  respond to ARP requests that match this registered station address. A call to 
+
+  Each ARP instance has one station address. The EFI_ARP_PROTOCOL driver will
+  respond to ARP requests that match this registered station address. A call to
   this function with the ConfigData field set to NULL will reset this ARP instance.
-  
-  Once a protocol type and station address have been assigned to this ARP instance, 
-  all the following ARP functions will use this information. Attempting to change 
+
+  Once a protocol type and station address have been assigned to this ARP instance,
+  all the following ARP functions will use this information. Attempting to change
   the protocol type or station address to a configured ARP instance will result in errors.
 
   @param  This                   The pointer to the EFI_ARP_PROTOCOL instance.
@@ -134,8 +128,8 @@ typedef struct {
   @retval EFI_SUCCESS            The new station address was successfully
                                  registered.
   @retval EFI_INVALID_PARAMETER  One or more of the following conditions is TRUE:
-                                 * This is NULL. 
-                                 * SwAddressLength is zero when ConfigData is not NULL. 
+                                 * This is NULL.
+                                 * SwAddressLength is zero when ConfigData is not NULL.
                                  * StationAddress is NULL when ConfigData is not NULL.
   @retval EFI_ACCESS_DENIED      The SwAddressType, SwAddressLength, or
                                  StationAddress is different from the one that is
@@ -144,27 +138,27 @@ typedef struct {
                                  allocated.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_ARP_CONFIGURE)(
   IN EFI_ARP_PROTOCOL       *This,
   IN EFI_ARP_CONFIG_DATA    *ConfigData   OPTIONAL
-  );  
+  );
 
 /**
   This function is used to insert entries into the ARP cache.
 
-  ARP cache entries are typically inserted and updated by network protocol drivers 
-  as network traffic is processed. Most ARP cache entries will time out and be 
-  deleted if the network traffic stops. ARP cache entries that were inserted 
+  ARP cache entries are typically inserted and updated by network protocol drivers
+  as network traffic is processed. Most ARP cache entries will time out and be
+  deleted if the network traffic stops. ARP cache entries that were inserted
   by the Add() function may be static (will not time out) or dynamic (will time out).
-  Default ARP cache timeout values are not covered in most network protocol 
-  specifications (although RFC 1122 comes pretty close) and will only be 
-  discussed in general terms in this specification. The timeout values that are 
-  used in the EFI Sample Implementation should be used only as a guideline. 
-  Final product implementations of the EFI network stack should be tuned for 
+  Default ARP cache timeout values are not covered in most network protocol
+  specifications (although RFC 1122 comes pretty close) and will only be
+  discussed in general terms in this specification. The timeout values that are
+  used in the EFI Sample Implementation should be used only as a guideline.
+  Final product implementations of the EFI network stack should be tuned for
   their expected network environments.
-  
+
   @param  This                   Pointer to the EFI_ARP_PROTOCOL instance.
   @param  DenyFlag               Set to TRUE if this entry is a deny entry. Set to
                                  FALSE if this  entry is a normal entry.
@@ -184,10 +178,10 @@ EFI_STATUS
 
   @retval EFI_SUCCESS            The entry has been added or updated.
   @retval EFI_INVALID_PARAMETER  One or more of the following conditions is TRUE:
-                                 * This is NULL. 
-                                 * DenyFlag is FALSE and TargetHwAddress is NULL. 
-                                 * DenyFlag is FALSE and TargetSwAddress is NULL. 
-                                 * TargetHwAddress is NULL and TargetSwAddress is NULL. 
+                                 * This is NULL.
+                                 * DenyFlag is FALSE and TargetHwAddress is NULL.
+                                 * DenyFlag is FALSE and TargetSwAddress is NULL.
+                                 * TargetHwAddress is NULL and TargetSwAddress is NULL.
                                  * Neither TargetSwAddress nor TargetHwAddress are NULL when DenyFlag is
                                  TRUE.
   @retval EFI_OUT_OF_RESOURCES   The new ARP cache entry could not be allocated.
@@ -205,24 +199,24 @@ EFI_STATUS
   IN VOID                   *TargetHwAddress  OPTIONAL,
   IN UINT32                 TimeoutValue,
   IN BOOLEAN                Overwrite
-  );  
+  );
 
 /**
   This function searches the ARP cache for matching entries and allocates a buffer into
   which those entries are copied.
-  
-  The first part of the allocated buffer is EFI_ARP_FIND_DATA, following which 
+
+  The first part of the allocated buffer is EFI_ARP_FIND_DATA, following which
   are protocol address pairs and hardware address pairs.
-  When finding a specific protocol address (BySwAddress is TRUE and AddressBuffer 
-  is not NULL), the ARP cache timeout for the found entry is reset if Refresh is 
-  set to TRUE. If the found ARP cache entry is a permanent entry, it is not 
+  When finding a specific protocol address (BySwAddress is TRUE and AddressBuffer
+  is not NULL), the ARP cache timeout for the found entry is reset if Refresh is
+  set to TRUE. If the found ARP cache entry is a permanent entry, it is not
   affected by Refresh.
-  
+
   @param  This                   The pointer to the EFI_ARP_PROTOCOL instance.
   @param  BySwAddress            Set to TRUE to look for matching software protocol
                                  addresses. Set to FALSE to look for matching
                                  hardware protocol addresses.
-  @param  AddressBuffer          The pointer to the address buffer. Set to NULL 
+  @param  AddressBuffer          The pointer to the address buffer. Set to NULL
                                  to match all addresses.
   @param  EntryLength            The size of an entry in the entries buffer.
   @param  EntryCount             The number of ARP cache entries that are found by
@@ -241,7 +235,7 @@ EFI_STATUS
   @retval EFI_NOT_STARTED        The ARP driver instance has not been configured.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_ARP_FIND)(
   IN EFI_ARP_PROTOCOL       *This,
@@ -251,7 +245,7 @@ EFI_STATUS
   OUT UINT32                *EntryCount       OPTIONAL,
   OUT EFI_ARP_FIND_DATA     **Entries         OPTIONAL,
   IN BOOLEAN                Refresh
-  );  
+  );
 
 
 /**
@@ -277,7 +271,7 @@ EFI_STATUS
   IN EFI_ARP_PROTOCOL       *This,
   IN BOOLEAN                BySwAddress,
   IN VOID                   *AddressBuffer   OPTIONAL
-  );  
+  );
 
 /**
   This function delete all dynamic entries from the ARP cache that match the specified
@@ -295,7 +289,7 @@ typedef
 EFI_STATUS
 (EFIAPI *EFI_ARP_FLUSH)(
   IN EFI_ARP_PROTOCOL       *This
-  );  
+  );
 
 /**
   This function tries to resolve the TargetSwAddress and optionally returns a
@@ -322,22 +316,22 @@ EFI_STATUS
 typedef
 EFI_STATUS
 (EFIAPI *EFI_ARP_REQUEST)(
-  IN EFI_ARP_PROTOCOL       *This, 
+  IN EFI_ARP_PROTOCOL       *This,
   IN VOID                   *TargetSwAddress  OPTIONAL,
   IN EFI_EVENT              ResolvedEvent     OPTIONAL,
-  OUT VOID                  *TargetHwAddress  
-  );  
+  OUT VOID                  *TargetHwAddress
+  );
 
 /**
   This function aborts the previous ARP request (identified by This, TargetSwAddress
   and ResolvedEvent) that is issued by EFI_ARP_PROTOCOL.Request().
-  
-  If the request is in the internal ARP request queue, the request is aborted 
-  immediately and its ResolvedEvent is signaled. Only an asynchronous address 
-  request needs to be canceled. If TargeSwAddress and ResolveEvent are both 
-  NULL, all the pending asynchronous requests that have been issued by This 
+
+  If the request is in the internal ARP request queue, the request is aborted
+  immediately and its ResolvedEvent is signaled. Only an asynchronous address
+  request needs to be canceled. If TargeSwAddress and ResolveEvent are both
+  NULL, all the pending asynchronous requests that have been issued by This
   instance will be cancelled and their corresponding events will be signaled.
-  
+
   @param  This                   The pointer to the EFI_ARP_PROTOCOL instance.
   @param  TargetSwAddress        The pointer to the protocol address in previous
                                  request session.
@@ -359,13 +353,13 @@ EFI_STATUS
 typedef
 EFI_STATUS
 (EFIAPI *EFI_ARP_CANCEL)(
-  IN EFI_ARP_PROTOCOL       *This, 
+  IN EFI_ARP_PROTOCOL       *This,
   IN VOID                   *TargetSwAddress  OPTIONAL,
   IN EFI_EVENT              ResolvedEvent     OPTIONAL
-  );  
+  );
 
 ///
-/// ARP is used to resolve local network protocol addresses into 
+/// ARP is used to resolve local network protocol addresses into
 /// network hardware addresses.
 ///
 struct _EFI_ARP_PROTOCOL {
diff --git a/MdePkg/Include/Protocol/AtaPassThru.h b/MdePkg/Include/Protocol/AtaPassThru.h
index 1cc596f9e424..06b7c31d09ea 100644
--- a/MdePkg/Include/Protocol/AtaPassThru.h
+++ b/MdePkg/Include/Protocol/AtaPassThru.h
@@ -3,14 +3,11 @@
   to send ATA Command Blocks to any ATA device attached to that ATA controller. The information
   includes the attributes of the ATA controller.
 
-  Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
+  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  @par Revision Reference:
+  This Protocol was introduced in UEFI Specification 2.3.
 
 **/
 
@@ -56,7 +53,7 @@ typedef struct _EFI_ATA_COMMAND_BLOCK {
   UINT8 AtaDeviceHead;
   UINT8 AtaSectorNumberExp;
   UINT8 AtaCylinderLowExp;
-  UINT8 AtaCylinderHighExp; 
+  UINT8 AtaCylinderHighExp;
   UINT8 AtaFeaturesExp;
   UINT8 AtaSectorCount;
   UINT8 AtaSectorCountExp;
@@ -73,7 +70,7 @@ typedef struct _EFI_ATA_STATUS_BLOCK {
   UINT8 AtaDeviceHead;
   UINT8 AtaSectorNumberExp;
   UINT8 AtaCylinderLowExp;
-  UINT8 AtaCylinderHighExp; 
+  UINT8 AtaCylinderHighExp;
   UINT8 Reserved2;
   UINT8 AtaSectorCount;
   UINT8 AtaSectorCountExp;
@@ -156,7 +153,7 @@ typedef struct {
   ///
   /// On Input, the size, in bytes of OutDataBuffer. On Output, the Number of bytes
   /// transferred between ATA Controller and the ATA device. If OutTransferLength is
-  /// larger than the ATA controller can handle, no data will be transferred, 
+  /// larger than the ATA controller can handle, no data will be transferred,
   /// OutTransferLength will be updated to contain the number of bytes that the ATA
   /// controller is able to transfer, and EFI_BAD_BUFFER_SIZE will be returned.
   ///
@@ -177,8 +174,8 @@ typedef struct {
   supports both blocking I/O and non-blocking I/O. The blocking I/O functionality is required,
   and the non-blocking I/O functionality is optional.
 
-  @param[in]     This                A pointer to the EFI_ATA_PASS_THRU_PROTOCOL instance. 
-  @param[in]     Port                The port number of the ATA device to send the command. 
+  @param[in]     This                A pointer to the EFI_ATA_PASS_THRU_PROTOCOL instance.
+  @param[in]     Port                The port number of the ATA device to send the command.
   @param[in]     PortMultiplierPort  The port multiplier port number of the ATA device to send the command.
                                      If there is no port multiplier, then specify 0xFFFF.
   @param[in,out] Packet              A pointer to the ATA command to send to the ATA device specified by Port
@@ -188,11 +185,11 @@ typedef struct {
                                      Event is not NULL and non blocking I/O is supported, then non-blocking
                                      I/O is performed, and Event will be signaled when the ATA command completes.
 
-  @retval EFI_SUCCESS                The ATA command was sent by the host. For bi-directional commands, 
+  @retval EFI_SUCCESS                The ATA command was sent by the host. For bi-directional commands,
                                      InTransferLength bytes were transferred from InDataBuffer. For write and
                                      bi-directional commands, OutTransferLength bytes were transferred by OutDataBuffer.
   @retval EFI_BAD_BUFFER_SIZE        The ATA command was not executed. The number of bytes that could be transferred
-                                     is returned in InTransferLength. For write and bi-directional commands, 
+                                     is returned in InTransferLength. For write and bi-directional commands,
                                      OutTransferLength bytes were transferred by OutDataBuffer.
   @retval EFI_NOT_READY              The ATA command could not be sent because there are too many ATA commands
                                      already queued. The caller may retry again later.
@@ -230,7 +227,7 @@ EFI_STATUS
   If Port is the port number of the last port on the ATA controller, then EFI_NOT_FOUND is
   returned.
 
-  @param[in]     This           A pointer to the EFI_ATA_PASS_THRU_PROTOCOL instance. 
+  @param[in]     This           A pointer to the EFI_ATA_PASS_THRU_PROTOCOL instance.
   @param[in,out] Port           On input, a pointer to the port number on the ATA controller.
                                 On output, a pointer to the next port number on the ATA
                                 controller. An input value of 0xFFFF retrieves the first port
@@ -250,36 +247,36 @@ EFI_STATUS
   );
 
 /**
-  Used to retrieve the list of legal port multiplier port numbers for ATA devices on a port of an ATA 
-  controller. These can either be the list of port multiplier ports where ATA devices are actually 
-  present on port or the list of legal port multiplier ports on that port. Regardless, the caller of this 
-  function must probe the port number and port multiplier port number returned to see if an ATA 
+  Used to retrieve the list of legal port multiplier port numbers for ATA devices on a port of an ATA
+  controller. These can either be the list of port multiplier ports where ATA devices are actually
+  present on port or the list of legal port multiplier ports on that port. Regardless, the caller of this
+  function must probe the port number and port multiplier port number returned to see if an ATA
   device is actually present.
 
-  The GetNextDevice() function retrieves the port multiplier port number of an ATA device 
+  The GetNextDevice() function retrieves the port multiplier port number of an ATA device
   present on a port of an ATA controller.
-  
-  If PortMultiplierPort points to a port multiplier port number value that was returned on a 
+
+  If PortMultiplierPort points to a port multiplier port number value that was returned on a
   previous call to GetNextDevice(), then the port multiplier port number of the next ATA device
   on the port of the ATA controller is returned in PortMultiplierPort, and EFI_SUCCESS is
   returned.
-  
-  If PortMultiplierPort points to 0xFFFF, then the port multiplier port number of the first 
-  ATA device on port of the ATA controller is returned in PortMultiplierPort and 
+
+  If PortMultiplierPort points to 0xFFFF, then the port multiplier port number of the first
+  ATA device on port of the ATA controller is returned in PortMultiplierPort and
   EFI_SUCCESS is returned.
-  
+
   If PortMultiplierPort is not 0xFFFF and the value pointed to by PortMultiplierPort
   was not returned on a previous call to GetNextDevice(), then EFI_INVALID_PARAMETER
   is returned.
-  
-  If PortMultiplierPort is the port multiplier port number of the last ATA device on the port of 
+
+  If PortMultiplierPort is the port multiplier port number of the last ATA device on the port of
   the ATA controller, then EFI_NOT_FOUND is returned.
 
   @param[in]     This                A pointer to the EFI_ATA_PASS_THRU_PROTOCOL instance.
   @param[in]     Port                The port number present on the ATA controller.
   @param[in,out] PortMultiplierPort  On input, a pointer to the port multiplier port number of an
-                                     ATA device present on the ATA controller. 
-                                     If on input a PortMultiplierPort of 0xFFFF is specified, 
+                                     ATA device present on the ATA controller.
+                                     If on input a PortMultiplierPort of 0xFFFF is specified,
                                      then the port multiplier port number of the first ATA device
                                      is returned. On output, a pointer to the port multiplier port
                                      number of the next ATA device present on an ATA controller.
@@ -318,7 +315,7 @@ EFI_STATUS
   @param[in]     PortMultiplierPort  The port multiplier port number of the ATA device for which a
                                      device path node is to be allocated and built. If there is no
                                      port multiplier, then specify 0xFFFF.
-  @param[in,out] DevicePath          A pointer to a single device path node that describes the ATA
+  @param[out]    DevicePath          A pointer to a single device path node that describes the ATA
                                      device specified by Port and PortMultiplierPort. This function
                                      is responsible for allocating the buffer DevicePath with the
                                      boot service AllocatePool(). It is the caller's responsibility
@@ -337,7 +334,7 @@ EFI_STATUS
   IN     EFI_ATA_PASS_THRU_PROTOCOL *This,
   IN     UINT16                     Port,
   IN     UINT16                     PortMultiplierPort,
-  IN OUT EFI_DEVICE_PATH_PROTOCOL   **DevicePath
+  OUT    EFI_DEVICE_PATH_PROTOCOL   **DevicePath
   );
 
 /**
@@ -345,7 +342,7 @@ EFI_STATUS
 
   The GetDevice() function determines the port and port multiplier port number associated with
   the ATA device described by DevicePath. If DevicePath is a device path node type that the
-  ATA Pass Thru driver supports, then the ATA Pass Thru driver will attempt to translate the contents 
+  ATA Pass Thru driver supports, then the ATA Pass Thru driver will attempt to translate the contents
   DevicePath into a port number and port multiplier port number.
 
   If this translation is successful, then that port number and port multiplier port number are returned
@@ -353,11 +350,11 @@ EFI_STATUS
 
   If DevicePath, Port, or PortMultiplierPort are NULL, then EFI_INVALID_PARAMETER is returned.
 
-  If DevicePath is not a device path node type that the ATA Pass Thru driver supports, then 
+  If DevicePath is not a device path node type that the ATA Pass Thru driver supports, then
   EFI_UNSUPPORTED is returned.
 
-  If DevicePath is a device path node type that the ATA Pass Thru driver supports, but there is not 
-  a valid translation from DevicePath to a port number and port multiplier port number, then 
+  If DevicePath is a device path node type that the ATA Pass Thru driver supports, but there is not
+  a valid translation from DevicePath to a port number and port multiplier port number, then
   EFI_NOT_FOUND is returned.
 
   @param[in]  This                A pointer to the EFI_ATA_PASS_THRU_PROTOCOL instance.
@@ -423,7 +420,7 @@ EFI_STATUS
   If this ATA controller does not support a device reset operation, then EFI_UNSUPPORTED is
   returned.
 
-  If Port or PortMultiplierPort are not in a valid range for this ATA controller, then 
+  If Port or PortMultiplierPort are not in a valid range for this ATA controller, then
   EFI_INVALID_PARAMETER is returned.
 
   If a device error occurs while executing that device reset operation, then EFI_DEVICE_ERROR
diff --git a/MdePkg/Include/Protocol/AuthenticationInfo.h b/MdePkg/Include/Protocol/AuthenticationInfo.h
index 99e20235913a..fe85c2a0a16d 100644
--- a/MdePkg/Include/Protocol/AuthenticationInfo.h
+++ b/MdePkg/Include/Protocol/AuthenticationInfo.h
@@ -1,16 +1,10 @@
 /** @file
   EFI_AUTHENTICATION_INFO_PROTOCOL as defined in UEFI 2.0.
-  This protocol is used on any device handle to obtain authentication information 
+  This protocol is used on any device handle to obtain authentication information
   associated with the physical or logical device.
 
-Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -21,7 +15,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   { \
     0x7671d9d0, 0x53db, 0x4173, {0xaa, 0x69, 0x23, 0x27, 0xf2, 0x1f, 0x0b, 0xc7 } \
   }
-  
+
 #define EFI_AUTHENTICATION_CHAP_RADIUS_GUID \
   { \
     0xd6062b50, 0x15ca, 0x11da, {0x92, 0x19, 0x00, 0x10, 0x83, 0xff, 0xca, 0x4d } \
@@ -75,7 +69,7 @@ typedef struct {
   ///
   UINT8            NasSecret[1];
 
-  /// 
+  ///
   /// CHAP Initiator Secret Length in bytes on offset NasSecret + NasSecretLength.
   ///
   /// UINT16           ChapSecretLength;
@@ -181,11 +175,11 @@ typedef struct {
                                     responsible for allocating the buffer and it is the caller's
                                     responsibility to free buffer when the caller is finished with buffer.
 
-  @retval EFI_SUCCESS           Successfully retrieved authentication information 
+  @retval EFI_SUCCESS           Successfully retrieved authentication information
                                 for the given ControllerHandle.
-  @retval EFI_INVALID_PARAMETER No matching authentication information found for 
+  @retval EFI_INVALID_PARAMETER No matching authentication information found for
                                 the given ControllerHandle.
-  @retval EFI_DEVICE_ERROR      The authentication information could not be retrieved 
+  @retval EFI_DEVICE_ERROR      The authentication information could not be retrieved
                                 due to a hardware error.
 
 **/
@@ -203,12 +197,12 @@ EFI_STATUS
   @param[in]  This                 The pointer to the EFI_AUTHENTICATION_INFO_PROTOCOL.
   @param[in]  ControllerHandle     The handle to the Controller.
   @param[in]  Buffer               The pointer to the authentication information.
-                                
-  @retval EFI_SUCCESS          Successfully set authentication information for the 
+
+  @retval EFI_SUCCESS          Successfully set authentication information for the
                                given ControllerHandle.
-  @retval EFI_UNSUPPORTED      If the platform policies do not allow setting of 
+  @retval EFI_UNSUPPORTED      If the platform policies do not allow setting of
                                the authentication information.
-  @retval EFI_DEVICE_ERROR     The authentication information could not be configured 
+  @retval EFI_DEVICE_ERROR     The authentication information could not be configured
                                due to a hardware error.
   @retval EFI_OUT_OF_RESOURCES Not enough storage is available to hold the data.
 
@@ -219,10 +213,10 @@ EFI_STATUS
   IN EFI_AUTHENTICATION_INFO_PROTOCOL  *This,
   IN EFI_HANDLE                        ControllerHandle,
   IN VOID                              *Buffer
-  );  
+  );
 
 ///
-/// This protocol is used on any device handle to obtain authentication 
+/// This protocol is used on any device handle to obtain authentication
 /// information associated with the physical or logical device.
 ///
 struct _EFI_AUTHENTICATION_INFO_PROTOCOL {
diff --git a/MdePkg/Include/Protocol/Bds.h b/MdePkg/Include/Protocol/Bds.h
index 0ecc66c8cab3..7ca7777c9ea0 100644
--- a/MdePkg/Include/Protocol/Bds.h
+++ b/MdePkg/Include/Protocol/Bds.h
@@ -3,14 +3,8 @@
 
   When the DXE core is done it calls the BDS via this protocol.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -29,19 +23,19 @@
 typedef struct _EFI_BDS_ARCH_PROTOCOL   EFI_BDS_ARCH_PROTOCOL;
 
 /**
-  This function uses policy data from the platform to determine what operating 
-  system or system utility should be loaded and invoked.  This function call 
-  also optionally make the use of user input to determine the operating system 
-  or system utility to be loaded and invoked.  When the DXE Core has dispatched 
-  all the drivers on the dispatch queue, this function is called.  This 
-  function will attempt to connect the boot devices required to load and invoke 
-  the selected operating system or system utility.  During this process, 
-  additional firmware volumes may be discovered that may contain addition DXE 
-  drivers that can be dispatched by the DXE Core.   If a boot device cannot be 
-  fully connected, this function calls the DXE Service Dispatch() to allow the 
-  DXE drivers from any newly discovered firmware volumes to be dispatched.  
-  Then the boot device connection can be attempted again.  If the same boot 
-  device connection operation fails twice in a row, then that boot device has 
+  This function uses policy data from the platform to determine what operating
+  system or system utility should be loaded and invoked.  This function call
+  also optionally make the use of user input to determine the operating system
+  or system utility to be loaded and invoked.  When the DXE Core has dispatched
+  all the drivers on the dispatch queue, this function is called.  This
+  function will attempt to connect the boot devices required to load and invoke
+  the selected operating system or system utility.  During this process,
+  additional firmware volumes may be discovered that may contain addition DXE
+  drivers that can be dispatched by the DXE Core.   If a boot device cannot be
+  fully connected, this function calls the DXE Service Dispatch() to allow the
+  DXE drivers from any newly discovered firmware volumes to be dispatched.
+  Then the boot device connection can be attempted again.  If the same boot
+  device connection operation fails twice in a row, then that boot device has
   failed, and should be skipped.  This function should never return.
 
   @param  This             The EFI_BDS_ARCH_PROTOCOL instance.
@@ -56,11 +50,11 @@ VOID
   );
 
 ///
-/// The EFI_BDS_ARCH_PROTOCOL transfers control from DXE to an operating 
-/// system or a system utility.  If there are not enough drivers initialized 
-/// when this protocol is used to access the required boot device(s), then 
-/// this protocol should add drivers to the dispatch queue and return control 
-/// back to the dispatcher.  Once the required boot devices are available, then 
+/// The EFI_BDS_ARCH_PROTOCOL transfers control from DXE to an operating
+/// system or a system utility.  If there are not enough drivers initialized
+/// when this protocol is used to access the required boot device(s), then
+/// this protocol should add drivers to the dispatch queue and return control
+/// back to the dispatcher.  Once the required boot devices are available, then
 /// the boot device can be used to load and invoke an OS or a system utility.
 ///
 struct _EFI_BDS_ARCH_PROTOCOL {
diff --git a/MdePkg/Include/Protocol/Bis.h b/MdePkg/Include/Protocol/Bis.h
index b3ac58ec0302..23dc6577fbf0 100644
--- a/MdePkg/Include/Protocol/Bis.h
+++ b/MdePkg/Include/Protocol/Bis.h
@@ -1,18 +1,12 @@
 /** @file
-  The EFI_BIS_PROTOCOL is used to check a digital signature of a data block 
+  The EFI_BIS_PROTOCOL is used to check a digital signature of a data block
   against a digital certificate for the purpose of an integrity and authorization check.
 
-Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.        
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
-  @par Revision Reference:          
-  This Protocol is introduced in EFI Specification 1.10.     
+  @par Revision Reference:
+  This Protocol is introduced in EFI Specification 1.10.
 
 **/
 
@@ -122,32 +116,32 @@ typedef struct {
 #define BOOT_OBJECT_AUTHORIZATION_PARMSET_GUIDVALUE \
         BOOT_OBJECT_AUTHORIZATION_PARMSET_GUID
 
-/**                                                                 
+/**
   Initializes the BIS service, checking that it is compatible with the version requested by the caller.
-  After this call, other BIS functions may be invoked.                                                 
-    
+  After this call, other BIS functions may be invoked.
+
   @param  This                     A pointer to the EFI_BIS_PROTOCOL object.
-  @param  AppHandle                The function writes the new BIS_APPLICATION_HANDLE if           
+  @param  AppHandle                The function writes the new BIS_APPLICATION_HANDLE if
                                    successful, otherwise it writes NULL. The caller must eventually
-                                   destroy this handle by calling Shutdown().                      
+                                   destroy this handle by calling Shutdown().
   @param  InterfaceVersion         On input, the caller supplies the major version number of the
-                                   interface version desired.                                   
-                                   On output, both the major and minor                         
+                                   interface version desired.
+                                   On output, both the major and minor
                                    version numbers are updated with the major and minor version
                                    numbers of the interface. This update is done whether or not the
-                                   initialization was successful.                                    
-  @param  TargetAddress            Indicates a network or device address of the BIS platform to connect to.                                                                 
+                                   initialization was successful.
+  @param  TargetAddress            Indicates a network or device address of the BIS platform to connect to.
 
   @retval EFI_SUCCESS              The function completed successfully.
-  @retval EFI_INCOMPATIBLE_VERSION The InterfaceVersion.Major requested by the                
+  @retval EFI_INCOMPATIBLE_VERSION The InterfaceVersion.Major requested by the
                                    caller was not compatible with the interface version of the
                                    implementation. The InterfaceVersion.Major has
                                    been updated with the current interface version.
-  @retval EFI_UNSUPPORTED          This is a local-platform implementation and        
-                                   TargetAddress.Data was not NULL, or                
+  @retval EFI_UNSUPPORTED          This is a local-platform implementation and
+                                   TargetAddress.Data was not NULL, or
                                    TargetAddress.Data was any other value that was not
-                                   supported by the implementation.                   
-  @retval EFI_OUT_OF_RESOURCES     The function failed due to lack of memory or other resources.                              
+                                   supported by the implementation.
+  @retval EFI_OUT_OF_RESOURCES     The function failed due to lack of memory or other resources.
   @retval EFI_DEVICE_ERROR         One of the following device errors:
                                    * The function encountered an unexpected internal failure while initializing a cryptographic software module
                                    * No cryptographic software module with compatible version was found
@@ -161,51 +155,51 @@ typedef struct {
                                    is NULL or an invalid memory reference. Or,
                                    the TargetAddress parameter supplied by the caller is
                                    NULL or an invalid memory reference.
-                                          
-**/                                       
+
+**/
 typedef
 EFI_STATUS
 (EFIAPI *EFI_BIS_INITIALIZE)(
-  IN     EFI_BIS_PROTOCOL        *This,              
-  OUT    BIS_APPLICATION_HANDLE  *AppHandle,         
-  IN OUT EFI_BIS_VERSION         *InterfaceVersion,  
-  IN     EFI_BIS_DATA            *TargetAddress      
+  IN     EFI_BIS_PROTOCOL        *This,
+  OUT    BIS_APPLICATION_HANDLE  *AppHandle,
+  IN OUT EFI_BIS_VERSION         *InterfaceVersion,
+  IN     EFI_BIS_DATA            *TargetAddress
   );
 
-/**                                                                 
-  Frees memory structures allocated and returned by other functions in the EFI_BIS protocol.  
-      
+/**
+  Frees memory structures allocated and returned by other functions in the EFI_BIS protocol.
+
   @param  AppHandle                An opaque handle that identifies the caller's instance of initialization
-                                   of the BIS service.                                                                                         
-  @param  ToFree                   An EFI_BIS_DATA* and associated memory block to be freed. 
+                                   of the BIS service.
+  @param  ToFree                   An EFI_BIS_DATA* and associated memory block to be freed.
                                    This EFI_BIS_DATA* must have been allocated by one of the other BIS functions.
 
   @retval EFI_SUCCESS              The function completed successfully.
   @retval EFI_NO_MAPPING           The AppHandle parameter is not or is no longer a valid
-                                   application instance handle associated with the EFI_BIS protocol.                                     
-  @retval EFI_OUT_OF_RESOURCES     The function failed due to lack of memory or other resources.                                
+                                   application instance handle associated with the EFI_BIS protocol.
+  @retval EFI_OUT_OF_RESOURCES     The function failed due to lack of memory or other resources.
   @retval EFI_INVALID_PARAMETER    The ToFree parameter is not or is no longer a memory resource
-                                   associated with this AppHandle.                              
-                                           
-**/     
+                                   associated with this AppHandle.
+
+**/
 typedef
 EFI_STATUS
 (EFIAPI *EFI_BIS_FREE)(
-  IN BIS_APPLICATION_HANDLE  AppHandle,               
-  IN EFI_BIS_DATA            *ToFree                  
+  IN BIS_APPLICATION_HANDLE  AppHandle,
+  IN EFI_BIS_DATA            *ToFree
   );
 
-/**                                                                 
+/**
   Shuts down an application's instance of the BIS service, invalidating the application handle. After
-  this call, other BIS functions may no longer be invoked using the application handle value.         
-      
+  this call, other BIS functions may no longer be invoked using the application handle value.
+
   @param  AppHandle                An opaque handle that identifies the caller's instance of initialization
-                                   of the BIS service.                                                                                           
+                                   of the BIS service.
 
   @retval EFI_SUCCESS              The function completed successfully.
   @retval EFI_NO_MAPPING           The AppHandle parameter is not, or is no longer, a valid
-                                   application instance handle associated with the EFI_BIS protocol.                                     
-  @retval EFI_OUT_OF_RESOURCES     The function failed due to lack of memory or other resources.                                
+                                   application instance handle associated with the EFI_BIS protocol.
+  @retval EFI_OUT_OF_RESOURCES     The function failed due to lack of memory or other resources.
   @retval EFI_DEVICE_ERROR         The function encountered an unexpected internal failure while
                                    returning resources associated with a cryptographic software module, or
                                    while trying to shut down a cryptographic software module.
@@ -213,206 +207,206 @@ EFI_STATUS
 typedef
 EFI_STATUS
 (EFIAPI *EFI_BIS_SHUTDOWN)(
-  IN BIS_APPLICATION_HANDLE  AppHandle               
+  IN BIS_APPLICATION_HANDLE  AppHandle
   );
 
-/**                                                                 
+/**
   Retrieves the certificate that has been configured as the identity of the organization designated as
   the source of authorization for signatures of boot objects.
-      
+
   @param  AppHandle                An opaque handle that identifies the caller's instance of initialization
-                                   of the BIS service.                                                                                           
+                                   of the BIS service.
   @param  Certificate              The function writes an allocated EFI_BIS_DATA* containing the Boot
                                    Object Authorization Certificate object.  The caller must
                                    eventually free the memory allocated by this function using the function Free().
 
   @retval EFI_SUCCESS              The function completed successfully.
   @retval EFI_NO_MAPPING           The AppHandle parameter is not or is no longer a valid
-                                   application instance handle associated with the EFI_BIS protocol.                                     
-  @retval EFI_NOT_FOUND            There is no Boot Object Authorization Certificate currently installed.                        
-  @retval EFI_OUT_OF_RESOURCES     The function failed due to lack of memory or other resources.                                
+                                   application instance handle associated with the EFI_BIS protocol.
+  @retval EFI_NOT_FOUND            There is no Boot Object Authorization Certificate currently installed.
+  @retval EFI_OUT_OF_RESOURCES     The function failed due to lack of memory or other resources.
   @retval EFI_INVALID_PARAMETER    The Certificate parameter supplied by the caller is NULL or
-                                   an invalid memory reference.                                       
-                                   
-**/ 
+                                   an invalid memory reference.
+
+**/
 typedef
 EFI_STATUS
 (EFIAPI *EFI_BIS_GET_BOOT_OBJECT_AUTHORIZATION_CERTIFICATE)(
-  IN  BIS_APPLICATION_HANDLE  AppHandle,              
-  OUT EFI_BIS_DATA            **Certificate           
+  IN  BIS_APPLICATION_HANDLE  AppHandle,
+  OUT EFI_BIS_DATA            **Certificate
   );
 
-/**                                                                 
+/**
   Verifies the integrity and authorization of the indicated data object according to the
-  indicated credentials.                                                                
-      
+  indicated credentials.
+
   @param  AppHandle                An opaque handle that identifies the caller's instance of initialization
-                                   of the BIS service.                                                                                           
+                                   of the BIS service.
   @param  Credentials              A Signed Manifest containing verification information for the indicated
-                                   data object.                                                            
+                                   data object.
   @param  DataObject               An in-memory copy of the raw data object to be verified.
   @param  IsVerified               The function writes TRUE if the verification succeeded, otherwise
-                                   FALSE.                                                           
-                                   
+                                   FALSE.
+
   @retval EFI_SUCCESS              The function completed successfully.
   @retval EFI_NO_MAPPING           The AppHandle parameter is not or is no longer a valid
-                                   application instance handle associated with the EFI_BIS protocol.                                       
-  @retval EFI_OUT_OF_RESOURCES     The function failed due to lack of memory or other resources.                                
+                                   application instance handle associated with the EFI_BIS protocol.
+  @retval EFI_OUT_OF_RESOURCES     The function failed due to lack of memory or other resources.
   @retval EFI_INVALID_PARAMETER    One or more parameters are invalid.
   @retval EFI_SECURITY_VIOLATION   The signed manifest supplied as the Credentials parameter
                                    was invalid (could not be parsed) or Platform-specific authorization failed, etc.
-  @retval EFI_DEVICE_ERROR         An unexpected internal error occurred.                           
-                                   
-**/ 
+  @retval EFI_DEVICE_ERROR         An unexpected internal error occurred.
+
+**/
 typedef
 EFI_STATUS
 (EFIAPI *EFI_BIS_VERIFY_BOOT_OBJECT)(
-  IN  BIS_APPLICATION_HANDLE AppHandle,               
-  IN  EFI_BIS_DATA           *Credentials,            
-  IN  EFI_BIS_DATA           *DataObject,             
-  OUT BOOLEAN                *IsVerified              
+  IN  BIS_APPLICATION_HANDLE AppHandle,
+  IN  EFI_BIS_DATA           *Credentials,
+  IN  EFI_BIS_DATA           *DataObject,
+  OUT BOOLEAN                *IsVerified
   );
 
-/**                                                                 
+/**
   Retrieves the current status of the Boot Authorization Check Flag.
-      
+
   @param  AppHandle                An opaque handle that identifies the caller's instance of initialization
-                                   of the BIS service.                                                                                           
+                                   of the BIS service.
   @param  CheckIsRequired          The function writes the value TRUE if a Boot Authorization Check is
-                                   currently required on this platform, otherwise the function writes 
-                                   FALSE.                                                             
-                                   
+                                   currently required on this platform, otherwise the function writes
+                                   FALSE.
+
   @retval EFI_SUCCESS              The function completed successfully.
   @retval EFI_NO_MAPPING           The AppHandle parameter is not or is no longer a valid
-                                   application instance handle associated with the EFI_BIS protocol.                                       
-  @retval EFI_OUT_OF_RESOURCES     The function failed due to lack of memory or other resources.                                
+                                   application instance handle associated with the EFI_BIS protocol.
+  @retval EFI_OUT_OF_RESOURCES     The function failed due to lack of memory or other resources.
   @retval EFI_INVALID_PARAMETER    The CheckIsRequired parameter supplied by the caller is
-                                   NULL or an invalid memory reference.                   
-                                   
-**/ 
+                                   NULL or an invalid memory reference.
+
+**/
 typedef
 EFI_STATUS
 (EFIAPI *EFI_BIS_GET_BOOT_OBJECT_AUTHORIZATION_CHECKFLAG)(
-  IN  BIS_APPLICATION_HANDLE  AppHandle,             
-  OUT BOOLEAN                 *CheckIsRequired       
+  IN  BIS_APPLICATION_HANDLE  AppHandle,
+  OUT BOOLEAN                 *CheckIsRequired
   );
 
-/**                                                                 
+/**
   Retrieves a unique token value to be included in the request credential for the next update of any
-  parameter in the Boot Object Authorization set                                                    
-      
-  @param  AppHandle                An opaque handle that identifies the caller's 
-                                   instance of initialization of the BIS service.                                                                                           
-  @param  UpdateToken              The function writes an allocated EFI_BIS_DATA* 
-                                   containing the newunique update token value.  
-                                   The caller musteventually free the memory allocated  
+  parameter in the Boot Object Authorization set
+
+  @param  AppHandle                An opaque handle that identifies the caller's
+                                   instance of initialization of the BIS service.
+  @param  UpdateToken              The function writes an allocated EFI_BIS_DATA*
+                                   containing the newunique update token value.
+                                   The caller musteventually free the memory allocated
                                    by this function using the function Free().
-                                   
+
   @retval EFI_SUCCESS              The function completed successfully.
   @retval EFI_NO_MAPPING           The AppHandle parameter is not or is no longer a valid
-                                   application instance handle associated with the EFI_BIS protocol.                                       
-  @retval EFI_OUT_OF_RESOURCES     The function failed due to lack of memory or other resources.                                
+                                   application instance handle associated with the EFI_BIS protocol.
+  @retval EFI_OUT_OF_RESOURCES     The function failed due to lack of memory or other resources.
   @retval EFI_INVALID_PARAMETER    The UpdateToken parameter supplied by the caller is NULL or
-                                   an invalid memory reference.        
-  @retval EFI_DEVICE_ERROR         An unexpected internal error occurred.                                                            
-                                   
-**/ 
+                                   an invalid memory reference.
+  @retval EFI_DEVICE_ERROR         An unexpected internal error occurred.
+
+**/
 typedef
 EFI_STATUS
 (EFIAPI *EFI_BIS_GET_BOOT_OBJECT_AUTHORIZATION_UPDATE_TOKEN)(
-  IN  BIS_APPLICATION_HANDLE  AppHandle,              
-  OUT EFI_BIS_DATA            **UpdateToken           
+  IN  BIS_APPLICATION_HANDLE  AppHandle,
+  OUT EFI_BIS_DATA            **UpdateToken
   );
 
-/**                                                                 
+/**
   Updates one of the configurable parameters of the Boot Object Authorization set.
-      
-  @param  AppHandle                An opaque handle that identifies the caller's 
-                                   instance of initialization of the BIS service.                                                                                           
-  @param  RequestCredential        This is a Signed Manifest with embedded attributes 
-                                   that carry the details of the requested update.                                                 
-  @param  NewUpdateToken           The function writes an allocated EFI_BIS_DATA* 
-                                   containing the new unique update token value. 
-                                   The caller must eventually free the memory allocated  
+
+  @param  AppHandle                An opaque handle that identifies the caller's
+                                   instance of initialization of the BIS service.
+  @param  RequestCredential        This is a Signed Manifest with embedded attributes
+                                   that carry the details of the requested update.
+  @param  NewUpdateToken           The function writes an allocated EFI_BIS_DATA*
+                                   containing the new unique update token value.
+                                   The caller must eventually free the memory allocated
                                    by this function using the function Free().
-                                   
-  @retval EFI_SUCCESS              The function completed successfully.                                                
-  @retval EFI_NO_MAPPING           The AppHandle parameter is not or is no longer a valid                              
-                                   application instance handle associated with the EFI_BIS protocol.                   
-  @retval EFI_OUT_OF_RESOURCES     The function failed due to lack of memory or other resources.                       
-  @retval EFI_INVALID_PARAMETER    One or more parameters are invalid.                                                 
-  @retval EFI_SECURITY_VIOLATION   The signed manifest supplied as the RequestCredential parameter                           
-                                   was invalid (could not be parsed) or Platform-specific authorization failed, etc.   
+
+  @retval EFI_SUCCESS              The function completed successfully.
+  @retval EFI_NO_MAPPING           The AppHandle parameter is not or is no longer a valid
+                                   application instance handle associated with the EFI_BIS protocol.
+  @retval EFI_OUT_OF_RESOURCES     The function failed due to lack of memory or other resources.
+  @retval EFI_INVALID_PARAMETER    One or more parameters are invalid.
+  @retval EFI_SECURITY_VIOLATION   The signed manifest supplied as the RequestCredential parameter
+                                   was invalid (could not be parsed) or Platform-specific authorization failed, etc.
   @retval EFI_DEVICE_ERROR         An unexpected internal error occurred while analyzing the new
                                    certificate's key algorithm, or while attempting to retrieve
                                    the public key algorithm of the manifest's signer's certificate,
-                                   or An unexpected internal error occurred in a cryptographic software module.                                                                                                                                                                  
-                                   
-**/ 
+                                   or An unexpected internal error occurred in a cryptographic software module.
+
+**/
 typedef
 EFI_STATUS
 (EFIAPI *EFI_BIS_UPDATE_BOOT_OBJECT_AUTHORIZATION)(
-  IN  BIS_APPLICATION_HANDLE AppHandle,               
-  IN  EFI_BIS_DATA           *RequestCredential,      
-  OUT EFI_BIS_DATA           **NewUpdateToken         
+  IN  BIS_APPLICATION_HANDLE AppHandle,
+  IN  EFI_BIS_DATA           *RequestCredential,
+  OUT EFI_BIS_DATA           **NewUpdateToken
   );
 
-/**                                                                 
+/**
   Verifies the integrity and authorization of the indicated data object according to the indicated
-  credentials and authority certificate.                                                          
-      
+  credentials and authority certificate.
+
   @param  AppHandle                An opaque handle that identifies the caller's instance of initialization
-                                   of the BIS service.                                                                                           
+                                   of the BIS service.
   @param  Credentials              A Signed Manifest containing verification information for the
-                                   indicated data object.                                       
+                                   indicated data object.
   @param  DataObject               An in-memory copy of the raw data object to be verified.
-  @param  SectionName              An ASCII string giving the section name in the  
+  @param  SectionName              An ASCII string giving the section name in the
                                    manifest holding the verification information (in other words,
-                                   hash value) that corresponds to DataObject.                             
-  @param  AuthorityCertificate     A digital certificate whose public key must match the signer's                              
-                                   public key which is found in the credentials.                  
+                                   hash value) that corresponds to DataObject.
+  @param  AuthorityCertificate     A digital certificate whose public key must match the signer's
+                                   public key which is found in the credentials.
   @param  IsVerified               The function writes TRUE if the verification was successful.
-                                   Otherwise, the function writes FALSE.                       
-                                   
-  @retval EFI_SUCCESS              The function completed successfully.                                                
-  @retval EFI_NO_MAPPING           The AppHandle parameter is not or is no longer a valid                              
-                                   application instance handle associated with the EFI_BIS protocol.                   
-  @retval EFI_OUT_OF_RESOURCES     The function failed due to lack of memory or other resources.                       
-  @retval EFI_INVALID_PARAMETER    One or more parameters are invalid.                                                 
+                                   Otherwise, the function writes FALSE.
+
+  @retval EFI_SUCCESS              The function completed successfully.
+  @retval EFI_NO_MAPPING           The AppHandle parameter is not or is no longer a valid
+                                   application instance handle associated with the EFI_BIS protocol.
+  @retval EFI_OUT_OF_RESOURCES     The function failed due to lack of memory or other resources.
+  @retval EFI_INVALID_PARAMETER    One or more parameters are invalid.
   @retval EFI_SECURITY_VIOLATION   The Credentials.Data supplied by the caller is NULL,
-                                   or the AuthorityCertificate supplied by the caller was 
-                                   invalid (could not be parsed),                      
-                                   or Platform-specific authorization failed, etc.   
+                                   or the AuthorityCertificate supplied by the caller was
+                                   invalid (could not be parsed),
+                                   or Platform-specific authorization failed, etc.
   @retval EFI_DEVICE_ERROR         An unexpected internal error occurred while attempting to retrieve
                                    the public key algorithm of the manifest's signer's certificate,
-                                   or An unexpected internal error occurred in a cryptographic software module.                                                                                                                                                                  
-**/ 
+                                   or An unexpected internal error occurred in a cryptographic software module.
+**/
 typedef
 EFI_STATUS
 (EFIAPI *EFI_BIS_VERIFY_OBJECT_WITH_CREDENTIAL)(
-  IN  BIS_APPLICATION_HANDLE AppHandle,              
-  IN  EFI_BIS_DATA           *Credentials,           
-  IN  EFI_BIS_DATA           *DataObject,            
-  IN  EFI_BIS_DATA           *SectionName,           
-  IN  EFI_BIS_DATA           *AuthorityCertificate,  
-  OUT BOOLEAN                *IsVerified             
+  IN  BIS_APPLICATION_HANDLE AppHandle,
+  IN  EFI_BIS_DATA           *Credentials,
+  IN  EFI_BIS_DATA           *DataObject,
+  IN  EFI_BIS_DATA           *SectionName,
+  IN  EFI_BIS_DATA           *AuthorityCertificate,
+  OUT BOOLEAN                *IsVerified
   );
 
-/**                                                                 
+/**
   Retrieves a list of digital certificate identifier, digital signature algorithm, hash algorithm, and keylength
-  combinations that the platform supports.                                                                      
+  combinations that the platform supports.
 
   @param  AppHandle                An opaque handle that identifies the caller's instance of initialization
-                                   of the BIS service.                                                                                           
+                                   of the BIS service.
   @param  SignatureInfo            The function writes an allocated EFI_BIS_DATA* containing the array
-                                   of EFI_BIS_SIGNATURE_INFO structures representing the supported    
+                                   of EFI_BIS_SIGNATURE_INFO structures representing the supported
                                    digital certificate identifier, algorithm, and key length combinations.
                                    The caller must eventually free the memory allocated by this function using the function Free().
 
-  @retval EFI_SUCCESS              The function completed successfully.                                                
-  @retval EFI_NO_MAPPING           The AppHandle parameter is not or is no longer a valid                              
-                                   application instance handle associated with the EFI_BIS protocol.                   
-  @retval EFI_OUT_OF_RESOURCES     The function failed due to lack of memory or other resources.                       
+  @retval EFI_SUCCESS              The function completed successfully.
+  @retval EFI_NO_MAPPING           The AppHandle parameter is not or is no longer a valid
+                                   application instance handle associated with the EFI_BIS protocol.
+  @retval EFI_OUT_OF_RESOURCES     The function failed due to lack of memory or other resources.
   @retval EFI_INVALID_PARAMETER    The SignatureInfo parameter supplied by the caller is NULL
                                    or an invalid memory reference.
   @retval EFI_DEVICE_ERROR         An unexpected internal error occurred in a
@@ -424,8 +418,8 @@ EFI_STATUS
 typedef
 EFI_STATUS
 (EFIAPI *EFI_BIS_GET_SIGNATURE_INFO)(
-  IN  BIS_APPLICATION_HANDLE  AppHandle,           
-  OUT EFI_BIS_DATA            **SignatureInfo      
+  IN  BIS_APPLICATION_HANDLE  AppHandle,
+  OUT EFI_BIS_DATA            **SignatureInfo
   );
 
 ///
diff --git a/MdePkg/Include/Protocol/BlockIo.h b/MdePkg/Include/Protocol/BlockIo.h
index 4bc2109db122..460b616fdd8b 100644
--- a/MdePkg/Include/Protocol/BlockIo.h
+++ b/MdePkg/Include/Protocol/BlockIo.h
@@ -4,14 +4,8 @@
   The Block IO protocol is used to abstract block devices like hard drives,
   DVD-ROMs and floppy drives.
 
-  Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -27,12 +21,12 @@ typedef struct _EFI_BLOCK_IO_PROTOCOL  EFI_BLOCK_IO_PROTOCOL;
 
 ///
 /// Protocol GUID name defined in EFI1.1.
-/// 
+///
 #define BLOCK_IO_PROTOCOL       EFI_BLOCK_IO_PROTOCOL_GUID
 
 ///
 /// Protocol defined in EFI1.1.
-/// 
+///
 typedef EFI_BLOCK_IO_PROTOCOL   EFI_BLOCK_IO;
 
 /**
@@ -68,7 +62,7 @@ EFI_STATUS
   @retval EFI_NO_MEDIA          There is no media in the device.
   @retval EFI_MEDIA_CHANGED     The MediaId does not matched the current device.
   @retval EFI_BAD_BUFFER_SIZE   The Buffer was not a multiple of the block size of the device.
-  @retval EFI_INVALID_PARAMETER The read request contains LBAs that are not valid, 
+  @retval EFI_INVALID_PARAMETER The read request contains LBAs that are not valid,
                                 or the buffer is not on proper alignment.
 
 **/
@@ -98,7 +92,7 @@ EFI_STATUS
   @retval EFI_NO_MEDIA          There is no media in the device.
   @retval EFI_MEDIA_CHNAGED     The MediaId does not matched the current device.
   @retval EFI_BAD_BUFFER_SIZE   The Buffer was not a multiple of the block size of the device.
-  @retval EFI_INVALID_PARAMETER The write request contains LBAs that are not valid, 
+  @retval EFI_INVALID_PARAMETER The write request contains LBAs that are not valid,
                                 or the buffer is not on proper alignment.
 
 **/
@@ -135,17 +129,17 @@ typedef struct {
   ///
   /// The curent media Id. If the media changes, this value is changed.
   ///
-  UINT32  MediaId;         
-   
+  UINT32  MediaId;
+
   ///
   /// TRUE if the media is removable; otherwise, FALSE.
-  ///    
+  ///
   BOOLEAN RemovableMedia;
-  
+
   ///
   /// TRUE if there is a media currently present in the device;
   /// othersise, FALSE. THis field shows the media present status
-  /// as of the most recent ReadBlocks() or WriteBlocks() call.  
+  /// as of the most recent ReadBlocks() or WriteBlocks() call.
   ///
   BOOLEAN MediaPresent;
 
@@ -154,45 +148,45 @@ typedef struct {
   /// FALSE. For media with only one partition this would be TRUE.
   ///
   BOOLEAN LogicalPartition;
-  
+
   ///
   /// TRUE if the media is marked read-only otherwise, FALSE.
   /// This field shows the read-only status as of the most recent WriteBlocks () call.
   ///
   BOOLEAN ReadOnly;
-  
+
   ///
   /// TRUE if the WriteBlock () function caches write data.
   ///
-  BOOLEAN WriteCaching; 
-  
+  BOOLEAN WriteCaching;
+
   ///
   /// The intrinsic block size of the device. If the media changes, then
-  /// this field is updated.  
+  /// this field is updated.
   ///
-  UINT32  BlockSize; 
-  
+  UINT32  BlockSize;
+
   ///
   /// Supplies the alignment requirement for any buffer to read or write block(s).
   ///
-  UINT32  IoAlign; 
-  
+  UINT32  IoAlign;
+
   ///
   /// The last logical block address on the device.
-  /// If the media changes, then this field is updated. 
+  /// If the media changes, then this field is updated.
   ///
-  EFI_LBA LastBlock; 
+  EFI_LBA LastBlock;
 
   ///
   /// Only present if EFI_BLOCK_IO_PROTOCOL.Revision is greater than or equal to
-  /// EFI_BLOCK_IO_PROTOCOL_REVISION2. Returns the first LBA is aligned to 
-  /// a physical block boundary. 
+  /// EFI_BLOCK_IO_PROTOCOL_REVISION2. Returns the first LBA is aligned to
+  /// a physical block boundary.
   ///
   EFI_LBA LowestAlignedLba;
 
   ///
   /// Only present if EFI_BLOCK_IO_PROTOCOL.Revision is greater than or equal to
-  /// EFI_BLOCK_IO_PROTOCOL_REVISION2. Returns the number of logical blocks 
+  /// EFI_BLOCK_IO_PROTOCOL_REVISION2. Returns the number of logical blocks
   /// per physical block.
   ///
   UINT32 LogicalBlocksPerPhysicalBlock;
@@ -211,7 +205,7 @@ typedef struct {
 
 ///
 /// Revision defined in EFI1.1.
-/// 
+///
 #define EFI_BLOCK_IO_INTERFACE_REVISION   EFI_BLOCK_IO_PROTOCOL_REVISION
 
 ///
diff --git a/MdePkg/Include/Protocol/BlockIo2.h b/MdePkg/Include/Protocol/BlockIo2.h
index 0e4bb289cffd..75ea914ffcdf 100644
--- a/MdePkg/Include/Protocol/BlockIo2.h
+++ b/MdePkg/Include/Protocol/BlockIo2.h
@@ -5,14 +5,8 @@
   enables the ability to read and write data at a block level in a non-blocking
   manner.
 
-  Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -69,7 +63,7 @@ EFI_STATUS
 
 /**
   Read BufferSize bytes from Lba into Buffer.
-  
+
   This function reads the requested number of blocks from the device. All the
   blocks are read, or an error is returned.
   If EFI_DEVICE_ERROR, EFI_NO_MEDIA,_or EFI_MEDIA_CHANGED is returned and
@@ -77,13 +71,13 @@ EFI_STATUS
   not be signaled.
 
   @param[in]       This       Indicates a pointer to the calling context.
-  @param[in]       MediaId    Id of the media, changes every time the media is 
+  @param[in]       MediaId    Id of the media, changes every time the media is
                               replaced.
   @param[in]       Lba        The starting Logical Block Address to read from.
-  @param[in, out]  Token	    A pointer to the token associated with the transaction.
-  @param[in]       BufferSize Size of Buffer, must be a multiple of device block size.  
-  @param[out]      Buffer     A pointer to the destination buffer for the data. The 
-                              caller is responsible for either having implicit or 
+  @param[in, out]  Token      A pointer to the token associated with the transaction.
+  @param[in]       BufferSize Size of Buffer, must be a multiple of device block size.
+  @param[out]      Buffer     A pointer to the destination buffer for the data. The
+                              caller is responsible for either having implicit or
                               explicit ownership of the buffer.
 
   @retval EFI_SUCCESS           The read request was queued if Token->Event is
@@ -95,7 +89,7 @@ EFI_STATUS
   @retval EFI_MEDIA_CHANGED     The MediaId is not for the current media.
   @retval EFI_BAD_BUFFER_SIZE   The BufferSize parameter is not a multiple of the
                                 intrinsic block size of the device.
-  @retval EFI_INVALID_PARAMETER The read request contains LBAs that are not valid, 
+  @retval EFI_INVALID_PARAMETER The read request contains LBAs that are not valid,
                                 or the buffer is not on proper alignment.
   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack
                                 of resources.
@@ -136,7 +130,7 @@ EFI_STATUS
   @retval EFI_MEDIA_CHNAGED     The MediaId does not matched the current device.
   @retval EFI_DEVICE_ERROR      The device reported an error while performing the write.
   @retval EFI_BAD_BUFFER_SIZE   The Buffer was not a multiple of the block size of the device.
-  @retval EFI_INVALID_PARAMETER The write request contains LBAs that are not valid, 
+  @retval EFI_INVALID_PARAMETER The write request contains LBAs that are not valid,
                                 or the buffer is not on proper alignment.
   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack
                                 of resources.
@@ -155,10 +149,10 @@ EFI_STATUS
 
 /**
   Flush the Block Device.
- 
+
   If EFI_DEVICE_ERROR, EFI_NO_MEDIA,_EFI_WRITE_PROTECTED or EFI_MEDIA_CHANGED
   is returned and non-blocking I/O is being used, the Event associated with
-  this request will not be signaled.  
+  this request will not be signaled.
 
   @param[in]      This     Indicates a pointer to the calling context.
   @param[in,out]  Token    A pointer to the token associated with the transaction
@@ -189,9 +183,9 @@ EFI_STATUS
 ///
 struct _EFI_BLOCK_IO2_PROTOCOL {
   ///
-  /// A pointer to the EFI_BLOCK_IO_MEDIA data for this device. 
+  /// A pointer to the EFI_BLOCK_IO_MEDIA data for this device.
   /// Type EFI_BLOCK_IO_MEDIA is defined in BlockIo.h.
-  ///  
+  ///
   EFI_BLOCK_IO_MEDIA      *Media;
 
   EFI_BLOCK_RESET_EX      Reset;
diff --git a/MdePkg/Include/Protocol/BlockIoCrypto.h b/MdePkg/Include/Protocol/BlockIoCrypto.h
index ffac54b3b157..178d31830ff9 100644
--- a/MdePkg/Include/Protocol/BlockIoCrypto.h
+++ b/MdePkg/Include/Protocol/BlockIoCrypto.h
@@ -2,14 +2,11 @@
   The UEFI Inline Cryptographic Interface protocol provides services to abstract
   access to inline cryptographic capabilities.
 
-  Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2015-2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  This Protocol was introduced in UEFI Specification 2.5.
 
 **/
 
diff --git a/MdePkg/Include/Protocol/BluetoothAttribute.h b/MdePkg/Include/Protocol/BluetoothAttribute.h
new file mode 100644
index 000000000000..eb39ea27f096
--- /dev/null
+++ b/MdePkg/Include/Protocol/BluetoothAttribute.h
@@ -0,0 +1,277 @@
+/** @file
+  EFI Bluetooth Attribute Protocol as defined in UEFI 2.7.
+  This protocol provides service for Bluetooth ATT (Attribute Protocol) and GATT (Generic
+  Attribute Profile) based protocol interfaces.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  This Protocol is introduced in UEFI Specification 2.7
+
+**/
+
+#ifndef __EFI_BLUETOOTH_ATTRIBUTE_H__
+#define __EFI_BLUETOOTH_ATTRIBUTE_H__
+
+#define EFI_BLUETOOTH_ATTRIBUTE_SERVICE_BINDING_PROTOCOL_GUID \
+  { \
+    0x5639867a, 0x8c8e, 0x408d, { 0xac, 0x2f, 0x4b, 0x61, 0xbd, 0xc0, 0xbb, 0xbb } \
+  }
+
+#define EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL_GUID \
+  { \
+    0x898890e9, 0x84b2, 0x4f3a, { 0x8c, 0x58, 0xd8, 0x57, 0x78, 0x13, 0xe0, 0xac } \
+  }
+
+typedef struct _EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL;
+
+#pragma pack(1)
+
+//
+// Bluetooth UUID
+//
+typedef struct {
+  UINT8                 Length;
+  union {
+    UINT16              Uuid16;
+    UINT32              Uuid32;
+    UINT8               Uuid128[16];
+  } Data;
+} EFI_BLUETOOTH_UUID;
+
+
+#define UUID_16BIT_TYPE_LEN   2
+#define UUID_32BIT_TYPE_LEN   4
+#define UUID_128BIT_TYPE_LEN  16
+
+#define BLUETOOTH_IS_ATTRIBUTE_OF_TYPE(a,t) ((a)->Type.Length == UUID_16BIT_TYPE_LEN && (a)->Type.Data.Uuid16 == (t))
+
+//
+// Bluetooth Attribute Permission
+//
+typedef union {
+  struct {
+    UINT16  Readable            : 1;
+    UINT16  ReadEncryption      : 1;
+    UINT16  ReadAuthentication  : 1;
+    UINT16  ReadAuthorization   : 1;
+    UINT16  ReadKeySize         : 5;
+    UINT16  Reserved1           : 7;
+    UINT16  Writeable           : 1;
+    UINT16  WriteEncryption     : 1;
+    UINT16  WriteAuthentication : 1;
+    UINT16  WriteAuthorization  : 1;
+    UINT16  WriteKeySize        : 5;
+    UINT16  Reserved2           : 7;
+  } Permission;
+  UINT32  Data32;
+} EFI_BLUETOOTH_ATTRIBUTE_PERMISSION;
+
+typedef struct {
+  EFI_BLUETOOTH_UUID                 Type;
+  UINT16                             Length;
+  UINT16                             AttributeHandle;
+  EFI_BLUETOOTH_ATTRIBUTE_PERMISSION AttributePermission;
+} EFI_BLUETOOTH_ATTRIBUTE_HEADER;
+
+typedef struct {
+  EFI_BLUETOOTH_ATTRIBUTE_HEADER Header;
+  UINT16                         EndGroupHandle;
+  EFI_BLUETOOTH_UUID             ServiceUuid;
+} EFI_BLUETOOTH_GATT_PRIMARY_SERVICE_INFO;
+
+typedef struct {
+  EFI_BLUETOOTH_ATTRIBUTE_HEADER Header;
+  UINT16                         StartGroupHandle;
+  UINT16                         EndGroupHandle;
+  EFI_BLUETOOTH_UUID             ServiceUuid;
+} EFI_BLUETOOTH_GATT_INCLUDE_SERVICE_INFO;
+
+typedef struct {
+  EFI_BLUETOOTH_ATTRIBUTE_HEADER Header;
+  UINT8                          CharacteristicProperties;
+  UINT16                         CharacteristicValueHandle;
+  EFI_BLUETOOTH_UUID             CharacteristicUuid;
+} EFI_BLUETOOTH_GATT_CHARACTERISTIC_INFO;
+
+typedef struct {
+  EFI_BLUETOOTH_ATTRIBUTE_HEADER Header;
+  EFI_BLUETOOTH_UUID             CharacteristicDescriptorUuid;
+} EFI_BLUETOOTH_GATT_CHARACTERISTIC_DESCRIPTOR_INFO;
+
+#pragma pack()
+
+typedef struct {
+  UINT16                    AttributeHandle;
+} EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_PARAMETER_NOTIFICATION;
+
+typedef struct {
+  UINT16                    AttributeHandle;
+} EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_PARAMETER_INDICATION;
+
+typedef struct {
+  UINT32                                                     Version;
+  UINT8                                                      AttributeOpCode;
+  union {
+    EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_PARAMETER_NOTIFICATION  Notification;
+    EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_PARAMETER_INDICATION    Indication;
+  } Parameter;
+} EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_PARAMETER;
+
+typedef struct {
+  UINT32               Version;
+  BLUETOOTH_LE_ADDRESS BD_ADDR;
+  BLUETOOTH_LE_ADDRESS DirectAddress;
+  UINT8                RSSI;
+  UINTN                AdvertisementDataSize;
+  VOID                 *AdvertisementData;
+} EFI_BLUETOOTH_LE_DEVICE_INFO;
+
+/**
+  The callback function to send request.
+
+  @param[in]  This                Pointer to the EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL instance.
+  @param[in]  Data                Data received. The first byte is the attribute opcode, followed by opcode specific
+                                  fields. See Bluetooth specification, Vol 3, Part F, Attribute Protocol. It might be a
+                                  normal RESPONSE message, or ERROR RESPONSE messag
+  @param[in]  DataLength          The length of Data in bytes.
+  @param[in]  Context             The context passed from the callback registration request.
+
+  @retval EFI_SUCCESS   The callback function complete successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_FUNCTION) (
+  IN EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL *This,
+  IN VOID                             *Data,
+  IN UINTN                            DataLength,
+  IN VOID                             *Context
+  );
+
+/**
+  Send a "REQUEST" or "COMMAND" message to remote server and receive a "RESPONSE" message
+  for "REQUEST" from remote server according to Bluetooth attribute protocol data unit(PDU).
+
+  @param[in]  This              Pointer to the EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL instance.
+  @param[in]  Data              Data of a REQUEST or COMMAND message. The first byte is the attribute PDU
+                                related opcode, followed by opcode specific fields. See Bluetooth specification,
+                                Vol 3, Part F, Attribute Protocol.
+  @param[in]  DataLength        The length of Data in bytes.
+  @param[in]  Callback          Callback function to notify the RESPONSE is received to the caller, with the
+                                response buffer. Caller must check the response buffer content to know if the
+                                request action is success or fail. It may be NULL if the data is a COMMAND.
+  @param[in]  Context           Data passed into Callback function. It is optional parameter and may be NULL.
+
+  @retval EFI_SUCCESS           The request is sent successfully.
+  @retval EFI_INVALID_PARAMETER One or more parameters are invalid due to following conditions:
+                                - The Buffer is NULL.
+                                - The BufferLength is 0.
+                                - The opcode in Buffer is not a valid OPCODE according to Bluetooth specification.
+                                - The Callback is NULL.
+  @retval EFI_DEVICE_ERROR      Sending the request failed due to the host controller or the device error.
+  @retval EFI_NOT_READY         A GATT operation is already underway for this device.
+  @retval EFI_UNSUPPORTED       The attribute does not support the corresponding operation.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_ATTRIBUTE_SEND_REQUEST) (
+  IN EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL            *This,
+  IN VOID                                        *Data,
+  IN UINTN                                       DataLength,
+  IN EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_FUNCTION   Callback,
+  IN VOID                                        *Context
+  );
+
+/**
+  Register or unregister a server initiated message, such as NOTIFICATION or INDICATION, on a
+  characteristic value on remote server.
+
+  @param[in]  This              Pointer to the EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL instance.
+  @param[in]  CallbackParameter The parameter of the callback.
+  @param[in]  Callback          Callback function for server initiated attribute protocol. NULL callback
+                                function means unregister the server initiated callback.
+  @param[in]  Context           Data passed into Callback function. It is optional parameter and may be NULL.
+
+  @retval EFI_SUCCESS           The callback function is registered or unregistered successfully
+  @retval EFI_INVALID_PARAMETER The attribute opcode is not server initiated message opcode. See
+                                Bluetooth specification, Vol 3, Part F, Attribute Protocol.
+  @retval EFI_ALREADY_STARTED   A callback function is already registered on the same attribute
+                                opcode and attribute handle, when the Callback is not NULL.
+  @retval EFI_NOT_STARTED       A callback function is not registered on the same attribute opcode
+                                and attribute handle, when the Callback is NULL.
+  @retval EFI_NOT_READY         A GATT operation is already underway for this device.
+  @retval EFI_UNSUPPORTED       The attribute does not support notification.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_ATTRIBUTE_REGISTER_FOR_SERVER_NOTIFICATION)(
+  IN  EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL           *This,
+  IN  EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_PARAMETER *CallbackParameter,
+  IN  EFI_BLUETOOTH_ATTRIBUTE_CALLBACK_FUNCTION  Callback,
+  IN  VOID                                       *Context
+  );
+
+/**
+  Get Bluetooth discovered service information.
+
+  @param[in]  This              Pointer to the EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL instance.
+  @param[out] ServiceInfoSize   A pointer to the size, in bytes, of the ServiceInfo buffer.
+  @param[out] ServiceInfo       A pointer to a callee allocated buffer that returns Bluetooth
+                                discovered service information. Callee allocates this buffer by
+                                using EFI Boot Service AllocatePool().
+
+  @retval EFI_SUCCESS           The Bluetooth discovered service information is returned successfully.
+  @retval EFI_DEVICE_ERROR      A hardware error occurred trying to retrieve the Bluetooth discovered
+                                service information.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_ATTRIBUTE_GET_SERVICE_INFO)(
+  IN EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL      *This,
+  OUT UINTN                                *ServiceInfoSize,
+  OUT VOID                                 **ServiceInfo
+  );
+
+/**
+  Get Bluetooth device information.
+
+  @param[in]  This              Pointer to the EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL instance.
+  @param[out] DeviceInfoSize    A pointer to the size, in bytes, of the DeviceInfo buffer.
+  @param[out] DeviceInfo        A pointer to a callee allocated buffer that returns Bluetooth
+                                device information. Callee allocates this buffer by using EFI Boot
+                                Service AllocatePool(). If this device is Bluetooth classic
+                                device, EFI_BLUETOOTH_DEVICE_INFO should be used. If
+                                this device is Bluetooth LE device, EFI_BLUETOOTH_LE_DEVICE_INFO
+                                should be used.
+
+  @retval EFI_SUCCESS           The Bluetooth device information is returned successfully.
+  @retval EFI_DEVICE_ERROR      A hardware error occurred trying to retrieve the Bluetooth device
+                                information
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_ATTRIBUTE_GET_DEVICE_INFO)(
+  IN  EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL  *This,
+  OUT UINTN                             *DeviceInfoSize,
+  OUT VOID                              **DeviceInfo
+  );
+
+struct _EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL {
+  EFI_BLUETOOTH_ATTRIBUTE_SEND_REQUEST                     SendRequest;
+  EFI_BLUETOOTH_ATTRIBUTE_REGISTER_FOR_SERVER_NOTIFICATION RegisterForServerNotification;
+  EFI_BLUETOOTH_ATTRIBUTE_GET_SERVICE_INFO                 GetServiceInfo;
+  EFI_BLUETOOTH_ATTRIBUTE_GET_DEVICE_INFO                  GetDeviceInfo;
+};
+
+
+extern EFI_GUID gEfiBluetoothAttributeProtocolGuid;
+extern EFI_GUID gEfiBluetoothAttributeServiceBindingProtocolGuid;
+
+#endif
+
diff --git a/MdePkg/Include/Protocol/BluetoothConfig.h b/MdePkg/Include/Protocol/BluetoothConfig.h
index cc72b1e21a6a..8a6013173448 100644
--- a/MdePkg/Include/Protocol/BluetoothConfig.h
+++ b/MdePkg/Include/Protocol/BluetoothConfig.h
@@ -1,18 +1,12 @@
 /** @file
-  EFI Bluetooth Configuration Protocol as defined in UEFI 2.5.
+  EFI Bluetooth Configuration Protocol as defined in UEFI 2.7.
   This protocol abstracts user interface configuration for Bluetooth device.
 
-  Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials are licensed and made available under 
-  the terms and conditions of the BSD License that accompanies this distribution.  
-  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php.                                          
-    
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
-  @par Revision Reference:          
-  This Protocol is introduced in UEFI Specification 2.5
+  @par Revision Reference:
+  This Protocol is introduced in UEFI Specification 2.7
 
 **/
 
@@ -25,7 +19,7 @@
   { \
     0x62960cf3, 0x40ff, 0x4263, { 0xa7, 0x7c, 0xdf, 0xde, 0xbd, 0x19, 0x1b, 0x4b } \
   }
-  
+
 typedef struct _EFI_BLUETOOTH_CONFIG_PROTOCOL EFI_BLUETOOTH_CONFIG_PROTOCOL;
 
 typedef UINT32      EFI_BLUETOOTH_CONFIG_REMOTE_DEVICE_STATE_TYPE;
@@ -41,7 +35,7 @@ typedef struct {
   ///
   BLUETOOTH_ADDRESS         BDAddr;
   ///
-  /// State of the remote deive 
+  /// State of the remote deive
   ///
   UINT8                     RemoteDeviceState;
   ///
@@ -69,7 +63,7 @@ typedef enum {
   ///
   /// Remote Bluetooth device state. Data structure is EFI_BLUETOOTH_CONFIG_REMOTE_DEVICE_STATE_TYPE.
   ///
-  EfiBluetoothConfigDataTypeRemoteDeviceState,
+  EfiBluetoothConfigDataTypeRemoteDeviceState, /* Relevant for LE*/
   ///
   /// Local/Remote Bluetooth device SDP information. Data structure is UINT8[].
   ///
@@ -77,11 +71,11 @@ typedef enum {
   ///
   /// Local Bluetooth device address. Data structure is BLUETOOTH_ADDRESS.
   ///
-  EfiBluetoothConfigDataTypeBDADDR,
+  EfiBluetoothConfigDataTypeBDADDR, /* Relevant for LE*/
   ///
   /// Local Bluetooth discoverable state. Data structure is UINT8. (Page scan and/or Inquiry scan)
   ///
-  EfiBluetoothConfigDataTypeDiscoverable,
+  EfiBluetoothConfigDataTypeDiscoverable, /* Relevant for LE*/
   ///
   /// Local Bluetooth controller stored paired device list. Data structure is BLUETOOTH_ADDRESS[].
   ///
@@ -90,6 +84,21 @@ typedef enum {
   /// Local available device list. Data structure is BLUETOOTH_ADDRESS[].
   ///
   EfiBluetoothConfigDataTypeAvailableDeviceList,
+  EfiBluetoothConfigDataTypeRandomAddress, /* Relevant for LE*/
+  EfiBluetoothConfigDataTypeRSSI, /* Relevant for LE*/
+  ///
+  /// Advertisement report. Data structure is UNIT8[].
+  ///
+  EfiBluetoothConfigDataTypeAdvertisementData, /* Relevant for LE*/
+  EfiBluetoothConfigDataTypeIoCapability, /* Relevant for LE*/
+  EfiBluetoothConfigDataTypeOOBDataFlag, /* Relevant for LE*/
+  ///
+  /// KeyType of Authentication Requirements flag of local
+  /// device as UINT8, indicating requested security properties.
+  /// See Bluetooth specification 3.H.3.5.1. BIT0: MITM, BIT1:SC.
+  ///
+  EfiBluetoothConfigDataTypeKeyType, /* Relevant for LE*/
+  EfiBluetoothConfigDataTypeEncKeySize, /* Relevant for LE*/
   EfiBluetoothConfigDataTypeMax,
 } EFI_BLUETOOTH_CONFIG_DATA_TYPE;
 
@@ -98,12 +107,12 @@ typedef enum {
 ///
 typedef enum {
   ///
-  /// For SSP - passkey entry. Input buffer is Passkey (4 bytes). No output buffer. 
+  /// For SSP - passkey entry. Input buffer is Passkey (4 bytes). No output buffer.
   /// See Bluetooth HCI command for detail.
   ///
   EfiBluetoothCallbackTypeUserPasskeyNotification,
   ///
-  /// For SSP - just work and numeric comparison. Input buffer is numeric value (4 bytes). 
+  /// For SSP - just work and numeric comparison. Input buffer is numeric value (4 bytes).
   /// Output buffer is BOOLEAN (1 byte). See Bluetooth HCI command for detail.
   ///
   EfiBluetoothCallbackTypeUserConfirmationRequest,
@@ -112,7 +121,7 @@ typedef enum {
   ///
   EfiBluetoothCallbackTypeOOBDataRequest,
   ///
-  /// For legacy paring. No input buffer. Output buffer is PIN code( <= 16 bytes). 
+  /// For legacy paring. No input buffer. Output buffer is PIN code( <= 16 bytes).
   /// See Bluetooth HCI command for detail.
   ///
   EfiBluetoothCallbackTypePinCodeRequest,
@@ -124,44 +133,44 @@ typedef enum {
 ///
 typedef enum {
   ///
-  /// This callback is called when Bluetooth receive Disconnection_Complete event. Input buffer is Event 
+  /// This callback is called when Bluetooth receive Disconnection_Complete event. Input buffer is Event
   /// Parameters of Disconnection_Complete Event defined in Bluetooth specification.
   ///
   EfiBluetoothConnCallbackTypeDisconnected,
   ///
-  /// This callback is called when Bluetooth receive Connection_Complete event. Input buffer is Event 
+  /// This callback is called when Bluetooth receive Connection_Complete event. Input buffer is Event
   /// Parameters of Connection_Complete Event defined in Bluetooth specification.
   ///
   EfiBluetoothConnCallbackTypeConnected,
   ///
-  /// This callback is called when Bluetooth receive Authentication_Complete event. Input buffer is Event 
+  /// This callback is called when Bluetooth receive Authentication_Complete event. Input buffer is Event
   /// Parameters of Authentication_Complete Event defined in Bluetooth specification.
   ///
   EfiBluetoothConnCallbackTypeAuthenticated,
   ///
-  /// This callback is called when Bluetooth receive Encryption_Change event. Input buffer is Event 
+  /// This callback is called when Bluetooth receive Encryption_Change event. Input buffer is Event
   /// Parameters of Encryption_Change Event defined in Bluetooth specification.
   ///
   EfiBluetoothConnCallbackTypeEncrypted
 } EFI_BLUETOOTH_CONNECT_COMPLETE_CALLBACK_TYPE;
 
-  
+
 /**
   Initialize Bluetooth host controller and local device.
 
   @param  This          Pointer to the EFI_BLUETOOTH_CONFIG_PROTOCOL instance.
 
   @retval EFI_SUCCESS           The Bluetooth host controller and local device is initialized successfully.
-  @retval EFI_DEVICE_ERROR      A hardware error occurred trying to initialize the Bluetooth host controller 
+  @retval EFI_DEVICE_ERROR      A hardware error occurred trying to initialize the Bluetooth host controller
                                 and local device.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_BLUETOOTH_CONFIG_INIT)(
   IN EFI_BLUETOOTH_CONFIG_PROTOCOL  *This
   );
-  
+
 /**
   Callback function, it is called if a Bluetooth device is found during scan process.
 
@@ -179,16 +188,16 @@ EFI_STATUS
   IN VOID                                     *Context,
   IN EFI_BLUETOOTH_SCAN_CALLBACK_INFORMATION  *CallbackInfo
   );
-  
+
 /**
   Scan Bluetooth device.
 
   @param  This          Pointer to the EFI_BLUETOOTH_CONFIG_PROTOCOL instance.
-  @param  ReScan        If TRUE, a new scan request is submitted no matter there is scan result before. 
-                        If FALSE and there is scan result, the previous scan result is returned and no scan request 
+  @param  ReScan        If TRUE, a new scan request is submitted no matter there is scan result before.
+                        If FALSE and there is scan result, the previous scan result is returned and no scan request
                         is submitted.
   @param  ScanType      Bluetooth scan type, Inquiry and/or Page. See Bluetooth specification for detail.
-  @param  Callback      The callback function. This function is called if a Bluetooth device is found during scan 
+  @param  Callback      The callback function. This function is called if a Bluetooth device is found during scan
                         process.
   @param  Context       Data passed into Callback function. This is optional parameter and may be NULL.
 
@@ -196,7 +205,7 @@ EFI_STATUS
   @retval EFI_DEVICE_ERROR      A hardware error occurred trying to scan the Bluetooth device.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_BLUETOOTH_CONFIG_SCAN)(
   IN EFI_BLUETOOTH_CONFIG_PROTOCOL                  *This,
@@ -205,7 +214,7 @@ EFI_STATUS
   IN EFI_BLUETOOTH_CONFIG_SCAN_CALLBACK_FUNCTION    Callback,
   IN VOID                                           *Context
   );
-  
+
 /**
   Connect a Bluetooth device.
 
@@ -218,7 +227,7 @@ EFI_STATUS
   @retval EFI_DEVICE_ERROR      A hardware error occurred trying to connect the Bluetooth device.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_BLUETOOTH_CONFIG_CONNECT)(
   IN EFI_BLUETOOTH_CONFIG_PROTOCOL                  *This,
@@ -238,14 +247,14 @@ EFI_STATUS
   @retval EFI_DEVICE_ERROR      A hardware error occurred trying to disconnect the Bluetooth device.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_BLUETOOTH_CONFIG_DISCONNECT)(
   IN EFI_BLUETOOTH_CONFIG_PROTOCOL                  *This,
   IN BLUETOOTH_ADDRESS                              *BD_ADDR,
   IN UINT8                                          Reason
   );
-  
+
 /**
   Get Bluetooth configuration data.
 
@@ -258,14 +267,14 @@ EFI_STATUS
   @retval EFI_SUCCESS           The Bluetooth configuration data is returned successfully.
   @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
                                 - DataSize is NULL.
-                                - *DataSize is 0.
-                                - Data is NULL.
+                                - *DataSize is not 0 and Data is NULL.
   @retval EFI_UNSUPPORTED       The DataType is unsupported.
   @retval EFI_NOT_FOUND         The DataType is not found.
   @retval EFI_BUFFER_TOO_SMALL  The buffer is too small to hold the buffer.
+                                *DataSize has been updated with the size needed to complete the request.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_BLUETOOTH_CONFIG_GET_DATA)(
   IN EFI_BLUETOOTH_CONFIG_PROTOCOL                  *This,
@@ -273,7 +282,7 @@ EFI_STATUS
   IN OUT UINTN                                      *DataSize,
   IN OUT VOID                                       *Data
   );
-  
+
 /**
   Set Bluetooth configuration data.
 
@@ -290,7 +299,7 @@ EFI_STATUS
   @retval EFI_BUFFER_TOO_SMALL  Cannot set configuration data.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_BLUETOOTH_CONFIG_SET_DATA)(
   IN EFI_BLUETOOTH_CONFIG_PROTOCOL                  *This,
@@ -298,7 +307,7 @@ EFI_STATUS
   IN UINTN                                          DataSize,
   IN VOID                                           *Data
   );
-  
+
 /**
   Get remove Bluetooth device configuration data.
 
@@ -312,23 +321,23 @@ EFI_STATUS
   @retval EFI_SUCCESS           The remote Bluetooth device configuration data is returned successfully.
   @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
                                 - DataSize is NULL.
-                                - *DataSize is 0.
-                                - Data is NULL.
+                                - *DataSize is not 0 and Data is NULL.
   @retval EFI_UNSUPPORTED       The DataType is unsupported.
   @retval EFI_NOT_FOUND         The DataType is not found.
   @retval EFI_BUFFER_TOO_SMALL  The buffer is too small to hold the buffer.
+                                *DataSize has been updated with the size needed to complete the request.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_BLUETOOTH_CONFIG_GET_REMOTE_DATA)(
   IN EFI_BLUETOOTH_CONFIG_PROTOCOL                  *This,
   IN EFI_BLUETOOTH_CONFIG_DATA_TYPE                 DataType,
-  IN BLUETOOTH_ADDRESS                              BDAddr,
+  IN BLUETOOTH_ADDRESS                              *BDAddr,
   IN OUT UINTN                                      *DataSize,
   IN OUT VOID                                       *Data
   );
-  
+
 /**
   The callback function for PIN code.
 
@@ -337,14 +346,14 @@ EFI_STATUS
   @param  CallbackType        Callback type in EFI_BLUETOOTH_PIN_CALLBACK_TYPE.
   @param  InputBuffer         A pointer to the buffer of data that is input from callback caller.
   @param  InputBufferSize     Indicates the size, in bytes, of the data buffer specified by InputBuffer.
-  @param  OutputBuffer        A pointer to the buffer of data that will be output from callback callee. 
+  @param  OutputBuffer        A pointer to the buffer of data that will be output from callback callee.
                               Callee allocates this buffer by using EFI Boot Service AllocatePool().
   @param  OutputBufferSize    Indicates the size, in bytes, of the data buffer specified by OutputBuffer.
 
   @retval EFI_SUCCESS   The callback function complete successfully.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_BLUETOOTH_CONFIG_REGISTER_PIN_CALLBACK_FUNCTION)(
   IN EFI_BLUETOOTH_CONFIG_PROTOCOL                        *This,
@@ -355,7 +364,7 @@ EFI_STATUS
   OUT VOID                                                **OutputBuffer,
   OUT UINTN                                               *OutputBufferSize
   );
-  
+
 /**
   Register PIN callback function.
 
@@ -366,7 +375,7 @@ EFI_STATUS
   @retval EFI_SUCCESS   The PIN callback function is registered successfully.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_BLUETOOTH_CONFIG_REGISTER_PIN_CALLBACK)(
   IN EFI_BLUETOOTH_CONFIG_PROTOCOL                        *This,
@@ -385,7 +394,7 @@ EFI_STATUS
   @retval EFI_SUCCESS   The callback function complete successfully.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_BLUETOOTH_CONFIG_REGISTER_GET_LINK_KEY_CALLBACK_FUNCTION)(
   IN EFI_BLUETOOTH_CONFIG_PROTOCOL        *This,
@@ -393,7 +402,7 @@ EFI_STATUS
   IN BLUETOOTH_ADDRESS                    *BDAddr,
   OUT UINT8                               LinkKey[BLUETOOTH_HCI_LINK_KEY_SIZE]
   );
-  
+
 /**
   Register get link key callback function.
 
@@ -404,14 +413,14 @@ EFI_STATUS
   @retval EFI_SUCCESS   The link key callback function is registered successfully.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_BLUETOOTH_CONFIG_REGISTER_GET_LINK_KEY_CALLBACK)(
   IN EFI_BLUETOOTH_CONFIG_PROTOCOL                                  *This,
   IN EFI_BLUETOOTH_CONFIG_REGISTER_GET_LINK_KEY_CALLBACK_FUNCTION   Callback,
   IN VOID                                                           *Context
   );
-  
+
 /**
   The callback function to set link key.
 
@@ -423,7 +432,7 @@ EFI_STATUS
   @retval EFI_SUCCESS   The callback function complete successfully.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_BLUETOOTH_CONFIG_REGISTER_SET_LINK_KEY_CALLBACK_FUNCTION)(
   IN EFI_BLUETOOTH_CONFIG_PROTOCOL        *This,
@@ -431,7 +440,7 @@ EFI_STATUS
   IN BLUETOOTH_ADDRESS                    *BDAddr,
   IN UINT8                                LinkKey[BLUETOOTH_HCI_LINK_KEY_SIZE]
   );
-  
+
 /**
   Register set link key callback function.
 
@@ -442,14 +451,14 @@ EFI_STATUS
   @retval EFI_SUCCESS   The link key callback function is registered successfully.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_BLUETOOTH_CONFIG_REGISTER_SET_LINK_KEY_CALLBACK)(
   IN EFI_BLUETOOTH_CONFIG_PROTOCOL                                  *This,
   IN EFI_BLUETOOTH_CONFIG_REGISTER_SET_LINK_KEY_CALLBACK_FUNCTION   Callback,
   IN VOID                                                           *Context
   );
-  
+
 /**
   The callback function. It is called after connect completed.
 
@@ -463,7 +472,7 @@ EFI_STATUS
   @retval EFI_SUCCESS   The callback function complete successfully.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_BLUETOOTH_CONFIG_REGISTER_CONNECT_COMPLETE_CALLBACK_FUNCTION)(
   IN EFI_BLUETOOTH_CONFIG_PROTOCOL                  *This,
@@ -473,7 +482,7 @@ EFI_STATUS
   IN VOID                                           *InputBuffer,
   IN UINTN                                          InputBufferSize
   );
-  
+
 /**
   Register link connect complete callback function.
 
@@ -484,14 +493,14 @@ EFI_STATUS
   @retval EFI_SUCCESS   The link connect complete callback function is registered successfully.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_BLUETOOTH_CONFIG_REGISTER_CONNECT_COMPLETE_CALLBACK)(
   IN EFI_BLUETOOTH_CONFIG_PROTOCOL                                      *This,
   IN EFI_BLUETOOTH_CONFIG_REGISTER_CONNECT_COMPLETE_CALLBACK_FUNCTION   Callback,
   IN VOID                                                               *Context
   );
-  
+
 ///
 /// This protocol abstracts user interface configuration for Bluetooth device.
 ///
diff --git a/MdePkg/Include/Protocol/BluetoothHc.h b/MdePkg/Include/Protocol/BluetoothHc.h
index eb55079bb81c..9bcb777e7822 100644
--- a/MdePkg/Include/Protocol/BluetoothHc.h
+++ b/MdePkg/Include/Protocol/BluetoothHc.h
@@ -2,16 +2,10 @@
   EFI Bluetooth Host Controller Protocol as defined in UEFI 2.5.
   This protocol abstracts the Bluetooth host controller layer message transmit and receive.
 
-  Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials are licensed and made available under 
-  the terms and conditions of the BSD License that accompanies this distribution.  
-  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php.                                          
-    
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-  @par Revision Reference:          
+  Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
   This Protocol is introduced in UEFI Specification 2.5
 
 **/
@@ -23,306 +17,402 @@
   { \
     0xb3930571, 0xbeba, 0x4fc5, { 0x92, 0x3, 0x94, 0x27, 0x24, 0x2e, 0x6a, 0x43 } \
   }
-  
+
 typedef struct _EFI_BLUETOOTH_HC_PROTOCOL EFI_BLUETOOTH_HC_PROTOCOL;
 
 /**
   Send HCI command packet.
 
-  @param  This          Pointer to the EFI_BLUETOOTH_HC_PROTOCOL instance.
-  @param  BufferSize    On input, indicates the size, in bytes, of the data buffer specified by Buffer. 
-                        On output, indicates the amount of data actually transferred.
-  @param  Buffer        A pointer to the buffer of data that will be transmitted to Bluetooth host 
-                        controller.
-  @param  Timeout       Indicating the transfer should be completed within this time frame. The units are 
-                        in milliseconds. If Timeout is 0, then the caller must wait for the function to 
-                        be completed until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.
-
-  @retval EFI_SUCCESS           The HCI command packet is sent successfully.
-  @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
-                                - BufferSize is NULL.
-                                - *BufferSize is 0.
-                                - Buffer is NULL.
-  @retval EFI_TIMEOUT           Sending HCI command packet fail due to timeout.
-  @retval EFI_DEVICE_ERROR      Sending HCI command packet fail due to host controller or device error.
+  The SendCommand() function sends HCI command packet. Buffer holds the whole HCI
+  command packet, including OpCode, OCF, OGF, parameter length, and parameters. When
+  this function is returned, it just means the HCI command packet is sent, it does not mean
+  the command is success or complete. Caller might need to wait a command status event
+  to know the command status, or wait a command complete event to know if the
+  command is completed.
+
+  @param[in]      This              Pointer to the EFI_BLUETOOTH_HC_PROTOCOL instance.
+  @param[in,out]  BufferSize        On input, indicates the size, in bytes, of the data buffer
+                                    specified by Buffer. On output, indicates the amount of
+                                    data actually transferred.
+  @param[in]      Buffer            A pointer to the buffer of data that will be transmitted to
+                                    Bluetooth host controller.
+  @param[in]      Timeout           Indicating the transfer should be completed within this
+                                    time frame. The units are in milliseconds. If Timeout is 0,
+                                    then the caller must wait for the function to be completed
+                                    until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.
+
+  @retval EFI_SUCCESS               The HCI command packet is sent successfully.
+  @retval EFI_INVALID_PARAMETER     One or more of the following conditions is TRUE:
+                                      BufferSize is NULL.
+                                      *BufferSize is 0.
+                                      Buffer is NULL.
+  @retval EFI_TIMEOUT               Sending HCI command packet fail due to timeout.
+  @retval EFI_DEVICE_ERROR          Sending HCI command packet fail due to host controller or device
+                                    error.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_BLUETOOTH_HC_SEND_COMMAND)(
-  IN EFI_BLUETOOTH_HC_PROTOCOL  *This,
-  IN OUT UINTN                  *BufferSize,
-  IN VOID                       *Buffer,
-  IN UINTN                      Timeout
+  IN EFI_BLUETOOTH_HC_PROTOCOL      *This,
+  IN OUT UINTN                      *BufferSize,
+  IN VOID                           *Buffer,
+  IN UINTN                          Timeout
   );
-  
 
 /**
   Receive HCI event packet.
 
-  @param  This          Pointer to the EFI_BLUETOOTH_HC_PROTOCOL instance.
-  @param  BufferSize    On input, indicates the size, in bytes, of the data buffer specified by Buffer. 
-                        On output, indicates the amount of data actually transferred.
-  @param  Buffer        A pointer to the buffer of data that will be received from Bluetooth host controller.
-  @param  Timeout       Indicating the transfer should be completed within this time frame. The units are 
-                        in milliseconds. If Timeout is 0, then the caller must wait for the function to 
-                        be completed until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.
-
-  @retval EFI_SUCCESS           The HCI event packet is received successfully.
-  @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
-                                - BufferSize is NULL.
-                                - *BufferSize is 0.
-                                - Buffer is NULL.
-  @retval EFI_TIMEOUT           Receiving HCI event packet fail due to timeout.
-  @retval EFI_DEVICE_ERROR      Receiving HCI event packet fail due to host controller or device error.
+  The ReceiveEvent() function receives HCI event packet. Buffer holds the whole HCI event
+  packet, including EventCode, parameter length, and parameters.
+
+  @param[in]      This              Pointer to the EFI_BLUETOOTH_HC_PROTOCOL instance.
+  @param[in,out]  BufferSize        On input, indicates the size, in bytes, of the data buffer
+                                    specified by Buffer. On output, indicates the amount of
+                                    data actually transferred.
+  @param[out]     Buffer            A pointer to the buffer of data that will be received from
+                                    Bluetooth host controller.
+  @param[in]      Timeout           Indicating the transfer should be completed within this
+                                    time frame. The units are in milliseconds. If Timeout is 0,
+                                    then the caller must wait for the function to be completed
+                                    until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.
+
+  @retval EFI_SUCCESS               The HCI event packet is received successfully.
+  @retval EFI_INVALID_PARAMETER     One or more of the following conditions is TRUE:
+                                      BufferSize is NULL.
+                                      *BufferSize is 0.
+                                      Buffer is NULL.
+  @retval EFI_TIMEOUT               Receiving HCI event packet fail due to timeout.
+  @retval EFI_DEVICE_ERROR          Receiving HCI event packet fail due to host controller or device
+                                    error.
 
 **/
 typedef
 EFI_STATUS
 (EFIAPI *EFI_BLUETOOTH_HC_RECEIVE_EVENT)(
-  IN EFI_BLUETOOTH_HC_PROTOCOL  *This,
-  IN OUT UINTN                  *BufferSize,
-  OUT VOID                      *Buffer,
-  IN UINTN                      Timeout
+  IN EFI_BLUETOOTH_HC_PROTOCOL      *This,
+  IN OUT UINTN                      *BufferSize,
+  OUT VOID                          *Buffer,
+  IN UINTN                          Timeout
   );
-  
+
 /**
-  Callback function, it is called when asynchronous transfer is completed.
+  The async callback of AsyncReceiveEvent().
 
-  @param  Data              Pointer to the EFI_BLUETOOTH_HC_PROTOCOL instance.
-  @param  DataLength        Specifies the length, in bytes, of the data to be received.
-  @param  Context           Data passed into Callback function. This is optional parameter and may be NULL.
+  @param[in]  Data                  Data received via asynchronous transfer.
+  @param[in]  DataLength            The length of Data in bytes, received via asynchronous
+                                    transfer.
+  @param[in]  Context               Context passed from asynchronous transfer request.
 
-  @retval EFI_SUCCESS             The callback function complete successfully.
+  @retval EFI_SUCCESS               The callback does execute successfully.
+  @retval Others                    The callback doesn't execute successfully.
 
 **/
 typedef
 EFI_STATUS
 (EFIAPI *EFI_BLUETOOTH_HC_ASYNC_FUNC_CALLBACK) (
-  IN VOID                       *Data,
-  IN UINTN                      DataLength,
-  IN VOID                       *Context
+  IN VOID                           *Data,
+  IN UINTN                          DataLength,
+  IN VOID                           *Context
   );
-  
+
 /**
   Receive HCI event packet in non-blocking way.
 
-  @param  This              Pointer to the EFI_BLUETOOTH_HC_PROTOCOL instance.
-  @param  IsNewTransfer     If TRUE, a new transfer will be submitted. If FALSE, the request is deleted.
-  @param  PollingInterval   Indicates the periodic rate, in milliseconds, that the transfer is to be executed.
-  @param  DataLength        Specifies the length, in bytes, of the data to be received.
-  @param  Callback          The callback function. This function is called if the asynchronous transfer is 
-                            completed.
-  @param  Context           Data passed into Callback function. This is optional parameter and may be NULL.
-
-  @retval EFI_SUCCESS           The HCI asynchronous receive request is submitted successfully.
-  @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
-                                - DataLength is 0.
-                                - If IsNewTransfer is TRUE, and an asynchronous receive request already exists.
-
+  The AsyncReceiveEvent() function receives HCI event packet in non-blocking way. Data
+  in Callback function holds the whole HCI event packet, including EventCode, parameter
+  length, and parameters.
+
+  @param[in]  This                  Pointer to the EFI_BLUETOOTH_HC_PROTOCOL instance.
+  @param[in]  IsNewTransfer         If TRUE, a new transfer will be submitted. If FALSE, the
+                                    request is deleted.
+  @param[in]  PollingInterval       Indicates the periodic rate, in milliseconds, that the
+                                    transfer is to be executed.
+  @param[in]  DataLength            Specifies the length, in bytes, of the data to be received.
+  @param[in]  Callback              The callback function. This function is called if the
+                                    asynchronous transfer is completed.
+  @param[in]  Context               Data passed into Callback function. This is optional
+                                    parameter and may be NULL.
+
+  @retval EFI_SUCCESS               The HCI asynchronous receive request is submitted successfully.
+  @retval EFI_INVALID_PARAMETER     One or more of the following conditions is TRUE:
+                                      DataLength is 0.
+                                      If IsNewTransfer is TRUE, and an asynchronous receive
+                                      request already exists.
 **/
 typedef
 EFI_STATUS
-(EFIAPI *EFI_BLUETOOTH_HC_ASYNC_RECEIVE_EVENT)(
-  IN EFI_BLUETOOTH_HC_PROTOCOL            *This,
-  IN BOOLEAN                              IsNewTransfer,
-  IN UINTN                                PollingInterval,
-  IN UINTN                                DataLength,
-  IN EFI_BLUETOOTH_HC_ASYNC_FUNC_CALLBACK Callback,
-  IN VOID                                 *Context
+(EFIAPI *EFI_BLUETOOTH_HC_ASYNC_RECEIVE_EVENT) (
+  IN EFI_BLUETOOTH_HC_PROTOCOL              *This,
+  IN BOOLEAN                                IsNewTransfer,
+  IN UINTN                                  PollingInterval,
+  IN UINTN                                  DataLength,
+  IN EFI_BLUETOOTH_HC_ASYNC_FUNC_CALLBACK   Callback,
+  IN VOID                                   *Context
   );
-  
+
 /**
   Send HCI ACL data packet.
 
-  @param  This          Pointer to the EFI_BLUETOOTH_HC_PROTOCOL instance.
-  @param  BufferSize    On input, indicates the size, in bytes, of the data buffer specified by Buffer. 
-                        On output, indicates the amount of data actually transferred.
-  @param  Buffer        A pointer to the buffer of data that will be transmitted to Bluetooth host 
-                        controller.
-  @param  Timeout       Indicating the transfer should be completed within this time frame. The units are 
-                        in milliseconds. If Timeout is 0, then the caller must wait for the function to 
-                        be completed until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.
-
-  @retval EFI_SUCCESS           The HCI ACL data packet is sent successfully.
-  @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
-                                - BufferSize is NULL.
-                                - *BufferSize is 0.
-                                - Buffer is NULL.
-  @retval EFI_TIMEOUT           Sending HCI ACL data packet fail due to timeout.
-  @retval EFI_DEVICE_ERROR      Sending HCI ACL data packet fail due to host controller or device error.
+  The SendACLData() function sends HCI ACL data packet. Buffer holds the whole HCI ACL
+  data packet, including Handle, PB flag, BC flag, data length, and data.
+
+  The SendACLData() function and ReceiveACLData() function just send and receive data
+  payload from application layer. In order to protect the payload data, the Bluetooth bus is
+  required to call HCI_Set_Connection_Encryption command to enable hardware based
+  encryption after authentication completed, according to pairing mode and host
+  capability.
+
+  @param[in]       This             Pointer to the EFI_BLUETOOTH_HC_PROTOCOL instance.
+  @param[in, out]  BufferSize       On input, indicates the size, in bytes, of the data buffer
+                                    specified by Buffer. On output, indicates the amount of
+                                    data actually transferred.
+  @param[in]       Buffer           A pointer to the buffer of data that will be transmitted to
+                                    Bluetooth host controller.
+  @param[in]       Timeout          Indicating the transfer should be completed within this
+                                    time frame. The units are in milliseconds. If Timeout is 0,
+                                    then the caller must wait for the function to be completed
+                                    until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.
+
+  @retval EFI_SUCCESS               The HCI ACL data packet is sent successfully.
+  @retval EFI_INVALID_PARAMETER     One or more of the following conditions is TRUE:
+                                      BufferSize is NULL.
+                                      *BufferSize is 0.
+                                      Buffer is NULL.
+  @retval EFI_TIMEOUT               Sending HCI ACL data packet fail due to timeout.
+  @retval EFI_DEVICE_ERROR          Sending HCI ACL data packet fail due to host controller or device
+                                    error.
 
 **/
 typedef
 EFI_STATUS
 (EFIAPI *EFI_BLUETOOTH_HC_SEND_ACL_DATA)(
-  IN EFI_BLUETOOTH_HC_PROTOCOL  *This,
-  IN OUT UINTN                  *BufferSize,
-  IN VOID                       *Buffer,
-  IN UINTN                      Timeout
+  IN EFI_BLUETOOTH_HC_PROTOCOL      *This,
+  IN OUT UINTN                      *BufferSize,
+  IN VOID                           *Buffer,
+  IN UINTN                          Timeout
   );
-  
+
 /**
   Receive HCI ACL data packet.
 
-  @param  This          Pointer to the EFI_BLUETOOTH_HC_PROTOCOL instance.
-  @param  BufferSize    On input, indicates the size, in bytes, of the data buffer specified by Buffer. 
-                        On output, indicates the amount of data actually transferred.
-  @param  Buffer        A pointer to the buffer of data that will be received from Bluetooth host controller.
-  @param  Timeout       Indicating the transfer should be completed within this time frame. The units are 
-                        in milliseconds. If Timeout is 0, then the caller must wait for the function to 
-                        be completed until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.
-
-  @retval EFI_SUCCESS           The HCI ACL data packet is received successfully.
-  @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
-                                - BufferSize is NULL.
-                                - *BufferSize is 0.
-                                - Buffer is NULL.
-  @retval EFI_TIMEOUT           Receiving HCI ACL data packet fail due to timeout.
-  @retval EFI_DEVICE_ERROR      Receiving HCI ACL data packet fail due to host controller or device error.
+  The ReceiveACLData() function receives HCI ACL data packet. Buffer holds the whole HCI
+  ACL data packet, including Handle, PB flag, BC flag, data length, and data.
+
+  @param[in]       This             Pointer to the EFI_BLUETOOTH_HC_PROTOCOL instance.
+  @param[in, out]  BufferSize       On input, indicates the size, in bytes, of the data buffer
+                                    specified by Buffer. On output, indicates the amount of
+                                    data actually transferred.
+  @param[out]      Buffer           A pointer to the buffer of data that will be received from
+                                    Bluetooth host controller.
+  @param[in]       Timeout          Indicating the transfer should be completed within this
+                                    time frame. The units are in milliseconds. If Timeout is 0,
+                                    then the caller must wait for the function to be completed
+                                    until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.
+
+  @retval EFI_SUCCESS               The HCI ACL data packet is received successfully.
+  @retval EFI_INVALID_PARAMETER     One or more of the following conditions is TRUE:
+                                      BufferSize is NULL.
+                                      *BufferSize is 0.
+                                      Buffer is NULL.
+  @retval EFI_TIMEOUT               Receiving HCI ACL data packet fail due to timeout.
+  @retval EFI_DEVICE_ERROR          Receiving HCI ACL data packet fail due to host controller or device
+                                    error.
 
 **/
 typedef
 EFI_STATUS
 (EFIAPI *EFI_BLUETOOTH_HC_RECEIVE_ACL_DATA)(
-  IN EFI_BLUETOOTH_HC_PROTOCOL  *This,
-  IN OUT UINTN                  *BufferSize,
-  OUT VOID                      *Buffer,
-  IN UINTN                      Timeout
+  IN EFI_BLUETOOTH_HC_PROTOCOL      *This,
+  IN OUT UINTN                      *BufferSize,
+  OUT VOID                          *Buffer,
+  IN UINTN                          Timeout
   );
-  
 
 /**
   Receive HCI ACL data packet in non-blocking way.
 
-  @param  This              Pointer to the EFI_BLUETOOTH_HC_PROTOCOL instance.
-  @param  IsNewTransfer     If TRUE, a new transfer will be submitted. If FALSE, the request is deleted.
-  @param  PollingInterval   Indicates the periodic rate, in milliseconds, that the transfer is to be executed.
-  @param  DataLength        Specifies the length, in bytes, of the data to be received.
-  @param  Callback          The callback function. This function is called if the asynchronous transfer is 
-                            completed.
-  @param  Context           Data passed into Callback function. This is optional parameter and may be NULL.
-
-  @retval EFI_SUCCESS           The HCI asynchronous receive request is submitted successfully.
-  @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
-                                - DataLength is 0.
-                                - If IsNewTransfer is TRUE, and an asynchronous receive request already exists.
-
+  The AsyncReceiveACLData() function receives HCI ACL data packet in non-blocking way.
+  Data in Callback holds the whole HCI ACL data packet, including Handle, PB flag, BC flag,
+  data length, and data.
+
+  @param[in]  This                  Pointer to the EFI_BLUETOOTH_HC_PROTOCOL instance.
+  @param[in]  IsNewTransfer         If TRUE, a new transfer will be submitted. If FALSE, the
+                                    request is deleted.
+  @param[in]  PollingInterval       Indicates the periodic rate, in milliseconds, that the
+                                    transfer is to be executed.
+  @param[in]  DataLength            Specifies the length, in bytes, of the data to be received.
+  @param[in]  Callback              The callback function. This function is called if the
+                                    asynchronous transfer is completed.
+  @param[in]  Context               Data passed into Callback function. This is optional
+                                    parameter and may be NULL.
+
+  @retval EFI_SUCCESS               The HCI asynchronous receive request is submitted successfully.
+  @retval EFI_INVALID_PARAMETER     One or more of the following conditions is TRUE:
+                                      DataLength is 0.
+                                      If IsNewTransfer is TRUE, and an asynchronous receive
+                                      request already exists.
 **/
 typedef
 EFI_STATUS
 (EFIAPI *EFI_BLUETOOTH_HC_ASYNC_RECEIVE_ACL_DATA) (
-  IN EFI_BLUETOOTH_HC_PROTOCOL            *This,
-  IN BOOLEAN                              IsNewTransfer,
-  IN UINTN                                PollingInterval,
-  IN UINTN                                DataLength,
-  IN EFI_BLUETOOTH_HC_ASYNC_FUNC_CALLBACK Callback,
-  IN VOID                                 *Context
+  IN EFI_BLUETOOTH_HC_PROTOCOL              *This,
+  IN BOOLEAN                                IsNewTransfer,
+  IN UINTN                                  PollingInterval,
+  IN UINTN                                  DataLength,
+  IN EFI_BLUETOOTH_HC_ASYNC_FUNC_CALLBACK   Callback,
+  IN VOID                                   *Context
   );
-  
+
 /**
   Send HCI SCO data packet.
 
-  @param  This          Pointer to the EFI_BLUETOOTH_HC_PROTOCOL instance.
-  @param  BufferSize    On input, indicates the size, in bytes, of the data buffer specified by Buffer. 
-                        On output, indicates the amount of data actually transferred.
-  @param  Buffer        A pointer to the buffer of data that will be transmitted to Bluetooth host 
-                        controller.
-  @param  Timeout       Indicating the transfer should be completed within this time frame. The units are 
-                        in milliseconds. If Timeout is 0, then the caller must wait for the function to 
-                        be completed until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.
-
-  @retval EFI_SUCCESS           The HCI SCO data packet is sent successfully.
-  @retval EFI_UNSUPPORTED       The implementation does not support HCI SCO transfer.
-  @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
-                                - BufferSize is NULL.
-                                - *BufferSize is 0.
-                                - Buffer is NULL.
-  @retval EFI_TIMEOUT           Sending HCI SCO data packet fail due to timeout.
-  @retval EFI_DEVICE_ERROR      Sending HCI SCO data packet fail due to host controller or device error.
-
+  The SendSCOData() function sends HCI SCO data packet. Buffer holds the whole HCI SCO
+  data packet, including ConnectionHandle, PacketStatus flag, data length, and data.
+
+  @param[in]      This              Pointer to the EFI_BLUETOOTH_HC_PROTOCOL instance.
+  @param[in,out]  BufferSize        On input, indicates the size, in bytes, of the data buffer
+                                    specified by Buffer. On output, indicates the amount of
+                                    data actually transferred.
+  @param[in]      Buffer            A pointer to the buffer of data that will be transmitted to
+                                    Bluetooth host controller.
+  @param[in]      Timeout           Indicating the transfer should be completed within this
+                                    time frame. The units are in milliseconds. If Timeout is 0,
+                                    then the caller must wait for the function to be completed
+                                    until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.
+
+  @retval EFI_SUCCESS               The HCI SCO data packet is sent successfully.
+  @retval EFI_UNSUPPORTED           The implementation does not support HCI SCO transfer.
+  @retval EFI_INVALID_PARAMETER     One or more of the following conditions is TRUE:
+                                      BufferSize is NULL.
+                                      *BufferSize is 0.
+                                      Buffer is NULL.
+  @retval EFI_TIMEOUT               Sending HCI SCO data packet fail due to timeout.
+  @retval EFI_DEVICE_ERROR          Sending HCI SCO data packet fail due to host controller or device
+                                    error.
 **/
 typedef
 EFI_STATUS
 (EFIAPI *EFI_BLUETOOTH_HC_SEND_SCO_DATA)(
-  IN EFI_BLUETOOTH_HC_PROTOCOL  *This,
-  IN OUT UINTN                  *BufferSize,
-  IN VOID                       *Buffer,
-  IN UINTN                      Timeout
+  IN EFI_BLUETOOTH_HC_PROTOCOL      *This,
+  IN OUT UINTN                      *BufferSize,
+  IN VOID                           *Buffer,
+  IN UINTN                          Timeout
   );
-  
+
 /**
   Receive HCI SCO data packet.
 
-  @param  This          Pointer to the EFI_BLUETOOTH_HC_PROTOCOL instance.
-  @param  BufferSize    On input, indicates the size, in bytes, of the data buffer specified by Buffer. 
-                        On output, indicates the amount of data actually transferred.
-  @param  Buffer        A pointer to the buffer of data that will be received from Bluetooth host controller.
-  @param  Timeout       Indicating the transfer should be completed within this time frame. The units are 
-                        in milliseconds. If Timeout is 0, then the caller must wait for the function to 
-                        be completed until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.
-
-  @retval EFI_SUCCESS           The HCI SCO data packet is received successfully.
-  @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
-                                - BufferSize is NULL.
-                                - *BufferSize is 0.
-                                - Buffer is NULL.
-  @retval EFI_TIMEOUT           Receiving HCI SCO data packet fail due to timeout
-  @retval EFI_DEVICE_ERROR      Receiving HCI SCO data packet fail due to host controller or device error.
-
+  The ReceiveSCOData() function receives HCI SCO data packet. Buffer holds the whole HCI
+  SCO data packet, including ConnectionHandle, PacketStatus flag, data length, and data.
+
+  @param[in]      This              Pointer to the EFI_BLUETOOTH_HC_PROTOCOL instance.
+  @param[in,out]  BufferSize        On input, indicates the size, in bytes, of the data buffer
+                                    specified by Buffer. On output, indicates the amount of
+                                    data actually transferred.
+  @param[out]     Buffer            A pointer to the buffer of data that will be received from
+                                    Bluetooth host controller.
+  @param[in]      Timeout           Indicating the transfer should be completed within this
+                                    time frame. The units are in milliseconds. If Timeout is 0,
+                                    then the caller must wait for the function to be completed
+                                    until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.
+
+  @retval EFI_SUCCESS               The HCI SCO data packet is received successfully.
+  @retval EFI_INVALID_PARAMETER     One or more of the following conditions is TRUE:
+                                      BufferSize is NULL.
+                                      *BufferSize is 0.
+                                      Buffer is NULL.
+  @retval EFI_TIMEOUT               Receiving HCI SCO data packet fail due to timeout.
+  @retval EFI_DEVICE_ERROR          Receiving HCI SCO data packet fail due to host controller or device
+                                    error.
 **/
 typedef
 EFI_STATUS
 (EFIAPI *EFI_BLUETOOTH_HC_RECEIVE_SCO_DATA)(
-  IN EFI_BLUETOOTH_HC_PROTOCOL  *This,
-  IN OUT UINTN                  *BufferSize,
-  OUT VOID                      *Buffer,
-  IN UINTN                      Timeout
+  IN EFI_BLUETOOTH_HC_PROTOCOL      *This,
+  IN OUT UINTN                      *BufferSize,
+  OUT VOID                          *Buffer,
+  IN UINTN                          Timeout
   );
 
 /**
   Receive HCI SCO data packet in non-blocking way.
 
-  @param  This              Pointer to the EFI_BLUETOOTH_HC_PROTOCOL instance.
-  @param  IsNewTransfer     If TRUE, a new transfer will be submitted. If FALSE, the request is deleted.
-  @param  PollingInterval   Indicates the periodic rate, in milliseconds, that the transfer is to be executed.
-  @param  DataLength        Specifies the length, in bytes, of the data to be received.
-  @param  Callback          The callback function. This function is called if the asynchronous transfer is 
-                            completed.
-  @param  Context           Data passed into Callback function. This is optional parameter and may be NULL.
-
-  @retval EFI_SUCCESS           The HCI asynchronous receive request is submitted successfully.
-  @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
-                                - DataLength is 0.
-                                - If IsNewTransfer is TRUE, and an asynchronous receive request already exists.
-
+  The AsyncReceiveSCOData() function receives HCI SCO data packet in non-blocking way.
+  Data in Callback holds the whole HCI SCO data packet, including ConnectionHandle,
+  PacketStatus flag, data length, and data.
+
+  @param[in]  This                  Pointer to the EFI_BLUETOOTH_HC_PROTOCOL instance.
+  @param[in]  IsNewTransfer         If TRUE, a new transfer will be submitted. If FALSE, the
+                                    request is deleted.
+  @param[in]  PollingInterval       Indicates the periodic rate, in milliseconds, that the
+                                    transfer is to be executed.
+  @param[in]  DataLength            Specifies the length, in bytes, of the data to be received.
+  @param[in]  Callback              The callback function. This function is called if the
+                                    asynchronous transfer is completed.
+  @param[in]  Context               Data passed into Callback function. This is optional
+                                    parameter and may be NULL.
+
+  @retval EFI_SUCCESS               The HCI asynchronous receive request is submitted successfully.
+  @retval EFI_INVALID_PARAMETER     One or more of the following conditions is TRUE:
+                                      DataLength is 0.
+                                      If IsNewTransfer is TRUE, and an asynchronous receive
+                                      request already exists.
 **/
 typedef
 EFI_STATUS
 (EFIAPI *EFI_BLUETOOTH_HC_ASYNC_RECEIVE_SCO_DATA) (
-  IN EFI_BLUETOOTH_HC_PROTOCOL            *This,
-  IN BOOLEAN                              IsNewTransfer,
-  IN UINTN                                PollingInterval,
-  IN UINTN                                DataLength,
-  IN EFI_BLUETOOTH_HC_ASYNC_FUNC_CALLBACK Callback,
-  IN VOID                                 *Context
+  IN EFI_BLUETOOTH_HC_PROTOCOL              *This,
+  IN BOOLEAN                                IsNewTransfer,
+  IN UINTN                                  PollingInterval,
+  IN UINTN                                  DataLength,
+  IN EFI_BLUETOOTH_HC_ASYNC_FUNC_CALLBACK   Callback,
+  IN VOID                                   *Context
   );
-  
-///
-/// This protocol abstracts the Bluetooth host controller layer message transmit and receive.
-///
+
+//
+// The EFI_BLUETOOTH_HC_PROTOCOL is used to transmit or receive HCI layer data packets.
+//
 struct _EFI_BLUETOOTH_HC_PROTOCOL {
+  //
+  // Send HCI command packet.
+  //
   EFI_BLUETOOTH_HC_SEND_COMMAND               SendCommand;
+  //
+  // Receive HCI event packets.
+  //
   EFI_BLUETOOTH_HC_RECEIVE_EVENT              ReceiveEvent;
+  //
+  // Non-blocking receive HCI event packets.
+  //
   EFI_BLUETOOTH_HC_ASYNC_RECEIVE_EVENT        AsyncReceiveEvent;
+  //
+  // Send HCI ACL (asynchronous connection-oriented) data packets.
+  //
   EFI_BLUETOOTH_HC_SEND_ACL_DATA              SendACLData;
+  //
+  // Receive HCI ACL data packets.
+  //
   EFI_BLUETOOTH_HC_RECEIVE_ACL_DATA           ReceiveACLData;
+  //
+  // Non-blocking receive HCI ACL data packets.
+  //
   EFI_BLUETOOTH_HC_ASYNC_RECEIVE_ACL_DATA     AsyncReceiveACLData;
+  //
+  // Send HCI synchronous (SCO and eSCO) data packets.
+  //
   EFI_BLUETOOTH_HC_SEND_SCO_DATA              SendSCOData;
+  //
+  // Receive HCI synchronous data packets.
+  //
   EFI_BLUETOOTH_HC_RECEIVE_SCO_DATA           ReceiveSCOData;
+  //
+  // Non-blocking receive HCI synchronous data packets.
+  //
   EFI_BLUETOOTH_HC_ASYNC_RECEIVE_SCO_DATA     AsyncReceiveSCOData;
 };
-  
+
 extern EFI_GUID gEfiBluetoothHcProtocolGuid;
 
 #endif
+
diff --git a/MdePkg/Include/Protocol/BluetoothIo.h b/MdePkg/Include/Protocol/BluetoothIo.h
index 652de57a95d6..6530d8e10421 100644
--- a/MdePkg/Include/Protocol/BluetoothIo.h
+++ b/MdePkg/Include/Protocol/BluetoothIo.h
@@ -1,19 +1,13 @@
 /** @file
   EFI Bluetooth IO Service Binding Protocol as defined in UEFI 2.5.
   EFI Bluetooth IO Protocol as defined in UEFI 2.5.
-  The EFI Bluetooth IO Service Binding Protocol is used to locate EFI Bluetooth IO Protocol drivers to 
+  The EFI Bluetooth IO Service Binding Protocol is used to locate EFI Bluetooth IO Protocol drivers to
   create and destroy child of the driver to communicate with other Bluetooth device by using Bluetooth IO protocol.
 
-  Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials are licensed and made available under 
-  the terms and conditions of the BSD License that accompanies this distribution.  
-  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php.                                          
-    
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
-  @par Revision Reference:          
+  @par Revision Reference:
   This Protocol is introduced in UEFI Specification 2.5
 
 **/
@@ -25,14 +19,14 @@
 
 #define EFI_BLUETOOTH_IO_SERVICE_BINDING_PROTOCOL_GUID \
   { \
-    0x388278d3, 0x7b85, 0x42f0, { 0xab, 0xa9, 0xfb, 0x4b, 0xfd, 0x69, 0xf5, 0xab   } \
+    0x388278d3, 0x7b85, 0x42f0, { 0xab, 0xa9, 0xfb, 0x4b, 0xfd, 0x69, 0xf5, 0xab } \
   }
-  
+
 #define EFI_BLUETOOTH_IO_PROTOCOL_GUID \
   { \
-    0x467313de, 0x4e30, 0x43f1, { 0x94, 0x3e, 0x32, 0x3f, 0x89, 0x84, 0x5d, 0xb5  } \
+    0x467313de, 0x4e30, 0x43f1, { 0x94, 0x3e, 0x32, 0x3f, 0x89, 0x84, 0x5d, 0xb5 } \
   }
-  
+
 typedef struct _EFI_BLUETOOTH_IO_PROTOCOL EFI_BLUETOOTH_IO_PROTOCOL;
 
 ///
@@ -72,51 +66,51 @@ typedef struct {
 /**
   Get Bluetooth device information.
 
-  @param  This            Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance.
-  @param  DeviceInfoSize  A pointer to the size, in bytes, of the DeviceInfo buffer.
-  @param  DeviceInfo      A pointer to a callee allocated buffer that returns Bluetooth device information.
+  @param[in]   This               Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance.
+  @param[out]  DeviceInfoSize     A pointer to the size, in bytes, of the DeviceInfo buffer.
+  @param[out]  DeviceInfo         A pointer to a callee allocated buffer that returns Bluetooth device information.
 
-  @retval EFI_SUCCESS           The Bluetooth device information is returned successfully.
-  @retval EFI_DEVICE_ERROR      A hardware error occurred trying to retrieve the Bluetooth device information.
+  @retval EFI_SUCCESS             The Bluetooth device information is returned successfully.
+  @retval EFI_DEVICE_ERROR        A hardware error occurred trying to retrieve the Bluetooth device information.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_BLUETOOTH_IO_GET_DEVICE_INFO)(
-  IN EFI_BLUETOOTH_IO_PROTOCOL  *This,
-  OUT UINTN                     *DeviceInfoSize,
-  OUT VOID                      **DeviceInfo
+  IN EFI_BLUETOOTH_IO_PROTOCOL    *This,
+  OUT UINTN                       *DeviceInfoSize,
+  OUT VOID                        **DeviceInfo
   );
-  
+
 /**
   Get Bluetooth SDP information.
 
-  @param  This            Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance.
-  @param  SdpInfoSize     A pointer to the size, in bytes, of the SdpInfo buffer.
-  @param  SdpInfo         A pointer to a callee allocated buffer that returns Bluetooth SDP information.
+  @param[in]  This                Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance.
+  @param[out] SdpInfoSize         A pointer to the size, in bytes, of the SdpInfo buffer.
+  @param[out] SdpInfo             A pointer to a callee allocated buffer that returns Bluetooth SDP information.
 
-  @retval EFI_SUCCESS           The Bluetooth device information is returned successfully.
-  @retval EFI_DEVICE_ERROR      A hardware error occurred trying to retrieve the Bluetooth SDP information.
+  @retval EFI_SUCCESS             The Bluetooth device information is returned successfully.
+  @retval EFI_DEVICE_ERROR        A hardware error occurred trying to retrieve the Bluetooth SDP information.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_BLUETOOTH_IO_GET_SDP_INFO)(
-  IN EFI_BLUETOOTH_IO_PROTOCOL  *This,
-  OUT UINTN                     *SdpInfoSize,
-  OUT VOID                      **SdpInfo
+  IN EFI_BLUETOOTH_IO_PROTOCOL    *This,
+  OUT UINTN                       *SdpInfoSize,
+  OUT VOID                        **SdpInfo
   );
-  
+
 /**
   Send L2CAP message (including L2CAP header).
 
-  @param  This            Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance.
-  @param  BufferSize      On input, indicates the size, in bytes, of the data buffer specified by Buffer. 
-                          On output, indicates the amount of data actually transferred.
-  @param  Buffer          A pointer to the buffer of data that will be transmitted to Bluetooth L2CAP layer.
-  @param  Timeout         Indicating the transfer should be completed within this time frame. The units are in 
-                          milliseconds. If Timeout is 0, then the caller must wait for the function to be completed 
-                          until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.
+  @param[in]      This            Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance.
+  @param[in, out] BufferSize      On input, indicates the size, in bytes, of the data buffer specified by Buffer.
+                                  On output, indicates the amount of data actually transferred.
+  @param[in]      Buffer          A pointer to the buffer of data that will be transmitted to Bluetooth L2CAP layer.
+  @param[in]      Timeout         Indicating the transfer should be completed within this time frame. The units are in
+                                  milliseconds. If Timeout is 0, then the caller must wait for the function to be completed
+                                  until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.
 
   @retval EFI_SUCCESS             The L2CAP message is sent successfully.
   @retval EFI_INVALID_PARAMETER   One or more of the following conditions is TRUE:
@@ -127,25 +121,25 @@ EFI_STATUS
   @retval EFI_DEVICE_ERROR        Sending L2CAP message fail due to host controller or device error.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_BLUETOOTH_IO_L2CAP_RAW_SEND)(
-  IN EFI_BLUETOOTH_IO_PROTOCOL  *This,
-  IN OUT UINTN                  *BufferSize,
-  IN VOID                       *Buffer,
-  IN UINTN                      Timeout
+  IN EFI_BLUETOOTH_IO_PROTOCOL      *This,
+  IN OUT UINTN                      *BufferSize,
+  IN VOID                           *Buffer,
+  IN UINTN                          Timeout
   );
-  
+
 /**
   Receive L2CAP message (including L2CAP header).
 
-  @param  This            Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance.
-  @param  BufferSize      On input, indicates the size, in bytes, of the data buffer specified by Buffer. 
-                          On output, indicates the amount of data actually transferred.
-  @param  Buffer          A pointer to the buffer of data that will be received from Bluetooth L2CAP layer.
-  @param  Timeout         Indicating the transfer should be completed within this time frame. The units are in 
-                          milliseconds. If Timeout is 0, then the caller must wait for the function to be completed 
-                          until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.
+  @param[in]  This                Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance.
+  @param[in]  BufferSize          On input, indicates the size, in bytes, of the data buffer specified by Buffer.
+                                  On output, indicates the amount of data actually transferred.
+  @param[out] Buffer              A pointer to the buffer of data that will be received from Bluetooth L2CAP layer.
+  @param[in]  Timeout             Indicating the transfer should be completed within this time frame. The units are in
+                                  milliseconds. If Timeout is 0, then the caller must wait for the function to be completed
+                                  until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.
 
   @retval EFI_SUCCESS             The L2CAP message is received successfully.
   @retval EFI_INVALID_PARAMETER   One or more of the following conditions is TRUE:
@@ -156,7 +150,7 @@ EFI_STATUS
   @retval EFI_DEVICE_ERROR        Receiving L2CAP message fail due to host controller or device error.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_BLUETOOTH_IO_L2CAP_RAW_RECEIVE)(
   IN EFI_BLUETOOTH_IO_PROTOCOL  *This,
@@ -164,16 +158,16 @@ EFI_STATUS
   OUT VOID                      *Buffer,
   IN UINTN                      Timeout
   );
-  
+
 /**
   Callback function, it is called when asynchronous transfer is completed.
 
-  @param  ChannelID         Bluetooth L2CAP message channel ID.
-  @param  Data              Data received via asynchronous transfer.
-  @param  DataLength        The length of Data in bytes, received via asynchronous transfer.
-  @param  Context           Context passed from asynchronous transfer request.
+  @param[in]  ChannelID         Bluetooth L2CAP message channel ID.
+  @param[in]  Data              Data received via asynchronous transfer.
+  @param[in]  DataLength        The length of Data in bytes, received via asynchronous transfer.
+  @param[in]  Context           Context passed from asynchronous transfer request.
 
-  @retval EFI_SUCCESS       The callback function complete successfully.
+  @retval EFI_SUCCESS           The callback function complete successfully.
 
 **/
 typedef
@@ -184,25 +178,25 @@ EFI_STATUS
   IN UINTN                      DataLength,
   IN VOID                       *Context
   );
-  
+
 /**
   Receive L2CAP message (including L2CAP header) in non-blocking way.
 
-  @param  This            Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance.
-  @param  IsNewTransfer   If TRUE, a new transfer will be submitted. If FALSE, the request is deleted.
-  @param  PollingInterval Indicates the periodic rate, in milliseconds, that the transfer is to be executed.
-  @param  DataLength      Specifies the length, in bytes, of the data to be received.
-  @param  Callback        The callback function. This function is called if the asynchronous transfer is 
-                          completed.
-  @param  Context         Data passed into Callback function. This is optional parameter and may be NULL. 
-  
+  @param[in]  This                Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance.
+  @param[in]  IsNewTransfer       If TRUE, a new transfer will be submitted. If FALSE, the request is deleted.
+  @param[in]  PollingInterval     Indicates the periodic rate, in milliseconds, that the transfer is to be executed.
+  @param[in]  DataLength          Specifies the length, in bytes, of the data to be received.
+  @param[in]  Callback            The callback function. This function is called if the asynchronous transfer is
+                                  completed.
+  @param[in]  Context             Data passed into Callback function. This is optional parameter and may be NULL.
+
   @retval EFI_SUCCESS             The L2CAP asynchronous receive request is submitted successfully.
   @retval EFI_INVALID_PARAMETER   One or more of the following conditions is TRUE:
                                   - DataLength is 0.
                                   - If IsNewTransfer is TRUE, and an asynchronous receive request already exists.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_BLUETOOTH_IO_L2CAP_RAW_ASYNC_RECEIVE)(
   IN EFI_BLUETOOTH_IO_PROTOCOL              *This,
@@ -216,14 +210,14 @@ EFI_STATUS
 /**
   Send L2CAP message (excluding L2CAP header) to a specific channel.
 
-  @param  This            Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance.
-  @param  Handle          A handle created by EFI_BLUETOOTH_IO_PROTOCOL.L2CapConnect indicates which channel to send.
-  @param  BufferSize      On input, indicates the size, in bytes, of the data buffer specified by Buffer. 
-                          On output, indicates the amount of data actually transferred.
-  @param  Buffer          A pointer to the buffer of data that will be transmitted to Bluetooth L2CAP layer.
-  @param  Timeout         Indicating the transfer should be completed within this time frame. The units are in 
-                          milliseconds. If Timeout is 0, then the caller must wait for the function to be completed 
-                          until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.
+  @param[in]      This            Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance.
+  @param[in]      Handle          A handle created by EFI_BLUETOOTH_IO_PROTOCOL.L2CapConnect indicates which channel to send.
+  @param[in, out] BufferSize      On input, indicates the size, in bytes, of the data buffer specified by Buffer.
+                                  On output, indicates the amount of data actually transferred.
+  @param[in]      Buffer          A pointer to the buffer of data that will be transmitted to Bluetooth L2CAP layer.
+  @param[in]      Timeout         Indicating the transfer should be completed within this time frame. The units are in
+                                  milliseconds. If Timeout is 0, then the caller must wait for the function to be completed
+                                  until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.
 
   @retval EFI_SUCCESS             The L2CAP message is sent successfully.
   @retval EFI_NOT_FOUND           Handle is invalid or not found.
@@ -235,26 +229,26 @@ EFI_STATUS
   @retval EFI_DEVICE_ERROR        Sending L2CAP message fail due to host controller or device error.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_BLUETOOTH_IO_L2CAP_SEND)(
-  IN EFI_BLUETOOTH_IO_PROTOCOL  *This,
-  IN EFI_HANDLE                 Handle,
-  IN OUT UINTN                  *BufferSize,
-  IN VOID                       *Buffer,
-  IN UINTN                      Timeout
+  IN EFI_BLUETOOTH_IO_PROTOCOL      *This,
+  IN EFI_HANDLE                     Handle,
+  IN OUT UINTN                      *BufferSize,
+  IN VOID                           *Buffer,
+  IN UINTN                          Timeout
   );
-  
+
 /**
   Receive L2CAP message (excluding L2CAP header) from a specific channel.
 
-  @param  This            Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance.
-  @param  Handle          A handle created by EFI_BLUETOOTH_IO_PROTOCOL.L2CapConnect indicates which channel to receive.
-  @param  BufferSize      Indicates the size, in bytes, of the data buffer specified by Buffer.
-  @param  Buffer          A pointer to the buffer of data that will be received from Bluetooth L2CAP layer.
-  @param  Timeout         Indicating the transfer should be completed within this time frame. The units are in 
-                          milliseconds. If Timeout is 0, then the caller must wait for the function to be completed 
-                          until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.
+  @param[in]  This                Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance.
+  @param[in]  Handle              A handle created by EFI_BLUETOOTH_IO_PROTOCOL.L2CapConnect indicates which channel to receive.
+  @param[out] BufferSize          Indicates the size, in bytes, of the data buffer specified by Buffer.
+  @param[out] Buffer              A pointer to the buffer of data that will be received from Bluetooth L2CAP layer.
+  @param[in]  Timeout             Indicating the transfer should be completed within this time frame. The units are in
+                                  milliseconds. If Timeout is 0, then the caller must wait for the function to be completed
+                                  until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.
 
   @retval EFI_SUCCESS             The L2CAP message is received successfully.
   @retval EFI_NOT_FOUND           Handle is invalid or not found.
@@ -266,22 +260,22 @@ EFI_STATUS
   @retval EFI_DEVICE_ERROR        Receiving L2CAP message fail due to host controller or device error.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_BLUETOOTH_IO_L2CAP_RECEIVE)(
-  IN EFI_BLUETOOTH_IO_PROTOCOL  *This,
-  IN EFI_HANDLE                 Handle,
-  OUT UINTN                     *BufferSize,
-  OUT VOID                      **Buffer,
-  IN UINTN                      Timeout
+  IN EFI_BLUETOOTH_IO_PROTOCOL    *This,
+  IN EFI_HANDLE                   Handle,
+  OUT UINTN                       *BufferSize,
+  OUT VOID                        **Buffer,
+  IN UINTN                        Timeout
   );
-  
+
 /**
   Callback function, it is called when asynchronous transfer is completed.
 
-  @param  Data              Data received via asynchronous transfer.
-  @param  DataLength        The length of Data in bytes, received via asynchronous transfer.
-  @param  Context           Context passed from asynchronous transfer request.
+  @param[in]  Data                Data received via asynchronous transfer.
+  @param[in]  DataLength          The length of Data in bytes, received via asynchronous transfer.
+  @param[in]  Context             Context passed from asynchronous transfer request.
 
   @retval EFI_SUCCESS       The callback function complete successfully.
 
@@ -289,20 +283,21 @@ EFI_STATUS
 typedef
 EFI_STATUS
 (EFIAPI *EFI_BLUETOOTH_IO_CHANNEL_SERVICE_CALLBACK) (
-  IN VOID                       *Data,
-  IN UINTN                      DataLength,
-  IN VOID                       *Context
+  IN VOID                         *Data,
+  IN UINTN                        DataLength,
+  IN VOID                         *Context
   );
-  
+
 /**
   Receive L2CAP message (excluding L2CAP header) in non-blocking way from a specific channel.
 
-  @param  This            Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance.
-  @param  Handel          A handle created by EFI_BLUETOOTH_IO_PROTOCOL.L2CapConnect indicates which channel to receive.
-  @param  Callback        The callback function. This function is called if the asynchronous transfer is 
-                          completed.
-  @param  Context         Data passed into Callback function. This is optional parameter and may be NULL. 
-  
+  @param[in]  This                Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance.
+  @param[in]  Handel              A handle created by EFI_BLUETOOTH_IO_PROTOCOL.L2CapConnect indicates which channel
+                                  to receive.
+  @param[in]  Callback            The callback function. This function is called if the asynchronous transfer is
+                                  completed.
+  @param[in]  Context             Data passed into Callback function. This is optional parameter and may be NULL.
+
   @retval EFI_SUCCESS             The L2CAP asynchronous receive request is submitted successfully.
   @retval EFI_NOT_FOUND           Handle is invalid or not found.
   @retval EFI_INVALID_PARAMETER   One or more of the following conditions is TRUE:
@@ -310,33 +305,33 @@ EFI_STATUS
                                   - If an asynchronous receive request already exists on same Handle.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_BLUETOOTH_IO_L2CAP_ASYNC_RECEIVE)(
-  IN EFI_BLUETOOTH_IO_PROTOCOL                    *This,
-  IN EFI_HANDLE                                   Handle,
-  IN EFI_BLUETOOTH_IO_CHANNEL_SERVICE_CALLBACK    Callback,
-  IN VOID                                         *Context
+  IN  EFI_BLUETOOTH_IO_PROTOCOL                   *This,
+  IN  EFI_HANDLE                                  Handle,
+  IN  EFI_BLUETOOTH_IO_CHANNEL_SERVICE_CALLBACK   Callback,
+  IN  VOID*                                       Context
   );
-  
+
 /**
   Do L2CAP connection.
 
-  @param  This            Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance.
-  @param  Handel          A handle to indicate this L2CAP connection.
-  @param  Psm             Bluetooth PSM. See Bluetooth specification for detail.
-  @param  Mtu             Bluetooth MTU. See Bluetooth specification for detail.
-  @param  Callback        The callback function. This function is called whenever there is message received 
-                          in this channel.
-  @param  Context         Data passed into Callback function. This is optional parameter and may be NULL.
-  
+  @param[in]  This                Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance.
+  @param[out] Handel              A handle to indicate this L2CAP connection.
+  @param[in]  Psm                 Bluetooth PSM. See Bluetooth specification for detail.
+  @param[in]  Mtu                 Bluetooth MTU. See Bluetooth specification for detail.
+  @param[in]  Callback            The callback function. This function is called whenever there is message received
+                                  in this channel.
+  @param[in]  Context             Data passed into Callback function. This is optional parameter and may be NULL.
+
   @retval EFI_SUCCESS             The Bluetooth L2CAP layer connection is created successfully.
   @retval EFI_INVALID_PARAMETER   One or more of the following conditions is TRUE:
                                   - Handle is NULL.
   @retval EFI_DEVICE_ERROR        A hardware error occurred trying to do Bluetooth L2CAP connection.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_BLUETOOTH_IO_L2CAP_CONNECT)(
   IN EFI_BLUETOOTH_IO_PROTOCOL                    *This,
@@ -346,42 +341,42 @@ EFI_STATUS
   IN EFI_BLUETOOTH_IO_CHANNEL_SERVICE_CALLBACK    Callback,
   IN VOID                                         *Context
   );
-  
+
 /**
   Do L2CAP disconnection.
 
-  @param  This            Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance.
-  @param  Handel          A handle to indicate this L2CAP connection.
-  
+  @param[in]  This                Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance.
+  @param[in]  Handel              A handle to indicate this L2CAP connection.
+
   @retval EFI_SUCCESS             The Bluetooth L2CAP layer is disconnected successfully.
   @retval EFI_NOT_FOUND           Handle is invalid or not found.
   @retval EFI_DEVICE_ERROR        A hardware error occurred trying to do Bluetooth L2CAP disconnection.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_BLUETOOTH_IO_L2CAP_DISCONNECT)(
   IN EFI_BLUETOOTH_IO_PROTOCOL                    *This,
   IN EFI_HANDLE                                   Handle
   );
-  
+
 /**
   Register L2CAP callback function for special channel.
 
-  @param  This            Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance.
-  @param  Handel          A handle to indicate this L2CAP connection.
-  @param  Psm             Bluetooth PSM. See Bluetooth specification for detail.
-  @param  Mtu             Bluetooth MTU. See Bluetooth specification for detail.
-  @param  Callback        The callback function. This function is called whenever there is message received 
-                          in this channel. NULL means unregister.
-  @param  Context         Data passed into Callback function. This is optional parameter and may be NULL.
-  
+  @param[in]  This                Pointer to the EFI_BLUETOOTH_IO_PROTOCOL instance.
+  @param[out] Handel              A handle to indicate this L2CAP connection.
+  @param[in]  Psm                 Bluetooth PSM. See Bluetooth specification for detail.
+  @param[in]  Mtu                 Bluetooth MTU. See Bluetooth specification for detail.
+  @param[in]  Callback            The callback function. This function is called whenever there is message received
+                                  in this channel. NULL means unregister.
+  @param[in]  Context             Data passed into Callback function. This is optional parameter and may be NULL.
+
   @retval EFI_SUCCESS             The Bluetooth L2CAP callback function is registered successfully.
   @retval EFI_ALREADY_STARTED     The callback function already exists when register.
   @retval EFI_NOT_FOUND           The callback function does not exist when unregister.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_BLUETOOTH_IO_L2CAP_REGISTER_SERVICE)(
   IN EFI_BLUETOOTH_IO_PROTOCOL                    *This,
@@ -391,9 +386,9 @@ EFI_STATUS
   IN EFI_BLUETOOTH_IO_CHANNEL_SERVICE_CALLBACK    Callback,
   IN VOID                                         *Context
   );
-  
+
 ///
-/// This protocol provides service for Bluetooth L2CAP (Logical Link Control and Adaptation Protocol) 
+/// This protocol provides service for Bluetooth L2CAP (Logical Link Control and Adaptation Protocol)
 /// and SDP (Service Discovery Protocol).
 ///
 struct _EFI_BLUETOOTH_IO_PROTOCOL {
diff --git a/MdePkg/Include/Protocol/BluetoothLeConfig.h b/MdePkg/Include/Protocol/BluetoothLeConfig.h
new file mode 100644
index 000000000000..eb92015d9ca0
--- /dev/null
+++ b/MdePkg/Include/Protocol/BluetoothLeConfig.h
@@ -0,0 +1,630 @@
+/** @file
+  EFI Bluetooth LE Config Protocol as defined in UEFI 2.7.
+  This protocol abstracts user interface configuration for BluetoothLe device.
+
+  Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  This Protocol is introduced in UEFI Specification 2.7
+
+**/
+
+#ifndef __EFI_BLUETOOTH_LE_CONFIG_H__
+#define __EFI_BLUETOOTH_LE_CONFIG_H__
+
+#include <Protocol/BluetoothConfig.h>
+#include <Protocol/BluetoothAttribute.h>
+
+#define EFI_BLUETOOTH_LE_CONFIG_PROTOCOL_GUID \
+  { \
+    0x8f76da58, 0x1f99, 0x4275, { 0xa4, 0xec, 0x47, 0x56, 0x51, 0x5b, 0x1c, 0xe8 } \
+  }
+
+typedef struct _EFI_BLUETOOTH_LE_CONFIG_PROTOCOL EFI_BLUETOOTH_LE_CONFIG_PROTOCOL;
+
+/**
+  Initialize BluetoothLE host controller and local device.
+
+  The Init() function initializes BluetoothLE host controller and local device.
+
+  @param[in]  This              Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance.
+
+  @retval EFI_SUCCESS           The BluetoothLE host controller and local device is initialized successfully.
+  @retval EFI_DEVICE_ERROR      A hardware error occurred trying to initialize the BluetoothLE host controller
+                                and local device.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_INIT)(
+  IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL  *This
+  );
+
+typedef struct {
+  ///
+  /// The version of the structure. A value of zero represents the EFI_BLUETOOTH_LE_CONFIG_SCAN_PARAMETER
+  /// structure as defined here. Future version of this specification may extend this data structure in a
+  /// backward compatible way and increase the value of Version.
+  ///
+  UINT32                    Version;
+  ///
+  /// Passive scanning or active scanning. See Bluetooth specification.
+  ///
+  UINT8                     ScanType;
+  ///
+  /// Recommended scan interval to be used while performing scan.
+  ///
+  UINT16                    ScanInterval;
+  ///
+  /// Recommended scan window to be used while performing a scan.
+  ///
+  UINT16                    ScanWindow;
+  ///
+  /// Recommended scanning filter policy to be used while performing a scan.
+  ///
+  UINT8                     ScanningFilterPolicy;
+  ///
+  /// This is one byte flag to serve as a filter to remove unneeded scan
+  /// result. For example, set BIT0 means scan in LE Limited Discoverable
+  /// Mode. Set BIT1 means scan in LE General Discoverable Mode.
+  ///
+  UINT8                     AdvertisementFlagFilter;
+} EFI_BLUETOOTH_LE_CONFIG_SCAN_PARAMETER;
+
+typedef struct{
+  BLUETOOTH_LE_ADDRESS BDAddr;
+  BLUETOOTH_LE_ADDRESS DirectAddress;
+  UINT8                RemoteDeviceState;
+  INT8                 RSSI;
+  UINTN                AdvertisementDataSize;
+  VOID                 *AdvertisementData;
+} EFI_BLUETOOTH_LE_SCAN_CALLBACK_INFORMATION;
+
+/**
+  Callback function, it is called if a BluetoothLE device is found during scan process.
+
+  @param[in]  This            Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance.
+  @param[in]  Context         Context passed from scan request.
+  @param[in]  CallbackInfo    Data related to scan result. NULL CallbackInfo means scan complete.
+
+  @retval EFI_SUCCESS         The callback function complete successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_SCAN_CALLBACK_FUNCTION) (
+  IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL             *This,
+  IN VOID                                         *Context,
+  IN EFI_BLUETOOTH_LE_SCAN_CALLBACK_INFORMATION   *CallbackInfo
+  );
+
+/**
+  Scan BluetoothLE device.
+
+  The Scan() function scans BluetoothLE device. When this function is returned, it just means scan
+  request is submitted. It does not mean scan process is started or finished. Whenever there is a
+  BluetoothLE device is found, the Callback function will be called. Callback function might be
+  called before this function returns or after this function returns
+
+  @param[in]  This              Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance.
+  @param[in]  ReScan            If TRUE, a new scan request is submitted no matter there is scan result before.
+                                If FALSE and there is scan result, the previous scan result is returned and no scan request
+                                is submitted.
+  @param[in]  Timeout           Duration in milliseconds for which to scan.
+  @param[in]  ScanParameter     If it is not NULL, the ScanParameter is used to perform a scan by the BluetoothLE bus driver.
+                                If it is NULL, the default parameter is used.
+  @param[in]  Callback          The callback function. This function is called if a BluetoothLE device is found during
+                                scan process.
+  @param[in]  Context           Data passed into Callback function. This is optional parameter and may be NULL.
+
+  @retval EFI_SUCCESS           The Bluetooth scan request is submitted.
+  @retval EFI_DEVICE_ERROR      A hardware error occurred trying to scan the BluetoothLE device.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_SCAN)(
+  IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL                *This,
+  IN BOOLEAN                                         ReScan,
+  IN UINT32                                          Timeout,
+  IN EFI_BLUETOOTH_LE_CONFIG_SCAN_PARAMETER          *ScanParameter, OPTIONAL
+  IN EFI_BLUETOOTH_LE_CONFIG_SCAN_CALLBACK_FUNCTION  Callback,
+  IN VOID                                            *Context
+  );
+
+typedef struct {
+  ///
+  /// The version of the structure. A value of zero represents the
+  /// EFI_BLUETOOTH_LE_CONFIG_CONNECT_PARAMETER
+  /// structure as defined here. Future version of this specification may
+  /// extend this data structure in a backward compatible way and
+  /// increase the value of Version.
+  ///
+  UINT32                    Version;
+  ///
+  /// Recommended scan interval to be used while performing scan before connect.
+  ///
+  UINT16                    ScanInterval;
+  ///
+  /// Recommended scan window to be used while performing a connection
+  ///
+  UINT16                    ScanWindow;
+  ///
+  /// Minimum allowed connection interval. Shall be less than or equal to ConnIntervalMax.
+  ///
+  UINT16                    ConnIntervalMin;
+  ///
+  /// Maximum allowed connection interval. Shall be greater than or equal to ConnIntervalMin.
+  ///
+  UINT16                    ConnIntervalMax;
+  ///
+  /// Slave latency for the connection in number of connection events.
+  ///
+  UINT16                    ConnLatency;
+  ///
+  /// Link supervision timeout for the connection.
+  ///
+  UINT16                    SupervisionTimeout;
+} EFI_BLUETOOTH_LE_CONFIG_CONNECT_PARAMETER;
+
+/**
+  Connect a BluetoothLE device.
+
+  The Connect() function connects a Bluetooth device. When this function is returned successfully,
+  a new EFI_BLUETOOTH_IO_PROTOCOL is created.
+
+  @param[in]  This              Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance.
+  @param[in]  AutoReconnect     If TRUE, the BluetoothLE host controller needs to do an auto
+                                reconnect. If FALSE, the BluetoothLE host controller does not do
+                                an auto reconnect.
+  @param[in]  DoBonding         If TRUE, the BluetoothLE host controller needs to do a bonding.
+                                If FALSE, the BluetoothLE host controller does not do a bonding.
+  @param[in]  ConnectParameter  If it is not NULL, the ConnectParameter is used to perform a
+                                scan by the BluetoothLE bus driver. If it is NULL, the default
+                                parameter is used.
+  @param[in]  BD_ADDR           The address of the BluetoothLE device to be connected.
+
+  @retval EFI_SUCCESS           The BluetoothLE device is connected successfully.
+  @retval EFI_ALREADY_STARTED   The BluetoothLE device is already connected.
+  @retval EFI_NOT_FOUND         The BluetoothLE device is not found.
+  @retval EFI_DEVICE_ERROR      A hardware error occurred trying to connect the BluetoothLE device.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_CONNECT)(
+  IN  EFI_BLUETOOTH_LE_CONFIG_PROTOCOL            *This,
+  IN  BOOLEAN                                     AutoReconnect,
+  IN  BOOLEAN                                     DoBonding,
+  IN  EFI_BLUETOOTH_LE_CONFIG_CONNECT_PARAMETER   *ConnectParameter, OPTIONAL
+  IN  BLUETOOTH_LE_ADDRESS                        *BD_ADDR
+  );
+
+/**
+  Disconnect a BluetoothLE device.
+
+  The Disconnect() function disconnects a BluetoothLE device. When this function is returned
+  successfully, the EFI_BLUETOOTH_ATTRIBUTE_PROTOCOL associated with this device is
+  destroyed and all services associated are stopped.
+
+  @param[in]  This          Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance.
+  @param[in]  BD_ADDR       The address of BluetoothLE device to be connected.
+  @param[in]  Reason        Bluetooth disconnect reason. See Bluetooth specification for detail.
+
+  @retval EFI_SUCCESS           The BluetoothLE device is disconnected successfully.
+  @retval EFI_NOT_STARTED       The BluetoothLE device is not connected.
+  @retval EFI_NOT_FOUND         The BluetoothLE device is not found.
+  @retval EFI_DEVICE_ERROR      A hardware error occurred trying to disconnect the BluetoothLE device.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_DISCONNECT)(
+  IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL  *This,
+  IN BLUETOOTH_LE_ADDRESS              *BD_ADDR,
+  IN UINT8                             Reason
+  );
+
+/**
+  Get BluetoothLE configuration data.
+
+  The GetData() function returns BluetoothLE configuration data. For remote BluetoothLE device
+  configuration data, please use GetRemoteData() function with valid BD_ADDR.
+
+  @param[in]       This         Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance.
+  @param[in]       DataType     Configuration data type.
+  @param[in, out]  DataSize     On input, indicates the size, in bytes, of the data buffer specified by Data.
+                                On output, indicates the amount of data actually returned.
+  @param[in, out]  Data         A pointer to the buffer of data that will be returned.
+
+  @retval EFI_SUCCESS           The BluetoothLE configuration data is returned successfully.
+  @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+                                - DataSize is NULL.
+                                - *DataSize is 0.
+                                - Data is NULL.
+  @retval EFI_UNSUPPORTED       The DataType is unsupported.
+  @retval EFI_NOT_FOUND         The DataType is not found.
+  @retval EFI_BUFFER_TOO_SMALL  The buffer is too small to hold the buffer.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_GET_DATA) (
+  IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL       *This,
+  IN EFI_BLUETOOTH_CONFIG_DATA_TYPE      DataType,
+  IN OUT UINTN                           *DataSize,
+  IN OUT VOID                            *Data OPTIONAL
+  );
+
+/**
+  Set BluetoothLE configuration data.
+
+  The SetData() function sets local BluetoothLE device configuration data. Not all DataType can be
+  set.
+
+  @param[in]  This              Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance.
+  @param[in]  DataType          Configuration data type.
+  @param[in]  DataSize          Indicates the size, in bytes, of the data buffer specified by Data.
+  @param[in]  Data              A pointer to the buffer of data that will be set.
+
+  @retval EFI_SUCCESS           The BluetoothLE configuration data is set successfully.
+  @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+                                - DataSize is 0.
+                                - Data is NULL.
+  @retval EFI_UNSUPPORTED       The DataType is unsupported.
+  @retval EFI_WRITE_PROTECTED   Cannot set configuration data.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_SET_DATA) (
+  IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL       *This,
+  IN EFI_BLUETOOTH_CONFIG_DATA_TYPE         DataType,
+  IN UINTN                                  DataSize,
+  IN VOID                                   *Data
+  );
+
+/**
+  Get remove BluetoothLE device configuration data.
+
+  The GetRemoteData() function returns remote BluetoothLE device configuration data.
+
+  @param[in]  This              Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance.
+  @param[in]  DataType          Configuration data type.
+  @param[in]  BDAddr            Remote BluetoothLE device address.
+  @param[in, out] DataSize      On input, indicates the size, in bytes, of the data buffer specified by Data.
+                                On output, indicates the amount of data actually returned.
+  @param[in, out] Data          A pointer to the buffer of data that will be returned.
+
+  @retval EFI_SUCCESS           The remote BluetoothLE device configuration data is returned successfully.
+  @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+                                - DataSize is NULL.
+                                - *DataSize is 0.
+                                - Data is NULL.
+  @retval EFI_UNSUPPORTED       The DataType is unsupported.
+  @retval EFI_NOT_FOUND         The DataType is not found.
+  @retval EFI_BUFFER_TOO_SMALL  The buffer is too small to hold the buffer.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_GET_REMOTE_DATA) (
+  IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL       *This,
+  IN EFI_BLUETOOTH_CONFIG_DATA_TYPE         DataType,
+  IN BLUETOOTH_LE_ADDRESS                   *BDAddr,
+  IN OUT UINTN                              *DataSize,
+  IN OUT VOID                               *Data
+  );
+
+typedef enum {
+  ///
+  /// It indicates an authorization request. No data is associated with the callback
+  /// input. In the output data, the application should return the authorization value.
+  /// The data structure is BOOLEAN. TRUE means YES. FALSE means NO.
+  ///
+  EfiBluetoothSmpAuthorizationRequestEvent,
+  ///
+  /// It indicates that a passkey has been generated locally by the driver, and the same
+  /// passkey should be entered at the remote device. The callback input data is the
+  /// passkey of type UINT32, to be displayed by the application. No output data
+  /// should be returned.
+  ///
+  EfiBluetoothSmpPasskeyReadyEvent,
+  ///
+  /// It indicates that the driver is requesting for the passkey has been generated at
+  /// the remote device. No data is associated with the callback input. The output data
+  /// is the passkey of type UINT32, to be entered by the user.
+  ///
+  EfiBluetoothSmpPasskeyRequestEvent,
+  ///
+  /// It indicates that the driver is requesting for the passkey that has been pre-shared
+  /// out-of-band with the remote device. No data is associated with the callback
+  /// input. The output data is the stored OOB data of type UINT8[16].
+  ///
+  EfiBluetoothSmpOOBDataRequestEvent,
+  ///
+  /// In indicates that a number have been generated locally by the bus driver, and
+  /// also at the remote device, and the bus driver wants to know if the two numbers
+  /// match. The callback input data is the number of type UINT32. The output data
+  /// is confirmation value of type BOOLEAN. TRUE means comparison pass. FALSE
+  /// means comparison fail.
+  ///
+  EfiBluetoothSmpNumericComparisonEvent,
+} EFI_BLUETOOTH_LE_SMP_EVENT_DATA_TYPE;
+
+/**
+  The callback function for SMP.
+
+  @param[in]  This                Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance.
+  @param[in]  Context             Data passed into callback function. This is optional parameter
+                                  and may be NULL.
+  @param[in]  BDAddr              Remote BluetoothLE device address.
+  @param[in]  EventDataType       Event data type in EFI_BLUETOOTH_LE_SMP_EVENT_DATA_TYPE.
+  @param[in]  DataSize            Indicates the size, in bytes, of the data buffer specified by Data.
+  @param[in]  Data                A pointer to the buffer of data.
+
+  @retval EFI_SUCCESS   The callback function complete successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_LE_SMP_CALLBACK) (
+  IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL       *This,
+  IN VOID                                   *Context,
+  IN BLUETOOTH_LE_ADDRESS                   *BDAddr,
+  IN EFI_BLUETOOTH_LE_SMP_EVENT_DATA_TYPE   EventDataType,
+  IN UINTN                                  DataSize,
+  IN VOID                                   *Data
+  );
+
+/**
+  Register Security Manager Protocol callback function for user authentication/authorization.
+
+  The RegisterSmpAuthCallback() function register Security Manager Protocol callback
+  function for user authentication/authorization.
+
+  @param[in]  This            Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance.
+  @param[in]  Callback        Callback function for user authentication/authorization.
+  @param[in]  Context         Data passed into Callback function. This is optional parameter and may be NULL.
+
+  @retval EFI_SUCCESS         The SMP callback function is registered successfully.
+  @retval EFI_ALREADY_STARTED A callback function is already registered on the same attribute
+                              opcode and attribute handle, when the Callback is not NULL.
+  @retval EFI_NOT_STARTED     A callback function is not registered on the same attribute opcode
+                              and attribute handle, when the Callback is NULL.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_LE_REGISTER_SMP_AUTH_CALLBACK) (
+  IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL  *This,
+  IN EFI_BLUETOOTH_LE_SMP_CALLBACK     Callback,
+  IN VOID                              *Context
+  );
+
+/**
+  Send user authentication/authorization to remote device.
+
+  The SendSmpAuthData() function sends user authentication/authorization to remote device. It
+  should be used to send these information after the caller gets the request data from the callback
+  function by RegisterSmpAuthCallback().
+
+  @param[in]  This            Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance.
+  @param[in]  BDAddr          Remote BluetoothLE device address.
+  @param[in]  EventDataType   Event data type in EFI_BLUETOOTH_LE_SMP_EVENT_DATA_TYPE.
+  @param[in]  DataSize        The size of Data in bytes, of the data buffer specified by Data.
+  @param[in]  Data            A pointer to the buffer of data that will be sent. The data format
+                              depends on the type of SMP event data being responded to.
+
+  @retval EFI_SUCCESS         The SMP authorization data is sent successfully.
+  @retval EFI_NOT_READY       SMP is not in the correct state to receive the auth data.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_LE_SEND_SMP_AUTH_DATA) (
+  IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL       *This,
+  IN BLUETOOTH_LE_ADDRESS                   *BDAddr,
+  IN EFI_BLUETOOTH_LE_SMP_EVENT_DATA_TYPE   EventDataType,
+  IN UINTN                                  DataSize,
+  IN VOID                                   *Data
+  );
+
+typedef enum {
+  // For local device only
+  EfiBluetoothSmpLocalIR, /* If Key hierarchy is supported */
+  EfiBluetoothSmpLocalER, /* If Key hierarchy is supported */
+  EfiBluetoothSmpLocalDHK, /* If Key hierarchy is supported. OPTIONAL */
+  // For peer specific
+  EfiBluetoothSmpKeysDistributed = 0x1000,
+  EfiBluetoothSmpKeySize,
+  EfiBluetoothSmpKeyType,
+  EfiBluetoothSmpPeerLTK,
+  EfiBluetoothSmpPeerIRK,
+  EfiBluetoothSmpPeerCSRK,
+  EfiBluetoothSmpPeerRand,
+  EfiBluetoothSmpPeerEDIV,
+  EfiBluetoothSmpPeerSignCounter,
+  EfiBluetoothSmpLocalLTK, /* If Key hierarchy not supported */
+  EfiBluetoothSmpLocalIRK, /* If Key hierarchy not supported */
+  EfiBluetoothSmpLocalCSRK, /* If Key hierarchy not supported */
+  EfiBluetoothSmpLocalSignCounter,
+  EfiBluetoothSmpLocalDIV,
+  EfiBluetoothSmpPeerAddressList,
+  EfiBluetoothSmpMax,
+} EFI_BLUETOOTH_LE_SMP_DATA_TYPE;
+
+/**
+  The callback function to get SMP data.
+
+  @param[in]      This            Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance.
+  @param[in]      Context         Data passed into callback function. This is optional parameter
+                                  and may be NULL.
+  @param[in]      BDAddr          Remote BluetoothLE device address. For Local device setting, it
+                                  should be NULL.
+  @param[in]      DataType        Data type in EFI_BLUETOOTH_LE_SMP_DATA_TYPE.
+  @param[in, out] DataSize        On input, indicates the size, in bytes, of the data buffer specified
+                                  by Data. On output, indicates the amount of data actually returned.
+  @param[out]     Data            A pointer to the buffer of data that will be returned.
+
+  @retval EFI_SUCCESS   The callback function complete successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI * EFI_BLUETOOTH_LE_CONFIG_SMP_GET_DATA_CALLBACK) (
+  IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL  *This,
+  IN VOID                              *Context,
+  IN BLUETOOTH_LE_ADDRESS              *BDAddr,
+  IN EFI_BLUETOOTH_LE_SMP_DATA_TYPE    DataType,
+  IN OUT UINTN                         *DataSize,
+  OUT VOID                             *Data
+  );
+
+/**
+  Register a callback function to get SMP related data.
+
+  The RegisterSmpGetDataCallback() function registers a callback function to get SMP related data.
+
+  @param[in]  This            Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance.
+  @param[in]  Callback        Callback function for SMP get data.
+  @param[in]  Context         Data passed into Callback function. This is optional parameter and may be NULL.
+
+  @retval EFI_SUCCESS         The SMP get data callback function is registered successfully.
+  @retval EFI_ALREADY_STARTED A callback function is already registered on the same attribute
+                              opcode and attribute handle, when the Callback is not NULL.
+  @retval EFI_NOT_STARTED     A callback function is not registered on the same attribute opcode
+                              and attribute handle, when the Callback is NULL
+**/
+typedef
+EFI_STATUS
+(EFIAPI * EFI_BLUETOOTH_LE_CONFIG_REGISTER_SMP_GET_DATA_CALLBACK) (
+  IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL              *This,
+  IN EFI_BLUETOOTH_LE_CONFIG_SMP_GET_DATA_CALLBACK Callback,
+  IN VOID                                          *Context
+  );
+
+/**
+  The callback function to set SMP data.
+
+  @param[in]  This                Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance.
+  @param[in]  Context             Data passed into callback function. This is optional parameter
+                                  and may be NULL.
+  @param[in]  BDAddr              Remote BluetoothLE device address.
+  @param[in]  DataType            Data type in EFI_BLUETOOTH_LE_SMP_DATA_TYPE.
+  @param[in]  DataSize            Indicates the size, in bytes, of the data buffer specified by Data.
+  @param[in]  Data                A pointer to the buffer of data.
+
+  @retval EFI_SUCCESS   The callback function complete successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI * EFI_BLUETOOTH_LE_CONFIG_SMP_SET_DATA_CALLBACK) (
+  IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL  *This,
+  IN VOID                              *Context,
+  IN BLUETOOTH_LE_ADDRESS              *BDAddr,
+  IN EFI_BLUETOOTH_LE_SMP_DATA_TYPE    Type,
+  IN UINTN                             DataSize,
+  IN VOID                              *Data
+  );
+
+/**
+  Register a callback function to set SMP related data.
+
+  The RegisterSmpSetDataCallback() function registers a callback function to set SMP related data.
+
+  @param[in]  This            Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance.
+  @param[in]  Callback        Callback function for SMP set data.
+  @param[in]  Context         Data passed into Callback function. This is optional parameter and may be NULL.
+
+  @retval EFI_SUCCESS         The SMP set data callback function is registered successfully.
+  @retval EFI_ALREADY_STARTED A callback function is already registered on the same attribute
+                              opcode and attribute handle, when the Callback is not NULL.
+  @retval EFI_NOT_STARTED     A callback function is not registered on the same attribute opcode
+                              and attribute handle, when the Callback is NULL
+**/
+typedef
+EFI_STATUS
+(EFIAPI * EFI_BLUETOOTH_LE_CONFIG_REGISTER_SMP_SET_DATA_CALLBACK) (
+  IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL              *This,
+  IN EFI_BLUETOOTH_LE_CONFIG_SMP_SET_DATA_CALLBACK Callback,
+  IN VOID                                          *Context
+  );
+
+/**
+  The callback function to hook connect complete event.
+
+  @param[in]  This                Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance.
+  @param[in]  Context             Data passed into callback function. This is optional parameter
+                                  and may be NULL.
+  @param[in]  CallbackType        The value defined in EFI_BLUETOOTH_CONNECT_COMPLETE_CALLBACK_TYPE.
+  @param[in]  BDAddr              Remote BluetoothLE device address.
+  @param[in]  InputBuffer         A pointer to the buffer of data that is input from callback caller.
+  @param[in]  InputBufferSize     Indicates the size, in bytes, of the data buffer specified by InputBuffer.
+
+  @retval EFI_SUCCESS   The callback function complete successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_CONNECT_COMPLETE_CALLBACK) (
+  IN  EFI_BLUETOOTH_LE_CONFIG_PROTOCOL                 *This,
+  IN  VOID                                             *Context,
+  IN  EFI_BLUETOOTH_CONNECT_COMPLETE_CALLBACK_TYPE     CallbackType,
+  IN  BLUETOOTH_LE_ADDRESS                             *BDAddr,
+  IN  VOID                                             *InputBuffer,
+  IN  UINTN                                            InputBufferSize
+  );
+
+/**
+  Register link connect complete callback function.
+
+  The RegisterLinkConnectCompleteCallback() function registers Bluetooth link connect
+  complete callback function. The Bluetooth Configuration driver may call
+  RegisterLinkConnectCompleteCallback() to register a callback function. During pairing,
+  Bluetooth bus driver must trigger this callback function to report device state, if it is registered.
+  Then Bluetooth Configuration driver will get information on device connection, according to
+  CallbackType defined by EFI_BLUETOOTH_CONNECT_COMPLETE_CALLBACK_TYPE
+
+  @param[in]  This            Pointer to the EFI_BLUETOOTH_LE_CONFIG_PROTOCOL instance.
+  @param[in]  Callback        The callback function. NULL means unregister.
+  @param[in]  Context         Data passed into Callback function. This is optional parameter and may be NULL.
+
+  @retval EFI_SUCCESS         The link connect complete callback function is registered successfully.
+  @retval EFI_ALREADY_STARTED A callback function is already registered on the same attribute
+                              opcode and attribute handle, when the Callback is not NULL.
+  @retval EFI_NOT_STARTED     A callback function is not registered on the same attribute opcode
+                              and attribute handle, when the Callback is NULL
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_BLUETOOTH_LE_CONFIG_REGISTER_CONNECT_COMPLETE_CALLBACK) (
+  IN EFI_BLUETOOTH_LE_CONFIG_PROTOCOL                        *This,
+  IN EFI_BLUETOOTH_LE_CONFIG_CONNECT_COMPLETE_CALLBACK       Callback,
+  IN VOID                                                    *Context
+  );
+
+///
+/// This protocol abstracts user interface configuration for BluetoothLe device.
+///
+struct _EFI_BLUETOOTH_LE_CONFIG_PROTOCOL {
+  EFI_BLUETOOTH_LE_CONFIG_INIT                               Init;
+  EFI_BLUETOOTH_LE_CONFIG_SCAN                               Scan;
+  EFI_BLUETOOTH_LE_CONFIG_CONNECT                            Connect;
+  EFI_BLUETOOTH_LE_CONFIG_DISCONNECT                         Disconnect;
+  EFI_BLUETOOTH_LE_CONFIG_GET_DATA                           GetData;
+  EFI_BLUETOOTH_LE_CONFIG_SET_DATA                           SetData;
+  EFI_BLUETOOTH_LE_CONFIG_GET_REMOTE_DATA                    GetRemoteData;
+  EFI_BLUETOOTH_LE_REGISTER_SMP_AUTH_CALLBACK                RegisterSmpAuthCallback;
+  EFI_BLUETOOTH_LE_SEND_SMP_AUTH_DATA                        SendSmpAuthData;
+  EFI_BLUETOOTH_LE_CONFIG_REGISTER_SMP_GET_DATA_CALLBACK     RegisterSmpGetDataCallback;
+  EFI_BLUETOOTH_LE_CONFIG_REGISTER_SMP_SET_DATA_CALLBACK     RegisterSmpSetDataCallback;
+  EFI_BLUETOOTH_LE_CONFIG_REGISTER_CONNECT_COMPLETE_CALLBACK RegisterLinkConnectCompleteCallback;
+};
+
+extern EFI_GUID gEfiBluetoothLeConfigProtocolGuid;
+
+#endif
+
diff --git a/MdePkg/Include/Protocol/BootManagerPolicy.h b/MdePkg/Include/Protocol/BootManagerPolicy.h
index f348e3f101da..42e90fdedeeb 100644
--- a/MdePkg/Include/Protocol/BootManagerPolicy.h
+++ b/MdePkg/Include/Protocol/BootManagerPolicy.h
@@ -4,14 +4,8 @@
   This protocol is used by EFI Applications to request the UEFI Boot Manager
   to connect devices using platform policy.
 
-  Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
 #ifndef __BOOT_MANAGER_POLICY_H__
@@ -53,7 +47,7 @@ typedef struct _EFI_BOOT_MANAGER_POLICY_PROTOCOL EFI_BOOT_MANAGER_POLICY_PROTOCO
                         system will be connected using the platforms EFI Boot
                         Manager policy.
   @param[in] Recursive  If TRUE, then ConnectController() is called recursively
-                        until the entire tree of controllers below the 
+                        until the entire tree of controllers below the
                         controller specified by DevicePath have been created.
                         If FALSE, then the tree of controllers is only expanded
                         one level. If DevicePath is NULL then Recursive is ignored.
@@ -61,7 +55,7 @@ typedef struct _EFI_BOOT_MANAGER_POLICY_PROTOCOL EFI_BOOT_MANAGER_POLICY_PROTOCO
   @retval EFI_SUCCESS            The DevicePath was connected.
   @retval EFI_NOT_FOUND          The DevicePath was not found.
   @retval EFI_NOT_FOUND          No driver was connected to DevicePath.
-  @retval EFI_SECURITY_VIOLATION The user has no permission to start UEFI device 
+  @retval EFI_SECURITY_VIOLATION The user has no permission to start UEFI device
                                  drivers on the DevicePath.
   @retval EFI_UNSUPPORTED        The current TPL is not TPL_APPLICATION.
 **/
@@ -80,7 +74,7 @@ EFI_STATUS
   Manager connect a class of devices.
 
   If Class is EFI_BOOT_MANAGER_POLICY_CONSOLE_GUID then the Boot Manager will
-  use platform policy to connect consoles. Some platforms may restrict the 
+  use platform policy to connect consoles. Some platforms may restrict the
   number of consoles connected as they attempt to fast boot, and calling
   ConnectDeviceClass() with a Class value of EFI_BOOT_MANAGER_POLICY_CONSOLE_GUID
   must connect the set of consoles that follow the Boot Manager platform policy,
@@ -98,7 +92,7 @@ EFI_STATUS
   application that called ConnectDeviceClass() may need to use the published
   protocols to establish the network connection. The Boot Manager can optionally
   have a policy to establish a network connection.
-  
+
   If Class is EFI_BOOT_MANAGER_POLICY_CONNECT_ALL_GUID then the Boot Manager
   will connect all UEFI drivers using the UEFI Boot Service
   EFI_BOOT_SERVICES.ConnectController(). If the Boot Manager has policy
@@ -115,7 +109,7 @@ EFI_STATUS
   @retval EFI_DEVICE_ERROR Devices were not connected due to an error.
   @retval EFI_NOT_FOUND    The Class is not supported by the platform.
   @retval EFI_UNSUPPORTED  The current TPL is not TPL_APPLICATION.
-**/        
+**/
 typedef
 EFI_STATUS
 (EFIAPI *EFI_BOOT_MANAGER_POLICY_CONNECT_DEVICE_CLASS)(
diff --git a/MdePkg/Include/Protocol/BusSpecificDriverOverride.h b/MdePkg/Include/Protocol/BusSpecificDriverOverride.h
index dcaeb9c53574..878458e9c8ea 100644
--- a/MdePkg/Include/Protocol/BusSpecificDriverOverride.h
+++ b/MdePkg/Include/Protocol/BusSpecificDriverOverride.h
@@ -6,14 +6,8 @@
   instance of this protocol for every PCI controller that has a PCI option ROM that contains one or
   more UEFI drivers. The protocol instance is attached to the handle of the PCI controller.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -34,14 +28,14 @@ typedef struct _EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL  EFI_BUS_SPECIFIC_DRIV
 // Prototypes for the Bus Specific Driver Override Protocol
 //
 
-/**                                                                   
+/**
   Uses a bus specific algorithm to retrieve a driver image handle for a controller.
-    
+
   @param  This                  A pointer to the EFI_BUS_SPECIFIC_DRIVER_
-                                OVERRIDE_PROTOCOL instance.              
+                                OVERRIDE_PROTOCOL instance.
   @param  DriverImageHandle     On input, a pointer to the previous driver image handle returned
-                                by GetDriver(). On output, a pointer to the next driver         
-                                image handle. Passing in a NULL, will return the first driver   
+                                by GetDriver(). On output, a pointer to the next driver
+                                image handle. Passing in a NULL, will return the first driver
                                 image handle.
 
   @retval EFI_SUCCESS           A bus specific override driver is returned in DriverImageHandle.
diff --git a/MdePkg/Include/Protocol/Capsule.h b/MdePkg/Include/Protocol/Capsule.h
index e35035da6a29..0122b6ebcdf4 100644
--- a/MdePkg/Include/Protocol/Capsule.h
+++ b/MdePkg/Include/Protocol/Capsule.h
@@ -1,23 +1,17 @@
 /** @file
   Capsule Architectural Protocol as defined in PI1.0a Specification VOLUME 2 DXE
 
-  The DXE Driver that produces this protocol must be a runtime driver. 
-  The driver is responsible for initializing the CapsuleUpdate() and 
-  QueryCapsuleCapabilities() fields of the UEFI Runtime Services Table. 
-  After the two fields of the UEFI Runtime Services Table have been initialized, 
-  the driver must install the EFI_CAPSULE_ARCH_PROTOCOL_GUID on a new handle 
-  with a NULL interface pointer. The installation of this protocol informs 
-  the DXE Foundation that the Capsule related services are now available and 
+  The DXE Driver that produces this protocol must be a runtime driver.
+  The driver is responsible for initializing the CapsuleUpdate() and
+  QueryCapsuleCapabilities() fields of the UEFI Runtime Services Table.
+  After the two fields of the UEFI Runtime Services Table have been initialized,
+  the driver must install the EFI_CAPSULE_ARCH_PROTOCOL_GUID on a new handle
+  with a NULL interface pointer. The installation of this protocol informs
+  the DXE Foundation that the Capsule related services are now available and
   that the DXE Foundation must update the 32-bit CRC of the UEFI Runtime Services Table.
 
-Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/Protocol/ComponentName.h b/MdePkg/Include/Protocol/ComponentName.h
index cdd87fce3157..91344fc576c6 100644
--- a/MdePkg/Include/Protocol/ComponentName.h
+++ b/MdePkg/Include/Protocol/ComponentName.h
@@ -1,16 +1,10 @@
 /** @file
   EFI Component Name Protocol as defined in the EFI 1.1 specification.
-  This protocol is used to retrieve user readable names of EFI Drivers 
+  This protocol is used to retrieve user readable names of EFI Drivers
   and controllers managed by EFI Drivers.
 
-Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -110,7 +104,7 @@ EFI_STATUS
   );
 
 ///
-/// This protocol is used to retrieve user readable names of drivers 
+/// This protocol is used to retrieve user readable names of drivers
 /// and controllers managed by UEFI Drivers.
 ///
 struct _EFI_COMPONENT_NAME_PROTOCOL {
@@ -119,7 +113,7 @@ struct _EFI_COMPONENT_NAME_PROTOCOL {
   ///
   /// A Null-terminated ASCII string that contains one or more
   /// ISO 639-2 language codes. This is the list of language codes
-  /// that this protocol supports.  
+  /// that this protocol supports.
   ///
   CHAR8                                   *SupportedLanguages;
 };
diff --git a/MdePkg/Include/Protocol/ComponentName2.h b/MdePkg/Include/Protocol/ComponentName2.h
index d005b02b873f..3d201501708a 100644
--- a/MdePkg/Include/Protocol/ComponentName2.h
+++ b/MdePkg/Include/Protocol/ComponentName2.h
@@ -1,16 +1,10 @@
 /** @file
   UEFI Component Name 2 Protocol as defined in the UEFI 2.1 specification.
-  This protocol is used to retrieve user readable names of drivers 
+  This protocol is used to retrieve user readable names of drivers
   and controllers managed by UEFI Drivers.
 
-  Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -32,7 +26,7 @@ typedef struct _EFI_COMPONENT_NAME2_PROTOCOL  EFI_COMPONENT_NAME2_PROTOCOL;
 
   @param  This       A pointer to the
                      EFI_COMPONENT_NAME2_PROTOCOL instance.
-  
+
   @param  Language   A pointer to a Null-terminated ASCII string
                      array indicating the language. This is the
                      language of the driver name that the caller
@@ -42,7 +36,7 @@ typedef struct _EFI_COMPONENT_NAME2_PROTOCOL  EFI_COMPONENT_NAME2_PROTOCOL;
                      driver is up to the driver writer. Language
                      is specified in RFC 4646 language code
                      format.
-  
+
   @param  DriverName A pointer to the string to return.
                      This string is the name of the
                      driver specified by This in the language
@@ -52,11 +46,11 @@ typedef struct _EFI_COMPONENT_NAME2_PROTOCOL  EFI_COMPONENT_NAME2_PROTOCOL;
                                 Driver specified by This and the
                                 language specified by Language
                                 was returned in DriverName.
-  
+
   @retval EFI_INVALID_PARAMETER Language is NULL.
-  
+
   @retval EFI_INVALID_PARAMETER DriverName is NULL.
-  
+
   @retval EFI_UNSUPPORTED       The driver specified by This
                                 does not support the language
                                 specified by Language.
@@ -150,7 +144,7 @@ EFI_STATUS
   );
 
 ///
-/// This protocol is used to retrieve user readable names of drivers 
+/// This protocol is used to retrieve user readable names of drivers
 /// and controllers managed by UEFI Drivers.
 ///
 struct _EFI_COMPONENT_NAME2_PROTOCOL {
@@ -162,7 +156,7 @@ struct _EFI_COMPONENT_NAME2_PROTOCOL {
   /// supported language codes. This is the list of language codes that
   /// this protocol supports. The number of languages supported by a
   /// driver is up to the driver writer. SupportedLanguages is
-  /// specified in RFC 4646 format.  
+  /// specified in RFC 4646 format.
   ///
   CHAR8                                    *SupportedLanguages;
 };
diff --git a/MdePkg/Include/Protocol/Cpu.h b/MdePkg/Include/Protocol/Cpu.h
index cfb2e7570155..72e061252326 100644
--- a/MdePkg/Include/Protocol/Cpu.h
+++ b/MdePkg/Include/Protocol/Cpu.h
@@ -3,14 +3,8 @@
 
   This code abstracts the DXE core from processor implementation details.
 
-  Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -61,14 +55,14 @@ VOID
   );
 
 /**
-  This function flushes the range of addresses from Start to Start+Length 
-  from the processor's data cache. If Start is not aligned to a cache line 
-  boundary, then the bytes before Start to the preceding cache line boundary 
-  are also flushed. If Start+Length is not aligned to a cache line boundary, 
-  then the bytes past Start+Length to the end of the next cache line boundary 
-  are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be 
-  supported. If the data cache is fully coherent with all DMA operations, then 
-  this function can just return EFI_SUCCESS. If the processor does not support 
+  This function flushes the range of addresses from Start to Start+Length
+  from the processor's data cache. If Start is not aligned to a cache line
+  boundary, then the bytes before Start to the preceding cache line boundary
+  are also flushed. If Start+Length is not aligned to a cache line boundary,
+  then the bytes past Start+Length to the end of the next cache line boundary
+  are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be
+  supported. If the data cache is fully coherent with all DMA operations, then
+  this function can just return EFI_SUCCESS. If the processor does not support
   flushing a range of the data cache, then the entire data cache can be flushed.
 
   @param  This             The EFI_CPU_ARCH_PROTOCOL instance.
@@ -98,7 +92,7 @@ EFI_STATUS
 
 
 /**
-  This function enables interrupt processing by the processor. 
+  This function enables interrupt processing by the processor.
 
   @param  This             The EFI_CPU_ARCH_PROTOCOL instance.
 
@@ -130,8 +124,8 @@ EFI_STATUS
 
 
 /**
-  This function retrieves the processor's current interrupt state a returns it in 
-  State. If interrupts are currently enabled, then TRUE is returned. If interrupts 
+  This function retrieves the processor's current interrupt state a returns it in
+  State. If interrupts are currently enabled, then TRUE is returned. If interrupts
   are currently disabled, then FALSE is returned.
 
   @param  This             The EFI_CPU_ARCH_PROTOCOL instance.
@@ -152,9 +146,9 @@ EFI_STATUS
 
 /**
   This function generates an INIT on the processor. If this function succeeds, then the
-  processor will be reset, and control will not be returned to the caller. If InitType is 
-  not supported by this processor, or the processor cannot programmatically generate an 
-  INIT without help from external hardware, then EFI_UNSUPPORTED is returned. If an error 
+  processor will be reset, and control will not be returned to the caller. If InitType is
+  not supported by this processor, or the processor cannot programmatically generate an
+  INIT without help from external hardware, then EFI_UNSUPPORTED is returned. If an error
   occurs attempting to generate an INIT, then EFI_DEVICE_ERROR is returned.
 
   @param  This             The EFI_CPU_ARCH_PROTOCOL instance.
@@ -175,9 +169,9 @@ EFI_STATUS
 
 
 /**
-  This function registers and enables the handler specified by InterruptHandler for a processor 
-  interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the 
-  handler for the processor interrupt or exception type specified by InterruptType is uninstalled. 
+  This function registers and enables the handler specified by InterruptHandler for a processor
+  interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the
+  handler for the processor interrupt or exception type specified by InterruptType is uninstalled.
   The installed handler is called once for each processor interrupt or exception.
 
   @param  This             The EFI_CPU_ARCH_PROTOCOL instance.
@@ -280,17 +274,17 @@ struct _EFI_CPU_ARCH_PROTOCOL {
   EFI_CPU_GET_TIMER_VALUE             GetTimerValue;
   EFI_CPU_SET_MEMORY_ATTRIBUTES       SetMemoryAttributes;
   ///
-  /// The number of timers that are available in a processor. The value in this 
-  /// field is a constant that must not be modified after the CPU Architectural 
+  /// The number of timers that are available in a processor. The value in this
+  /// field is a constant that must not be modified after the CPU Architectural
   /// Protocol is installed. All consumers must treat this as a read-only field.
   ///
   UINT32                              NumberOfTimers;
   ///
-  /// The size, in bytes, of the alignment required for DMA buffer allocations. 
-  /// This is typically the size of the largest data cache line in the platform. 
-  /// The value in this field is a constant that must not be modified after the 
-  /// CPU Architectural Protocol is installed. All consumers must treat this as 
-  /// a read-only field.  
+  /// The size, in bytes, of the alignment required for DMA buffer allocations.
+  /// This is typically the size of the largest data cache line in the platform.
+  /// The value in this field is a constant that must not be modified after the
+  /// CPU Architectural Protocol is installed. All consumers must treat this as
+  /// a read-only field.
   ///
   UINT32                              DmaBufferAlignment;
 };
diff --git a/MdePkg/Include/Protocol/CpuIo2.h b/MdePkg/Include/Protocol/CpuIo2.h
index 49fb470713e7..173b00d5c3a4 100644
--- a/MdePkg/Include/Protocol/CpuIo2.h
+++ b/MdePkg/Include/Protocol/CpuIo2.h
@@ -1,28 +1,22 @@
 /** @file
   This files describes the CPU I/O 2 Protocol.
-  
+
   This protocol provides an I/O abstraction for a system processor. This protocol
   is used by a PCI root bridge I/O driver to perform memory-mapped I/O and I/O transactions.
   The I/O or memory primitives can be used by the consumer of the protocol to materialize
   bus-specific configuration cycles, such as the transitional configuration address and data
-  ports for PCI. Only drivers that require direct access to the entire system should use this 
-  protocol. 
-  
+  ports for PCI. Only drivers that require direct access to the entire system should use this
+  protocol.
+
   Note: This is a boot-services only protocol and it may not be used by runtime drivers after
   ExitBootServices(). It is different from the Framework CPU I/O Protocol, which is a runtime
   protocol and can be used by runtime drivers after ExitBootServices().
 
-  Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
-  This Protocol is defined in UEFI Platform Initialization Specification 1.2 
+  This Protocol is defined in UEFI Platform Initialization Specification 1.2
   Volume 5: Standards
 
 **/
@@ -57,35 +51,35 @@ typedef enum {
 } EFI_CPU_IO_PROTOCOL_WIDTH;
 
 /**
-  Enables a driver to access registers in the PI CPU I/O space. 
+  Enables a driver to access registers in the PI CPU I/O space.
 
-  The Io.Read() and Io.Write() functions enable a driver to access PCI controller 
-  registers in the PI CPU I/O space. 
+  The Io.Read() and Io.Write() functions enable a driver to access PCI controller
+  registers in the PI CPU I/O space.
 
-  The I/O operations are carried out exactly as requested. The caller is responsible 
-  for satisfying any alignment and I/O width restrictions that a PI System on a 
-  platform might require. For example on some platforms, width requests of 
-  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will 
+  The I/O operations are carried out exactly as requested. The caller is responsible
+  for satisfying any alignment and I/O width restrictions that a PI System on a
+  platform might require. For example on some platforms, width requests of
+  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
   be handled by the driver.
-  
-  If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, 
-  or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for 
+
+  If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,
+  or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for
   each of the Count operations that is performed.
-  
-  If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, 
-  EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is 
-  incremented for each of the Count operations that is performed. The read or 
+
+  If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,
+  EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is
+  incremented for each of the Count operations that is performed. The read or
   write operation is performed Count times on the same Address.
-  
-  If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, 
-  EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is 
-  incremented for each of the Count operations that is performed. The read or 
+
+  If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,
+  EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is
+  incremented for each of the Count operations that is performed. The read or
   write operation is performed Count times from the first element of Buffer.
 
   @param[in]       This     A pointer to the EFI_CPU_IO2_PROTOCOL instance.
   @param[in]       Width    Signifies the width of the I/O or Memory operation.
-  @param[in]       Address  The base address of the I/O operation. 
-  @param[in]       Count    The number of I/O operations to perform. The number 
+  @param[in]       Address  The base address of the I/O operation.
+  @param[in]       Count    The number of I/O operations to perform. The number
                             of bytes moved is Width size * Count, starting at Address.
   @param[in, out]  Buffer   For read operations, the destination buffer to store the results.
                             For write operations, the source buffer from which to write data.
@@ -94,7 +88,7 @@ typedef enum {
   @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.
   @retval EFI_INVALID_PARAMETER  Buffer is NULL.
   @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.
-  @retval EFI_UNSUPPORTED        The address range specified by Address, Width, 
+  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,
                                  and Count is not valid for this PI system.
 
 **/
diff --git a/MdePkg/Include/Protocol/DebugPort.h b/MdePkg/Include/Protocol/DebugPort.h
index ba14591107e7..d3aa3bbf2a4f 100644
--- a/MdePkg/Include/Protocol/DebugPort.h
+++ b/MdePkg/Include/Protocol/DebugPort.h
@@ -1,17 +1,11 @@
 /** @file
-  
+
   The file defines the EFI Debugport protocol.
   This protocol is used by debug agent to communicate with the
   remote debug host.
-  
-  Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -35,14 +29,14 @@ typedef struct _EFI_DEBUGPORT_PROTOCOL EFI_DEBUGPORT_PROTOCOL;
 // DebugPort member functions
 //
 
-/**                                                                 
+/**
   Resets the debugport.
-    
+
   @param  This                  A pointer to the EFI_DEBUGPORT_PROTOCOL instance.
-                                
+
   @retval EFI_SUCCESS           The debugport device was reset and is in usable state.
   @retval EFI_DEVICE_ERROR      The debugport device could not be reset and is unusable.
-                                   
+
 **/
 typedef
 EFI_STATUS
@@ -50,19 +44,19 @@ EFI_STATUS
   IN EFI_DEBUGPORT_PROTOCOL               *This
   );
 
-/**                                                                 
+/**
   Writes data to the debugport.
-    
+
   @param  This                  A pointer to the EFI_DEBUGPORT_PROTOCOL instance.
   @param  Timeout               The number of microseconds to wait before timing out a write operation.
   @param  BufferSize            On input, the requested number of bytes of data to write. On output, the
                                 number of bytes of data actually written.
-  @param  Buffer                A pointer to a buffer containing the data to write.                                
-                                  
+  @param  Buffer                A pointer to a buffer containing the data to write.
+
   @retval EFI_SUCCESS           The data was written.
   @retval EFI_DEVICE_ERROR      The device reported an error.
   @retval EFI_TIMEOUT           The data write was stopped due to a timeout.
-                                   
+
 **/
 typedef
 EFI_STATUS
@@ -73,20 +67,20 @@ EFI_STATUS
   IN VOID                                 *Buffer
   );
 
-/**                                                                 
+/**
   Reads data from the debugport.
-    
+
   @param  This                  A pointer to the EFI_DEBUGPORT_PROTOCOL instance.
   @param  Timeout               The number of microseconds to wait before timing out a read operation.
   @param  BufferSize            On input, the requested number of bytes of data to read. On output, the
                                 number of bytes of data actually number of bytes
                                 of data read and returned in Buffer.
   @param  Buffer                A pointer to a buffer into which the data read will be saved.
-                                  
+
   @retval EFI_SUCCESS           The data was read.
   @retval EFI_DEVICE_ERROR      The device reported an error.
   @retval EFI_TIMEOUT           The operation was stopped due to a timeout or overrun.
-                                   
+
 **/
 typedef
 EFI_STATUS
@@ -97,15 +91,15 @@ EFI_STATUS
   OUT VOID                                *Buffer
   );
 
-/**                                                                 
+/**
   Checks to see if any data is available to be read from the debugport device.
-    
+
   @param  This                  A pointer to the EFI_DEBUGPORT_PROTOCOL instance.
-                                  
+
   @retval EFI_SUCCESS           At least one byte of data is available to be read.
   @retval EFI_DEVICE_ERROR      The debugport device is not functioning correctly.
   @retval EFI_NOT_READY         No data is available to be read.
-                                   
+
 **/
 typedef
 EFI_STATUS
diff --git a/MdePkg/Include/Protocol/DebugSupport.h b/MdePkg/Include/Protocol/DebugSupport.h
index 80f87061bd0e..3ab78ee1baf3 100644
--- a/MdePkg/Include/Protocol/DebugSupport.h
+++ b/MdePkg/Include/Protocol/DebugSupport.h
@@ -5,16 +5,11 @@
   The DebugSupport protocol is used by source level debuggers to abstract the
   processor and handle context save and restore operations.
 
-Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
 Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
 
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -183,7 +178,7 @@ typedef struct {
   UINT8   Xmm6[16];
   UINT8   Xmm7[16];
   //
-  // NOTE: UEFI 2.0 spec definition as follows. 
+  // NOTE: UEFI 2.0 spec definition as follows.
   //
   UINT8   Reserved11[14 * 16];
 } EFI_FX_SAVE_STATE_X64;
@@ -609,6 +604,59 @@ typedef struct {
   UINT64  FAR;  // Fault Address Register
 } EFI_SYSTEM_CONTEXT_AARCH64;
 
+///
+/// RISC-V processor exception types.
+///
+#define EXCEPT_RISCV_INST_MISALIGNED              0
+#define EXCEPT_RISCV_INST_ACCESS_FAULT            1
+#define EXCEPT_RISCV_ILLEGAL_INST                 2
+#define EXCEPT_RISCV_BREAKPOINT                   3
+#define EXCEPT_RISCV_LOAD_ADDRESS_MISALIGNED      4
+#define EXCEPT_RISCV_LOAD_ACCESS_FAULT            5
+#define EXCEPT_RISCV_STORE_AMO_ADDRESS_MISALIGNED 6
+#define EXCEPT_RISCV_STORE_AMO_ACCESS_FAULT       7
+#define EXCEPT_RISCV_ENV_CALL_FROM_UMODE          8
+#define EXCEPT_RISCV_ENV_CALL_FROM_SMODE          9
+#define EXCEPT_RISCV_ENV_CALL_FROM_HMODE          10
+#define EXCEPT_RISCV_ENV_CALL_FROM_MMODE          11
+
+#define EXCEPT_RISCV_SOFTWARE_INT       0x0
+#define EXCEPT_RISCV_TIMER_INT          0x1
+
+typedef struct {
+  UINT64  X0;
+  UINT64  X1;
+  UINT64  X2;
+  UINT64  X3;
+  UINT64  X4;
+  UINT64  X5;
+  UINT64  X6;
+  UINT64  X7;
+  UINT64  X8;
+  UINT64  X9;
+  UINT64  X10;
+  UINT64  X11;
+  UINT64  X12;
+  UINT64  X13;
+  UINT64  X14;
+  UINT64  X15;
+  UINT64  X16;
+  UINT64  X17;
+  UINT64  X18;
+  UINT64  X19;
+  UINT64  X20;
+  UINT64  X21;
+  UINT64  X22;
+  UINT64  X23;
+  UINT64  X24;
+  UINT64  X25;
+  UINT64  X26;
+  UINT64  X27;
+  UINT64  X28;
+  UINT64  X29;
+  UINT64  X30;
+  UINT64  X31;
+} EFI_SYSTEM_CONTEXT_RISCV64;
 
 ///
 /// Universal EFI_SYSTEM_CONTEXT definition.
@@ -620,18 +668,19 @@ typedef union {
   EFI_SYSTEM_CONTEXT_IPF  *SystemContextIpf;
   EFI_SYSTEM_CONTEXT_ARM  *SystemContextArm;
   EFI_SYSTEM_CONTEXT_AARCH64  *SystemContextAArch64;
+  EFI_SYSTEM_CONTEXT_RISCV64  *SystemContextRiscV64;
 } EFI_SYSTEM_CONTEXT;
 
 //
 // DebugSupport callback function prototypes
 //
 
-/**                                                                 
+/**
   Registers and enables an exception callback function for the specified exception.
-    
+
   @param  ExceptionType         Exception types in EBC, IA-32, x64, or IPF.
   @param  SystemContext         Exception content.
-                                   
+
 **/
 typedef
 VOID
@@ -640,11 +689,11 @@ VOID
   IN OUT EFI_SYSTEM_CONTEXT               SystemContext
   );
 
-/**                                                                 
+/**
   Registers and enables the on-target debug agent's periodic entry point.
-      
+
   @param  SystemContext         Exception content.
-                                   
+
 **/
 typedef
 VOID
@@ -669,16 +718,16 @@ typedef enum {
 // DebugSupport member function definitions
 //
 
-/**                                                                 
+/**
   Returns the maximum value that may be used for the ProcessorIndex parameter in
-  RegisterPeriodicCallback() and RegisterExceptionCallback().                   
-    
+  RegisterPeriodicCallback() and RegisterExceptionCallback().
+
   @param  This                  A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.
   @param  MaxProcessorIndex     Pointer to a caller-allocated UINTN in which the maximum supported
-                                processor index is returned.                                      
-                                
-  @retval EFI_SUCCESS           The function completed successfully.  
-                                   
+                                processor index is returned.
+
+  @retval EFI_SUCCESS           The function completed successfully.
+
 **/
 typedef
 EFI_STATUS
@@ -687,20 +736,20 @@ EFI_STATUS
   OUT UINTN                              *MaxProcessorIndex
   );
 
-/**                                                                 
+/**
   Registers a function to be called back periodically in interrupt context.
-    
+
   @param  This                  A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.
   @param  ProcessorIndex        Specifies which processor the callback function applies to.
   @param  PeriodicCallback      A pointer to a function of type PERIODIC_CALLBACK that is the main
                                 periodic entry point of the debug agent.
-                                
-  @retval EFI_SUCCESS           The function completed successfully.  
+
+  @retval EFI_SUCCESS           The function completed successfully.
   @retval EFI_ALREADY_STARTED   Non-NULL PeriodicCallback parameter when a callback
-                                function was previously registered.                
-  @retval EFI_OUT_OF_RESOURCES  System has insufficient memory resources to register new callback                               
-                                function.                                                           
-                                
+                                function was previously registered.
+  @retval EFI_OUT_OF_RESOURCES  System has insufficient memory resources to register new callback
+                                function.
+
 **/
 typedef
 EFI_STATUS
@@ -710,21 +759,21 @@ EFI_STATUS
   IN EFI_PERIODIC_CALLBACK               PeriodicCallback
   );
 
-/**                                                                 
+/**
   Registers a function to be called when a given processor exception occurs.
-    
+
   @param  This                  A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.
   @param  ProcessorIndex        Specifies which processor the callback function applies to.
   @param  ExceptionCallback     A pointer to a function of type EXCEPTION_CALLBACK that is called
-                                when the processor exception specified by ExceptionType occurs.  
-  @param  ExceptionType         Specifies which processor exception to hook.                       
-                                
-  @retval EFI_SUCCESS           The function completed successfully.  
+                                when the processor exception specified by ExceptionType occurs.
+  @param  ExceptionType         Specifies which processor exception to hook.
+
+  @retval EFI_SUCCESS           The function completed successfully.
   @retval EFI_ALREADY_STARTED   Non-NULL PeriodicCallback parameter when a callback
-                                function was previously registered.                
-  @retval EFI_OUT_OF_RESOURCES  System has insufficient memory resources to register new callback                               
-                                function.                                                           
-                                
+                                function was previously registered.
+  @retval EFI_OUT_OF_RESOURCES  System has insufficient memory resources to register new callback
+                                function.
+
 **/
 typedef
 EFI_STATUS
@@ -735,18 +784,18 @@ EFI_STATUS
   IN EFI_EXCEPTION_TYPE                  ExceptionType
   );
 
-/**                                                                 
+/**
   Invalidates processor instruction cache for a memory range. Subsequent execution in this range
-  causes a fresh memory fetch to retrieve code to be executed.                                  
-    
+  causes a fresh memory fetch to retrieve code to be executed.
+
   @param  This                  A pointer to the EFI_DEBUG_SUPPORT_PROTOCOL instance.
   @param  ProcessorIndex        Specifies which processor's instruction cache is to be invalidated.
-  @param  Start                 Specifies the physical base of the memory range to be invalidated.                                
+  @param  Start                 Specifies the physical base of the memory range to be invalidated.
   @param  Length                Specifies the minimum number of bytes in the processor's instruction
-                                cache to invalidate.                                                 
-                                
-  @retval EFI_SUCCESS           The function completed successfully.  
-                                
+                                cache to invalidate.
+
+  @retval EFI_SUCCESS           The function completed successfully.
+
 **/
 typedef
 EFI_STATUS
@@ -758,8 +807,8 @@ EFI_STATUS
   );
 
 ///
-/// This protocol provides the services to allow the debug agent to register 
-/// callback functions that are called either periodically or when specific 
+/// This protocol provides the services to allow the debug agent to register
+/// callback functions that are called either periodically or when specific
 /// processor exceptions occur.
 ///
 struct _EFI_DEBUG_SUPPORT_PROTOCOL {
@@ -775,4 +824,4 @@ struct _EFI_DEBUG_SUPPORT_PROTOCOL {
 
 extern EFI_GUID gEfiDebugSupportProtocolGuid;
 
-#endif 
+#endif
diff --git a/MdePkg/Include/Protocol/Decompress.h b/MdePkg/Include/Protocol/Decompress.h
index 965b7d2f45ae..9ca3e14b5ab0 100644
--- a/MdePkg/Include/Protocol/Decompress.h
+++ b/MdePkg/Include/Protocol/Decompress.h
@@ -1,14 +1,8 @@
 /** @file
   The Decompress Protocol Interface as defined in UEFI spec
 
-  Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -23,16 +17,16 @@
 typedef struct _EFI_DECOMPRESS_PROTOCOL  EFI_DECOMPRESS_PROTOCOL;
 
 /**
-  The GetInfo() function retrieves the size of the uncompressed buffer 
-  and the temporary scratch buffer required to decompress the buffer 
+  The GetInfo() function retrieves the size of the uncompressed buffer
+  and the temporary scratch buffer required to decompress the buffer
   specified by Source and SourceSize.  If the size of the uncompressed
-  buffer or the size of the scratch buffer cannot be determined from 
-  the compressed data specified by Source and SourceData, then 
+  buffer or the size of the scratch buffer cannot be determined from
+  the compressed data specified by Source and SourceData, then
   EFI_INVALID_PARAMETER is returned.  Otherwise, the size of the uncompressed
-  buffer is returned in DestinationSize, the size of the scratch buffer is 
+  buffer is returned in DestinationSize, the size of the scratch buffer is
   returned in ScratchSize, and EFI_SUCCESS is returned.
 
-  The GetInfo() function does not have a scratch buffer available to perform 
+  The GetInfo() function does not have a scratch buffer available to perform
   a thorough checking of the validity of the source data. It just retrieves
   the 'Original Size' field from the beginning bytes of the source data and
   output it as DestinationSize.  And ScratchSize is specific to the decompression
@@ -68,15 +62,15 @@ EFI_STATUS
 /**
   The Decompress() function extracts decompressed data to its original form.
 
-  This protocol is designed so that the decompression algorithm can be 
-  implemented without using any memory services.  As a result, the 
-  Decompress() function is not allowed to call AllocatePool() or 
-  AllocatePages() in its implementation.  It is the caller's responsibility 
+  This protocol is designed so that the decompression algorithm can be
+  implemented without using any memory services.  As a result, the
+  Decompress() function is not allowed to call AllocatePool() or
+  AllocatePages() in its implementation.  It is the caller's responsibility
   to allocate and free the Destination and Scratch buffers.
 
-  If the compressed source data specified by Source and SourceSize is 
-  successfully decompressed into Destination, then EFI_SUCCESS is returned.  
-  If the compressed source data specified by Source and SourceSize is not in 
+  If the compressed source data specified by Source and SourceSize is
+  successfully decompressed into Destination, then EFI_SUCCESS is returned.
+  If the compressed source data specified by Source and SourceSize is not in
   a valid compressed data format, then EFI_INVALID_PARAMETER is returned.
 
   @param  This            A pointer to the EFI_DECOMPRESS_PROTOCOL instance.
@@ -87,7 +81,7 @@ EFI_STATUS
   @param  DestinationSize The size of destination buffer. The size of destination
                           buffer needed is obtained from GetInfo().
   @param  Scratch         A temporary scratch buffer that is used to perform the
-                          decompression.          
+                          decompression.
   @param  ScratchSize     The size of scratch buffer. The size of scratch buffer needed
                           is obtained from GetInfo().
 
diff --git a/MdePkg/Include/Protocol/DeferredImageLoad.h b/MdePkg/Include/Protocol/DeferredImageLoad.h
index 4d1bbf0ed402..7161ce02fe3c 100644
--- a/MdePkg/Include/Protocol/DeferredImageLoad.h
+++ b/MdePkg/Include/Protocol/DeferredImageLoad.h
@@ -1,19 +1,13 @@
 /** @file
   UEFI 2.2 Deferred Image Load Protocol definition.
 
-  This protocol returns information about images whose load was denied because of security 
-  considerations. This information can be used by the Boot Manager or another agent to reevaluate the 
-  images when the current security profile has been changed, such as when the current user profile 
+  This protocol returns information about images whose load was denied because of security
+  considerations. This information can be used by the Boot Manager or another agent to reevaluate the
+  images when the current security profile has been changed, such as when the current user profile
   changes. There can be more than one instance of this protocol installed.
 
-  Copyright (c) 2009, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -33,28 +27,28 @@ typedef struct _EFI_DEFERRED_IMAGE_LOAD_PROTOCOL  EFI_DEFERRED_IMAGE_LOAD_PROTOC
 /**
   Returns information about a deferred image.
 
-  This function returns information about a single deferred image. The deferred images are numbered 
-  consecutively, starting with 0.  If there is no image which corresponds to ImageIndex, then 
-  EFI_NOT_FOUND is returned. All deferred images may be returned by iteratively calling this 
+  This function returns information about a single deferred image. The deferred images are numbered
+  consecutively, starting with 0.  If there is no image which corresponds to ImageIndex, then
+  EFI_NOT_FOUND is returned. All deferred images may be returned by iteratively calling this
   function until EFI_NOT_FOUND is returned.
-  Image may be NULL and ImageSize set to 0 if the decision to defer execution was made because 
+  Image may be NULL and ImageSize set to 0 if the decision to defer execution was made because
   of the location of the executable image rather than its actual contents.  record handle until
-  there are no more, at which point UserInfo will point to NULL. 
+  there are no more, at which point UserInfo will point to NULL.
 
   @param[in]  This               Points to this instance of the EFI_DEFERRED_IMAGE_LOAD_PROTOCOL.
   @param[in]  ImageIndex         Zero-based index of the deferred index.
-  @param[out] ImageDevicePath    On return, points to a pointer to the device path of the image. 
-                                 The device path should not be freed by the caller. 
-  @param[out] Image              On return, points to the first byte of the image or NULL if the  
-                                 image is not available. The image should not be freed by the caller 
-                                 unless LoadImage() has been called successfully.  
+  @param[out] ImageDevicePath    On return, points to a pointer to the device path of the image.
+                                 The device path should not be freed by the caller.
+  @param[out] Image              On return, points to the first byte of the image or NULL if the
+                                 image is not available. The image should not be freed by the caller
+                                 unless LoadImage() has been called successfully.
   @param[out] ImageSize          On return, the size of the image, or 0 if the image is not available.
-  @param[out] BootOption         On return, points to TRUE if the image was intended as a boot option 
-                                 or FALSE if it was not intended as a boot option. 
- 
+  @param[out] BootOption         On return, points to TRUE if the image was intended as a boot option
+                                 or FALSE if it was not intended as a boot option.
+
   @retval EFI_SUCCESS            Image information returned successfully.
   @retval EFI_NOT_FOUND          ImageIndex does not refer to a valid image.
-  @retval EFI_INVALID_PARAMETER  ImageDevicePath is NULL or Image is NULL or ImageSize is NULL or 
+  @retval EFI_INVALID_PARAMETER  ImageDevicePath is NULL or Image is NULL or ImageSize is NULL or
                                  BootOption is NULL.
 **/
 typedef
diff --git a/MdePkg/Include/Protocol/DeviceIo.h b/MdePkg/Include/Protocol/DeviceIo.h
index d84a6202effd..7d52f1238bea 100644
--- a/MdePkg/Include/Protocol/DeviceIo.h
+++ b/MdePkg/Include/Protocol/DeviceIo.h
@@ -4,14 +4,8 @@
   Device IO is used to abstract hardware access to devices. It includes
   memory mapped IO, IO, PCI Config space, and DMA.
 
-  Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -27,16 +21,16 @@ typedef struct _EFI_DEVICE_IO_PROTOCOL EFI_DEVICE_IO_PROTOCOL;
 
 ///
 /// Protocol GUID name defined in EFI1.1.
-/// 
+///
 #define DEVICE_IO_PROTOCOL  EFI_DEVICE_IO_PROTOCOL_GUID
 
 ///
 /// Protocol defined in EFI1.1.
-/// 
+///
 typedef EFI_DEVICE_IO_PROTOCOL  EFI_DEVICE_IO_INTERFACE;
 
 ///
-/// Device IO Access Width 
+/// Device IO Access Width
 ///
 typedef enum {
   IO_UINT8  = 0,
@@ -44,7 +38,7 @@ typedef enum {
   IO_UINT32 = 2,
   IO_UINT64 = 3,
   //
-  // Below enumerations are added in "Extensible Firmware Interface Specification, 
+  // Below enumerations are added in "Extensible Firmware Interface Specification,
   // Version 1.10, Specification Update, Version 001".
   //
   MMIO_COPY_UINT8  = 4,
@@ -53,23 +47,23 @@ typedef enum {
   MMIO_COPY_UINT64 = 7
 } EFI_IO_WIDTH;
 
-/**                                                                 
+/**
   Enables a driver to access device registers in the appropriate memory or I/O space.
-    
+
   @param  This                  A pointer to the EFI_DEVICE_IO_INTERFACE instance.
-  @param  Width                 Signifies the width of the I/O operations.                                                                   
-  @param  Address               The base address of the I/O operations. 
+  @param  Width                 Signifies the width of the I/O operations.
+  @param  Address               The base address of the I/O operations.
   @param  Count                 The number of I/O operations to perform.
   @param  Buffer                For read operations, the destination buffer to store the results. For write
                                 operations, the source buffer to write data from. If
                                 Width is MMIO_COPY_UINT8, MMIO_COPY_UINT16,
                                 MMIO_COPY_UINT32, or MMIO_COPY_UINT64, then
-                                Buffer is interpreted as a base address of an I/O operation such as Address. 
+                                Buffer is interpreted as a base address of an I/O operation such as Address.
 
   @retval EFI_SUCCESS           The data was read from or written to the device.
-  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.      
+  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
   @retval EFI_INVALID_PARAMETER Width is invalid.
-                                   
+
 **/
 typedef
 EFI_STATUS
@@ -86,19 +80,19 @@ typedef struct {
   EFI_DEVICE_IO Write;
 } EFI_IO_ACCESS;
 
-/**                                                                 
+/**
   Provides an EFI Device Path for a PCI device with the given PCI configuration space address.
-    
+
   @param  This                  A pointer to the EFI_DEVICE_IO_INTERFACE instance.
   @param  PciAddress            The PCI configuration space address of the device whose Device Path
-                                is going to be returned.  
+                                is going to be returned.
   @param  PciDevicePath         A pointer to the pointer for the EFI Device Path for PciAddress.
-                                Memory for the Device Path is allocated from the pool.          
+                                Memory for the Device Path is allocated from the pool.
 
   @retval EFI_SUCCESS           The PciDevicePath returns a pointer to a valid EFI Device Path.
-  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.      
+  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
   @retval EFI_UNSUPPORTED       The PciAddress does not map to a valid EFI Device Path.
-                                   
+
 **/
 typedef
 EFI_STATUS
@@ -118,7 +112,7 @@ typedef enum {
   /// A write operation to system memory by a bus master.
   ///
   EfiBusMasterWrite,
-  
+
   ///
   /// Provides both read and write access to system memory
   /// by both the processor and a bus master. The buffer is
@@ -128,9 +122,9 @@ typedef enum {
   EfiBusMasterCommonBuffer
 } EFI_IO_OPERATION_TYPE;
 
-/**                                                                 
+/**
   Provides the device-specific addresses needed to access system memory.
-    
+
   @param  This                  A pointer to the EFI_DEVICE_IO_INTERFACE instance.
   @param  Operation             Indicates if the bus master is going to read or write to system memory.
   @param  HostAddress           The system memory address to map to the device.
@@ -141,11 +135,11 @@ typedef enum {
   @param  Mapping               A resulting value to pass to Unmap().
 
   @retval EFI_SUCCESS           The range was mapped for the returned NumberOfBytes.
-  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.      
+  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
   @retval EFI_UNSUPPORTED       The HostAddress cannot be mapped as a common buffer.
   @retval EFI_INVALID_PARAMETER The Operation or HostAddress is undefined.
   @retval EFI_DEVICE_ERROR      The system hardware could not map the requested address.
-                                   
+
 **/
 typedef
 EFI_STATUS
@@ -158,15 +152,15 @@ EFI_STATUS
   OUT VOID                            **Mapping
   );
 
-/**                                                                 
+/**
   Completes the Map() operation and releases any corresponding resources.
-    
+
   @param  This                  A pointer to the EFI_DEVICE_IO_INTERFACE instance.
   @param  Mapping               A resulting value to pass to Unmap().
 
   @retval EFI_SUCCESS           The range was mapped for the returned NumberOfBytes.
   @retval EFI_DEVICE_ERROR      The system hardware could not map the requested address.
-                                   
+
 **/
 typedef
 EFI_STATUS
@@ -175,22 +169,22 @@ EFI_STATUS
   IN VOID                             *Mapping
   );
 
-/**                                                                 
+/**
   Allocates pages that are suitable for an EFIBusMasterCommonBuffer mapping.
-    
+
   @param  This                  A pointer to the EFI_DEVICE_IO_INTERFACE instance.
   @param  Type                  The type allocation to perform.
   @param  MemoryType            The type of memory to allocate, EfiBootServicesData or
                                 EfiRuntimeServicesData.
   @param  Pages                 The number of pages to allocate.
-  @param  HostAddress           A pointer to store the base address of the allocated range.                                
+  @param  HostAddress           A pointer to store the base address of the allocated range.
 
   @retval EFI_SUCCESS           The requested memory pages were allocated.
   @retval EFI_OUT_OF_RESOURCES  The memory pages could not be allocated.
   @retval EFI_INVALID_PARAMETER The requested memory type is invalid.
   @retval EFI_UNSUPPORTED       The requested HostAddress is not supported on
-                                this platform.                               
-                                   
+                                this platform.
+
 **/
 typedef
 EFI_STATUS
@@ -202,14 +196,14 @@ EFI_STATUS
   IN OUT EFI_PHYSICAL_ADDRESS         *HostAddress
   );
 
-/**                                                                 
+/**
   Flushes any posted write data to the device.
-    
+
   @param  This                  A pointer to the EFI_DEVICE_IO_INTERFACE instance.
 
   @retval EFI_SUCCESS           The buffers were flushed.
-  @retval EFI_DEVICE_ERROR      The buffers were not flushed due to a hardware error.                                 
-  
+  @retval EFI_DEVICE_ERROR      The buffers were not flushed due to a hardware error.
+
 **/
 typedef
 EFI_STATUS
@@ -217,18 +211,18 @@ EFI_STATUS
   IN EFI_DEVICE_IO_PROTOCOL  *This
   );
 
-/**                                                                 
+/**
   Frees pages that were allocated with AllocateBuffer().
-    
-  @param  This                  A pointer to the EFI_DEVICE_IO_INTERFACE instance.  
+
+  @param  This                  A pointer to the EFI_DEVICE_IO_INTERFACE instance.
   @param  Pages                 The number of pages to free.
   @param  HostAddress           The base address of the range to free.
 
   @retval EFI_SUCCESS           The requested memory pages were allocated.
   @retval EFI_NOT_FOUND         The requested memory pages were not allocated with
-                                AllocateBuffer().  
+                                AllocateBuffer().
   @retval EFI_INVALID_PARAMETER HostAddress is not page aligned or Pages is invalid.
-  
+
 **/
 typedef
 EFI_STATUS
@@ -239,7 +233,7 @@ EFI_STATUS
   );
 
 ///
-/// This protocol provides the basic Memory, I/O, and PCI interfaces that 
+/// This protocol provides the basic Memory, I/O, and PCI interfaces that
 /// are used to abstract accesses to devices.
 ///
 struct _EFI_DEVICE_IO_PROTOCOL {
diff --git a/MdePkg/Include/Protocol/DevicePath.h b/MdePkg/Include/Protocol/DevicePath.h
index 1958a3dd180f..5eeca70c8bce 100644
--- a/MdePkg/Include/Protocol/DevicePath.h
+++ b/MdePkg/Include/Protocol/DevicePath.h
@@ -2,17 +2,11 @@
   The device path protocol as defined in UEFI 2.0.
 
   The device path represents a programmatic path to a device,
-  from a software point of view. The path must persist from boot to boot, so 
+  from a software point of view. The path must persist from boot to boot, so
   it can not contain things like PCI bus numbers that change from boot to boot.
 
-Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.              
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -39,11 +33,11 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #pragma pack(1)
 
 /**
-  This protocol can be used on any device handle to obtain generic path/location 
-  information concerning the physical device or logical device. If the handle does 
-  not logically map to a physical device, the handle may not necessarily support 
-  the device path protocol. The device path describes the location of the device 
-  the handle is for. The size of the Device Path can be determined from the structures 
+  This protocol can be used on any device handle to obtain generic path/location
+  information concerning the physical device or logical device. If the handle does
+  not logically map to a physical device, the handle may not necessarily support
+  the device path protocol. The device path describes the location of the device
+  the handle is for. The size of the Device Path can be determined from the structures
   that make up the Device Path.
 **/
 typedef struct {
@@ -53,20 +47,20 @@ typedef struct {
                     ///< 0x04 Media Device Path.
                     ///< 0x05 BIOS Boot Specification Device Path.
                     ///< 0x7F End of Hardware Device Path.
-                    
+
   UINT8 SubType;    ///< Varies by Type
                     ///< 0xFF End Entire Device Path, or
                     ///< 0x01 End This Instance of a Device Path and start a new
                     ///< Device Path.
-                    
+
   UINT8 Length[2];  ///< Specific Device Path data. Type and Sub-Type define
                     ///< type of data. Size of data is included in Length.
-                    
+
 } EFI_DEVICE_PATH_PROTOCOL;
 
 ///
 /// Device Path protocol definition for backward-compatible with EFI1.1.
-/// 
+///
 typedef EFI_DEVICE_PATH_PROTOCOL  EFI_DEVICE_PATH;
 
 ///
@@ -288,6 +282,21 @@ typedef struct {
   //
 } ACPI_ADR_DEVICE_PATH;
 
+///
+/// ACPI NVDIMM Device Path SubType.
+///
+#define ACPI_NVDIMM_DP               0x04
+///
+///
+typedef struct {
+  EFI_DEVICE_PATH_PROTOCOL        Header;
+  ///
+  /// NFIT Device Handle, the _ADR of the NVDIMM device.
+  /// The value of this field comes from Section 9.20.3 of the ACPI 6.2A specification.
+  ///
+  UINT32                          NFITDeviceHandle;
+} ACPI_NVDIMM_DEVICE_PATH;
+
 #define ACPI_ADR_DISPLAY_TYPE_OTHER             0
 #define ACPI_ADR_DISPLAY_TYPE_VGA               1
 #define ACPI_ADR_DISPLAY_TYPE_TV                2
@@ -718,6 +727,18 @@ typedef struct {
   UINT8                           StopBits;
 } UART_DEVICE_PATH;
 
+///
+/// NVDIMM Namespace Device Path SubType.
+///
+#define NVDIMM_NAMESPACE_DP               0x20
+typedef struct {
+  EFI_DEVICE_PATH_PROTOCOL        Header;
+  ///
+  /// Namespace unique label identifier UUID.
+  ///
+  EFI_GUID Uuid;
+} NVDIMM_NAMESPACE_DEVICE_PATH;
+
 //
 // Use VENDOR_DEVICE_PATH struct
 //
@@ -818,6 +839,22 @@ typedef struct {
 } NVME_NAMESPACE_DEVICE_PATH;
 
 ///
+/// DNS Device Path SubType
+///
+#define MSG_DNS_DP                0x1F
+typedef struct {
+  EFI_DEVICE_PATH_PROTOCOL        Header;
+  ///
+  /// Indicates the DNS server address is IPv4 or IPv6 address.
+  ///
+  UINT8                           IsIPv6;
+  ///
+  /// Instance of the DNS server address.
+  ///
+  EFI_IP_ADDRESS                  DnsServerIp[];
+} DNS_DEVICE_PATH;
+
+///
 /// Uniform Resource Identifiers (URI) Device Path SubType
 ///
 #define MSG_URI_DP                0x18
@@ -938,6 +975,15 @@ typedef struct {
   UINT8                           SSId[32];
 } WIFI_DEVICE_PATH;
 
+///
+/// Bluetooth LE Device Path SubType.
+///
+#define MSG_BLUETOOTH_LE_DP       0x1E
+typedef struct {
+  EFI_DEVICE_PATH_PROTOCOL        Header;
+  BLUETOOTH_LE_ADDRESS            Address;
+} BLUETOOTH_LE_DEVICE_PATH;
+
 //
 // Media Device Path
 //
@@ -1047,8 +1093,8 @@ typedef struct {
 #define MEDIA_PROTOCOL_DP         0x05
 
 ///
-/// The Media Protocol Device Path is used to denote the protocol that is being 
-/// used in a device path at the location of the path specified. 
+/// The Media Protocol Device Path is used to denote the protocol that is being
+/// used in a device path at the location of the path specified.
 /// Many protocols are inherent to the style of device path.
 ///
 typedef struct {
@@ -1243,6 +1289,7 @@ typedef union {
   SAS_DEVICE_PATH                            Sas;
   SASEX_DEVICE_PATH                          SasEx;
   NVME_NAMESPACE_DEVICE_PATH                 NvmeNamespace;
+  DNS_DEVICE_PATH                            Dns;
   URI_DEVICE_PATH                            Uri;
   BLUETOOTH_DEVICE_PATH                      Bluetooth;
   WIFI_DEVICE_PATH                           WiFi;
@@ -1300,6 +1347,7 @@ typedef union {
   SAS_DEVICE_PATH                            *Sas;
   SASEX_DEVICE_PATH                          *SasEx;
   NVME_NAMESPACE_DEVICE_PATH                 *NvmeNamespace;
+  DNS_DEVICE_PATH                            *Dns;
   URI_DEVICE_PATH                            *Uri;
   BLUETOOTH_DEVICE_PATH                      *Bluetooth;
   WIFI_DEVICE_PATH                           *WiFi;
@@ -1321,7 +1369,7 @@ typedef union {
 } EFI_DEV_PATH_PTR;
 
 #pragma pack()
-                                             
+
 #define END_DEVICE_PATH_TYPE                 0x7f
 #define END_ENTIRE_DEVICE_PATH_SUBTYPE       0xFF
 #define END_INSTANCE_DEVICE_PATH_SUBTYPE     0x01
diff --git a/MdePkg/Include/Protocol/DevicePathFromText.h b/MdePkg/Include/Protocol/DevicePathFromText.h
index cbdbc466dcad..998fa5cd6562 100644
--- a/MdePkg/Include/Protocol/DevicePathFromText.h
+++ b/MdePkg/Include/Protocol/DevicePathFromText.h
@@ -1,15 +1,9 @@
 /** @file
-  EFI_DEVICE_PATH_FROM_TEXT_PROTOCOL as defined in UEFI 2.0.  
+  EFI_DEVICE_PATH_FROM_TEXT_PROTOCOL as defined in UEFI 2.0.
   This protocol provides service to convert text to device paths and device nodes.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -39,8 +33,8 @@ typedef
 EFI_DEVICE_PATH_PROTOCOL*
 (EFIAPI *EFI_DEVICE_PATH_FROM_TEXT_NODE)(
   IN CONST CHAR16                 *TextDeviceNode
-  );    
-  
+  );
+
 
 /**
   Convert text to the binary representation of a device node.
@@ -57,7 +51,7 @@ typedef
 EFI_DEVICE_PATH_PROTOCOL*
 (EFIAPI *EFI_DEVICE_PATH_FROM_TEXT_PATH)(
   IN CONST CHAR16                 *TextDevicePath
-  );  
+  );
 
 ///
 /// This protocol converts text to device paths and device nodes.
diff --git a/MdePkg/Include/Protocol/DevicePathToText.h b/MdePkg/Include/Protocol/DevicePathToText.h
index 923ee648404f..4a8cdaffb330 100644
--- a/MdePkg/Include/Protocol/DevicePathToText.h
+++ b/MdePkg/Include/Protocol/DevicePathToText.h
@@ -1,15 +1,9 @@
 /** @file
-  EFI_DEVICE_PATH_TO_TEXT_PROTOCOL as defined in UEFI 2.0.  
+  EFI_DEVICE_PATH_TO_TEXT_PROTOCOL as defined in UEFI 2.0.
   This protocol provides service to convert device nodes and paths to text.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -45,7 +39,7 @@ CHAR16*
   IN CONST EFI_DEVICE_PATH_PROTOCOL   *DeviceNode,
   IN BOOLEAN                          DisplayOnly,
   IN BOOLEAN                          AllowShortcuts
-  );      
+  );
 
 /**
   Convert a device path to its text representation.
@@ -54,7 +48,7 @@ CHAR16*
   @param  DisplayOnly    If DisplayOnly is TRUE, then the shorter text representation
                          of the display node is used, where applicable. If DisplayOnly
                          is FALSE, then the longer text representation of the display node
-                         is used.  
+                         is used.
   @param  AllowShortcuts The AllowShortcuts is FALSE, then the shortcut forms of
                          text representation for a device node cannot be used.
 
@@ -68,7 +62,7 @@ CHAR16*
   IN CONST EFI_DEVICE_PATH_PROTOCOL   *DevicePath,
   IN BOOLEAN                          DisplayOnly,
   IN BOOLEAN                          AllowShortcuts
-  );    
+  );
 
 ///
 /// This protocol converts device paths and device nodes to text.
diff --git a/MdePkg/Include/Protocol/DevicePathUtilities.h b/MdePkg/Include/Protocol/DevicePathUtilities.h
index 35fd624f2c39..68c91f05f1a0 100644
--- a/MdePkg/Include/Protocol/DevicePathUtilities.h
+++ b/MdePkg/Include/Protocol/DevicePathUtilities.h
@@ -1,15 +1,9 @@
 /** @file
-  EFI_DEVICE_PATH_UTILITIES_PROTOCOL as defined in UEFI 2.0.  
+  EFI_DEVICE_PATH_UTILITIES_PROTOCOL as defined in UEFI 2.0.
   Use to create and manipulate device paths and device nodes.
 
-  Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -30,15 +24,15 @@
   @param  DevicePath Points to the start of the EFI device path.
 
   @return Size  Size of the specified device path, in bytes, including the end-of-path tag.
-  @retval 0     DevicePath is NULL   
+  @retval 0     DevicePath is NULL
 
 **/
 typedef
 UINTN
 (EFIAPI *EFI_DEVICE_PATH_UTILS_GET_DEVICE_PATH_SIZE)(
   IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath
-  );    
-  
+  );
+
 
 /**
   Create a duplicate of the specified path.
@@ -53,11 +47,11 @@ typedef
 EFI_DEVICE_PATH_PROTOCOL*
 (EFIAPI *EFI_DEVICE_PATH_UTILS_DUP_DEVICE_PATH)(
   IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath
-  );      
+  );
 
 /**
   Create a new path by appending the second device path to the first.
-  If Src1 is NULL and Src2 is non-NULL, then a duplicate of Src2 is returned. 
+  If Src1 is NULL and Src2 is non-NULL, then a duplicate of Src2 is returned.
   If Src1 is non-NULL and Src2 is NULL, then a duplicate of Src1 is returned.
   If Src1 and Src2 are both NULL, then a copy of an end-of-device-path is returned.
 
@@ -73,11 +67,11 @@ EFI_DEVICE_PATH_PROTOCOL*
 (EFIAPI *EFI_DEVICE_PATH_UTILS_APPEND_PATH)(
   IN CONST EFI_DEVICE_PATH_PROTOCOL *Src1,
   IN CONST EFI_DEVICE_PATH_PROTOCOL *Src2
-  );     
-  
+  );
+
 /**
   Creates a new path by appending the device node to the device path.
-  If DeviceNode is NULL then a copy of DevicePath is returned. 
+  If DeviceNode is NULL then a copy of DevicePath is returned.
   If DevicePath is NULL then a copy of DeviceNode, followed by an end-of-device path device node is returned.
   If both DeviceNode and DevicePath are NULL then a copy of an end-of-device-path device node is returned.
 
@@ -110,7 +104,7 @@ EFI_DEVICE_PATH_PROTOCOL*
 (EFIAPI *EFI_DEVICE_PATH_UTILS_APPEND_INSTANCE)(
   IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath,
   IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePathInstance
-  );  
+  );
 
 /**
   Creates a copy of the current device path instance and returns a pointer to the next device path
@@ -119,7 +113,7 @@ EFI_DEVICE_PATH_PROTOCOL*
   @param  DevicePathInstance     On input, this holds the pointer to the current device path
                                  instance. On output, this holds the pointer to the next
                                  device path instance or NULL if there are no more device
-                                 path instances in the device path.  
+                                 path instances in the device path.
   @param  DevicePathInstanceSize On output, this holds the size of the device path instance,
                                  in bytes or zero, if DevicePathInstance is NULL.
                                  If NULL, then the instance size is not output.
@@ -133,7 +127,7 @@ EFI_DEVICE_PATH_PROTOCOL*
 (EFIAPI *EFI_DEVICE_PATH_UTILS_GET_NEXT_INSTANCE)(
   IN  OUT EFI_DEVICE_PATH_PROTOCOL  **DevicePathInstance,
   OUT UINTN                         *DevicePathInstanceSize
-  );  
+  );
 
 /**
   Creates a device node
@@ -156,7 +150,7 @@ EFI_DEVICE_PATH_PROTOCOL*
   IN UINT8                          NodeType,
   IN UINT8                          NodeSubType,
   IN UINT16                         NodeLength
-);   
+);
 
 /**
   Returns whether a device path is multi-instance.
@@ -171,11 +165,11 @@ typedef
 BOOLEAN
 (EFIAPI *EFI_DEVICE_PATH_UTILS_IS_MULTI_INSTANCE)(
   IN CONST EFI_DEVICE_PATH_PROTOCOL         *DevicePath
-  );                                                                                                       
-  
+  );
+
 ///
 /// This protocol is used to creates and manipulates device paths and device nodes.
-/// 
+///
 typedef struct {
   EFI_DEVICE_PATH_UTILS_GET_DEVICE_PATH_SIZE GetDevicePathSize;
   EFI_DEVICE_PATH_UTILS_DUP_DEVICE_PATH      DuplicateDevicePath;
@@ -187,6 +181,6 @@ typedef struct {
   EFI_DEVICE_PATH_UTILS_CREATE_NODE          CreateDeviceNode;
 } EFI_DEVICE_PATH_UTILITIES_PROTOCOL;
 
-extern EFI_GUID gEfiDevicePathUtilitiesProtocolGuid; 
+extern EFI_GUID gEfiDevicePathUtilitiesProtocolGuid;
 
 #endif
diff --git a/MdePkg/Include/Protocol/Dhcp4.h b/MdePkg/Include/Protocol/Dhcp4.h
index 5dcd47c76b85..05a0a6e20403 100644
--- a/MdePkg/Include/Protocol/Dhcp4.h
+++ b/MdePkg/Include/Protocol/Dhcp4.h
@@ -4,16 +4,10 @@
   These protocols are used to collect configuration information for the EFI IPv4 Protocol
   drivers and to provide DHCPv4 server and PXE boot server discovery services.
 
-Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-  @par Revision Reference:          
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
   This Protocol was introduced in UEFI Specification 2.0.
 
 **/
@@ -82,7 +76,7 @@ typedef struct {
   ///
   UINT32              Size;
   ///
-  /// Length of the EFI_DHCP4_PACKET from the first byte of the Header field 
+  /// Length of the EFI_DHCP4_PACKET from the first byte of the Header field
   /// to the last byte of the Option[] field.
   ///
   UINT32              Length;
@@ -183,24 +177,24 @@ typedef enum{
   ///
   Dhcp4BoundCompleted = 0x08,
   ///
-  /// It is time to enter the Dhcp4Renewing state and to contact the server 
+  /// It is time to enter the Dhcp4Renewing state and to contact the server
   /// that originally issued the network address. No packet is associated with this event.
   ///
   Dhcp4EnterRenewing  = 0x09,
   ///
-  /// It is time to enter the Dhcp4Rebinding state and to contact any server. 
+  /// It is time to enter the Dhcp4Rebinding state and to contact any server.
   /// No packet is associated with this event.
   ///
   Dhcp4EnterRebinding = 0x0a,
   ///
-  /// The configured IP address was lost either because the lease has expired, 
-  /// the user released the configuration, or a DHCPNAK packet was received in 
+  /// The configured IP address was lost either because the lease has expired,
+  /// the user released the configuration, or a DHCPNAK packet was received in
   /// the Dhcp4Renewing or Dhcp4Rebinding state. No packet is associated with this event.
   ///
   Dhcp4AddressLost    = 0x0b,
   ///
-  /// The DHCP process failed because a DHCPNAK packet was received or the user 
-  /// aborted the DHCP process at a time when the configuration was not available yet. 
+  /// The DHCP process failed because a DHCPNAK packet was received or the user
+  /// aborted the DHCP process at a time when the configuration was not available yet.
   /// No packet is associated with this event.
   ///
   Dhcp4Fail           = 0x0c
@@ -208,7 +202,7 @@ typedef enum{
 
 /**
   Callback routine.
-  
+
   EFI_DHCP4_CALLBACK is provided by the consumer of the EFI DHCPv4 Protocol driver
   to intercept events that occurred in the configuration process. This structure
   provides advanced control of each state transition of the DHCP process. The
@@ -257,8 +251,8 @@ typedef struct {
   ///
   UINT32                      DiscoverTryCount;
   ///
-  /// The maximum amount of time (in seconds) to wait for returned packets in each 
-  /// of the retries. Timeout values of zero will default to a timeout value 
+  /// The maximum amount of time (in seconds) to wait for returned packets in each
+  /// of the retries. Timeout values of zero will default to a timeout value
   /// of one second. Set to NULL to use default timeout values.
   ///
   UINT32                      *DiscoverTimeout;
@@ -269,21 +263,21 @@ typedef struct {
   ///
   UINT32                      RequestTryCount;
   ///
-  /// The maximum amount of time (in seconds) to wait for return packets in each of the retries. 
-  /// Timeout values of zero will default to a timeout value of one second. 
+  /// The maximum amount of time (in seconds) to wait for return packets in each of the retries.
+  /// Timeout values of zero will default to a timeout value of one second.
   /// Set to NULL to use default timeout values.
   ///
   UINT32                      *RequestTimeout;
   ///
   /// For a DHCPDISCOVER, setting this parameter to the previously allocated IP
-  /// address will cause the EFI DHCPv4 Protocol driver to enter the Dhcp4InitReboot state. 
+  /// address will cause the EFI DHCPv4 Protocol driver to enter the Dhcp4InitReboot state.
   /// And set this field to 0.0.0.0 to enter the Dhcp4Init state.
   /// For a DHCPINFORM this parameter should be set to the client network address
   /// which was assigned to the client during a DHCPDISCOVER.
   ///
   EFI_IPv4_ADDRESS            ClientAddress;
   ///
-  /// The callback function to intercept various events that occurred in 
+  /// The callback function to intercept various events that occurred in
   /// the DHCP configuration process. Set to NULL to ignore all those events.
   ///
   EFI_DHCP4_CALLBACK          Dhcp4Callback;
@@ -308,7 +302,7 @@ typedef struct {
 
 typedef struct {
   ///
-  /// The EFI DHCPv4 Protocol driver operating state. 
+  /// The EFI DHCPv4 Protocol driver operating state.
   ///
   EFI_DHCP4_STATE             State;
   ///
@@ -329,7 +323,7 @@ typedef struct {
   ///
   EFI_IPv4_ADDRESS            ServerAddress;
   ///
-  /// The router IP address that was acquired from the DHCP server. 
+  /// The router IP address that was acquired from the DHCP server.
   /// May be zero if the server does not offer this address.
   ///
   EFI_IPv4_ADDRESS            RouterAddress;
@@ -338,8 +332,8 @@ typedef struct {
   ///
   EFI_IPv4_ADDRESS            SubnetMask;
   ///
-  /// The lease time (in 1-second units) of the configured IP address. 
-  /// The value 0xFFFFFFFF means that the lease time is infinite. 
+  /// The lease time (in 1-second units) of the configured IP address.
+  /// The value 0xFFFFFFFF means that the lease time is infinite.
   /// A default lease of 7 days is used if the DHCP server does not provide a value.
   ///
   UINT32                      LeaseTime;
@@ -356,12 +350,12 @@ typedef struct {
   ///
   EFI_IPv4_ADDRESS            ListenAddress;
   ///
-  /// The subnet mask of above listening unicast/broadcast IP address. 
+  /// The subnet mask of above listening unicast/broadcast IP address.
   /// Ignored if ListenAddress is a multicast address.
   ///
   EFI_IPv4_ADDRESS            SubnetMask;
   ///
-  /// Alternate station source (or listening) port number. 
+  /// Alternate station source (or listening) port number.
   /// If zero, then the default station port number (68) will be used.
   ///
   UINT16                      ListenPort;
@@ -374,7 +368,7 @@ typedef struct {
   ///
   EFI_STATUS              Status;
   ///
-  /// If not NULL, the event that will be signaled when the collection process 
+  /// If not NULL, the event that will be signaled when the collection process
   /// completes. If NULL, this function will busy-wait until the collection process competes.
   ///
   EFI_EVENT               CompletionEvent;
@@ -395,7 +389,7 @@ typedef struct {
   ///
   UINT32                  ListenPointCount;
   ///
-  /// An array of station address and port number pairs that are used as receiving filters. 
+  /// An array of station address and port number pairs that are used as receiving filters.
   /// The first entry is also used as the source address and source port of the outgoing packet.
   ///
   EFI_DHCP4_LISTEN_POINT  *ListenPoints;
@@ -420,7 +414,7 @@ typedef struct {
 
 /**
   Returns the current operating mode and cached data packet for the EFI DHCPv4 Protocol driver.
-  
+
   The GetModeData() function returns the current operating mode and cached data
   packet for the EFI DHCPv4 Protocol driver.
 
@@ -510,7 +504,7 @@ EFI_STATUS
   time when each event occurs in this process, the callback function that was set
   by EFI_DHCP4_PROTOCOL.Configure() will be called and the user can take this
   opportunity to control the process.
-  
+
   @param  This            The pointer to the EFI_DHCP4_PROTOCOL instance.
   @param  CompletionEvent If not NULL, it indicates the event that will be signaled when the
                           EFI DHCPv4 Protocol driver is transferred into the
@@ -544,7 +538,7 @@ EFI_STATUS
 
 /**
   Extends the lease time by sending a request packet.
-  
+
   The RenewRebind() function is used to manually extend the lease time when the
   EFI DHCPv4 Protocol driver is in the Dhcp4Bound state, and the lease time has
   not expired yet. This function will send a request packet to the previously
@@ -617,7 +611,7 @@ EFI_STATUS
 
 /**
   Stops the current address configuration.
-  
+
   The Stop() function is used to stop the DHCP configuration process. After this
   function is called successfully, the EFI DHCPv4 Protocol driver is transferred
   into the Dhcp4Stopped state. EFI_DHCP4_PROTOCOL.Configure() needs to be called
@@ -686,7 +680,7 @@ EFI_STATUS
 
 /**
   Transmits a DHCP formatted packet and optionally waits for responses.
-  
+
   The TransmitReceive() function is used to transmit a DHCP packet and optionally
   wait for the response from servers. This function does not change the state of
   the EFI DHCPv4 Protocol driver. It can be used at any time because of this.
@@ -719,7 +713,7 @@ EFI_STATUS
 
 /**
   Parses the packed DHCP option data.
-  
+
   The Parse() function is used to retrieve the option list from a DHCP packet.
   If *OptionCount isn't zero, and there is enough space for all the DHCP options
   in the Packet, each element of PacketOptionList is set to point to somewhere in
diff --git a/MdePkg/Include/Protocol/Dhcp6.h b/MdePkg/Include/Protocol/Dhcp6.h
index 8e0ae27eb934..ca79afa2d546 100644
--- a/MdePkg/Include/Protocol/Dhcp6.h
+++ b/MdePkg/Include/Protocol/Dhcp6.h
@@ -2,16 +2,10 @@
   UEFI Dynamic Host Configuration Protocol 6 Definition, which is used to get IPv6
   addresses and other configuration parameters from DHCPv6 servers.
 
-  Copyright (c) 2008 - 2010, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-                                                                                            
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 
-
-  @par Revision Reference:          
+  Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
   This Protocol is introduced in UEFI Specification 2.2
 
 **/
@@ -31,9 +25,9 @@
 
 typedef struct _EFI_DHCP6_PROTOCOL EFI_DHCP6_PROTOCOL;
 
-typedef enum { 
+typedef enum {
   ///
-  /// The EFI DHCPv6 Protocol instance is configured, and start() needs 
+  /// The EFI DHCPv6 Protocol instance is configured, and start() needs
   /// to be called
   ///
   Dhcp6Init                    = 0x0,
@@ -43,7 +37,7 @@ typedef enum {
   ///
   Dhcp6Selecting               = 0x1,
   ///
-  /// A Request is sent out to the DHCPv6 server, and the EFI DHCPv6 
+  /// A Request is sent out to the DHCPv6 server, and the EFI DHCPv6
   /// Protocol instance is waiting for Reply packet.
   ///
   Dhcp6Requesting              = 0x2,
@@ -54,7 +48,7 @@ typedef enum {
   ///
   Dhcp6Declining               = 0x3,
   ///
-  /// A Confirm packet is sent out to confirm the IPv6 addresses of the 
+  /// A Confirm packet is sent out to confirm the IPv6 addresses of the
   /// configured IA, and the EFI DHCPv6 Protocol instance is waiting for Reply packet.
   ///
   Dhcp6Confirming              = 0x4,
@@ -80,55 +74,55 @@ typedef enum {
 } EFI_DHCP6_STATE;
 
 typedef enum {
-  ///     
+  ///
   /// A Solicit packet is about to be sent. The packet is passed to Dhcp6Callback and
   /// can be modified or replaced in Dhcp6Callback.
   ///
   Dhcp6SendSolicit             = 0x0,
-  ///     
+  ///
   /// An Advertise packet is received and will be passed to Dhcp6Callback.
   ///
   Dhcp6RcvdAdvertise           = 0x1,
-  ///     
+  ///
   /// It is time for Dhcp6Callback to determine whether select the default Advertise
   /// packet by RFC 3315 policy, or overwrite it by specific user policy.
   ///
   Dhcp6SelectAdvertise         = 0x2,
-  ///     
+  ///
   /// A Request packet is about to be sent. The packet is passed to Dhcp6Callback and
   /// can be modified or replaced in Dhcp6Callback.
   ///
   Dhcp6SendRequest             = 0x3,
-  ///     
+  ///
   /// A Reply packet is received and will be passed to Dhcp6Callback.
   ///
   Dhcp6RcvdReply               = 0x4,
-  ///     
+  ///
   /// A Reconfigure packet is received and will be passed to Dhcp6Callback.
   ///
   Dhcp6RcvdReconfigure         = 0x5,
-  ///     
+  ///
   /// A Decline packet is about to be sent. The packet is passed to Dhcp6Callback and
   /// can be modified or replaced in Dhcp6Callback.
   ///
   Dhcp6SendDecline             = 0x6,
-  ///     
+  ///
   /// A Confirm packet is about to be sent. The packet is passed to Dhcp6Callback and
   /// can be modified or replaced in Dhcp6Callback.
   ///
   Dhcp6SendConfirm             = 0x7,
-  ///     
+  ///
   /// A Release packet is about to be sent. The packet is passed to Dhcp6Callback and
   /// can be modified or replaced in Dhcp6Callback.
   ///
   Dhcp6SendRelease             = 0x8,
-  ///     
+  ///
   /// A Renew packet is about to be sent. The packet is passed to Dhcp6Callback and
-  /// can be modified or replaced in Dhcp6Callback. 
+  /// can be modified or replaced in Dhcp6Callback.
   ///
   Dhcp6EnterRenewing           = 0x9,
-  ///     
-  /// A Rebind packet is about to be sent. The packet is passed to Dhcp6Callback and 
+  ///
+  /// A Rebind packet is about to be sent. The packet is passed to Dhcp6Callback and
   /// can be modified or replaced in Dhcp6Callback.
   ///
   Dhcp6EnterRebinding          = 0xa
@@ -147,7 +141,7 @@ typedef enum {
 ///
 /// EFI_DHCP6_PACKET_OPTION
 /// defines the format of the DHCPv6 option, See RFC 3315 for more information.
-/// This data structure is used to reference option data that is packed in the DHCPv6 packet. 
+/// This data structure is used to reference option data that is packed in the DHCPv6 packet.
 ///
 typedef struct {
   ///
@@ -167,7 +161,7 @@ typedef struct {
 
 ///
 /// EFI_DHCP6_HEADER
-/// defines the format of the DHCPv6 header. See RFC 3315 for more information. 
+/// defines the format of the DHCPv6 header. See RFC 3315 for more information.
 ///
 typedef struct{
   ///
@@ -181,7 +175,7 @@ typedef struct{
 } EFI_DHCP6_HEADER;
 
 ///
-/// EFI_DHCP6_PACKET 
+/// EFI_DHCP6_PACKET
 /// defines the format of the DHCPv6 packet. See RFC 3315 for more information.
 ///
 typedef struct {
@@ -225,19 +219,19 @@ typedef struct {
   ///
   UINT32                       Irt;
   ///
-  /// Maximum retransmission count for one packet. If Mrc is zero, there's no upper limit 
+  /// Maximum retransmission count for one packet. If Mrc is zero, there's no upper limit
   /// for retransmission count.
   ///
   UINT32                       Mrc;
   ///
-  /// Maximum retransmission timeout for each retry. It's the upper bound of the number of 
-  /// retransmission timeout. If Mrt is zero, there is no upper limit for retransmission 
+  /// Maximum retransmission timeout for each retry. It's the upper bound of the number of
+  /// retransmission timeout. If Mrt is zero, there is no upper limit for retransmission
   /// timeout.
   ///
   UINT32                       Mrt;
   ///
-  /// Maximum retransmission duration for one packet. It's the upper bound of the numbers 
-  /// the client may retransmit a message. If Mrd is zero, there's no upper limit for 
+  /// Maximum retransmission duration for one packet. It's the upper bound of the numbers
+  /// the client may retransmit a message. If Mrd is zero, there's no upper limit for
   /// retransmission duration.
   ///
   UINT32                       Mrd;
@@ -281,7 +275,7 @@ typedef struct {
   ///
   UINT32                       IaAddressCount;
   ///
-  /// List of the IPv6 addresses of the configured IA. When the state of the configured IA is 
+  /// List of the IPv6 addresses of the configured IA. When the state of the configured IA is
   /// in Dhcp6Bound, Dhcp6Renewing and Dhcp6Rebinding, the IPv6 addresses are usable.
   ///
   EFI_DHCP6_IA_ADDRESS         IaAddress[1];
@@ -300,39 +294,39 @@ typedef struct {
 } EFI_DHCP6_MODE_DATA;
 
 /**
-  EFI_DHCP6_CALLBACK is provided by the consumer of the EFI DHCPv6 Protocol instance to 
+  EFI_DHCP6_CALLBACK is provided by the consumer of the EFI DHCPv6 Protocol instance to
   intercept events that occurs in the DHCPv6 S.A.R.R process.
 
-  @param[in]  This              Pointer to the EFI_DHCP6_PROTOCOL instance that is used to configure this 
+  @param[in]  This              Pointer to the EFI_DHCP6_PROTOCOL instance that is used to configure this
                                 callback function.
   @param[in]  Context           Pointer to the context that is initialized by EFI_DHCP6_PROTOCOL.Configure().
   @param[in]  CurrentState      The current state of the configured IA.
   @param[in]  Dhcp6Event        The event that occurs in the current state, which usually means a state transition.
   @param[in]  Packet            Pointer to the DHCPv6 packet that is about to be sent or has been received.
-                                The EFI DHCPv6 Protocol instance is responsible for freeing the buffer. 
-  @param[out] NewPacket         Pointer to the new DHCPv6 packet to overwrite the Packet. NewPacket can not 
-                                share the buffer with Packet. If *NewPacket is not NULL, the EFI DHCPv6 
+                                The EFI DHCPv6 Protocol instance is responsible for freeing the buffer.
+  @param[out] NewPacket         Pointer to the new DHCPv6 packet to overwrite the Packet. NewPacket can not
+                                share the buffer with Packet. If *NewPacket is not NULL, the EFI DHCPv6
                                 Protocol instance is responsible for freeing the buffer.
 
   @retval EFI_SUCCESS           Tell the EFI DHCPv6 Protocol instance to continue the DHCPv6 S.A.R.R process.
-  @retval EFI_ABORTED           Tell the EFI DHCPv6 Protocol instance to abort the DHCPv6 S.A.R.R process, 
+  @retval EFI_ABORTED           Tell the EFI DHCPv6 Protocol instance to abort the DHCPv6 S.A.R.R process,
                                 and the state of the configured IA will be transferred to Dhcp6Init.
 
 **/
-typedef 
-EFI_STATUS 
+typedef
+EFI_STATUS
 (EFIAPI *EFI_DHCP6_CALLBACK)(
   IN EFI_DHCP6_PROTOCOL        *This,
   IN VOID                      *Context,
   IN EFI_DHCP6_STATE           CurrentState,
   IN EFI_DHCP6_EVENT           Dhcp6Event,
-  IN EFI_DHCP6_PACKET          *Packet,        
+  IN EFI_DHCP6_PACKET          *Packet,
   OUT EFI_DHCP6_PACKET         **NewPacket OPTIONAL
   );
 
 typedef struct {
   ///
-  /// The callback function is to intercept various events that occur in the DHCPv6 S.A.R.R 
+  /// The callback function is to intercept various events that occur in the DHCPv6 S.A.R.R
   /// process. Set to NULL to ignore all those events.
   ///
   EFI_DHCP6_CALLBACK           Dhcp6Callback;
@@ -345,11 +339,11 @@ typedef struct {
   ///
   UINT32                       OptionCount;
   ///
-  /// List of the DHCPv6 options to be included in Solicit and Request packet. The buffer 
-  /// can be freed after EFI_DHCP6_PROTOCOL.Configure() returns. Ignored if 
-  /// OptionCount is zero. OptionList should not contain Client Identifier option 
-  /// and any IA option, which will be appended by EFI DHCPv6 Protocol instance 
-  /// automatically. 
+  /// List of the DHCPv6 options to be included in Solicit and Request packet. The buffer
+  /// can be freed after EFI_DHCP6_PROTOCOL.Configure() returns. Ignored if
+  /// OptionCount is zero. OptionList should not contain Client Identifier option
+  /// and any IA option, which will be appended by EFI DHCPv6 Protocol instance
+  /// automatically.
   ///
   EFI_DHCP6_PACKET_OPTION      **OptionList;
   ///
@@ -357,40 +351,40 @@ typedef struct {
   ///
   EFI_DHCP6_IA_DESCRIPTOR      IaDescriptor;
   ///
-  /// If not NULL, the event will be signaled when any IPv6 address information of the 
-  /// configured IA is updated, including IPv6 address, preferred lifetime and valid 
-  /// lifetime, or the DHCPv6 S.A.R.R process fails. Otherwise, Start(), 
-  /// renewrebind(), decline(), release() and stop() will be blocking 
+  /// If not NULL, the event will be signaled when any IPv6 address information of the
+  /// configured IA is updated, including IPv6 address, preferred lifetime and valid
+  /// lifetime, or the DHCPv6 S.A.R.R process fails. Otherwise, Start(),
+  /// renewrebind(), decline(), release() and stop() will be blocking
   /// operations, and they will wait for the exchange process completion or failure.
   ///
   EFI_EVENT                    IaInfoEvent;
   ///
-  /// If TRUE, the EFI DHCPv6 Protocol instance is willing to accept Reconfigure packet. 
-  /// Otherwise, it will ignore it. Reconfigure Accept option can not be specified through 
+  /// If TRUE, the EFI DHCPv6 Protocol instance is willing to accept Reconfigure packet.
+  /// Otherwise, it will ignore it. Reconfigure Accept option can not be specified through
   /// OptionList parameter.
   ///
   BOOLEAN                      ReconfigureAccept;
   ///
-  /// If TRUE, the EFI DHCPv6 Protocol instance will send Solicit packet with Rapid 
-  /// Commit option. Otherwise, Rapid Commit option will not be included in Solicit 
+  /// If TRUE, the EFI DHCPv6 Protocol instance will send Solicit packet with Rapid
+  /// Commit option. Otherwise, Rapid Commit option will not be included in Solicit
   /// packet. Rapid Commit option can not be specified through OptionList parameter.
   ///
   BOOLEAN                      RapidCommit;
   ///
-  /// Parameter to control Solicit packet retransmission behavior. The 
+  /// Parameter to control Solicit packet retransmission behavior. The
   /// buffer can be freed after EFI_DHCP6_PROTOCOL.Configure() returns.
   ///
   EFI_DHCP6_RETRANSMISSION     *SolicitRetransmission;
 } EFI_DHCP6_CONFIG_DATA;
 
 /**
-  EFI_DHCP6_INFO_CALLBACK is provided by the consumer of the EFI DHCPv6 Protocol 
+  EFI_DHCP6_INFO_CALLBACK is provided by the consumer of the EFI DHCPv6 Protocol
   instance to intercept events that occurs in the DHCPv6 Information Request exchange process.
 
-  @param[in]  This              Pointer to the EFI_DHCP6_PROTOCOL instance that is used to configure this 
+  @param[in]  This              Pointer to the EFI_DHCP6_PROTOCOL instance that is used to configure this
                                 callback function.
   @param[in]  Context           Pointer to the context that is initialized in the EFI_DHCP6_PROTOCOL.InfoRequest().
-  @param[in]  Packet            Pointer to Reply packet that has been received. The EFI DHCPv6 Protocol instance is 
+  @param[in]  Packet            Pointer to Reply packet that has been received. The EFI DHCPv6 Protocol instance is
                                 responsible for freeing the buffer.
 
   @retval EFI_SUCCESS           Tell the EFI DHCPv6 Protocol instance to finish Information Request exchange process.
@@ -410,20 +404,20 @@ EFI_STATUS
   Retrieve the current operating mode data and configuration data for the EFI DHCPv6 Protocol instance.
 
   @param[in]  This              Pointer to the EFI_DHCP6_PROTOCOL instance.
-  @param[out] Dhcp6ModeData     Pointer to the DHCPv6 mode data structure. The caller is responsible for freeing this 
+  @param[out] Dhcp6ModeData     Pointer to the DHCPv6 mode data structure. The caller is responsible for freeing this
                                 structure and each reference buffer.
-  @param[out] Dhcp6ConfigData   Pointer to the DHCPv6 configuration data structure. The caller is responsible for 
+  @param[out] Dhcp6ConfigData   Pointer to the DHCPv6 configuration data structure. The caller is responsible for
                                 freeing this structure and each reference buffer.
 
   @retval EFI_SUCCESS           The mode data was returned.
   @retval EFI_ACCESS_DENIED     The EFI DHCPv6 Protocol instance has not been configured when Dhcp6ConfigData is not NULL.
   @retval EFI_INVALID_PARAMETER One or more following conditions are TRUE:
-                                - This is NULL. 
+                                - This is NULL.
                                 - Both Dhcp6ConfigData and Dhcp6ModeData are NULL.
 
 **/
-typedef 
-EFI_STATUS 
+typedef
+EFI_STATUS
 (EFIAPI *EFI_DHCP6_GET_MODE_DATA)(
   IN EFI_DHCP6_PROTOCOL        *This,
   OUT EFI_DHCP6_MODE_DATA      *Dhcp6ModeData OPTIONAL,
@@ -433,15 +427,15 @@ EFI_STATUS
 /**
   Initialize or clean up the configuration data for the EFI DHCPv6 Protocol instance.
 
-  The Configure() function is used to initialize or clean up the configuration data of the EFI 
+  The Configure() function is used to initialize or clean up the configuration data of the EFI
   DHCPv6 Protocol instance.
-  - When Dhcp6CfgData is not NULL and Configure() is called successfully, the 
-    configuration data will be initialized in the EFI DHCPv6 Protocol instance and the state of the 
+  - When Dhcp6CfgData is not NULL and Configure() is called successfully, the
+    configuration data will be initialized in the EFI DHCPv6 Protocol instance and the state of the
     configured IA will be transferred into Dhcp6Init.
-  - When Dhcp6CfgData is NULL and Configure() is called successfully, the configuration 
+  - When Dhcp6CfgData is NULL and Configure() is called successfully, the configuration
     data will be cleaned up and no IA will be associated with the EFI DHCPv6 Protocol instance.
 
-  To update the configuration data for an EFI DCHPv6 Protocol instance, the original data must be 
+  To update the configuration data for an EFI DCHPv6 Protocol instance, the original data must be
   cleaned up before setting the new configuration data.
 
   @param[in]  This              Pointer to the EFI_DHCP6_PROTOCOL instance.
@@ -449,24 +443,24 @@ EFI_STATUS
 
   @retval EFI_SUCCESS           The mode data was returned.
   @retval EFI_INVALID_PARAMETER One or more following conditions are TRUE
-                                - This is NULL. 
+                                - This is NULL.
                                 - OptionCount > 0 and OptionList is NULL.
                                 - OptionList is not NULL, and Client Id option, Reconfigure Accept option,
                                   Rapid Commit option or any IA option is specified in the OptionList.
                                 - IaDescriptor.Type is neither EFI_DHCP6_IA_TYPE_NA nor EFI_DHCP6_IA_TYPE_NA.
                                 - IaDescriptor is not unique.
                                 - Both IaInfoEvent and SolicitRetransimssion are NULL.
-                                - SolicitRetransmission is not NULL, and both SolicitRetransimssion->Mrc and 
+                                - SolicitRetransmission is not NULL, and both SolicitRetransimssion->Mrc and
                                   SolicitRetransmission->Mrd are zero.
-  @retval EFI_ACCESS_DENIED     The EFI DHCPv6 Protocol instance has been already configured 
+  @retval EFI_ACCESS_DENIED     The EFI DHCPv6 Protocol instance has been already configured
                                 when Dhcp6CfgData is not NULL.
-                                The EFI DHCPv6 Protocol instance has already started the 
+                                The EFI DHCPv6 Protocol instance has already started the
                                 DHCPv6 S.A.R.R when Dhcp6CfgData is NULL.
   @retval EFI_OUT_OF_RESOURCES  Required system resources could not be allocated.
   @retval EFI_DEVICE_ERROR      An unexpected system or network error occurred.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_DHCP6_CONFIGURE)(
   IN EFI_DHCP6_PROTOCOL        *This,
@@ -476,13 +470,13 @@ EFI_STATUS
 /**
   Start the DHCPv6 S.A.R.R process.
 
-  The Start() function starts the DHCPv6 S.A.R.R process. This function can be called only when 
+  The Start() function starts the DHCPv6 S.A.R.R process. This function can be called only when
   the state of the configured IA is in the Dhcp6Init state. If the DHCPv6 S.A.R.R process completes
-  successfully, the state of the configured IA will be transferred through Dhcp6Selecting and 
-  Dhcp6Requesting to Dhcp6Bound state. The update of the IPv6 addresses will be notified through 
-  EFI_DHCP6_CONFIG_DATA.IaInfoEvent. At the time when each event occurs in this process, the 
-  callback function set by EFI_DHCP6_PROTOCOL.Configure() will be called and the user can take 
-  this opportunity to control the process. If EFI_DHCP6_CONFIG_DATA.IaInfoEvent is NULL, the 
+  successfully, the state of the configured IA will be transferred through Dhcp6Selecting and
+  Dhcp6Requesting to Dhcp6Bound state. The update of the IPv6 addresses will be notified through
+  EFI_DHCP6_CONFIG_DATA.IaInfoEvent. At the time when each event occurs in this process, the
+  callback function set by EFI_DHCP6_PROTOCOL.Configure() will be called and the user can take
+  this opportunity to control the process. If EFI_DHCP6_CONFIG_DATA.IaInfoEvent is NULL, the
   Start() function call is a blocking operation. It will return after the DHCPv6 S.A.R.R process
   completes or aborted by users. If the process is aborted by system or network error, the state of
   the configured IA will be transferred to Dhcp6Init. The Start() function can be called again to
@@ -490,10 +484,10 @@ EFI_STATUS
 
   @param[in]  This              Pointer to the EFI_DHCP6_PROTOCOL instance.
 
-  @retval EFI_SUCCESS           The DHCPv6 S.A.R.R process is completed and at least one IPv6 
-                                address has been bound to the configured IA when 
-                                EFI_DHCP6_CONFIG_DATA.IaInfoEvent is NULL. 
-                                The DHCPv6 S.A.R.R process is started when 
+  @retval EFI_SUCCESS           The DHCPv6 S.A.R.R process is completed and at least one IPv6
+                                address has been bound to the configured IA when
+                                EFI_DHCP6_CONFIG_DATA.IaInfoEvent is NULL.
+                                The DHCPv6 S.A.R.R process is started when
                                 EFI_DHCP6_CONFIG_DATA.IaInfoEvent is not NULL.
   @retval EFI_ACCESS_DENIED     The EFI DHCPv6 Child instance hasn't been configured.
   @retval EFI_INVALID_PARAMETER This is NULL.
@@ -501,13 +495,13 @@ EFI_STATUS
   @retval EFI_ALREADY_STARTED   The DHCPv6 S.A.R.R process has already started.
   @retval EFI_DEVICE_ERROR      An unexpected network or system error occurred.
   @retval EFI_NO_RESPONSE       The DHCPv6 S.A.R.R process failed because of no response.
-  @retval EFI_NO_MAPPING        No IPv6 address has been bound to the configured IA after the 
+  @retval EFI_NO_MAPPING        No IPv6 address has been bound to the configured IA after the
                                 DHCPv6 S.A.R.R process.
   @retval EFI_ABORTED           The DHCPv6 S.A.R.R process aborted by user.
   @retval EFI_NO_MEDIA          There was a media error.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_DHCP6_START)(
   IN EFI_DHCP6_PROTOCOL        *This
@@ -517,19 +511,19 @@ EFI_STATUS
   Request configuration information without the assignment of any IA addresses of the client.
 
   The InfoRequest() function is used to request configuration information without the assignment
-  of any IPv6 address of the client. Client sends out Information Request packet to obtain 
-  the required configuration information, and DHCPv6 server responds with Reply packet containing 
-  the information for the client. The received Reply packet will be passed to the user by 
+  of any IPv6 address of the client. Client sends out Information Request packet to obtain
+  the required configuration information, and DHCPv6 server responds with Reply packet containing
+  the information for the client. The received Reply packet will be passed to the user by
   ReplyCallback function. If user returns EFI_NOT_READY from ReplyCallback, the EFI DHCPv6
-  Protocol instance will continue to receive other Reply packets unless timeout according to 
-  the Retransmission parameter. Otherwise, the Information Request exchange process will be 
+  Protocol instance will continue to receive other Reply packets unless timeout according to
+  the Retransmission parameter. Otherwise, the Information Request exchange process will be
   finished successfully if user returns EFI_SUCCESS from ReplyCallback.
 
   @param[in]  This              Pointer to the EFI_DHCP6_PROTOCOL instance.
   @param[in]  SendClientId      If TRUE, the EFI DHCPv6 Protocol instance will build Client
                                 Identifier option and include it into Information Request
                                 packet. If FALSE, Client Identifier option will not be included.
-                                Client Identifier option can not be specified through OptionList 
+                                Client Identifier option can not be specified through OptionList
                                 parameter.
   @param[in]  OptionRequest     Pointer to the Option Request option in the Information Request
                                 packet. Option Request option can not be specified through
@@ -543,29 +537,29 @@ EFI_STATUS
                                 returns.
   @param[in]  TimeoutEvent      If not NULL, this event is signaled when the information request
                                 exchange aborted because of no response. If NULL, the function
-                                call is a blocking operation; and it will return after the 
+                                call is a blocking operation; and it will return after the
                                 information-request exchange process finish or aborted by users.
   @param[in]  ReplyCallback     The callback function is to intercept various events that occur
                                 in the Information Request exchange process. It should not be
                                 set to NULL.
   @param[in]  CallbackContext   Pointer to the context that will be passed to ReplyCallback.
 
-  @retval EFI_SUCCESS           The DHCPv6 S.A.R.R process is completed and at least one IPv6 
-  @retval EFI_SUCCESS           The DHCPv6 information request exchange process completed 
+  @retval EFI_SUCCESS           The DHCPv6 S.A.R.R process is completed and at least one IPv6
+  @retval EFI_SUCCESS           The DHCPv6 information request exchange process completed
                                 when TimeoutEvent is NULL. Information Request packet has been
                                 sent to DHCPv6 server when TimeoutEvent is not NULL.
   @retval EFI_INVALID_PARAMETER One or more following conditions are TRUE:
-                                - This is NULL. 
+                                - This is NULL.
                                 - OptionRequest is NULL or OptionRequest->OpCode is invalid.
                                 - OptionCount > 0 and OptionList is NULL.
-                                - OptionList is not NULL, and Client Identify option or 
+                                - OptionList is not NULL, and Client Identify option or
                                   Option Request option is specified in the OptionList.
                                 - Retransimssion is NULL.
                                 - Both Retransimssion->Mrc and Retransmission->Mrd are zero.
                                 - ReplyCallback is NULL.
   @retval EFI_DEVICE_ERROR      An unexpected network or system error occurred.
-  @retval EFI_NO_RESPONSE       The DHCPv6 information request exchange process failed 
-                                because of no response, or not all requested-options are 
+  @retval EFI_NO_RESPONSE       The DHCPv6 information request exchange process failed
+                                because of no response, or not all requested-options are
                                 responded by DHCPv6 servers when Timeout happened.
   @retval EFI_ABORTED           The DHCPv6 information request exchange process aborted by user.
 
@@ -578,7 +572,7 @@ EFI_STATUS
   IN EFI_DHCP6_PACKET_OPTION   *OptionRequest,
   IN UINT32                    OptionCount,
   IN EFI_DHCP6_PACKET_OPTION   *OptionList[] OPTIONAL,
-  IN EFI_DHCP6_RETRANSMISSION  *Retransmission, 
+  IN EFI_DHCP6_RETRANSMISSION  *Retransmission,
   IN EFI_EVENT                 TimeoutEvent OPTIONAL,
   IN EFI_DHCP6_INFO_CALLBACK   ReplyCallback,
   IN VOID                      *CallbackContext OPTIONAL
@@ -588,38 +582,38 @@ EFI_STATUS
   Manually extend the valid and preferred lifetimes for the IPv6 addresses of the configured
   IA and update other configuration parameters by sending Renew or Rebind packet.
 
-  The RenewRebind() function is used to manually extend the valid and preferred lifetimes for the 
-  IPv6 addresses of the configured IA and update other configuration parameters by sending Renew or 
-  Rebind packet. 
-  - When RebindRequest is FALSE and the state of the configured IA is Dhcp6Bound, it 
-  will send Renew packet to the previously DHCPv6 server and transfer the state of the configured 
-  IA to Dhcp6Renewing. If valid Reply packet received, the state transfers to Dhcp6Bound 
-  and the valid and preferred timer restarts. If fails, the state transfers to Dhcp6Bound but the 
-  timer continues. 
-  - When RebindRequest is TRUE and the state of the configured IA is Dhcp6Bound, it will 
-  send Rebind packet. If valid Reply packet received, the state transfers to Dhcp6Bound and the 
+  The RenewRebind() function is used to manually extend the valid and preferred lifetimes for the
+  IPv6 addresses of the configured IA and update other configuration parameters by sending Renew or
+  Rebind packet.
+  - When RebindRequest is FALSE and the state of the configured IA is Dhcp6Bound, it
+  will send Renew packet to the previously DHCPv6 server and transfer the state of the configured
+  IA to Dhcp6Renewing. If valid Reply packet received, the state transfers to Dhcp6Bound
+  and the valid and preferred timer restarts. If fails, the state transfers to Dhcp6Bound but the
+  timer continues.
+  - When RebindRequest is TRUE and the state of the configured IA is Dhcp6Bound, it will
+  send Rebind packet. If valid Reply packet received, the state transfers to Dhcp6Bound and the
   valid and preferred timer restarts. If fails, the state transfers to Dhcp6Init and the IA can't
   be used.
 
   @param[in]  This              Pointer to the EFI_DHCP4_PROTOCOL instance.
-  @param[in]  RebindRequest     If TRUE, it will send Rebind packet and enter the Dhcp6Rebinding state. 
+  @param[in]  RebindRequest     If TRUE, it will send Rebind packet and enter the Dhcp6Rebinding state.
                                 Otherwise, it will send Renew packet and enter the Dhcp6Renewing state.
 
-  @retval EFI_SUCCESS           The DHCPv6 renew/rebind exchange process has completed and at 
+  @retval EFI_SUCCESS           The DHCPv6 renew/rebind exchange process has completed and at
                                 least one IPv6 address of the configured IA has been bound again
-                                when EFI_DHCP6_CONFIG_DATA.IaInfoEvent is NULL. 
-                                The EFI DHCPv6 Protocol instance has sent Renew or Rebind packet 
+                                when EFI_DHCP6_CONFIG_DATA.IaInfoEvent is NULL.
+                                The EFI DHCPv6 Protocol instance has sent Renew or Rebind packet
                                 when EFI_DHCP6_CONFIG_DATA.IaInfoEvent is not NULL.
   @retval EFI_ACCESS_DENIED     The EFI DHCPv6 Child instance hasn't been configured, or the state
                                 of the configured IA is not in Dhcp6Bound.
-  @retval EFI_ALREADY_STARTED   The state of the configured IA has already entered Dhcp6Renewing 
-                                when RebindRequest is FALSE. 
-                                The state of the configured IA has already entered Dhcp6Rebinding 
+  @retval EFI_ALREADY_STARTED   The state of the configured IA has already entered Dhcp6Renewing
+                                when RebindRequest is FALSE.
+                                The state of the configured IA has already entered Dhcp6Rebinding
                                 when RebindRequest is TRUE.
   @retval EFI_INVALID_PARAMETER This is NULL.
   @retval EFI_DEVICE_ERROR      An unexpected system or system error occurred.
   @retval EFI_NO_RESPONSE       The DHCPv6 renew/rebind exchange process failed because of no response.
-  @retval EFI_NO_MAPPING        No IPv6 address has been bound to the configured IA after the DHCPv6 
+  @retval EFI_NO_MAPPING        No IPv6 address has been bound to the configured IA after the DHCPv6
                                 renew/rebind exchange process.
   @retval EFI_ABORTED           The DHCPv6 renew/rebind exchange process aborted by user.
 
@@ -635,34 +629,34 @@ EFI_STATUS
   Inform that one or more IPv6 addresses assigned by a server are already in use by
   another node.
 
-  The Decline() function is used to manually decline the assignment of IPv6 addresses, which 
-  have been already used by another node. If all IPv6 addresses of the configured IA are declined 
-  through this function, the state of the IA will switch through Dhcp6Declining to Dhcp6Init, 
-  otherwise, the state of the IA will restore to Dhcp6Bound after the declining process. The 
-  Decline() can only be called when the IA is in Dhcp6Bound state. If the 
-  EFI_DHCP6_CONFIG_DATA.IaInfoEvent is NULL, this function is a blocking operation. It 
+  The Decline() function is used to manually decline the assignment of IPv6 addresses, which
+  have been already used by another node. If all IPv6 addresses of the configured IA are declined
+  through this function, the state of the IA will switch through Dhcp6Declining to Dhcp6Init,
+  otherwise, the state of the IA will restore to Dhcp6Bound after the declining process. The
+  Decline() can only be called when the IA is in Dhcp6Bound state. If the
+  EFI_DHCP6_CONFIG_DATA.IaInfoEvent is NULL, this function is a blocking operation. It
   will return after the declining process finishes, or aborted by user.
 
   @param[in]  This              Pointer to the EFI_DHCP4_PROTOCOL instance.
-  @param[in]  AddressCount      Number of declining IPv6 addresses. 
+  @param[in]  AddressCount      Number of declining IPv6 addresses.
   @param[in]  Addresses         Pointer to the buffer stored all the declining IPv6 addresses.
 
-  @retval EFI_SUCCESS           The DHCPv6 decline exchange process has completed when 
+  @retval EFI_SUCCESS           The DHCPv6 decline exchange process has completed when
                                 EFI_DHCP6_CONFIG_DATA.IaInfoEvent is NULL.
-                                The EFI DHCPv6 Protocol instance has sent Decline packet when 
+                                The EFI DHCPv6 Protocol instance has sent Decline packet when
                                 EFI_DHCP6_CONFIG_DATA.IaInfoEvent is not NULL.
   @retval EFI_INVALID_PARAMETER One or more following conditions are TRUE
-                                - This is NULL.  
+                                - This is NULL.
                                 - AddressCount is zero or Addresses is NULL.
-  @retval EFI_NOT_FOUND         Any specified IPv6 address is not correlated with the configured IA 
+  @retval EFI_NOT_FOUND         Any specified IPv6 address is not correlated with the configured IA
                                 for this instance.
-  @retval EFI_ACCESS_DENIED     The EFI DHCPv6 Child instance hasn't been configured, or the 
+  @retval EFI_ACCESS_DENIED     The EFI DHCPv6 Child instance hasn't been configured, or the
                                 state of the configured IA is not in Dhcp6Bound.
   @retval EFI_DEVICE_ERROR      An unexpected network or system error occurred.
   @retval EFI_ABORTED           The DHCPv6 decline exchange process aborted by user.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_DHCP6_DECLINE)(
   IN EFI_DHCP6_PROTOCOL        *This,
@@ -675,32 +669,32 @@ EFI_STATUS
 
   The Release() function is used to manually release the one or more IPv6 address. If AddressCount
   is zero, it will release all IPv6 addresses of the configured IA. If all IPv6 addresses of the IA
-  are released through this function, the state of the IA will switch through Dhcp6Releasing to 
+  are released through this function, the state of the IA will switch through Dhcp6Releasing to
   Dhcp6Init, otherwise, the state of the IA will restore to Dhcp6Bound after the releasing process.
   The Release() can only be called when the IA is in Dhcp6Bound state. If the
   EFI_DHCP6_CONFIG_DATA.IaInfoEvent is NULL, the function is a blocking operation. It will return
-  after the releasing process finishes, or aborted by user. 
+  after the releasing process finishes, or aborted by user.
 
   @param[in]  This              Pointer to the EFI_DHCP6_PROTOCOL instance.
-  @param[in]  AddressCount      Number of releasing IPv6 addresses. 
+  @param[in]  AddressCount      Number of releasing IPv6 addresses.
   @param[in]  Addresses         Pointer to the buffer stored all the releasing IPv6 addresses.
                                 Ignored if AddressCount is zero.
-  @retval EFI_SUCCESS           The DHCPv6 release exchange process has completed when 
+  @retval EFI_SUCCESS           The DHCPv6 release exchange process has completed when
                                 EFI_DHCP6_CONFIG_DATA.IaInfoEvent is NULL.
-                                The EFI DHCPv6 Protocol instance has sent Release packet when 
+                                The EFI DHCPv6 Protocol instance has sent Release packet when
                                 EFI_DHCP6_CONFIG_DATA.IaInfoEvent is not NULL.
   @retval EFI_INVALID_PARAMETER One or more following conditions are TRUE
-                                - This is NULL.  
+                                - This is NULL.
                                 - AddressCount is not zero or Addresses is NULL.
   @retval EFI_NOT_FOUND         Any specified IPv6 address is not correlated with the configured
                                 IA for this instance.
-  @retval EFI_ACCESS_DENIED     The EFI DHCPv6 Child instance hasn't been configured, or the 
+  @retval EFI_ACCESS_DENIED     The EFI DHCPv6 Child instance hasn't been configured, or the
                                 state of the configured IA is not in Dhcp6Bound.
   @retval EFI_DEVICE_ERROR      An unexpected network or system error occurred.
-  @retval EFI_ABORTED           The DHCPv6 release exchange process aborted by user. 
+  @retval EFI_ABORTED           The DHCPv6 release exchange process aborted by user.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_DHCP6_RELEASE)(
   IN EFI_DHCP6_PROTOCOL        *This,
@@ -713,7 +707,7 @@ EFI_STATUS
 
   The Stop() function is used to stop the DHCPv6 S.A.R.R process. If this function is called
   successfully, all the IPv6 addresses of the configured IA will be released and the state of
-  the configured IA will be transferred to Dhcp6Init.   
+  the configured IA will be transferred to Dhcp6Init.
 
   @param[in]  This              Pointer to the EFI_DHCP6_PROTOCOL instance.
 
@@ -725,7 +719,7 @@ EFI_STATUS
   @retval EFI_INVALID_PARAMETER This is NULL.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_DHCP6_STOP)(
   IN EFI_DHCP6_PROTOCOL        *This
@@ -734,7 +728,7 @@ EFI_STATUS
 /**
   Parse the option data in the DHCPv6 packet.
 
-  The Parse() function is used to retrieve the option list in the DHCPv6 packet. 
+  The Parse() function is used to retrieve the option list in the DHCPv6 packet.
 
   @param[in]  This              Pointer to the EFI_DHCP6_PROTOCOL instance.
 
@@ -751,7 +745,7 @@ EFI_STATUS
                                 - Packet is not a well-formed DHCPv6 packet.
                                 - OptionCount is NULL.
                                 - *OptionCount is not zero and PacketOptionList is NULL.
-  @retval EFI_BUFFER_TOO_SMALL  *OptionCount is smaller than the number of options that were 
+  @retval EFI_BUFFER_TOO_SMALL  *OptionCount is smaller than the number of options that were
                                 found in the Packet.
 
 **/
diff --git a/MdePkg/Include/Protocol/DiskInfo.h b/MdePkg/Include/Protocol/DiskInfo.h
index e60ae0e98921..e0215d61df00 100644
--- a/MdePkg/Include/Protocol/DiskInfo.h
+++ b/MdePkg/Include/Protocol/DiskInfo.h
@@ -1,20 +1,14 @@
 /** @file
-  Provides the basic interfaces to abstract platform information regarding an 
-  IDE controller.  
+  Provides the basic interfaces to abstract platform information regarding an
+  IDE controller.
 
-  Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
-  This Protocol is defined in UEFI Platform Initialization Specification 1.2 
+  This Protocol is defined in UEFI Platform Initialization Specification 1.6
   Volume 5: Standards
-  
+
 **/
 
 #ifndef __DISK_INFO_H__
@@ -81,9 +75,17 @@ typedef struct _EFI_DISK_INFO_PROTOCOL  EFI_DISK_INFO_PROTOCOL;
     0x4b3029cc, 0x6b98, 0x47fb, { 0xbc, 0x96, 0x76, 0xdc, 0xb8, 0x4, 0x41, 0xf0 } \
   }
 
+///
+/// Global ID for an SD/MMC interface.  Used to fill in EFI_DISK_INFO_PROTOCOL.Interface
+///
+#define EFI_DISK_INFO_SD_MMC_INTERFACE_GUID \
+  { \
+    0x8deec992, 0xd39c, 0x4a5c, { 0xab, 0x6b, 0x98, 0x6e, 0x14, 0x24, 0x2b, 0x9d } \
+  }
+
 /**
   Provides inquiry information for the controller type.
-  
+
   This function is used by the IDE bus driver to get inquiry data.  Data format
   of Identify data is defined by the Interface GUID.
 
@@ -92,9 +94,9 @@ typedef struct _EFI_DISK_INFO_PROTOCOL  EFI_DISK_INFO_PROTOCOL;
   @param[in,out] InquiryDataSize   Pointer to the value for the inquiry data size.
 
   @retval EFI_SUCCESS            The command was accepted without any errors.
-  @retval EFI_NOT_FOUND          Device does not support this data class 
-  @retval EFI_DEVICE_ERROR       Error reading InquiryData from device 
-  @retval EFI_BUFFER_TOO_SMALL   InquiryDataSize not big enough 
+  @retval EFI_NOT_FOUND          Device does not support this data class
+  @retval EFI_DEVICE_ERROR       Error reading InquiryData from device
+  @retval EFI_BUFFER_TOO_SMALL   InquiryDataSize not big enough
 
 **/
 typedef
@@ -111,16 +113,16 @@ EFI_STATUS
   This function is used by the IDE bus driver to get identify data.  Data format
   of Identify data is defined by the Interface GUID.
 
-  @param[in]     This               Pointer to the EFI_DISK_INFO_PROTOCOL 
+  @param[in]     This               Pointer to the EFI_DISK_INFO_PROTOCOL
                                     instance.
   @param[in,out] IdentifyData       Pointer to a buffer for the identify data.
   @param[in,out] IdentifyDataSize   Pointer to the value for the identify data
                                     size.
 
   @retval EFI_SUCCESS            The command was accepted without any errors.
-  @retval EFI_NOT_FOUND          Device does not support this data class 
-  @retval EFI_DEVICE_ERROR       Error reading IdentifyData from device 
-  @retval EFI_BUFFER_TOO_SMALL   IdentifyDataSize not big enough 
+  @retval EFI_NOT_FOUND          Device does not support this data class
+  @retval EFI_DEVICE_ERROR       Error reading IdentifyData from device
+  @retval EFI_BUFFER_TOO_SMALL   IdentifyDataSize not big enough
 
 **/
 typedef
@@ -133,8 +135,8 @@ EFI_STATUS
 
 /**
   Provides sense data information for the controller type.
-  
-  This function is used by the IDE bus driver to get sense data. 
+
+  This function is used by the IDE bus driver to get sense data.
   Data format of Sense data is defined by the Interface GUID.
 
   @param[in]     This              Pointer to the EFI_DISK_INFO_PROTOCOL instance.
@@ -160,7 +162,7 @@ EFI_STATUS
 /**
   This function is used by the IDE bus driver to get controller information.
 
-  @param[in]  This         Pointer to the EFI_DISK_INFO_PROTOCOL instance. 
+  @param[in]  This         Pointer to the EFI_DISK_INFO_PROTOCOL instance.
   @param[out] IdeChannel   Pointer to the Ide Channel number.  Primary or secondary.
   @param[out] IdeDevice    Pointer to the Ide Device number.  Master or slave.
 
@@ -181,7 +183,7 @@ EFI_STATUS
 ///
 struct _EFI_DISK_INFO_PROTOCOL {
   ///
-  /// A GUID that defines the format of buffers for the other member functions 
+  /// A GUID that defines the format of buffers for the other member functions
   /// of this protocol.
   ///
   EFI_GUID                  Interface;
@@ -201,7 +203,7 @@ struct _EFI_DISK_INFO_PROTOCOL {
   ///
   EFI_DISK_INFO_SENSE_DATA  SenseData;
   ///
-  /// Specific controller. 
+  /// Specific controller.
   ///
   EFI_DISK_INFO_WHICH_IDE   WhichIde;
 };
@@ -214,5 +216,6 @@ extern EFI_GUID gEfiDiskInfoUsbInterfaceGuid;
 extern EFI_GUID gEfiDiskInfoAhciInterfaceGuid;
 extern EFI_GUID gEfiDiskInfoNvmeInterfaceGuid;
 extern EFI_GUID gEfiDiskInfoUfsInterfaceGuid;
+extern EFI_GUID gEfiDiskInfoSdMmcInterfaceGuid;
 
 #endif
diff --git a/MdePkg/Include/Protocol/DiskIo.h b/MdePkg/Include/Protocol/DiskIo.h
index 9f2526161c7c..d6e6a47b31dd 100644
--- a/MdePkg/Include/Protocol/DiskIo.h
+++ b/MdePkg/Include/Protocol/DiskIo.h
@@ -5,14 +5,8 @@
   oriented devices. The Disk IO protocol is intended to layer on top of the
   Block IO protocol.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -26,14 +20,14 @@
 
 ///
 /// Protocol GUID name defined in EFI1.1.
-/// 
+///
 #define DISK_IO_PROTOCOL  EFI_DISK_IO_PROTOCOL_GUID
 
 typedef struct _EFI_DISK_IO_PROTOCOL EFI_DISK_IO_PROTOCOL;
 
 ///
 /// Protocol defined in EFI1.1.
-/// 
+///
 typedef EFI_DISK_IO_PROTOCOL  EFI_DISK_IO;
 
 /**
@@ -95,7 +89,7 @@ EFI_STATUS
 
 ///
 /// Revision defined in EFI1.1
-/// 
+///
 #define EFI_DISK_IO_INTERFACE_REVISION  EFI_DISK_IO_PROTOCOL_REVISION
 
 ///
diff --git a/MdePkg/Include/Protocol/DiskIo2.h b/MdePkg/Include/Protocol/DiskIo2.h
index c2994c2facd5..b3dfb24be344 100644
--- a/MdePkg/Include/Protocol/DiskIo2.h
+++ b/MdePkg/Include/Protocol/DiskIo2.h
@@ -4,14 +4,8 @@
   The Disk I/O 2 protocol defines an extension to the Disk I/O protocol to enable
   non-blocking / asynchronous byte-oriented disk operation.
 
-  Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/Protocol/Dns4.h b/MdePkg/Include/Protocol/Dns4.h
index 61c8e5c38ad5..d02713f706fd 100644
--- a/MdePkg/Include/Protocol/Dns4.h
+++ b/MdePkg/Include/Protocol/Dns4.h
@@ -4,14 +4,8 @@
   DNSv4 Service Binding Protocol (DNSv4SB)
   DNSv4 Protocol (DNSv4)
 
-  Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution. The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This Protocol is introduced in UEFI Specification 2.5
@@ -38,23 +32,23 @@ typedef struct _EFI_DNS4_PROTOCOL EFI_DNS4_PROTOCOL;
 ///
 typedef struct {
   ///
-  /// Count of the DNS servers. When used with GetModeData(), 
-  /// this field is the count of originally configured servers when 
-  /// Configure() was called for this instance. When used with 
-  /// Configure() this is the count of caller-supplied servers. If the 
-  /// DnsServerListCount is zero, the DNS server configuration 
+  /// Count of the DNS servers. When used with GetModeData(),
+  /// this field is the count of originally configured servers when
+  /// Configure() was called for this instance. When used with
+  /// Configure() this is the count of caller-supplied servers. If the
+  /// DnsServerListCount is zero, the DNS server configuration
   /// will be retrieved from DHCP server automatically.
   ///
   UINTN                         DnsServerListCount;
   ///
-  /// Pointer to DNS server list containing DnsServerListCount entries or NULL 
-  /// if DnsServerListCountis 0. For Configure(), this will be NULL when there are 
-  /// no caller supplied server addresses, and, the DNS instance will retrieve 
-  /// DNS server from DHCP Server. The provided DNS server list is 
-  /// recommended to be filled up in the sequence of preference. When 
-  /// used with GetModeData(), the buffer containing the list will 
-  /// be allocated by the driver implementing this protocol and must be 
-  /// freed by the caller. When used with Configure(), the buffer 
+  /// Pointer to DNS server list containing DnsServerListCount entries or NULL
+  /// if DnsServerListCountis 0. For Configure(), this will be NULL when there are
+  /// no caller supplied server addresses, and, the DNS instance will retrieve
+  /// DNS server from DHCP Server. The provided DNS server list is
+  /// recommended to be filled up in the sequence of preference. When
+  /// used with GetModeData(), the buffer containing the list will
+  /// be allocated by the driver implementing this protocol and must be
+  /// freed by the caller. When used with Configure(), the buffer
   /// containing the list will be allocated and released by the caller.
   ///
   EFI_IPv4_ADDRESS              *DnsServerList;
@@ -68,10 +62,10 @@ typedef struct {
   ///
   BOOLEAN                       EnableDnsCache;
   ///
-  /// Use the protocol number defined in "Links to UEFI-Related 
-  /// Documents"(http://uefi.org/uefi) under the heading "IANA 
-  /// Protocol Numbers". Only TCP or UDP are supported, and other 
-  /// protocol values are invalid. An implementation can choose to 
+  /// Use the protocol number defined in "Links to UEFI-Related
+  /// Documents"(http://uefi.org/uefi) under the heading "IANA
+  /// Protocol Numbers". Only TCP or UDP are supported, and other
+  /// protocol values are invalid. An implementation can choose to
   /// support only UDP, or both TCP and UDP.
   ///
   UINT8                         Protocol;
@@ -135,10 +129,10 @@ typedef struct {
   ///
   UINT32                        DnsServerCount;
   ///
-  /// Pointer to common list of addresses of all configured DNS server 
-  /// used by EFI_DNS4_PROTOCOL instances. List will include 
-  /// DNS servers configured by this or any other EFI_DNS4_PROTOCOL instance. 
-  /// The storage for this list is allocated by the driver publishing this 
+  /// Pointer to common list of addresses of all configured DNS server
+  /// used by EFI_DNS4_PROTOCOL instances. List will include
+  /// DNS servers configured by this or any other EFI_DNS4_PROTOCOL instance.
+  /// The storage for this list is allocated by the driver publishing this
   /// protocol, and must be freed by the caller.
   ///
   EFI_IPv4_ADDRESS              *DnsServerList;
@@ -147,8 +141,8 @@ typedef struct {
   ///
   UINT32                        DnsCacheCount;
   ///
-  /// Pointer to a buffer containing DnsCacheCount DNS Cache 
-  /// entry structures. The storage for this list is allocated by the driver 
+  /// Pointer to a buffer containing DnsCacheCount DNS Cache
+  /// entry structures. The storage for this list is allocated by the driver
   /// publishing this protocol and must be freed by caller.
   ///
   EFI_DNS4_CACHE_ENTRY          *DnsCacheList;
@@ -311,7 +305,7 @@ EFI_STATUS
   @retval EFI_SUCCESS             The operation completed successfully.
   @retval EFI_UNSUPPORTED         The designated protocol is not supported.
   @retval EFI_INVALID_PARAMETER   This is NULL.
-                                  The StationIp address provided in DnsConfigData is not a 
+                                  The StationIp address provided in DnsConfigData is not a
                                   valid unicast.
                                   DnsServerList is NULL while DnsServerListCount
                                   is not ZERO.
@@ -321,8 +315,8 @@ EFI_STATUS
                                   allocated.
   @retval EFI_DEVICE_ERROR        An unexpected system or network error occurred. The
                                   EFI DNSv4 Protocol instance is not configured.
-  @retval EFI_ALREADY_STARTED     Second call to Configure() with DnsConfigData. To 
-                                  reconfigure the instance the caller must call Configure() 
+  @retval EFI_ALREADY_STARTED     Second call to Configure() with DnsConfigData. To
+                                  reconfigure the instance the caller must call Configure()
                                   with NULL first to return driver to unconfigured state.
 **/
 typedef
@@ -363,7 +357,7 @@ EFI_STATUS
 /**
   IPv4 address to host name translation also known as Reverse DNS lookup.
 
-  The IpToHostName() function is used to translate the host address to host name. A type PTR 
+  The IpToHostName() function is used to translate the host address to host name. A type PTR
   query is used to get the primary name of the host. Support of this function is optional.
 
   @param[in]  This                Pointer to EFI_DNS4_PROTOCOL instance.
@@ -391,7 +385,7 @@ EFI_STATUS
   );
 
 /**
-  Retrieve arbitrary information from the DNS server. 
+  Retrieve arbitrary information from the DNS server.
 
   This GeneralLookup() function retrieves arbitrary information from the DNS. The caller
   supplies a QNAME, QTYPE, and QCLASS, and all of the matching RRs are returned. All
diff --git a/MdePkg/Include/Protocol/Dns6.h b/MdePkg/Include/Protocol/Dns6.h
index bf8814606e4d..9839b822c146 100644
--- a/MdePkg/Include/Protocol/Dns6.h
+++ b/MdePkg/Include/Protocol/Dns6.h
@@ -4,14 +4,8 @@
   DNSv6 Service Binding Protocol (DNSv6SB)
   DNSv6 Protocol (DNSv6)
 
-  Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution. The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This Protocol is introduced in UEFI Specification 2.5
@@ -49,8 +43,8 @@ typedef struct {
   ///
   UINT8                         Protocol;
   ///
-  /// The local IP address to use. Set to zero to let the underlying IPv6 
-  /// driver choose a source address. If not zero it must be one of the 
+  /// The local IP address to use. Set to zero to let the underlying IPv6
+  /// driver choose a source address. If not zero it must be one of the
   /// configured IP addresses in the underlying IPv6 driver.
   ///
   EFI_IPv6_ADDRESS              StationIp;
@@ -59,23 +53,23 @@ typedef struct {
   ///
   UINT16                        LocalPort;
   ///
-  /// Count of the DNS servers. When used with GetModeData(), 
-  /// this field is the count of originally configured servers when 
-  /// Configure() was called for this instance. When used with 
-  /// Configure() this is the count of caller-supplied servers. If the 
-  /// DnsServerListCount is zero, the DNS server configuration 
+  /// Count of the DNS servers. When used with GetModeData(),
+  /// this field is the count of originally configured servers when
+  /// Configure() was called for this instance. When used with
+  /// Configure() this is the count of caller-supplied servers. If the
+  /// DnsServerListCount is zero, the DNS server configuration
   /// will be retrieved from DHCP server automatically.
   ///
   UINT32                        DnsServerCount;
   ///
   /// Pointer to DNS server list containing DnsServerListCount
-  /// entries or NULL if DnsServerListCount is 0. For Configure(), 
-  /// this will be NULL when there are no caller supplied server addresses 
-  /// and the DNS instance will retrieve DNS server from DHCP Server. 
-  /// The provided DNS server list is recommended to be filled up in the sequence 
-  /// of preference. When used with GetModeData(), the buffer containing the list 
-  /// will be allocated by the driver implementing this protocol and must be 
-  /// freed by the caller. When used with Configure(), the buffer 
+  /// entries or NULL if DnsServerListCount is 0. For Configure(),
+  /// this will be NULL when there are no caller supplied server addresses
+  /// and the DNS instance will retrieve DNS server from DHCP Server.
+  /// The provided DNS server list is recommended to be filled up in the sequence
+  /// of preference. When used with GetModeData(), the buffer containing the list
+  /// will be allocated by the driver implementing this protocol and must be
+  /// freed by the caller. When used with Configure(), the buffer
   /// containing the list will be allocated and released by the caller.
   ///
   EFI_IPv6_ADDRESS              *DnsServerList;
@@ -121,21 +115,21 @@ typedef struct {
   ///
   /// Number of configured DNS6 servers.
   ///
-  UINT32               	        DnsServerCount;
+  UINT32                         DnsServerCount;
   ///
-  /// Pointer to common list of addresses of all configured DNS server used by EFI_DNS6_PROTOCOL 
-  /// instances. List will include DNS servers configured by this or any other EFI_DNS6_PROTOCOL 
-  /// instance. The storage for this list is allocated by the driver publishing this protocol, 
+  /// Pointer to common list of addresses of all configured DNS server used by EFI_DNS6_PROTOCOL
+  /// instances. List will include DNS servers configured by this or any other EFI_DNS6_PROTOCOL
+  /// instance. The storage for this list is allocated by the driver publishing this protocol,
   /// and must be freed by the caller.
   ///
-  EFI_IPv6_ADDRESS     	        *DnsServerList;
+  EFI_IPv6_ADDRESS               *DnsServerList;
   ///
   /// Number of DNS Cache entries. The DNS Cache is shared among all DNS instances.
   ///
   UINT32                        DnsCacheCount;
   ///
-  /// Pointer to a buffer containing DnsCacheCount DNS Cache 
-  /// entry structures. The storage for thislist is allocated by the driver 
+  /// Pointer to a buffer containing DnsCacheCount DNS Cache
+  /// entry structures. The storage for thislist is allocated by the driver
   /// publishing this protocol and must be freed by caller.
   ///
   EFI_DNS6_CACHE_ENTRY          *DnsCacheList;
@@ -272,7 +266,7 @@ typedef struct {
   This function is used to retrieve DNS mode data for this DNS instance.
 
   @param[in]   This                Pointer to EFI_DNS6_PROTOCOL instance.
-  @param[out]  DnsModeData         Pointer to the caller-allocated storage for the 
+  @param[out]  DnsModeData         Pointer to the caller-allocated storage for the
                                    EFI_DNS6_MODE_DATA data.
 
   @retval EFI_SUCCESS             The operation completed successfully.
@@ -296,7 +290,7 @@ EFI_STATUS
   EFI DNSv6 Protocol driver instance. Reset the DNS instance if DnsConfigData is NULL.
 
   @param[in]  This                Pointer to EFI_DNS6_PROTOCOL instance.
-  @param[in]  DnsConfigData       Pointer to the configuration data structure. All associated 
+  @param[in]  DnsConfigData       Pointer to the configuration data structure. All associated
                                   storage to be allocated and released by caller.
 
   @retval EFI_SUCCESS             The operation completed successfully.
@@ -308,8 +302,8 @@ EFI_STATUS
   @retval EFI_DEVICE_ERROR        An unexpected system or network error occurred. The
                                   EFI DNSv6 Protocol instance is not configured.
   @retval EFI_UNSUPPORTED         The designated protocol is not supported.
-  @retval EFI_ALREADY_STARTED     Second call to Configure() with DnsConfigData. To 
-                                  reconfigure the instance the caller must call Configure() with 
+  @retval EFI_ALREADY_STARTED     Second call to Configure() with DnsConfigData. To
+                                  reconfigure the instance the caller must call Configure() with
                                   NULL first to return driver to unconfigured state.
 **/
 typedef
diff --git a/MdePkg/Include/Protocol/DriverBinding.h b/MdePkg/Include/Protocol/DriverBinding.h
index b325c0ccf7a3..fca636f22dae 100644
--- a/MdePkg/Include/Protocol/DriverBinding.h
+++ b/MdePkg/Include/Protocol/DriverBinding.h
@@ -1,17 +1,11 @@
 /** @file
   UEFI DriverBinding Protocol is defined in UEFI specification.
-  
-  This protocol is produced by every driver that follows the UEFI Driver Model, 
+
+  This protocol is produced by every driver that follows the UEFI Driver Model,
   and it is the central component that allows drivers and controllers to be managed.
 
-Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -29,33 +23,33 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 typedef struct _EFI_DRIVER_BINDING_PROTOCOL  EFI_DRIVER_BINDING_PROTOCOL;
 
 /**
-  Tests to see if this driver supports a given controller. If a child device is provided, 
+  Tests to see if this driver supports a given controller. If a child device is provided,
   it further tests to see if this driver supports creating a handle for the specified child device.
 
-  This function checks to see if the driver specified by This supports the device specified by 
-  ControllerHandle. Drivers will typically use the device path attached to 
-  ControllerHandle and/or the services from the bus I/O abstraction attached to 
-  ControllerHandle to determine if the driver supports ControllerHandle. This function 
-  may be called many times during platform initialization. In order to reduce boot times, the tests 
-  performed by this function must be very small, and take as little time as possible to execute. This 
-  function must not change the state of any hardware devices, and this function must be aware that the 
-  device specified by ControllerHandle may already be managed by the same driver or a 
-  different driver. This function must match its calls to AllocatePages() with FreePages(), 
-  AllocatePool() with FreePool(), and OpenProtocol() with CloseProtocol().  
-  Because ControllerHandle may have been previously started by the same driver, if a protocol is 
-  already in the opened state, then it must not be closed with CloseProtocol(). This is required 
+  This function checks to see if the driver specified by This supports the device specified by
+  ControllerHandle. Drivers will typically use the device path attached to
+  ControllerHandle and/or the services from the bus I/O abstraction attached to
+  ControllerHandle to determine if the driver supports ControllerHandle. This function
+  may be called many times during platform initialization. In order to reduce boot times, the tests
+  performed by this function must be very small, and take as little time as possible to execute. This
+  function must not change the state of any hardware devices, and this function must be aware that the
+  device specified by ControllerHandle may already be managed by the same driver or a
+  different driver. This function must match its calls to AllocatePages() with FreePages(),
+  AllocatePool() with FreePool(), and OpenProtocol() with CloseProtocol().
+  Because ControllerHandle may have been previously started by the same driver, if a protocol is
+  already in the opened state, then it must not be closed with CloseProtocol(). This is required
   to guarantee the state of ControllerHandle is not modified by this function.
 
   @param[in]  This                 A pointer to the EFI_DRIVER_BINDING_PROTOCOL instance.
-  @param[in]  ControllerHandle     The handle of the controller to test. This handle 
-                                   must support a protocol interface that supplies 
+  @param[in]  ControllerHandle     The handle of the controller to test. This handle
+                                   must support a protocol interface that supplies
                                    an I/O abstraction to the driver.
-  @param[in]  RemainingDevicePath  A pointer to the remaining portion of a device path.  This 
-                                   parameter is ignored by device drivers, and is optional for bus 
-                                   drivers. For bus drivers, if this parameter is not NULL, then 
-                                   the bus driver must determine if the bus controller specified 
-                                   by ControllerHandle and the child controller specified 
-                                   by RemainingDevicePath are both supported by this 
+  @param[in]  RemainingDevicePath  A pointer to the remaining portion of a device path.  This
+                                   parameter is ignored by device drivers, and is optional for bus
+                                   drivers. For bus drivers, if this parameter is not NULL, then
+                                   the bus driver must determine if the bus controller specified
+                                   by ControllerHandle and the child controller specified
+                                   by RemainingDevicePath are both supported by this
                                    bus driver.
 
   @retval EFI_SUCCESS              The device specified by ControllerHandle and
@@ -82,28 +76,28 @@ EFI_STATUS
   Starts a device controller or a bus controller.
 
   The Start() function is designed to be invoked from the EFI boot service ConnectController().
-  As a result, much of the error checking on the parameters to Start() has been moved into this 
-  common boot service. It is legal to call Start() from other locations, 
+  As a result, much of the error checking on the parameters to Start() has been moved into this
+  common boot service. It is legal to call Start() from other locations,
   but the following calling restrictions must be followed, or the system behavior will not be deterministic.
   1. ControllerHandle must be a valid EFI_HANDLE.
   2. If RemainingDevicePath is not NULL, then it must be a pointer to a naturally aligned
      EFI_DEVICE_PATH_PROTOCOL.
   3. Prior to calling Start(), the Supported() function for the driver specified by This must
-     have been called with the same calling parameters, and Supported() must have returned EFI_SUCCESS.  
+     have been called with the same calling parameters, and Supported() must have returned EFI_SUCCESS.
 
   @param[in]  This                 A pointer to the EFI_DRIVER_BINDING_PROTOCOL instance.
-  @param[in]  ControllerHandle     The handle of the controller to start. This handle 
-                                   must support a protocol interface that supplies 
+  @param[in]  ControllerHandle     The handle of the controller to start. This handle
+                                   must support a protocol interface that supplies
                                    an I/O abstraction to the driver.
-  @param[in]  RemainingDevicePath  A pointer to the remaining portion of a device path.  This 
-                                   parameter is ignored by device drivers, and is optional for bus 
-                                   drivers. For a bus driver, if this parameter is NULL, then handles 
-                                   for all the children of Controller are created by this driver.  
-                                   If this parameter is not NULL and the first Device Path Node is 
-                                   not the End of Device Path Node, then only the handle for the 
-                                   child device specified by the first Device Path Node of 
+  @param[in]  RemainingDevicePath  A pointer to the remaining portion of a device path.  This
+                                   parameter is ignored by device drivers, and is optional for bus
+                                   drivers. For a bus driver, if this parameter is NULL, then handles
+                                   for all the children of Controller are created by this driver.
+                                   If this parameter is not NULL and the first Device Path Node is
+                                   not the End of Device Path Node, then only the handle for the
+                                   child device specified by the first Device Path Node of
                                    RemainingDevicePath is created by this driver.
-                                   If the first Device Path Node of RemainingDevicePath is 
+                                   If the first Device Path Node of RemainingDevicePath is
                                    the End of Device Path Node, no child handle is created by this
                                    driver.
 
@@ -123,10 +117,10 @@ EFI_STATUS
 
 /**
   Stops a device controller or a bus controller.
-  
-  The Stop() function is designed to be invoked from the EFI boot service DisconnectController(). 
-  As a result, much of the error checking on the parameters to Stop() has been moved 
-  into this common boot service. It is legal to call Stop() from other locations, 
+
+  The Stop() function is designed to be invoked from the EFI boot service DisconnectController().
+  As a result, much of the error checking on the parameters to Stop() has been moved
+  into this common boot service. It is legal to call Stop() from other locations,
   but the following calling restrictions must be followed, or the system behavior will not be deterministic.
   1. ControllerHandle must be a valid EFI_HANDLE that was used on a previous call to this
      same driver's Start() function.
@@ -134,13 +128,13 @@ EFI_STATUS
      EFI_HANDLE. In addition, all of these handles must have been created in this driver's
      Start() function, and the Start() function must have called OpenProtocol() on
      ControllerHandle with an Attribute of EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER.
-  
+
   @param[in]  This              A pointer to the EFI_DRIVER_BINDING_PROTOCOL instance.
-  @param[in]  ControllerHandle  A handle to the device being stopped. The handle must 
-                                support a bus specific I/O protocol for the driver 
+  @param[in]  ControllerHandle  A handle to the device being stopped. The handle must
+                                support a bus specific I/O protocol for the driver
                                 to use to stop the device.
   @param[in]  NumberOfChildren  The number of child device handles in ChildHandleBuffer.
-  @param[in]  ChildHandleBuffer An array of child handles to be freed. May be NULL 
+  @param[in]  ChildHandleBuffer An array of child handles to be freed. May be NULL
                                 if NumberOfChildren is 0.
 
   @retval EFI_SUCCESS           The device was stopped.
@@ -157,14 +151,14 @@ EFI_STATUS
   );
 
 ///
-/// This protocol provides the services required to determine if a driver supports a given controller. 
+/// This protocol provides the services required to determine if a driver supports a given controller.
 /// If a controller is supported, then it also provides routines to start and stop the controller.
 ///
 struct _EFI_DRIVER_BINDING_PROTOCOL {
   EFI_DRIVER_BINDING_SUPPORTED  Supported;
   EFI_DRIVER_BINDING_START      Start;
   EFI_DRIVER_BINDING_STOP       Stop;
-  
+
   ///
   /// The version number of the UEFI driver that produced the
   /// EFI_DRIVER_BINDING_PROTOCOL. This field is used by
@@ -178,20 +172,20 @@ struct _EFI_DRIVER_BINDING_PROTOCOL {
   /// 0xffffffef are reserved for IHV-developed drivers.
   ///
   UINT32                        Version;
-  
+
   ///
   /// The image handle of the UEFI driver that produced this instance
   /// of the EFI_DRIVER_BINDING_PROTOCOL.
   ///
   EFI_HANDLE                    ImageHandle;
-  
+
   ///
   /// The handle on which this instance of the
   /// EFI_DRIVER_BINDING_PROTOCOL is installed. In most
   /// cases, this is the same handle as ImageHandle. However, for
   /// UEFI drivers that produce more than one instance of the
   /// EFI_DRIVER_BINDING_PROTOCOL, this value may not be
-  /// the same as ImageHandle.  
+  /// the same as ImageHandle.
   ///
   EFI_HANDLE                    DriverBindingHandle;
 };
diff --git a/MdePkg/Include/Protocol/DriverConfiguration.h b/MdePkg/Include/Protocol/DriverConfiguration.h
index 53c5296720b1..2a0018fabd30 100644
--- a/MdePkg/Include/Protocol/DriverConfiguration.h
+++ b/MdePkg/Include/Protocol/DriverConfiguration.h
@@ -1,14 +1,8 @@
 /** @file
   EFI Driver Configuration Protocol
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -24,11 +18,11 @@
   { \
     0x107a772b, 0xd5e1, 0x11d4, {0x9a, 0x46, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \
   }
- 
+
 typedef struct _EFI_DRIVER_CONFIGURATION_PROTOCOL  EFI_DRIVER_CONFIGURATION_PROTOCOL;
 
 /**
-  Allows the user to set controller specific options for a controller that a 
+  Allows the user to set controller specific options for a controller that a
   driver is currently managing.
 
   @param  This             A pointer to the EFI_DRIVER_CONFIGURATION_PROTOCOL instance.
@@ -154,9 +148,9 @@ struct _EFI_DRIVER_CONFIGURATION_PROTOCOL {
   EFI_DRIVER_CONFIGURATION_OPTIONS_VALID  OptionsValid;
   EFI_DRIVER_CONFIGURATION_FORCE_DEFAULTS ForceDefaults;
   ///
-  /// A Null-terminated ASCII string that contains one or more 
-  /// ISO 639-2 language codes.  This is the list of language 
-  /// codes that this protocol supports.  
+  /// A Null-terminated ASCII string that contains one or more
+  /// ISO 639-2 language codes.  This is the list of language
+  /// codes that this protocol supports.
   ///
   CHAR8                                   *SupportedLanguages;
 };
diff --git a/MdePkg/Include/Protocol/DriverConfiguration2.h b/MdePkg/Include/Protocol/DriverConfiguration2.h
index 1610eb4741af..066968670b16 100644
--- a/MdePkg/Include/Protocol/DriverConfiguration2.h
+++ b/MdePkg/Include/Protocol/DriverConfiguration2.h
@@ -1,14 +1,8 @@
 /** @file
   UEFI Driver Configuration2 Protocol
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -22,7 +16,7 @@
   { \
     0xbfd7dc1d, 0x24f1, 0x40d9, {0x82, 0xe7, 0x2e, 0x09, 0xbb, 0x6b, 0x4e, 0xbe } \
   }
-  
+
 typedef struct _EFI_DRIVER_CONFIGURATION2_PROTOCOL  EFI_DRIVER_CONFIGURATION2_PROTOCOL;
 
 typedef enum {
@@ -55,7 +49,7 @@ typedef enum {
 #define EFI_DRIVER_CONFIGURATION_PERORMANCE_DEFAULTS    0x00000003
 
 /**
-  Allows the user to set controller specific options for a controller that a 
+  Allows the user to set controller specific options for a controller that a
   driver is currently managing.
 
   @param  This             A pointer to the EFI_DRIVER_CONFIGURATION2_PROTOCOL instance.
@@ -180,7 +174,7 @@ struct _EFI_DRIVER_CONFIGURATION2_PROTOCOL {
   EFI_DRIVER_CONFIGURATION2_FORCE_DEFAULTS  ForceDefaults;
   ///
   /// A Null-terminated ASCII string that contains one or more RFC 4646
-  /// language codes.  This is the list of language codes that this protocol supports.  
+  /// language codes.  This is the list of language codes that this protocol supports.
   ///
   CHAR8                                     *SupportedLanguages;
 };
diff --git a/MdePkg/Include/Protocol/DriverDiagnostics.h b/MdePkg/Include/Protocol/DriverDiagnostics.h
index 431b649223e5..53ebe0852901 100644
--- a/MdePkg/Include/Protocol/DriverDiagnostics.h
+++ b/MdePkg/Include/Protocol/DriverDiagnostics.h
@@ -1,14 +1,8 @@
 /** @file
   EFI Driver Diagnostics Protocol
 
-Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -41,7 +35,7 @@ typedef enum {
   ///
   EfiDriverDiagnosticTypeManufacturing= 2,
   ///
-  /// This is an optional diagnostic type that would only be used in the situation where an 
+  /// This is an optional diagnostic type that would only be used in the situation where an
   /// EFI_NOT_READY had been returned by a previous call to RunDiagnostics()
   /// and there is a desire to cancel the current running diagnostics operation.
   ///
@@ -121,8 +115,8 @@ struct _EFI_DRIVER_DIAGNOSTICS_PROTOCOL {
   EFI_DRIVER_DIAGNOSTICS_RUN_DIAGNOSTICS  RunDiagnostics;
   ///
   /// A Null-terminated ASCII string that contains one or more ISO 639-2
-  /// language codes.  This is the list of language codes that this protocol supports.  
-  ///  
+  /// language codes.  This is the list of language codes that this protocol supports.
+  ///
   CHAR8                                   *SupportedLanguages;
 };
 
diff --git a/MdePkg/Include/Protocol/DriverDiagnostics2.h b/MdePkg/Include/Protocol/DriverDiagnostics2.h
index 78d5ec6fe93e..b0b4c8cd6789 100644
--- a/MdePkg/Include/Protocol/DriverDiagnostics2.h
+++ b/MdePkg/Include/Protocol/DriverDiagnostics2.h
@@ -1,14 +1,8 @@
 /** @file
   UEFI Driver Diagnostics2 Protocol
 
-  Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -21,7 +15,7 @@
   { \
     0x4d330321, 0x025f, 0x4aac, {0x90, 0xd8, 0x5e, 0xd9, 0x00, 0x17, 0x3b, 0x63 } \
   }
-  
+
 typedef struct _EFI_DRIVER_DIAGNOSTICS2_PROTOCOL  EFI_DRIVER_DIAGNOSTICS2_PROTOCOL;
 
 /**
@@ -31,7 +25,7 @@ typedef struct _EFI_DRIVER_DIAGNOSTICS2_PROTOCOL  EFI_DRIVER_DIAGNOSTICS2_PROTOC
   @param  ControllerHandle The handle of the controller to run diagnostics on.
   @param  ChildHandle      The handle of the child controller to run diagnostics on
                            This is an optional parameter that may be NULL.  It will
-                           be NULL for device drivers.  It will also be NULL for 
+                           be NULL for device drivers.  It will also be NULL for
                            bus drivers that wish to run diagnostics on the bus
                            controller.  It will not be NULL for a bus driver that
                            wishes to run diagnostics on one of its child controllers.
@@ -101,8 +95,8 @@ struct _EFI_DRIVER_DIAGNOSTICS2_PROTOCOL {
   EFI_DRIVER_DIAGNOSTICS2_RUN_DIAGNOSTICS RunDiagnostics;
   ///
   /// A Null-terminated ASCII string that contains one or more RFC 4646
-  /// language codes.  This is the list of language codes that this protocol supports.  
-  ///    
+  /// language codes.  This is the list of language codes that this protocol supports.
+  ///
   CHAR8                                   *SupportedLanguages;
 };
 
diff --git a/MdePkg/Include/Protocol/DriverFamilyOverride.h b/MdePkg/Include/Protocol/DriverFamilyOverride.h
index 868c7734117a..5b06f0b0e025 100644
--- a/MdePkg/Include/Protocol/DriverFamilyOverride.h
+++ b/MdePkg/Include/Protocol/DriverFamilyOverride.h
@@ -1,14 +1,8 @@
 /** @file
   UEFI Driver Family Protocol
 
-Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -19,14 +13,14 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   { \
     0xb1ee129e, 0xda36, 0x4181, { 0x91, 0xf8, 0x4, 0xa4, 0x92, 0x37, 0x66, 0xa7 } \
   }
-  
+
 typedef struct _EFI_DRIVER_FAMILY_OVERRIDE_PROTOCOL  EFI_DRIVER_FAMILY_OVERRIDE_PROTOCOL;
 
 //
 // Prototypes for the Driver Family Override Protocol
 //
-// 
-/**                                                                 
+//
+/**
   This function returns the version value associated with the driver specified by This.
 
   Retrieves the version of the driver that is used by the EFI Boot Service ConnectController()
@@ -35,10 +29,10 @@ typedef struct _EFI_DRIVER_FAMILY_OVERRIDE_PROTOCOL  EFI_DRIVER_FAMILY_OVERRIDE_
   the drivers with higher values returned by GetVersion() are higher priority than drivers that
   return lower values from GetVersion().
 
-  @param  This                  A pointer to the EFI_DRIVER_FAMILY_OVERRIDE_PROTOCOL instance.                            
-                                
-  @return The version value associated with the driver specified by This.                                  
-                                   
+  @param  This                  A pointer to the EFI_DRIVER_FAMILY_OVERRIDE_PROTOCOL instance.
+
+  @return The version value associated with the driver specified by This.
+
 **/
 typedef
 UINT32
@@ -47,15 +41,15 @@ UINT32
   );
 
 ///
-/// When installed, the Driver Family Override Protocol produces a GUID that represents 
-/// a family of drivers.  Drivers with the same GUID are members of the same family 
-/// When drivers are connected to controllers, drivers with a higher revision value 
-/// in the same driver family are connected with a higher priority than drivers 
+/// When installed, the Driver Family Override Protocol produces a GUID that represents
+/// a family of drivers.  Drivers with the same GUID are members of the same family
+/// When drivers are connected to controllers, drivers with a higher revision value
+/// in the same driver family are connected with a higher priority than drivers
 /// with a lower revision value in the same driver family.  The EFI Boot Service
-/// Connect Controller uses five rules to build a prioritized list of drivers when 
+/// Connect Controller uses five rules to build a prioritized list of drivers when
 /// a request is made to connect a driver to a controller.  The Driver Family Protocol
-/// rule is between the Platform Specific Driver Override Protocol and above the 
-/// Bus Specific Driver Override Protocol.  
+/// rule is between the Platform Specific Driver Override Protocol and above the
+/// Bus Specific Driver Override Protocol.
 ///
 struct _EFI_DRIVER_FAMILY_OVERRIDE_PROTOCOL {
   EFI_DRIVER_FAMILY_OVERRIDE_GET_VERSION GetVersion;
diff --git a/MdePkg/Include/Protocol/DriverHealth.h b/MdePkg/Include/Protocol/DriverHealth.h
index d23140d20bd1..691d205ec065 100644
--- a/MdePkg/Include/Protocol/DriverHealth.h
+++ b/MdePkg/Include/Protocol/DriverHealth.h
@@ -5,33 +5,27 @@
   the health status for a controller to be retrieved. If a controller is not in a usable
   state, status messages may be reported to the user, repair operations can be invoked,
   and the user may be asked to make software and/or hardware configuration changes.
-  
-  The Driver Health Protocol is optionally produced by a driver that follows the 
-  EFI Driver Model.  If an EFI Driver needs to report health status to the platform, 
-  provide warning or error messages to the user, perform length repair operations, 
-  or request the user to make hardware or software configuration changes, then the 
+
+  The Driver Health Protocol is optionally produced by a driver that follows the
+  EFI Driver Model.  If an EFI Driver needs to report health status to the platform,
+  provide warning or error messages to the user, perform length repair operations,
+  or request the user to make hardware or software configuration changes, then the
   Driver Health Protocol must be produced.
- 
-  A controller that is managed by driver that follows the EFI Driver Model and 
-  produces the Driver Health Protocol must report the current health of the 
-  controllers that the driver is currently managing.  The controller can initially 
-  be healthy, failed, require repair, or require configuration.  If a controller 
-  requires configuration, and the user make configuration changes, the controller 
-  may then need to be reconnected or the system may need to be rebooted for the 
-  configuration changes to take affect. 
-
-  Copyright (c) 2009 - 2013, Intel Corporation. All rights reserved.<BR>
-  Copyright (c) 2014, Hewlett-Packard Development Company, L.P.<BR>  
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+  A controller that is managed by driver that follows the EFI Driver Model and
+  produces the Driver Health Protocol must report the current health of the
+  controllers that the driver is currently managing.  The controller can initially
+  be healthy, failed, require repair, or require configuration.  If a controller
+  requires configuration, and the user make configuration changes, the controller
+  may then need to be reconnected or the system may need to be rebooted for the
+  configuration changes to take affect.
+
+  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2014, Hewlett-Packard Development Company, L.P.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
-  This Protocol is defined in UEFI Specification 2.3d 
+  This Protocol is defined in UEFI Specification 2.3d
 
 **/
 
@@ -42,7 +36,7 @@
   { \
     0x2a534210, 0x9280, 0x41d8, { 0xae, 0x79, 0xca, 0xda, 0x1, 0xa2, 0xb1, 0x27 } \
   }
-  
+
 typedef struct _EFI_DRIVER_HEALTH_PROTOCOL  EFI_DRIVER_HEALTH_PROTOCOL;
 
 ///
@@ -63,12 +57,12 @@ typedef enum {
 typedef struct {
   EFI_HII_HANDLE  HiiHandle;
   EFI_STRING_ID   StringId;
-  
+
   ///
-  /// 64-bit numeric value of the warning/error specified by this message. 
-  ///   A value of 0x0000000000000000 is used to indicate that MessageCode is not specified. 
+  /// 64-bit numeric value of the warning/error specified by this message.
+  ///   A value of 0x0000000000000000 is used to indicate that MessageCode is not specified.
   ///   The values  0x0000000000000001 to 0x0fffffffffffffff are reserved for allocation by the UEFI Specification.
-  ///   The values  0x1000000000000000 to 0x1fffffffffffffff are reserved for IHV-developed drivers. 
+  ///   The values  0x1000000000000000 to 0x1fffffffffffffff are reserved for IHV-developed drivers.
   ///   The values 0x8000000000000000 to 0x8fffffffffffffff is reserved for platform/OEM drivers.
   ///   All other values are reserved and should not be used.
   ///
@@ -78,11 +72,11 @@ typedef struct {
 /**
   Reports the progress of a repair operation
 
-  @param[in]  Value             A value between 0 and Limit that identifies the current 
+  @param[in]  Value             A value between 0 and Limit that identifies the current
                                 progress of the repair operation.
-  
+
   @param[in]  Limit             The maximum value of Value for the current repair operation.
-                                For example, a driver that wants to specify progress in 
+                                For example, a driver that wants to specify progress in
                                 percent would use a Limit value of 100.
 **/
 typedef
@@ -93,88 +87,88 @@ EFI_STATUS
   );
 
 /**
-  Retrieves the health status of a controller in the platform.  This function can also 
-  optionally return warning messages, error messages, and a set of HII Forms that may 
-  be repair a controller that is not proper configured. 
-  
+  Retrieves the health status of a controller in the platform.  This function can also
+  optionally return warning messages, error messages, and a set of HII Forms that may
+  be repair a controller that is not proper configured.
+
   @param[in] This             A pointer to the EFI_DRIVER_HEALTH_PROTOCOL instance.
 
-  @param[in] ControllerHandle The handle of the controller to retrieve the health status 
-                              on.  This is an optional parameter that may be NULL.  If 
-                              this parameter is NULL, then the value of ChildHandle is 
-                              ignored, and the combined health status of all the devices 
+  @param[in] ControllerHandle The handle of the controller to retrieve the health status
+                              on.  This is an optional parameter that may be NULL.  If
+                              this parameter is NULL, then the value of ChildHandle is
+                              ignored, and the combined health status of all the devices
                               that the driver is managing is returned.
 
-  @param[in] ChildHandle      The handle of the child controller to retrieve the health 
-                              status on.  This is an optional parameter that may be NULL.  
-                              This parameter is ignored of ControllerHandle is NULL.  It 
-                              will be NULL for device drivers.  It will also be NULL for 
-                              bus drivers when an attempt is made to collect the health 
-                              status of the bus controller.  If will not be NULL when an 
-                              attempt is made to collect the health status for a child 
+  @param[in] ChildHandle      The handle of the child controller to retrieve the health
+                              status on.  This is an optional parameter that may be NULL.
+                              This parameter is ignored of ControllerHandle is NULL.  It
+                              will be NULL for device drivers.  It will also be NULL for
+                              bus drivers when an attempt is made to collect the health
+                              status of the bus controller.  If will not be NULL when an
+                              attempt is made to collect the health status for a child
                               controller produced by the driver.
 
-  @param[out] HealthStatus    A pointer to the health status that is returned by this 
-                              function.  This is an optional parameter that may be NULL.  
-                              This parameter is ignored of ControllerHandle is NULL.  
-                              The health status for the controller specified by 
-                              ControllerHandle and ChildHandle is returned. 
-
-  @param[out] MessageList     A pointer to an array of warning or error messages associated 
-                              with the controller specified by ControllerHandle and 
-                              ChildHandle.  This is an optional parameter that may be NULL.  
-                              MessageList is allocated by this function with the EFI Boot 
-                              Service AllocatePool(), and it is the caller's responsibility 
-                              to free MessageList with the EFI Boot Service FreePool().  
-                              Each message is specified by tuple of an EFI_HII_HANDLE and 
-                              an EFI_STRING_ID.  The array of messages is terminated by tuple 
-                              containing a EFI_HII_HANDLE with a value of NULL.  The 
-                              EFI_HII_STRING_PROTOCOL.GetString() function can be used to 
-                              retrieve the warning or error message as a Null-terminated 
-                              string in a specific language.  Messages may be 
-                              returned for any of the HealthStatus values except 
-                              EfiDriverHealthStatusReconnectRequired and 
+  @param[out] HealthStatus    A pointer to the health status that is returned by this
+                              function.  This is an optional parameter that may be NULL.
+                              This parameter is ignored of ControllerHandle is NULL.
+                              The health status for the controller specified by
+                              ControllerHandle and ChildHandle is returned.
+
+  @param[out] MessageList     A pointer to an array of warning or error messages associated
+                              with the controller specified by ControllerHandle and
+                              ChildHandle.  This is an optional parameter that may be NULL.
+                              MessageList is allocated by this function with the EFI Boot
+                              Service AllocatePool(), and it is the caller's responsibility
+                              to free MessageList with the EFI Boot Service FreePool().
+                              Each message is specified by tuple of an EFI_HII_HANDLE and
+                              an EFI_STRING_ID.  The array of messages is terminated by tuple
+                              containing a EFI_HII_HANDLE with a value of NULL.  The
+                              EFI_HII_STRING_PROTOCOL.GetString() function can be used to
+                              retrieve the warning or error message as a Null-terminated
+                              string in a specific language.  Messages may be
+                              returned for any of the HealthStatus values except
+                              EfiDriverHealthStatusReconnectRequired and
                               EfiDriverHealthStatusRebootRequired.
 
-  @param[out] FormHiiHandle   A pointer to the HII handle containing the HII form used when 
-                              configuration is required. The HII handle is associated with 
+  @param[out] FormHiiHandle   A pointer to the HII handle containing the HII form used when
+                              configuration is required. The HII handle is associated with
                               the controller specified by ControllerHandle and ChildHandle.
                               If this is NULL, then no HII form is available. An HII handle
-                              will only be returned with a HealthStatus value of 
+                              will only be returned with a HealthStatus value of
                               EfiDriverHealthStatusConfigurationRequired.
 
-  @retval EFI_SUCCESS           ControllerHandle is NULL, and all the controllers 
-                                managed by this driver specified by This have a health 
-                                status of EfiDriverHealthStatusHealthy with no warning 
-                                messages to be returned.  The ChildHandle, HealthStatus, 
+  @retval EFI_SUCCESS           ControllerHandle is NULL, and all the controllers
+                                managed by this driver specified by This have a health
+                                status of EfiDriverHealthStatusHealthy with no warning
+                                messages to be returned.  The ChildHandle, HealthStatus,
                                 MessageList, and FormList parameters are ignored.
 
-  @retval EFI_DEVICE_ERROR      ControllerHandle is NULL, and one or more of the 
-                                controllers managed by this driver specified by This 
-                                do not have a health status of EfiDriverHealthStatusHealthy.  
-                                The ChildHandle, HealthStatus, MessageList, and 
+  @retval EFI_DEVICE_ERROR      ControllerHandle is NULL, and one or more of the
+                                controllers managed by this driver specified by This
+                                do not have a health status of EfiDriverHealthStatusHealthy.
+                                The ChildHandle, HealthStatus, MessageList, and
                                 FormList parameters are ignored.
 
-  @retval EFI_DEVICE_ERROR      ControllerHandle is NULL, and one or more of the 
-                                controllers managed by this driver specified by This 
-                                have one or more warning and/or error messages.  
-                                The ChildHandle, HealthStatus, MessageList, and 
+  @retval EFI_DEVICE_ERROR      ControllerHandle is NULL, and one or more of the
+                                controllers managed by this driver specified by This
+                                have one or more warning and/or error messages.
+                                The ChildHandle, HealthStatus, MessageList, and
                                 FormList parameters are ignored.
 
-  @retval EFI_SUCCESS           ControllerHandle is not NULL and the health status 
-                                of the controller specified by ControllerHandle and 
-                                ChildHandle was returned in HealthStatus.  A list 
-                                of warning and error messages may be optionally 
-                                returned in MessageList, and a list of HII Forms 
+  @retval EFI_SUCCESS           ControllerHandle is not NULL and the health status
+                                of the controller specified by ControllerHandle and
+                                ChildHandle was returned in HealthStatus.  A list
+                                of warning and error messages may be optionally
+                                returned in MessageList, and a list of HII Forms
                                 may be optionally returned in FormList.
 
-  @retval EFI_UNSUPPORTED       ControllerHandle is not NULL, and the controller 
-                                specified by ControllerHandle and ChildHandle is not 
+  @retval EFI_UNSUPPORTED       ControllerHandle is not NULL, and the controller
+                                specified by ControllerHandle and ChildHandle is not
                                 currently being managed by the driver specified by This.
 
   @retval EFI_INVALID_PARAMETER HealthStatus is NULL.
 
-  @retval EFI_OUT_OF_RESOURCES  MessageList is not NULL, and there are not enough 
+  @retval EFI_OUT_OF_RESOURCES  MessageList is not NULL, and there are not enough
                                 resource available to allocate memory for MessageList.
 
 **/
@@ -190,30 +184,30 @@ EFI_STATUS
   );
 
 /**
-  Performs a repair operation on a controller in the platform.  This function can 
-  optionally report repair progress information back to the platform. 
-  
+  Performs a repair operation on a controller in the platform.  This function can
+  optionally report repair progress information back to the platform.
+
   @param[in] This              A pointer to the EFI_DRIVER_HEALTH_PROTOCOL instance.
   @param[in] ControllerHandle  The handle of the controller to repair.
-  @param[in] ChildHandle       The handle of the child controller to repair.  This is 
-                               an optional parameter that may be NULL.  It will be NULL 
-                               for device drivers.  It will also be NULL for bus 
+  @param[in] ChildHandle       The handle of the child controller to repair.  This is
+                               an optional parameter that may be NULL.  It will be NULL
+                               for device drivers.  It will also be NULL for bus
                                drivers when an attempt is made to repair a bus controller.
-                               If will not be NULL when an attempt is made to repair a 
+                               If will not be NULL when an attempt is made to repair a
                                child controller produced by the driver.
-  @param[in] RepairNotify      A notification function that may be used by a driver to 
-                               report the progress of the repair operation.  This is 
-                               an optional parameter that may be NULL.  
+  @param[in] RepairNotify      A notification function that may be used by a driver to
+                               report the progress of the repair operation.  This is
+                               an optional parameter that may be NULL.
 
 
-  @retval EFI_SUCCESS           An attempt to repair the controller specified by 
-                                ControllerHandle and ChildHandle was performed.  
-                                The result of the repair operation can bet 
+  @retval EFI_SUCCESS           An attempt to repair the controller specified by
+                                ControllerHandle and ChildHandle was performed.
+                                The result of the repair operation can bet
                                 determined by calling GetHealthStatus().
-  @retval EFI_UNSUPPORTED       The driver specified by This is not currently 
-                                managing the controller specified by ControllerHandle 
+  @retval EFI_UNSUPPORTED       The driver specified by This is not currently
+                                managing the controller specified by ControllerHandle
                                 and ChildHandle.
-  @retval EFI_OUT_OF_RESOURCES  There are not enough resources to perform the 
+  @retval EFI_OUT_OF_RESOURCES  There are not enough resources to perform the
                                 repair operation.
 
 */
@@ -228,10 +222,10 @@ EFI_STATUS
 
 ///
 /// When installed, the Driver Health Protocol produces a collection of services
-/// that allow the health status for a controller to be retrieved.  If a controller 
-/// is not in a usable state, status messages may be reported to the user, repair 
-/// operations can be invoked, and the user may be asked to make software and/or 
-/// hardware configuration changes. 
+/// that allow the health status for a controller to be retrieved.  If a controller
+/// is not in a usable state, status messages may be reported to the user, repair
+/// operations can be invoked, and the user may be asked to make software and/or
+/// hardware configuration changes.
 ///
 struct _EFI_DRIVER_HEALTH_PROTOCOL {
   EFI_DRIVER_HEALTH_GET_HEALTH_STATUS  GetHealthStatus;
diff --git a/MdePkg/Include/Protocol/DriverSupportedEfiVersion.h b/MdePkg/Include/Protocol/DriverSupportedEfiVersion.h
index 2689ddd7f957..056ac3addfa4 100644
--- a/MdePkg/Include/Protocol/DriverSupportedEfiVersion.h
+++ b/MdePkg/Include/Protocol/DriverSupportedEfiVersion.h
@@ -4,14 +4,8 @@
   required for EFI drivers that are on PCI and other plug-in
   cards.
 
-  Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -24,16 +18,16 @@
 
 ///
 /// The EFI_DRIVER_SUPPORTED_EFI_VERSION_PROTOCOL provides a
-/// mechanism for an EFI driver to publish the version of the EFI   
-/// specification it conforms to. This protocol must be placed on   
-/// the driver's image handle when the driver's entry point is   
+/// mechanism for an EFI driver to publish the version of the EFI
+/// specification it conforms to. This protocol must be placed on
+/// the driver's image handle when the driver's entry point is
 /// called.
 ///
 typedef struct _EFI_DRIVER_SUPPORTED_EFI_VERSION_PROTOCOL {
   ///
-  /// The size, in bytes, of the entire structure. Future versions of this 
+  /// The size, in bytes, of the entire structure. Future versions of this
   /// specification may grow the size of the structure.
-  /// 
+  ///
   UINT32 Length;
   ///
   /// The latest version of the UEFI specification that this driver conforms to.
diff --git a/MdePkg/Include/Protocol/DxeMmReadyToLock.h b/MdePkg/Include/Protocol/DxeMmReadyToLock.h
new file mode 100644
index 000000000000..d406aeefc38f
--- /dev/null
+++ b/MdePkg/Include/Protocol/DxeMmReadyToLock.h
@@ -0,0 +1,19 @@
+/** @file
+  DXE MM Ready To Lock protocol introduced in the PI 1.5 specification.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _DXE_MM_READY_TO_LOCK_H_
+#define _DXE_MM_READY_TO_LOCK_H_
+
+#define EFI_DXE_MM_READY_TO_LOCK_PROTOCOL_GUID \
+  { \
+    0x60ff8964, 0xe906, 0x41d0, { 0xaf, 0xed, 0xf2, 0x41, 0xe9, 0x74, 0xe0, 0x8e } \
+  }
+
+extern EFI_GUID gEfiDxeMmReadyToLockProtocolGuid;
+
+#endif
diff --git a/MdePkg/Include/Protocol/DxeSmmReadyToLock.h b/MdePkg/Include/Protocol/DxeSmmReadyToLock.h
index 540f4cf5e204..e4756dfc3055 100644
--- a/MdePkg/Include/Protocol/DxeSmmReadyToLock.h
+++ b/MdePkg/Include/Protocol/DxeSmmReadyToLock.h
@@ -17,24 +17,17 @@
   platform code may choose to use notification handler to lock SMM by invoking
   EFI_SMM_ACCESS2_PROTOCOL.Lock() function.
 
-  Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
 #ifndef _DXE_SMM_READY_TO_LOCK_H_
 #define _DXE_SMM_READY_TO_LOCK_H_
 
-#define EFI_DXE_SMM_READY_TO_LOCK_PROTOCOL_GUID \
-  { \
-    0x60ff8964, 0xe906, 0x41d0, { 0xaf, 0xed, 0xf2, 0x41, 0xe9, 0x74, 0xe0, 0x8e } \
-  }
+#include <Protocol/DxeMmReadyToLock.h>
+
+#define EFI_DXE_SMM_READY_TO_LOCK_PROTOCOL_GUID EFI_DXE_MM_READY_TO_LOCK_PROTOCOL_GUID
 
 extern EFI_GUID gEfiDxeSmmReadyToLockProtocolGuid;
 
diff --git a/MdePkg/Include/Protocol/Eap.h b/MdePkg/Include/Protocol/Eap.h
index e91deb867006..3c2afa4cd4af 100644
--- a/MdePkg/Include/Protocol/Eap.h
+++ b/MdePkg/Include/Protocol/Eap.h
@@ -1,20 +1,14 @@
 /** @file
   EFI EAP(Extended Authenticaton Protocol) Protocol Definition
   The EFI EAP Protocol is used to abstract the ability to configure and extend the
-  EAP framework. 
+  EAP framework.
   The definitions in this file are defined in UEFI Specification 2.3.1B, which have
   not been verified by one implementation yet.
 
-  Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
+  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-  @par Revision Reference:          
+  @par Revision Reference:
   This Protocol is introduced in UEFI Specification 2.2
 
 **/
@@ -31,7 +25,7 @@
 typedef struct _EFI_EAP_PROTOCOL EFI_EAP_PROTOCOL;
 
 ///
-/// Type for the identification number assigned to the Port by the  
+/// Type for the identification number assigned to the Port by the
 /// System in which the Port resides.
 ///
 typedef VOID *  EFI_PORT_HANDLE;
@@ -61,7 +55,7 @@ typedef VOID *  EFI_PORT_HANDLE;
   @param[in]      RequestSize    Packet size in bytes for the most recently received
                                  EAP-Request packet.
   @param[in]      Buffer         Pointer to the buffer to hold the built packet.
-  @param[in, out] BufferSize     Pointer to the buffer size in bytes. 
+  @param[in, out] BufferSize     Pointer to the buffer size in bytes.
                                  On input, it is the buffer size provided by the caller.
                                  On output, it is the buffer size in fact needed to contain
                                  the packet.
@@ -74,32 +68,32 @@ typedef
 EFI_STATUS
 (EFIAPI *EFI_EAP_BUILD_RESPONSE_PACKET)(
   IN EFI_PORT_HANDLE        PortNumber,
-  IN UINT8                  *RequestBuffer, 
-  IN UINTN                  RequestSize, 
-  IN UINT8                  *Buffer, 
+  IN UINT8                  *RequestBuffer,
+  IN UINTN                  RequestSize,
+  IN UINT8                  *Buffer,
   IN OUT UINTN              *BufferSize
   );
 
 /**
   Set the desired EAP authentication method for the Port.
 
-  The SetDesiredAuthMethod() function sets the desired EAP authentication method indicated 
+  The SetDesiredAuthMethod() function sets the desired EAP authentication method indicated
   by EapAuthType for the Port.
-  
-  If EapAuthType is an invalid EAP authentication type, then EFI_INVALID_PARAMETER is 
+
+  If EapAuthType is an invalid EAP authentication type, then EFI_INVALID_PARAMETER is
   returned.
   If the EAP authentication method of EapAuthType is unsupported by the Ports, then it will
   return EFI_UNSUPPORTED.
-  The cryptographic strength of EFI_EAP_TYPE_TLS shall be at least of hash strength 
+  The cryptographic strength of EFI_EAP_TYPE_TLS shall be at least of hash strength
   SHA-256 and RSA key length of at least 2048 bits.
-  
-  @param[in] This                A pointer to the EFI_EAP_PROTOCOL instance that indicates 
+
+  @param[in] This                A pointer to the EFI_EAP_PROTOCOL instance that indicates
                                  the calling context.
-  @param[in] EapAuthType         The type of the EAP authentication method to register. It should 
+  @param[in] EapAuthType         The type of the EAP authentication method to register. It should
                                  be the type value defined by RFC. See RFC 2284 for details.
   @param[in] Handler             The handler of the EAP authentication method to register.
 
-  @retval EFI_SUCCESS            The EAP authentication method of EapAuthType is 
+  @retval EFI_SUCCESS            The EAP authentication method of EapAuthType is
                                  registered successfully.
   @retval EFI_INVALID_PARAMETER  EapAuthType is an invalid EAP authentication type.
   @retval EFI_UNSUPPORTED        The EAP authentication method of EapAuthType is
@@ -109,28 +103,28 @@ EFI_STATUS
 typedef
 EFI_STATUS
 (EFIAPI *EFI_EAP_SET_DESIRED_AUTHENTICATION_METHOD)(
-  IN EFI_EAP_PROTOCOL            *This, 
+  IN EFI_EAP_PROTOCOL            *This,
   IN UINT8                       EapAuthType
   );
 
 /**
-  Register an EAP authentication method. 
+  Register an EAP authentication method.
+
+  The RegisterAuthMethod() function registers the user provided EAP authentication method,
+  the type of which is EapAuthType and the handler of which is Handler.
 
-  The RegisterAuthMethod() function registers the user provided EAP authentication method, 
-  the type of which is EapAuthType and the handler of which is Handler. 
-  
-  If EapAuthType is an invalid EAP authentication type, then EFI_INVALID_PARAMETER is 
+  If EapAuthType is an invalid EAP authentication type, then EFI_INVALID_PARAMETER is
   returned.
-  If there is not enough system memory to perform the registration, then 
+  If there is not enough system memory to perform the registration, then
   EFI_OUT_OF_RESOURCES is returned.
 
-  @param[in] This                A pointer to the EFI_EAP_PROTOCOL instance that indicates 
+  @param[in] This                A pointer to the EFI_EAP_PROTOCOL instance that indicates
                                  the calling context.
-  @param[in] EapAuthType         The type of the EAP authentication method to register. It should 
+  @param[in] EapAuthType         The type of the EAP authentication method to register. It should
                                  be the type value defined by RFC. See RFC 2284 for details.
   @param[in] Handler             The handler of the EAP authentication method to register.
 
-  @retval EFI_SUCCESS            The EAP authentication method of EapAuthType is 
+  @retval EFI_SUCCESS            The EAP authentication method of EapAuthType is
                                  registered successfully.
   @retval EFI_INVALID_PARAMETER  EapAuthType is an invalid EAP authentication type.
   @retval EFI_OUT_OF_RESOURCES   There is not enough system memory to perform the registration.
@@ -139,17 +133,17 @@ EFI_STATUS
 typedef
 EFI_STATUS
 (EFIAPI *EFI_EAP_REGISTER_AUTHENTICATION_METHOD)(
-  IN EFI_EAP_PROTOCOL                     *This, 
-  IN UINT8                                EapAuthType, 
+  IN EFI_EAP_PROTOCOL                     *This,
+  IN UINT8                                EapAuthType,
   IN EFI_EAP_BUILD_RESPONSE_PACKET        Handler
   );
 
 ///
-/// EFI_EAP_PROTOCOL 
-/// is used to configure the desired EAP authentication method for the EAP 
+/// EFI_EAP_PROTOCOL
+/// is used to configure the desired EAP authentication method for the EAP
 /// framework and extend the EAP framework by registering new EAP authentication
 /// method on a Port. The EAP framework is built on a per-Port basis. Herein, a
-/// Port means a NIC. For the details of EAP protocol, please refer to RFC 2284. 
+/// Port means a NIC. For the details of EAP protocol, please refer to RFC 2284.
 ///
 struct _EFI_EAP_PROTOCOL {
   EFI_EAP_SET_DESIRED_AUTHENTICATION_METHOD   SetDesiredAuthMethod;
diff --git a/MdePkg/Include/Protocol/EapConfiguration.h b/MdePkg/Include/Protocol/EapConfiguration.h
index dc30e62ad033..698d835410a2 100644
--- a/MdePkg/Include/Protocol/EapConfiguration.h
+++ b/MdePkg/Include/Protocol/EapConfiguration.h
@@ -1,14 +1,8 @@
 /** @file
   This file defines the EFI EAP Configuration protocol.
 
-  Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution. The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This Protocol is introduced in UEFI Specification 2.5
@@ -156,4 +150,4 @@ struct _EFI_EAP_CONFIGURATION_PROTOCOL {
 
 extern EFI_GUID gEfiEapConfigurationProtocolGuid;
 
-#endif
\ No newline at end of file
+#endif
diff --git a/MdePkg/Include/Protocol/EapManagement.h b/MdePkg/Include/Protocol/EapManagement.h
index 8fe4afb2a17d..c65bc1bdf032 100644
--- a/MdePkg/Include/Protocol/EapManagement.h
+++ b/MdePkg/Include/Protocol/EapManagement.h
@@ -1,21 +1,15 @@
 /** @file
   EFI EAP Management Protocol Definition
   The EFI EAP Management Protocol is designed to provide ease of management and
-  ease of test for EAPOL state machine. It is intended for the supplicant side. 
-  It conforms to IEEE 802.1x specification. 
+  ease of test for EAPOL state machine. It is intended for the supplicant side.
+  It conforms to IEEE 802.1x specification.
   The definitions in this file are defined in UEFI Specification 2.2, which have
   not been verified by one implementation yet.
 
-  Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
+  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-  @par Revision Reference:          
+  @par Revision Reference:
   This Protocol is introduced in UEFI Specification 2.2
 
 **/
@@ -43,22 +37,22 @@ typedef struct _EFI_EAP_MANAGEMENT_PROTOCOL EFI_EAP_MANAGEMENT_PROTOCOL;
 ///
 /// EFI_EAPOL_PORT_INFO
 ///
-typedef struct _EFI_EAPOL_PORT_INFO {      
-  /// 
-  /// The identification number assigned to the Port by the System in 
+typedef struct _EFI_EAPOL_PORT_INFO {
+  ///
+  /// The identification number assigned to the Port by the System in
   /// which the Port resides.
-  /// 
+  ///
   EFI_PORT_HANDLE     PortNumber;
-  /// 
-  /// The protocol version number of the EAPOL implementation 
-  /// supported by the Port. 
-  /// 
+  ///
+  /// The protocol version number of the EAPOL implementation
+  /// supported by the Port.
+  ///
   UINT8               ProtocolVersion;
-  /// 
-  /// The capabilities of the PAE associated with the Port. This field 
-  /// indicates whether Authenticator functionality, Supplicant 
+  ///
+  /// The capabilities of the PAE associated with the Port. This field
+  /// indicates whether Authenticator functionality, Supplicant
   /// functionality, both, or neither, is supported by the Port's PAE.
-  /// 
+  ///
   UINT8               PaeCapabilities;
 } EFI_EAPOL_PORT_INFO;
 
@@ -77,7 +71,7 @@ typedef enum _EFI_EAPOL_SUPPLICANT_PAE_STATE {
 } EFI_EAPOL_SUPPLICANT_PAE_STATE;
 
 ///
-/// Definitions for ValidFieldMask 
+/// Definitions for ValidFieldMask
 ///
 ///@{
 #define AUTH_PERIOD_FIELD_VALID       0x01
@@ -90,27 +84,27 @@ typedef enum _EFI_EAPOL_SUPPLICANT_PAE_STATE {
 /// EFI_EAPOL_SUPPLICANT_PAE_CONFIGURATION
 ///
 typedef struct _EFI_EAPOL_SUPPLICANT_PAE_CONFIGURATION {
-  /// 
+  ///
   /// Indicates which of the following fields are valid.
-  /// 
-  UINT8       ValidFieldMask;  
+  ///
+  UINT8       ValidFieldMask;
   ///
   /// The initial value for the authWhile timer. Its default value is 30s.
   ///
-  UINTN       AuthPeriod;   
+  UINTN       AuthPeriod;
+  ///
+  /// The initial value for the heldWhile timer. Its default value is 60s.
   ///
-  /// The initial value for the heldWhile timer. Its default value is 60s. 
+  UINTN       HeldPeriod;
   ///
-  UINTN       HeldPeriod;    
+  /// The initial value for the startWhen timer. Its default value is 30s.
   ///
-  /// The initial value for the startWhen timer. Its default value is 30s. 
+  UINTN       StartPeriod;
   ///
-  UINTN       StartPeriod;    
-  ///   
-  /// The maximum number of successive EAPOL-Start messages will 
-  /// be sent before the Supplicant assumes that there is no 
+  /// The maximum number of successive EAPOL-Start messages will
+  /// be sent before the Supplicant assumes that there is no
   /// Authenticator present. Its default value is 3.
-  /// 
+  ///
   UINTN       MaxStart;
 } EFI_EAPOL_SUPPLICANT_PAE_CONFIGURATION;
 
@@ -120,17 +114,17 @@ typedef struct _EFI_EAPOL_SUPPLICANT_PAE_CONFIGURATION {
 typedef struct _EFI_EAPOL_SUPPLICANT_PAE_STATISTICS {
   ///
   /// The number of EAPOL frames of any type that have been received by this Supplican.
-  /// 
+  ///
   UINTN     EapolFramesReceived;
   ///
-  /// The number of EAPOL frames of any type that have been transmitted by this Supplicant. 
+  /// The number of EAPOL frames of any type that have been transmitted by this Supplicant.
   ///
   UINTN     EapolFramesTransmitted;
-  /// 
-  /// The number of EAPOL Start frames that have been transmitted by this Supplicant. 
-  /// 
+  ///
+  /// The number of EAPOL Start frames that have been transmitted by this Supplicant.
+  ///
   UINTN     EapolStartFramesTransmitted;
-  /// 
+  ///
   /// The number of EAPOL Logoff frames that have been transmitted by this Supplicant.
   ///
   UINTN     EapolLogoffFramesTransmitted;
@@ -138,48 +132,48 @@ typedef struct _EFI_EAPOL_SUPPLICANT_PAE_STATISTICS {
   /// The number of EAP Resp/Id frames that have been transmitted by this Supplicant.
   ///
   UINTN     EapRespIdFramesTransmitted;
-  ///   
-  /// The number of valid EAP Response frames (other than Resp/Id frames) that have been 
+  ///
+  /// The number of valid EAP Response frames (other than Resp/Id frames) that have been
   /// transmitted by this Supplicant.
   ///
   UINTN     EapResponseFramesTransmitted;
-  /// 
+  ///
   /// The number of EAP Req/Id frames that have been received by this Supplicant.
-  /// 
+  ///
   UINTN     EapReqIdFramesReceived;
   ///
-  /// The number of EAP Request frames (other than Rq/Id frames) that have been received 
+  /// The number of EAP Request frames (other than Rq/Id frames) that have been received
   /// by this Supplicant.
   ///
   UINTN     EapRequestFramesReceived;
   ///
-  /// The number of EAPOL frames that have been received by this Supplicant in which the 
+  /// The number of EAPOL frames that have been received by this Supplicant in which the
   /// frame type is not recognized.
   ///
   UINTN     InvalidEapolFramesReceived;
-  /// 
-  /// The number of EAPOL frames that have been received by this Supplicant in which the 
+  ///
+  /// The number of EAPOL frames that have been received by this Supplicant in which the
   /// Packet Body Length field (7.5.5) is invalid.
-  /// 
+  ///
   UINTN     EapLengthErrorFramesReceived;
-  /// 
+  ///
   /// The protocol version number carried in the most recently received EAPOL frame.
-  /// 
+  ///
   UINTN     LastEapolFrameVersion;
-  /// 
+  ///
   /// The source MAC address carried in the most recently received EAPOL frame.
-  /// 
+  ///
   UINTN     LastEapolFrameSource;
 } EFI_EAPOL_SUPPLICANT_PAE_STATISTICS;
 
 /**
-  Read the system configuration information associated with the Port. 
+  Read the system configuration information associated with the Port.
 
   The GetSystemConfiguration() function reads the system configuration
-  information associated with the Port, including the value of the 
+  information associated with the Port, including the value of the
   SystemAuthControl parameter of the System is returned in SystemAuthControl
   and the Port's information is returned in the buffer pointed to by PortInfo.
-  The Port's information is optional. 
+  The Port's information is optional.
   If PortInfo is NULL, then reading the Port's information is ignored.
 
   If SystemAuthControl is NULL, then EFI_INVALID_PARAMETER is returned.
@@ -187,7 +181,7 @@ typedef struct _EFI_EAPOL_SUPPLICANT_PAE_STATISTICS {
   @param[in]  This               A pointer to the EFI_EAP_MANAGEMENT_PROTOCOL
                                  instance that indicates the calling context.
   @param[out] SystemAuthControl  Returns the value of the SystemAuthControl
-                                 parameter of the System. 
+                                 parameter of the System.
                                  TRUE means Enabled. FALSE means Disabled.
   @param[out] PortInfo           Returns EFI_EAPOL_PORT_INFO structure to describe
                                  the Port's information. This parameter can be NULL
@@ -202,21 +196,21 @@ typedef struct _EFI_EAPOL_SUPPLICANT_PAE_STATISTICS {
 typedef
 EFI_STATUS
 (EFIAPI *EFI_EAP_GET_SYSTEM_CONFIGURATION)(
-  IN EFI_EAP_MANAGEMENT_PROTOCOL          *This, 
-  OUT BOOLEAN                             *SystemAuthControl, 
+  IN EFI_EAP_MANAGEMENT_PROTOCOL          *This,
+  OUT BOOLEAN                             *SystemAuthControl,
   OUT EFI_EAPOL_PORT_INFO                 *PortInfo OPTIONAL
   );
 
 /**
-  Set the system configuration information associated with the Port. 
+  Set the system configuration information associated with the Port.
 
-  The SetSystemConfiguration() function sets the value of the SystemAuthControl 
+  The SetSystemConfiguration() function sets the value of the SystemAuthControl
   parameter of the System to SystemAuthControl.
 
   @param[in] This                A pointer to the EFI_EAP_MANAGEMENT_PROTOCOL
                                  instance that indicates the calling context.
-  @param[in] SystemAuthControl   The desired value of the SystemAuthControl 
-                                 parameter of the System. 
+  @param[in] SystemAuthControl   The desired value of the SystemAuthControl
+                                 parameter of the System.
                                  TRUE means Enabled. FALSE means Disabled.
 
   @retval EFI_SUCCESS            The system configuration information of the
@@ -226,7 +220,7 @@ EFI_STATUS
 typedef
 EFI_STATUS
 (EFIAPI *EFI_EAP_SET_SYSTEM_CONFIGURATION)(
-  IN EFI_EAP_MANAGEMENT_PROTOCOL          *This, 
+  IN EFI_EAP_MANAGEMENT_PROTOCOL          *This,
   IN BOOLEAN                              SystemAuthControl
   );
 
@@ -266,7 +260,7 @@ EFI_STATUS
   );
 
 /**
-  Notify the EAPOL state machines for the Port that the user of the System has 
+  Notify the EAPOL state machines for the Port that the user of the System has
   logged off.
 
   The UserLogoff() function notifies the EAPOL state machines for the Port.
@@ -290,8 +284,8 @@ EFI_STATUS
   The GetSupplicantStatus() function reads the status of the Supplicant PAE state
   machine for the Port, including the current state CurrentState  and the configuration
   of the operational parameters Configuration. The configuration of the operational
-  parameters is optional. If Configuration is NULL, then reading the configuration 
-  is ignored. The operational parameters in Configuration to be read can also be 
+  parameters is optional. If Configuration is NULL, then reading the configuration
+  is ignored. The operational parameters in Configuration to be read can also be
   specified by Configuration.ValidFieldMask.
 
   If CurrentState is NULL, then EFI_INVALID_PARAMETER is returned.
@@ -303,11 +297,11 @@ EFI_STATUS
   @param[in, out] Configuration  Returns the configuration of the operational
                                  parameters of the Supplicant PAE state machine
                                  for the Port as required. This parameter can be
-                                 NULL to ignore reading the configuration. 
-                                 On input, Configuration.ValidFieldMask specifies the 
+                                 NULL to ignore reading the configuration.
+                                 On input, Configuration.ValidFieldMask specifies the
                                  operational parameters to be read.
                                  On output, Configuration returns the configuration
-                                 of the required operational parameters. 
+                                 of the required operational parameters.
 
   @retval EFI_SUCCESS            The configuration of the operational parameter
                                  of the Supplicant PAE state machine for the Port
@@ -318,16 +312,16 @@ EFI_STATUS
 typedef
 EFI_STATUS
 (EFIAPI *EFI_EAP_GET_SUPPLICANT_STATUS)(
-  IN EFI_EAP_MANAGEMENT_PROTOCOL                  *This, 
-  OUT EFI_EAPOL_SUPPLICANT_PAE_STATE              *CurrentState, 
+  IN EFI_EAP_MANAGEMENT_PROTOCOL                  *This,
+  OUT EFI_EAPOL_SUPPLICANT_PAE_STATE              *CurrentState,
   IN OUT EFI_EAPOL_SUPPLICANT_PAE_CONFIGURATION   *Configuration  OPTIONAL
   );
 
 /**
-  Set the configuration of the operational parameter of the Supplicant PAE 
+  Set the configuration of the operational parameter of the Supplicant PAE
   state machine for the Port.
 
-  The SetSupplicantConfiguration() function sets the configuration of the 
+  The SetSupplicantConfiguration() function sets the configuration of the
   operational Parameter of the Supplicant PAE state machine for the Port to
   Configuration. The operational parameters in Configuration to be set can be
   specified by Configuration.ValidFieldMask.
@@ -336,7 +330,7 @@ EFI_STATUS
 
   @param[in] This                A pointer to the EFI_EAP_MANAGEMENT_PROTOCOL
                                  instance that indicates the calling context.
-  @param[in] Configuration       The desired configuration of the operational 
+  @param[in] Configuration       The desired configuration of the operational
                                  parameters of the Supplicant PAE state machine
                                  for the Port as required.
 
@@ -349,23 +343,23 @@ EFI_STATUS
 typedef
 EFI_STATUS
 (EFIAPI *EFI_EAP_SET_SUPPLICANT_CONFIGURATION)(
-  IN EFI_EAP_MANAGEMENT_PROTOCOL              *This, 
+  IN EFI_EAP_MANAGEMENT_PROTOCOL              *This,
   IN EFI_EAPOL_SUPPLICANT_PAE_CONFIGURATION   *Configuration
   );
 
 /**
   Read the statistical information regarding the operation of the Supplicant
-  associated with the Port. 
+  associated with the Port.
 
-  The GetSupplicantStatistics() function reads the statistical information 
+  The GetSupplicantStatistics() function reads the statistical information
   Statistics regarding the operation of the Supplicant associated with the Port.
-  
+
   If Statistics is NULL, then EFI_INVALID_PARAMETER is returned.
 
   @param[in]  This               A pointer to the EFI_EAP_MANAGEMENT_PROTOCOL
                                  instance that indicates the calling context.
-  @param[out] Statistics         Returns the statistical information regarding the 
-                                 operation of the Supplicant for the Port. 
+  @param[out] Statistics         Returns the statistical information regarding the
+                                 operation of the Supplicant for the Port.
 
   @retval EFI_SUCCESS            The statistical information regarding the operation
                                  of the Supplicant for the Port is read successfully.
@@ -375,15 +369,15 @@ EFI_STATUS
 typedef
 EFI_STATUS
 (EFIAPI *EFI_EAP_GET_SUPPLICANT_STATISTICS)(
-  IN EFI_EAP_MANAGEMENT_PROTOCOL              *This, 
+  IN EFI_EAP_MANAGEMENT_PROTOCOL              *This,
   OUT EFI_EAPOL_SUPPLICANT_PAE_STATISTICS     *Statistics
   );
 
 ///
-/// EFI_EAP_MANAGEMENT_PROTOCOL 
+/// EFI_EAP_MANAGEMENT_PROTOCOL
 /// is used to control, configure and monitor EAPOL state machine on
 /// a Port. EAPOL state machine is built on a per-Port basis. Herein,
-/// a Port means a NIC. For the details of EAPOL, please refer to 
+/// a Port means a NIC. For the details of EAPOL, please refer to
 /// IEEE 802.1x specification.
 ///
 struct _EFI_EAP_MANAGEMENT_PROTOCOL {
diff --git a/MdePkg/Include/Protocol/EapManagement2.h b/MdePkg/Include/Protocol/EapManagement2.h
index d1e5981d0374..faae59116f5b 100644
--- a/MdePkg/Include/Protocol/EapManagement2.h
+++ b/MdePkg/Include/Protocol/EapManagement2.h
@@ -2,13 +2,7 @@
   This file defines the EFI EAP Management2 protocol.
 
   Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution. The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This Protocol is introduced in UEFI Specification 2.5
diff --git a/MdePkg/Include/Protocol/Ebc.h b/MdePkg/Include/Protocol/Ebc.h
index dd6320d61cf4..ff28fcacb29c 100644
--- a/MdePkg/Include/Protocol/Ebc.h
+++ b/MdePkg/Include/Protocol/Ebc.h
@@ -1,14 +1,8 @@
 /** @file
   Describes the protocol interface to the EBC interpreter.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -193,7 +187,7 @@ typedef struct _EFI_EBC_PROTOCOL EFI_EBC_PROTOCOL;
 
 /**
   Creates a thunk for an EBC entry point, returning the address of the thunk.
-  
+
   A PE32+ EBC image, like any other PE32+ image, contains an optional header that specifies the
   entry point for image execution. However, for EBC images, this is the entry point of EBC
   instructions, so is not directly executable by the native processor. Therefore, when an EBC image is
@@ -229,7 +223,7 @@ EFI_STATUS
   @param  ImageHandle   Image handle of the EBC image that is being unloaded from memory.
 
   @retval EFI_SUCCESS            The function completed successfully.
-  @retval EFI_INVALID_PARAMETER  Image handle is not recognized as belonging 
+  @retval EFI_INVALID_PARAMETER  Image handle is not recognized as belonging
                                  to an EBC image that has been executed.
 **/
 typedef
@@ -240,7 +234,7 @@ EFI_STATUS
   );
 
 /**
-  This is the prototype for the Flush callback routine. A pointer to a routine 
+  This is the prototype for the Flush callback routine. A pointer to a routine
   of this type is passed to the EBC EFI_EBC_REGISTER_ICACHE_FLUSH protocol service.
 
   @param  Start  The beginning physical address to flush from the processor's instruction cache.
@@ -257,7 +251,7 @@ EFI_STATUS
   );
 
 /**
-  Registers a callback function that the EBC interpreter calls to flush 
+  Registers a callback function that the EBC interpreter calls to flush
   the processor instruction cache following creation of thunks.
 
   @param  This       A pointer to the EFI_EBC_PROTOCOL instance.
@@ -279,7 +273,7 @@ EFI_STATUS
   This function is called to get the version of the loaded EBC interpreter. The value and format of the
   returned version is identical to that returned by the EBC BREAK 1 instruction.
 
-  @param  This       A pointer to the EFI_EBC_PROTOCOL instance.  
+  @param  This       A pointer to the EFI_EBC_PROTOCOL instance.
   @param  Version    Pointer to where to store the returned version of the interpreter.
 
   @retval EFI_SUCCESS            The function completed successfully.
diff --git a/MdePkg/Include/Protocol/EdidActive.h b/MdePkg/Include/Protocol/EdidActive.h
index 8e1ec8426288..531d077334ad 100644
--- a/MdePkg/Include/Protocol/EdidActive.h
+++ b/MdePkg/Include/Protocol/EdidActive.h
@@ -3,14 +3,8 @@
 
   Placed on the video output device child handle that is actively displaying output.
 
-  Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/Protocol/EdidDiscovered.h b/MdePkg/Include/Protocol/EdidDiscovered.h
index ccaae1bbb353..4975564adc57 100644
--- a/MdePkg/Include/Protocol/EdidDiscovered.h
+++ b/MdePkg/Include/Protocol/EdidDiscovered.h
@@ -4,14 +4,8 @@
   This protocol is placed on the video output device child handle. It represents
   the EDID information being used for the output device represented by the child handle.
 
-  Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -33,7 +27,7 @@ typedef struct {
   /// minimum of 128 bytes.
   ///
   UINT32   SizeOfEdid;
-  
+
   ///
   /// A pointer to a read-only array of bytes that contains the EDID
   /// information for an active video output device. This pointer is
@@ -41,7 +35,7 @@ typedef struct {
   /// device. The minimum size of a valid Edid buffer is 128 bytes.
   /// EDID information is defined in the E-EDID EEPROM
   /// specification published by VESA (www.vesa.org).
-  ///  
+  ///
   UINT8    *Edid;
 } EFI_EDID_DISCOVERED_PROTOCOL;
 
diff --git a/MdePkg/Include/Protocol/EdidOverride.h b/MdePkg/Include/Protocol/EdidOverride.h
index cd847b666d75..6c7c082eab54 100644
--- a/MdePkg/Include/Protocol/EdidOverride.h
+++ b/MdePkg/Include/Protocol/EdidOverride.h
@@ -4,14 +4,8 @@
   Allow platform to provide EDID information to the producer of the Graphics Output
   protocol.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -50,18 +44,18 @@ EFI_STATUS
   IN  EFI_EDID_OVERRIDE_PROTOCOL          *This,
   IN  EFI_HANDLE                          *ChildHandle,
   OUT UINT32                              *Attributes,
-  IN OUT UINTN                            *EdidSize,
-  IN OUT UINT8                            **Edid
+  OUT UINTN                               *EdidSize,
+  OUT UINT8                               **Edid
   );
 
 ///
-/// This protocol is produced by the platform to allow the platform to provide 
+/// This protocol is produced by the platform to allow the platform to provide
 /// EDID information to the producer of the Graphics Output protocol.
 ///
 struct _EFI_EDID_OVERRIDE_PROTOCOL {
   EFI_EDID_OVERRIDE_PROTOCOL_GET_EDID   GetEdid;
 };
-                                             
+
 extern EFI_GUID gEfiEdidOverrideProtocolGuid;
 
 #endif
diff --git a/MdePkg/Include/Protocol/EraseBlock.h b/MdePkg/Include/Protocol/EraseBlock.h
index d136ccee24a8..bfedcf32c249 100644
--- a/MdePkg/Include/Protocol/EraseBlock.h
+++ b/MdePkg/Include/Protocol/EraseBlock.h
@@ -2,13 +2,7 @@
   This file defines the EFI Erase Block Protocol.
 
   Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution. The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This Protocol is introduced in UEFI Specification 2.6
diff --git a/MdePkg/Include/Protocol/ExtendedSalBootService.h b/MdePkg/Include/Protocol/ExtendedSalBootService.h
deleted file mode 100644
index 167201d85a95..000000000000
--- a/MdePkg/Include/Protocol/ExtendedSalBootService.h
+++ /dev/null
@@ -1,214 +0,0 @@
-/** @file
-  Definition of Extended SAL Boot Service Protocol
-
-  The Extended SAL Boot Service Protocol provides a mechanisms for platform specific 
-  drivers to update the SAL System Table and register Extended SAL Procedures that are
-  callable in physical or virtual mode using the SAL calling convention.
-
-  Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
-
-**/
-
-#ifndef _EXTENDED_SAL_BOOT_SERVICE_PROTOCOL_H_
-#define _EXTENDED_SAL_BOOT_SERVICE_PROTOCOL_H_
-
-#include <IndustryStandard/Sal.h>
-
-#define EXTENDED_SAL_BOOT_SERVICE_PROTOCOL_GUID   \
-  { 0xde0ee9a4, 0x3c7a, 0x44f2, {0xb7, 0x8b, 0xe3, 0xcc, 0xd6, 0x9c, 0x3a, 0xf7 } }
-
-typedef struct _EXTENDED_SAL_BOOT_SERVICE_PROTOCOL EXTENDED_SAL_BOOT_SERVICE_PROTOCOL;
-
-/**
-  Adds platform specific information to the to the header of the SAL System Table.
-
-  @param  This                  A pointer to the EXTENDED_SAL_BOOT_SERVICE_PROTOCOL instance.
-  @param  SalAVersion           Version of recovery SAL PEIM(s) in BCD format. Higher byte contains
-                                the major revision and the lower byte contains the minor revision.
-  @param  SalBVersion           Version of DXE SAL Driver in BCD format. Higher byte contains
-                                the major revision and the lower byte contains the minor revision.
-  @param  OemId                 A pointer to a Null-terminated ASCII string that contains OEM unique string.
-                                The string cannot be longer than 32 bytes in total length
-  @param  ProductId             A pointer to a Null-terminated ASCII string that uniquely identifies a family of 
-                                compatible products. The string cannot be longer than 32 bytes in total length.
-
-  @retval EFI_SUCCESS           The SAL System Table header was updated successfully.
-  @retval EFI_INVALID_PARAMETER OemId is NULL.
-  @retval EFI_INVALID_PARAMETER ProductId is NULL.
-  @retval EFI_INVALID_PARAMETER The length of OemId is greater than 32 characters.
-  @retval EFI_INVALID_PARAMETER The length of ProductId is greater than 32 characters.
-
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EXTENDED_SAL_ADD_SST_INFO)(
-  IN EXTENDED_SAL_BOOT_SERVICE_PROTOCOL  *This,
-  IN UINT16                              SalAVersion,
-  IN UINT16                              SalBVersion,
-  IN CHAR8                               *OemId,
-  IN CHAR8                               *ProductId
-  );
-
-/**
-  Adds an entry to the SAL System Table.
-
-  This function adds the SAL System Table Entry specified by TableEntry and EntrySize
-  to the SAL System Table.
-
-  @param  This         A pointer to the EXTENDED_SAL_BOOT_SERVICE_PROTOCOL instance.
-  @param  TableEntry   Pointer to a buffer containing a SAL System Table entry that is EntrySize bytes 
-                       in length. The first byte of the TableEntry describes the type of entry.
-  @param  EntrySize    The size, in bytes, of TableEntry.
-
-  @retval EFI_SUCCESSThe        SAL System Table was updated successfully.
-  @retval EFI_INVALID_PARAMETER TableEntry is NULL.
-  @retval EFI_INVALID_PARAMETER TableEntry specifies an invalid entry type.
-  @retval EFI_INVALID_PARAMETER EntrySize is not valid for this type of entry.
-
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EXTENDED_SAL_ADD_SST_ENTRY)(
-  IN EXTENDED_SAL_BOOT_SERVICE_PROTOCOL  *This,
-  IN UINT8                               *TableEntry,
-  IN UINTN                               EntrySize
-  );
-
-/**
-  Internal ESAL procedures.
-
-  This is prototype of internal Extended SAL procedures, which is registerd by
-  EXTENDED_SAL_REGISTER_INTERNAL_PROC service.
-
-  @param  FunctionId         The Function ID associated with this Extended SAL Procedure.
-  @param  Arg2               Second argument to the Extended SAL procedure.
-  @param  Arg3               Third argument to the Extended SAL procedure.
-  @param  Arg4               Fourth argument to the Extended SAL procedure.
-  @param  Arg5               Fifth argument to the Extended SAL procedure.
-  @param  Arg6               Sixth argument to the Extended SAL procedure.
-  @param  Arg7               Seventh argument to the Extended SAL procedure.
-  @param  Arg8               Eighth argument to the Extended SAL procedure.
-  @param  VirtualMode        TRUE if the Extended SAL Procedure is being invoked in virtual mode.
-                             FALSE if the Extended SAL Procedure is being invoked in physical mode.
-  @param  ModuleGlobal       A pointer to the global context associated with this Extended SAL Procedure. 
-
-  @return The result returned from the specified Extended SAL Procedure
-
-**/
-typedef
-SAL_RETURN_REGS
-(EFIAPI *SAL_INTERNAL_EXTENDED_SAL_PROC)(
-  IN  UINT64   FunctionId,
-  IN  UINT64   Arg2,
-  IN  UINT64   Arg3,
-  IN  UINT64   Arg4,
-  IN  UINT64   Arg5,
-  IN  UINT64   Arg6,
-  IN  UINT64   Arg7,
-  IN  UINT64   Arg8,
-  IN  BOOLEAN  VirtualMode,
-  IN  VOID     *ModuleGlobal  OPTIONAL
-  ); 
-
-/**
-  Registers an Extended SAL Procedure.
-
-  The Extended SAL Procedure specified by InternalSalProc and named by ClassGuidLo,
-  ClassGuidHi, and FunctionId is added to the set of available Extended SAL Procedures.
-
-  @param  This                   A pointer to the EXTENDED_SAL_BOOT_SERVICE_PROTOCOL instance.
-  @param  ClassGuidLo            The lower 64-bits of  the class GUID for the Extended SAL Procedure being added.  
-                                 Each class GUID contains one or more functions specified by a Function ID.
-  @param  ClassGuidHi            The upper 64-bits of  the class GUID for the Extended SAL Procedure being added.  
-                                 Each class GUID contains one or more functions specified by a Function ID.
-  @param  FunctionId             The Function ID for the Extended SAL Procedure that is being added.  This Function 
-                                 ID is a member of the Extended SAL Procedure class specified by ClassGuidLo 
-                                 and ClassGuidHi.
-  @param  InternalSalProc        A pointer to the Extended SAL Procedure being added.
-  @param  PhysicalModuleGlobal   Pointer to a  module global structure. This is a physical mode pointer.
-                                 This pointer is passed to the Extended SAL Procedure specified by ClassGuidLo, 
-                                 ClassGuidHi, FunctionId, and InternalSalProc.  If the system is in physical mode,
-                                 then this pointer is passed unmodified to InternalSalProc.  If the system is in
-                                 virtual mode, then the virtual address associated with this pointer is passed to
-                                 InternalSalProc.
-
-  @retval EFI_SUCCESS            The Extended SAL Procedure was added.
-  @retval EFI_OUT_OF_RESOURCES   There are not enough resources available to add the Extended SAL Procedure.
-
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EXTENDED_SAL_REGISTER_INTERNAL_PROC)(
-  IN EXTENDED_SAL_BOOT_SERVICE_PROTOCOL  *This,
-  IN UINT64                              ClassGuidLo,
-  IN UINT64                              ClassGuidHi,
-  IN UINT64                              FunctionId,
-  IN SAL_INTERNAL_EXTENDED_SAL_PROC      InternalSalProc,
-  IN VOID                                *PhysicalModuleGlobal  OPTIONAL
-  );
-
-/**
-  Calls a previously registered Extended SAL Procedure.
-
-  This function calls the Extended SAL Procedure specified by ClassGuidLo, ClassGuidHi, 
-  and FunctionId.  The set of previously registered Extended SAL Procedures is searched for a 
-  matching ClassGuidLo, ClassGuidHi, and FunctionId.  If a match is not found, then 
-  EFI_SAL_NOT_IMPLEMENTED is returned.
-
-  @param  ClassGuidLo        The lower 64-bits of the class GUID for the Extended SAL Procedure
-                             that is being called.
-  @param  ClassGuidHi        The upper 64-bits of the class GUID for the Extended SAL Procedure
-                             that is being called.
-  @param  FunctionId         Function ID for the Extended SAL Procedure being called.
-  @param  Arg2               Second argument to the Extended SAL procedure.
-  @param  Arg3               Third argument to the Extended SAL procedure.
-  @param  Arg4               Fourth argument to the Extended SAL procedure.
-  @param  Arg5               Fifth argument to the Extended SAL procedure.
-  @param  Arg6               Sixth argument to the Extended SAL procedure.
-  @param  Arg7               Seventh argument to the Extended SAL procedure.
-  @param  Arg8               Eighth argument to the Extended SAL procedure.
-
-  @retval EFI_SAL_NOT_IMPLEMENTED        The Extended SAL Procedure specified by ClassGuidLo, 
-                                         ClassGuidHi, and FunctionId has not been registered.
-  @retval EFI_SAL_VIRTUAL_ADDRESS_ERROR  This function was called in virtual mode before virtual mappings 
-                                         for the specified Extended SAL Procedure are available.
-  @retval Other                          The result returned from the specified Extended SAL Procedure
-
-**/
-typedef
-SAL_RETURN_REGS
-(EFIAPI *EXTENDED_SAL_PROC)(
-  IN UINT64  ClassGuidLo,
-  IN UINT64  ClassGuidHi,
-  IN UINT64  FunctionId,
-  IN UINT64  Arg2,
-  IN UINT64  Arg3,
-  IN UINT64  Arg4,
-  IN UINT64  Arg5,
-  IN UINT64  Arg6,
-  IN UINT64  Arg7,
-  IN UINT64  Arg8
-  );
-
-///
-/// The EXTENDED_SAL_BOOT_SERVICE_PROTOCOL provides a mechanisms for platform specific 
-/// drivers to update the SAL System Table and register Extended SAL Procedures that are
-/// callable in physical or virtual mode using the SAL calling convention.
-///
-struct _EXTENDED_SAL_BOOT_SERVICE_PROTOCOL {
-  EXTENDED_SAL_ADD_SST_INFO            AddSalSystemTableInfo;
-  EXTENDED_SAL_ADD_SST_ENTRY           AddSalSystemTableEntry;
-  EXTENDED_SAL_REGISTER_INTERNAL_PROC  RegisterExtendedSalProc;   
-  EXTENDED_SAL_PROC                    ExtendedSalProc;
-};
-
-extern EFI_GUID  gEfiExtendedSalBootServiceProtocolGuid;
-
-#endif
diff --git a/MdePkg/Include/Protocol/ExtendedSalServiceClasses.h b/MdePkg/Include/Protocol/ExtendedSalServiceClasses.h
deleted file mode 100644
index 126beedacf2e..000000000000
--- a/MdePkg/Include/Protocol/ExtendedSalServiceClasses.h
+++ /dev/null
@@ -1,275 +0,0 @@
-/** @file
-  The standard set of Extended SAL service classes.
-
-  Copyright (c) 2009, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
-
-**/
-
-#ifndef _EXTENDED_SAL_SERVICE_CLASSES_H_
-#define _EXTENDED_SAL_SERVICE_CLASSES_H_
-
-///
-/// Extended SAL Base I/O Services Class
-///
-///@{
-#define EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID_LO 0x451531e15aea42b5
-#define EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID_HI 0xa6657525d5b831bc
-#define EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID \
-  { 0x5aea42b5, 0x31e1, 0x4515, {0xbc, 0x31, 0xb8, 0xd5, 0x25, 0x75, 0x65, 0xa6 } }
-
-typedef enum {
-  IoReadFunctionId,
-  IoWriteFunctionId,
-  MemReadFunctionId,
-  MemWriteFunctionId
-} EFI_EXTENDED_SAL_BASE_IO_SERVICES_FUNC_ID;
-///@}
-
-///
-/// Extended SAL Stall Services Class
-///
-///@{
-#define EFI_EXTENDED_SAL_STALL_SERVICES_PROTOCOL_GUID_LO 0x4d8cac2753a58d06
-#define EFI_EXTENDED_SAL_STALL_SERVICES_PROTOCOL_GUID_HI 0x704165808af0e9b5
-#define EFI_EXTENDED_SAL_STALL_SERVICES_PROTOCOL_GUID \
-  { 0x53a58d06, 0xac27, 0x4d8c, {0xb5, 0xe9, 0xf0, 0x8a, 0x80, 0x65, 0x41, 0x70 } }
-
-typedef enum {
-  StallFunctionId
-} EFI_EXTENDED_SAL_STALL_FUNC_ID;
-///@}
-
-///
-/// Extended SAL Real Time Clock Services Class
-///
-///@{
-#define EFI_EXTENDED_SAL_RTC_SERVICES_PROTOCOL_GUID_LO 0x4d02efdb7e97a470
-#define EFI_EXTENDED_SAL_RTC_SERVICES_PROTOCOL_GUID_HI 0x96a27bd29061ce8f 
-#define EFI_EXTENDED_SAL_RTC_SERVICES_PROTOCOL_GUID  \
-  { 0x7e97a470, 0xefdb, 0x4d02, {0x8f, 0xce, 0x61, 0x90, 0xd2, 0x7b, 0xa2, 0x96 } }
-
-typedef enum {
-  GetTimeFunctionId,
-  SetTimeFunctionId,
-  GetWakeupTimeFunctionId,
-  SetWakeupTimeFunctionId,
-  GetRtcFreqFunctionId,
-  InitializeThresholdFunctionId,
-  BumpThresholdCountFunctionId,
-  GetThresholdCountFunctionId
-} EFI_EXTENDED_SAL_RTC_SERVICES_FUNC_ID;
-///@}
-
-///
-/// Extended SAL Variable Services Class
-///
-///@{
-#define EFI_EXTENDED_SAL_VARIABLE_SERVICES_PROTOCOL_GUID_LO 0x4370c6414ecb6c53 
-#define EFI_EXTENDED_SAL_VARIABLE_SERVICES_PROTOCOL_GUID_HI 0x78836e490e3bb28c
-#define EFI_EXTENDED_SAL_VARIABLE_SERVICES_PROTOCOL_GUID  \
-  { 0x4ecb6c53, 0xc641, 0x4370, {0x8c, 0xb2, 0x3b, 0x0e, 0x49, 0x6e, 0x83, 0x78 } }
-
-typedef enum {
-  EsalGetVariableFunctionId,
-  EsalGetNextVariableNameFunctionId,
-  EsalSetVariableFunctionId,
-  EsalQueryVariableInfoFunctionId
-} EFI_EXTENDED_SAL_VARIABLE_SERVICES_FUNC_ID;
-///@}
-
-///
-/// Extended SAL Monotonic Counter Services Class
-///
-///@{
-#define EFI_EXTENDED_SAL_MTC_SERVICES_PROTOCOL_GUID_LO 0x408b75e8899afd18
-#define EFI_EXTENDED_SAL_MTC_SERVICES_PROTOCOL_GUID_HI 0x54f4cd7e2e6e1aa4
-#define EFI_EXTENDED_SAL_MTC_SERVICES_PROTOCOL_GUID  \
-  { 0x899afd18, 0x75e8, 0x408b, {0xa4, 0x1a, 0x6e, 0x2e, 0x7e, 0xcd, 0xf4, 0x54 } }
-
-typedef enum {
-  GetNextHighMonotonicCountFunctionId
-} EFI_EXTENDED_SAL_MTC_SERVICES_FUNC_ID;
-///@}
-
-///
-/// Extended SAL Reset Services Class
-///
-///@{
-#define EFI_EXTENDED_SAL_RESET_SERVICES_PROTOCOL_GUID_LO  0x46f58ce17d019990
-#define EFI_EXTENDED_SAL_RESET_SERVICES_PROTOCOL_GUID_HI  0xa06a6798513c76a7
-#define EFI_EXTENDED_SAL_RESET_SERVICES_PROTOCOL_GUID  \
-  { 0x7d019990, 0x8ce1, 0x46f5, {0xa7, 0x76, 0x3c, 0x51, 0x98, 0x67, 0x6a, 0xa0 } }
-
-typedef enum {
-  ResetSystemFunctionId
-} EFI_EXTENDED_SAL_RESET_SERVICES_FUNC_ID;
-///@}
-
-///
-/// Extended SAL Status Code Services Class
-///
-///@{
-#define EFI_EXTENDED_SAL_STATUS_CODE_SERVICES_PROTOCOL_GUID_LO 0x420f55e9dbd91d
-#define EFI_EXTENDED_SAL_STATUS_CODE_SERVICES_PROTOCOL_GUID_HI 0x4fb437849f5e3996
-#define EFI_EXTENDED_SAL_STATUS_CODE_SERVICES_PROTOCOL_GUID  \
-  { 0xdbd91d, 0x55e9, 0x420f, {0x96, 0x39, 0x5e, 0x9f, 0x84, 0x37, 0xb4, 0x4f } }
-
-typedef enum {
-  ReportStatusCodeServiceFunctionId
-} EFI_EXTENDED_SAL_STATUS_CODE_SERVICES_FUNC_ID;
-///@}
-
-///
-/// Extended SAL Firmware Volume Block Services Class
-///
-///@{
-#define EFI_EXTENDED_SAL_FV_BLOCK_SERVICES_PROTOCOL_GUID_LO 0x4f1dbcbba2271df1
-#define EFI_EXTENDED_SAL_FV_BLOCK_SERVICES_PROTOCOL_GUID_HI 0x1a072f17bc06a998
-#define EFI_EXTENDED_SAL_FV_BLOCK_SERVICES_PROTOCOL_GUID \
-  { 0xa2271df1, 0xbcbb, 0x4f1d, {0x98, 0xa9, 0x06, 0xbc, 0x17, 0x2f, 0x07, 0x1a } }
-
-typedef enum {
-  ReadFunctionId,
-  WriteFunctionId,
-  EraseBlockFunctionId,
-  GetVolumeAttributesFunctionId,
-  SetVolumeAttributesFunctionId,
-  GetPhysicalAddressFunctionId,
-  GetBlockSizeFunctionId,
-} EFI_EXTENDED_SAL_FV_BLOCK_SERVICES_FUNC_ID;
-///@}
-
-///
-/// Extended SAL MP Services Class
-///
-///@{
-#define EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO 0x4dc0cf18697d81a2
-#define EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI 0x3f8a613b11060d9e
-#define EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID \
-  { 0x697d81a2, 0xcf18, 0x4dc0, {0x9e, 0x0d, 0x06, 0x11, 0x3b, 0x61, 0x8a, 0x3f } }
-
-typedef enum {
-  AddCpuDataFunctionId,
-  RemoveCpuDataFunctionId,
-  ModifyCpuDataFunctionId,
-  GetCpuDataByIDFunctionId,
-  GetCpuDataByIndexFunctionId,
-  SendIpiFunctionId,
-  CurrentProcInfoFunctionId,
-  NumProcessorsFunctionId,
-  SetMinStateFunctionId,
-  GetMinStateFunctionId               
-} EFI_EXTENDED_SAL_MP_SERVICES_FUNC_ID;
-///@}
-
-///
-/// Extended SAL PAL Services Class
-///
-///@{
-#define EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID_LO 0x438d0fc2e1cd9d21
-#define EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID_HI 0x571e966de6040397
-#define EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID \
-  { 0xe1cd9d21, 0x0fc2, 0x438d, {0x97, 0x03, 0x04, 0xe6, 0x6d, 0x96, 0x1e, 0x57 } }
-
-typedef enum {
-  PalProcFunctionId,
-  SetNewPalEntryFunctionId,
-  GetNewPalEntryFunctionId,
-  EsalUpdatePalFunctionId
-} EFI_EXTENDED_SAL_PAL_SERVICES_FUNC_ID;
-///@}
-
-///
-/// Extended SAL Base Services Class
-///
-///@{
-#define EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO 0x41c30fe0d9e9fa06
-#define EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI 0xf894335a4283fb96
-#define EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID \
-  { 0xd9e9fa06, 0x0fe0, 0x41c3, {0x96, 0xfb, 0x83, 0x42, 0x5a, 0x33, 0x94, 0xf8 } }
-
-typedef enum {
-  SalSetVectorsFunctionId,
-  SalMcRendezFunctionId,
-  SalMcSetParamsFunctionId,
-  EsalGetVectorsFunctionId,
-  EsalMcGetParamsFunctionId,
-  EsalMcGetMcParamsFunctionId,
-  EsalGetMcCheckinFlagsFunctionId,
-  EsalGetPlatformBaseFreqFunctionId,
-  EsalPhysicalIdInfoFunctionId, 
-  EsalRegisterPhysicalAddrFunctionId
-} EFI_EXTENDED_SAL_BASE_SERVICES_FUNC_ID;
-///@}
-
-///
-/// Extended SAL MCA Services Class
-///
-///@{
-#define EFI_EXTENDED_SAL_MCA_SERVICES_PROTOCOL_GUID_LO 0x42b16cc72a591128
-#define EFI_EXTENDED_SAL_MCA_SERVICES_PROTOCOL_GUID_HI 0xbb2d683b9358f08a
-#define EFI_EXTENDED_SAL_MCA_SERVICES_PROTOCOL_GUID \
-  { 0x2a591128, 0x6cc7, 0x42b1, {0x8a, 0xf0, 0x58, 0x93, 0x3b, 0x68, 0x2d, 0xbb } }
-
-typedef enum {
-  McaGetStateInfoFunctionId,
-  McaRegisterCpuFunctionId
-} EFI_EXTENDED_SAL_MCA_SERVICES_FUNC_ID;
-///@}
-
-///
-/// Extended SAL PCI Services Class
-///
-///@{
-#define EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO 0x4905ad66a46b1a31
-#define EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI 0x6330dc59462bf692
-#define EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID \
-  { 0xa46b1a31, 0xad66, 0x4905, {0x92, 0xf6, 0x2b, 0x46, 0x59, 0xdc, 0x30, 0x63 } }
-
-typedef enum {
-  SalPciConfigReadFunctionId,
-  SalPciConfigWriteFunctionId
-} EFI_EXTENDED_SAL_PCI_SERVICES_FUNC_ID;
-///@}
-
-///
-/// Extended SAL Cache Services Class
-///
-///@{
-#define EFI_EXTENDED_SAL_CACHE_SERVICES_PROTOCOL_GUID_LO 0x4ba52743edc9494
-#define EFI_EXTENDED_SAL_CACHE_SERVICES_PROTOCOL_GUID_HI 0x88f11352ef0a1888
-#define EFI_EXTENDED_SAL_CACHE_SERVICES_PROTOCOL_GUID \
-  { 0xedc9494, 0x2743, 0x4ba5, { 0x88, 0x18, 0x0a, 0xef, 0x52, 0x13, 0xf1, 0x88 } }
-
-typedef enum {
-  SalCacheInitFunctionId,
-  SalCacheFlushFunctionId
-} EFI_EXTENDED_SAL_CACHE_SERVICES_FUNC_ID;
-///@}
-
-///
-/// Extended SAL MCA Log Services Class
-///
-///@{
-#define EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_LO 0x4c0338a3cb3fd86e
-#define EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_HI 0x7aaba2a3cf905c9a
-#define EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID \
-  { 0xcb3fd86e, 0x38a3, 0x4c03, {0x9a, 0x5c, 0x90, 0xcf, 0xa3, 0xa2, 0xab, 0x7a } }
-
-typedef enum {
-  SalGetStateInfoFunctionId,
-  SalGetStateInfoSizeFunctionId,
-  SalClearStateInfoFunctionId,
-  EsalGetStateBufferFunctionId,
-  EsalSaveStateBufferFunctionId
-} EFI_EXTENDED_SAL_MCA_LOG_SERVICES_FUNC_ID;
-///@}
-
-#endif
diff --git a/MdePkg/Include/Protocol/FirmwareManagement.h b/MdePkg/Include/Protocol/FirmwareManagement.h
index e9a9e04ea0c3..d998b5738e4a 100644
--- a/MdePkg/Include/Protocol/FirmwareManagement.h
+++ b/MdePkg/Include/Protocol/FirmwareManagement.h
@@ -8,15 +8,9 @@
   CheckImage(), GetPackageInfo(), and SetPackageInfo() shall return
   EFI_UNSUPPORTED if not supported by the driver.
 
-  Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2009 - 2020, Intel Corporation. All rights reserved.<BR>
   Copyright (c) 2013 - 2014, Hewlett-Packard Development Company, L.P.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This Protocol is introduced in UEFI Specification 2.3
@@ -35,6 +29,31 @@
 typedef struct _EFI_FIRMWARE_MANAGEMENT_PROTOCOL EFI_FIRMWARE_MANAGEMENT_PROTOCOL;
 
 ///
+/// Dependency Expression Opcode
+///
+#define EFI_FMP_DEP_PUSH_GUID        0x00
+#define EFI_FMP_DEP_PUSH_VERSION     0x01
+#define EFI_FMP_DEP_VERSION_STR      0x02
+#define EFI_FMP_DEP_AND              0x03
+#define EFI_FMP_DEP_OR               0x04
+#define EFI_FMP_DEP_NOT              0x05
+#define EFI_FMP_DEP_TRUE             0x06
+#define EFI_FMP_DEP_FALSE            0x07
+#define EFI_FMP_DEP_EQ               0x08
+#define EFI_FMP_DEP_GT               0x09
+#define EFI_FMP_DEP_GTE              0x0A
+#define EFI_FMP_DEP_LT               0x0B
+#define EFI_FMP_DEP_LTE              0x0C
+#define EFI_FMP_DEP_END              0x0D
+
+///
+/// Image Attribute - Dependency
+///
+typedef struct {
+  UINT8 Dependencies[1];
+} EFI_FIRMWARE_IMAGE_DEP;
+
+///
 /// EFI_FIRMWARE_IMAGE_DESCRIPTOR
 ///
 typedef struct {
@@ -117,6 +136,7 @@ typedef struct {
   /// present in version 3 or higher.
   ///
   UINT64                           HardwareInstance;
+  EFI_FIRMWARE_IMAGE_DEP           *Dependencies;
 } EFI_FIRMWARE_IMAGE_DESCRIPTOR;
 
 
@@ -149,11 +169,17 @@ typedef struct {
 /// The attribute IMAGE_ATTRIBUTE_UEFI_IMAGE indicates that this image is an EFI compatible image.
 ///
 #define    IMAGE_ATTRIBUTE_UEFI_IMAGE              0x0000000000000010
+///
+/// The attribute IMAGE_ATTRIBUTE_DEPENDENCY indicates that there is an EFI_FIRMWARE_IMAGE_DEP
+/// section associated with the image.
+///
+#define    IMAGE_ATTRIBUTE_DEPENDENCY              0x0000000000000020
 
 
 //
 // Image Compatibility Definitions
 //
+///
 /// Values from 0x0000000000000002 thru 0x000000000000FFFF are reserved for future assignments.
 /// Values from 0x0000000000010000 thru 0xFFFFFFFFFFFFFFFF are used by firmware vendor for
 /// compatibility check.
@@ -163,11 +189,11 @@ typedef struct {
 ///
 /// Descriptor Version exposed by GetImageInfo() function
 ///
-#define   EFI_FIRMWARE_IMAGE_DESCRIPTOR_VERSION   3
+#define   EFI_FIRMWARE_IMAGE_DESCRIPTOR_VERSION   4
 
 
 ///
-/// Image Attribute -Authentication Required
+/// Image Attribute - Authentication Required
 ///
 typedef struct {
   ///
@@ -316,11 +342,11 @@ EFI_STATUS
   This function allows a copy of the current firmware image to be created and saved.
   The saved copy could later been used, for example, in firmware image recovery or rollback.
 
-  @param[in]  This               A pointer to the EFI_FIRMWARE_MANAGEMENT_PROTOCOL instance.
-  @param[in]  ImageIndex         A unique number identifying the firmware image(s) within the device.
+  @param[in]      This           A pointer to the EFI_FIRMWARE_MANAGEMENT_PROTOCOL instance.
+  @param[in]      ImageIndex     A unique number identifying the firmware image(s) within the device.
                                  The number is between 1 and DescriptorCount.
-  @param[out] Image              Points to the buffer where the current image is copied to.
-  @param[out] ImageSize          On entry, points to the size of the buffer pointed to by Image, in bytes.
+  @param[out]     Image          Points to the buffer where the current image is copied to.
+  @param[in, out] ImageSize      On entry, points to the size of the buffer pointed to by Image, in bytes.
                                  On return, points to the length of the image, in bytes.
 
   @retval EFI_SUCCESS            The device was successfully updated with the new image.
@@ -330,7 +356,7 @@ EFI_STATUS
   @retval EFI_INVALID_PARAMETER  The Image was NULL.
   @retval EFI_NOT_FOUND          The current image is not copied to the buffer.
   @retval EFI_UNSUPPORTED        The operation is not supported.
-  @retval EFI_SECURITY_VIOLATIO  The operation could not be performed due to an authentication failure.
+  @retval EFI_SECURITY_VIOLATION The operation could not be performed due to an authentication failure.
 
 **/
 typedef
@@ -338,7 +364,7 @@ EFI_STATUS
 (EFIAPI *EFI_FIRMWARE_MANAGEMENT_PROTOCOL_GET_IMAGE)(
   IN  EFI_FIRMWARE_MANAGEMENT_PROTOCOL  *This,
   IN  UINT8                             ImageIndex,
-  IN  OUT  VOID                         *Image,
+  OUT  VOID                             *Image,
   IN  OUT  UINTN                        *ImageSize
   );
 
@@ -385,7 +411,7 @@ EFI_STATUS
   @retval EFI_ABORTED            The operation is aborted.
   @retval EFI_INVALID_PARAMETER  The Image was NULL.
   @retval EFI_UNSUPPORTED        The operation is not supported.
-  @retval EFI_SECURITY_VIOLATIO  The operation could not be performed due to an authentication failure.
+  @retval EFI_SECURITY_VIOLATION The operation could not be performed due to an authentication failure.
 
 **/
 typedef
@@ -417,7 +443,7 @@ EFI_STATUS
   @retval EFI_SUCCESS            The image was successfully checked.
   @retval EFI_INVALID_PARAMETER  The Image was NULL.
   @retval EFI_UNSUPPORTED        The operation is not supported.
-  @retval EFI_SECURITY_VIOLATIO  The operation could not be performed due to an authentication failure.
+  @retval EFI_SECURITY_VIOLATION The operation could not be performed due to an authentication failure.
 
 **/
 typedef
@@ -501,7 +527,7 @@ EFI_STATUS
   @retval EFI_INVALID_PARAMETER  The PackageVersionName length is longer than the value
                                  returned in PackageVersionNameMaxLen.
   @retval EFI_UNSUPPORTED        The operation is not supported.
-  @retval EFI_SECURITY_VIOLATIO  The operation could not be performed due to an authentication failure.
+  @retval EFI_SECURITY_VIOLATION The operation could not be performed due to an authentication failure.
 
 **/
 typedef
diff --git a/MdePkg/Include/Protocol/FirmwareVolume2.h b/MdePkg/Include/Protocol/FirmwareVolume2.h
index 00523bf0837e..cc52ecc794e2 100644
--- a/MdePkg/Include/Protocol/FirmwareVolume2.h
+++ b/MdePkg/Include/Protocol/FirmwareVolume2.h
@@ -1,18 +1,12 @@
 /** @file
-  The Firmware Volume Protocol provides file-level access to the firmware volume. 
-  Each firmware volume driver must produce an instance of the 
+  The Firmware Volume Protocol provides file-level access to the firmware volume.
+  Each firmware volume driver must produce an instance of the
   Firmware Volume Protocol if the firmware volume is to be visible to
   the system during the DXE phase. The Firmware Volume Protocol also provides
   mechanisms for determining and modifying some attributes of the firmware volume.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference: PI
   Version 1.00.
@@ -98,7 +92,7 @@ typedef UINT64  EFI_FV_ATTRIBUTES;
   undefined.
 
   @param  This          Indicates the EFI_FIRMWARE_VOLUME2_PROTOCOL instance.
-  
+
   @param  FvAttributes  Pointer to an EFI_FV_ATTRIBUTES in which
                         the attributes and current settings are
                         returned.
@@ -118,7 +112,7 @@ EFI_STATUS
 
 /**
   Modifies the current settings of the firmware volume according to the input parameter.
-  
+
   The SetVolumeAttributes() function is used to set configurable
   firmware volume attributes. Only EFI_FV_READ_STATUS,
   EFI_FV_WRITE_STATUS, and EFI_FV_LOCK_STATUS may be modified, and
@@ -136,7 +130,7 @@ EFI_STATUS
   TPL_NOTIFY is undefined.
 
   @param  This          Indicates the EFI_FIRMWARE_VOLUME2_PROTOCOL instance.
-  
+
   @param  FvAttributes  On input, FvAttributes is a pointer to
                         an EFI_FV_ATTRIBUTES containing the
                         desired firmware volume settings. On
@@ -145,7 +139,7 @@ EFI_STATUS
                         unsuccessful return, FvAttributes is not
                         modified and the firmware volume
                         settings are not changed.
-  
+
   @retval EFI_SUCCESS           The requested firmware volume attributes
                                 were set and the resulting
                                 EFI_FV_ATTRIBUTES is returned in
@@ -254,13 +248,13 @@ EFI_STATUS
   undefined.
 
   @param  This                  Indicates the EFI_FIRMWARE_VOLUME2_PROTOCOL instance.
-  
+
   @param  NameGuid              Pointer to an EFI_GUID, which is the file
                                 name. All firmware file names are EFI_GUIDs.
                                 A single firmware volume must not have two
                                 valid files with the same file name
                                 EFI_GUID.
-  
+
   @param  Buffer                Pointer to a pointer to a buffer in which the
                                 file contents are returned, not including the
                                 file header.
@@ -268,19 +262,19 @@ EFI_STATUS
   @param  BufferSize            Pointer to a caller-allocated UINTN. It
                                 indicates the size of the memory
                                 represented by Buffer.
-  
+
   @param  FoundType             Pointer to a caller-allocated EFI_FV_FILETYPE.
-  
+
   @param  FileAttributes        Pointer to a  caller-allocated
                                 EFI_FV_FILE_ATTRIBUTES.
-  
+
   @param  AuthenticationStatus  Pointer to a caller-allocated
                                 UINT32 in which the
                                 authentication status is
                                 returned.
-  
+
   @retval EFI_SUCCESS                 The call completed successfully.
-  
+
   @retval EFI_WARN_BUFFER_TOO_SMALL   The buffer is too small to
                                       contain the requested
                                       output. The buffer is
@@ -342,56 +336,56 @@ EFI_STATUS
   undefined.
 
   @param  This                Indicates the EFI_FIRMWARE_VOLUME2_PROTOCOL instance.
- 
+
   @param NameGuid             Pointer to an EFI_GUID, which indicates the
                               file name from which the requested section
                               will be read.
-  
+
   @param SectionType          Indicates the section type to return.
                               SectionType in conjunction with
                               SectionInstance indicates which section to
                               return.
-  
+
   @param SectionInstance      Indicates which instance of sections
                               with a type of SectionType to return.
                               SectionType in conjunction with
                               SectionInstance indicates which
                               section to return. SectionInstance is
                               zero based.
-  
+
   @param Buffer               Pointer to a pointer to a buffer in which the
                               section contents are returned, not including
                               the section header.
-  
+
   @param BufferSize           Pointer to a caller-allocated UINTN. It
                               indicates the size of the memory
                               represented by Buffer.
-  
+
   @param AuthenticationStatus Pointer to a caller-allocated
                               UINT32 in which the authentication
                               status is returned.
-  
-  
+
+
   @retval EFI_SUCCESS   The call completed successfully.
-  
+
   @retval EFI_WARN_BUFFER_TOO_SMALL   The caller-allocated
                                       buffer is too small to
                                       contain the requested
                                       output. The buffer is
                                       filled and the output is
                                       truncated.
-  
+
   @retval EFI_OUT_OF_RESOURCES  An allocation failure occurred.
-  
+
   @retval EFI_NOT_FOUND   The requested file was not found in
                           the firmware volume. EFI_NOT_FOUND The
                           requested section was not found in the
                           specified file.
-  
+
   @retval EFI_DEVICE_ERROR  A hardware error occurred when
                             attempting to access the firmware
                             volume.
-  
+
   @retval EFI_ACCESS_DENIED The firmware volume is configured to
                             disallow reads. EFI_PROTOCOL_ERROR
                             The requested section was not found,
@@ -472,7 +466,7 @@ typedef struct {
   Architectural Elements 84 August 21, 2006 Version 1.0
   WriteFile() is callable only from TPL_NOTIFY and below.
   Behavior of WriteFile() at any EFI_TPL above TPL_NOTIFY is
-  undefined. 
+  undefined.
 
   @param This           Indicates the EFI_FIRMWARE_VOLUME2_PROTOCOL instance.
 
@@ -482,31 +476,31 @@ typedef struct {
                         write in the event of a power failure or
                         other system failure during the write
                         operation.
- 
+
   @param FileData       Pointer to an array of
                         EFI_FV_WRITE_FILE_DATA. Each element of
                         FileData[] represents a file to be written.
 
 
   @retval EFI_SUCCESS             The write completed successfully.
-  
+
   @retval EFI_OUT_OF_RESOURCES    The firmware volume does not
                                   have enough free space to
                                   storefile(s).
-  
+
   @retval EFI_DEVICE_ERROR        A hardware error occurred when
                                   attempting to access the firmware volume.
-  
+
   @retval EFI_WRITE_PROTECTED     The firmware volume is
                                   configured to disallow writes.
-  
+
   @retval EFI_NOT_FOUND           A delete was requested, but the
                                   requested file was not found in the
                                   firmware volume.
-  
+
   @retval EFI_INVALID_PARAMETER   A delete was requested with a
                                   multiple file write.
-  
+
   @retval EFI_INVALID_PARAMETER   An unsupported WritePolicy was
                                   requested.
 
@@ -515,10 +509,10 @@ typedef struct {
 
   @retval EFI_INVALID_PARAMETER   A file system specific error
                                   has occurred.
-  
+
 **/
 typedef
-EFI_STATUS 
+EFI_STATUS
 (EFIAPI * EFI_FV_WRITE_FILE)(
   IN CONST  EFI_FIRMWARE_VOLUME2_PROTOCOL *This,
   IN        UINT32                        NumberOfFiles,
@@ -528,7 +522,7 @@ EFI_STATUS
 
 
 /**
-  Retrieves information about the next file in the firmware volume store 
+  Retrieves information about the next file in the firmware volume store
   that matches the search criteria.
 
   GetNextFile() is the interface that is used to search a firmware
@@ -547,7 +541,7 @@ EFI_STATUS
   implementation specific and no semantic content is implied.
   GetNextFile() is callable only from TPL_NOTIFY and below.
   Behavior of GetNextFile() at any EFI_TPL above TPL_NOTIFY is
-  undefined. 
+  undefined.
 
   @param This       Indicates the EFI_FIRMWARE_VOLUME2_PROTOCOL instance.
 
@@ -600,7 +594,7 @@ EFI_STATUS
   @retval EFI_ACCESS_DENIED The firmware volume is configured to
                             disallow reads.
 
-   
+
 **/
 typedef
 EFI_STATUS
@@ -629,29 +623,29 @@ EFI_STATUS
   @param This             A pointer to the EFI_FIRMWARE_VOLUME2_PROTOCOL
                           instance that is the file handle the requested
                           information is for.
-  
+
   @param InformationType  The type identifier for the
                           information being requested.
-  
+
   @param BufferSize       On input, the size of Buffer. On output,
                           the amount of data returned in Buffer. In
                           both cases, the size is measured in bytes.
-  
+
   @param Buffer           A pointer to the data buffer to return. The
                           buffer's type is indicated by InformationType.
-  
-  
+
+
   @retval EFI_SUCCESS           The information was retrieved.
-  
+
   @retval EFI_UNSUPPORTED       The InformationType is not known.
-  
+
   @retval EFI_NO_MEDIA          The device has no medium.
-  
+
   @retval EFI_DEVICE_ERROR      The device reported an error.
-  
+
   @retval EFI_VOLUME_CORRUPTED  The file system structures are
                                 corrupted.
-  
+
   @retval EFI_BUFFER_TOO_SMALL  The BufferSize is too small to
                                 read the current directory
                                 entry. BufferSize has been
@@ -740,14 +734,14 @@ struct _EFI_FIRMWARE_VOLUME2_PROTOCOL {
   EFI_FV_READ_SECTION     ReadSection;
   EFI_FV_WRITE_FILE       WriteFile;
   EFI_FV_GET_NEXT_FILE    GetNextFile;
-  
+
   ///
   /// Data field that indicates the size in bytes
   /// of the Key input buffer for the
-  /// GetNextFile() API.  
+  /// GetNextFile() API.
   ///
   UINT32                  KeySize;
-  
+
   ///
   /// Handle of the parent firmware volume.
   ///
diff --git a/MdePkg/Include/Protocol/FirmwareVolumeBlock.h b/MdePkg/Include/Protocol/FirmwareVolumeBlock.h
index 48c06e143906..3be86b003956 100644
--- a/MdePkg/Include/Protocol/FirmwareVolumeBlock.h
+++ b/MdePkg/Include/Protocol/FirmwareVolumeBlock.h
@@ -1,14 +1,8 @@
 /** @file
   This file provides control over block-oriented firmware devices.
 
-Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference: PI
   Version 1.0 and 1.2.
@@ -21,7 +15,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 //
 // EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL is defined in PI 1.0 spec and its GUID value
 // is later updated to be the same as that of EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL
-// defined in PI 1.2 spec. 
+// defined in PI 1.2 spec.
 //
 #define EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL_GUID \
   { 0x8f644fa9, 0xe850, 0x4db1, {0x9c, 0xe2, 0xb, 0x44, 0x69, 0x8e, 0x8d, 0xa4 } }
@@ -31,7 +25,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
 typedef struct _EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL;
 
-typedef EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL;    
+typedef EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL;
 
 /**
   The GetAttributes() function retrieves the attributes and
@@ -69,7 +63,7 @@ EFI_STATUS
                       settings of the firmware volume. Type
                       EFI_FVB_ATTRIBUTES_2 is defined in
                       EFI_FIRMWARE_VOLUME_HEADER.
-  
+
   @retval EFI_SUCCESS           The firmware volume attributes were returned.
 
   @retval EFI_INVALID_PARAMETER The attributes requested are in
@@ -92,14 +86,14 @@ EFI_STATUS
   only for memory-mapped firmware volumes.
 
   @param This     Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
-  
+
   @param Address  Pointer to a caller-allocated
                   EFI_PHYSICAL_ADDRESS that, on successful
                   return from GetPhysicalAddress(), contains the
                   base address of the firmware volume.
-  
+
   @retval EFI_SUCCESS       The firmware volume base address was returned.
-  
+
   @retval EFI_UNSUPPORTED   The firmware volume is not memory mapped.
 
 **/
@@ -130,9 +124,9 @@ EFI_STATUS
                         blocks in this range have a size of
                         BlockSize.
 
-  
+
   @retval EFI_SUCCESS             The firmware volume base address was returned.
-  
+
   @retval EFI_INVALID_PARAMETER   The requested LBA is out of range.
 
 **/
@@ -163,7 +157,7 @@ EFI_STATUS
   aware that a read may be partially completed.
 
   @param This     Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
-  
+
   @param Lba      The starting logical block index
                   from which to read.
 
@@ -179,15 +173,15 @@ EFI_STATUS
 
   @retval EFI_SUCCESS         The firmware volume was read successfully,
                               and contents are in Buffer.
-  
+
   @retval EFI_BAD_BUFFER_SIZE Read attempted across an LBA
                               boundary. On output, NumBytes
                               contains the total number of bytes
                               returned in Buffer.
-  
+
   @retval EFI_ACCESS_DENIED   The firmware volume is in the
                               ReadDisabled state.
-  
+
   @retval EFI_DEVICE_ERROR    The block device is not
                               functioning correctly and could
                               not be read.
@@ -215,7 +209,7 @@ EFI_STATUS
   unpredictability arises because, for a sticky-write firmware
   volume, a write may negate a bit in the EFI_FVB_ERASE_POLARITY
   state but cannot flip it back again.  Before calling the
-  Write() function,  it is recommended for the caller to first call 
+  Write() function,  it is recommended for the caller to first call
   the EraseBlocks() function to erase the specified block to
   write. A block erase cycle will transition bits from the
   (NOT)EFI_FVB_ERASE_POLARITY state back to the
@@ -234,29 +228,29 @@ EFI_STATUS
   returns.
 
   @param This     Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance.
-  
+
   @param Lba      The starting logical block index to write to.
-  
+
   @param Offset   Offset into the block at which to begin writing.
-  
+
   @param NumBytes The pointer to a UINTN. At entry, *NumBytes
                   contains the total size of the buffer. At
                   exit, *NumBytes contains the total number of
                   bytes actually written.
-  
+
   @param Buffer   The pointer to a caller-allocated buffer that
                   contains the source for the write.
-  
+
   @retval EFI_SUCCESS         The firmware volume was written successfully.
-  
+
   @retval EFI_BAD_BUFFER_SIZE The write was attempted across an
                               LBA boundary. On output, NumBytes
                               contains the total number of bytes
                               actually written.
-  
+
   @retval EFI_ACCESS_DENIED   The firmware volume is in the
                               WriteDisabled state.
-  
+
   @retval EFI_DEVICE_ERROR    The block device is malfunctioning
                               and could not be written.
 
@@ -317,7 +311,7 @@ EFI_STATUS
 
   @retval EFI_SUCCESS The erase request successfully
                       completed.
-  
+
   @retval EFI_ACCESS_DENIED   The firmware volume is in the
                               WriteDisabled state.
   @retval EFI_DEVICE_ERROR  The block device is not functioning
@@ -326,7 +320,7 @@ EFI_STATUS
                             partially erased.
   @retval EFI_INVALID_PARAMETER One or more of the LBAs listed
                                 in the variable argument list do
-                                not exist in the firmware volume.  
+                                not exist in the firmware volume.
 
 **/
 typedef
@@ -355,7 +349,7 @@ struct _EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL{
   EFI_FVB_ERASE_BLOCKS          EraseBlocks;
   ///
   /// The handle of the parent firmware volume.
-  ///  
+  ///
   EFI_HANDLE                    ParentHandle;
 };
 
diff --git a/MdePkg/Include/Protocol/FormBrowser2.h b/MdePkg/Include/Protocol/FormBrowser2.h
index de132f88c062..8bc26d6fda6d 100644
--- a/MdePkg/Include/Protocol/FormBrowser2.h
+++ b/MdePkg/Include/Protocol/FormBrowser2.h
@@ -1,17 +1,11 @@
 /** @file
   This protocol is defined in UEFI spec.
-  
-  The EFI_FORM_BROWSER2_PROTOCOL is the interface to call for drivers to 
+
+  The EFI_FORM_BROWSER2_PROTOCOL is the interface to call for drivers to
   leverage the EFI configuration driver interface.
-  
-Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -29,11 +23,11 @@ typedef struct _EFI_FORM_BROWSER2_PROTOCOL   EFI_FORM_BROWSER2_PROTOCOL;
 
 
 /**
-   
+
   @param LeftColumn   The value that designates the text column
                       where the browser window will begin from
                       the left-hand side of the screen
-                      
+
   @param RightColumn  The value that designates the text
                       column where the browser window will end
                       on the right-hand side of the screen.
@@ -44,7 +38,7 @@ typedef struct _EFI_FORM_BROWSER2_PROTOCOL   EFI_FORM_BROWSER2_PROTOCOL;
 
   @param BottomRow    The value that designates the text row from the
                       bottom of the screen where the browser
-                      window will end. 
+                      window will end.
 **/
 typedef struct {
   UINTN   LeftColumn;
@@ -69,14 +63,14 @@ typedef UINTN EFI_BROWSER_ACTION_REQUEST;
 /**
   Initialize the browser to display the specified configuration forms.
 
-  This function is the primary interface to the internal forms-based browser. 
-  The forms browser will display forms associated with the specified Handles. 
-  The browser will select all forms in packages which have the specified Type 
+  This function is the primary interface to the internal forms-based browser.
+  The forms browser will display forms associated with the specified Handles.
+  The browser will select all forms in packages which have the specified Type
   and (for EFI_HII_PACKAGE_TYPE_GUID) the specified PackageGuid.
 
   @param This            A pointer to the EFI_FORM_BROWSER2_PROTOCOL instance
 
-  @param Handles         A pointer to an array of Handles. This value should correspond 
+  @param Handles         A pointer to an array of Handles. This value should correspond
                          to the value of the HII form package that is required to be displayed.
 
   @param HandleCount     The number of Handles specified in Handle.
@@ -90,17 +84,17 @@ typedef UINTN EFI_BROWSER_ACTION_REQUEST;
                          displayable page. If this field has a value of 0x0000, then the Forms Browser will
                          render the first enabled form in the form set.
 
-  @param ScreenDimensions Points to recommended form dimensions, including any non-content area, in 
+  @param ScreenDimensions Points to recommended form dimensions, including any non-content area, in
                           characters.
 
   @param ActionRequest   Points to the action recommended by the form.
 
   @retval EFI_SUCCESS           The function completed successfully
-  
+
   @retval EFI_NOT_FOUND         The variable was not found.
-  
+
   @retval EFI_INVALID_PARAMETER One of the parameters has an
-                                invalid value.  
+                                invalid value.
 **/
 typedef
 EFI_STATUS
@@ -126,7 +120,7 @@ EFI_STATUS
 
   @param ResultsDataSize  A pointer to the size of the buffer
                           associated with ResultsData. On input, the size in
-                          bytes of ResultsData. On output, the size of data 
+                          bytes of ResultsData. On output, the size of data
                           returned in ResultsData.
 
   @param ResultsData    A string returned from an IFR browser or
@@ -148,7 +142,7 @@ EFI_STATUS
 
   @retval EFI_SUCCESS           The results have been distributed or are
                                 awaiting distribution.
-  
+
   @retval EFI_OUT_OF_RESOURCES  The ResultsDataSize specified
                                 was too small to contain the
                                 results data.
@@ -166,7 +160,7 @@ EFI_STATUS
 );
 
 ///
-/// This interface will allow the caller to direct the configuration 
+/// This interface will allow the caller to direct the configuration
 /// driver to use either the HII database or use the passed-in packet of data.
 ///
 struct _EFI_FORM_BROWSER2_PROTOCOL {
diff --git a/MdePkg/Include/Protocol/Ftp4.h b/MdePkg/Include/Protocol/Ftp4.h
index 939ea9e9c7a3..22b97ebda677 100644
--- a/MdePkg/Include/Protocol/Ftp4.h
+++ b/MdePkg/Include/Protocol/Ftp4.h
@@ -1,22 +1,16 @@
 /** @file
   EFI FTPv4 (File Transfer Protocol version 4) Protocol Definition
-  The EFI FTPv4 Protocol is used to locate communication devices that are 
+  The EFI FTPv4 Protocol is used to locate communication devices that are
   supported by an EFI FTPv4 Protocol driver and to create and destroy instances
   of the EFI FTPv4 Protocol child protocol driver that can use the underlying
   communication device.
   The definitions in this file are defined in UEFI Specification 2.3, which have
   not been verified by one implementation yet.
 
-  Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
+  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-  @par Revision Reference:          
+  @par Revision Reference:
   This Protocol is introduced in UEFI Specification 2.2
 
 **/
@@ -41,103 +35,103 @@ typedef struct _EFI_FTP4_PROTOCOL EFI_FTP4_PROTOCOL;
 /// EFI_FTP4_CONNECTION_TOKEN
 ///
 typedef struct {
-  /// 
-  /// The Event to signal after the connection is established and Status field is updated 
-  /// by the EFI FTP v4 Protocol driver. The type of Event must be 
-  /// EVENT_NOTIFY_SIGNAL, and its Task Priority Level (TPL) must be lower than or 
-  /// equal to TPL_CALLBACK. If it is set to NULL, this function will not return  until the 
+  ///
+  /// The Event to signal after the connection is established and Status field is updated
+  /// by the EFI FTP v4 Protocol driver. The type of Event must be
+  /// EVENT_NOTIFY_SIGNAL, and its Task Priority Level (TPL) must be lower than or
+  /// equal to TPL_CALLBACK. If it is set to NULL, this function will not return  until the
   /// function completes.
-  /// 
-  EFI_EVENT                            Event; 
+  ///
+  EFI_EVENT                            Event;
   ///
   /// The variable to receive the result of the completed operation.
   /// EFI_SUCCESS:              The FTP connection is established successfully
-  /// EFI_ACCESS_DENIED:        The FTP server denied the access the user's request to access it. 
-  /// EFI_CONNECTION_RESET:     The connect fails because the connection is reset either by instance 
+  /// EFI_ACCESS_DENIED:        The FTP server denied the access the user's request to access it.
+  /// EFI_CONNECTION_RESET:     The connect fails because the connection is reset either by instance
   ///                           itself or communication peer.
-  /// EFI_TIMEOUT:              The connection establishment timer expired and no more specific 
+  /// EFI_TIMEOUT:              The connection establishment timer expired and no more specific
   ///                           information is available.
-  /// EFI_NETWORK_UNREACHABLE:  The active open fails because an ICMP network unreachable error is 
-  ///                           received. 
-  /// EFI_HOST_UNREACHABLE:     The active open fails because an ICMP host unreachable error is 
-  ///                           received. 
-  /// EFI_PROTOCOL_UNREACHABLE: The active open fails because an ICMP protocol unreachable error is 
+  /// EFI_NETWORK_UNREACHABLE:  The active open fails because an ICMP network unreachable error is
+  ///                           received.
+  /// EFI_HOST_UNREACHABLE:     The active open fails because an ICMP host unreachable error is
   ///                           received.
-  /// EFI_PORT_UNREACHABLE:     The connection establishment timer times out and an ICMP port 
+  /// EFI_PROTOCOL_UNREACHABLE: The active open fails because an ICMP protocol unreachable error is
+  ///                           received.
+  /// EFI_PORT_UNREACHABLE:     The connection establishment timer times out and an ICMP port
   ///                           unreachable error is received.
-  /// EFI_ICMP_ERROR:           The connection establishment timer timeout and some other ICMP 
+  /// EFI_ICMP_ERROR:           The connection establishment timer timeout and some other ICMP
   ///                           error is received.
   /// EFI_DEVICE_ERROR:         An unexpected system or network error occurred.
-  /// 
+  ///
   EFI_STATUS                           Status;
 } EFI_FTP4_CONNECTION_TOKEN;
 
 ///
-/// EFI_FTP4_CONFIG_DATA 
+/// EFI_FTP4_CONFIG_DATA
 ///
 typedef struct {
-  /// 
-  /// Pointer to a ASCII string that contains user name. The caller is 
+  ///
+  /// Pointer to a ASCII string that contains user name. The caller is
   /// responsible for freeing Username after GetModeData() is called.
-  /// 
+  ///
   UINT8                                *Username;
-  /// 
-  /// Pointer to a ASCII string that contains password. The caller is 
+  ///
+  /// Pointer to a ASCII string that contains password. The caller is
   /// responsible for freeing Password after GetModeData() is called.
-  /// 
+  ///
   UINT8                                *Password;
-  /// 
-  /// Set it to TRUE to initiate an active data connection. Set it to 
+  ///
+  /// Set it to TRUE to initiate an active data connection. Set it to
   /// FALSE to initiate a passive data connection.
-  /// 
+  ///
   BOOLEAN                              Active;
-  /// 
+  ///
   /// Boolean value indicating if default network settting used.
-  /// 
+  ///
   BOOLEAN                              UseDefaultSetting;
-  /// 
+  ///
   /// IP address of station if UseDefaultSetting is FALSE.
-  /// 
+  ///
   EFI_IPv4_ADDRESS                     StationIp;
-  /// 
+  ///
   /// Subnet mask of station if UseDefaultSetting is FALSE.
-  /// 
+  ///
   EFI_IPv4_ADDRESS                     SubnetMask;
-  /// 
+  ///
   /// IP address of gateway if UseDefaultSetting is FALSE.
-  /// 
+  ///
   EFI_IPv4_ADDRESS                     GatewayIp;
-  /// 
+  ///
   /// IP address of FTPv4 server.
-  /// 
+  ///
   EFI_IPv4_ADDRESS                     ServerIp;
-  /// 
-  /// FTPv4 server port number of control connection, and the default 
+  ///
+  /// FTPv4 server port number of control connection, and the default
   /// value is 21 as convention.
-  /// 
+  ///
   UINT16                               ServerPort;
-  /// 
-  /// FTPv4 server port number of data connection. If it is zero, use 
-  /// (ServerPort - 1) by convention. 
-  /// 
+  ///
+  /// FTPv4 server port number of data connection. If it is zero, use
+  /// (ServerPort - 1) by convention.
+  ///
   UINT16                               AltDataPort;
-  /// 
-  /// A byte indicate the representation type. The right 4 bit is used for 
+  ///
+  /// A byte indicate the representation type. The right 4 bit is used for
   /// first parameter, the left 4 bit is use for second parameter
   /// - For the first parameter, 0x0 = image, 0x1 = EBCDIC, 0x2 = ASCII, 0x3 = local
-  /// - For the second parameter, 0x0 = Non-print, 0x1 = Telnet format effectors, 0x2 = 
+  /// - For the second parameter, 0x0 = Non-print, 0x1 = Telnet format effectors, 0x2 =
   ///   Carriage Control.
   /// - If it is a local type, the second parameter is the local byte byte size.
   /// - If it is a image type, the second parameter is undefined.
-  /// 
+  ///
   UINT8                                RepType;
-  /// 
+  ///
   /// Defines the file structure in FTP used. 0x00 = file, 0x01 = record, 0x02 = page.
-  /// 
+  ///
   UINT8                                FileStruct;
-  /// 
+  ///
   /// Defines the transifer mode used in FTP. 0x00 = stream, 0x01 = Block, 0x02 = Compressed.
-  /// 
+  ///
   UINT8                                TransMode;
 } EFI_FTP4_CONFIG_DATA;
 
@@ -149,9 +143,9 @@ typedef struct _EFI_FTP4_COMMAND_TOKEN EFI_FTP4_COMMAND_TOKEN;
   If it is receiving function that leads to inbound data, the callback function
   is called when data buffer is full. Then, old data in the data buffer should be
   flushed and new data is stored from the beginning of data buffer.
-  If it is a transmit function that lead to outbound data and the size of 
-  Data in daata buffer has been transmitted, this callback function is called to 
-  supply additional data to be transmitted. 
+  If it is a transmit function that lead to outbound data and the size of
+  Data in daata buffer has been transmitted, this callback function is called to
+  supply additional data to be transmitted.
 
   @param[in] This                Pointer to the EFI_FTP4_PROTOCOL instance.
   @param[in] Token               Pointer to the token structure to provide the parameters that
@@ -160,8 +154,8 @@ typedef struct _EFI_FTP4_COMMAND_TOKEN EFI_FTP4_COMMAND_TOKEN;
 
 **/
 typedef
-EFI_STATUS 
-(EFIAPI *EFI_FTP4_DATA_CALLBACK)( 
+EFI_STATUS
+(EFIAPI *EFI_FTP4_DATA_CALLBACK)(
   IN EFI_FTP4_PROTOCOL           *This,
   IN EFI_FTP4_COMMAND_TOKEN      *Token
   );
@@ -170,57 +164,57 @@ EFI_STATUS
 /// EFI_FTP4_COMMAND_TOKEN
 ///
 struct _EFI_FTP4_COMMAND_TOKEN {
-  /// 
-  /// The Event to signal after request is finished and Status field 
-  /// is updated by the EFI FTP v4 Protocol driver. The type of Event 
-  /// must be EVT_NOTIFY_SIGNAL, and its Task Priority Level 
-  /// (TPL) must be lower than or equal to TPL_CALLBACK. If it is 
-  /// set to NULL, related function must wait until the function 
+  ///
+  /// The Event to signal after request is finished and Status field
+  /// is updated by the EFI FTP v4 Protocol driver. The type of Event
+  /// must be EVT_NOTIFY_SIGNAL, and its Task Priority Level
+  /// (TPL) must be lower than or equal to TPL_CALLBACK. If it is
+  /// set to NULL, related function must wait until the function
   /// completes.
-  /// 
-  EFI_EVENT                             Event; 
-  /// 
-  /// Pointer to a null-terminated ASCII name string. 
-  /// 
+  ///
+  EFI_EVENT                             Event;
+  ///
+  /// Pointer to a null-terminated ASCII name string.
+  ///
   UINT8                                 *Pathname;
-  /// 
+  ///
   /// The size of data buffer in bytes.
-  /// 
-  UINT64                                DataBufferSize;        
-  /// 
-  /// Pointer to the data buffer. Data downloaded from FTP server 
+  ///
+  UINT64                                DataBufferSize;
+  ///
+  /// Pointer to the data buffer. Data downloaded from FTP server
   /// through connection is downloaded here.
-  /// 
+  ///
   VOID                                  *DataBuffer;
-  /// 
-  /// Pointer to a callback function. If it is receiving function that leads 
-  /// to inbound data, the callback function is called when databuffer is 
-  /// full. Then, old data in the data buffer should be flushed and new 
-  /// data is stored from the beginning of data buffer. If it is a transmit 
-  /// function that lead to outbound data and DataBufferSize of 
-  /// Data in DataBuffer has been transmitted, this callback 
-  /// function is called to supply additional data to be transmitted. The 
-  /// size of additional data to be transmitted is indicated in 
-  /// DataBufferSize, again. If there is no data remained, 
+  ///
+  /// Pointer to a callback function. If it is receiving function that leads
+  /// to inbound data, the callback function is called when databuffer is
+  /// full. Then, old data in the data buffer should be flushed and new
+  /// data is stored from the beginning of data buffer. If it is a transmit
+  /// function that lead to outbound data and DataBufferSize of
+  /// Data in DataBuffer has been transmitted, this callback
+  /// function is called to supply additional data to be transmitted. The
+  /// size of additional data to be transmitted is indicated in
+  /// DataBufferSize, again. If there is no data remained,
   /// DataBufferSize should be set to 0.
-  /// 
-  EFI_FTP4_DATA_CALLBACK                *DataCallback;
-  /// 
+  ///
+  EFI_FTP4_DATA_CALLBACK                DataCallback;
+  ///
   /// Pointer to the parameter for DataCallback.
-  /// 
+  ///
   VOID                                  *Context;
-  /// 
+  ///
   /// The variable to receive the result of the completed operation.
   /// EFI_SUCCESS:              The FTP command is completed successfully.
   /// EFI_ACCESS_DENIED:        The FTP server denied the access to the requested file.
   /// EFI_CONNECTION_RESET:     The connect fails because the connection is reset either
   ///                           by instance itself or communication peer.
-  /// EFI_TIMEOUT:              The connection establishment timer expired and no more 
+  /// EFI_TIMEOUT:              The connection establishment timer expired and no more
   ///                           specific information is available.
   /// EFI_NETWORK_UNREACHABLE:  The active open fails because an ICMP network unreachable
-  ///                           error is received. 
+  ///                           error is received.
   /// EFI_HOST_UNREACHABLE:     The active open fails because an ICMP host unreachable
-  ///                           error is received. 
+  ///                           error is received.
   /// EFI_PROTOCOL_UNREACHABLE: The active open fails because an ICMP protocol unreachable
   ///                           error is received.
   /// EFI_PORT_UNREACHABLE:     The connection establishment timer times out and an ICMP port
@@ -236,14 +230,14 @@ struct _EFI_FTP4_COMMAND_TOKEN {
   Gets the current operational settings.
 
   The GetModeData() function reads the current operational settings of this
-  EFI FTPv4 Protocol driver instance. EFI_FTP4_CONFIG_DATA  is defined in the 
+  EFI FTPv4 Protocol driver instance. EFI_FTP4_CONFIG_DATA  is defined in the
   EFI_FTP4_PROTOCOL.Configure.
 
   @param[in]  This               Pointer to the EFI_FTP4_PROTOCOL instance.
-  @param[out] ModeData           Pointer to storage for the EFI FTPv4 Protocol driver 
+  @param[out] ModeData           Pointer to storage for the EFI FTPv4 Protocol driver
                                  mode data. The string buffers for Username and Password
                                  in EFI_FTP4_CONFIG_DATA are allocated by the function,
-                                 and the caller should take the responsibility to free the 
+                                 and the caller should take the responsibility to free the
                                  buffer later.
 
   @retval EFI_SUCCESS            This function is called successfully.
@@ -255,8 +249,8 @@ struct _EFI_FTP4_COMMAND_TOKEN {
   @retval EFI_DEVICE_ERROR       An unexpected system or network error occurred.
 
 **/
-typedef 
-EFI_STATUS 
+typedef
+EFI_STATUS
 (EFIAPI *EFI_FTP4_GET_MODE_DATA)(
   IN EFI_FTP4_PROTOCOL        *This,
   OUT EFI_FTP4_CONFIG_DATA    *ModeData
@@ -266,7 +260,7 @@ EFI_STATUS
   Disconnecting a FTP connection gracefully.
 
   The Connect() function will initiate a connection request to the remote FTP server
-  with the corresponding connection token. If this function returns EFI_SUCCESS, the 
+  with the corresponding connection token. If this function returns EFI_SUCCESS, the
   connection sequence is initiated successfully.  If the connection succeeds or faild
   due to any error, the Token->Event will be signaled and Token->Status will be updated
   accordingly.
@@ -280,7 +274,7 @@ EFI_STATUS
                                  - Token is NULL.
                                  - Token->Event is NULL.
   @retval EFI_NOT_STARTED        The EFI FTPv4 Protocol driver has not been started.
-  @retval EFI_NO_MAPPING         When using a default address, configuration (DHCP, BOOTP, 
+  @retval EFI_NO_MAPPING         When using a default address, configuration (DHCP, BOOTP,
                                  RARP, etc.) is not finished yet.
   @retval EFI_OUT_OF_RESOURCES   Could not allocate enough resource to finish the operation.
   @retval EFI_DEVICE_ERROR       An unexpected system or network error occurred.
@@ -297,7 +291,7 @@ EFI_STATUS
   Disconnecting a FTP connection gracefully.
 
   The Close() function will initiate a close request to the remote FTP server with the
-  corresponding connection token. If this function returns EFI_SUCCESS, the control 
+  corresponding connection token. If this function returns EFI_SUCCESS, the control
   connection with the remote FTP server is closed.
 
   @param[in] This                Pointer to the EFI_FTP4_PROTOCOL instance.
@@ -309,7 +303,7 @@ EFI_STATUS
                                  - Token is NULL.
                                  - Token->Event is NULL.
   @retval EFI_NOT_STARTED        The EFI FTPv4 Protocol driver has not been started.
-  @retval EFI_NO_MAPPING         When using a default address, configuration (DHCP, BOOTP, 
+  @retval EFI_NO_MAPPING         When using a default address, configuration (DHCP, BOOTP,
                                  RARP, etc.) is not finished yet.
   @retval EFI_OUT_OF_RESOURCES   Could not allocate enough resource to finish the operation.
   @retval EFI_DEVICE_ERROR       An unexpected system or network error occurred.
@@ -325,14 +319,14 @@ EFI_STATUS
 /**
   Sets or clears the operational parameters for the FTP child driver.
 
-  The Configure() function will configure the connected FTP session with the 
+  The Configure() function will configure the connected FTP session with the
   configuration setting specified in  FtpConfigData. The configuration data can
   be reset by calling Configure() with FtpConfigData set to NULL.
 
   @param[in] This                Pointer to the EFI_FTP4_PROTOCOL instance.
-  @param[in] FtpConfigData       Pointer to configuration data that will be assigned to 
+  @param[in] FtpConfigData       Pointer to configuration data that will be assigned to
                                  the FTP child driver instance. If NULL, the FTP child
-                                 driver instance is reset to startup defaults and all 
+                                 driver instance is reset to startup defaults and all
                                  pending transmit and receive requests are flushed.
 
   @retval EFI_SUCCESS            The FTPv4 driver was configured successfully.
@@ -342,13 +336,13 @@ EFI_STATUS
                                  - FtpConfigData.FileStruct is invalid.
                                  - FtpConfigData.TransMode is invalid.
                                  - IP address in FtpConfigData is invalid.
-  @retval EFI_NO_MAPPING         When using a default address, configuration (DHCP, BOOTP, 
+  @retval EFI_NO_MAPPING         When using a default address, configuration (DHCP, BOOTP,
                                  RARP, etc.) is not finished yet.
   @retval EFI_UNSUPPORTED        One or more of the configuration parameters are not supported
-                                 by this implementation. 
-  @retval EFI_OUT_OF_RESOURCES   The EFI FTPv4 Protocol driver instance data could not be 
+                                 by this implementation.
+  @retval EFI_OUT_OF_RESOURCES   The EFI FTPv4 Protocol driver instance data could not be
                                  allocated.
-  @retval EFI_DEVICE_ERROR       An unexpected system or network error occurred. The EFI FTPv4 
+  @retval EFI_DEVICE_ERROR       An unexpected system or network error occurred. The EFI FTPv4
                                  Protocol driver instance is not configured.
 
 **/
@@ -361,15 +355,15 @@ EFI_STATUS
 
 
 /**
-  Downloads a file from an FTPv4 server. 
+  Downloads a file from an FTPv4 server.
 
   The ReadFile() function is used to initialize and start an FTPv4 download process
   and optionally wait for completion. When the download operation completes, whether
-  successfully or not, the Token.Status field is updated by the EFI FTPv4 Protocol 
+  successfully or not, the Token.Status field is updated by the EFI FTPv4 Protocol
   driver and then Token.Event is signaled (if it is not NULL).
 
   Data will be downloaded from the FTPv4 server into Token.DataBuffer. If the file size
-  is larger than Token.DataBufferSize, Token.DataCallback will be called to allow for 
+  is larger than Token.DataBufferSize, Token.DataCallback will be called to allow for
   processing data and then new data will be placed at the beginning of Token.DataBuffer.
 
   @param[in] This                Pointer to the EFI_FTP4_PROTOCOL instance.
@@ -384,29 +378,29 @@ EFI_STATUS
                                  - Token. DataBuffer is NULL.
                                  - Token. DataBufferSize is 0.
   @retval EFI_NOT_STARTED        The EFI FTPv4 Protocol driver has not been started.
-  @retval EFI_NO_MAPPING         When using a default address, configuration (DHCP, BOOTP, 
+  @retval EFI_NO_MAPPING         When using a default address, configuration (DHCP, BOOTP,
                                  RARP, etc.) is not finished yet.
   @retval EFI_OUT_OF_RESOURCES   Required system resources could not be allocated.
   @retval EFI_DEVICE_ERROR       An unexpected network error or system error occurred.
 
 **/
-typedef 
-EFI_STATUS 
+typedef
+EFI_STATUS
 (EFIAPI *EFI_FTP4_READ_FILE)(
   IN EFI_FTP4_PROTOCOL         *This,
   IN EFI_FTP4_COMMAND_TOKEN    *Token
   );
 
 /**
-  Uploads a file from an FTPv4 server. 
+  Uploads a file from an FTPv4 server.
 
   The WriteFile() function is used to initialize and start an FTPv4 upload process and
   optionally wait for completion. When the upload operation completes, whether successfully
   or not, the Token.Status field is updated by the EFI FTPv4 Protocol driver and then
   Token.Event is signaled (if it is not NULL). Data to be  uploaded to server is stored
-  into Token.DataBuffer. Token.DataBufferSize is the number bytes to be transferred. 
+  into Token.DataBuffer. Token.DataBufferSize is the number bytes to be transferred.
   If the file size is larger than Token.DataBufferSize, Token.DataCallback will be called
-  to allow for processing data and then new data will be placed at the beginning of 
+  to allow for processing data and then new data will be placed at the beginning of
   Token.DataBuffer. Token.DataBufferSize is updated to reflect the actual number of bytes
   to be transferred. Token.DataBufferSize is set to 0 by the call back to indicate the
   completion of data transfer.
@@ -424,30 +418,30 @@ EFI_STATUS
                                  - Token. DataBuffer is NULL.
                                  - Token. DataBufferSize is 0.
   @retval EFI_NOT_STARTED        The EFI FTPv4 Protocol driver has not been started.
-  @retval EFI_NO_MAPPING         When using a default address, configuration (DHCP, BOOTP, 
+  @retval EFI_NO_MAPPING         When using a default address, configuration (DHCP, BOOTP,
                                  RARP, etc.) is not finished yet.
   @retval EFI_OUT_OF_RESOURCES   Required system resources could not be allocated.
   @retval EFI_DEVICE_ERROR       An unexpected network error or system error occurred.
 
 **/
-typedef 
-EFI_STATUS 
+typedef
+EFI_STATUS
 (EFIAPI *EFI_FTP4_WRITE_FILE)(
   IN EFI_FTP4_PROTOCOL         *This,
   IN EFI_FTP4_COMMAND_TOKEN    *Token
   );
 
 /**
-  Download a data file "directory" from a FTPv4 server. May be unsupported in some EFI 
+  Download a data file "directory" from a FTPv4 server. May be unsupported in some EFI
   implementations.
 
   The ReadDirectory() function is used to return a list of files on the FTPv4 server that
   logically (or operationally) related to Token.Pathname, and optionally wait for completion.
-  When the download operation completes, whether successfully or not, the Token.Status field 
+  When the download operation completes, whether successfully or not, the Token.Status field
   is updated by the EFI FTPv4 Protocol driver and then Token.Event is signaled (if it is not
   NULL). Data will be downloaded from the FTPv4 server into Token.DataBuffer. If the file size
   is larger than Token.DataBufferSize, Token.DataCallback will be called to allow for processing
-  data and then new data will be placed at the beginning of Token.DataBuffer. 
+  data and then new data will be placed at the beginning of Token.DataBuffer.
 
   @param[in] This                Pointer to the EFI_FTP4_PROTOCOL instance.
   @param[in] Token               Pointer to the token structure to provide the parameters that
@@ -461,7 +455,7 @@ EFI_STATUS
                                  - Token. DataBuffer is NULL.
                                  - Token. DataBufferSize is 0.
   @retval EFI_NOT_STARTED        The EFI FTPv4 Protocol driver has not been started.
-  @retval EFI_NO_MAPPING         When using a default address, configuration (DHCP, BOOTP, 
+  @retval EFI_NO_MAPPING         When using a default address, configuration (DHCP, BOOTP,
                                  RARP, etc.) is not finished yet.
   @retval EFI_OUT_OF_RESOURCES   Required system resources could not be allocated.
   @retval EFI_DEVICE_ERROR       An unexpected network error or system error occurred.
@@ -475,15 +469,15 @@ EFI_STATUS
   );
 
 /**
-  Polls for incoming data packets and processes outgoing data packets. 
+  Polls for incoming data packets and processes outgoing data packets.
 
   The Poll() function can be used by network drivers and applications to increase the
   rate that data packets are moved between the communications device and the transmit
   and receive queues. In some systems, the periodic timer event in the managed network
-  driver may not poll the underlying communications device fast enough to transmit 
+  driver may not poll the underlying communications device fast enough to transmit
   and/or receive all data packets without missing incoming packets or dropping outgoing
   packets. Drivers and applications that are experiencing packet loss should try calling
-  the Poll() function more often. 
+  the Poll() function more often.
 
   @param[in] This                Pointer to the EFI_FTP4_PROTOCOL instance.
 
@@ -502,8 +496,8 @@ EFI_STATUS
   );
 
 ///
-/// EFI_FTP4_PROTOCOL 
-/// provides basic services for client-side FTP (File Transfer Protocol) 
+/// EFI_FTP4_PROTOCOL
+/// provides basic services for client-side FTP (File Transfer Protocol)
 /// operations.
 ///
 struct _EFI_FTP4_PROTOCOL {
diff --git a/MdePkg/Include/Protocol/GraphicsOutput.h b/MdePkg/Include/Protocol/GraphicsOutput.h
index a3432ce1d6ef..9ba38c577a45 100644
--- a/MdePkg/Include/Protocol/GraphicsOutput.h
+++ b/MdePkg/Include/Protocol/GraphicsOutput.h
@@ -3,14 +3,8 @@
 
   Abstraction of a very simple graphics device.
 
-  Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -33,18 +27,18 @@ typedef struct {
 
 typedef enum {
   ///
-  /// A pixel is 32-bits and byte zero represents red, byte one represents green, 
-  /// byte two represents blue, and byte three is reserved. This is the definition 
-  /// for the physical frame buffer. The byte values for the red, green, and blue 
-  /// components represent the color intensity. This color intensity value range 
+  /// A pixel is 32-bits and byte zero represents red, byte one represents green,
+  /// byte two represents blue, and byte three is reserved. This is the definition
+  /// for the physical frame buffer. The byte values for the red, green, and blue
+  /// components represent the color intensity. This color intensity value range
   /// from a minimum intensity of 0 to maximum intensity of 255.
   ///
   PixelRedGreenBlueReserved8BitPerColor,
   ///
-  /// A pixel is 32-bits and byte zero represents blue, byte one represents green, 
-  /// byte two represents red, and byte three is reserved. This is the definition 
-  /// for the physical frame buffer. The byte values for the red, green, and blue 
-  /// components represent the color intensity. This color intensity value range 
+  /// A pixel is 32-bits and byte zero represents blue, byte one represents green,
+  /// byte two represents red, and byte three is reserved. This is the definition
+  /// for the physical frame buffer. The byte values for the red, green, and blue
+  /// components represent the color intensity. This color intensity value range
   /// from a minimum intensity of 0 to maximum intensity of 255.
   ///
   PixelBlueGreenRedReserved8BitPerColor,
@@ -64,7 +58,7 @@ typedef enum {
 
 typedef struct {
   ///
-  /// The version of this data structure. A value of zero represents the 
+  /// The version of this data structure. A value of zero represents the
   /// EFI_GRAPHICS_OUTPUT_MODE_INFORMATION structure as defined in this specification.
   ///
   UINT32                     Version;
@@ -77,18 +71,18 @@ typedef struct {
   ///
   UINT32                     VerticalResolution;
   ///
-  /// Enumeration that defines the physical format of the pixel. A value of PixelBltOnly 
+  /// Enumeration that defines the physical format of the pixel. A value of PixelBltOnly
   /// implies that a linear frame buffer is not available for this mode.
   ///
   EFI_GRAPHICS_PIXEL_FORMAT  PixelFormat;
   ///
-  /// This bit-mask is only valid if PixelFormat is set to PixelPixelBitMask. 
+  /// This bit-mask is only valid if PixelFormat is set to PixelPixelBitMask.
   /// A bit being set defines what bits are used for what purpose such as Red, Green, Blue, or Reserved.
   ///
   EFI_PIXEL_BITMASK          PixelInformation;
   ///
   /// Defines the number of pixel elements per video memory line.
-  /// 
+  ///
   UINT32                     PixelsPerScanLine;
 } EFI_GRAPHICS_OUTPUT_MODE_INFORMATION;
 
@@ -116,7 +110,7 @@ EFI_STATUS
   );
 
 /**
-  Set the video device into the specified mode and clears the visible portions of 
+  Set the video device into the specified mode and clears the visible portions of
   the output display to black.
 
   @param  This              The EFI_GRAPHICS_OUTPUT_PROTOCOL instance.
@@ -151,47 +145,47 @@ typedef union {
 ///
 typedef enum {
   ///
-  /// Write data from the BltBuffer pixel (0, 0) 
-  /// directly to every pixel of the video display rectangle 
-  /// (DestinationX, DestinationY) (DestinationX + Width, DestinationY + Height). 
-  /// Only one pixel will be used from the BltBuffer. Delta is NOT used.  
+  /// Write data from the BltBuffer pixel (0, 0)
+  /// directly to every pixel of the video display rectangle
+  /// (DestinationX, DestinationY) (DestinationX + Width, DestinationY + Height).
+  /// Only one pixel will be used from the BltBuffer. Delta is NOT used.
   ///
   EfiBltVideoFill,
-  
+
   ///
-  /// Read data from the video display rectangle 
-  /// (SourceX, SourceY) (SourceX + Width, SourceY + Height) and place it in 
-  /// the BltBuffer rectangle (DestinationX, DestinationY ) 
-  /// (DestinationX + Width, DestinationY + Height). If DestinationX or 
-  /// DestinationY is not zero then Delta must be set to the length in bytes 
-  /// of a row in the BltBuffer.  
+  /// Read data from the video display rectangle
+  /// (SourceX, SourceY) (SourceX + Width, SourceY + Height) and place it in
+  /// the BltBuffer rectangle (DestinationX, DestinationY )
+  /// (DestinationX + Width, DestinationY + Height). If DestinationX or
+  /// DestinationY is not zero then Delta must be set to the length in bytes
+  /// of a row in the BltBuffer.
   ///
   EfiBltVideoToBltBuffer,
-  
+
   ///
-  /// Write data from the BltBuffer rectangle 
-  /// (SourceX, SourceY) (SourceX + Width, SourceY + Height) directly to the 
-  /// video display rectangle (DestinationX, DestinationY) 
-  /// (DestinationX + Width, DestinationY + Height). If SourceX or SourceY is 
-  /// not zero then Delta must be set to the length in bytes of a row in the 
+  /// Write data from the BltBuffer rectangle
+  /// (SourceX, SourceY) (SourceX + Width, SourceY + Height) directly to the
+  /// video display rectangle (DestinationX, DestinationY)
+  /// (DestinationX + Width, DestinationY + Height). If SourceX or SourceY is
+  /// not zero then Delta must be set to the length in bytes of a row in the
   /// BltBuffer.
   ///
-  EfiBltBufferToVideo, 
-  
+  EfiBltBufferToVideo,
+
   ///
   /// Copy from the video display rectangle (SourceX, SourceY)
-  /// (SourceX + Width, SourceY + Height) to the video display rectangle 
-  /// (DestinationX, DestinationY) (DestinationX + Width, DestinationY + Height). 
+  /// (SourceX + Width, SourceY + Height) to the video display rectangle
+  /// (DestinationX, DestinationY) (DestinationX + Width, DestinationY + Height).
   /// The BltBuffer and Delta are not used in this mode.
   ///
   EfiBltVideoToVideo,
-  
+
   EfiGraphicsOutputBltOperationMax
 } EFI_GRAPHICS_OUTPUT_BLT_OPERATION;
 
 /**
   Blt a rectangle of pixels on the graphics screen. Blt stands for BLock Transfer.
-  
+
   @param  This         Protocol instance pointer.
   @param  BltBuffer    The data to transfer to the graphics screen.
                        Size is at least Width*Height*sizeof(EFI_GRAPHICS_OUTPUT_BLT_PIXEL).
@@ -250,15 +244,15 @@ typedef struct {
   ///
   EFI_PHYSICAL_ADDRESS                   FrameBufferBase;
   ///
-  /// Amount of frame buffer needed to support the active mode as defined by 
+  /// Amount of frame buffer needed to support the active mode as defined by
   /// PixelsPerScanLine xVerticalResolution x PixelElementSize.
   ///
   UINTN                                  FrameBufferSize;
 } EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE;
 
 ///
-/// Provides a basic abstraction to set video modes and copy pixels to and from 
-/// the graphics controller's frame buffer. The linear address of the hardware 
+/// Provides a basic abstraction to set video modes and copy pixels to and from
+/// the graphics controller's frame buffer. The linear address of the hardware
 /// frame buffer is also exposed so software can write directly to the video hardware.
 ///
 struct _EFI_GRAPHICS_OUTPUT_PROTOCOL {
diff --git a/MdePkg/Include/Protocol/GuidedSectionExtraction.h b/MdePkg/Include/Protocol/GuidedSectionExtraction.h
index 8f35002cdd41..e44d639889ae 100644
--- a/MdePkg/Include/Protocol/GuidedSectionExtraction.h
+++ b/MdePkg/Include/Protocol/GuidedSectionExtraction.h
@@ -4,14 +4,8 @@
   instance of the GUIDed Section Extraction Protocol to extract
   the section stream contained therein.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference: PI
   Version 1.00.
@@ -22,14 +16,14 @@
 #define __GUID_SECTION_EXTRACTION_PROTOCOL_H__
 
 //
-// The protocol interface structures are identified by associating 
-// them with a GUID. Each instance of a protocol with a given 
-// GUID must have the same interface structure. While all instances 
-// of the GUIDed Section Extraction Protocol must have the same 
-// interface structure, they do not all have the same GUID. The 
-// GUID that is associated with an instance of the GUIDed Section 
-// Extraction Protocol is used to correlate it with the GUIDed 
-// section type that it is intended to process. 
+// The protocol interface structures are identified by associating
+// them with a GUID. Each instance of a protocol with a given
+// GUID must have the same interface structure. While all instances
+// of the GUIDed Section Extraction Protocol must have the same
+// interface structure, they do not all have the same GUID. The
+// GUID that is associated with an instance of the GUIDed Section
+// Extraction Protocol is used to correlate it with the GUIDed
+// section type that it is intended to process.
 //
 
 typedef struct _EFI_GUIDED_SECTION_EXTRACTION_PROTOCOL EFI_GUIDED_SECTION_EXTRACTION_PROTOCOL;
@@ -61,9 +55,9 @@ typedef struct _EFI_GUIDED_SECTION_EXTRACTION_PROTOCOL EFI_GUIDED_SECTION_EXTRAC
   EFI_TPL above TPL_NOTIFY is undefined. Type EFI_TPL is
   defined in RaiseTPL() in the UEFI 2.0 specification.
 
-  
+
   @param This         Indicates the EFI_GUIDED_SECTION_EXTRACTION_PROTOCOL instance.
-  
+
   @param InputSection Buffer containing the input GUIDed section
                       to be processed. OutputBuffer OutputBuffer
                       is allocated from boot services pool
diff --git a/MdePkg/Include/Protocol/Hash.h b/MdePkg/Include/Protocol/Hash.h
index 872dfb7abfd0..178926a1c42a 100644
--- a/MdePkg/Include/Protocol/Hash.h
+++ b/MdePkg/Include/Protocol/Hash.h
@@ -1,18 +1,12 @@
 /** @file
   EFI_HASH_SERVICE_BINDING_PROTOCOL as defined in UEFI 2.0.
   EFI_HASH_PROTOCOL as defined in UEFI 2.0.
-  The EFI Hash Service Binding Protocol is used to locate hashing services support 
-  provided by a driver and to create and destroy instances of the EFI Hash Protocol 
+  The EFI Hash Service Binding Protocol is used to locate hashing services support
+  provided by a driver and to create and destroy instances of the EFI Hash Protocol
   so that a multiple drivers can use the underlying hashing services.
 
-Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -23,7 +17,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   { \
     0x42881c98, 0xa4f3, 0x44b0, {0xa3, 0x9d, 0xdf, 0xa1, 0x86, 0x67, 0xd8, 0xcd } \
   }
-  
+
 #define EFI_HASH_PROTOCOL_GUID \
   { \
     0xc5184932, 0xdba5, 0x46db, {0xa5, 0xba, 0xcc, 0x0b, 0xda, 0x9c, 0x14, 0x35 } \
@@ -37,17 +31,17 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #define EFI_HASH_ALGORITHM_SHA224_GUID \
   { \
     0x8df01a06, 0x9bd5, 0x4bf7, {0xb0, 0x21, 0xdb, 0x4f, 0xd9, 0xcc, 0xf4, 0x5b } \
-  } 
+  }
 
 #define EFI_HASH_ALGORITHM_SHA256_GUID \
   { \
     0x51aa59de, 0xfdf2, 0x4ea3, {0xbc, 0x63, 0x87, 0x5f, 0xb7, 0x84, 0x2e, 0xe9 } \
-  } 
+  }
 
 #define EFI_HASH_ALGORITHM_SHA384_GUID \
   { \
     0xefa96432, 0xde33, 0x4dd2, {0xae, 0xe6, 0x32, 0x8c, 0x33, 0xdf, 0x77, 0x7a } \
-  } 
+  }
 
 #define EFI_HASH_ALGORITHM_SHA512_GUID \
   { \
@@ -106,7 +100,7 @@ typedef union {
 
   @retval EFI_SUCCESS           Hash size returned successfully.
   @retval EFI_INVALID_PARAMETER HashSize is NULL or HashAlgorithm is NULL.
-  @retval EFI_UNSUPPORTED       The algorithm specified by HashAlgorithm is not supported 
+  @retval EFI_UNSUPPORTED       The algorithm specified by HashAlgorithm is not supported
                                 by this driver.
 
 **/
@@ -116,7 +110,7 @@ EFI_STATUS
   IN  CONST EFI_HASH_PROTOCOL     *This,
   IN  CONST EFI_GUID              *HashAlgorithm,
   OUT UINTN                       *HashSize
-  );      
+  );
 
 /**
   Creates a hash for the specified message text.
@@ -127,13 +121,13 @@ EFI_STATUS
                             existing hash (TRUE).
   @param[in]  Message       Points to the start of the message.
   @param[in]  MessageSize   The size of Message, in bytes.
-  @param[in,out]  Hash      On input, if Extend is TRUE, then this parameter holds a pointer 
-                            to a pointer to an array containing the hash to extend. If Extend 
-                            is FALSE, then this parameter holds a pointer to a pointer to a 
-                            caller-allocated array that will receive the result of the hash 
-                            computation. On output (regardless of the value of Extend), the 
+  @param[in,out]  Hash      On input, if Extend is TRUE, then this parameter holds a pointer
+                            to a pointer to an array containing the hash to extend. If Extend
+                            is FALSE, then this parameter holds a pointer to a pointer to a
+                            caller-allocated array that will receive the result of the hash
+                            computation. On output (regardless of the value of Extend), the
                             array will contain the result of the hash computation.
-  
+
   @retval EFI_SUCCESS           Hash returned successfully.
   @retval EFI_INVALID_PARAMETER Message or Hash, HashAlgorithm is NULL or MessageSize is 0.
                                 MessageSize is not an integer multiple of block size.
@@ -150,10 +144,10 @@ EFI_STATUS
   IN CONST UINT8                  *Message,
   IN UINT64                       MessageSize,
   IN OUT EFI_HASH_OUTPUT          *Hash
-  );    
+  );
 
 ///
-/// This protocol allows creating a hash of an arbitrary message digest 
+/// This protocol allows creating a hash of an arbitrary message digest
 /// using one or more hash algorithms.
 ///
 struct _EFI_HASH_PROTOCOL {
diff --git a/MdePkg/Include/Protocol/Hash2.h b/MdePkg/Include/Protocol/Hash2.h
index d049e8faffa2..9ad0e3023da3 100644
--- a/MdePkg/Include/Protocol/Hash2.h
+++ b/MdePkg/Include/Protocol/Hash2.h
@@ -8,13 +8,7 @@
   message padding and finalization are performed by the supporting driver.
 
 Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under
-the terms and conditions of the BSD License that accompanies this distribution.
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/Protocol/HiiConfigAccess.h b/MdePkg/Include/Protocol/HiiConfigAccess.h
index 3b076511c6e2..21feba5fea56 100644
--- a/MdePkg/Include/Protocol/HiiConfigAccess.h
+++ b/MdePkg/Include/Protocol/HiiConfigAccess.h
@@ -1,18 +1,15 @@
 /** @file
 
-  The EFI HII results processing protocol invokes this type of protocol 
-  when it needs to forward results to a driver's configuration handler. 
-  This protocol is published by drivers providing and requesting 
+  The EFI HII results processing protocol invokes this type of protocol
+  when it needs to forward results to a driver's configuration handler.
+  This protocol is published by drivers providing and requesting
   configuration data from HII. It may only be invoked by HII.
-  
-Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  This Protocol was introduced in UEFI Specification 2.1.
 
 **/
 
@@ -43,7 +40,7 @@ typedef UINTN EFI_BROWSER_ACTION;
 #define EFI_BROWSER_ACTION_DEFAULT_FIRMWARE      0x4000
 
 /**
-   
+
   This function allows the caller to request the current
   configuration for one or more named elements. The resulting
   string is in <ConfigAltResp> format. Any and all alternative
@@ -64,12 +61,12 @@ typedef UINTN EFI_BROWSER_ACTION;
                     includes the routing information as well as
                     the configurable name / value pairs. It is
                     invalid for this string to be in
-                    <MultiConfigRequest> format. 
-                    If a NULL is passed in for the Request field, 
-                    all of the settings being abstracted by this function 
-                    will be returned in the Results field.  In addition, 
-                    if a ConfigHdr is passed in with no request elements, 
-                    all of the settings being abstracted for that particular 
+                    <MultiConfigRequest> format.
+                    If a NULL is passed in for the Request field,
+                    all of the settings being abstracted by this function
+                    will be returned in the Results field.  In addition,
+                    if a ConfigHdr is passed in with no request elements,
+                    all of the settings being abstracted for that particular
                     ConfigHdr reference will be returned in the Results Field.
 
   @param Progress   On return, points to a character in the
@@ -95,7 +92,7 @@ typedef UINTN EFI_BROWSER_ACTION;
                                   stored awaiting possible future
                                   protocols.
 
-  @retval EFI_NOT_FOUND           A configuration element matching 
+  @retval EFI_NOT_FOUND           A configuration element matching
                                   the routing data is not found.
                                   Progress set to the first character
                                   in the routing header.
@@ -121,7 +118,7 @@ EFI_STATUS
 
 
 /**
-   
+
   This function applies changes in a driver's configuration.
   Input is a Configuration, which has the routing data for this
   driver followed by name / value configuration pairs. The driver
@@ -134,8 +131,8 @@ EFI_STATUS
   @param This           Points to the EFI_HII_CONFIG_ACCESS_PROTOCOL.
 
   @param Configuration  A null-terminated Unicode string in
-                        <ConfigString> format. 
-  
+                        <ConfigString> format.
+
   @param Progress       A pointer to a string filled in with the
                         offset of the most recent '&' before the
                         first failing name / value pair (or the
@@ -146,16 +143,16 @@ EFI_STATUS
 
   @retval EFI_SUCCESS             The results have been distributed or are
                                   awaiting distribution.
-  
+
   @retval EFI_OUT_OF_RESOURCES    Not enough memory to store the
                                   parts of the results that must be
                                   stored awaiting possible future
                                   protocols.
-  
+
   @retval EFI_INVALID_PARAMETERS  Passing in a NULL for the
                                   Results parameter would result
                                   in this type of error.
-  
+
   @retval EFI_NOT_FOUND           Target for the specified routing data
                                   was not found
 
@@ -169,7 +166,7 @@ EFI_STATUS
 );
 
 /**
-   
+
   This function is called to provide results data to the driver.
   This data consists of a unique key that is used to identify
   which data is either being passed back or being asked for.
@@ -178,7 +175,7 @@ EFI_STATUS
   @param  Action                 Specifies the type of action taken by the browser.
   @param  QuestionId             A unique value which is sent to the original
                                  exporting driver so that it can identify the type
-                                 of data to expect. The format of the data tends to 
+                                 of data to expect. The format of the data tends to
                                  vary based on the opcode that generated the callback.
   @param  Type                   The type of value for the question.
   @param  Value                  A pointer to the data being sent to the original
@@ -204,7 +201,7 @@ EFI_STATUS
   OUT    EFI_BROWSER_ACTION_REQUEST             *ActionRequest
   )
   ;
-  
+
 ///
 /// This protocol provides a callable interface between the HII and
 /// drivers. Only drivers which provide IFR data to HII are required
diff --git a/MdePkg/Include/Protocol/HiiConfigKeyword.h b/MdePkg/Include/Protocol/HiiConfigKeyword.h
index 1c2d3c67dcac..5786fbc3693e 100644
--- a/MdePkg/Include/Protocol/HiiConfigKeyword.h
+++ b/MdePkg/Include/Protocol/HiiConfigKeyword.h
@@ -1,16 +1,14 @@
 /** @file
-  The file provides the mechanism to set and get the values 
-  associated with a keyword exposed through a x-UEFI- prefixed 
+  The file provides the mechanism to set and get the values
+  associated with a keyword exposed through a x-UEFI- prefixed
   configuration language namespace.
-  
-Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  This Protocol was introduced in UEFI Specification 2.5.
+
 
 **/
 
@@ -40,18 +38,18 @@ typedef struct _EFI_CONFIG_KEYWORD_HANDLER_PROTOCOL EFI_CONFIG_KEYWORD_HANDLER_P
   This function accepts a <MultiKeywordResp> formatted string, finds the associated
   keyword owners, creates a <MultiConfigResp> string from it and forwards it to the
   EFI_HII_ROUTING_PROTOCOL.RouteConfig function.
-  
-  If there is an issue in resolving the contents of the KeywordString, then the 
-  function returns an error and also sets the Progress and ProgressErr with the 
+
+  If there is an issue in resolving the contents of the KeywordString, then the
+  function returns an error and also sets the Progress and ProgressErr with the
   appropriate information about where the issue occurred and additional data about
-  the nature of the issue. 
-  
+  the nature of the issue.
+
   In the case when KeywordString containing multiple keywords, when an EFI_NOT_FOUND
   error is generated during processing the second or later keyword element, the system
-  storage associated with earlier keywords is not modified. All elements of the 
+  storage associated with earlier keywords is not modified. All elements of the
   KeywordString must successfully pass all tests for format and access prior to making
   any modifications to storage.
-  
+
   In the case when EFI_DEVICE_ERROR is returned from the processing of a KeywordString
   containing multiple keywords, the state of storage associated with earlier keywords
   is undefined.
@@ -59,18 +57,18 @@ typedef struct _EFI_CONFIG_KEYWORD_HANDLER_PROTOCOL EFI_CONFIG_KEYWORD_HANDLER_P
 
   @param This             Pointer to the EFI_KEYWORD_HANDLER _PROTOCOL instance.
 
-  @param KeywordString    A null-terminated string in <MultiKeywordResp> format. 
+  @param KeywordString    A null-terminated string in <MultiKeywordResp> format.
 
-  @param Progress         On return, points to a character in the KeywordString. 
-                          Points to the string's NULL terminator if the request 
-                          was successful. Points to the most recent '&' before 
+  @param Progress         On return, points to a character in the KeywordString.
+                          Points to the string's NULL terminator if the request
+                          was successful. Points to the most recent '&' before
                           the first failing name / value pair (or the beginning
                           of the string if the failure is in the first name / value
                           pair) if the request was not successful.
 
   @param ProgressErr      If during the processing of the KeywordString there was
-                          a failure, this parameter gives additional information 
-                          about the possible source of the problem. The various 
+                          a failure, this parameter gives additional information
+                          about the possible source of the problem. The various
                           errors are defined in "Related Definitions" below.
 
 
@@ -78,23 +76,23 @@ typedef struct _EFI_CONFIG_KEYWORD_HANDLER_PROTOCOL EFI_CONFIG_KEYWORD_HANDLER_P
 
   @retval EFI_INVALID_PARAMETER   One or more of the following are TRUE:
                                   1. KeywordString is NULL.
-                                  2. Parsing of the KeywordString resulted in an 
+                                  2. Parsing of the KeywordString resulted in an
                                      error. See Progress and ProgressErr for more data.
 
-  @retval EFI_NOT_FOUND           An element of the KeywordString was not found. 
+  @retval EFI_NOT_FOUND           An element of the KeywordString was not found.
                                   See ProgressErr for more data.
 
-  @retval EFI_OUT_OF_RESOURCES    Required system resources could not be allocated.  
+  @retval EFI_OUT_OF_RESOURCES    Required system resources could not be allocated.
                                   See ProgressErr for more data.
-                                  
-  @retval EFI_ACCESS_DENIED       The action violated system policy. See ProgressErr 
+
+  @retval EFI_ACCESS_DENIED       The action violated system policy. See ProgressErr
                                   for more data.
 
   @retval EFI_DEVICE_ERROR        An unexpected system error occurred. See ProgressErr
                                   for more data.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_CONFIG_KEYWORD_HANDLER_SET_DATA) (
   IN EFI_CONFIG_KEYWORD_HANDLER_PROTOCOL *This,
@@ -106,56 +104,56 @@ EFI_STATUS
 
 /**
 
-  This function accepts a <MultiKeywordRequest> formatted string, finds the underlying 
+  This function accepts a <MultiKeywordRequest> formatted string, finds the underlying
   keyword owners, creates a <MultiConfigRequest> string from it and forwards it to the
   EFI_HII_ROUTING_PROTOCOL.ExtractConfig function.
-  
+
   If there is an issue in resolving the contents of the KeywordString, then the function
   returns an EFI_INVALID_PARAMETER and also set the Progress and ProgressErr with the
   appropriate information about where the issue occurred and additional data about the
   nature of the issue.
-  
+
   In the case when KeywordString is NULL, or contains multiple keywords, or when
   EFI_NOT_FOUND is generated while processing the keyword elements, the Results string
-  contains values returned for all keywords processed prior to the keyword generating the 
+  contains values returned for all keywords processed prior to the keyword generating the
   error but no values for the keyword with error or any following keywords.
 
-  
+
   @param This           Pointer to the EFI_KEYWORD_HANDLER _PROTOCOL instance.
-  
+
   @param NameSpaceId    A null-terminated string containing the platform configuration
                         language to search through in the system. If a NULL is passed
                         in, then it is assumed that any platform configuration language
                         with the prefix of "x-UEFI-" are searched.
-                        
+
   @param KeywordString  A null-terminated string in <MultiKeywordRequest> format. If a
-                        NULL is passed in the KeywordString field, all of the known 
-                        keywords in the system for the NameSpaceId specified are 
+                        NULL is passed in the KeywordString field, all of the known
+                        keywords in the system for the NameSpaceId specified are
                         returned in the Results field.
-  
+
   @param Progress       On return, points to a character in the KeywordString. Points
-                        to the string's NULL terminator if the request was successful. 
+                        to the string's NULL terminator if the request was successful.
                         Points to the most recent '&' before the first failing name / value
                         pair (or the beginning of the string if the failure is in the first
                         name / value pair) if the request was not successful.
-                        
+
   @param ProgressErr    If during the processing of the KeywordString there was a
-                        failure, this parameter gives additional information about the 
+                        failure, this parameter gives additional information about the
                         possible source of the problem. See the definitions in SetData()
                         for valid value definitions.
-  
+
   @param Results        A null-terminated string in <MultiKeywordResp> format is returned
-                        which has all the values filled in for the keywords in the 
+                        which has all the values filled in for the keywords in the
                         KeywordString. This is a callee-allocated field, and must be freed
-                        by the caller after being used. 
+                        by the caller after being used.
 
   @retval EFI_SUCCESS             The specified action was completed successfully.
-  
+
   @retval EFI_INVALID_PARAMETER   One or more of the following are TRUE:
                                   1.Progress, ProgressErr, or Results is NULL.
                                   2.Parsing of the KeywordString resulted in an error. See
                                     Progress and ProgressErr for more data.
-  
+
 
   @retval EFI_NOT_FOUND           An element of the KeywordString was not found. See
                                   ProgressErr for more data.
@@ -165,7 +163,7 @@ EFI_STATUS
 
   @retval EFI_OUT_OF_RESOURCES    Required system resources could not be allocated.  See
                                   ProgressErr for more data.
-                                  
+
   @retval EFI_ACCESS_DENIED       The action violated system policy.  See ProgressErr for
                                   more data.
 
@@ -173,20 +171,20 @@ EFI_STATUS
                                   for more data.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_CONFIG_KEYWORD_HANDLER_GET_DATA) (
   IN EFI_CONFIG_KEYWORD_HANDLER_PROTOCOL  *This,
   IN CONST EFI_STRING                     NameSpaceId, OPTIONAL
   IN CONST EFI_STRING                     KeywordString, OPTIONAL
-  OUT EFI_STRING                          *Progress, 
+  OUT EFI_STRING                          *Progress,
   OUT UINT32                              *ProgressErr,
   OUT EFI_STRING                          *Results
   );
 
 ///
-/// The EFI_CONFIG_KEYWORD_HANDLER_PROTOCOL provides the mechanism 
-/// to set and get the values associated with a keyword exposed 
+/// The EFI_CONFIG_KEYWORD_HANDLER_PROTOCOL provides the mechanism
+/// to set and get the values associated with a keyword exposed
 /// through a x-UEFI- prefixed configuration language namespace
 ///
 
diff --git a/MdePkg/Include/Protocol/HiiConfigRouting.h b/MdePkg/Include/Protocol/HiiConfigRouting.h
index 89f3f9b2dbfd..88f98d19fdfd 100644
--- a/MdePkg/Include/Protocol/HiiConfigRouting.h
+++ b/MdePkg/Include/Protocol/HiiConfigRouting.h
@@ -4,15 +4,13 @@
   It then serves as the single point to receive configuration
   information from configuration applications, routing the
   results to the appropriate drivers.
-  
-Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  This Protocol was introduced in UEFI Specification 2.1.
+
 
 **/
 
@@ -26,7 +24,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 typedef struct _EFI_HII_CONFIG_ROUTING_PROTOCOL EFI_HII_CONFIG_ROUTING_PROTOCOL;
 
 /**
-   
+
   This function allows the caller to request the current
   configuration for one or more named elements from one or more
   drivers. The resulting string is in the standard HII
@@ -84,8 +82,8 @@ typedef struct _EFI_HII_CONFIG_ROUTING_PROTOCOL EFI_HII_CONFIG_ROUTING_PROTOCOL;
                                   for the Request parameter
                                   would result in this type of
                                   error. The Progress parameter
-                                  is set to NULL. 
-  
+                                  is set to NULL.
+
   @retval EFI_NOT_FOUND           Routing data doesn't match any
                                   known driver. Progress set to
                                   the "G" in "GUID" of the
@@ -100,8 +98,8 @@ typedef struct _EFI_HII_CONFIG_ROUTING_PROTOCOL EFI_HII_CONFIG_ROUTING_PROTOCOL;
                                   error, or the beginning of the
                                   string.
   @retval EFI_INVALID_PARAMETER   The ExtractConfig function of the
-                                  underlying HII Configuration 
-                                  Access Protocol returned 
+                                  underlying HII Configuration
+                                  Access Protocol returned
                                   EFI_INVALID_PARAMETER. Progress
                                   set to most recent & before the
                                   error or the beginning of the
@@ -118,32 +116,32 @@ EFI_STATUS
 );
 
 /**
-  This function allows the caller to request the current configuration 
+  This function allows the caller to request the current configuration
   for the entirety of the current HII database and returns the data in
   a null-terminated string.
 
   This function allows the caller to request the current
   configuration for all of the current HII database. The results
   include both the current and alternate configurations as
-  described in ExtractConfig() above. 
-  
+  described in ExtractConfig() above.
+
   @param This     Points to the EFI_HII_CONFIG_ROUTING_PROTOCOL instance.
-  
+
   @param  Results Null-terminated Unicode string in
                   <MultiConfigAltResp> format which has all values
-                  filled in for the entirety of the current HII 
-                  database. String to be allocated by the  called 
+                  filled in for the entirety of the current HII
+                  database. String to be allocated by the  called
                   function. De-allocation is up to the caller.
-  
+
   @retval EFI_SUCCESS             The Results string is filled with the
                                   values corresponding to all requested
                                   names.
-  
+
   @retval EFI_OUT_OF_RESOURCES    Not enough memory to store the
                                   parts of the results that must be
                                   stored awaiting possible future
                                   protocols.
-  
+
   @retval EFI_INVALID_PARAMETERS  For example, passing in a NULL
                                   for the Results parameter
                                   would result in this type of
@@ -158,7 +156,7 @@ EFI_STATUS
 );
 
 /**
-   
+
   This function routes the results of processing forms to the
   appropriate targets. It scans for <ConfigHdr> within the string
   and passes the header and subsequent body to the driver whose
@@ -182,16 +180,16 @@ EFI_STATUS
 
   @retval EFI_SUCCESS             The results have been distributed or are
                                   awaiting distribution.
-  
+
   @retval EFI_OUT_OF_RESOURCES    Not enough memory to store the
                                   parts of the results that must be
                                   stored awaiting possible future
                                   protocols.
-  
+
   @retval EFI_INVALID_PARAMETERS  Passing in a NULL for the
                                   Results parameter would result
                                   in this type of error.
-  
+
   @retval EFI_NOT_FOUND           The target for the specified routing data
                                   was not found.
 
@@ -206,7 +204,7 @@ EFI_STATUS
 
 
 /**
-   
+
   This function extracts the current configuration from a block of
   bytes. To do so, it requires that the ConfigRequest string
   consists of a list of <BlockName> formatted names. It uses the
@@ -228,7 +226,7 @@ EFI_STATUS
 
   @param Config     The filled-in configuration string. String
                     allocated by the function. Returned only if
-                    call is successful. The null-terminated string 
+                    call is successful. The null-terminated string
                     will be <ConfigResp> format.
 
   @param Progress   A pointer to a string filled in with the
@@ -256,7 +254,7 @@ EFI_STATUS
   @retval EFI_NOT_FOUND           The target for the specified routing data
                                   was not found. Progress points to the
                                   'G' in "GUID" of the errant routing
-                                  data. 
+                                  data.
   @retval EFI_DEVICE_ERROR        The block is not large enough. Progress undefined.
 
   @retval EFI_INVALID_PARAMETER   Encountered non <BlockName>
@@ -310,7 +308,7 @@ EFI_STATUS
 
   @param BlockSize      The length of the Block in units of UINT8.
                         On input, this is the size of the Block. On
-                        output, if successful, contains the largest 
+                        output, if successful, contains the largest
                         index of the modified byte in the Block, or
                         the required buffer size if the Block is not
                         large enough.
@@ -339,7 +337,7 @@ EFI_STATUS
   @retval EFI_NOT_FOUND          Target for the specified routing data was not found.
                                  Progress points to the "G" in "GUID" of the errant
                                  routing data.
-  @retval EFI_BUFFER_TOO_SMALL   Block not large enough. Progress undefined. 
+  @retval EFI_BUFFER_TOO_SMALL   Block not large enough. Progress undefined.
                                  BlockSize is updated with the required buffer size.
 
 **/
@@ -354,48 +352,48 @@ EFI_STATUS
 );
 
 /**
-  This helper function is to be called by drivers to extract portions of 
+  This helper function is to be called by drivers to extract portions of
   a larger configuration string.
-          
+
   @param This              A pointer to the EFI_HII_CONFIG_ROUTING_PROTOCOL instance.
   @param ConfigResp        A null-terminated string in <ConfigAltResp> format.
-  @param Guid              A pointer to the GUID value to search for in the 
-                           routing portion of the ConfigResp string when retrieving 
-                           the requested data. If Guid is NULL, then all GUID 
+  @param Guid              A pointer to the GUID value to search for in the
+                           routing portion of the ConfigResp string when retrieving
+                           the requested data. If Guid is NULL, then all GUID
+                           values will be searched for.
+  @param Name              A pointer to the NAME value to search for in the
+                           routing portion of the ConfigResp string when retrieving
+                           the requested data. If Name is NULL, then all Name
                            values will be searched for.
-  @param Name              A pointer to the NAME value to search for in the 
-                           routing portion of the ConfigResp string when retrieving 
-                           the requested data. If Name is NULL, then all Name 
-                           values will be searched for.                         
-  @param DevicePath        A pointer to the PATH value to search for in the 
-                           routing portion of the ConfigResp string when retrieving 
-                           the requested data. If DevicePath is NULL, then all 
-                           DevicePath values will be searched for.             
-  @param AltCfgId          A pointer to the ALTCFG value to search for in the 
-                           routing portion of the ConfigResp string when retrieving 
-                           the requested data.  If this parameter is NULL, 
+  @param DevicePath        A pointer to the PATH value to search for in the
+                           routing portion of the ConfigResp string when retrieving
+                           the requested data. If DevicePath is NULL, then all
+                           DevicePath values will be searched for.
+  @param AltCfgId          A pointer to the ALTCFG value to search for in the
+                           routing portion of the ConfigResp string when retrieving
+                           the requested data.  If this parameter is NULL,
                            then the current setting will be retrieved.
-  @param AltCfgResp        A pointer to a buffer which will be allocated by the 
-                           function which contains the retrieved string as requested.  
-                           This buffer is only allocated if the call was successful. 
+  @param AltCfgResp        A pointer to a buffer which will be allocated by the
+                           function which contains the retrieved string as requested.
+                           This buffer is only allocated if the call was successful.
                            The null-terminated string will be <ConfigResp> format.
-  
-  @retval EFI_SUCCESS             The request succeeded. The requested data was extracted 
+
+  @retval EFI_SUCCESS             The request succeeded. The requested data was extracted
                                   and placed in the newly allocated AltCfgResp buffer.
-  @retval EFI_OUT_OF_RESOURCES    Not enough memory to allocate AltCfgResp.    
+  @retval EFI_OUT_OF_RESOURCES    Not enough memory to allocate AltCfgResp.
   @retval EFI_INVALID_PARAMETER   Any parameter is invalid.
   @retval EFI_NOT_FOUND           The target for the specified routing data was not found.
 **/
 typedef
-EFI_STATUS 
+EFI_STATUS
 (EFIAPI * EFI_HII_GET_ALT_CFG)(
-  IN  CONST EFI_HII_CONFIG_ROUTING_PROTOCOL    *This, 
-  IN  CONST EFI_STRING                         ConfigResp, 
-  IN  CONST EFI_GUID                           *Guid, 
-  IN  CONST EFI_STRING                         Name, 
-  IN  CONST EFI_DEVICE_PATH_PROTOCOL           *DevicePath,  
+  IN  CONST EFI_HII_CONFIG_ROUTING_PROTOCOL    *This,
+  IN  CONST EFI_STRING                         ConfigResp,
+  IN  CONST EFI_GUID                           *Guid,
+  IN  CONST EFI_STRING                         Name,
+  IN  CONST EFI_DEVICE_PATH_PROTOCOL           *DevicePath,
   IN  CONST UINT16                             *AltCfgId,
-  OUT EFI_STRING                               *AltCfgResp 
+  OUT EFI_STRING                               *AltCfgResp
   );
 
 ///
diff --git a/MdePkg/Include/Protocol/HiiDatabase.h b/MdePkg/Include/Protocol/HiiDatabase.h
index 435fe1be787a..8ea5b7d90996 100644
--- a/MdePkg/Include/Protocol/HiiDatabase.h
+++ b/MdePkg/Include/Protocol/HiiDatabase.h
@@ -1,15 +1,12 @@
 /** @file
   The file provides Database manager for HII-related data
   structures.
-  
-Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  This Protocol was introduced in UEFI Specification 2.1.
 
 **/
 
@@ -25,7 +22,7 @@ typedef struct _EFI_HII_DATABASE_PROTOCOL EFI_HII_DATABASE_PROTOCOL;
 
 ///
 /// EFI_HII_DATABASE_NOTIFY_TYPE.
-/// 
+///
 typedef UINTN   EFI_HII_DATABASE_NOTIFY_TYPE;
 
 #define EFI_HII_DATABASE_NOTIFY_NEW_PACK    0x00000001
@@ -33,7 +30,7 @@ typedef UINTN   EFI_HII_DATABASE_NOTIFY_TYPE;
 #define EFI_HII_DATABASE_NOTIFY_EXPORT_PACK 0x00000004
 #define EFI_HII_DATABASE_NOTIFY_ADD_PACK    0x00000008
 /**
-   
+
   Functions which are registered to receive notification of
   database events have this prototype. The actual event is encoded
   in NotifyType. The following table describes how PackageType,
@@ -48,8 +45,8 @@ typedef UINTN   EFI_HII_DATABASE_NOTIFY_TYPE;
                       field of EFI_HII_PACKAGE_GUID_HEADER.
                       Otherwise, it must be NULL.
 
-  @param Package      Points to the package referred to by the notification. 
-  
+  @param Package      Points to the package referred to by the notification.
+
   @param Handle       The handle of the package
                       list which contains the specified package.
 
@@ -80,7 +77,7 @@ EFI_STATUS
   be called. For each call to NewPackageList(), there should be a
   corresponding call to
   EFI_HII_DATABASE_PROTOCOL.RemovePackageList().
-  
+
   @param This           A pointer to the EFI_HII_DATABASE_PROTOCOL instance.
 
   @param PackageList    A pointer to an EFI_HII_PACKAGE_LIST_HEADER structure.
@@ -88,7 +85,7 @@ EFI_STATUS
   @param DriverHandle   Associate the package list with this EFI handle.
                         If a NULL is specified, this data will not be associate
                         with any drivers and cannot have a callback induced.
-  
+
   @param Handle         A pointer to the EFI_HII_HANDLE instance.
 
   @retval EFI_SUCCESS           The package list associated with the
@@ -121,10 +118,10 @@ EFI_STATUS
   be a corresponding call to RemovePackageList.
 
   @param This             A pointer to the EFI_HII_DATABASE_PROTOCOL instance.
-  
+
   @param Handle           The handle that was registered to the data
                           that is requested for removal.
-  
+
   @retval EFI_SUCCESS     The data associated with the Handle was
                           removed from the HII database.
   @retval EFI_NOT_FOUND   The specified Handle is not in database.
@@ -139,7 +136,7 @@ EFI_STATUS
 
 
 /**
-   
+
   This function updates the existing package list (which has the
   specified Handle) in the HII databases, using the new package
   list specified by PackageList. The update process has the
@@ -162,18 +159,18 @@ EFI_STATUS
   ADD_PACK.
 
   @param This         A pointer to the EFI_HII_DATABASE_PROTOCOL instance.
-  
+
   @param Handle       The handle that was registered to the data
                       that is requested for removal.
-  
+
   @param PackageList  A pointer to an EFI_HII_PACKAGE_LIST
                       package.
-  
+
   @retval EFI_SUCCESS            The HII database was successfully updated.
-  
+
   @retval EFI_OUT_OF_RESOURCES   Unable to allocate enough memory
                                  for the updated database.
-  
+
   @retval EFI_INVALID_PARAMETER  PackageList was NULL.
   @retval EFI_NOT_FOUND          The specified Handle is not in database.
 
@@ -188,25 +185,25 @@ EFI_STATUS
 
 
 /**
-  
-  This function returns a list of the package handles of the   
-  specified type that are currently active in the database. The   
-  pseudo-type EFI_HII_PACKAGE_TYPE_ALL will cause all package   
+
+  This function returns a list of the package handles of the
+  specified type that are currently active in the database. The
+  pseudo-type EFI_HII_PACKAGE_TYPE_ALL will cause all package
   handles to be listed.
-  
+
   @param This                 A pointer to the EFI_HII_DATABASE_PROTOCOL instance.
-  
+
   @param PackageType          Specifies the package type of the packages
                               to list or EFI_HII_PACKAGE_TYPE_ALL for
                               all packages to be listed.
-  
+
   @param PackageGuid          If PackageType is
                               EFI_HII_PACKAGE_TYPE_GUID, then this is
                               the pointer to the GUID which must match
                               the Guid field of
                               EFI_HII_PACKAGE_GUID_HEADER. Otherwise, it
                               must be NULL.
-  
+
   @param HandleBufferLength   On input, a pointer to the length
                               of the handle buffer. On output,
                               the length of the handle buffer
@@ -258,7 +255,7 @@ EFI_STATUS
   @param Handle       An EFI_HII_HANDLE  that corresponds to the
                       desired package list in the HII database to
                       export or NULL to indicate all package lists
-                      should be exported. 
+                      should be exported.
 
   @param BufferSize   On input, a pointer to the length of the
                       buffer. On output, the length of the
@@ -267,18 +264,18 @@ EFI_STATUS
 
   @param Buffer       A pointer to a buffer that will contain the
                       results of the export function.
-  
-  
+
+
   @retval EFI_SUCCESS           Package exported.
-  
+
   @retval EFI_OUT_OF_RESOURCES  BufferSize is too small to hold the package.
 
   @retval EFI_NOT_FOUND         The specified Handle could not be found in the
                                 current database.
-  
+
   @retval EFI_INVALID_PARAMETER BufferSize was NULL.
-  
-  @retval EFI_INVALID_PARAMETER The value referenced by BufferSize was not zero 
+
+  @retval EFI_INVALID_PARAMETER The value referenced by BufferSize was not zero
                                 and Buffer was NULL.
 **/
 typedef
@@ -292,8 +289,8 @@ EFI_STATUS
 
 
 /**
-   
-  
+
+
   This function registers a function which will be called when
   specified actions related to packages of the specified type
   occur in the HII database. By registering a function, other
@@ -302,12 +299,12 @@ EFI_STATUS
   or application which registers a notification should use
   EFI_HII_DATABASE_PROTOCOL.UnregisterPackageNotify() before
   exiting.
-  
-  
+
+
   @param This             A pointer to the EFI_HII_DATABASE_PROTOCOL instance.
 
   @param PackageType      The package type. See
-                          EFI_HII_PACKAGE_TYPE_x in EFI_HII_PACKAGE_HEADER. 
+                          EFI_HII_PACKAGE_TYPE_x in EFI_HII_PACKAGE_HEADER.
 
   @param PackageGuid      If PackageType is
                           EFI_HII_PACKAGE_TYPE_GUID, then this is
@@ -355,19 +352,19 @@ EFI_STATUS
 
 
 /**
-   
+
   Removes the specified HII database package-related notification.
-  
+
   @param This                 A pointer to the EFI_HII_DATABASE_PROTOCOL instance.
 
   @param NotificationHandle   The handle of the notification
                               function being unregistered.
-  
-  @retval EFI_SUCCESS   Successsfully unregistered the notification. 
-  
-  @retval EFI_NOT_FOUND The incoming notification handle does not exist 
+
+  @retval EFI_SUCCESS   Successsfully unregistered the notification.
+
+  @retval EFI_NOT_FOUND The incoming notification handle does not exist
                         in the current hii database.
-  
+
 **/
 typedef
 EFI_STATUS
@@ -378,7 +375,7 @@ EFI_STATUS
 
 
 /**
-   
+
   This routine retrieves an array of GUID values for each keyboard
   layout that was previously registered in the system.
 
@@ -388,13 +385,13 @@ EFI_STATUS
                               of the keyboard GUID buffer. On
                               output, the length of the handle
                               buffer that is required for the
-                              handles found. 
-  
+                              handles found.
+
   @param KeyGuidBuffer        An array of keyboard layout GUID
                               instances returned.
 
   @retval EFI_SUCCESS           KeyGuidBuffer was updated successfully.
-  
+
   @retval EFI_BUFFER_TOO_SMALL  The KeyGuidBufferLength
                                 parameter indicates that
                                 KeyGuidBuffer is too small to
@@ -403,7 +400,7 @@ EFI_STATUS
                                 with a value that will enable
                                 the data to fit.
   @retval EFI_INVALID_PARAMETER The KeyGuidBufferLength is NULL.
-  @retval EFI_INVALID_PARAMETER The value referenced by 
+  @retval EFI_INVALID_PARAMETER The value referenced by
                                 KeyGuidBufferLength is not
                                 zero and KeyGuidBuffer is NULL.
   @retval EFI_NOT_FOUND         There was no keyboard layout.
@@ -419,14 +416,14 @@ EFI_STATUS
 
 
 /**
-   
+
   This routine retrieves the requested keyboard layout. The layout
   is a physical description of the keys on a keyboard, and the
   character(s) that are associated with a particular set of key
   strokes.
 
   @param This                   A pointer to the EFI_HII_PROTOCOL instance.
-  
+
   @param KeyGuid                A pointer to the unique ID associated with a
                                 given keyboard layout. If KeyGuid is NULL then
                                 the current layout will be retrieved.
@@ -434,13 +431,13 @@ EFI_STATUS
   @param KeyboardLayoutLength   On input, a pointer to the length of the
                                 KeyboardLayout buffer.  On output, the length of
                                 the data placed into KeyboardLayout.
-  
+
   @param KeyboardLayout         A pointer to a buffer containing the
                                 retrieved keyboard layout.
-  
+
   @retval EFI_SUCCESS   The keyboard layout was retrieved
                         successfully.
-  
+
   @retval EFI_NOT_FOUND The requested keyboard layout was not found.
 
 **/
@@ -454,7 +451,7 @@ EFI_STATUS
 );
 
 /**
-   
+
   This routine sets the default keyboard layout to the one
   referenced by KeyGuid. When this routine is called, an event
   will be signaled of the EFI_HII_SET_KEYBOARD_LAYOUT_EVENT_GUID
@@ -481,21 +478,21 @@ EFI_STATUS
 );
 
 /**
-   
+
   Return the EFI handle associated with a package list.
-  
+
   @param This               A pointer to the EFI_HII_PROTOCOL instance.
-  
+
   @param PackageListHandle  An EFI_HII_HANDLE  that corresponds
                             to the desired package list in the
                             HIIdatabase.
-  
+
   @param DriverHandle       On return, contains the EFI_HANDLE which
                             was registered with the package list in
                             NewPackageList().
-  
+
   @retval EFI_SUCCESS            The DriverHandle was returned successfully.
-  
+
   @retval EFI_INVALID_PARAMETER  The PackageListHandle was not valid.
 
 **/
diff --git a/MdePkg/Include/Protocol/HiiFont.h b/MdePkg/Include/Protocol/HiiFont.h
index b94073449611..c229e394423d 100644
--- a/MdePkg/Include/Protocol/HiiFont.h
+++ b/MdePkg/Include/Protocol/HiiFont.h
@@ -1,14 +1,11 @@
 /** @file
   The file provides services to retrieve font information.
-  
-Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  This Protocol was introduced in UEFI Specification 2.1.
 
 **/
 
@@ -27,7 +24,7 @@ typedef VOID    *EFI_FONT_HANDLE;
 
 ///
 /// EFI_HII_OUT_FLAGS.
-/// 
+///
 typedef UINT32  EFI_HII_OUT_FLAGS;
 
 #define EFI_HII_OUT_FLAG_CLIP         0x00000001
@@ -49,12 +46,12 @@ typedef struct _EFI_HII_ROW_INFO {
   UINTN   StartIndex;
   ///
   /// The index of the last character in the string which is displayed on the line.
-  /// If this is the same as StartIndex, then no characters are displayed.  
+  /// If this is the same as StartIndex, then no characters are displayed.
   ///
   UINTN   EndIndex;
   UINTN   LineHeight; ///< The height of the line, in pixels.
   UINTN   LineWidth;  ///< The width of the text on the line, in pixels.
-  
+
   ///
   /// The font baseline offset in pixels from the bottom of the row, or 0 if none.
   ///
@@ -80,7 +77,7 @@ typedef UINT32  EFI_FONT_INFO_MASK;
 
 //
 // EFI_FONT_INFO
-// 
+//
 typedef struct {
   EFI_HII_FONT_STYLE FontStyle;
   UINT16             FontSize;      ///< character cell height in pixels
@@ -103,7 +100,7 @@ typedef struct _EFI_FONT_DISPLAY_INFO {
   EFI_GRAPHICS_OUTPUT_BLT_PIXEL ForegroundColor;
   EFI_GRAPHICS_OUTPUT_BLT_PIXEL BackgroundColor;
   EFI_FONT_INFO_MASK            FontInfoMask;
-  EFI_FONT_INFO                 FontInfo;  
+  EFI_FONT_INFO                 FontInfo;
 } EFI_FONT_DISPLAY_INFO;
 
 /**
@@ -155,7 +152,7 @@ typedef struct _EFI_FONT_DISPLAY_INFO {
 
   @param Flags            Describes how the string is to be drawn.
 
-  @param String           Points to the null-terminated string to be 
+  @param String           Points to the null-terminated string to be
 
   @param StringInfo       Points to the string output information,
                           including the color and font. If NULL, then
@@ -203,9 +200,9 @@ typedef struct _EFI_FONT_DISPLAY_INFO {
                           overlap.
 
   @retval EFI_SUCCESS           The string was successfully updated.
-  
+
   @retval EFI_OUT_OF_RESOURCES  Unable to allocate an output buffer for RowInfoArray or Blt.
-  
+
   @retval EFI_INVALID_PARAMETER The String or Blt was NULL.
 
   @retval EFI_INVALID_PARAMETER Flags were invalid combination.
@@ -276,7 +273,7 @@ EFI_STATUS
 
   @param Flags      Describes how the string is to be drawn.
 
-  @param PackageList  
+  @param PackageList
                     The package list in the HII database to
                     search for the specified string.
 
@@ -342,8 +339,8 @@ EFI_STATUS
                                 Width was NULL.
   @retval EFI_INVALID_PARAMETER The Blt or PackageList was NULL.
   @retval EFI_INVALID_PARAMETER Flags were invalid combination.
-  @retval EFI_NOT_FOUND         The specified PackageList is not in the Database, 
-                                or the stringid is not in the specified PackageList. 
+  @retval EFI_NOT_FOUND         The specified PackageList is not in the Database,
+                                or the stringid is not in the specified PackageList.
 
 **/
 typedef
@@ -424,26 +421,26 @@ EFI_STATUS
                         to NULL if there are no more matching fonts.
 
   @param StringInfoIn   Upon entry, points to the font to return
-                        information about. If NULL, then the information 
+                        information about. If NULL, then the information
                         about the system default font will be returned.
 
   @param  StringInfoOut Upon return, contains the matching font's information.
                         If NULL, then no information is returned. This buffer
                         is allocated with a call to the Boot Service AllocatePool().
-                        It is the caller's responsibility to call the Boot 
+                        It is the caller's responsibility to call the Boot
                         Service FreePool() when the caller no longer requires
                         the contents of StringInfoOut.
 
   @param String         Points to the string which will be tested to
                         determine if all characters are available. If
                         NULL, then any font is acceptable.
-  
+
   @retval EFI_SUCCESS            Matching font returned successfully.
-  
+
   @retval EFI_NOT_FOUND          No matching font was found.
 
   @retval EFI_OUT_OF_RESOURCES   There were insufficient resources to complete the request.
-  
+
 **/
 typedef
 EFI_STATUS
diff --git a/MdePkg/Include/Protocol/HiiImage.h b/MdePkg/Include/Protocol/HiiImage.h
index 3407532ea2c1..ef4559988e4f 100644
--- a/MdePkg/Include/Protocol/HiiImage.h
+++ b/MdePkg/Include/Protocol/HiiImage.h
@@ -1,14 +1,11 @@
 /** @file
   The file provides services to access to images in the images database.
-  
-  Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  This Protocol was introduced in UEFI Specification 2.1.
 
 **/
 
@@ -25,18 +22,18 @@ typedef struct _EFI_HII_IMAGE_PROTOCOL EFI_HII_IMAGE_PROTOCOL;
 
 ///
 /// Flags in EFI_IMAGE_INPUT
-/// 
+///
 #define EFI_IMAGE_TRANSPARENT 0x00000001
 
 /**
-   
+
   Definition of EFI_IMAGE_INPUT.
-   
+
   @param Flags  Describe image characteristics. If
                 EFI_IMAGE_TRANSPARENT is set, then the image was
                 designed for transparent display.
 
-  @param Width  Image width, in pixels. 
+  @param Width  Image width, in pixels.
 
   @param Height Image height, in pixels.
 
@@ -44,7 +41,7 @@ typedef struct _EFI_HII_IMAGE_PROTOCOL EFI_HII_IMAGE_PROTOCOL;
                 top-to-bottom. The size of the bitmap is
                 Width*Height*sizeof(EFI_GRAPHICS_OUTPUT_BLT_PIXEL).
 
-   
+
 **/
 typedef struct _EFI_IMAGE_INPUT {
   UINT32                          Flags;
@@ -60,8 +57,8 @@ typedef struct _EFI_IMAGE_INPUT {
   owned by PackageList, and returns a new image identifier
   (ImageId).
 
-  @param This        A pointer to the EFI_HII_IMAGE_PROTOCOL instance. 
-  
+  @param This        A pointer to the EFI_HII_IMAGE_PROTOCOL instance.
+
   @param PackageList Handle of the package list where this image will be added.
 
   @param ImageId     On return, contains the new image id, which is
@@ -71,9 +68,9 @@ typedef struct _EFI_IMAGE_INPUT {
 
   @retval EFI_SUCCESS             The new image was added
                                   successfully
-  
+
   @retval EFI_OUT_OF_RESOURCES    Could not add the image.
-  
+
   @retval EFI_INVALID_PARAMETER   Image is NULL or ImageId is
                                   NULL.
 
@@ -100,21 +97,21 @@ EFI_STATUS
   updated to the size of buffer actually required to hold the
   image.
 
-  @param This         A pointer to the EFI_HII_IMAGE_PROTOCOL instance. 
-  
+  @param This         A pointer to the EFI_HII_IMAGE_PROTOCOL instance.
+
   @param PackageList  The package list in the HII database to
                       search for the specified image.
-  
+
   @param ImageId      The image's id, which is unique within
                       PackageList.
-  
+
   @param Image        Points to the new image.
-  
+
   @retval EFI_SUCCESS            The image was returned successfully.
 
   @retval EFI_NOT_FOUND          The image specified by ImageId is not
                                  available. Or The specified PackageList is not in the database.
-  
+
   @retval EFI_INVALID_PARAMETER  The Image or Langugae was NULL.
   @retval EFI_OUT_OF_RESOURCES   The bitmap could not be retrieved because there was not
                                  enough memory.
@@ -131,12 +128,12 @@ EFI_STATUS
 );
 
 /**
-   
+
   This function updates the image specified by ImageId in the
   specified PackageListHandle to the image specified by Image.
 
 
-  @param This         A pointer to the EFI_HII_IMAGE_PROTOCOL instance. 
+  @param This         A pointer to the EFI_HII_IMAGE_PROTOCOL instance.
 
   @param PackageList  The package list containing the images.
 
@@ -145,10 +142,10 @@ EFI_STATUS
   @param Image        Points to the image.
 
   @retval EFI_SUCCESS           The image was successfully updated.
-  
+
   @retval EFI_NOT_FOUND         The image specified by ImageId is not in the database.
-                                The specified PackageList is not in the database. 
-  
+                                The specified PackageList is not in the database.
+
   @retval EFI_INVALID_PARAMETER The Image or Language was NULL.
 
 **/
@@ -176,9 +173,9 @@ typedef UINT32  EFI_HII_DRAW_FLAGS;
 #define EFI_HII_DIRECT_TO_SCREEN        0x00000080
 
 /**
-   
+
   Definition of EFI_IMAGE_OUTPUT.
-   
+
   @param Width  Width of the output image.
 
   @param Height Height of the output image.
@@ -201,7 +198,7 @@ typedef struct _EFI_IMAGE_OUTPUT {
 
 
 /**
-   
+
   This function renders an image to a bitmap or the screen using
   the specified color and options. It draws the image on an
   existing bitmap, allocates a new bitmap or uses the screen. The
@@ -216,14 +213,14 @@ typedef struct _EFI_IMAGE_OUTPUT {
   specified by Bitmap.
 
 
-  @param This       A pointer to the EFI_HII_IMAGE_PROTOCOL instance. 
- 
+  @param This       A pointer to the EFI_HII_IMAGE_PROTOCOL instance.
+
   @param Flags      Describes how the image is to be drawn.
                     EFI_HII_DRAW_FLAGS is defined in Related
                     Definitions, below.
-  
-  @param Image      Points to the image to be displayed. 
-  
+
+  @param Image      Points to the image to be displayed.
+
   @param Blt        If this points to a non-NULL on entry, this points
                     to the image, which is Width pixels wide and
                     Height pixels high. The image will be drawn onto
@@ -259,7 +256,7 @@ EFI_STATUS
 );
 
 /**
-   
+
   This function renders an image as a bitmap or to the screen and
   can clip the image. The bitmap is either supplied by the caller
   or else is allocated by the function. The images can be drawn
@@ -292,7 +289,7 @@ EFI_STATUS
   directly to the output device specified by Screen. Otherwise the
   image will be rendered to the bitmap specified by Bitmap.
 
-  @param This         A pointer to the EFI_HII_IMAGE_PROTOCOL instance. 
+  @param This         A pointer to the EFI_HII_IMAGE_PROTOCOL instance.
 
   @param Flags        Describes how the image is to be drawn.
 
@@ -315,14 +312,14 @@ EFI_STATUS
                       pixel in the image.
 
   @retval EFI_SUCCESS           The image was successfully updated.
-  
+
   @retval EFI_OUT_OF_RESOURCES  Unable to allocate an output
                                 buffer for RowInfoArray or Blt.
-  
-  @retval EFI_NOT_FOUND         The image specified by ImageId is not in the database. 
-                                Or The specified PackageList is not in the database.                            
-  
-  @retval EFI_INVALID_PARAMETER The Blt was NULL.    
+
+  @retval EFI_NOT_FOUND         The image specified by ImageId is not in the database.
+                                Or The specified PackageList is not in the database.
+
+  @retval EFI_INVALID_PARAMETER The Blt was NULL.
 
 **/
 typedef
diff --git a/MdePkg/Include/Protocol/HiiImageDecoder.h b/MdePkg/Include/Protocol/HiiImageDecoder.h
index 6ee16c922243..965c59a9e0e0 100644
--- a/MdePkg/Include/Protocol/HiiImageDecoder.h
+++ b/MdePkg/Include/Protocol/HiiImageDecoder.h
@@ -2,15 +2,12 @@
   This protocol provides generic image decoder interfaces to various image formats.
 
 (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2016-2018, Intel Corporation. All rights reserved.<BR>
 
-This program and the accompanying materials are licensed and made available under
-the terms and conditions of the BSD License that accompanies this distribution.
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  @par Revision Reference:
+  This Protocol was introduced in UEFI Specification 2.6.
 
 **/
 #ifndef __HII_IMAGE_DECODER_H__
@@ -18,15 +15,6 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
 #include <Protocol/HiiImage.h>
 
-
-//
-// In UEFI 2.6 spec,this guid value is duplicate with
-// EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GUID. Now update this guid value to
-// avoid the duplicate guid issue. So its value is not consistent with
-// UEFI spec definition now. We have proposed to update UEFI spec to
-// use this new guid. After new spec released, we will remove this
-// comments.
-//
 #define EFI_HII_IMAGE_DECODER_PROTOCOL_GUID \
   {0x9e66f251, 0x727c, 0x418c, { 0xbf, 0xd6, 0xc2, 0xb4, 0x25, 0x28, 0x18, 0xea }}
 
diff --git a/MdePkg/Include/Protocol/HiiImageEx.h b/MdePkg/Include/Protocol/HiiImageEx.h
index 5c4fd647e198..c0402b7bbb51 100644
--- a/MdePkg/Include/Protocol/HiiImageEx.h
+++ b/MdePkg/Include/Protocol/HiiImageEx.h
@@ -1,15 +1,12 @@
 /** @file
   Protocol which allows access to the images in the images database.
 
-(C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
+(C) Copyright 2016-2018 Hewlett Packard Enterprise Development LP<BR>
 
-This program and the accompanying materials are licensed and made available under
-the terms and conditions of the BSD License that accompanies this distribution.
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  @par Revision Reference:
+  This Protocol was introduced in UEFI Specification 2.6.
 
 **/
 
@@ -28,8 +25,7 @@ typedef struct _EFI_HII_IMAGE_EX_PROTOCOL EFI_HII_IMAGE_EX_PROTOCOL;
 
 /**
   The prototype of this extension function is the same with EFI_HII_IMAGE_PROTOCOL.NewImage().
-  Same with EFI_HII_IMAGE_PROTOCOL.NewImage().This protocol invokes
-EFI_HII_IMAGE_PROTOCOL.NewImage() implicitly.
+  This protocol invokes EFI_HII_IMAGE_PROTOCOL.NewImage() implicitly.
 
   @param  This                   A pointer to the EFI_HII_IMAGE_EX_PROTOCOL instance.
   @param  PackageList            Handle of the package list where this image will
@@ -57,22 +53,24 @@ EFI_STATUS
 /**
   Return the information about the image, associated with the package list.
   The prototype of this extension function is the same with EFI_HII_IMAGE_PROTOCOL.GetImage().
-  Same with EFI_HII_IMAGE_PROTOCOL.SetImage(),this protocol invokes EFI_HII_IMAGE_PROTOCOL.SetImage() implicitly.
+
+  This function is similar to EFI_HII_IMAGE_PROTOCOL.GetImage().The difference is that
+  this function will locate all EFI_HII_IMAGE_DECODER_PROTOCOL instances installed in the
+  system if the decoder of the certain image type is not supported by the
+  EFI_HII_IMAGE_EX_PROTOCOL. The function will attempt to decode the image to the
+  EFI_IMAGE_INPUT using the first EFI_HII_IMAGE_DECODER_PROTOCOL instance that
+  supports the requested image type.
 
   @param  This                   A pointer to the EFI_HII_IMAGE_EX_PROTOCOL instance.
-  @param  PackageList            Handle of the package list where this image will
-                                 be searched.
-  @param  ImageId                The image's id,, which is unique within
-                                 PackageList.
+  @param  PackageList            The package list in the HII database to search for the
+                                 specified image.
+  @param  ImageId                The image's id, which is unique within PackageList.
   @param  Image                  Points to the image.
 
   @retval EFI_SUCCESS            The new image was returned successfully.
-  @retval EFI_NOT_FOUND          The image specified by ImageId is not in the
-                                 database. The specified PackageList is not in
-                                 the database.
-  @retval EFI_BUFFER_TOO_SMALL   The buffer specified by ImageSize is too small to
-                                 hold the image.
-  @retval EFI_INVALID_PARAMETER  The Image or ImageSize was NULL.
+  @retval EFI_NOT_FOUND          The image specified by ImageId is not available. The specified
+                                 PackageList is not in the Database.
+  @retval EFI_INVALID_PARAMETER  Image was NULL or ImageId was 0.
   @retval EFI_OUT_OF_RESOURCES   The bitmap could not be retrieved because there
                                  was not enough memory.
 
@@ -87,21 +85,22 @@ EFI_STATUS
   );
 
 /**
-  Change the information about the image. The prototype of this extension
-  function is the same with EFI_HII_IMAGE_PROTOCOL.SetImage().  Same with
-  EFI_HII_IMAGE_PROTOCOL.DrawImageId(),this protocol invokes EFI_HII_IMAGE_PROTOCOL.DrawImageId() implicitly.
+  Change the information about the image.
+
+  Same with EFI_HII_IMAGE_PROTOCOL.SetImage(),this protocol invokes
+  EFI_HII_IMAGE_PROTOCOL.SetImage()implicitly.
 
   @param  This                   A pointer to the EFI_HII_IMAGE_EX_PROTOCOL instance.
   @param  PackageList            The package list containing the images.
-  @param  ImageId                The image's id,, which is unique within
-                                 PackageList.
+  @param  ImageId                The image's id, which is unique within PackageList.
   @param  Image                  Points to the image.
 
-  @retval EFI_SUCCESS            The new image was updated successfully.
+  @retval EFI_SUCCESS            The new image was successfully updated.
   @retval EFI_NOT_FOUND          The image specified by ImageId is not in the
                                  database. The specified PackageList is not in
                                  the database.
-  @retval EFI_INVALID_PARAMETER  The Image was NULL.
+  @retval EFI_INVALID_PARAMETER  The Image was NULL, the ImageId was 0 or
+                                 the Image->Bitmap was NULL.
 
 **/
 typedef
@@ -114,9 +113,11 @@ EFI_STATUS
   );
 
 /**
-  Renders an image to a bitmap or to the display. The prototype of this extension
-  function is the same with EFI_HII_IMAGE_PROTOCOL.DrawImage().
-  Same with EFI_HII_IMAGE_PROTOCOL.SetImage(),this protocol invokes EFI_HII_IMAGE_PROTOCOL.SetImage() implicitly.
+  Renders an image to a bitmap or to the display.
+
+  The prototype of this extension function is the same with
+  EFI_HII_IMAGE_PROTOCOL.DrawImage(). This protocol invokes
+  EFI_HII_IMAGE_PROTOCOL.DrawImage() implicitly.
 
   @param  This                   A pointer to the EFI_HII_IMAGE_EX_PROTOCOL instance.
   @param  Flags                  Describes how the image is to be drawn.
@@ -125,19 +126,18 @@ EFI_STATUS
                                  to the image, which is Width pixels wide and
                                  Height pixels high.  The image will be drawn onto
                                  this image and  EFI_HII_DRAW_FLAG_CLIP is implied.
-                                 If this points to a  NULL on entry, then a buffer
-                                 will be allocated to hold  the generated image and
+                                 If this points to a NULL on entry, then a buffer
+                                 will be allocated to hold the generated image and
                                  the pointer updated on exit. It is the caller's
                                  responsibility to free this buffer.
   @param  BltX                   Specifies the offset from the left and top edge of
-                                 the  output image of the first pixel in the image.
+                                 the output image of the first pixel in the image.
   @param  BltY                   Specifies the offset from the left and top edge of
-                                 the  output image of the first pixel in the image.
+                                 the output image of the first pixel in the image.
 
   @retval EFI_SUCCESS            The image was successfully drawn.
   @retval EFI_OUT_OF_RESOURCES   Unable to allocate an output buffer for Blt.
   @retval EFI_INVALID_PARAMETER  The Image or Blt was NULL.
-                                 Any combination of Flags is invalid.
 
 **/
 typedef
@@ -153,17 +153,20 @@ EFI_STATUS
 
 /**
   Renders an image to a bitmap or the screen containing the contents of the specified
-  image. The prototype of this extension function is the same with E
-  FI_HII_IMAGE_PROTOCOL.DrawImageId().
-  Same with EFI_HII_IMAGE_PROTOCOL.DrawImageId(),this protocol invokes
-EFI_HII_IMAGE_PROTOCOL.DrawImageId() implicitly.
+  image.
+
+  This function is similar to EFI_HII_IMAGE_PROTOCOL.DrawImageId(). The difference is that
+  this function will locate all EFI_HII_IMAGE_DECODER_PROTOCOL instances installed in the
+  system if the decoder of the certain image type is not supported by the
+  EFI_HII_IMAGE_EX_PROTOCOL. The function will attempt to decode the image to the
+  EFI_IMAGE_INPUT using the first EFI_HII_IMAGE_DECODER_PROTOCOL instance that
+  supports the requested image type.
 
   @param  This                   A pointer to the EFI_HII_IMAGE_EX_PROTOCOL instance.
   @param  Flags                  Describes how the image is to be drawn.
   @param  PackageList            The package list in the HII database to search for
                                  the  specified image.
-  @param  ImageId                The image's id, which is unique within
-                                 PackageList.
+  @param  ImageId                The image's id, which is unique within PackageList.
   @param  Blt                    If this points to a non-NULL on entry, this points
                                  to the image, which is Width pixels wide and
                                  Height pixels high. The image will be drawn onto
@@ -179,7 +182,7 @@ EFI_HII_IMAGE_PROTOCOL.DrawImageId() implicitly.
 
   @retval EFI_SUCCESS            The image was successfully drawn.
   @retval EFI_OUT_OF_RESOURCES   Unable to allocate an output buffer for Blt.
-  @retval EFI_INVALID_PARAMETER  The Blt was NULL.
+  @retval EFI_INVALID_PARAMETER  The Blt was NULL or ImageId was 0.
   @retval EFI_NOT_FOUND          The image specified by ImageId is not in the database.
                                  The specified PackageList is not in the database.
 
@@ -206,7 +209,7 @@ EFI_STATUS
   @param  This                   A pointer to the EFI_HII_IMAGE_EX_PROTOCOL instance.
   @param  PackageList            Handle of the package list where this image will
                                  be searched.
-  @param  ImageId                The image's id,, which is unique within PackageList.
+  @param  ImageId                The image's id, which is unique within PackageList.
   @param  Image                  Points to the image.
 
   @retval EFI_SUCCESS            The new image was returned successfully.
@@ -214,7 +217,7 @@ EFI_STATUS
                                  database. The specified PackageList is not in the database.
   @retval EFI_BUFFER_TOO_SMALL   The buffer specified by ImageSize is too small to
                                  hold the image.
-  @retval EFI_INVALID_PARAMETER  The Image or ImageSize was NULL.
+  @retval EFI_INVALID_PARAMETER  The Image was NULL or the ImageId was 0.
   @retval EFI_OUT_OF_RESOURCES   The bitmap could not be retrieved because there
                                  was not enough memory.
 
diff --git a/MdePkg/Include/Protocol/HiiPackageList.h b/MdePkg/Include/Protocol/HiiPackageList.h
index 3842973281ec..a161edfa592a 100644
--- a/MdePkg/Include/Protocol/HiiPackageList.h
+++ b/MdePkg/Include/Protocol/HiiPackageList.h
@@ -4,15 +4,9 @@
   if the image contains a custom PE/COFF resource with the type 'HII'.
   The protocol's interface pointer points to the HII package list, which is
   contained in the resource's data.
-  
-  Copyright (c) 2009, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/Protocol/HiiPopup.h b/MdePkg/Include/Protocol/HiiPopup.h
new file mode 100644
index 000000000000..8924a3a5704c
--- /dev/null
+++ b/MdePkg/Include/Protocol/HiiPopup.h
@@ -0,0 +1,78 @@
+/** @file
+  This protocol provides services to display a popup window.
+  The protocol is typically produced by the forms browser and consumed by a driver callback handler.
+
+  Copyright (c) 2017-2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  This Protocol was introduced in UEFI Specification 2.7.
+
+**/
+
+#ifndef __HII_POPUP_H__
+#define __HII_POPUP_H__
+
+#define EFI_HII_POPUP_PROTOCOL_GUID \
+  {0x4311edc0, 0x6054, 0x46d4, {0x9e, 0x40, 0x89, 0x3e, 0xa9, 0x52, 0xfc, 0xcc}}
+
+#define EFI_HII_POPUP_PROTOCOL_REVISION 1
+
+typedef struct _EFI_HII_POPUP_PROTOCOL EFI_HII_POPUP_PROTOCOL;
+
+typedef enum {
+  EfiHiiPopupStyleInfo,
+  EfiHiiPopupStyleWarning,
+  EfiHiiPopupStyleError
+} EFI_HII_POPUP_STYLE;
+
+typedef enum {
+  EfiHiiPopupTypeOk,
+  EfiHiiPopupTypeOkCancel,
+  EfiHiiPopupTypeYesNo,
+  EfiHiiPopupTypeYesNoCancel
+} EFI_HII_POPUP_TYPE;
+
+typedef enum {
+  EfiHiiPopupSelectionOk,
+  EfiHiiPopupSelectionCancel,
+  EfiHiiPopupSelectionYes,
+  EfiHiiPopupSelectionNo
+} EFI_HII_POPUP_SELECTION;
+
+/**
+  Displays a popup window.
+
+  @param  This           A pointer to the EFI_HII_POPUP_PROTOCOL instance.
+  @param  PopupStyle     Popup style to use.
+  @param  PopupType      Type of the popup to display.
+  @param  HiiHandle      HII handle of the string pack containing Message
+  @param  Message        A message to display in the popup box.
+  @param  UserSelection  User selection.
+
+  @retval EFI_SUCCESS            The popup box was successfully displayed.
+  @retval EFI_INVALID_PARAMETER  HiiHandle and Message do not define a valid HII string.
+  @retval EFI_INVALID_PARAMETER  PopupType is not one of the values defined by this specification.
+  @retval EFI_OUT_OF_RESOURCES   There are not enough resources available to display the popup box.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI * EFI_HII_CREATE_POPUP) (
+  IN  EFI_HII_POPUP_PROTOCOL  *This,
+  IN  EFI_HII_POPUP_STYLE     PopupStyle,
+  IN  EFI_HII_POPUP_TYPE      PopupType,
+  IN  EFI_HII_HANDLE          HiiHandle,
+  IN  EFI_STRING_ID           Message,
+  OUT EFI_HII_POPUP_SELECTION *UserSelection OPTIONAL
+);
+
+typedef struct _EFI_HII_POPUP_PROTOCOL {
+  UINT64                Revision;
+  EFI_HII_CREATE_POPUP  CreatePopup;
+} EFI_HII_POPUP_PROTOCOL;
+
+extern EFI_GUID gEfiHiiPopupProtocolGuid;
+
+#endif
+
diff --git a/MdePkg/Include/Protocol/HiiString.h b/MdePkg/Include/Protocol/HiiString.h
index 9e9f7ff50753..989d181f5aa8 100644
--- a/MdePkg/Include/Protocol/HiiString.h
+++ b/MdePkg/Include/Protocol/HiiString.h
@@ -1,14 +1,11 @@
 /** @file
   The file provides services to manipulate string data.
-  
-Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  This Protocol was introduced in UEFI Specification 2.1.
 
 **/
 
@@ -25,8 +22,8 @@ typedef struct _EFI_HII_STRING_PROTOCOL EFI_HII_STRING_PROTOCOL;
 /**
   This function adds the string String to the group of strings owned by PackageList, with the
   specified font information StringFontInfo, and returns a new string id.
-  The new string identifier is guaranteed to be unique within the package list. 
-  That new string identifier is reserved for all languages in the package list. 
+  The new string identifier is guaranteed to be unique within the package list.
+  That new string identifier is reserved for all languages in the package list.
 
   @param  This                   A pointer to the EFI_HII_STRING_PROTOCOL instance.
   @param  PackageList            The handle of the package list where this string will
@@ -61,7 +58,7 @@ EFI_STATUS
   IN        EFI_HII_HANDLE            PackageList,
   OUT       EFI_STRING_ID             *StringId,
   IN CONST  CHAR8                     *Language,
-  IN  CONST CHAR16                    *LanguageName, OPTIONAL  
+  IN  CONST CHAR16                    *LanguageName, OPTIONAL
   IN CONST  EFI_STRING                String,
   IN CONST  EFI_FONT_INFO             *StringFontInfo OPTIONAL
 );
@@ -89,7 +86,7 @@ EFI_STATUS
   @retval EFI_SUCCESS            The string was returned successfully.
   @retval EFI_NOT_FOUND          The string specified by StringId is not available.
                                  The specified PackageList is not in the database.
-  @retval EFI_INVALID_LANGUAGE    The string specified by StringId is available but 
+  @retval EFI_INVALID_LANGUAGE    The string specified by StringId is available but
                                   not in the specified language.
   @retval EFI_BUFFER_TOO_SMALL   The buffer specified by StringSize is too small to
                                  hold the string.
diff --git a/MdePkg/Include/Protocol/Http.h b/MdePkg/Include/Protocol/Http.h
index bdfe76db80d4..30a691bd2def 100644
--- a/MdePkg/Include/Protocol/Http.h
+++ b/MdePkg/Include/Protocol/Http.h
@@ -4,15 +4,9 @@
   HTTP Service Binding Protocol (HTTPSB)
   HTTP Protocol (HTTP)
 
-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
-  (C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution. The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
+  (C) Copyright 2015-2017 Hewlett Packard Enterprise Development LP<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This Protocol is introduced in UEFI Specification 2.5
@@ -73,7 +67,7 @@ typedef enum {
   HTTP_STATUS_204_NO_CONTENT,
   HTTP_STATUS_205_RESET_CONTENT,
   HTTP_STATUS_206_PARTIAL_CONTENT,
-  HTTP_STATUS_300_MULTIPLE_CHIOCES,
+  HTTP_STATUS_300_MULTIPLE_CHOICES,
   HTTP_STATUS_301_MOVED_PERMANENTLY,
   HTTP_STATUS_302_FOUND,
   HTTP_STATUS_303_SEE_OTHER,
@@ -103,7 +97,8 @@ typedef enum {
   HTTP_STATUS_502_BAD_GATEWAY,
   HTTP_STATUS_503_SERVICE_UNAVAILABLE,
   HTTP_STATUS_504_GATEWAY_TIME_OUT,
-  HTTP_STATUS_505_HTTP_VERSION_NOT_SUPPORTED
+  HTTP_STATUS_505_HTTP_VERSION_NOT_SUPPORTED,
+  HTTP_STATUS_308_PERMANENT_REDIRECT
 } EFI_HTTP_STATUS_CODE;
 
 ///
@@ -304,20 +299,22 @@ typedef struct {
 
   @param[in]  This                Pointer to EFI_HTTP_PROTOCOL instance.
   @param[out] HttpConfigData      Point to buffer for operational parameters of this
-                                  HTTP instance.
+                                  HTTP instance. It is the responsibility of the caller
+                                  to allocate the memory for HttpConfigData and
+                                  HttpConfigData->AccessPoint.IPv6Node/IPv4Node. In fact,
+                                  it is recommended to allocate sufficient memory to record
+                                  IPv6Node since it is big enough for all possibilities.
 
   @retval EFI_SUCCESS             Operation succeeded.
   @retval EFI_INVALID_PARAMETER   This is NULL.
                                   HttpConfigData is NULL.
-                                  HttpInstance->LocalAddressIsIPv6 is FALSE and
-                                  HttpConfigData->IPv4Node is NULL.
-                                  HttpInstance->LocalAddressIsIPv6 is TRUE and
-                                  HttpConfigData->IPv6Node is NULL.
+                                  HttpConfigData->AccessPoint.IPv4Node or
+                                  HttpConfigData->AccessPoint.IPv6Node is NULL.
   @retval EFI_NOT_STARTED         This EFI HTTP Protocol instance has not been started.
 **/
 typedef
 EFI_STATUS
-(EFIAPI * EFI_HTTP_GET_MODE_DATA)(
+(EFIAPI *EFI_HTTP_GET_MODE_DATA)(
   IN  EFI_HTTP_PROTOCOL         *This,
   OUT EFI_HTTP_CONFIG_DATA      *HttpConfigData
   );
@@ -342,9 +339,9 @@ EFI_STATUS
   @retval EFI_INVALID_PARAMETER   One or more of the following conditions is TRUE:
                                   This is NULL.
                                   HttpConfigData->LocalAddressIsIPv6 is FALSE and
-                                  HttpConfigData->IPv4Node is NULL.
+                                  HttpConfigData->AccessPoint.IPv4Node is NULL.
                                   HttpConfigData->LocalAddressIsIPv6 is TRUE and
-                                  HttpConfigData->IPv6Node is NULL.
+                                  HttpConfigData->AccessPoint.IPv6Node is NULL.
   @retval EFI_ALREADY_STARTED     Reinitialize this HTTP instance without calling
                                   Configure() with NULL to reset it.
   @retval EFI_DEVICE_ERROR        An unexpected system or network error occurred.
@@ -355,13 +352,13 @@ EFI_STATUS
 **/
 typedef
 EFI_STATUS
-(EFIAPI * EFI_HTTP_CONFIGURE)(
+(EFIAPI *EFI_HTTP_CONFIGURE)(
   IN  EFI_HTTP_PROTOCOL         *This,
-  IN  EFI_HTTP_CONFIG_DATA      *HttpConfigData
+  IN  EFI_HTTP_CONFIG_DATA      *HttpConfigData OPTIONAL
   );
 
 /**
-  The Request() function queues an HTTP request to this HTTP instance, 
+  The Request() function queues an HTTP request to this HTTP instance,
   similar to Transmit() function in the EFI TCP driver. When the HTTP request is sent
   successfully, or if there is an error, Status in token will be updated and Event will
   be signaled.
diff --git a/MdePkg/Include/Protocol/HttpBootCallback.h b/MdePkg/Include/Protocol/HttpBootCallback.h
new file mode 100644
index 000000000000..2381c9dbc791
--- /dev/null
+++ b/MdePkg/Include/Protocol/HttpBootCallback.h
@@ -0,0 +1,94 @@
+/** @file
+  This file defines the EFI HTTP Boot Callback Protocol interface.
+
+  Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  This Protocol is introduced in UEFI Specification 2.7
+
+**/
+
+#ifndef __EFI_HTTP_BOOT_CALLBACK_H__
+#define __EFI_HTTP_BOOT_CALLBACK_H__
+
+#define EFI_HTTP_BOOT_CALLBACK_PROTOCOL_GUID \
+  { \
+    0xba23b311, 0x343d, 0x11e6, {0x91, 0x85, 0x58, 0x20, 0xb1, 0xd6, 0x52, 0x99} \
+  }
+
+typedef struct _EFI_HTTP_BOOT_CALLBACK_PROTOCOL  EFI_HTTP_BOOT_CALLBACK_PROTOCOL;
+
+///
+/// EFI_HTTP_BOOT_CALLBACK_DATA_TYPE
+///
+typedef enum {
+  ///
+  /// Data points to a DHCP4 packet which is about to transmit or has received.
+  ///
+  HttpBootDhcp4,
+  ///
+  /// Data points to a DHCP6 packet which is about to be transmit or has received.
+  ///
+  HttpBootDhcp6,
+  ///
+  /// Data points to an EFI_HTTP_MESSAGE structure, whichcontians a HTTP request message
+  /// to be transmitted.
+  ///
+  HttpBootHttpRequest,
+  ///
+  /// Data points to an EFI_HTTP_MESSAGE structure, which contians a received HTTP
+  /// response message.
+  ///
+  HttpBootHttpResponse,
+  ///
+  /// Part of the entity body has been received from the HTTP server. Data points to the
+  /// buffer of the entity body data.
+  ///
+  HttpBootHttpEntityBody,
+  HttpBootTypeMax
+} EFI_HTTP_BOOT_CALLBACK_DATA_TYPE;
+
+/**
+  Callback function that is invoked when the HTTP Boot driver is about to transmit or has received a
+  packet.
+
+  This function is invoked when the HTTP Boot driver is about to transmit or has received packet.
+  Parameters DataType and Received specify the type of event and the format of the buffer pointed
+  to by Data. Due to the polling nature of UEFI device drivers, this callback function should not
+  execute for more than 5 ms.
+  The returned status code determines the behavior of the HTTP Boot driver.
+
+  @param[in]  This                Pointer to the EFI_HTTP_BOOT_CALLBACK_PROTOCOL instance.
+  @param[in]  DataType            The event that occurs in the current state.
+  @param[in]  Received            TRUE if the callback is being invoked due to a receive event.
+                                  FALSE if the callback is being invoked due to a transmit event.
+  @param[in]  DataLength          The length in bytes of the buffer pointed to by Data.
+  @param[in]  Data                A pointer to the buffer of data, the data type is specified by
+                                  DataType.
+
+  @retval EFI_SUCCESS             Tells the HTTP Boot driver to continue the HTTP Boot process.
+  @retval EFI_ABORTED             Tells the HTTP Boot driver to abort the current HTTP Boot process.
+**/
+typedef
+EFI_STATUS
+(EFIAPI * EFI_HTTP_BOOT_CALLBACK) (
+  IN EFI_HTTP_BOOT_CALLBACK_PROTOCOL    *This,
+  IN EFI_HTTP_BOOT_CALLBACK_DATA_TYPE   DataType,
+  IN BOOLEAN                            Received,
+  IN UINT32                             DataLength,
+  IN VOID                               *Data   OPTIONAL
+ );
+
+///
+/// EFI HTTP Boot Callback Protocol is invoked when the HTTP Boot driver is about to transmit or
+/// has received a packet. The EFI HTTP Boot Callback Protocol must be installed on the same handle
+/// as the Load File Protocol for the HTTP Boot.
+///
+struct _EFI_HTTP_BOOT_CALLBACK_PROTOCOL {
+  EFI_HTTP_BOOT_CALLBACK Callback;
+};
+
+extern EFI_GUID gEfiHttpBootCallbackProtocolGuid;
+
+#endif
diff --git a/MdePkg/Include/Protocol/HttpUtilities.h b/MdePkg/Include/Protocol/HttpUtilities.h
index 59c1ea2f7853..b54666295b66 100644
--- a/MdePkg/Include/Protocol/HttpUtilities.h
+++ b/MdePkg/Include/Protocol/HttpUtilities.h
@@ -3,13 +3,7 @@
   message comprehension.
 
   Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution. The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This Protocol is introduced in UEFI Specification 2.5
diff --git a/MdePkg/Include/Protocol/I2cBusConfigurationManagement.h b/MdePkg/Include/Protocol/I2cBusConfigurationManagement.h
index b29333e0009e..848e141567a3 100644
--- a/MdePkg/Include/Protocol/I2cBusConfigurationManagement.h
+++ b/MdePkg/Include/Protocol/I2cBusConfigurationManagement.h
@@ -1,19 +1,13 @@
 /** @file
   I2C Bus Configuration Management Protocol as defined in the PI 1.3 specification.
 
-  The EFI I2C bus configuration management protocol provides platform specific 
-  services that allow the I2C host protocol to reconfigure the switches and multiplexers 
-  and set the clock frequency for the I2C bus. This protocol also enables the I2C host protocol 
+  The EFI I2C bus configuration management protocol provides platform specific
+  services that allow the I2C host protocol to reconfigure the switches and multiplexers
+  and set the clock frequency for the I2C bus. This protocol also enables the I2C host protocol
   to reset an I2C device which may be locking up the I2C bus by holding the clock or data line low.
 
-  Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This protocol is from PI Version 1.3.
diff --git a/MdePkg/Include/Protocol/I2cEnumerate.h b/MdePkg/Include/Protocol/I2cEnumerate.h
index 00f80d0b68e4..d7bcb15ea8a7 100644
--- a/MdePkg/Include/Protocol/I2cEnumerate.h
+++ b/MdePkg/Include/Protocol/I2cEnumerate.h
@@ -3,14 +3,8 @@
 
   This protocol supports the enumerations of device on the I2C bus.
 
-  Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This protocol is from PI Version 1.3.
diff --git a/MdePkg/Include/Protocol/I2cHost.h b/MdePkg/Include/Protocol/I2cHost.h
index fcd82de6b96e..27373a0784a3 100644
--- a/MdePkg/Include/Protocol/I2cHost.h
+++ b/MdePkg/Include/Protocol/I2cHost.h
@@ -1,17 +1,11 @@
 /** @file
   I2C Host Protocol as defined in the PI 1.3 specification.
 
-  This protocol provides callers with the ability to do I/O transactions 
+  This protocol provides callers with the ability to do I/O transactions
   to all of the devices on the I2C bus.
 
-  Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This protocol is from PI Version 1.3.
@@ -50,7 +44,7 @@ typedef struct _EFI_I2C_HOST_PROTOCOL EFI_I2C_HOST_PROTOCOL;
   This routine must be called at or below TPL_NOTIFY.  For
   synchronous requests this routine must be called at or below
   TPL_CALLBACK.
-  
+
   The I2C host protocol uses the concept of I2C bus configurations
   to describe the I2C bus.  An I2C bus configuration is defined as
   a unique setting of the multiplexers and switches in the I2C bus
diff --git a/MdePkg/Include/Protocol/I2cIo.h b/MdePkg/Include/Protocol/I2cIo.h
index 4e4267d83855..282308ecd4bb 100644
--- a/MdePkg/Include/Protocol/I2cIo.h
+++ b/MdePkg/Include/Protocol/I2cIo.h
@@ -1,17 +1,11 @@
 /** @file
   I2C I/O Protocol as defined in the PI 1.3 specification.
 
-  The EFI I2C I/O protocol enables the user to manipulate a single 
+  The EFI I2C I/O protocol enables the user to manipulate a single
   I2C device independent of the host controller and I2C design.
 
-  Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This protocol is from PI Version 1.3.
@@ -66,7 +60,7 @@ typedef struct _EFI_I2C_IO_PROTOCOL  EFI_I2C_IO_PROTOCOL;
 
   The upper layer driver writer provides the following to the platform
   vendor:
-  
+
   1.  Vendor specific GUID for the I2C part
   2.  Guidance on proper construction of the slave address array when the
       I2C device uses more than one slave address.  The I2C bus protocol
diff --git a/MdePkg/Include/Protocol/I2cMaster.h b/MdePkg/Include/Protocol/I2cMaster.h
index 26f689788c36..e3053ffa75f9 100644
--- a/MdePkg/Include/Protocol/I2cMaster.h
+++ b/MdePkg/Include/Protocol/I2cMaster.h
@@ -1,17 +1,11 @@
 /** @file
   I2C Master Protocol as defined in the PI 1.3 specification.
 
-  This protocol manipulates the I2C host controller to perform transactions as a master 
+  This protocol manipulates the I2C host controller to perform transactions as a master
   on the I2C bus using the current state of any switches or multiplexers in the I2C bus.
 
-  Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This protocol is from PI Version 1.3.
@@ -72,7 +66,7 @@ EFI_STATUS
   @retval EFI_SUCCESS         The reset completed successfully.
   @retval EFI_ALREADY_STARTED The controller is busy with another transaction.
   @retval EFI_DEVICE_ERROR    The reset operation failed.
-  
+
 **/
 typedef
 EFI_STATUS
diff --git a/MdePkg/Include/Protocol/IScsiInitiatorName.h b/MdePkg/Include/Protocol/IScsiInitiatorName.h
index 5dffaeedf96c..d8f9e885a202 100644
--- a/MdePkg/Include/Protocol/IScsiInitiatorName.h
+++ b/MdePkg/Include/Protocol/IScsiInitiatorName.h
@@ -1,15 +1,9 @@
 /** @file
   EFI_ISCSI_INITIATOR_NAME_PROTOCOL as defined in UEFI 2.0.
-  It provides the ability to get and set the iSCSI Initiator Name.                                                  
+  It provides the ability to get and set the iSCSI Initiator Name.
 
-  Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -39,7 +33,7 @@ typedef struct _EFI_ISCSI_INITIATOR_NAME_PROTOCOL EFI_ISCSI_INITIATOR_NAME_PROTO
   @retval EFI_DEVICE_ERROR      The iSCSI initiator name could not be retrieved due to a hardware error.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_ISCSI_INITIATOR_NAME_GET)(
   IN EFI_ISCSI_INITIATOR_NAME_PROTOCOL *This,
@@ -47,7 +41,7 @@ EFI_STATUS
   OUT VOID                             *Buffer
   );
 
-  
+
 
 /**
   Sets the iSCSI Initiator Name.
@@ -71,10 +65,10 @@ typedef EFI_STATUS
   IN EFI_ISCSI_INITIATOR_NAME_PROTOCOL *This,
   IN OUT UINTN                         *BufferSize,
   IN VOID                              *Buffer
-  );  
+  );
 
 ///
-/// iSCSI Initiator Name Protocol for setting and obtaining the iSCSI Initiator Name. 
+/// iSCSI Initiator Name Protocol for setting and obtaining the iSCSI Initiator Name.
 ///
 struct _EFI_ISCSI_INITIATOR_NAME_PROTOCOL {
   EFI_ISCSI_INITIATOR_NAME_GET         Get;
diff --git a/MdePkg/Include/Protocol/IdeControllerInit.h b/MdePkg/Include/Protocol/IdeControllerInit.h
index c099af308435..9b5b7894500e 100644
--- a/MdePkg/Include/Protocol/IdeControllerInit.h
+++ b/MdePkg/Include/Protocol/IdeControllerInit.h
@@ -1,31 +1,25 @@
 /** @file
   This file declares EFI IDE Controller Init Protocol
-  
+
   The EFI_IDE_CONTROLLER_INIT_PROTOCOL provides the chipset-specific information
   to the driver entity. This protocol is mandatory for IDE controllers if the
   IDE devices behind the controller are to be enumerated by a driver entity.
-  
+
   There can only be one instance of EFI_IDE_CONTROLLER_INIT_PROTOCOL for each IDE
   controller in a system. It is installed on the handle that corresponds to the
   IDE controller. A driver entity that wishes to manage an IDE bus and possibly
   IDE devices in a system will have to retrieve the EFI_IDE_CONTROLLER_INIT_PROTOCOL
   instance that is associated with the controller to be managed.
-  
+
   A device handle for an IDE controller must contain an EFI_DEVICE_PATH_PROTOCOL.
 
-Copyright (c) 2007 - 2011, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
-  This Protocol is defined in UEFI Platform Initialization Specification 1.2 
+  This Protocol is defined in UEFI Platform Initialization Specification 1.2
   Volume 5: Standards.
-  
+
 **/
 
 #ifndef _EFI_IDE_CONTROLLER_INIT_PROTOCOL_H_
@@ -71,7 +65,7 @@ typedef enum {
   ///
   /// The driver entity has completed resetting the devices behind
   /// the specified channel. This notification can be used to perform
-  /// any chipset-specific programming.  
+  /// any chipset-specific programming.
   ///
   EfiIdeAfterChannelReset,
   ///
@@ -84,13 +78,13 @@ typedef enum {
   ///
   /// The driver entity is done with detecting the presence of
   /// devices behind the specified channel. This notification can be
-  /// used to perform any chipset-specific programming.  
+  /// used to perform any chipset-specific programming.
   ///
   EfiIdeBusAfterDevicePresenceDetection,
   ///
   /// The IDE bus is requesting the IDE controller driver to
   /// reprogram the IDE controller hardware and thereby reset all
-  /// the mode and timing settings to default settings.  
+  /// the mode and timing settings to default settings.
   ///
   EfiIdeResetMode,
   EfiIdeBusPhaseMaximum
@@ -135,11 +129,11 @@ typedef struct {
 typedef struct {
   ///
   /// An enumeration defining various transfer protocols other than the protocols
-  /// that exist at the time this specification was developed (i.e., PIO, single 
-  /// word DMA, multiword DMA, and UDMA). Each transfer protocol is associated 
-  /// with a mode. The various transfer protocols are defined by the ATA/ATAPI 
-  /// specification. This enumeration makes the interface extensible because we 
-  /// can support new transport protocols beyond UDMA. Type EFI_ATA_EXT_TRANSFER_PROTOCOL 
+  /// that exist at the time this specification was developed (i.e., PIO, single
+  /// word DMA, multiword DMA, and UDMA). Each transfer protocol is associated
+  /// with a mode. The various transfer protocols are defined by the ATA/ATAPI
+  /// specification. This enumeration makes the interface extensible because we
+  /// can support new transport protocols beyond UDMA. Type EFI_ATA_EXT_TRANSFER_PROTOCOL
   /// is defined below.
   ///
   EFI_ATA_EXT_TRANSFER_PROTOCOL  TransferProtocol;
@@ -155,7 +149,7 @@ typedef struct {
 typedef struct {
   ///
   /// This field specifies the PIO mode. PIO modes are defined in the ATA/ATAPI
-  /// specification. The ATA/ATAPI specification defines the enumeration.  In 
+  /// specification. The ATA/ATAPI specification defines the enumeration.  In
   /// other words, a value of 1 in this field means PIO mode 1. The actual meaning
   /// of PIO mode 1 is governed by the ATA/ATAPI specification. Type EFI_ATA_MODE
   /// is defined below.
@@ -168,26 +162,26 @@ typedef struct {
   /// controllers will not support this transfer mode. The ATA/ATAPI specification defines
   /// the enumeration. In other words, a value of 1 in this field means single word DMA
   /// mode 1. The actual meaning of single word DMA mode 1 is governed by the ATA/
-  /// ATAPI specification.  
+  /// ATAPI specification.
   ///
   EFI_ATA_MODE           SingleWordDmaMode;
   ///
   /// This field specifies the multiword DMA mode. Various multiword DMA modes are
   /// defined in the ATA/ATAPI specification. A value of 1 in this field means multiword
   /// DMA mode 1. The actual meaning of multiword DMA mode 1 is governed by the
-  /// ATA/ATAPI specification.  
+  /// ATA/ATAPI specification.
   ///
   EFI_ATA_MODE           MultiWordDmaMode;
   ///
   /// This field specifies the ultra DMA (UDMA) mode. UDMA modes are defined in the
   /// ATA/ATAPI specification. A value of 1 in this field means UDMA mode 1. The
-  /// actual meaning of UDMA mode 1 is governed by the ATA/ATAPI specification.  
+  /// actual meaning of UDMA mode 1 is governed by the ATA/ATAPI specification.
   ///
   EFI_ATA_MODE           UdmaMode;
   ///
   /// The number of extended-mode bitmap entries. Extended modes describe transfer
   /// protocols beyond PIO, single word DMA, multiword DMA, and UDMA. This field
-  /// can be zero and provides extensibility.  
+  /// can be zero and provides extensibility.
   ///
   UINT32                 ExtModeCount;
   ///
@@ -195,7 +189,7 @@ typedef struct {
   /// than the ones defined above (i.e., PIO, single word DMA, multiword DMA, and
   /// UDMA). This field is defined for extensibility. At this time, only one extended
   /// transfer protocol is defined to cover SATA transfers. Type
-  /// EFI_ATA_EXTENDED_MODE is defined below.  
+  /// EFI_ATA_EXTENDED_MODE is defined below.
   ///
   EFI_ATA_EXTENDED_MODE  ExtMode[1];
 } EFI_ATA_COLLECTIVE_MODE;
@@ -206,16 +200,16 @@ typedef struct {
 /// The definition of these two structures is not part of the protocol
 /// definition because the ATA/ATAPI Specification controls the definition
 /// of all the fields. The ATA/ATAPI Specification can obsolete old fields
-/// or redefine existing fields. 
+/// or redefine existing fields.
 typedef ATA_IDENTIFY_DATA   EFI_ATA_IDENTIFY_DATA;
 typedef ATAPI_IDENTIFY_DATA EFI_ATAPI_IDENTIFY_DATA;
 
 ///
 /// This flag indicates whether the IDENTIFY data is a response from an ATA device
-/// (EFI_ATA_IDENTIFY_DATA) or response from an ATAPI device 
+/// (EFI_ATA_IDENTIFY_DATA) or response from an ATAPI device
 /// (EFI_ATAPI_IDENTIFY_DATA).  According to the ATA/ATAPI specification,
-/// EFI_IDENTIFY_DATA is for an ATA device if bit 15 of the Config field is zero. 
-/// The Config field is common to both EFI_ATA_IDENTIFY_DATA and 
+/// EFI_IDENTIFY_DATA is for an ATA device if bit 15 of the Config field is zero.
+/// The Config field is common to both EFI_ATA_IDENTIFY_DATA and
 /// EFI_ATAPI_IDENTIFY_DATA.
 ///
 #define   EFI_ATAPI_DEVICE_IDENTIFY_DATA  0x8000
@@ -225,8 +219,8 @@ typedef ATAPI_IDENTIFY_DATA EFI_ATAPI_IDENTIFY_DATA;
 ///
 typedef union {
   ///
-  /// The data that is returned by an ATA device upon successful completion 
-  /// of the ATA IDENTIFY_DEVICE command. 
+  /// The data that is returned by an ATA device upon successful completion
+  /// of the ATA IDENTIFY_DEVICE command.
   ///
   EFI_ATA_IDENTIFY_DATA       AtaData;
   ///
@@ -238,34 +232,34 @@ typedef union {
 
 /**
   Returns the information about the specified IDE channel.
-  
+
   This function can be used to obtain information about a particular IDE channel.
-  The driver entity uses this information during the enumeration process. 
-  
-  If Enabled is set to FALSE, the driver entity will not scan the channel. Note 
+  The driver entity uses this information during the enumeration process.
+
+  If Enabled is set to FALSE, the driver entity will not scan the channel. Note
   that it will not prevent an operating system driver from scanning the channel.
-  
-  For most of today's controllers, MaxDevices will either be 1 or 2. For SATA 
-  controllers, this value will always be 1. SATA configurations can contain SATA 
+
+  For most of today's controllers, MaxDevices will either be 1 or 2. For SATA
+  controllers, this value will always be 1. SATA configurations can contain SATA
   port multipliers. SATA port multipliers behave like SATA bridges and can support
-  up to 16 devices on the other side. If a SATA port out of the IDE controller 
-  is connected to a port multiplier, MaxDevices will be set to the number of SATA 
-  devices that the port multiplier supports. Because today's port multipliers 
-  support up to fifteen SATA devices, this number can be as large as fifteen. The IDE  
-  bus driver is required to scan for the presence of port multipliers behind an SATA 
-  controller and enumerate up to MaxDevices number of devices behind the port 
-  multiplier.    
-  
-  In this context, the devices behind a port multiplier constitute a channel.  
-  
+  up to 16 devices on the other side. If a SATA port out of the IDE controller
+  is connected to a port multiplier, MaxDevices will be set to the number of SATA
+  devices that the port multiplier supports. Because today's port multipliers
+  support up to fifteen SATA devices, this number can be as large as fifteen. The IDE
+  bus driver is required to scan for the presence of port multipliers behind an SATA
+  controller and enumerate up to MaxDevices number of devices behind the port
+  multiplier.
+
+  In this context, the devices behind a port multiplier constitute a channel.
+
   @param[in]  This         The pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance.
   @param[in]  Channel      Zero-based channel number.
-  @param[out] Enabled      TRUE if this channel is enabled.  Disabled channels 
+  @param[out] Enabled      TRUE if this channel is enabled.  Disabled channels
                            are not scanned to see if any devices are present.
   @param[out] MaxDevices   The maximum number of IDE devices that the bus driver
-                           can expect on this channel.  For the ATA/ATAPI 
-                           specification, version 6, this number will either be 
-                           one or two. For Serial ATA (SATA) configurations with a 
+                           can expect on this channel.  For the ATA/ATAPI
+                           specification, version 6, this number will either be
+                           one or two. For Serial ATA (SATA) configurations with a
                            port multiplier, this number can be as large as fifteen.
 
   @retval EFI_SUCCESS             Information was returned without any errors.
@@ -284,13 +278,13 @@ EFI_STATUS
 /**
   The notifications from the driver entity that it is about to enter a certain
   phase of the IDE channel enumeration process.
-  
-  This function can be used to notify the IDE controller driver to perform 
-  specific actions, including any chipset-specific initialization, so that the 
-  chipset is ready to enter the next phase. Seven notification points are defined 
-  at this time. 
-  
-  More synchronization points may be added as required in the future.  
+
+  This function can be used to notify the IDE controller driver to perform
+  specific actions, including any chipset-specific initialization, so that the
+  chipset is ready to enter the next phase. Seven notification points are defined
+  at this time.
+
+  More synchronization points may be added as required in the future.
 
   @param[in] This      The pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance.
   @param[in] Phase     The phase during enumeration.
@@ -299,9 +293,9 @@ EFI_STATUS
   @retval EFI_SUCCESS             The notification was accepted without any errors.
   @retval EFI_UNSUPPORTED         Phase is not supported.
   @retval EFI_INVALID_PARAMETER   Channel is invalid (Channel >= ChannelCount).
-  @retval EFI_NOT_READY           This phase cannot be entered at this time; for 
-                                  example, an attempt was made to enter a Phase 
-                                  without having entered one or more previous 
+  @retval EFI_NOT_READY           This phase cannot be entered at this time; for
+                                  example, an attempt was made to enter a Phase
+                                  without having entered one or more previous
                                   Phase.
 
 **/
@@ -316,32 +310,32 @@ EFI_STATUS
 /**
   Submits the device information to the IDE controller driver.
 
-  This function is used by the driver entity to pass detailed information about 
-  a particular device to the IDE controller driver. The driver entity obtains 
+  This function is used by the driver entity to pass detailed information about
+  a particular device to the IDE controller driver. The driver entity obtains
   this information by issuing an ATA or ATAPI IDENTIFY_DEVICE command. IdentifyData
-  is the pointer to the response data buffer. The IdentifyData buffer is owned 
-  by the driver entity, and the IDE controller driver must make a local copy 
-  of the entire buffer or parts of the buffer as needed. The original IdentifyData 
+  is the pointer to the response data buffer. The IdentifyData buffer is owned
+  by the driver entity, and the IDE controller driver must make a local copy
+  of the entire buffer or parts of the buffer as needed. The original IdentifyData
   buffer pointer may not be valid when
-  
+
     - EFI_IDE_CONTROLLER_INIT_PROTOCOL.CalculateMode() or
     - EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyMode() is called at a later point.
-    
-  The IDE controller driver may consult various fields of EFI_IDENTIFY_DATA to 
-  compute the optimum mode for the device. These fields are not limited to the 
-  timing information. For example, an implementation of the IDE controller driver 
-  may examine the vendor and type/mode field to match known bad drives.  
-  
-  The driver entity may submit drive information in any order, as long as it 
-  submits information for all the devices belonging to the enumeration group 
+
+  The IDE controller driver may consult various fields of EFI_IDENTIFY_DATA to
+  compute the optimum mode for the device. These fields are not limited to the
+  timing information. For example, an implementation of the IDE controller driver
+  may examine the vendor and type/mode field to match known bad drives.
+
+  The driver entity may submit drive information in any order, as long as it
+  submits information for all the devices belonging to the enumeration group
   before EFI_IDE_CONTROLLER_INIT_PROTOCOL.CalculateMode() is called for any device
   in that enumeration group. If a device is absent, EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData()
-  should be called with IdentifyData set to NULL.  The IDE controller driver may 
-  not have any other mechanism to know whether a device is present or not. Therefore, 
-  setting IdentifyData to NULL does not constitute an error condition. 
-  EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData() can be called only once for a 
-  given (Channel, Device) pair.  
-    
+  should be called with IdentifyData set to NULL.  The IDE controller driver may
+  not have any other mechanism to know whether a device is present or not. Therefore,
+  setting IdentifyData to NULL does not constitute an error condition.
+  EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData() can be called only once for a
+  given (Channel, Device) pair.
+
   @param[in] This           A pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance.
   @param[in] Channel        Zero-based channel number.
   @param[in] Device         Zero-based device number on the Channel.
@@ -364,31 +358,31 @@ EFI_STATUS
 /**
   Disqualifies specific modes for an IDE device.
 
-  This function allows the driver entity or other drivers (such as platform 
+  This function allows the driver entity or other drivers (such as platform
   drivers) to reject certain timing modes and request the IDE controller driver
-  to recalculate modes. This function allows the driver entity and the IDE 
-  controller driver to negotiate the timings on a per-device basis. This function 
-  is useful in the case of drives that lie about their capabilities. An example 
-  is when the IDE device fails to accept the timing modes that are calculated 
+  to recalculate modes. This function allows the driver entity and the IDE
+  controller driver to negotiate the timings on a per-device basis. This function
+  is useful in the case of drives that lie about their capabilities. An example
+  is when the IDE device fails to accept the timing modes that are calculated
   by the IDE controller driver based on the response to the Identify Drive command.
 
-  If the driver entity does not want to limit the ATA timing modes and leave that 
-  decision to the IDE controller driver, it can either not call this function for 
-  the given device or call this function and set the Valid flag to FALSE for all 
+  If the driver entity does not want to limit the ATA timing modes and leave that
+  decision to the IDE controller driver, it can either not call this function for
+  the given device or call this function and set the Valid flag to FALSE for all
   modes that are listed in EFI_ATA_COLLECTIVE_MODE.
-  
-  The driver entity may disqualify modes for a device in any order and any number 
+
+  The driver entity may disqualify modes for a device in any order and any number
   of times.
-  
-  This function can be called multiple times to invalidate multiple modes of the 
-  same type (e.g., Programmed Input/Output [PIO] modes 3 and 4). See the ATA/ATAPI 
-  specification for more information on PIO modes.  
-  
+
+  This function can be called multiple times to invalidate multiple modes of the
+  same type (e.g., Programmed Input/Output [PIO] modes 3 and 4). See the ATA/ATAPI
+  specification for more information on PIO modes.
+
   For Serial ATA (SATA) controllers, this member function can be used to disqualify
   a higher transfer rate mode on a given channel. For example, a platform driver
-  may inform the IDE controller driver to not use second-generation (Gen2) speeds 
+  may inform the IDE controller driver to not use second-generation (Gen2) speeds
   for a certain SATA drive.
-  
+
   @param[in] This       The pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance.
   @param[in] Channel    The zero-based channel number.
   @param[in] Device     The zero-based device number on the Channel.
@@ -399,7 +393,7 @@ EFI_STATUS
   @retval EFI_INVALID_PARAMETER   Channel is invalid (Channel >= ChannelCount).
   @retval EFI_INVALID_PARAMETER   Device is invalid.
   @retval EFI_INVALID_PARAMETER   IdentifyData is NULL.
-                                
+
 **/
 typedef
 EFI_STATUS
@@ -414,39 +408,39 @@ EFI_STATUS
   Returns the information about the optimum modes for the specified IDE device.
 
   This function is used by the driver entity to obtain the optimum ATA modes for
-  a specific device.  The IDE controller driver takes into account the following 
+  a specific device.  The IDE controller driver takes into account the following
   while calculating the mode:
     - The IdentifyData inputs to EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData()
     - The BadModes inputs to EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyMode()
 
-  The driver entity is required to call EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData() 
-  for all the devices that belong to an enumeration group before calling 
-  EFI_IDE_CONTROLLER_INIT_PROTOCOL.CalculateMode() for any device in the same group.  
-  
-  The IDE controller driver will use controller- and possibly platform-specific 
-  algorithms to arrive at SupportedModes.  The IDE controller may base its 
-  decision on user preferences and other considerations as well. This function 
-  may be called multiple times because the driver entity may renegotiate the mode 
+  The driver entity is required to call EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData()
+  for all the devices that belong to an enumeration group before calling
+  EFI_IDE_CONTROLLER_INIT_PROTOCOL.CalculateMode() for any device in the same group.
+
+  The IDE controller driver will use controller- and possibly platform-specific
+  algorithms to arrive at SupportedModes.  The IDE controller may base its
+  decision on user preferences and other considerations as well. This function
+  may be called multiple times because the driver entity may renegotiate the mode
   with the IDE controller driver using EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyMode().
-    
-  The driver entity may collect timing information for various devices in any 
+
+  The driver entity may collect timing information for various devices in any
   order. The driver entity is responsible for making sure that all the dependencies
-  are satisfied. For example, the SupportedModes information for device A that 
-  was previously returned may become stale after a call to 
+  are satisfied. For example, the SupportedModes information for device A that
+  was previously returned may become stale after a call to
   EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyMode() for device B.
-  
-  The buffer SupportedModes is allocated by the callee because the caller does 
-  not necessarily know the size of the buffer. The type EFI_ATA_COLLECTIVE_MODE 
-  is defined in a way that allows for future extensibility and can be of variable 
-  length. This memory pool should be deallocated by the caller when it is no 
-  longer necessary.  
-  
-  The IDE controller driver for a Serial ATA (SATA) controller can use this 
-  member function to force a lower speed (first-generation [Gen1] speeds on a 
-  second-generation [Gen2]-capable hardware).  The IDE controller driver can 
-  also allow the driver entity to stay with the speed that has been negotiated 
+
+  The buffer SupportedModes is allocated by the callee because the caller does
+  not necessarily know the size of the buffer. The type EFI_ATA_COLLECTIVE_MODE
+  is defined in a way that allows for future extensibility and can be of variable
+  length. This memory pool should be deallocated by the caller when it is no
+  longer necessary.
+
+  The IDE controller driver for a Serial ATA (SATA) controller can use this
+  member function to force a lower speed (first-generation [Gen1] speeds on a
+  second-generation [Gen2]-capable hardware).  The IDE controller driver can
+  also allow the driver entity to stay with the speed that has been negotiated
   by the physical layer.
-  
+
   @param[in]  This             The pointer to the EFI_IDE_CONTROLLER_INIT_PROTOCOL instance.
   @param[in]  Channel          A zero-based channel number.
   @param[in]  Device           A zero-based device number on the Channel.
@@ -454,13 +448,13 @@ EFI_STATUS
 
   @retval EFI_SUCCESS             SupportedModes was returned.
   @retval EFI_INVALID_PARAMETER   Channel is invalid (Channel >= ChannelCount).
-  @retval EFI_INVALID_PARAMETER   Device is invalid. 
+  @retval EFI_INVALID_PARAMETER   Device is invalid.
   @retval EFI_INVALID_PARAMETER   SupportedModes is NULL.
-  @retval EFI_NOT_READY           Modes cannot be calculated due to a lack of 
-                                  data.  This error may happen if 
-                                  EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData() 
-                                  and EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyData() 
-                                  were not called for at least one drive in the 
+  @retval EFI_NOT_READY           Modes cannot be calculated due to a lack of
+                                  data.  This error may happen if
+                                  EFI_IDE_CONTROLLER_INIT_PROTOCOL.SubmitData()
+                                  and EFI_IDE_CONTROLLER_INIT_PROTOCOL.DisqualifyData()
+                                  were not called for at least one drive in the
                                   same enumeration group.
 
 **/
@@ -477,9 +471,9 @@ EFI_STATUS
   Commands the IDE controller driver to program the IDE controller hardware
   so that the specified device can operate at the specified mode.
 
-  This function is used by the driver entity to instruct the IDE controller 
-  driver to program the IDE controller hardware to the specified modes. This 
-  function can be called only once for a particular device. For a Serial ATA 
+  This function is used by the driver entity to instruct the IDE controller
+  driver to program the IDE controller hardware to the specified modes. This
+  function can be called only once for a particular device. For a Serial ATA
   (SATA) Advanced Host Controller Interface (AHCI) controller, no controller-
   specific programming may be required.
 
@@ -513,48 +507,48 @@ struct _EFI_IDE_CONTROLLER_INIT_PROTOCOL {
   /// Returns the information about a specific channel.
   ///
   EFI_IDE_CONTROLLER_GET_CHANNEL_INFO    GetChannelInfo;
-  
+
   ///
   /// The notification that the driver entity is about to enter the
-  /// specified phase during the enumeration process.  
+  /// specified phase during the enumeration process.
   ///
   EFI_IDE_CONTROLLER_NOTIFY_PHASE        NotifyPhase;
-  
+
   ///
   /// Submits the Drive Identify data that was returned by the device.
   ///
   EFI_IDE_CONTROLLER_SUBMIT_DATA         SubmitData;
-  
+
   ///
-  /// Submits information about modes that should be disqualified.  The specified 
-  /// IDE device does not support these modes and these modes should not be 
+  /// Submits information about modes that should be disqualified.  The specified
+  /// IDE device does not support these modes and these modes should not be
   /// returned by EFI_IDE_CONTROLLER_INIT_PROTOCOL.CalculateMode()
   ///
   EFI_IDE_CONTROLLER_DISQUALIFY_MODE     DisqualifyMode;
-  
+
   ///
   /// Calculates and returns the optimum mode for a particular IDE device.
   ///
   EFI_IDE_CONTROLLER_CALCULATE_MODE      CalculateMode;
-  
+
   ///
   /// Programs the IDE controller hardware to the default timing or per the modes
-  /// that were returned by the last call to EFI_IDE_CONTROLLER_INIT_PROTOCOL.CalculateMode().  
+  /// that were returned by the last call to EFI_IDE_CONTROLLER_INIT_PROTOCOL.CalculateMode().
   ///
   EFI_IDE_CONTROLLER_SET_TIMING          SetTiming;
-  
+
   ///
   /// Set to TRUE if the enumeration group includes all the channels that are
   /// produced by this controller. Set to FALSE if an enumeration group consists of
-  /// only one channel.  
+  /// only one channel.
   ///
   BOOLEAN                                EnumAll;
-  
+
   ///
   /// The number of channels that are produced by this controller. Parallel ATA
-  /// (PATA) controllers can support up to two channels. Advanced Host Controller 
+  /// (PATA) controllers can support up to two channels. Advanced Host Controller
   /// Interface (AHCI) Serial ATA (SATA) controllers can support up to 32 channels,
-  /// each of which can have up to one device. In the presence of a multiplier, 
+  /// each of which can have up to one device. In the presence of a multiplier,
   /// each channel can have fifteen devices.
   ///
   UINT8                                  ChannelCount;
diff --git a/MdePkg/Include/Protocol/IncompatiblePciDeviceSupport.h b/MdePkg/Include/Protocol/IncompatiblePciDeviceSupport.h
index 9a924d4a6725..d963cb43f4ca 100644
--- a/MdePkg/Include/Protocol/IncompatiblePciDeviceSupport.h
+++ b/MdePkg/Include/Protocol/IncompatiblePciDeviceSupport.h
@@ -1,74 +1,68 @@
 /** @file
   This file declares Incompatible PCI Device Support Protocol
-  
-  Allows the PCI bus driver to support resource allocation for some PCI devices 
+
+  Allows the PCI bus driver to support resource allocation for some PCI devices
   that do not comply with the PCI Specification.
-  
-  @par Note: 
-    This protocol is optional. Only those platforms that implement this protocol 
-    will have the capability to support incompatible PCI devices. The absence of 
-    this protocol can cause the PCI bus driver to configure these incompatible 
-    PCI devices incorrectly. As a result, these devices may not work properly.  
-  
+
+  @par Note:
+    This protocol is optional. Only those platforms that implement this protocol
+    will have the capability to support incompatible PCI devices. The absence of
+    this protocol can cause the PCI bus driver to configure these incompatible
+    PCI devices incorrectly. As a result, these devices may not work properly.
+
   The EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL is used by the PCI bus driver
-  to support resource allocation for some PCI devices that do not comply with the 
-  PCI Specification.  This protocol can find some incompatible PCI devices and 
-  report their special resource requirements to the PCI bus driver. The generic 
-  PCI bus driver does not have prior knowledge of any incompatible PCI devices. 
-  It interfaces with the EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL to find out 
-  if a device is incompatible and to obtain the special configuration requirements 
+  to support resource allocation for some PCI devices that do not comply with the
+  PCI Specification.  This protocol can find some incompatible PCI devices and
+  report their special resource requirements to the PCI bus driver. The generic
+  PCI bus driver does not have prior knowledge of any incompatible PCI devices.
+  It interfaces with the EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL to find out
+  if a device is incompatible and to obtain the special configuration requirements
   for a specific incompatible PCI device.
 
   This protocol is optional, and only one instance of this protocol can be present
-  in the system. If a platform supports this protocol, this protocol is produced 
-  by a Driver Execution Environment (DXE) driver and must be made available before 
-  the Boot Device Selection (BDS) phase. The PCI bus driver will look for the 
-  presence of this protocol before it begins PCI enumeration.  If this protocol 
+  in the system. If a platform supports this protocol, this protocol is produced
+  by a Driver Execution Environment (DXE) driver and must be made available before
+  the Boot Device Selection (BDS) phase. The PCI bus driver will look for the
+  presence of this protocol before it begins PCI enumeration.  If this protocol
   exists in a platform, it indicates that the platform has the capability to support
-  those incompatible PCI devices. However, final support for incompatible PCI 
-  devices still depends on the implementation of the PCI bus driver. The PCI bus 
-  driver may fully, partially, or not even support these incompatible devices.  
-
-  During PCI bus enumeration, the PCI bus driver will probe the PCI Base Address 
-  Registers (BARs) for each PCI device regardless of whether the PCI device is 
-  incompatible or not to determine the resource requirements so that the PCI bus 
-  driver can invoke the proper PCI resources for them.  Generally, this resource 
+  those incompatible PCI devices. However, final support for incompatible PCI
+  devices still depends on the implementation of the PCI bus driver. The PCI bus
+  driver may fully, partially, or not even support these incompatible devices.
+
+  During PCI bus enumeration, the PCI bus driver will probe the PCI Base Address
+  Registers (BARs) for each PCI device regardless of whether the PCI device is
+  incompatible or not to determine the resource requirements so that the PCI bus
+  driver can invoke the proper PCI resources for them.  Generally, this resource
   information includes the following:
     - Resource type
     - Resource length
     - Alignment
-    
+
   However, some incompatible PCI devices may have special requirements. As a result,
-  the length or the alignment that is derived through BAR probing may not be exactly 
-  the same as the actual resource requirement of the device. For example, there 
+  the length or the alignment that is derived through BAR probing may not be exactly
+  the same as the actual resource requirement of the device. For example, there
   are some devices that request I/O resources at a length of 0x100 from their I/O
-  BAR, but these incompatible devices will never work correctly if an odd I/O base 
-  address, such as 0x100, 0x300, or 0x500, is assigned to the BAR. Instead, these 
-  devices request an even base address, such as 0x200 or 0x400. The Incompatible 
-  PCI Device Support Protocol can then be used to obtain these special resource 
-  requirements for these incompatible PCI devices. In this way, the PCI bus driver 
-  will take special consideration for these devices during PCI resource allocation 
+  BAR, but these incompatible devices will never work correctly if an odd I/O base
+  address, such as 0x100, 0x300, or 0x500, is assigned to the BAR. Instead, these
+  devices request an even base address, such as 0x200 or 0x400. The Incompatible
+  PCI Device Support Protocol can then be used to obtain these special resource
+  requirements for these incompatible PCI devices. In this way, the PCI bus driver
+  will take special consideration for these devices during PCI resource allocation
   to ensure that they can work correctly.
-  
+
   This protocol may support the following incompatible PCI BAR types:
     - I/O or memory length that is different from what the BAR reports
     - I/O or memory alignment that is different from what the BAR reports
     - Fixed I/O or memory base address
-    
-  See the Conventional PCI Specification 3.0 for the details of how a PCI BAR 
-  reports the resource length and the alignment that it requires.
 
-  Copyright (c) 2007 - 2009, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
+  See the Conventional PCI Specification 3.0 for the details of how a PCI BAR
+  reports the resource length and the alignment that it requires.
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
-  This Protocol is defined in UEFI Platform Initialization Specification 1.2 
+  This Protocol is defined in UEFI Platform Initialization Specification 1.2
   Volume 5: Standards
 
 **/
@@ -92,51 +86,51 @@ typedef struct _EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL EFI_INCOMPATIBLE_PC
 /**
   Returns a list of ACPI resource descriptors that detail the special resource
   configuration requirements for an incompatible PCI device.
-  
-  This function returns a list of ACPI resource descriptors that detail the 
-  special resource configuration requirements for an incompatible PCI device.  
-  
+
+  This function returns a list of ACPI resource descriptors that detail the
+  special resource configuration requirements for an incompatible PCI device.
+
   Prior to bus enumeration, the PCI bus driver will look for the presence
   of the EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL. Only one instance of this
-  protocol can be present in the system. For each PCI device that the PCI bus 
+  protocol can be present in the system. For each PCI device that the PCI bus
   driver discovers, the PCI bus driver calls this function with the device's vendor
   ID, device ID, revision ID, subsystem vendor ID, and subsystem device ID. If the
   VendorId, DeviceId, RevisionId, SubsystemVendorId, or SubsystemDeviceId value is
   set to (UINTN)-1, that field will be ignored. The ID values that are not (UINTN)-1
-  will be used to identify the current device.  
-  
-  This function will only return EFI_SUCCESS. However, if the device is an 
-  incompatible PCI device, a list of ACPI resource descriptors will be returned 
-  in Configuration. Otherwise, NULL will be returned in Configuration instead. 
-  The PCI bus driver does not need to allocate memory for Configuration. However, 
-  it is the PCI bus driver's responsibility to free it. The PCI bus driver then 
-  can configure this device with the information that is derived from this list 
+  will be used to identify the current device.
+
+  This function will only return EFI_SUCCESS. However, if the device is an
+  incompatible PCI device, a list of ACPI resource descriptors will be returned
+  in Configuration. Otherwise, NULL will be returned in Configuration instead.
+  The PCI bus driver does not need to allocate memory for Configuration. However,
+  it is the PCI bus driver's responsibility to free it. The PCI bus driver then
+  can configure this device with the information that is derived from this list
   of resource nodes, rather than the result of BAR probing.
 
-  Only the following two resource descriptor types from the ACPI Specification 
+  Only the following two resource descriptor types from the ACPI Specification
   may be used to describe the incompatible PCI device resource requirements:
     - QWORD Address Space Descriptor (ACPI 2.0, section 6.4.3.5.1; also ACPI 3.0)
     - End Tag (ACPI 2.0, section 6.4.2.8; also ACPI 3.0)
 
-  The QWORD Address Space Descriptor can describe memory, I/O, and bus number 
-  ranges for dynamic or fixed resources.  The configuration of a PCI root bridge 
-  is described with one or more QWORD Address Space Descriptors, followed by an 
+  The QWORD Address Space Descriptor can describe memory, I/O, and bus number
+  ranges for dynamic or fixed resources.  The configuration of a PCI root bridge
+  is described with one or more QWORD Address Space Descriptors, followed by an
   End Tag. See the ACPI Specification for details on the field values.
-  
-  @param[in]  This                Pointer to the EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL 
+
+  @param[in]  This                Pointer to the EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL
                                   instance.
-  @param[in]  VendorId            A unique ID to identify the manufacturer of 
+  @param[in]  VendorId            A unique ID to identify the manufacturer of
                                   the PCI device.  See the Conventional PCI
                                   Specification 3.0 for details.
-  @param[in]  DeviceId            A unique ID to identify the particular PCI 
-                                  device. See the Conventional PCI Specification 
+  @param[in]  DeviceId            A unique ID to identify the particular PCI
+                                  device. See the Conventional PCI Specification
                                   3.0 for details.
-  @param[in]  RevisionId          A PCI device-specific revision identifier. 
+  @param[in]  RevisionId          A PCI device-specific revision identifier.
                                   See the Conventional PCI Specification 3.0
                                   for details.
-  @param[in]  SubsystemVendorId   Specifies the subsystem vendor ID. See the 
+  @param[in]  SubsystemVendorId   Specifies the subsystem vendor ID. See the
                                   Conventional PCI Specification 3.0 for details.
-  @param[in]  SubsystemDeviceId   Specifies the subsystem device ID. See the 
+  @param[in]  SubsystemDeviceId   Specifies the subsystem device ID. See the
                                   Conventional PCI Specification 3.0 for details.
   @param[out] Configuration       A list of ACPI resource descriptors that detail
                                   the configuration requirement.
diff --git a/MdePkg/Include/Protocol/Ip4.h b/MdePkg/Include/Protocol/Ip4.h
index e36f38d8f5d2..519c80d62916 100644
--- a/MdePkg/Include/Protocol/Ip4.h
+++ b/MdePkg/Include/Protocol/Ip4.h
@@ -6,21 +6,15 @@
   - EFI IPv4 Variable (deprecated in UEFI 2.4B)
   - EFI IPv4 Protocol.
   The EFI IPv4 Protocol provides basic network IPv4 packet I/O services,
-  which includes support foR a subset of the Internet Control Message 
+  which includes support foR a subset of the Internet Control Message
   Protocol (ICMP) and may include support for the Internet Group Management
   Protocol (IGMP).
-  
-Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.   
-
-  @par Revision Reference:          
-  This Protocol is introduced in UEFI Specification 2.0.        
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  This Protocol is introduced in UEFI Specification 2.0.
 
 **/
 
@@ -49,7 +43,7 @@ typedef struct {
   EFI_HANDLE              InstanceHandle;
   EFI_IPv4_ADDRESS        Ip4Address;
   EFI_IPv4_ADDRESS        SubnetMask;
-} EFI_IP4_ADDRESS_PAIR; 
+} EFI_IP4_ADDRESS_PAIR;
 
 ///
 /// EFI_IP4_VARIABLE_DATA is deprecated in the UEFI 2.4B and should not be used any more.
@@ -271,7 +265,7 @@ typedef struct {
 
 /**
   Gets the current operational settings for this instance of the EFI IPv4 Protocol driver.
-  
+
   The GetModeData() function returns the current operational mode data for this
   driver instance. The data fields in EFI_IP4_MODE_DATA are read only. This
   function is used optionally to retrieve the operational mode data of underlying
@@ -294,11 +288,11 @@ EFI_STATUS
   OUT       EFI_IP4_MODE_DATA               *Ip4ModeData     OPTIONAL,
   OUT       EFI_MANAGED_NETWORK_CONFIG_DATA *MnpConfigData   OPTIONAL,
   OUT       EFI_SIMPLE_NETWORK_MODE         *SnpModeData     OPTIONAL
-  );  
+  );
 
 /**
   Assigns an IPv4 address and subnet mask to this EFI IPv4 Protocol driver instance.
-  
+
   The Configure() function is used to set, change, or reset the operational
   parameters and filter settings for this EFI IPv4 Protocol instance. Until these
   parameters have been set, no network traffic can be sent or received by this
@@ -307,14 +301,14 @@ EFI_STATUS
   parameters have been set again. Each EFI IPv4 Protocol instance can be started
   and stopped independently of each other by enabling or disabling their receive
   filter settings with the Configure() function.
-  
+
   When IpConfigData.UseDefaultAddress is set to FALSE, the new station address will
   be appended as an alias address into the addresses list in the EFI IPv4 Protocol
   driver. While set to TRUE, Configure() will trigger the EFI_IP4_CONFIG_PROTOCOL
   to retrieve the default IPv4 address if it is not available yet. Clients could
   frequently call GetModeData() to check the status to ensure that the default IPv4
   address is ready.
-  
+
   If operational parameters are reset or changed, any pending transmit and receive
   requests will be cancelled. Their completion token status will be set to EFI_ABORTED
   and their events will be signaled.
@@ -328,7 +322,7 @@ EFI_STATUS
   @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
                                 This is NULL.
                                 IpConfigData.StationAddress is not a unicast IPv4 address.
-                                IpConfigData.SubnetMask is not a valid IPv4 subnet 
+                                IpConfigData.SubnetMask is not a valid IPv4 subnet
   @retval EFI_UNSUPPORTED       One or more of the following conditions is TRUE:
                                 A configuration protocol (DHCP, BOOTP, RARP, etc.) could
                                 not be located when clients choose to use the default IPv4
@@ -342,20 +336,20 @@ EFI_STATUS
                                 Protocol driver instance is not opened.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_IP4_CONFIGURE)(
   IN EFI_IP4_PROTOCOL    *This,
   IN EFI_IP4_CONFIG_DATA *IpConfigData     OPTIONAL
-  );  
+  );
 
 /**
   Joins and leaves multicast groups.
-  
+
   The Groups() function is used to join and leave multicast group sessions. Joining
   a group will enable reception of matching multicast packets. Leaving a group will
   disable the multicast packet reception.
-  
+
   If JoinFlag is FALSE and GroupAddress is NULL, all joined groups will be left.
 
   @param  This                  The pointer to the EFI_IP4_PROTOCOL instance.
@@ -379,32 +373,32 @@ EFI_STATUS
   @retval EFI_DEVICE_ERROR      An unexpected system or network error occurred.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_IP4_GROUPS)(
   IN EFI_IP4_PROTOCOL    *This,
   IN BOOLEAN             JoinFlag,
   IN EFI_IPv4_ADDRESS    *GroupAddress  OPTIONAL
-  );    
+  );
 
 /**
   Adds and deletes routing table entries.
 
   The Routes() function adds a route to or deletes a route from the routing table.
-  
+
   Routes are determined by comparing the SubnetAddress with the destination IPv4
   address arithmetically AND-ed with the SubnetMask. The gateway address must be
   on the same subnet as the configured station address.
-  
+
   The default route is added with SubnetAddress and SubnetMask both set to 0.0.0.0.
   The default route matches all destination IPv4 addresses that do not match any
   other routes.
-  
+
   A GatewayAddress that is zero is a nonroute. Packets are sent to the destination
   IP address if it can be found in the ARP cache or on the local subnet. One automatic
   nonroute entry will be inserted into the routing table for outgoing packets that
   are addressed to a local subnet (gateway address of 0.0.0.0).
-  
+
   Each EFI IPv4 Protocol instance has its own independent routing table. Those EFI
   IPv4 Protocol instances that use the default IPv4 address will also have copies
   of the routing table that was provided by the EFI_IP4_CONFIG_PROTOCOL, and these
@@ -435,17 +429,17 @@ EFI_STATUS
   @retval EFI_NOT_FOUND          This route is not in the routing table (when DeleteRoute is TRUE).
   @retval EFI_ACCESS_DENIED      The route is already defined in the routing table (when
                                  DeleteRoute is FALSE).
-                                 
+
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_IP4_ROUTES)(
   IN EFI_IP4_PROTOCOL    *This,
   IN BOOLEAN             DeleteRoute,
   IN EFI_IPv4_ADDRESS    *SubnetAddress,
   IN EFI_IPv4_ADDRESS    *SubnetMask,
-  IN EFI_IPv4_ADDRESS    *GatewayAddress  
-  );  
+  IN EFI_IPv4_ADDRESS    *GatewayAddress
+  );
 
 /**
   Places outgoing data packets into the transmit queue.
@@ -465,7 +459,7 @@ EFI_STATUS
   @retval  EFI_ACCESS_DENIED     The transmit completion token with the same Token.Event
                                  was already in the transmit queue.
   @retval  EFI_NOT_READY         The completion token could not be queued because the transmit
-                                 queue is full. 
+                                 queue is full.
   @retval  EFI_NOT_FOUND         Not route is found to destination address.
   @retval  EFI_OUT_OF_RESOURCES  Could not queue the transmit data.
   @retval  EFI_BUFFER_TOO_SMALL  Token.Packet.TxData.TotalDataLength is too
@@ -476,19 +470,19 @@ EFI_STATUS
                                  DoNotFragment is TRUE.)
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_IP4_TRANSMIT)(
   IN EFI_IP4_PROTOCOL          *This,
   IN EFI_IP4_COMPLETION_TOKEN  *Token
-  );    
+  );
 
 /**
   Places a receiving request into the receiving queue.
-  
+
   The Receive() function places a completion token into the receive packet queue.
   This function is always asynchronous.
-  
+
   The Token.Event field in the completion token must be filled in by the caller
   and cannot be NULL. When the receive operation completes, the EFI IPv4 Protocol
   driver updates the Token.Status and Token.Packet.RxData fields and the Token.Event
@@ -515,16 +509,16 @@ EFI_STATUS
   @retval EFI_ICMP_ERROR        An ICMP error packet was received.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_IP4_RECEIVE)(
   IN EFI_IP4_PROTOCOL          *This,
   IN EFI_IP4_COMPLETION_TOKEN  *Token
-  );      
+  );
 
 /**
   Abort an asynchronous transmit or receive request.
-  
+
   The Cancel() function is used to abort a pending transmit or receive request.
   If the token is in the transmit or receive request queues, after calling this
   function, Token->Status will be set to EFI_ABORTED and then Token->Event will
@@ -556,16 +550,16 @@ EFI_STATUS
 (EFIAPI *EFI_IP4_CANCEL)(
   IN EFI_IP4_PROTOCOL          *This,
   IN EFI_IP4_COMPLETION_TOKEN  *Token OPTIONAL
-  );      
-  
+  );
+
 /**
   Polls for incoming data packets and processes outgoing data packets.
-  
+
   The Poll() function polls for incoming data packets and processes outgoing data
   packets. Network drivers and applications can call the EFI_IP4_PROTOCOL.Poll()
   function to increase the rate that data packets are moved between the communications
   device and the transmit and receive queues.
-  
+
   In some systems the periodic timer event may not poll the underlying communications
   device fast enough to transmit and/or receive all data packets without missing
   incoming packets or dropping outgoing packets. Drivers and applications that are
@@ -585,14 +579,14 @@ EFI_STATUS
                                  Consider increasing the polling rate.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_IP4_POLL)(
   IN EFI_IP4_PROTOCOL          *This
-  );  
+  );
 
 ///
-/// The EFI IPv4 Protocol implements a simple packet-oriented interface that can be 
+/// The EFI IPv4 Protocol implements a simple packet-oriented interface that can be
 /// used by drivers, daemons, and applications to transmit and receive network packets.
 ///
 struct _EFI_IP4_PROTOCOL {
diff --git a/MdePkg/Include/Protocol/Ip4Config.h b/MdePkg/Include/Protocol/Ip4Config.h
index ece7efb6688c..6f991feb3491 100644
--- a/MdePkg/Include/Protocol/Ip4Config.h
+++ b/MdePkg/Include/Protocol/Ip4Config.h
@@ -2,16 +2,10 @@
   This file provides a definition of the EFI IPv4 Configuration
   Protocol.
 
-Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-  
-  @par Revision Reference:          
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
   This Protocol is introduced in UEFI Specification 2.0.
 
 **/
@@ -31,11 +25,11 @@ typedef struct _EFI_IP4_CONFIG_PROTOCOL EFI_IP4_CONFIG_PROTOCOL;
         (EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS)
 
 ///
-/// EFI_IP4_IPCONFIG_DATA contains the minimum IPv4 configuration data 
-/// that is needed to start basic network communication. The StationAddress 
+/// EFI_IP4_IPCONFIG_DATA contains the minimum IPv4 configuration data
+/// that is needed to start basic network communication. The StationAddress
 /// and SubnetMask must be a valid unicast IP address and subnet mask.
-/// If RouteTableSize is not zero, then RouteTable contains a properly 
-/// formatted routing table for the StationAddress/SubnetMask, with the 
+/// If RouteTableSize is not zero, then RouteTable contains a properly
+/// formatted routing table for the StationAddress/SubnetMask, with the
 /// last entry in the table being the default route.
 ///
 typedef struct {
@@ -61,47 +55,47 @@ typedef struct {
 
 /**
   Starts running the configuration policy for the EFI IPv4 Protocol driver.
-  
-  The Start() function is called to determine and to begin the platform 
-  configuration policy by the EFI IPv4 Protocol driver. This determination may 
-  be as simple as returning EFI_UNSUPPORTED if there is no EFI IPv4 Protocol 
-  driver configuration policy. It may be as involved as loading some defaults 
-  from nonvolatile storage, downloading dynamic data from a DHCP server, and 
+
+  The Start() function is called to determine and to begin the platform
+  configuration policy by the EFI IPv4 Protocol driver. This determination may
+  be as simple as returning EFI_UNSUPPORTED if there is no EFI IPv4 Protocol
+  driver configuration policy. It may be as involved as loading some defaults
+  from nonvolatile storage, downloading dynamic data from a DHCP server, and
   checking permissions with a site policy server.
-  Starting the configuration policy is just the beginning. It may finish almost 
-  instantly or it may take several minutes before it fails to retrieve configuration 
-  information from one or more servers. Once the policy is started, drivers 
-  should use the DoneEvent parameter to determine when the configuration policy 
-  has completed. EFI_IP4_CONFIG_PROTOCOL.GetData() must then be called to 
+  Starting the configuration policy is just the beginning. It may finish almost
+  instantly or it may take several minutes before it fails to retrieve configuration
+  information from one or more servers. Once the policy is started, drivers
+  should use the DoneEvent parameter to determine when the configuration policy
+  has completed. EFI_IP4_CONFIG_PROTOCOL.GetData() must then be called to
   determine if the configuration succeeded or failed.
-  Until the configuration completes successfully, EFI IPv4 Protocol driver instances 
+  Until the configuration completes successfully, EFI IPv4 Protocol driver instances
   that are attempting to use default configurations must return EFI_NO_MAPPING.
-  Once the configuration is complete, the EFI IPv4 Configuration Protocol driver 
-  signals DoneEvent. The configuration may need to be updated in the future. 
-  Note that in this case the EFI IPv4 Configuration Protocol driver must signal 
-  ReconfigEvent, and all EFI IPv4 Protocol driver instances that are using default 
-  configurations must return EFI_NO_MAPPING until the configuration policy has 
+  Once the configuration is complete, the EFI IPv4 Configuration Protocol driver
+  signals DoneEvent. The configuration may need to be updated in the future.
+  Note that in this case the EFI IPv4 Configuration Protocol driver must signal
+  ReconfigEvent, and all EFI IPv4 Protocol driver instances that are using default
+  configurations must return EFI_NO_MAPPING until the configuration policy has
   been rerun.
 
   @param  This                   The pointer to the EFI_IP4_CONFIG_PROTOCOL instance.
-  @param  DoneEvent              Event that will be signaled when the EFI IPv4 
-                                 Protocol driver configuration policy completes 
+  @param  DoneEvent              Event that will be signaled when the EFI IPv4
+                                 Protocol driver configuration policy completes
                                  execution. This event must be of type EVT_NOTIFY_SIGNAL.
-  @param  ReconfigEvent          Event that will be signaled when the EFI IPv4 
-                                 Protocol driver configuration needs to be updated. 
+  @param  ReconfigEvent          Event that will be signaled when the EFI IPv4
+                                 Protocol driver configuration needs to be updated.
                                  This event must be of type EVT_NOTIFY_SIGNAL.
-  
-  @retval EFI_SUCCESS            The configuration policy for the EFI IPv4 Protocol 
+
+  @retval EFI_SUCCESS            The configuration policy for the EFI IPv4 Protocol
                                  driver is now running.
   @retval EFI_INVALID_PARAMETER  One or more of the following parameters is NULL:
                                   This
                                   DoneEvent
                                   ReconfigEvent
   @retval EFI_OUT_OF_RESOURCES   Required system resources could not be allocated.
-  @retval EFI_ALREADY_STARTED    The configuration policy for the EFI IPv4 Protocol 
+  @retval EFI_ALREADY_STARTED    The configuration policy for the EFI IPv4 Protocol
                                  driver was already started.
   @retval EFI_DEVICE_ERROR       An unexpected system error or network error occurred.
-  @retval EFI_UNSUPPORTED        This interface does not support the EFI IPv4 Protocol 
+  @retval EFI_UNSUPPORTED        This interface does not support the EFI IPv4 Protocol
                                  driver configuration.
 
 **/
@@ -115,18 +109,18 @@ EFI_STATUS
 
 /**
   Stops running the configuration policy for the EFI IPv4 Protocol driver.
-  
-  The Stop() function stops the configuration policy for the EFI IPv4 Protocol driver. 
+
+  The Stop() function stops the configuration policy for the EFI IPv4 Protocol driver.
   All configuration data will be lost after calling Stop().
 
   @param  This                   The pointer to the EFI_IP4_CONFIG_PROTOCOL instance.
 
-  @retval EFI_SUCCESS            The configuration policy for the EFI IPv4 Protocol 
+  @retval EFI_SUCCESS            The configuration policy for the EFI IPv4 Protocol
                                  driver has been stopped.
   @retval EFI_INVALID_PARAMETER  This is NULL.
-  @retval EFI_NOT_STARTED        The configuration policy for the EFI IPv4 Protocol 
+  @retval EFI_NOT_STARTED        The configuration policy for the EFI IPv4 Protocol
                                  driver was not started.
-  
+
 **/
 typedef
 EFI_STATUS
@@ -137,25 +131,25 @@ EFI_STATUS
 /**
   Returns the default configuration data (if any) for the EFI IPv4 Protocol driver.
 
-  The GetData() function returns the current configuration data for the EFI IPv4 
+  The GetData() function returns the current configuration data for the EFI IPv4
   Protocol driver after the configuration policy has completed.
-  
+
   @param  This                   The pointer to the EFI_IP4_CONFIG_PROTOCOL instance.
-  @param  IpConfigDataSize       On input, the size of the IpConfigData buffer. 
-                                 On output, the count of bytes that were written 
+  @param  IpConfigDataSize       On input, the size of the IpConfigData buffer.
+                                 On output, the count of bytes that were written
                                  into the IpConfigData buffer.
-  @param  IpConfigData           The pointer to the EFI IPv4 Configuration Protocol 
-                                 driver configuration data structure. 
-                                 Type EFI_IP4_IPCONFIG_DATA is defined in 
+  @param  IpConfigData           The pointer to the EFI IPv4 Configuration Protocol
+                                 driver configuration data structure.
+                                 Type EFI_IP4_IPCONFIG_DATA is defined in
                                  "Related Definitions" below.
 
   @retval EFI_SUCCESS            The EFI IPv4 Protocol driver configuration has been returned.
   @retval EFI_INVALID_PARAMETER  This is NULL.
-  @retval EFI_NOT_STARTED        The configuration policy for the EFI IPv4 Protocol 
+  @retval EFI_NOT_STARTED        The configuration policy for the EFI IPv4 Protocol
                                  driver is not running.
   @retval EFI_NOT_READY EFI      IPv4 Protocol driver configuration is still running.
   @retval EFI_ABORTED EFI        IPv4 Protocol driver configuration could not complete.
-  @retval EFI_BUFFER_TOO_SMALL   *IpConfigDataSize is smaller than the configuration 
+  @retval EFI_BUFFER_TOO_SMALL   *IpConfigDataSize is smaller than the configuration
                                  data buffer or IpConfigData is NULL.
 
 **/
@@ -168,8 +162,8 @@ EFI_STATUS
   );
 
 ///
-/// The EFI_IP4_CONFIG_PROTOCOL driver performs platform-dependent and policy-dependent 
-/// configurations for the EFI IPv4 Protocol driver. 
+/// The EFI_IP4_CONFIG_PROTOCOL driver performs platform-dependent and policy-dependent
+/// configurations for the EFI IPv4 Protocol driver.
 ///
 struct _EFI_IP4_CONFIG_PROTOCOL {
   EFI_IP4_CONFIG_START         Start;
diff --git a/MdePkg/Include/Protocol/Ip4Config2.h b/MdePkg/Include/Protocol/Ip4Config2.h
index 5eed0cbc1342..e1c4a7e3ff63 100644
--- a/MdePkg/Include/Protocol/Ip4Config2.h
+++ b/MdePkg/Include/Protocol/Ip4Config2.h
@@ -2,14 +2,8 @@
   This file provides a definition of the EFI IPv4 Configuration II
   Protocol.
 
-Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at<BR>
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 @par Revision Reference:
 This Protocol is introduced in UEFI Specification 2.5
@@ -33,43 +27,49 @@ typedef struct _EFI_IP4_CONFIG2_PROTOCOL EFI_IP4_CONFIG2_PROTOCOL;
 ///
 typedef enum {
   ///
-  /// The interface information of the communication device this EFI 
-  /// IPv4 Configuration II Protocol instance manages. This type of 
-  /// data is read only. The corresponding Data is of type 
+  /// The interface information of the communication device this EFI
+  /// IPv4 Configuration II Protocol instance manages. This type of
+  /// data is read only. The corresponding Data is of type
   /// EFI_IP4_CONFIG2_INTERFACE_INFO.
   ///
   Ip4Config2DataTypeInterfaceInfo,
   ///
-  /// The general configuration policy for the EFI IPv4 network stack 
-  /// running on the communication device this EFI IPv4 
-  /// Configuration II Protocol instance manages. The policy will 
-  /// affect other configuration settings. The corresponding Data is of 
+  /// The general configuration policy for the EFI IPv4 network stack
+  /// running on the communication device this EFI IPv4
+  /// Configuration II Protocol instance manages. The policy will
+  /// affect other configuration settings. The corresponding Data is of
   /// type EFI_IP4_CONFIG2_POLICY.
   ///
   Ip4Config2DataTypePolicy,
   ///
-  /// The station addresses set manually for the EFI IPv4 network 
-  /// stack. It is only configurable when the policy is 
-  /// Ip4Config2PolicyStatic. The corresponding Data is of 
-  /// type EFI_IP4_CONFIG2_MANUAL_ADDRESS.
+  /// The station addresses set manually for the EFI IPv4 network
+  /// stack. It is only configurable when the policy is
+  /// Ip4Config2PolicyStatic. The corresponding Data is of
+  /// type EFI_IP4_CONFIG2_MANUAL_ADDRESS. When DataSize
+  /// is 0 and Data is NULL, the existing configuration is cleared
+  /// from the EFI IPv4 Configuration II Protocol instance.
   ///
   Ip4Config2DataTypeManualAddress,
   ///
-  /// The gateway addresses set manually for the EFI IPv4 network 
-  /// stack running on the communication device this EFI IPv4 
-  /// Configuration II Protocol manages. It is not configurable when 
-  /// the policy is Ip4Config2PolicyDhcp. The gateway 
-  /// addresses must be unicast IPv4 addresses. The corresponding 
+  /// The gateway addresses set manually for the EFI IPv4 network
+  /// stack running on the communication device this EFI IPv4
+  /// Configuration II Protocol manages. It is not configurable when
+  /// the policy is Ip4Config2PolicyDhcp. The gateway
+  /// addresses must be unicast IPv4 addresses. The corresponding
   /// Data is a pointer to an array of EFI_IPv4_ADDRESS instances.
+  /// When DataSize is 0 and Data is NULL, the existing configuration
+  /// is cleared from the EFI IPv4 Configuration II Protocol instance.
   ///
   Ip4Config2DataTypeGateway,
   ///
-  /// The DNS server list for the EFI IPv4 network stack running on 
-  /// the communication device this EFI IPv4 Configuration II 
-  /// Protocol manages. It is not configurable when the policy is 
-  /// Ip4Config2PolicyDhcp. The DNS server addresses must be 
-  /// unicast IPv4 addresses. The corresponding Data is a pointer to 
-  /// an array of EFI_IPv4_ADDRESS instances.
+  /// The DNS server list for the EFI IPv4 network stack running on
+  /// the communication device this EFI IPv4 Configuration II
+  /// Protocol manages. It is not configurable when the policy is
+  /// Ip4Config2PolicyDhcp. The DNS server addresses must be
+  /// unicast IPv4 addresses. The corresponding Data is a pointer to
+  /// an array of EFI_IPv4_ADDRESS instances. When DataSize
+  /// is 0 and Data is NULL, the existing configuration is cleared
+  /// from the EFI IPv4 Configuration II Protocol instance.
   ///
   Ip4Config2DataTypeDnsServer,
   Ip4Config2DataTypeMaximum
@@ -89,7 +89,7 @@ typedef struct {
   ///
   CHAR16                Name[EFI_IP4_CONFIG2_INTERFACE_INFO_NAME_SIZE];
   ///
-  /// The interface type of the network interface. See RFC 1700, 
+  /// The interface type of the network interface. See RFC 1700,
   /// section "Number Hardware Type".
   ///
   UINT8                 IfType;
@@ -114,8 +114,8 @@ typedef struct {
   ///
   UINT32                RouteTableSize;
   ///
-  /// The route table of the IPv4 network stack runs on this interface. 
-  /// Set to NULL if RouteTableSize is zero. Type EFI_IP4_ROUTE_TABLE is defined in 
+  /// The route table of the IPv4 network stack runs on this interface.
+  /// Set to NULL if RouteTableSize is zero. Type EFI_IP4_ROUTE_TABLE is defined in
   /// EFI_IP4_PROTOCOL.GetModeData().
   ///
   EFI_IP4_ROUTE_TABLE   *RouteTable     OPTIONAL;
@@ -126,17 +126,17 @@ typedef struct {
 ///
 typedef enum {
   ///
-  /// Under this policy, the Ip4Config2DataTypeManualAddress, 
-  /// Ip4Config2DataTypeGateway and Ip4Config2DataTypeDnsServer configuration 
-  /// data are required to be set manually. The EFI IPv4 Protocol will get all 
-  /// required configuration such as IPv4 address, subnet mask and 
+  /// Under this policy, the Ip4Config2DataTypeManualAddress,
+  /// Ip4Config2DataTypeGateway and Ip4Config2DataTypeDnsServer configuration
+  /// data are required to be set manually. The EFI IPv4 Protocol will get all
+  /// required configuration such as IPv4 address, subnet mask and
   /// gateway settings from the EFI IPv4 Configuration II protocol.
   ///
   Ip4Config2PolicyStatic,
   ///
-  /// Under this policy, the Ip4Config2DataTypeManualAddress, 
-  /// Ip4Config2DataTypeGateway and Ip4Config2DataTypeDnsServer configuration data are 
-  /// not allowed to set via SetData(). All of these configurations are retrieved from DHCP 
+  /// Under this policy, the Ip4Config2DataTypeManualAddress,
+  /// Ip4Config2DataTypeGateway and Ip4Config2DataTypeDnsServer configuration data are
+  /// not allowed to set via SetData(). All of these configurations are retrieved from DHCP
   /// server or other auto-configuration mechanism.
   ///
   Ip4Config2PolicyDhcp,
@@ -147,59 +147,58 @@ typedef enum {
 /// EFI_IP4_CONFIG2_MANUAL_ADDRESS
 ///
 typedef struct {
-  ///  
+  ///
   /// The IPv4 unicast address.
   ///
   EFI_IPv4_ADDRESS        Address;
   ///
-  /// The subnet mask. 
+  /// The subnet mask.
   ///
   EFI_IPv4_ADDRESS        SubnetMask;
 } EFI_IP4_CONFIG2_MANUAL_ADDRESS;
 
 /**
-  Set the configuration for the EFI IPv4 network stack running on the communication device this EFI 
+  Set the configuration for the EFI IPv4 network stack running on the communication device this EFI
   IPv4 Configuration II Protocol instance manages.
 
-  This function is used to set the configuration data of type DataType for the EFI IPv4 network stack 
+  This function is used to set the configuration data of type DataType for the EFI IPv4 network stack
   running on the communication device this EFI IPv4 Configuration II Protocol instance manages.
   The successfully configured data is valid after system reset or power-off.
-  The DataSize is used to calculate the count of structure instances in the Data for some 
+  The DataSize is used to calculate the count of structure instances in the Data for some
   DataType that multiple structure instances are allowed.
-  This function is always non-blocking. When setting some typeof configuration data, an 
-  asynchronous process is invoked to check the correctness of the data, such as doing address conflict 
-  detection on the manually set local IPv4 address. EFI_NOT_READY is returned immediately to 
-  indicate that such an asynchronous process is invoked and the process is not finished yet. The caller 
+  This function is always non-blocking. When setting some typeof configuration data, an
+  asynchronous process is invoked to check the correctness of the data, such as doing address conflict
+  detection on the manually set local IPv4 address. EFI_NOT_READY is returned immediately to
+  indicate that such an asynchronous process is invoked and the process is not finished yet. The caller
   willing to get the result of the asynchronous process is required to call RegisterDataNotify()
-  to register an event on the specified configuration data. Once the event is signaled, the caller can call 
-  GetData()to get back the configuration data in order to know the result. For other types of 
-  configuration data that do not require an asynchronous configuration process, the result of the 
-  operation is immediately returned. 
+  to register an event on the specified configuration data. Once the event is signaled, the caller can call
+  GetData()to get back the configuration data in order to know the result. For other types of
+  configuration data that do not require an asynchronous configuration process, the result of the
+  operation is immediately returned.
 
-  @param[in]   This               Pointer to the EFI_IP4_CONFIG2_PROTOCOL instance.       
+  @param[in]   This               Pointer to the EFI_IP4_CONFIG2_PROTOCOL instance.
   @param[in]   DataType           The type of data to set.
   @param[in]   DataSize           Size of the buffer pointed to by Data in bytes.
-  @param[in]   Data               The data buffer to set. The type ofthe data buffer is associated 
-                                  with the DataType. 
+  @param[in]   Data               The data buffer to set. The type ofthe data buffer is associated
+                                  with the DataType.
 
-  @retval EFI_SUCCESS             The specified configuration data for the EFI IPv4 network stack is set 
+  @retval EFI_SUCCESS             The specified configuration data for the EFI IPv4 network stack is set
                                   successfully.
   @retval EFI_INVALID_PARAMETER   One or more of the following are TRUE:
                                   This is NULL.
-                                  Data is NULL.
-                                  One or more fields in Data do not match the requirement of the data type 
-                                  indicated by DataType.
-  @retval EFI_WRITE_PROTECTED     The specified configuration data is read-only or the specified configuration 
+                                  One or more fields in Data and DataSize do not match the
+                                  requirement of the data type indicated by DataType.
+  @retval EFI_WRITE_PROTECTED     The specified configuration data is read-only or the specified configuration
                                   data can not be set under the current policy.
   @retval EFI_ACCESS_DENIED       Another set operation on the specified configuration data is already in process.
-  @retval EFI_NOT_READY           An asynchronous process is invoked to set the specified configuration data and 
+  @retval EFI_NOT_READY           An asynchronous process is invoked to set the specified configuration data and
                                   the process is not finished yet.
-  @retval EFI_BAD_BUFFER_SIZE     The DataSize does not match the size of the type indicated by DataType.                                 
+  @retval EFI_BAD_BUFFER_SIZE     The DataSize does not match the size of the type indicated by DataType.
   @retval EFI_UNSUPPORTED         This DataType is not supported.
   @retval EFI_OUT_OF_RESOURCES    Required system resources could not be allocated.
   @retval EFI_DEVICE_ERROR        An unexpected system error or network error occurred.
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_IP4_CONFIG2_SET_DATA) (
   IN EFI_IP4_CONFIG2_PROTOCOL   *This,
@@ -209,35 +208,35 @@ EFI_STATUS
   );
 
 /**
-  Get the configuration data for the EFI IPv4 network stack running on the communication device this 
+  Get the configuration data for the EFI IPv4 network stack running on the communication device this
   EFI IPv4 Configuration II Protocol instance manages.
 
-  This function returns the configuration data of type DataType for the EFI IPv4 network stack 
+  This function returns the configuration data of type DataType for the EFI IPv4 network stack
   running on the communication device this EFI IPv4 Configuration II Protocol instance manages.
-  The caller is responsible for allocating the buffer usedto return the specified configuration data and 
+  The caller is responsible for allocating the buffer usedto return the specified configuration data and
   the required size will be returned to the caller if the size of the buffer is too small.
-  EFI_NOT_READY is returned if the specified configuration data is not ready due to an already in 
-  progress asynchronous configuration process. The caller can call RegisterDataNotify() to 
-  register an event on the specified configuration data. Once the asynchronous configuration process is 
-  finished, the event will be signaled and a subsequent GetData() call will return the specified 
+  EFI_NOT_READY is returned if the specified configuration data is not ready due to an already in
+  progress asynchronous configuration process. The caller can call RegisterDataNotify() to
+  register an event on the specified configuration data. Once the asynchronous configuration process is
+  finished, the event will be signaled and a subsequent GetData() call will return the specified
   configuration data.
 
-  @param[in]   This               Pointer to the EFI_IP4_CONFIG2_PROTOCOL instance.       
+  @param[in]   This               Pointer to the EFI_IP4_CONFIG2_PROTOCOL instance.
   @param[in]   DataType           The type of data to get.
-  @param[out]  DataSize           On input, in bytes, the size of Data. On output, in bytes, the size 
-                                  of buffer required to store the specified configuration data. 
-  @param[in]   Data               The data buffer in which the configuration data is returned. The 
-                                  type of the data buffer is associated with the DataType. Ignored 
-                                  if DataSize is 0.  
+  @param[out]  DataSize           On input, in bytes, the size of Data. On output, in bytes, the size
+                                  of buffer required to store the specified configuration data.
+  @param[in]   Data               The data buffer in which the configuration data is returned. The
+                                  type of the data buffer is associated with the DataType. Ignored
+                                  if DataSize is 0.
 
   @retval EFI_SUCCESS             The specified configuration data is got successfully.
   @retval EFI_INVALID_PARAMETER   One or more of the followings are TRUE:
                                   This is NULL.
                                   DataSize is NULL.
                                   Data is NULL if *DataSizeis not zero.
-  @retval EFI_BUFFER_TOO_SMALL    The size of Data is too small for the specified configuration data 
+  @retval EFI_BUFFER_TOO_SMALL    The size of Data is too small for the specified configuration data
                                   and the required size is returned in DataSize.
-  @retval EFI_NOT_READY           The specified configuration data is not ready due to an already in 
+  @retval EFI_NOT_READY           The specified configuration data is not ready due to an already in
                                   progress asynchronous configuration process.
   @retval EFI_NOT_FOUND           The specified configuration data is not found.
 **/
@@ -251,19 +250,19 @@ EFI_STATUS
   );
 
 /**
-  Register an event that is to be signaled whenever a configuration process on the specified 
+  Register an event that is to be signaled whenever a configuration process on the specified
   configuration data is done.
 
-  This function registers an event that is to be signaled whenever a configuration process on the 
+  This function registers an event that is to be signaled whenever a configuration process on the
   specified configuration data is done. An event can be registered for different DataType
-  simultaneously and the caller is responsible for determining which type of configuration data causes 
+  simultaneously and the caller is responsible for determining which type of configuration data causes
   the signaling of the event in such case.
 
-  @param[in]   This               Pointer to the EFI_IP4_CONFIG2_PROTOCOL instance.       
+  @param[in]   This               Pointer to the EFI_IP4_CONFIG2_PROTOCOL instance.
   @param[in]   DataType           The type of data to unregister the event for.
   @param[in]   Event              The event to register.
 
-  @retval EFI_SUCCESS             The notification event for the specified configuration data is 
+  @retval EFI_SUCCESS             The notification event for the specified configuration data is
                                   registered.
   @retval EFI_INVALID_PARAMETER   This is NULL or Event is NULL.
   @retval EFI_UNSUPPORTED         The configuration data type specified by DataType is not supported.
@@ -283,7 +282,7 @@ EFI_STATUS
 
   This function removes a previously registeredevent for the specified configuration data.
 
-  @param[in]   This               Pointer to the EFI_IP4_CONFIG2_PROTOCOL instance.       
+  @param[in]   This               Pointer to the EFI_IP4_CONFIG2_PROTOCOL instance.
   @param[in]   DataType           The type of data to remove the previously registered event for.
   @param[in]   Event              The event to unregister.
 
@@ -300,9 +299,9 @@ EFI_STATUS
   );
 
 ///
-/// The EFI_IP4_CONFIG2_PROTOCOL is designed to be the central repository for the common 
+/// The EFI_IP4_CONFIG2_PROTOCOL is designed to be the central repository for the common
 /// configurations and the administrator configurable settings for the EFI IPv4 network stack.
-/// An EFI IPv4 Configuration II Protocol instance will be installed on each communication device that 
+/// An EFI IPv4 Configuration II Protocol instance will be installed on each communication device that
 /// the EFI IPv4 network stack runs on.
 ///
 struct _EFI_IP4_CONFIG2_PROTOCOL {
diff --git a/MdePkg/Include/Protocol/Ip6.h b/MdePkg/Include/Protocol/Ip6.h
index 1598f8250a87..c82f36501d22 100644
--- a/MdePkg/Include/Protocol/Ip6.h
+++ b/MdePkg/Include/Protocol/Ip6.h
@@ -11,13 +11,7 @@
   Message Protocol (ICMPv6).
 
   Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This Protocol is introduced in UEFI Specification 2.2
diff --git a/MdePkg/Include/Protocol/Ip6Config.h b/MdePkg/Include/Protocol/Ip6Config.h
index dd4facb897c5..fe93ba24e8bc 100644
--- a/MdePkg/Include/Protocol/Ip6Config.h
+++ b/MdePkg/Include/Protocol/Ip6Config.h
@@ -2,14 +2,8 @@
   This file provides a definition of the EFI IPv6 Configuration
   Protocol.
 
-Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at<BR>
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 #ifndef __EFI_IP6CONFIG_PROTOCOL_H__
@@ -27,65 +21,71 @@ typedef struct _EFI_IP6_CONFIG_PROTOCOL EFI_IP6_CONFIG_PROTOCOL;
 ///
 /// EFI_IP6_CONFIG_DATA_TYPE
 ///
-typedef enum {         
-  /// 
-  /// The interface information of the communication 
-  /// device this EFI IPv6 Configuration Protocol instance manages. 
-  /// This type of data is read only.The corresponding Data is of type 
+typedef enum {
+  ///
+  /// The interface information of the communication
+  /// device this EFI IPv6 Configuration Protocol instance manages.
+  /// This type of data is read only.The corresponding Data is of type
   /// EFI_IP6_CONFIG_INTERFACE_INFO.
-  /// 
+  ///
   Ip6ConfigDataTypeInterfaceInfo,
-  /// 
-  /// The alternative interface ID for the 
-  /// communication device this EFI IPv6 Configuration Protocol 
-  /// instance manages if the link local IPv6 address generated from 
-  /// the interfaced ID based on the default source the EFI IPv6 
-  /// Protocol uses is a duplicate address. The length of the interface 
-  /// ID is 64 bit. The corresponding Data is of type 
+  ///
+  /// The alternative interface ID for the
+  /// communication device this EFI IPv6 Configuration Protocol
+  /// instance manages if the link local IPv6 address generated from
+  /// the interfaced ID based on the default source the EFI IPv6
+  /// Protocol uses is a duplicate address. The length of the interface
+  /// ID is 64 bit. The corresponding Data is of type
   /// EFI_IP6_CONFIG_INTERFACE_ID.
-  /// 
+  ///
   Ip6ConfigDataTypeAltInterfaceId,
-  /// 
-  /// The general configuration policy for the EFI IPv6 network 
-  /// stack running on the communication device this EFI IPv6 
-  /// Configuration Protocol instance manages. The policy will affect 
-  /// other configuration settings. The corresponding Data is of type 
+  ///
+  /// The general configuration policy for the EFI IPv6 network
+  /// stack running on the communication device this EFI IPv6
+  /// Configuration Protocol instance manages. The policy will affect
+  /// other configuration settings. The corresponding Data is of type
   /// EFI_IP6_CONFIG_POLICY.
   ///
   Ip6ConfigDataTypePolicy,
-  /// 
-  /// The number of consecutive 
-  /// Neighbor Solicitation messages sent while performing Duplicate 
-  /// Address Detection on a tentative address. A value of zero 
-  /// indicates that Duplicate Address Detection will not be performed 
-  /// on tentative addresses. The corresponding Data is of type 
+  ///
+  /// The number of consecutive
+  /// Neighbor Solicitation messages sent while performing Duplicate
+  /// Address Detection on a tentative address. A value of zero
+  /// indicates that Duplicate Address Detection will not be performed
+  /// on tentative addresses. The corresponding Data is of type
   /// EFI_IP6_CONFIG_DUP_ADDR_DETECT_TRANSMITS.
-  /// 
+  ///
   Ip6ConfigDataTypeDupAddrDetectTransmits,
-  /// 
-  /// The station addresses set manually for the EFI 
-  /// IPv6 network stack. It is only configurable when the policy is 
-  /// Ip6ConfigPolicyManual. The corresponding Data is a 
-  /// pointer to an array of EFI_IPv6_ADDRESS instances.
-  /// 
+  ///
+  /// The station addresses set manually for the EFI
+  /// IPv6 network stack. It is only configurable when the policy is
+  /// Ip6ConfigPolicyManual. The corresponding Data is a
+  /// pointer to an array of EFI_IPv6_ADDRESS instances. When
+  /// DataSize is 0 and Data is NULL, the existing configuration
+  /// is cleared from the EFI IPv6 Configuration Protocol instance.
+  ///
   Ip6ConfigDataTypeManualAddress,
-  /// 
-  /// The gateway addresses set manually for the EFI IPv6 
-  /// network stack running on the communication device this EFI 
-  /// IPv6 Configuration Protocol manages. It is not configurable when 
-  /// the policy is Ip6ConfigPolicyAutomatic. The gateway 
-  /// addresses must be unicast IPv6 addresses. The corresponding 
+  ///
+  /// The gateway addresses set manually for the EFI IPv6
+  /// network stack running on the communication device this EFI
+  /// IPv6 Configuration Protocol manages. It is not configurable when
+  /// the policy is Ip6ConfigPolicyAutomatic. The gateway
+  /// addresses must be unicast IPv6 addresses. The corresponding
   /// Data is a pointer to an array of EFI_IPv6_ADDRESS instances.
-  /// 
+  /// When DataSize is 0 and Data is NULL, the existing configuration
+  /// is cleared from the EFI IPv6 Configuration Protocol instance.
+  ///
   Ip6ConfigDataTypeGateway,
-  /// 
-  /// The DNS server list for the EFI IPv6 network stack 
-  /// running on the communication device this EFI IPv6 
-  /// Configuration Protocol manages. It is not configurable when the 
-  /// policy is Ip6ConfigPolicyAutomatic.The DNS server 
-  /// addresses must be unicast IPv6 addresses. The corresponding 
+  ///
+  /// The DNS server list for the EFI IPv6 network stack
+  /// running on the communication device this EFI IPv6
+  /// Configuration Protocol manages. It is not configurable when the
+  /// policy is Ip6ConfigPolicyAutomatic.The DNS server
+  /// addresses must be unicast IPv6 addresses. The corresponding
   /// Data is a pointer to an array of EFI_IPv6_ADDRESS instances.
-  /// 
+  /// When DataSize is 0 and Data is NULL, the existing configuration
+  /// is cleared from the EFI IPv6 Configuration Protocol instance.
+  ///
   Ip6ConfigDataTypeDnsServer,
   ///
   /// The number of this enumeration memebers.
@@ -95,7 +95,7 @@ typedef enum {
 
 ///
 /// EFI_IP6_CONFIG_INTERFACE_INFO
-/// describes the operational state of the interface this 
+/// describes the operational state of the interface this
 /// EFI IPv6 Configuration Protocol instance manages.
 ///
 typedef struct {
@@ -103,37 +103,37 @@ typedef struct {
   /// The name of the interface. It is a NULL-terminated string.
   ///
   CHAR16                Name[32];
-  /// 
+  ///
   /// The interface type of the network interface.
-  /// 
+  ///
   UINT8                 IfType;
-  /// 
+  ///
   /// The size, in bytes, of the network interface's hardware address.
-  /// 
+  ///
   UINT32                HwAddressSize;
-  /// 
+  ///
   /// The hardware address for the network interface.
-  /// 
+  ///
   EFI_MAC_ADDRESS       HwAddress;
-  /// 
+  ///
   /// Number of EFI_IP6_ADDRESS_INFO structures pointed to by AddressInfo.
-  /// 
+  ///
   UINT32                AddressInfoCount;
-  /// 
-  /// Pointer to an array of EFI_IP6_ADDRESS_INFO instances 
-  /// which contain the local IPv6 addresses and the corresponding 
-  /// prefix length information. Set to NULL if AddressInfoCount 
+  ///
+  /// Pointer to an array of EFI_IP6_ADDRESS_INFO instances
+  /// which contain the local IPv6 addresses and the corresponding
+  /// prefix length information. Set to NULL if AddressInfoCount
   /// is zero.
-  /// 
+  ///
   EFI_IP6_ADDRESS_INFO  *AddressInfo;
-  /// 
+  ///
   /// Number of route table entries in the following RouteTable.
-  /// 
+  ///
   UINT32                RouteCount;
-  /// 
-  /// The route table of the IPv6 network stack runs on this interface. 
-  /// Set to NULL if RouteCount is zero. 
-  /// 
+  ///
+  /// The route table of the IPv6 network stack runs on this interface.
+  /// Set to NULL if RouteCount is zero.
+  ///
   EFI_IP6_ROUTE_TABLE   *RouteTable;
 } EFI_IP6_CONFIG_INTERFACE_INFO;
 
@@ -147,42 +147,42 @@ typedef struct {
 
 ///
 /// EFI_IP6_CONFIG_POLICY
-/// defines the general configuration policy the EFI IPv6 
+/// defines the general configuration policy the EFI IPv6
 /// Configuration Protocol supports.
 ///
 typedef enum {
   ///
-  /// Under this policy, the IpI6ConfigDataTypeManualAddress, 
+  /// Under this policy, the IpI6ConfigDataTypeManualAddress,
   /// Ip6ConfigDataTypeGateway and Ip6ConfigDataTypeDnsServer
-  /// configuration data are required to be set manually. 
+  /// configuration data are required to be set manually.
   /// The EFI IPv6 Protocol will get all required configuration
   /// such as address, prefix and gateway settings from the EFI
   /// IPv6 Configuration protocol.
   ///
-  Ip6ConfigPolicyManual,      
-  /// 
-  /// Under this policy, the IpI6ConfigDataTypeManualAddress, 
+  Ip6ConfigPolicyManual,
+  ///
+  /// Under this policy, the IpI6ConfigDataTypeManualAddress,
   /// Ip6ConfigDataTypeGateway and Ip6ConfigDataTypeDnsServer
   /// configuration data are not allowed to set via SetData().
   /// All of these configurations are retrieved from some auto
-  /// configuration mechanism. 
-  /// The EFI IPv6 Protocol will use the IPv6 stateless address 
-  /// autoconfiguration mechanism and/or the IPv6 stateful address 
-  /// autoconfiguration mechanism described in the related RFCs to 
+  /// configuration mechanism.
+  /// The EFI IPv6 Protocol will use the IPv6 stateless address
+  /// autoconfiguration mechanism and/or the IPv6 stateful address
+  /// autoconfiguration mechanism described in the related RFCs to
   /// get address and other configuration information
-  /// 
+  ///
   Ip6ConfigPolicyAutomatic
 } EFI_IP6_CONFIG_POLICY;
 
 ///
 /// EFI_IP6_CONFIG_DUP_ADDR_DETECT_TRANSMITS
 /// describes the number of consecutive Neighbor Solicitation messages sent
-/// while performing Duplicate Address Detection on a tentative address. 
+/// while performing Duplicate Address Detection on a tentative address.
 /// The default value for a newly detected communication device is 1.
 ///
 typedef struct {
   UINT32    DupAddrDetectTransmits;  ///< The number of consecutive Neighbor Solicitation messages sent.
-} EFI_IP6_CONFIG_DUP_ADDR_DETECT_TRANSMITS;           
+} EFI_IP6_CONFIG_DUP_ADDR_DETECT_TRANSMITS;
 
 ///
 /// EFI_IP6_CONFIG_MANUAL_ADDRESS
@@ -199,50 +199,49 @@ typedef struct {
 /**
   Set the configuration for the EFI IPv6 network stack running on the communication
   device this EFI IPv6 Configuration Protocol instance manages.
-  
-  This function is used to set the configuration data of type DataType for the EFI 
+
+  This function is used to set the configuration data of type DataType for the EFI
   IPv6 network stack running on the communication device this EFI IPv6 Configuration
   Protocol instance manages.
 
-  The DataSize is used to calculate the count of structure instances in the Data for 
+  The DataSize is used to calculate the count of structure instances in the Data for
   some DataType that multiple structure instances are allowed.
-  
+
   This function is always non-blocking. When setting some type of configuration data,
-  an asynchronous process is invoked to check the correctness of the data, such as 
-  doing Duplicate Address Detection on the manually set local IPv6 addresses. 
+  an asynchronous process is invoked to check the correctness of the data, such as
+  doing Duplicate Address Detection on the manually set local IPv6 addresses.
   EFI_NOT_READY is returned immediately to indicate that such an asynchronous process
   is invoked and the process is not finished yet. The caller willing to get the result
   of the asynchronous process is required to call RegisterDataNotify() to register an
-  event on the specified configuration data. Once the event is signaled, the caller 
+  event on the specified configuration data. Once the event is signaled, the caller
   can call GetData() to get back the configuration data in order to know the result.
-  For other types of configuration data that do not require an asynchronous configuration 
+  For other types of configuration data that do not require an asynchronous configuration
   process, the result of the operation is immediately returned.
 
   @param[in]     This           Pointer to the EFI_IP6_CONFIG_PROTOCOL instance.
-  @param[in]     DataType       The type of data to set.  
+  @param[in]     DataType       The type of data to set.
   @param[in]     DataSize       Size of the buffer pointed to by Data in bytes.
   @param[in]     Data           The data buffer to set. The type of the data buffer is
                                 associated with the DataType.
-  
-  @retval EFI_SUCCESS           The specified configuration data for the EFI IPv6 
+
+  @retval EFI_SUCCESS           The specified configuration data for the EFI IPv6
                                 network stack is set successfully.
   @retval EFI_INVALID_PARAMETER One or more of the following are TRUE:
                                 - This is NULL.
-                                - Data is NULL.
-                                - One or more fields in Data do not match the requirement of the 
-                                  data type indicated by DataType. 
-  @retval EFI_WRITE_PROTECTED   The specified configuration data is read-only or the specified 
+                                - One or more fields in Data and DataSize do not match the
+                                  requirement of the data type indicated by DataType.
+  @retval EFI_WRITE_PROTECTED   The specified configuration data is read-only or the specified
                                 configuration data can not be set under the current policy
-  @retval EFI_ACCESS_DENIED     Another set operation on the specified configuration 
+  @retval EFI_ACCESS_DENIED     Another set operation on the specified configuration
                                 data is already in process.
   @retval EFI_NOT_READY         An asynchronous process is invoked to set the specified
                                 configuration data and the process is not finished yet.
-  @retval EFI_BAD_BUFFER_SIZE   The DataSize does not match the size of the type 
+  @retval EFI_BAD_BUFFER_SIZE   The DataSize does not match the size of the type
                                 indicated by DataType.
   @retval EFI_UNSUPPORTED       This DataType is not supported.
   @retval EFI_OUT_OF_RESOURCES  Required system resources could not be allocated.
   @retval EFI_DEVICE_ERROR      An unexpected system error or network error occurred.
-  
+
 **/
 typedef
 EFI_STATUS
@@ -256,39 +255,39 @@ EFI_STATUS
 /**
   Get the configuration data for the EFI IPv6 network stack running on the communication
   device this EFI IPv6 Configuration Protocol instance manages.
-  
+
   This function returns the configuration data of type DataType for the EFI IPv6 network
   stack running on the communication device this EFI IPv6 Configuration Protocol instance
   manages.
 
   The caller is responsible for allocating the buffer used to return the specified
   configuration data and the required size will be returned to the caller if the size of
-  the buffer is too small. 
-  
-  EFI_NOT_READY is returned if the specified configuration data is not ready due to an 
+  the buffer is too small.
+
+  EFI_NOT_READY is returned if the specified configuration data is not ready due to an
   already in progress asynchronous configuration process. The caller can call RegisterDataNotify()
   to register an event on the specified configuration data. Once the asynchronous configuration
-  process is finished, the event will be signaled and a subsequent GetData() call will return 
+  process is finished, the event will be signaled and a subsequent GetData() call will return
   the specified configuration data.
 
   @param[in]     This           Pointer to the EFI_IP6_CONFIG_PROTOCOL instance.
-  @param[in]     DataType       The type of data to get.  
-  @param[in,out] DataSize       On input, in bytes, the size of Data. On output, in bytes, the 
+  @param[in]     DataType       The type of data to get.
+  @param[in,out] DataSize       On input, in bytes, the size of Data. On output, in bytes, the
                                 size of buffer required to store the specified configuration data.
-  @param[in]     Data           The data buffer in which the configuration data is returned. The 
+  @param[in]     Data           The data buffer in which the configuration data is returned. The
                                 type of the data buffer is associated with the DataType.
-  
+
   @retval EFI_SUCCESS           The specified configuration data is got successfully.
   @retval EFI_INVALID_PARAMETER One or more of the followings are TRUE:
                                 - This is NULL.
                                 - DataSize is NULL.
                                 - Data is NULL if *DataSize is not zero.
-  @retval EFI_BUFFER_TOO_SMALL  The size of Data is too small for the specified configuration data 
+  @retval EFI_BUFFER_TOO_SMALL  The size of Data is too small for the specified configuration data
                                 and the required size is returned in DataSize.
-  @retval EFI_NOT_READY         The specified configuration data is not ready due to an already in 
+  @retval EFI_NOT_READY         The specified configuration data is not ready due to an already in
                                 progress asynchronous configuration process.
   @retval EFI_NOT_FOUND         The specified configuration data is not found.
-  
+
 **/
 typedef
 EFI_STATUS
@@ -302,24 +301,24 @@ EFI_STATUS
 /**
   Register an event that is to be signaled whenever a configuration process on the specified
   configuration data is done.
-  
+
   This function registers an event that is to be signaled whenever a configuration process
   on the specified configuration data is done. An event can be registered for different DataType
   simultaneously and the caller is responsible for determining which type of configuration data
   causes the signaling of the event in such case.
 
   @param[in]     This           Pointer to the EFI_IP6_CONFIG_PROTOCOL instance.
-  @param[in]     DataType       The type of data to unregister the event for.  
-  @param[in]     Event          The event to register. 
-  
-  @retval EFI_SUCCESS           The notification event for the specified configuration data is 
+  @param[in]     DataType       The type of data to unregister the event for.
+  @param[in]     Event          The event to register.
+
+  @retval EFI_SUCCESS           The notification event for the specified configuration data is
                                 registered.
   @retval EFI_INVALID_PARAMETER This is NULL or Event is NULL.
-  @retval EFI_UNSUPPORTED       The configuration data type specified by DataType is not 
+  @retval EFI_UNSUPPORTED       The configuration data type specified by DataType is not
                                 supported.
   @retval EFI_OUT_OF_RESOURCES  Required system resources could not be allocated.
   @retval EFI_ACCESS_DENIED     The Event is already registered for the DataType.
-  
+
 **/
 typedef
 EFI_STATUS
@@ -331,18 +330,18 @@ EFI_STATUS
 
 /**
   Remove a previously registered event for the specified configuration data.
-  
+
   This function removes a previously registered event for the specified configuration data.
 
   @param[in]     This           Pointer to the EFI_IP6_CONFIG_PROTOCOL instance.
-  @param[in]     DataType       The type of data to remove the previously registered event for.  
+  @param[in]     DataType       The type of data to remove the previously registered event for.
   @param[in]     Event          The event to unregister.
-  
+
   @retval EFI_SUCCESS           The event registered for the specified configuration data is removed.
   @retval EFI_INVALID_PARAMETER This is NULL or Event is NULL.
-  @retval EFI_NOT_FOUND         The Event has not been registered for the specified 
+  @retval EFI_NOT_FOUND         The Event has not been registered for the specified
                                 DataType.
-  
+
 **/
 typedef
 EFI_STATUS
diff --git a/MdePkg/Include/Protocol/IpSec.h b/MdePkg/Include/Protocol/IpSec.h
index a22326309ca0..b51936c49068 100644
--- a/MdePkg/Include/Protocol/IpSec.h
+++ b/MdePkg/Include/Protocol/IpSec.h
@@ -1,25 +1,19 @@
 /** @file
   EFI IPSEC Protocol Definition
   The EFI_IPSEC_PROTOCOL is used to abstract the ability to deal with the individual
-  packets sent and received by the host and provide packet-level security for IP 
+  packets sent and received by the host and provide packet-level security for IP
   datagram.
   The EFI_IPSEC2_PROTOCOL is used to abstract the ability to deal with the individual
-  packets sent and received by the host and provide packet-level security for IP 
-  datagram. In addition, it supports the Option (extension header) processing in 
-  IPsec which doesn't support in EFI_IPSEC_PROTOCOL. It is also recommended to 
-  use EFI_IPSEC2_PROTOCOL instead of EFI_IPSEC_PROTOCOL especially for IPsec Tunnel 
+  packets sent and received by the host and provide packet-level security for IP
+  datagram. In addition, it supports the Option (extension header) processing in
+  IPsec which doesn't support in EFI_IPSEC_PROTOCOL. It is also recommended to
+  use EFI_IPSEC2_PROTOCOL instead of EFI_IPSEC_PROTOCOL especially for IPsec Tunnel
   Mode.
 
-  Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
+  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-  @par Revision Reference:          
+  @par Revision Reference:
   The EFI_IPSEC2_PROTOCOL is introduced in UEFI Specification 2.3D.
 
 **/
@@ -43,34 +37,34 @@ typedef struct _EFI_IPSEC_PROTOCOL  EFI_IPSEC_PROTOCOL;
 typedef struct _EFI_IPSEC2_PROTOCOL EFI_IPSEC2_PROTOCOL;
 
 ///
-/// EFI_IPSEC_FRAGMENT_DATA 
+/// EFI_IPSEC_FRAGMENT_DATA
 /// defines the instances of packet fragments.
 ///
-typedef struct _EFI_IPSEC_FRAGMENT_DATA { 
+typedef struct _EFI_IPSEC_FRAGMENT_DATA {
   UINT32  FragmentLength;
   VOID    *FragmentBuffer;
-} EFI_IPSEC_FRAGMENT_DATA; 
+} EFI_IPSEC_FRAGMENT_DATA;
 
 
 /**
-  Handles IPsec packet processing for inbound and outbound IP packets. 
+  Handles IPsec packet processing for inbound and outbound IP packets.
 
   The EFI_IPSEC_PROCESS process routine handles each inbound or outbound packet.
-  The behavior is that it can perform one of the following actions: 
-  bypass the packet, discard the packet, or protect the packet.       
+  The behavior is that it can perform one of the following actions:
+  bypass the packet, discard the packet, or protect the packet.
 
   @param[in]      This             Pointer to the EFI_IPSEC_PROTOCOL instance.
   @param[in]      NicHandle        Instance of the network interface.
   @param[in]      IpVer            IPV4 or IPV6.
   @param[in, out] IpHead           Pointer to the IP Header.
   @param[in]      LastHead         The protocol of the next layer to be processed by IPsec.
-  @param[in]      OptionsBuffer    Pointer to the options buffer. 
+  @param[in]      OptionsBuffer    Pointer to the options buffer.
   @param[in]      OptionsLength    Length of the options buffer.
-  @param[in, out] FragmentTable    Pointer to a list of fragments. 
+  @param[in, out] FragmentTable    Pointer to a list of fragments.
   @param[in]      FragmentCount    Number of fragments.
   @param[in]      TrafficDirection Traffic direction.
   @param[out]     RecycleSignal    Event for recycling of resources.
- 
+
   @retval EFI_SUCCESS              The packet was bypassed and all buffers remain the same.
   @retval EFI_SUCCESS              The packet was protected.
   @retval EFI_ACCESS_DENIED        The packet was discarded.
@@ -93,9 +87,9 @@ EFI_STATUS
   );
 
 ///
-/// EFI_IPSEC_PROTOCOL 
+/// EFI_IPSEC_PROTOCOL
 /// provides the ability for  securing IP communications by authenticating
-/// and/or encrypting each IP packet in a data stream. 
+/// and/or encrypting each IP packet in a data stream.
 //  EFI_IPSEC_PROTOCOL can be consumed by both the IPv4 and IPv6 stack.
 //  A user can employ this protocol for IPsec package handling in both IPv4
 //  and IPv6 environment.
@@ -107,72 +101,72 @@ struct _EFI_IPSEC_PROTOCOL {
 };
 
 /**
-  Handles IPsec processing for both inbound and outbound IP packets. Compare with 
-  Process() in EFI_IPSEC_PROTOCOL, this interface has the capability to process 
-  Option(Extension Header). 
+  Handles IPsec processing for both inbound and outbound IP packets. Compare with
+  Process() in EFI_IPSEC_PROTOCOL, this interface has the capability to process
+  Option(Extension Header).
 
   The EFI_IPSEC2_PROCESS process routine handles each inbound or outbound packet.
-  The behavior is that it can perform one of the following actions: 
-  bypass the packet, discard the packet, or protect the packet.  
+  The behavior is that it can perform one of the following actions:
+  bypass the packet, discard the packet, or protect the packet.
 
   @param[in]       This               Pointer to the EFI_IPSEC2_PROTOCOL instance.
-  @param[in]       NicHandle          Instance of the network interface. 
+  @param[in]       NicHandle          Instance of the network interface.
   @param[in]       IpVer              IP version.IPv4 or IPv6.
-  @param[in, out]  IpHead             Pointer to the IP Header it is either 
+  @param[in, out]  IpHead             Pointer to the IP Header it is either
                                       the EFI_IP4_HEADER or EFI_IP6_HEADER.
-                                      On input, it contains the IP header. 
-                                      On output, 1) in tunnel mode and the 
-                                      traffic direction is inbound, the buffer 
-                                      will be reset to zero by IPsec; 2) in 
-                                      tunnel mode and the traffic direction 
-                                      is outbound, the buffer will reset to 
-                                      be the tunnel IP header.3) in transport 
-                                      mode, the related fielders (like payload 
-                                      length, Next header) in IP header will 
+                                      On input, it contains the IP header.
+                                      On output, 1) in tunnel mode and the
+                                      traffic direction is inbound, the buffer
+                                      will be reset to zero by IPsec; 2) in
+                                      tunnel mode and the traffic direction
+                                      is outbound, the buffer will reset to
+                                      be the tunnel IP header.3) in transport
+                                      mode, the related fielders (like payload
+                                      length, Next header) in IP header will
                                       be modified according to the condition.
   @param[in, out]  LastHead           For IP4, it is the next protocol in IP
-                                      header. For IP6 it is the Next Header 
+                                      header. For IP6 it is the Next Header
                                       of the last extension header.
-  @param[in, out]  OptionsBuffer      On input, it contains the options 
-                                      (extensions header) to be processed by 
+  @param[in, out]  OptionsBuffer      On input, it contains the options
+                                      (extensions header) to be processed by
                                       IPsec. On output, 1) in tunnel mode and
-                                      the traffic direction is outbound, it 
-                                      will be set to NULL, and that means this 
-                                      contents was wrapped after inner header 
-                                      and should not be concatenated after 
-                                      tunnel header again; 2) in transport 
-                                      mode and the traffic direction is inbound, 
-                                      if there are IP options (extension headers) 
-                                      protected by IPsec, IPsec will concatenate 
-                                      the those options after the input options 
-                                      (extension headers); 3) on other situations, 
-                                      the output of contents of OptionsBuffer 
-                                      might be same with input's. The caller 
-                                      should take the responsibility to free 
+                                      the traffic direction is outbound, it
+                                      will be set to NULL, and that means this
+                                      contents was wrapped after inner header
+                                      and should not be concatenated after
+                                      tunnel header again; 2) in transport
+                                      mode and the traffic direction is inbound,
+                                      if there are IP options (extension headers)
+                                      protected by IPsec, IPsec will concatenate
+                                      the those options after the input options
+                                      (extension headers); 3) on other situations,
+                                      the output of contents of OptionsBuffer
+                                      might be same with input's. The caller
+                                      should take the responsibility to free
                                       the buffer both on input and on output.
-  @param[in, out]  OptionsLength      On input, the input length of the options 
-                                      buffer. On output, the output length of 
+  @param[in, out]  OptionsLength      On input, the input length of the options
+                                      buffer. On output, the output length of
                                       the options buffer.
-  @param[in, out]  FragmentTable      Pointer to a list of fragments. On input, 
-                                      these fragments contain the IP payload. 
-                                      On output, 1) in tunnel mode and the traffic 
-                                      direction is inbound, the fragments contain 
-                                      the whole IP payload which is from the 
-                                      IP inner header to the last byte of the 
-                                      packet; 2) in tunnel mode and the traffic 
-                                      direction is the outbound, the fragments 
-                                      contains the whole encapsulated payload 
-                                      which encapsulates the whole IP payload 
-                                      between the encapsulated header and 
-                                      encapsulated trailer fields. 3) in transport 
-                                      mode and the traffic direction is inbound, 
-                                      the fragments contains the IP payload 
-                                      which is from the next layer protocol to 
-                                      the last byte of the packet; 4) in transport 
-                                      mode and the traffic direction is outbound, 
-                                      the fragments contains the whole encapsulated 
-                                      payload which encapsulates the next layer 
-                                      protocol information between the encapsulated 
+  @param[in, out]  FragmentTable      Pointer to a list of fragments. On input,
+                                      these fragments contain the IP payload.
+                                      On output, 1) in tunnel mode and the traffic
+                                      direction is inbound, the fragments contain
+                                      the whole IP payload which is from the
+                                      IP inner header to the last byte of the
+                                      packet; 2) in tunnel mode and the traffic
+                                      direction is the outbound, the fragments
+                                      contains the whole encapsulated payload
+                                      which encapsulates the whole IP payload
+                                      between the encapsulated header and
+                                      encapsulated trailer fields. 3) in transport
+                                      mode and the traffic direction is inbound,
+                                      the fragments contains the IP payload
+                                      which is from the next layer protocol to
+                                      the last byte of the packet; 4) in transport
+                                      mode and the traffic direction is outbound,
+                                      the fragments contains the whole encapsulated
+                                      payload which encapsulates the next layer
+                                      protocol information between the encapsulated
                                       header and encapsulated trailer fields.
   @param[in, out]  FragmentCount      Number of fragments.
   @param[in]       TrafficDirection   Traffic direction.
@@ -180,7 +174,7 @@ struct _EFI_IPSEC_PROTOCOL {
 
   @retval      EFI_SUCCESS           The packet was processed by IPsec successfully.
   @retval      EFI_ACCESS_DENIED     The packet was discarded.
-  @retval      EFI_NOT_READY         The IKE negotiation is invoked and the packet 
+  @retval      EFI_NOT_READY         The IKE negotiation is invoked and the packet
                                      was discarded.
   @retval      EFI_INVALID_PARAMETER One or more of following are TRUE:
                                      If OptionsBuffer is NULL;
@@ -189,23 +183,23 @@ struct _EFI_IPSEC_PROTOCOL {
                                      If FragmentCount is NULL.
 
 **/
-typedef 
+typedef
 EFI_STATUS
-(EFIAPI *EFI_IPSEC_PROCESSEXT) ( 
-  IN EFI_IPSEC2_PROTOCOL         *This, 
-  IN EFI_HANDLE                  NicHandle, 
-  IN UINT8                       IpVer, 
-  IN OUT VOID                    *IpHead, 
-  IN OUT UINT8                   *LastHead, 
-  IN OUT VOID                    **OptionsBuffer, 
-  IN OUT UINT32                  *OptionsLength, 
-  IN OUT EFI_IPSEC_FRAGMENT_DATA **FragmentTable, 
-  IN OUT UINT32                  *FragmentCount, 
-  IN EFI_IPSEC_TRAFFIC_DIR       TrafficDirection, 
+(EFIAPI *EFI_IPSEC_PROCESSEXT) (
+  IN EFI_IPSEC2_PROTOCOL         *This,
+  IN EFI_HANDLE                  NicHandle,
+  IN UINT8                       IpVer,
+  IN OUT VOID                    *IpHead,
+  IN OUT UINT8                   *LastHead,
+  IN OUT VOID                    **OptionsBuffer,
+  IN OUT UINT32                  *OptionsLength,
+  IN OUT EFI_IPSEC_FRAGMENT_DATA **FragmentTable,
+  IN OUT UINT32                  *FragmentCount,
+  IN EFI_IPSEC_TRAFFIC_DIR       TrafficDirection,
      OUT EFI_EVENT               *RecycleSignal
   );
 
-/// 
+///
 /// EFI_IPSEC2_PROTOCOL
 /// supports the Option (extension header) processing in IPsec which doesn't support
 /// in EFI_IPSEC_PROTOCOL. It is also recommended to use EFI_IPSEC2_PROTOCOL instead
@@ -213,10 +207,10 @@ EFI_STATUS
 /// provides the ability for securing IP communications by authenticating and/or
 /// encrypting each IP packet in a data stream.
 ///
-struct _EFI_IPSEC2_PROTOCOL { 
+struct _EFI_IPSEC2_PROTOCOL {
 EFI_IPSEC_PROCESSEXT ProcessExt;
-EFI_EVENT            DisabledEvent; 
-BOOLEAN              DisabledFlag; 
+EFI_EVENT            DisabledEvent;
+BOOLEAN              DisabledFlag;
 };
 
 extern EFI_GUID gEfiIpSecProtocolGuid;
diff --git a/MdePkg/Include/Protocol/IpSecConfig.h b/MdePkg/Include/Protocol/IpSecConfig.h
index 4efc2e3d747a..78a201d4a47b 100644
--- a/MdePkg/Include/Protocol/IpSecConfig.h
+++ b/MdePkg/Include/Protocol/IpSecConfig.h
@@ -1,18 +1,12 @@
 /** @file
   EFI IPsec Configuration Protocol Definition
-  The EFI_IPSEC_CONFIG_PROTOCOL provides the mechanism to set and retrieve security and 
+  The EFI_IPSEC_CONFIG_PROTOCOL provides the mechanism to set and retrieve security and
   policy related information for the EFI IPsec protocol driver.
 
-  Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
+  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-  @par Revision Reference:          
+  @par Revision Reference:
   This Protocol is introduced in UEFI Specification 2.2
 
 **/
@@ -32,34 +26,34 @@ typedef struct _EFI_IPSEC_CONFIG_PROTOCOL EFI_IPSEC_CONFIG_PROTOCOL;
 /// EFI_IPSEC_CONFIG_DATA_TYPE
 ///
 typedef enum {
-  /// 
-  /// The IPsec Security Policy Database (aka SPD) setting.  In IPsec, 
-  /// an essential element of Security Association (SA) processing is 
-  /// underlying SPD that specifies what services are to be offered to 
-  /// IP datagram and in what fashion. The SPD must be consulted 
-  /// during the processing of all traffic (inbound and outbound), 
-  /// including traffic not protected by IPsec, that traverses the IPsec 
-  /// boundary. With this DataType, SetData() function is to set 
-  /// the SPD entry information, which may add one new entry, delete 
-  /// one existed entry or flush the whole database according to the 
-  /// parameter values. The corresponding Data is of type 
+  ///
+  /// The IPsec Security Policy Database (aka SPD) setting.  In IPsec,
+  /// an essential element of Security Association (SA) processing is
+  /// underlying SPD that specifies what services are to be offered to
+  /// IP datagram and in what fashion. The SPD must be consulted
+  /// during the processing of all traffic (inbound and outbound),
+  /// including traffic not protected by IPsec, that traverses the IPsec
+  /// boundary. With this DataType, SetData() function is to set
+  /// the SPD entry information, which may add one new entry, delete
+  /// one existed entry or flush the whole database according to the
+  /// parameter values. The corresponding Data is of type
   /// EFI_IPSEC_SPD_DATA
-  /// 
+  ///
   IPsecConfigDataTypeSpd,
-  /// 
-  /// The IPsec Security Association Database (aka SAD) setting. A 
-  /// SA is a simplex connection that affords security services to the 
-  /// traffic carried by it. Security services are afforded to an SA by the 
-  /// use of AH, or ESP, but not both. The corresponding Data is of 
+  ///
+  /// The IPsec Security Association Database (aka SAD) setting. A
+  /// SA is a simplex connection that affords security services to the
+  /// traffic carried by it. Security services are afforded to an SA by the
+  /// use of AH, or ESP, but not both. The corresponding Data is of
   /// type EFI_IPSEC_SAD_DATA.
-  /// 
+  ///
   IPsecConfigDataTypeSad,
-  /// 
-  /// The IPsec Peer Authorization Database (aka PAD) setting, which 
-  /// provides the link between the SPD and a security association 
-  /// management protocol. The PAD entry specifies the 
-  /// authentication protocol (e.g. IKEv1, IKEv2) method used and the 
-  /// authentication data. The corresponding Data is of type 
+  ///
+  /// The IPsec Peer Authorization Database (aka PAD) setting, which
+  /// provides the link between the SPD and a security association
+  /// management protocol. The PAD entry specifies the
+  /// authentication protocol (e.g. IKEv1, IKEv2) method used and the
+  /// authentication data. The corresponding Data is of type
   /// EFI_IPSEC_PAD_DATA.
   ///
   IPsecConfigDataTypePad,
@@ -79,70 +73,70 @@ typedef struct _EFI_IP_ADDRESS_INFO {
 /// EFI_IPSEC_SPD_SELECTOR
 ///
 typedef struct _EFI_IPSEC_SPD_SELECTOR {
-  /// 
+  ///
   /// Specifies the actual number of entries in LocalAddress.
-  /// 
+  ///
   UINT32                          LocalAddressCount;
-  /// 
-  /// A list of ranges of IPv4 or IPv6 addresses, which refers to the 
+  ///
+  /// A list of ranges of IPv4 or IPv6 addresses, which refers to the
   /// addresses being protected by IPsec policy.
-  /// 
+  ///
   EFI_IP_ADDRESS_INFO             *LocalAddress;
-  /// 
+  ///
   /// Specifies the actual number of entries in RemoteAddress.
-  /// 
+  ///
   UINT32                          RemoteAddressCount;
-  /// 
-  /// A list of ranges of IPv4 or IPv6 addresses, which are peer entities 
-  /// to LocalAddress. 
-  /// 
+  ///
+  /// A list of ranges of IPv4 or IPv6 addresses, which are peer entities
+  /// to LocalAddress.
+  ///
   EFI_IP_ADDRESS_INFO             *RemoteAddress;
-  /// 
-  /// Next layer protocol. Obtained from the IPv4 Protocol or the IPv6 
-  /// Next Header fields. The next layer protocol is whatever comes 
-  /// after any IP extension headers that are present. A zero value is a 
+  ///
+  /// Next layer protocol. Obtained from the IPv4 Protocol or the IPv6
+  /// Next Header fields. The next layer protocol is whatever comes
+  /// after any IP extension headers that are present. A zero value is a
   /// wildcard that matches any value in NextLayerProtocol field.
-  /// 
-  UINT16                          NextLayerProtocol; 
-  /// 
-  /// Local Port if the Next Layer Protocol uses two ports (as do TCP, 
-  /// UDP, and others). A zero value is a wildcard that matches any 
+  ///
+  UINT16                          NextLayerProtocol;
+  ///
+  /// Local Port if the Next Layer Protocol uses two ports (as do TCP,
+  /// UDP, and others). A zero value is a wildcard that matches any
   /// value in LocalPort field.
-  /// 
+  ///
   UINT16                          LocalPort;
-  /// 
-  /// A designed port range size. The start port is LocalPort, and 
-  /// the total number of ports is described by LocalPortRange. 
-  /// This field is ignored if NextLayerProtocol does not use 
-  /// ports. 
-  /// 
+  ///
+  /// A designed port range size. The start port is LocalPort, and
+  /// the total number of ports is described by LocalPortRange.
+  /// This field is ignored if NextLayerProtocol does not use
+  /// ports.
+  ///
   UINT16                          LocalPortRange;
-  /// 
-  /// Remote Port if the Next Layer Protocol uses two ports. A zero 
+  ///
+  /// Remote Port if the Next Layer Protocol uses two ports. A zero
   /// value is a wildcard that matches any value in RemotePort field.
-  /// 
+  ///
   UINT16                          RemotePort;
-  /// 
-  /// A designed port range size. The start port is RemotePort, and 
-  /// the total number of ports is described by RemotePortRange. 
+  ///
+  /// A designed port range size. The start port is RemotePort, and
+  /// the total number of ports is described by RemotePortRange.
   /// This field is ignored if NextLayerProtocol does not use ports.
-  /// 
+  ///
   UINT16                          RemotePortRange;
 } EFI_IPSEC_SPD_SELECTOR;
- 
+
 ///
 /// EFI_IPSEC_TRAFFIC_DIR
 /// represents the directionality in an SPD entry.
 ///
 typedef enum {
   ///
-  /// The EfiIPsecInBound refers to traffic entering an IPsec implementation via 
+  /// The EfiIPsecInBound refers to traffic entering an IPsec implementation via
   /// the unprotected interface or emitted by the implementation on the unprotected
-  /// side of the boundary and directed towards the protected interface. 
+  /// side of the boundary and directed towards the protected interface.
   ///
   EfiIPsecInBound,
   ///
-  /// The EfiIPsecOutBound refers to traffic entering the implementation via 
+  /// The EfiIPsecOutBound refers to traffic entering the implementation via
   /// the protected interface, or emitted by the implementation on the protected side
   /// of the boundary and directed toward the unprotected interface.
   ///
@@ -154,54 +148,54 @@ typedef enum {
 /// represents three possible processing choices.
 ///
 typedef enum {
-  /// 
+  ///
   /// Refers to traffic that is not allowed to traverse the IPsec boundary.
-  /// 
+  ///
   EfiIPsecActionDiscard,
-  /// 
-  /// Refers to traffic that is allowed to cross the IPsec boundary 
+  ///
+  /// Refers to traffic that is allowed to cross the IPsec boundary
   /// without protection.
-  /// 
+  ///
   EfiIPsecActionBypass,
-  /// 
-  /// Refers to traffic that is afforded IPsec protection, and for such 
-  /// traffic the SPD must specify the security protocols to be 
-  /// employed, their mode, security service options, and the 
-  /// cryptographic algorithms to be used. 
+  ///
+  /// Refers to traffic that is afforded IPsec protection, and for such
+  /// traffic the SPD must specify the security protocols to be
+  /// employed, their mode, security service options, and the
+  /// cryptographic algorithms to be used.
   ///
   EfiIPsecActionProtect
 } EFI_IPSEC_ACTION;
 
 ///
 /// EFI_IPSEC_SA_LIFETIME
-/// defines the lifetime of an SA, which represents when a SA must be 
-/// replaced or terminated. A value of all 0 for each field removes 
+/// defines the lifetime of an SA, which represents when a SA must be
+/// replaced or terminated. A value of all 0 for each field removes
 /// the limitation of a SA lifetime.
 ///
 typedef struct _EFI_IPSEC_SA_LIFETIME {
-  /// 
+  ///
   /// The number of bytes to which the IPsec cryptographic algorithm
   /// can be applied. For ESP, this is the encryption algorithm and for
-  /// AH, this is the authentication algorithm. The ByteCount 
+  /// AH, this is the authentication algorithm. The ByteCount
   /// includes pad bytes for cryptographic operations.
-  /// 
+  ///
   UINT64        ByteCount;
-  /// 
-  /// A time interval in second that warns the implementation to 
+  ///
+  /// A time interval in second that warns the implementation to
   /// initiate action such as setting up a replacement SA.
-  /// 
+  ///
   UINT64        SoftLifetime;
-  /// 
-  /// A time interval in second when the current SA ends and is 
+  ///
+  /// A time interval in second when the current SA ends and is
   /// destroyed.
-  /// 
+  ///
   UINT64        HardLifetime;
 } EFI_IPSEC_SA_LIFETIME;
 
 ///
 /// EFI_IPSEC_MODE
-/// There are two modes of IPsec operation: transport mode and tunnel mode. In 
-/// EfiIPsecTransport mode, AH and ESP provide protection primarily for next layer protocols; 
+/// There are two modes of IPsec operation: transport mode and tunnel mode. In
+/// EfiIPsecTransport mode, AH and ESP provide protection primarily for next layer protocols;
 /// In EfiIPsecTunnel mode, AH and ESP are applied to tunneled IP packets.
 ///
 typedef enum {
@@ -226,19 +220,19 @@ typedef enum {
 /// EFI_IPSEC_TUNNEL_OPTION
 ///
 typedef struct _EFI_IPSEC_TUNNEL_OPTION {
-  /// 
+  ///
   /// Local tunnel address when IPsec mode is EfiIPsecTunnel.
-  /// 
+  ///
   EFI_IP_ADDRESS              LocalTunnelAddress;
-  /// 
+  ///
   /// Remote tunnel address when IPsec mode is EfiIPsecTunnel.
-  /// 
+  ///
   EFI_IP_ADDRESS              RemoteTunnelAddress;
-  /// 
+  ///
   /// The option of copying the DF bit from an outbound package
-  /// to the tunnel mode header that it emits, when traffic is 
-  /// carried via a tunnel mode SA. 
-  /// 
+  /// to the tunnel mode header that it emits, when traffic is
+  /// carried via a tunnel mode SA.
+  ///
   EFI_IPSEC_TUNNEL_DF_OPTION  DF;
 } EFI_IPSEC_TUNNEL_OPTION;
 
@@ -247,7 +241,7 @@ typedef struct _EFI_IPSEC_TUNNEL_OPTION {
 ///
 typedef enum {
   EfiIPsecAH,  ///< IP Authentication Header protocol which is specified in RFC 4302.
-  EfiIPsecESP  ///< IP Encapsulating Security Payload which is specified in RFC 4303. 
+  EfiIPsecESP  ///< IP Encapsulating Security Payload which is specified in RFC 4303.
 } EFI_IPSEC_PROTOCOL_TYPE;
 
 ///
@@ -255,48 +249,48 @@ typedef enum {
 /// describes a policy list for traffic processing.
 ///
 typedef struct _EFI_IPSEC_PROCESS_POLICY {
-  /// 
-  /// Extended Sequence Number. Is this SA using extended sequence 
+  ///
+  /// Extended Sequence Number. Is this SA using extended sequence
   /// numbers. 64 bit counter is used if TRUE.
-  /// 
+  ///
   BOOLEAN                 ExtSeqNum;
-  /// 
-  /// A flag indicating whether overflow of the sequence number 
-  /// counter should generate an auditable event and prevent 
-  /// transmission of additional packets on the SA, or whether rollover 
+  ///
+  /// A flag indicating whether overflow of the sequence number
+  /// counter should generate an auditable event and prevent
+  /// transmission of additional packets on the SA, or whether rollover
   /// is permitted.
-  /// 
+  ///
   BOOLEAN                 SeqOverflow;
-  /// 
-  /// Is this SA using stateful fragment checking. TRUE represents 
+  ///
+  /// Is this SA using stateful fragment checking. TRUE represents
   /// stateful fragment checking.
-  /// 
+  ///
   BOOLEAN                 FragCheck;
-  /// 
-  /// A time interval after which a SA must be replaced with a new SA 
-  /// (and new SPI) or terminated. 
-  /// 
+  ///
+  /// A time interval after which a SA must be replaced with a new SA
+  /// (and new SPI) or terminated.
+  ///
   EFI_IPSEC_SA_LIFETIME   SaLifetime;
-  /// 
+  ///
   /// IPsec mode: tunnel or transport.
-  /// 
+  ///
   EFI_IPSEC_MODE          Mode;
-  /// 
+  ///
   /// Tunnel Option. TunnelOption is ignored if Mode is EfiIPsecTransport.
-  /// 
+  ///
   EFI_IPSEC_TUNNEL_OPTION *TunnelOption;
-  /// 
+  ///
   /// IPsec protocol: AH or ESP
-  /// 
+  ///
   EFI_IPSEC_PROTOCOL_TYPE Proto;
-  ///  
+  ///
   /// Cryptographic algorithm type used for authentication.
-  /// 
+  ///
   UINT8                   AuthAlgoId;
-  /// 
-  /// Cryptographic algorithm type used for encryption. EncAlgo is 
-  /// NULL when IPsec protocol is AH. For ESP protocol, EncAlgo 
-  /// can also be used to describe the algorithm if a combined mode 
+  ///
+  /// Cryptographic algorithm type used for encryption. EncAlgo is
+  /// NULL when IPsec protocol is AH. For ESP protocol, EncAlgo
+  /// can also be used to describe the algorithm if a combined mode
   /// algorithm is used.
   ///
   UINT8                   EncAlgoId;
@@ -307,19 +301,19 @@ typedef struct _EFI_IPSEC_PROCESS_POLICY {
 /// A triplet to identify an SA, consisting of the following members.
 ///
 typedef struct _EFI_IPSEC_SA_ID {
-  /// 
-  /// Security Parameter Index (aka SPI).  An arbitrary 32-bit value 
-  /// that is used by a receiver to identity the SA to which an incoming 
+  ///
+  /// Security Parameter Index (aka SPI).  An arbitrary 32-bit value
+  /// that is used by a receiver to identity the SA to which an incoming
   /// package should be bound.
-  /// 
+  ///
   UINT32                          Spi;
-  /// 
+  ///
   /// IPsec protocol: AH or ESP
-  /// 
+  ///
   EFI_IPSEC_PROTOCOL_TYPE         Proto;
-  /// 
-  /// Destination IP address. 
-  /// 
+  ///
+  /// Destination IP address.
+  ///
   EFI_IP_ADDRESS                  DestAddress;
 } EFI_IPSEC_SA_ID;
 
@@ -330,48 +324,48 @@ typedef struct _EFI_IPSEC_SA_ID {
 /// EFI_IPSEC_SPD_DATA
 ///
 typedef struct _EFI_IPSEC_SPD_DATA {
-  /// 
-  /// A null-terminated ASCII name string which is used as a symbolic 
+  ///
+  /// A null-terminated ASCII name string which is used as a symbolic
   /// identifier for an IPsec Local or Remote address.
-  /// 
+  ///
   UINT8                           Name[MAX_PEERID_LEN];
-  /// 
-  /// Bit-mapped list describing Populate from Packet flags. When 
-  /// creating a SA, if PackageFlag bit is set to TRUE, instantiate 
-  /// the selector from the corresponding field in the package that 
-  /// triggered the creation of the SA, else from the value(s) in the 
-  /// corresponding SPD entry. The PackageFlag bit setting for 
+  ///
+  /// Bit-mapped list describing Populate from Packet flags. When
+  /// creating a SA, if PackageFlag bit is set to TRUE, instantiate
+  /// the selector from the corresponding field in the package that
+  /// triggered the creation of the SA, else from the value(s) in the
+  /// corresponding SPD entry. The PackageFlag bit setting for
   /// corresponding selector field of EFI_IPSEC_SPD_SELECTOR:
-  ///     Bit 0: EFI_IPSEC_SPD_SELECTOR.LocalAddress 
-  ///     Bit 1: EFI_IPSEC_SPD_SELECTOR.RemoteAddress 
-  ///     Bit 2: 
-  /// EFI_IPSEC_SPD_SELECTOR.NextLayerProtocol 
-  ///     Bit 3: EFI_IPSEC_SPD_SELECTOR.LocalPort 
-  ///     Bit 4: EFI_IPSEC_SPD_SELECTOR.RemotePort 
+  ///     Bit 0: EFI_IPSEC_SPD_SELECTOR.LocalAddress
+  ///     Bit 1: EFI_IPSEC_SPD_SELECTOR.RemoteAddress
+  ///     Bit 2:
+  /// EFI_IPSEC_SPD_SELECTOR.NextLayerProtocol
+  ///     Bit 3: EFI_IPSEC_SPD_SELECTOR.LocalPort
+  ///     Bit 4: EFI_IPSEC_SPD_SELECTOR.RemotePort
   ///     Others: Reserved.
   ///
   UINT32                          PackageFlag;
-  /// 
+  ///
   /// The traffic direction of data gram.
-  /// 
+  ///
   EFI_IPSEC_TRAFFIC_DIR           TrafficDirection;
-  /// 
-  /// Processing choices to indicate which action is required by this 
-  /// policy. 
-  /// 
+  ///
+  /// Processing choices to indicate which action is required by this
+  /// policy.
+  ///
   EFI_IPSEC_ACTION                Action;
-  /// 
+  ///
   /// The policy and rule information for a SPD entry.
-  /// 
+  ///
   EFI_IPSEC_PROCESS_POLICY        *ProcessingPolicy;
-  /// 
+  ///
   /// Specifies the actual number of entries in SaId list.
-  /// 
+  ///
   UINTN                           SaIdCount;
-  /// 
-  /// The SAD entry used for the traffic processing. The 
+  ///
+  /// The SAD entry used for the traffic processing. The
   /// existed SAD entry links indicate this is the manual key case.
-  /// 
+  ///
   EFI_IPSEC_SA_ID                 SaId[1];
 } EFI_IPSEC_SPD_DATA;
 
@@ -389,9 +383,9 @@ typedef struct _EFI_IPSEC_AH_ALGO_INFO {
 ///
 /// EFI_IPSEC_ESP_ALGO_INFO
 /// The security algorithm selection for IPsec ESP encryption and authentication.
-/// The required authentication algorithm is specified in RFC 4305. 
-/// EncAlgoId fields can also specify an ESP combined mode algorithm 
-/// (e.g. AES with CCM mode, specified in RFC 4309), which provides both 
+/// The required authentication algorithm is specified in RFC 4305.
+/// EncAlgoId fields can also specify an ESP combined mode algorithm
+/// (e.g. AES with CCM mode, specified in RFC 4309), which provides both
 /// confidentiality and authentication services.
 ///
 typedef struct _EFI_IPSEC_ESP_ALGO_INFO {
@@ -415,40 +409,40 @@ typedef union {
 /// EFI_IPSEC_SA_DATA
 ///
 typedef struct _EFI_IPSEC_SA_DATA {
-  /// 
+  ///
   /// IPsec mode: tunnel or transport.
-  /// 
+  ///
   EFI_IPSEC_MODE                  Mode;
-  /// 
-  /// Sequence Number Counter. A 64-bit counter used to generate the 
+  ///
+  /// Sequence Number Counter. A 64-bit counter used to generate the
   /// sequence number field in AH or ESP headers.
-  /// 
+  ///
   UINT64                          SNCount;
-  /// 
-  /// Anti-Replay Window. A 64-bit counter and a bit-map used to 
+  ///
+  /// Anti-Replay Window. A 64-bit counter and a bit-map used to
   /// determine whether an inbound AH or ESP packet is a replay.
-  /// 
+  ///
   UINT8                           AntiReplayWindows;
-  /// 
-  /// AH/ESP cryptographic algorithm, key and parameters. 
-  /// 
+  ///
+  /// AH/ESP cryptographic algorithm, key and parameters.
+  ///
   EFI_IPSEC_ALGO_INFO             AlgoInfo;
-  /// 
-  /// Lifetime of this SA. 
-  /// 
+  ///
+  /// Lifetime of this SA.
+  ///
   EFI_IPSEC_SA_LIFETIME           SaLifetime;
-  /// 
-  /// Any observed path MTU and aging variables. The Path MTU 
+  ///
+  /// Any observed path MTU and aging variables. The Path MTU
   /// processing is defined in section 8 of RFC 4301.
-  /// 
+  ///
   UINT32                          PathMTU;
-  /// 
+  ///
   /// Link to one SPD entry.
-  /// 
+  ///
   EFI_IPSEC_SPD_SELECTOR          *SpdSelector;
-  /// 
-  /// Indication of whether it's manually set or negotiated automatically. 
-  /// If ManualSet is FALSE, the corresponding SA entry is inserted through 
+  ///
+  /// Indication of whether it's manually set or negotiated automatically.
+  /// If ManualSet is FALSE, the corresponding SA entry is inserted through
   /// IKE protocol negotiation.
   ///
   BOOLEAN                         ManualSet;
@@ -457,41 +451,41 @@ typedef struct _EFI_IPSEC_SA_DATA {
 ///
 /// EFI_IPSEC_SA_DATA2
 ///
-typedef struct _EFI_IPSEC_SA_DATA2 { 
+typedef struct _EFI_IPSEC_SA_DATA2 {
   ///
   /// IPsec mode: tunnel or transport
   ///
-  EFI_IPSEC_MODE             Mode; 
+  EFI_IPSEC_MODE             Mode;
   ///
-  /// Sequence Number Counter. A 64-bit counter used to generate the sequence 
-  /// number field in AH or ESP headers. 
+  /// Sequence Number Counter. A 64-bit counter used to generate the sequence
+  /// number field in AH or ESP headers.
   ///
-  UINT64                     SNCount; 
+  UINT64                     SNCount;
   ///
-  /// Anti-Replay Window. A 64-bit counter and a bit-map used to determine 
+  /// Anti-Replay Window. A 64-bit counter and a bit-map used to determine
   /// whether an inbound AH or ESP packet is a replay.
   ///
-  UINT8                      AntiReplayWindows; 
+  UINT8                      AntiReplayWindows;
   ///
   /// AH/ESP cryptographic algorithm, key and parameters.
   ///
-  EFI_IPSEC_ALGO_INFO        AlgoInfo; 
+  EFI_IPSEC_ALGO_INFO        AlgoInfo;
   ///
   /// Lifetime of this SA.
   ///
-  EFI_IPSEC_SA_LIFETIME      SaLifetime; 
+  EFI_IPSEC_SA_LIFETIME      SaLifetime;
   ///
-  /// Any observed path MTU and aging variables. The Path MTU processing is 
+  /// Any observed path MTU and aging variables. The Path MTU processing is
   /// defined in section 8 of RFC 4301.
   ///
-  UINT32                     PathMTU; 
+  UINT32                     PathMTU;
   ///
   /// Link to one SPD entry
   ///
-  EFI_IPSEC_SPD_SELECTOR     *SpdSelector; 
+  EFI_IPSEC_SPD_SELECTOR     *SpdSelector;
   ///
-  /// Indication of whether it's manually set or negotiated automatically. 
-  /// If ManualSet is FALSE, the corresponding SA entry is inserted through IKE 
+  /// Indication of whether it's manually set or negotiated automatically.
+  /// If ManualSet is FALSE, the corresponding SA entry is inserted through IKE
   /// protocol negotiation
   ///
   BOOLEAN                    ManualSet;
@@ -503,7 +497,7 @@ typedef struct _EFI_IPSEC_SA_DATA2 {
   /// The tunnel header IP destination address.
   ///
   EFI_IP_ADDRESS             TunnelDestinationAddress;
-} EFI_IPSEC_SA_DATA2; 
+} EFI_IPSEC_SA_DATA2;
 
 
 ///
@@ -514,8 +508,8 @@ typedef struct _EFI_IPSEC_SA_DATA2 {
 typedef struct _EFI_IPSEC_PAD_ID {
   ///
   /// Flag to identify which type of PAD Id is used.
-  /// 
-  BOOLEAN               PeerIdValid;    
+  ///
+  BOOLEAN               PeerIdValid;
   union {
     ///
     /// Pointer to the IPv4 or IPv6 address range.
@@ -523,8 +517,8 @@ typedef struct _EFI_IPSEC_PAD_ID {
     EFI_IP_ADDRESS_INFO   IpAddress;
     ///
     /// Pointer to a null terminated ASCII string
-    /// representing the symbolic names. A PeerId can be a DNS 
-    /// name, Distinguished Name, RFC 822 email address or Key ID 
+    /// representing the symbolic names. A PeerId can be a DNS
+    /// name, Distinguished Name, RFC 822 email address or Key ID
     /// (specified in section 4.4.3.1 of RFC 4301)
     ///
     UINT8                 PeerId[MAX_PEERID_LEN];
@@ -533,7 +527,7 @@ typedef struct _EFI_IPSEC_PAD_ID {
 
 ///
 /// EFI_IPSEC_CONFIG_SELECTOR
-/// describes the expected IPsec configuration data selector 
+/// describes the expected IPsec configuration data selector
 /// of type EFI_IPSEC_CONFIG_DATA_TYPE.
 ///
 typedef union {
@@ -544,7 +538,7 @@ typedef union {
 
 ///
 /// EFI_IPSEC_AUTH_PROTOCOL_TYPE
-/// defines the possible authentication protocol for IPsec 
+/// defines the possible authentication protocol for IPsec
 /// security association management.
 ///
 typedef enum {
@@ -572,64 +566,64 @@ typedef enum {
 /// EFI_IPSEC_PAD_DATA
 ///
 typedef struct _EFI_IPSEC_PAD_DATA {
-  /// 
+  ///
   /// Authentication Protocol for IPsec security association  management.
-  /// 
+  ///
   EFI_IPSEC_AUTH_PROTOCOL_TYPE  AuthProtocol;
-  /// 
+  ///
   /// Authentication method used.
-  /// 
+  ///
   EFI_IPSEC_AUTH_METHOD         AuthMethod;
-  /// 
-  /// The IKE ID payload will be used as a symbolic name for SPD 
-  /// lookup if IkeIdFlag is TRUE. Otherwise, the remote IP 
+  ///
+  /// The IKE ID payload will be used as a symbolic name for SPD
+  /// lookup if IkeIdFlag is TRUE. Otherwise, the remote IP
   /// address provided in traffic selector playloads will be used.
-  /// 
+  ///
   BOOLEAN                       IkeIdFlag;
-  /// 
+  ///
   /// The size of Authentication data buffer, in bytes.
-  /// 
+  ///
   UINTN                         AuthDataSize;
-  /// 
-  /// Buffer for Authentication data, (e.g., the pre-shared secret or the 
-  /// trust anchor relative to which the peer's certificate will be 
+  ///
+  /// Buffer for Authentication data, (e.g., the pre-shared secret or the
+  /// trust anchor relative to which the peer's certificate will be
   /// validated).
-  /// 
+  ///
   VOID                          *AuthData;
-  /// 
+  ///
   /// The size of RevocationData, in bytes
-  /// 
+  ///
   UINTN                         RevocationDataSize;
-  /// 
-  /// Pointer to CRL or OCSP data, if certificates are used for 
+  ///
+  /// Pointer to CRL or OCSP data, if certificates are used for
   /// authentication method.
-  /// 
+  ///
   VOID                          *RevocationData;
 } EFI_IPSEC_PAD_DATA;
 
 
 /**
   Set the security association, security policy and peer authorization configuration
-  information for the EFI IPsec driver. 
+  information for the EFI IPsec driver.
 
   This function is used to set the IPsec configuration information of type DataType for
   the EFI IPsec driver.
   The IPsec configuration data has a unique selector/identifier separately to identify
   a data entry. The selector structure depends on DataType's definition.
   Using SetData() with a Data of NULL causes the IPsec configuration data entry identified
-  by DataType and Selector to be deleted.        
+  by DataType and Selector to be deleted.
 
   @param[in] This               Pointer to the EFI_IPSEC_CONFIG_PROTOCOL instance.
   @param[in] DataType           The type of data to be set.
-  @param[in] Selector           Pointer to an entry selector on operated configuration data 
-                                specified by DataType. A NULL Selector causes the entire 
+  @param[in] Selector           Pointer to an entry selector on operated configuration data
+                                specified by DataType. A NULL Selector causes the entire
                                 specified-type configuration information to be flushed.
-  @param[in] Data               The data buffer to be set. The structure of the data buffer is 
+  @param[in] Data               The data buffer to be set. The structure of the data buffer is
                                 associated with the DataType.
   @param[in] InsertBefore       Pointer to one entry selector which describes the expected
                                 position the new data entry will be added. If InsertBefore is NULL,
                                 the new entry will be appended the end of database.
- 
+
   @retval EFI_SUCCESS           The specified configuration entry data is set successfully.
   @retval EFI_INVALID_PARAMETER One or more of the following are TRUE:
                                 - This is NULL.
@@ -648,20 +642,20 @@ EFI_STATUS
   );
 
 /**
-  Return the configuration value for the EFI IPsec driver. 
+  Return the configuration value for the EFI IPsec driver.
 
   This function lookup the data entry from IPsec database or IKEv2 configuration
   information. The expected data type and unique identification are described in
-  DataType and Selector parameters.        
+  DataType and Selector parameters.
 
   @param[in]      This          Pointer to the EFI_IPSEC_CONFIG_PROTOCOL instance.
   @param[in]      DataType      The type of data to retrieve.
-  @param[in]      Selector      Pointer to an entry selector which is an identifier of the IPsec 
+  @param[in]      Selector      Pointer to an entry selector which is an identifier of the IPsec
                                 configuration data entry.
   @param[in, out] DataSize      On output the size of data returned in Data.
-  @param[out]     Data          The buffer to return the contents of the IPsec configuration data. 
-                                The type of the data buffer is associated with the DataType. 
- 
+  @param[out]     Data          The buffer to return the contents of the IPsec configuration data.
+                                The type of the data buffer is associated with the DataType.
+
   @retval EFI_SUCCESS           The specified configuration data is got successfully.
   @retval EFI_INVALID_PARAMETER One or more of the followings are TRUE:
                                 - This is NULL.
@@ -685,30 +679,30 @@ EFI_STATUS
   );
 
 /**
-  Enumerates the current selector for IPsec configuration data entry. 
+  Enumerates the current selector for IPsec configuration data entry.
 
   This function is called multiple times to retrieve the entry Selector in IPsec
-  configuration database. On each call to GetNextSelector(), the next entry 
+  configuration database. On each call to GetNextSelector(), the next entry
   Selector are retrieved into the output interface.
- 
-  If the entire IPsec configuration database has been iterated, the error 
+
+  If the entire IPsec configuration database has been iterated, the error
   EFI_NOT_FOUND is returned.
-  If the Selector buffer is too small for the next Selector copy, an 
-  EFI_BUFFER_TOO_SMALL error is returned, and SelectorSize is updated to reflect 
+  If the Selector buffer is too small for the next Selector copy, an
+  EFI_BUFFER_TOO_SMALL error is returned, and SelectorSize is updated to reflect
   the size of buffer needed.
 
   On the initial call to GetNextSelector() to start the IPsec configuration database
-  search, a pointer to the buffer with all zero value is passed in Selector. Calls 
-  to SetData() between calls to GetNextSelector may produce unpredictable results.         
+  search, a pointer to the buffer with all zero value is passed in Selector. Calls
+  to SetData() between calls to GetNextSelector may produce unpredictable results.
 
   @param[in]      This          Pointer to the EFI_IPSEC_CONFIG_PROTOCOL instance.
   @param[in]      DataType      The type of IPsec configuration data to retrieve.
   @param[in, out] SelectorSize  The size of the Selector buffer.
-  @param[in, out] Selector      On input, supplies the pointer to last Selector that was 
+  @param[in, out] Selector      On input, supplies the pointer to last Selector that was
                                 returned by GetNextSelector().
                                 On output, returns one copy of the current entry Selector
-                                of a given DataType. 
- 
+                                of a given DataType.
+
   @retval EFI_SUCCESS           The specified configuration data is got successfully.
   @retval EFI_INVALID_PARAMETER One or more of the followings are TRUE:
                                 - This is NULL.
@@ -717,7 +711,7 @@ EFI_STATUS
   @retval EFI_NOT_FOUND         The next configuration data entry was not found.
   @retval EFI_UNSUPPORTED       The specified DataType is not supported.
   @retval EFI_BUFFER_TOO_SMALL  The SelectorSize is too small for the result. This parameter
-                                has been updated with the size needed to complete the search 
+                                has been updated with the size needed to complete the search
                                 request.
 
 **/
@@ -732,18 +726,18 @@ EFI_STATUS
 
 /**
   Register an event that is to be signaled whenever a configuration process on the
-  specified IPsec configuration information is done. 
+  specified IPsec configuration information is done.
 
   This function registers an event that is to be signaled whenever a configuration
-  process on the specified IPsec configuration data is done (e.g. IPsec security 
+  process on the specified IPsec configuration data is done (e.g. IPsec security
   policy database configuration is ready). An event can be registered for different
-  DataType simultaneously and the caller is responsible for determining which type 
-  of configuration data causes the signaling of the event in such case.        
+  DataType simultaneously and the caller is responsible for determining which type
+  of configuration data causes the signaling of the event in such case.
 
   @param[in] This               Pointer to the EFI_IPSEC_CONFIG_PROTOCOL instance.
   @param[in] DataType           The type of data to be registered the event for.
   @param[in] Event              The event to be registered.
- 
+
   @retval EFI_SUCCESS           The event is registered successfully.
   @retval EFI_INVALID_PARAMETER This is NULL or Event is NULL.
   @retval EFI_ACCESS_DENIED     The Event is already registered for the DataType.
@@ -761,16 +755,16 @@ EFI_STATUS
 
 /**
   Remove the specified event that is previously registered on the specified IPsec
-  configuration data. 
+  configuration data.
 
-  This function removes a previously registered event for the specified configuration data.        
+  This function removes a previously registered event for the specified configuration data.
 
   @param[in] This               Pointer to the EFI_IPSEC_CONFIG_PROTOCOL instance.
   @param[in] DataType           The configuration data type to remove the registered event for.
   @param[in] Event              The event to be unregistered.
- 
+
   @retval EFI_SUCCESS           The event is removed successfully.
-  @retval EFI_NOT_FOUND         The Event specified by DataType could not be found in the 
+  @retval EFI_NOT_FOUND         The Event specified by DataType could not be found in the
                                 database.
   @retval EFI_INVALID_PARAMETER This is NULL or Event is NULL.
   @retval EFI_UNSUPPORTED       The notify registration unsupported or the specified
@@ -788,12 +782,12 @@ EFI_STATUS
 ///
 /// EFI_IPSEC_CONFIG_PROTOCOL
 /// provides the ability to set and lookup the IPsec SAD (Security Association Database),
-/// SPD (Security Policy Database) data entry and configure the security association 
-/// management protocol such as IKEv2. This protocol is used as the central 
+/// SPD (Security Policy Database) data entry and configure the security association
+/// management protocol such as IKEv2. This protocol is used as the central
 /// repository of any policy-specific configuration for EFI IPsec driver.
-/// EFI_IPSEC_CONFIG_PROTOCOL can be bound to both IPv4 and IPv6 stack. User can use this 
+/// EFI_IPSEC_CONFIG_PROTOCOL can be bound to both IPv4 and IPv6 stack. User can use this
 /// protocol for IPsec configuration in both IPv4 and IPv6 environment.
-/// 
+///
 struct _EFI_IPSEC_CONFIG_PROTOCOL {
   EFI_IPSEC_CONFIG_SET_DATA           SetData;
   EFI_IPSEC_CONFIG_GET_DATA           GetData;
diff --git a/MdePkg/Include/Protocol/IsaHc.h b/MdePkg/Include/Protocol/IsaHc.h
index bc92675d12ca..66f19a755bf2 100644
--- a/MdePkg/Include/Protocol/IsaHc.h
+++ b/MdePkg/Include/Protocol/IsaHc.h
@@ -5,14 +5,8 @@
   subtractive-decode ISA bus. It allows devices to be registered and also
   handles opening and closing the apertures which are positively-decoded.
 
-  Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This protocol is from PI Version 1.2.1.
@@ -76,7 +70,7 @@ EFI_STATUS
   hardware aperture (via CloseIoAperture()) until there are no more references to it.
 
   @param This             A pointer to this instance of the EFI_ISA_HC_PROTOCOL.
-  @param IoApertureHandle The I/O aperture handle previously returned from a 
+  @param IoApertureHandle The I/O aperture handle previously returned from a
                           call to OpenIoAperture().
 
   @retval EFI_SUCCESS     The IO aperture was closed successfully.
diff --git a/MdePkg/Include/Protocol/Kms.h b/MdePkg/Include/Protocol/Kms.h
index a8e58bc89b49..0b261a25892b 100644
--- a/MdePkg/Include/Protocol/Kms.h
+++ b/MdePkg/Include/Protocol/Kms.h
@@ -8,14 +8,8 @@
   server over the network, or to a Hardware Security Module (HSM) attached to the system it
   runs on, or anything else that is capable of providing the key management service.
 
-  Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials are licensed and made available under
-  the terms and conditions of the BSD License that accompanies this distribution.
-  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php.
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -80,6 +74,10 @@ typedef struct _EFI_KMS_PROTOCOL EFI_KMS_PROTOCOL;
   { \
     0xb9237513, 0x6c44, 0x4411, {0xa9, 0x90, 0x21, 0xe5, 0x56, 0xe0, 0x5a, 0xde } \
   }
+#define EFI_KMS_FORMAT_GENERIC_DYNAMIC_GUID \
+  { \
+    0x2156e996, 0x66de, 0x4b27, {0x9c, 0xc9, 0xb0, 0x9f, 0xac, 0x4d, 0x2, 0xbe } \
+  }
 ///@}
 
 ///
@@ -177,6 +175,17 @@ typedef struct _EFI_KMS_PROTOCOL EFI_KMS_PROTOCOL;
 
 typedef struct {
   ///
+  /// Length in bytes of the KeyData.
+  ///
+  UINT32        KeySize;
+  ///
+  /// The data of the key.
+  ///
+  UINT8         KeyData[1];
+} EFI_KMS_FORMAT_GENERIC_DYNAMIC;
+
+typedef struct {
+  ///
   /// The size in bytes for the client identifier.
   ///
   UINT16        ClientIdSize;
@@ -358,7 +367,7 @@ EFI_STATUS
 
   @param[in]      This              Pointer to the EFI_KMS_PROTOCOL instance.
   @param[in]      Client            Pointer to a valid EFI_KMS_CLIENT_INFO structure.
-  @param[in, out] ClientDataSize    Pointer to the size, in bytes, of an arbitrary block of 
+  @param[in, out] ClientDataSize    Pointer to the size, in bytes, of an arbitrary block of
                                     data specified by the ClientData parameter. This
                                     parameter may be NULL, in which case the ClientData
                                     parameter will be ignored and no data will be
@@ -373,11 +382,11 @@ EFI_STATUS
                                     which will be zero if no data is returned from the KMS.
   @param[in, out] ClientData        Pointer to a pointer to an arbitrary block of data of
                                     *ClientDataSize that is to be passed directly to the
-                                    KMS if it supports the use of client data. This 
-                                    parameter may be NULL if and only if the 
+                                    KMS if it supports the use of client data. This
+                                    parameter may be NULL if and only if the
                                     ClientDataSize parameter is also NULL. Upon return to
-                                    the caller, *ClientData points to a block of data of 
-                                    *ClientDataSize that was returned from the KMS. 
+                                    the caller, *ClientData points to a block of data of
+                                    *ClientDataSize that was returned from the KMS.
                                     If the returned value for *ClientDataSize is zero,
                                     then the returned value for *ClientData must be NULL
                                     and should be ignored by the caller. The KMS protocol
@@ -403,7 +412,7 @@ EFI_STATUS
   IN EFI_KMS_CLIENT_INFO        *Client,
   IN OUT UINTN                  *ClientDataSize OPTIONAL,
   IN OUT VOID                   **ClientData OPTIONAL
-  ); 
+  );
 
 /**
   Request that the KMS generate one or more new keys and associate them with key identifiers.
@@ -439,7 +448,7 @@ EFI_STATUS
                                      type and must be freed by the caller when it is no longer
                                      needed. Also, the KeyStatus field must reflect the result
                                      of the request relative to that key.
-  @param[in, out] ClientDataSize     Pointer to the size, in bytes, of an arbitrary block of 
+  @param[in, out] ClientDataSize     Pointer to the size, in bytes, of an arbitrary block of
                                      data specified by the ClientData parameter. This
                                      parameter may be NULL, in which case the ClientData
                                      parameter will be ignored and no data will be
@@ -454,11 +463,11 @@ EFI_STATUS
                                      which will be zero if no data is returned from the KMS.
   @param[in, out] ClientData         Pointer to a pointer to an arbitrary block of data of
                                      *ClientDataSize that is to be passed directly to the
-                                     KMS if it supports the use of client data. This 
-                                     parameter may be NULL if and only if the 
+                                     KMS if it supports the use of client data. This
+                                     parameter may be NULL if and only if the
                                      ClientDataSize parameter is also NULL. Upon return to
-                                     the caller, *ClientData points to a block of data of 
-                                     *ClientDataSize that was returned from the KMS. 
+                                     the caller, *ClientData points to a block of data of
+                                     *ClientDataSize that was returned from the KMS.
                                      If the returned value for *ClientDataSize is zero,
                                      then the returned value for *ClientData must be NULL
                                      and should be ignored by the caller. The KMS protocol
@@ -520,12 +529,12 @@ EFI_STATUS
                                      On output, the KeyIdentifierSize and KeyIdentifier fields
                                      will be unchanged, while the KeyFormat and KeyValue
                                      fields will be updated values associated with this key
-                                     identifier. Memory for the KeyValue field will be 
+                                     identifier. Memory for the KeyValue field will be
                                      allocated with the BOOT_SERVICES_DATA type and
                                      must be freed by the caller when it is no longer needed.
                                      Also, the KeyStatus field will reflect the result of the
                                      request relative to the individual key descriptor.
-  @param[in, out] ClientDataSize     Pointer to the size, in bytes, of an arbitrary block of 
+  @param[in, out] ClientDataSize     Pointer to the size, in bytes, of an arbitrary block of
                                      data specified by the ClientData parameter. This
                                      parameter may be NULL, in which case the ClientData
                                      parameter will be ignored and no data will be
@@ -540,11 +549,11 @@ EFI_STATUS
                                      which will be zero if no data is returned from the KMS.
   @param[in, out] ClientData         Pointer to a pointer to an arbitrary block of data of
                                      *ClientDataSize that is to be passed directly to the
-                                     KMS if it supports the use of client data. This 
-                                     parameter may be NULL if and only if the 
+                                     KMS if it supports the use of client data. This
+                                     parameter may be NULL if and only if the
                                      ClientDataSize parameter is also NULL. Upon return to
-                                     the caller, *ClientData points to a block of data of 
-                                     *ClientDataSize that was returned from the KMS. 
+                                     the caller, *ClientData points to a block of data of
+                                     *ClientDataSize that was returned from the KMS.
                                      If the returned value for *ClientDataSize is zero,
                                      then the returned value for *ClientData must be NULL
                                      and should be ignored by the caller. The KMS protocol
@@ -611,7 +620,7 @@ EFI_STATUS
                                      consistent values to be associated with the given KeyId.
                                      On return, the KeyStatus field will reflect the result
                                      of the operation for each key request.
-  @param[in, out] ClientDataSize     Pointer to the size, in bytes, of an arbitrary block of 
+  @param[in, out] ClientDataSize     Pointer to the size, in bytes, of an arbitrary block of
                                      data specified by the ClientData parameter. This
                                      parameter may be NULL, in which case the ClientData
                                      parameter will be ignored and no data will be
@@ -626,11 +635,11 @@ EFI_STATUS
                                      which will be zero if no data is returned from the KMS.
   @param[in, out] ClientData         Pointer to a pointer to an arbitrary block of data of
                                      *ClientDataSize that is to be passed directly to the
-                                     KMS if it supports the use of client data. This 
-                                     parameter may be NULL if and only if the 
+                                     KMS if it supports the use of client data. This
+                                     parameter may be NULL if and only if the
                                      ClientDataSize parameter is also NULL. Upon return to
-                                     the caller, *ClientData points to a block of data of 
-                                     *ClientDataSize that was returned from the KMS. 
+                                     the caller, *ClientData points to a block of data of
+                                     *ClientDataSize that was returned from the KMS.
                                      If the returned value for *ClientDataSize is zero,
                                      then the returned value for *ClientData must be NULL
                                      and should be ignored by the caller. The KMS protocol
@@ -696,7 +705,7 @@ EFI_STATUS
                                      KeyValue fields are ignored, but should be 0.
                                      On return, the KeyStatus field will reflect the result
                                      of the operation for each key request.
-  @param[in, out] ClientDataSize     Pointer to the size, in bytes, of an arbitrary block of 
+  @param[in, out] ClientDataSize     Pointer to the size, in bytes, of an arbitrary block of
                                      data specified by the ClientData parameter. This
                                      parameter may be NULL, in which case the ClientData
                                      parameter will be ignored and no data will be
@@ -711,11 +720,11 @@ EFI_STATUS
                                      which will be zero if no data is returned from the KMS.
   @param[in, out] ClientData         Pointer to a pointer to an arbitrary block of data of
                                      *ClientDataSize that is to be passed directly to the
-                                     KMS if it supports the use of client data. This 
-                                     parameter may be NULL if and only if the 
+                                     KMS if it supports the use of client data. This
+                                     parameter may be NULL if and only if the
                                      ClientDataSize parameter is also NULL. Upon return to
-                                     the caller, *ClientData points to a block of data of 
-                                     *ClientDataSize that was returned from the KMS. 
+                                     the caller, *ClientData points to a block of data of
+                                     *ClientDataSize that was returned from the KMS.
                                      If the returned value for *ClientDataSize is zero,
                                      then the returned value for *ClientData must be NULL
                                      and should be ignored by the caller. The KMS protocol
@@ -774,7 +783,7 @@ EFI_STATUS
                                      On input, the fields in the structure should be NULL.
                                      On output, the attribute fields will have updated values
                                      for attributes associated with this key identifier.
-  @param[in, out] ClientDataSize     Pointer to the size, in bytes, of an arbitrary block of 
+  @param[in, out] ClientDataSize     Pointer to the size, in bytes, of an arbitrary block of
                                      data specified by the ClientData parameter. This
                                      parameter may be NULL, in which case the ClientData
                                      parameter will be ignored and no data will be
@@ -789,11 +798,11 @@ EFI_STATUS
                                      which will be zero if no data is returned from the KMS.
   @param[in, out] ClientData         Pointer to a pointer to an arbitrary block of data of
                                      *ClientDataSize that is to be passed directly to the
-                                     KMS if it supports the use of client data. This 
-                                     parameter may be NULL if and only if the 
+                                     KMS if it supports the use of client data. This
+                                     parameter may be NULL if and only if the
                                      ClientDataSize parameter is also NULL. Upon return to
-                                     the caller, *ClientData points to a block of data of 
-                                     *ClientDataSize that was returned from the KMS. 
+                                     the caller, *ClientData points to a block of data of
+                                     *ClientDataSize that was returned from the KMS.
                                      If the returned value for *ClientDataSize is zero,
                                      then the returned value for *ClientData must be NULL
                                      and should be ignored by the caller. The KMS protocol
@@ -861,7 +870,7 @@ EFI_STATUS
                                      are completely filled in.
                                      On return the KeyAttributeStatus field will reflect the
                                      result of the operation for each key attribute request.
-  @param[in, out] ClientDataSize     Pointer to the size, in bytes, of an arbitrary block of 
+  @param[in, out] ClientDataSize     Pointer to the size, in bytes, of an arbitrary block of
                                      data specified by the ClientData parameter. This
                                      parameter may be NULL, in which case the ClientData
                                      parameter will be ignored and no data will be
@@ -876,11 +885,11 @@ EFI_STATUS
                                      which will be zero if no data is returned from the KMS.
   @param[in, out] ClientData         Pointer to a pointer to an arbitrary block of data of
                                      *ClientDataSize that is to be passed directly to the
-                                     KMS if it supports the use of client data. This 
-                                     parameter may be NULL if and only if the 
+                                     KMS if it supports the use of client data. This
+                                     parameter may be NULL if and only if the
                                      ClientDataSize parameter is also NULL. Upon return to
-                                     the caller, *ClientData points to a block of data of 
-                                     *ClientDataSize that was returned from the KMS. 
+                                     the caller, *ClientData points to a block of data of
+                                     *ClientDataSize that was returned from the KMS.
                                      If the returned value for *ClientDataSize is zero,
                                      then the returned value for *ClientData must be NULL
                                      and should be ignored by the caller. The KMS protocol
@@ -952,7 +961,7 @@ EFI_STATUS
                                      are completely filled in.
                                      On return the KeyAttributeStatus field will reflect the
                                      result of the operation for each key attribute request.
-  @param[in, out] ClientDataSize     Pointer to the size, in bytes, of an arbitrary block of 
+  @param[in, out] ClientDataSize     Pointer to the size, in bytes, of an arbitrary block of
                                      data specified by the ClientData parameter. This
                                      parameter may be NULL, in which case the ClientData
                                      parameter will be ignored and no data will be
@@ -967,11 +976,11 @@ EFI_STATUS
                                      which will be zero if no data is returned from the KMS.
   @param[in, out] ClientData         Pointer to a pointer to an arbitrary block of data of
                                      *ClientDataSize that is to be passed directly to the
-                                     KMS if it supports the use of client data. This 
-                                     parameter may be NULL if and only if the 
+                                     KMS if it supports the use of client data. This
+                                     parameter may be NULL if and only if the
                                      ClientDataSize parameter is also NULL. Upon return to
-                                     the caller, *ClientData points to a block of data of 
-                                     *ClientDataSize that was returned from the KMS. 
+                                     the caller, *ClientData points to a block of data of
+                                     *ClientDataSize that was returned from the KMS.
                                      If the returned value for *ClientDataSize is zero,
                                      then the returned value for *ClientData must be NULL
                                      and should be ignored by the caller. The KMS protocol
@@ -1049,7 +1058,7 @@ EFI_STATUS
                                      caller when it is no longer needed. Also, the KeyStatus
                                      field of each descriptor will reflect the result of the
                                      request relative to that key descriptor.
-  @param[in, out] ClientDataSize     Pointer to the size, in bytes, of an arbitrary block of 
+  @param[in, out] ClientDataSize     Pointer to the size, in bytes, of an arbitrary block of
                                      data specified by the ClientData parameter. This
                                      parameter may be NULL, in which case the ClientData
                                      parameter will be ignored and no data will be
@@ -1064,11 +1073,11 @@ EFI_STATUS
                                      which will be zero if no data is returned from the KMS.
   @param[in, out] ClientData         Pointer to a pointer to an arbitrary block of data of
                                      *ClientDataSize that is to be passed directly to the
-                                     KMS if it supports the use of client data. This 
-                                     parameter may be NULL if and only if the 
+                                     KMS if it supports the use of client data. This
+                                     parameter may be NULL if and only if the
                                      ClientDataSize parameter is also NULL. Upon return to
-                                     the caller, *ClientData points to a block of data of 
-                                     *ClientDataSize that was returned from the KMS. 
+                                     the caller, *ClientData points to a block of data of
+                                     *ClientDataSize that was returned from the KMS.
                                      If the returned value for *ClientDataSize is zero,
                                      then the returned value for *ClientData must be NULL
                                      and should be ignored by the caller. The KMS protocol
diff --git a/MdePkg/Include/Protocol/LegacyRegion2.h b/MdePkg/Include/Protocol/LegacyRegion2.h
index 6f553bd7ad25..4a21784ce361 100644
--- a/MdePkg/Include/Protocol/LegacyRegion2.h
+++ b/MdePkg/Include/Protocol/LegacyRegion2.h
@@ -2,17 +2,11 @@
   The Legacy Region Protocol controls the read, write and boot-lock attributes for
   the region 0xC0000 to 0xFFFFF.
 
-  Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
-  This Protocol is defined in UEFI Platform Initialization Specification 1.2 
+  This Protocol is defined in UEFI Platform Initialization Specification 1.2
   Volume 5: Standards
 
 **/
@@ -31,9 +25,9 @@ typedef struct _EFI_LEGACY_REGION2_PROTOCOL EFI_LEGACY_REGION2_PROTOCOL;
 /**
   Modify the hardware to allow (decode) or disallow (not decode) memory reads in a region.
 
-  If the On parameter evaluates to TRUE, this function enables memory reads in the address range 
+  If the On parameter evaluates to TRUE, this function enables memory reads in the address range
   Start to (Start + Length - 1).
-  If the On parameter evaluates to FALSE, this function disables memory reads in the address range 
+  If the On parameter evaluates to FALSE, this function disables memory reads in the address range
   Start to (Start + Length - 1).
 
   @param  This[in]              Indicates the EFI_LEGACY_REGION2_PROTOCOL instance.
@@ -96,7 +90,7 @@ EFI_STATUS
 /**
   Modify the hardware to disallow memory attribute changes in a region.
 
-  This function makes the attributes of a region read only. Once a region is boot-locked with this 
+  This function makes the attributes of a region read only. Once a region is boot-locked with this
   function, the read and write attributes of that region cannot be changed until a power cycle has
   reset the boot-lock attribute. Calls to Decode(), Lock() and Unlock() will have no effect.
 
@@ -131,7 +125,7 @@ EFI_STATUS
 /**
   Modify the hardware to allow memory writes in a region.
 
-  This function changes the attributes of a memory range to allow writes.  
+  This function changes the attributes of a memory range to allow writes.
 
   @param  This[in]              Indicates the EFI_LEGACY_REGION2_PROTOCOL instance.
   @param  Start[in]             The beginning of the physical address of the region whose
@@ -195,9 +189,9 @@ typedef struct {
 /**
   Get region information for the attributes of the Legacy Region.
 
-  This function is used to discover the granularity of the attributes for the memory in the legacy 
+  This function is used to discover the granularity of the attributes for the memory in the legacy
   region. Each attribute may have a different granularity and the granularity may not be the same
-  for all memory ranges in the legacy region.  
+  for all memory ranges in the legacy region.
 
   @param  This[in]              Indicates the EFI_LEGACY_REGION2_PROTOCOL instance.
   @param  DescriptorCount[out]  The number of region descriptor entries returned in the Descriptor
@@ -220,8 +214,8 @@ EFI_STATUS
   );
 
 
-/// 
-/// The EFI_LEGACY_REGION2_PROTOCOL is used to abstract the hardware control of the memory 
+///
+/// The EFI_LEGACY_REGION2_PROTOCOL is used to abstract the hardware control of the memory
 /// attributes of the Option ROM shadowing region, 0xC0000 to 0xFFFFF.
 /// There are three memory attributes that can be modified through this protocol: read, write and
 /// boot-lock. These protocols may be set in any combination.
diff --git a/MdePkg/Include/Protocol/LegacySpiController.h b/MdePkg/Include/Protocol/LegacySpiController.h
new file mode 100644
index 000000000000..d08741d5ed81
--- /dev/null
+++ b/MdePkg/Include/Protocol/LegacySpiController.h
@@ -0,0 +1,259 @@
+/** @file
+  This file defines the Legacy SPI Controller Protocol.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+    This Protocol was introduced in UEFI PI Specification 1.6.
+
+**/
+
+#ifndef __LEGACY_SPI_CONTROLLER_PROTOCOL_H__
+#define __LEGACY_SPI_CONTROLLER_PROTOCOL_H__
+
+///
+/// Note: The UEFI PI 1.6 specification uses the character 'l' in the GUID
+///       definition. This definition assumes it was supposed to be '1'.
+///
+/// Global ID for the Legacy SPI Controller Protocol
+///
+#define EFI_LEGACY_SPI_CONTROLLER_GUID  \
+  { 0x39136fc7, 0x1a11, 0x49de,         \
+    { 0xbf, 0x35, 0x0e, 0x78, 0xdd, 0xb5, 0x24, 0xfc }}
+
+typedef
+struct _EFI_LEGACY_SPI_CONTROLLER_PROTOCOL
+EFI_LEGACY_SPI_CONTROLLER_PROTOCOL;
+
+/**
+  Set the erase block opcode.
+
+  This routine must be called at or below TPL_NOTIFY.
+  The menu table contains SPI transaction opcodes which are accessible after
+  the legacy SPI flash controller's configuration is locked. The board layer
+  specifies the erase block size for the SPI NOR flash part. The SPI NOR flash
+  peripheral driver selects the erase block opcode which matches the erase
+  block size and uses this API to load the opcode into the opcode menu table.
+
+  @param[in] This              Pointer to an EFI_LEGACY_SPI_CONTROLLER_PROTOCOL
+                               structure.
+  @param[in] EraseBlockOpcode  Erase block opcode to be placed into the opcode
+                               menu table.
+
+  @retval EFI_SUCCESS       The opcode menu table was updated
+  @retval EFI_ACCESS_ERROR  The SPI controller is locked
+
+**/
+typedef EFI_STATUS
+(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_ERASE_BLOCK_OPCODE) (
+  IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL  *This,
+  IN UINT8                                     EraseBlockOpcode
+  );
+
+/**
+  Set the write status prefix opcode.
+
+  This routine must be called at or below TPL_NOTIFY.
+  The prefix table contains SPI transaction write prefix opcodes which are
+  accessible after the legacy SPI flash controller's configuration is locked.
+  The board layer specifies the write status prefix opcode for the SPI NOR
+  flash part. The SPI NOR flash peripheral driver uses this API to load the
+  opcode into the prefix table.
+
+  @param[in] This               Pointer to an
+                                EFI_LEGACY_SPI_CONTROLLER_PROTOCOL structure.
+  @param[in] WriteStatusPrefix  Prefix opcode for the write status command.
+
+  @retval EFI_SUCCESS       The prefix table was updated
+  @retval EFI_ACCESS_ERROR  The SPI controller is locked
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_WRITE_STATUS_PREFIX) (
+  IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL  *This,
+  IN UINT8                                     WriteStatusPrefix
+  );
+
+/**
+  Set the BIOS base address.
+
+  This routine must be called at or below TPL_NOTIFY.
+  The BIOS base address works with the protect range registers to protect
+  portions of the SPI NOR flash from erase and write operat ions. The BIOS
+  calls this API prior to passing control to the OS loader.
+
+  @param[in] This             Pointer to an EFI_LEGACY_SPI_CONTROLLER_PROTOCOL
+                              structure.
+  @param[in] BiosBaseAddress  The BIOS base address.
+
+  @retval EFI_SUCCESS            The BIOS base address was properly set
+  @retval EFI_ACCESS_ERROR       The SPI controller is locked
+  @retval EFI_INVALID_PARAMETER  The BIOS base address is greater than
+                                 This->Maxi.mumOffset
+  @retval EFI_UNSUPPORTED        The BIOS base address was already set
+
+**/
+typedef EFI_STATUS
+(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_BIOS_BASE_ADDRESS) (
+  IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL  *This,
+  IN UINT32 BiosBaseAddress
+  );
+
+/**
+  Clear the SPI protect range registers.
+
+  This routine must be called at or below TPL_NOTIFY.
+  The BIOS uses this routine to set an initial condition on the SPI protect
+  range registers.
+
+  @param[in] This  Pointer to an EFI_LEGACY_SPI_CONTROLLER_PROTOCOL structure.
+
+  @retval EFI_SUCCESS       The registers were successfully cleared
+  @retval EFI_ACCESS_ERROR  The SPI controller is locked
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_CLEAR_SPI_PROTECT) (
+  IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL  *This
+  );
+
+/**
+  Determine if the SPI range is protected.
+
+  This routine must be called at or below TPL_NOTIFY.
+  The BIOS uses this routine to verify a range in the SPI is protected.
+
+  @param[in] This            Pointer to an EFI_LEGACY_SPI_CONTROLLER_PROTOCOL
+                             structure.
+  @param[in] BiosAddress     Address within a 4 KiB block to start protecting.
+  @param[in] BytesToProtect  The number of 4 KiB blocks to protect.
+
+  @retval TRUE   The range is protected
+  @retval FALSE  The range is not protected
+
+**/
+typedef
+BOOLEAN
+(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_IS_RANGE_PROTECTED) (
+  IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL  *This,
+  IN UINT32                                    BiosAddress,
+  IN UINT32                                    BlocksToProtect
+  );
+
+/**
+  Set the next protect range register.
+
+  This routine must be called at or below TPL_NOTIFY.
+  The BIOS sets the protect range register to prevent write and erase
+  operations to a portion of the SPI NOR flash device.
+
+  @param[in] This             Pointer to an EFI_LEGACY_SPI_CONTROLLER_PROTOCOL
+                              structure.
+  @param[in] BiosAddress      Address within a 4 KiB block to start protecting.
+  @param[in] BlocksToProtect  The number of 4 KiB blocks to protect.
+
+  @retval EFI_SUCCESS            The register was successfully updated
+  @retval EFI_ACCESS_ERROR       The SPI controller is locked
+  @retval EFI_INVALID_PARAMETER  BiosAddress < This->BiosBaseAddress, or
+                                 BlocksToProtect * 4 KiB
+                                   > This->MaximumRangeBytes, or
+                                 BiosAddress - This->BiosBaseAddress
+                                   + (BlocksToProtect * 4 KiB)
+                                     > This->MaximumRangeBytes
+  @retval EFI_OUT_OF_RESOURCES  No protect range register available
+  @retval EFI_UNSUPPORTED       Call This->SetBaseAddress because the BIOS base
+                                address is not set
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_PROTECT_NEXT_RANGE) (
+  IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL  *This,
+  IN UINT32                                    BiosAddress,
+  IN UINT32                                    BlocksToProtect
+  );
+
+/**
+  Lock the SPI controller configuration.
+
+  This routine must be called at or below TPL_NOTIFY.
+  This routine locks the SPI controller's configuration so that the software
+  is no longer able to update:
+  * Prefix table
+  * Opcode menu
+  * Opcode type table
+  * BIOS base address
+  * Protect range registers
+
+  @param[in] This  Pointer to an EFI_LEGACY_SPI_CONTROLLER_PROTOCOL structure.
+
+  @retval EFI_SUCCESS          The SPI controller was successfully locked
+  @retval EFI_ALREADY_STARTED  The SPI controller was already locked
+
+**/
+typedef EFI_STATUS
+(EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_LOCK_CONTROLLER) (
+  IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL  *This
+  );
+
+///
+/// Support the extra features of the legacy SPI flash controller.
+///
+struct _EFI_LEGACY_SPI_CONTROLLER_PROTOCOL {
+  ///
+  /// Maximum offset from the BIOS base address that is able to be protected.
+  ///
+  UINT32                                                 MaximumOffset;
+
+  ///
+  /// Maximum number of bytes that can be protected by one range register.
+  ///
+  UINT32                                                 MaximumRangeBytes;
+
+  ///
+  /// The number of registers available for protecting the BIOS.
+  ///
+  UINT32                                                 RangeRegisterCount;
+
+  ///
+  /// Set the erase block opcode.
+  ///
+  EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_ERASE_BLOCK_OPCODE  EraseBlockOpcode;
+
+  ///
+  /// Set the write status prefix opcode.
+  ///
+  EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_WRITE_STATUS_PREFIX WriteStatusPrefix;
+
+  ///
+  /// Set the BIOS base address.
+  ///
+  EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_BIOS_BASE_ADDRESS   BiosBaseAddress;
+
+  ///
+  /// Clear the SPI protect range registers.
+  ///
+  EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_CLEAR_SPI_PROTECT   ClearSpiProtect;
+
+  ///
+  /// Determine if the SPI range is protected.
+  ///
+  EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_IS_RANGE_PROTECTED  IsRangeProtected;
+
+  ///
+  /// Set the next protect range register.
+  ///
+  EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_PROTECT_NEXT_RANGE  ProtectNextRange;
+
+  ///
+  /// Lock the SPI controller configuration.
+  ///
+  EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_LOCK_CONTROLLER     LockController;
+};
+
+extern EFI_GUID gEfiLegacySpiControllerProtocolGuid;
+
+#endif // __LEGACY_SPI_CONTROLLER_PROTOCOL_H__
diff --git a/MdePkg/Include/Protocol/LegacySpiFlash.h b/MdePkg/Include/Protocol/LegacySpiFlash.h
new file mode 100644
index 000000000000..539ecedb2676
--- /dev/null
+++ b/MdePkg/Include/Protocol/LegacySpiFlash.h
@@ -0,0 +1,195 @@
+/** @file
+  This file defines the Legacy SPI Flash Protocol.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+    This Protocol was introduced in UEFI PI Specification 1.6.
+
+**/
+
+#ifndef __LEGACY_SPI_FLASH_PROTOCOL_H__
+#define __LEGACY_SPI_FLASH_PROTOCOL_H__
+
+#include <Protocol/SpiNorFlash.h>
+
+///
+/// Global ID for the Legacy SPI Flash Protocol
+///
+#define EFI_LEGACY_SPI_FLASH_PROTOCOL_GUID  \
+  { 0xf01bed57, 0x04bc, 0x4f3f,             \
+    { 0x96, 0x60, 0xd6, 0xf2, 0xea, 0x22, 0x82, 0x59 }}
+
+typedef struct _EFI_LEGACY_SPI_FLASH_PROTOCOL EFI_LEGACY_SPI_FLASH_PROTOCOL;
+
+/**
+  Set the BIOS base address.
+
+  This routine must be called at or below TPL_NOTIFY.
+  The BIOS base address works with the protect range registers to protect
+  portions of the SPI NOR flash from erase and write operat ions.
+  The BIOS calls this API prior to passing control to the OS loader.
+
+  @param[in] This             Pointer to an EFI_LEGACY_SPI_FLASH_PROTOCOL data
+                              structure.
+  @param[in] BiosBaseAddress  The BIOS base address.
+
+  @retval EFI_SUCCESS            The BIOS base address was properly set
+  @retval EFI_ACCESS_ERROR       The SPI controller is locked
+  @retval EFI_INVALID_PARAMETER  BiosBaseAddress > This->MaximumOffset
+  @retval EFI_UNSUPPORTED        The BIOS base address was already set or not a
+                                 legacy SPI host controller
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_LEGACY_SPI_FLASH_PROTOCOL_BIOS_BASE_ADDRESS) (
+  IN CONST EFI_LEGACY_SPI_FLASH_PROTOCOL  *This,
+  IN UINT32                               BiosBaseAddress
+  );
+
+/**
+  Clear the SPI protect range registers.
+
+  This routine must be called at or below TPL_NOTIFY.
+  The BIOS uses this routine to set an initial condition on the SPI protect
+  range registers.
+
+  @param[in] This  Pointer to an EFI_LEGACY_SPI_FLASH_PROTOCOL data structure.
+
+  @retval EFI_SUCCESS       The registers were successfully cleared
+  @retval EFI_ACCESS_ERROR  The SPI controller is locked
+  @retval EFI_UNSUPPORTED   Not a legacy SPI host controller
+
+**/
+typedef EFI_STATUS
+(EFIAPI *EFI_LEGACY_SPI_FLASH_PROTOCOL_CLEAR_SPI_PROTECT) (
+  IN CONST EFI_LEGACY_SPI_FLASH_PROTOCOL  *This
+  );
+
+/**
+  Determine if the SPI range is protected.
+
+  This routine must be called at or below TPL_NOTIFY.
+  The BIOS uses this routine to verify a range in the SPI is protected.
+
+  @param[in] This             Pointer to an EFI_LEGACY_SPI_FLASH_PROTOCOL data
+                              structure.
+  @param[in] BiosAddress      Address within a 4 KiB block to start protecting.
+  @param[in] BlocksToProtect  The number of 4 KiB blocks to protect.
+
+  @retval TRUE   The range is protected
+  @retval FALSE  The range is not protected
+
+**/
+typedef
+BOOLEAN
+(EFIAPI *EFI_LEGACY_SPI_FLASH_PROTOCOL_IS_RANGE_PROTECTED) (
+  IN CONST EFI_LEGACY_SPI_FLASH_PROTOCOL  *This,
+  IN UINT32                               BiosAddress,
+  IN UINT32                               BlocksToProtect
+  );
+
+/**
+  Set the next protect range register.
+
+  This routine must be called at or below TPL_NOTIFY.
+  The BIOS sets the protect range register to prevent write and erase
+  operations to a portion of the SPI NOR flash device.
+
+  @param[in] This             Pointer to an EFI_LEGACY_SPI_FLASH_PROTOCOL data
+                              structure.
+  @param[in] BiosAddress      Address within a 4 KiB block to start protecting.
+  @param[in] BlocksToProtect  The number of 4 KiB blocks to protect.
+
+  @retval EFI_SUCCESS            The register was successfully updated
+  @retval EFI_ACCESS_ERROR       The SPI controller is locked
+  @retval EFI_INVALID_PARAMETER  BiosAddress < This->BiosBaseAddress, or
+  @retval EFI_INVALID_PARAMETER  BlocksToProtect * 4 KiB
+                                   > This->MaximumRangeBytes, or
+                                 BiosAddress - This->BiosBaseAddress
+                                   + (BlocksToProtect * 4 KiB)
+                                     > This->MaximumRangeBytes
+  @retval EFI_OUT_OF_RESOURCES   No protect range register available
+  @retval EFI_UNSUPPORTED        Call This->SetBaseAddress because the BIOS
+                                 base address is not set Not a legacy SPI host
+                                 controller
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_LEGACY_SPI_FLASH_PROTOCOL_PROTECT_NEXT_RANGE) (
+  IN CONST EFI_LEGACY_SPI_FLASH_PROTOCOL  *This,
+  IN UINT32                               BiosAddress,
+  IN UINT32                               BlocksToProtect
+  );
+
+/**
+  Lock the SPI controller configuration.
+
+  This routine must be called at or below TPL_NOTIFY.
+  This routine locks the SPI controller's configuration so that the software is
+  no longer able to update:
+  * Prefix table
+  * Opcode menu
+  * Opcode type table
+  * BIOS base address
+  * Protect range registers
+
+  @param[in] This  Pointer to an EFI_LEGACY_SPI_FLASH_PROTOCOL data structure.
+
+  @retval EFI_SUCCESS          The SPI controller was successfully locked
+  @retval EFI_ALREADY_STARTED  The SPI controller was already locked
+  @retval EFI_UNSUPPORTED      Not a legacy SPI host controller
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_LEGACY_SPI_FLASH_PROTOCOL_LOCK_CONTROLLER) (
+  IN CONST EFI_LEGACY_SPI_FLASH_PROTOCOL  *This
+  );
+
+///
+/// The EFI_LEGACY_SPI_FLASH_PROTOCOL extends the EFI_SPI_NOR_FLASH_PROTOCOL
+/// with APls to support the legacy SPI flash controller.
+///
+struct _EFI_LEGACY_SPI_FLASH_PROTOCOL {
+  ///
+  /// This protocol manipulates the SPI NOR flash parts using a common set of
+  /// commands.
+  ///
+  EFI_SPI_NOR_FLASH_PROTOCOL                       FlashProtocol;
+
+  //
+  // Legacy flash (SPI host) controller support
+  //
+
+  ///
+  /// Set the BIOS base address.
+  ///
+  EFI_LEGACY_SPI_FLASH_PROTOCOL_BIOS_BASE_ADDRESS  BiosBaseAddress;
+
+  ///
+  /// Clear the SPI protect range registers.
+  ///
+  EFI_LEGACY_SPI_FLASH_PROTOCOL_CLEAR_SPI_PROTECT  ClearSpiProtect;
+
+  ///
+  /// Determine if the SPI range is protected.
+  ///
+  EFI_LEGACY_SPI_FLASH_PROTOCOL_IS_RANGE_PROTECTED IsRangeProtected;
+
+  ///
+  /// Set the next protect range register.
+  ///
+  EFI_LEGACY_SPI_FLASH_PROTOCOL_PROTECT_NEXT_RANGE ProtectNextRange;
+
+  ///
+  /// Lock the SPI controller configuration.
+  ///
+  EFI_LEGACY_SPI_FLASH_PROTOCOL_LOCK_CONTROLLER    LockController;
+};
+
+extern EFI_GUID gEfiLegacySpiFlashProtocolGuid;
+
+#endif // __LEGACY_SPI_FLASH_PROTOCOL_H__
diff --git a/MdePkg/Include/Protocol/LegacySpiSmmController.h b/MdePkg/Include/Protocol/LegacySpiSmmController.h
new file mode 100644
index 000000000000..e4fa7d967284
--- /dev/null
+++ b/MdePkg/Include/Protocol/LegacySpiSmmController.h
@@ -0,0 +1,30 @@
+/** @file
+  This file defines the Legacy SPI SMM Controler Protocol.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+    This Protocol was introduced in UEFI PI Specification 1.6.
+
+**/
+
+#ifndef __LEGACY_SPI_SMM_CONTROLLER_PROTOCOL_H__
+#define __LEGACY_SPI_SMM_CONTROLLER_PROTOCOL_H__
+
+#include <Protocol/LegacySpiController.h>
+
+///
+/// Global ID for the Legacy SPI SMM Controller Protocol
+///
+#define EFI_LEGACY_SPI_SMM_CONTROLLER_PROTOCOL_GUID  \
+  { 0x62331b78, 0xd8d0, 0x4c8c,                 \
+    { 0x8c, 0xcb, 0xd2, 0x7d, 0xfe, 0x32, 0xdb, 0x9b }}
+
+typedef
+struct _EFI_LEGACY_SPI_CONTROLLER_PROTOCOL
+EFI_LEGACY_SPI_SMM_CONTROLLER_PROTOCOL;
+
+extern EFI_GUID gEfiLegacySpiSmmControllerProtocolGuid;
+
+#endif // __LEGACY_SPI_SMM_CONTROLLER_PROTOCOL_H__
diff --git a/MdePkg/Include/Protocol/LegacySpiSmmFlash.h b/MdePkg/Include/Protocol/LegacySpiSmmFlash.h
new file mode 100644
index 000000000000..6e3f234065ab
--- /dev/null
+++ b/MdePkg/Include/Protocol/LegacySpiSmmFlash.h
@@ -0,0 +1,30 @@
+/** @file
+  This file defines the Legacy SPI SMM Flash Protocol.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+    This Protocol was introduced in UEFI PI Specification 1.6.
+
+**/
+
+#ifndef __LEGACY_SPI_SMM_FLASH_PROTOCOL_H__
+#define __LEGACY_SPI_SMM_FLASH_PROTOCOL_H__
+
+#include <Protocol/LegacySpiFlash.h>
+
+///
+/// Global ID for the Legacy SPI SMM Flash Protocol
+///
+#define EFI_LEGACY_SPI_SMM_FLASH_PROTOCOL_GUID  \
+  { 0x5e3848d4, 0x0db5, 0x4fc0,                 \
+    { 0x97, 0x29, 0x3f, 0x35, 0x3d, 0x4f, 0x87, 0x9f }}
+
+typedef
+struct _EFI_LEGACY_SPI_FLASH_PROTOCOL
+EFI_LEGACY_SPI_SMM_FLASH_PROTOCOL;
+
+extern EFI_GUID gEfiLegacySpiSmmFlashProtocolGuid;
+
+#endif // __SPI_SMM_FLASH_PROTOCOL_H__
diff --git a/MdePkg/Include/Protocol/LoadFile.h b/MdePkg/Include/Protocol/LoadFile.h
index 430ddb843dc9..1c2890feae47 100644
--- a/MdePkg/Include/Protocol/LoadFile.h
+++ b/MdePkg/Include/Protocol/LoadFile.h
@@ -1,20 +1,14 @@
 /** @file
   Load File protocol as defined in the UEFI 2.0 specification.
 
-  The load file protocol exists to supports the addition of new boot devices, 
-  and to support booting from devices that do not map well to file system. 
+  The load file protocol exists to supports the addition of new boot devices,
+  and to support booting from devices that do not map well to file system.
   Network boot is done via a LoadFile protocol.
 
   UEFI 2.0 can boot from any device that produces a LoadFile protocol.
 
-Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -35,7 +29,7 @@ typedef struct _EFI_LOAD_FILE_PROTOCOL EFI_LOAD_FILE_PROTOCOL;
 
 ///
 /// Backward-compatible with EFI1.1
-/// 
+///
 typedef EFI_LOAD_FILE_PROTOCOL  EFI_LOAD_FILE_INTERFACE;
 
 /**
diff --git a/MdePkg/Include/Protocol/LoadFile2.h b/MdePkg/Include/Protocol/LoadFile2.h
index cb977fbf3ec6..52105a1bfbd7 100644
--- a/MdePkg/Include/Protocol/LoadFile2.h
+++ b/MdePkg/Include/Protocol/LoadFile2.h
@@ -1,20 +1,14 @@
 /** @file
   Load File protocol as defined in the UEFI 2.0 specification.
 
-  Load file protocol exists to supports the addition of new boot devices, 
-  and to support booting from devices that do not map well to file system. 
+  Load file protocol exists to supports the addition of new boot devices,
+  and to support booting from devices that do not map well to file system.
   Network boot is done via a LoadFile protocol.
 
   UEFI 2.0 can boot from any device that produces a LoadFile protocol.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -57,7 +51,7 @@ typedef struct _EFI_LOAD_FILE2_PROTOCOL EFI_LOAD_FILE2_PROTOCOL;
   @retval EFI_NO_RESPONSE       The remote system did not respond.
   @retval EFI_NOT_FOUND         The file was not found
   @retval EFI_ABORTED           The file load process was manually canceled.
-  @retval EFI_BUFFER_TOO_SMALL  The BufferSize is too small to read the current 
+  @retval EFI_BUFFER_TOO_SMALL  The BufferSize is too small to read the current
                                 directory entry. BufferSize has been updated with
                                 the size needed to complete the request.
 
diff --git a/MdePkg/Include/Protocol/LoadedImage.h b/MdePkg/Include/Protocol/LoadedImage.h
index 53971bc91868..6b4aee651a45 100644
--- a/MdePkg/Include/Protocol/LoadedImage.h
+++ b/MdePkg/Include/Protocol/LoadedImage.h
@@ -4,14 +4,8 @@
   Every EFI driver and application is passed an image handle when it is loaded.
   This image handle will contain a Loaded Image Protocol.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -30,7 +24,7 @@
 
 ///
 /// Protocol GUID defined in EFI1.1.
-/// 
+///
 #define LOADED_IMAGE_PROTOCOL   EFI_LOADED_IMAGE_PROTOCOL_GUID
 
 ///
@@ -40,25 +34,25 @@
 
 ///
 /// Revision defined in EFI1.1.
-/// 
+///
 #define EFI_LOADED_IMAGE_INFORMATION_REVISION    EFI_LOADED_IMAGE_PROTOCOL_REVISION
 
 ///
 /// Can be used on any image handle to obtain information about the loaded image.
 ///
 typedef struct {
-  UINT32            Revision;       ///< Defines the revision of the EFI_LOADED_IMAGE_PROTOCOL structure. 
+  UINT32            Revision;       ///< Defines the revision of the EFI_LOADED_IMAGE_PROTOCOL structure.
                                     ///< All future revisions will be backward compatible to the current revision.
-  EFI_HANDLE        ParentHandle;   ///< Parent image's image handle. NULL if the image is loaded directly from 
-                                    ///< the firmware's boot manager. 
+  EFI_HANDLE        ParentHandle;   ///< Parent image's image handle. NULL if the image is loaded directly from
+                                    ///< the firmware's boot manager.
   EFI_SYSTEM_TABLE  *SystemTable;   ///< the image's EFI system table pointer.
 
   //
   // Source location of image
   //
-  EFI_HANDLE        DeviceHandle;   ///< The device handle that the EFI Image was loaded from. 
-  EFI_DEVICE_PATH_PROTOCOL  *FilePath;  ///< A pointer to the file path portion specific to DeviceHandle 
-                                        ///< that the EFI Image was loaded from. 
+  EFI_HANDLE        DeviceHandle;   ///< The device handle that the EFI Image was loaded from.
+  EFI_DEVICE_PATH_PROTOCOL  *FilePath;  ///< A pointer to the file path portion specific to DeviceHandle
+                                        ///< that the EFI Image was loaded from.
   VOID              *Reserved;      ///< Reserved. DO NOT USE.
 
   //
@@ -79,7 +73,7 @@ typedef struct {
 
 //
 // For backward-compatible with EFI1.1.
-// 
+//
 typedef EFI_LOADED_IMAGE_PROTOCOL EFI_LOADED_IMAGE;
 
 extern EFI_GUID gEfiLoadedImageProtocolGuid;
diff --git a/MdePkg/Include/Protocol/ManagedNetwork.h b/MdePkg/Include/Protocol/ManagedNetwork.h
index 2ac001c4f95c..4617afbc188a 100644
--- a/MdePkg/Include/Protocol/ManagedNetwork.h
+++ b/MdePkg/Include/Protocol/ManagedNetwork.h
@@ -2,16 +2,10 @@
   EFI_MANAGED_NETWORK_SERVICE_BINDING_PROTOCOL as defined in UEFI 2.0.
   EFI_MANAGED_NETWORK_PROTOCOL as defined in UEFI 2.0.
 
-Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-  @par Revision Reference:          
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
   This Protocol is introduced in UEFI Specification 2.0
 
 **/
@@ -352,7 +346,7 @@ EFI_STATUS
   );
 
 ///
-/// The MNP is used by network applications (and drivers) to 
+/// The MNP is used by network applications (and drivers) to
 /// perform raw (unformatted) asynchronous network packet I/O.
 ///
 struct _EFI_MANAGED_NETWORK_PROTOCOL {
diff --git a/MdePkg/Include/Protocol/McaInitPmi.h b/MdePkg/Include/Protocol/McaInitPmi.h
deleted file mode 100644
index c0c66147eab8..000000000000
--- a/MdePkg/Include/Protocol/McaInitPmi.h
+++ /dev/null
@@ -1,207 +0,0 @@
-/** @file
-  MCA/PMI/INIT Protocol as defined in PI Specification VOLUME 4.
-
-  This protocol provides services to handle Machine Checks (MCA),
-  Initialization (INIT) events, and Platform Management Interrupt (PMI) events
-  on an Intel Itanium Processor Family based system.
-
-  Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __MCA_INIT_PMI_PROTOCOL_H__
-#define __MCA_INIT_PMI_PROTOCOL_H__
-
-///
-/// Global ID for the MCA/PMI/INIT Protocol.
-///
-#define EFI_SAL_MCA_INIT_PMI_PROTOCOL_GUID \
-  { 0xb60dc6e8, 0x3b6f, 0x11d5, {0xaf, 0x9, 0x0, 0xa0, 0xc9, 0x44, 0xa0, 0x5b} }
-
-
-///
-/// Declare forward reference for the Timer Architectural Protocol
-///
-typedef struct _EFI_SAL_MCA_INIT_PMI_PROTOCOL  EFI_SAL_MCA_INIT_PMI_PROTOCOL;
-
-#pragma pack(1)
-///
-/// MCA Records Structure
-///
-typedef struct {
-  UINT64  First : 1;
-  UINT64  Last : 1;
-  UINT64  EntryCount : 16;
-  UINT64  DispatchedCount : 16;
-  UINT64  Reserved : 30;
-} SAL_MCA_COUNT_STRUCTURE;
-
-#pragma pack()
-
-/**
-  Prototype of MCA handler.
-
-  @param  ModuleGlobal                The context of MCA Handler
-  @param  ProcessorStateParameters    The processor state parameters (PSP)
-  @param  MinstateBase                Base address of the min-state
-  @param  RendezvouseStateInformation Rendezvous state information to be passed to
-                                      the OS on OS MCA entry
-  @param  CpuIndex                    Index of the logical processor
-  @param  McaCountStructure           Pointer to the MCA records structure
-  @param  CorrectedMachineCheck       This flag is set to TRUE is the MCA has been
-                                      corrected by the handler or by a previous handler
-
-  @retval EFI_SUCCESS                 Handler successfully returned
-
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_SAL_MCA_HANDLER)(
-  IN  VOID                    *ModuleGlobal,
-  IN  UINT64                  ProcessorStateParameters,
-  IN  EFI_PHYSICAL_ADDRESS    MinstateBase,
-  IN  UINT64                  RendezvouseStateInformation,
-  IN  UINT64                  CpuIndex,
-  IN  SAL_MCA_COUNT_STRUCTURE *McaCountStructure,
-  OUT BOOLEAN                 *CorrectedMachineCheck
-  );
-
-/**
-  Prototype of INIT handler.
-
-  @param  ModuleGlobal                The context of INIT Handler
-  @param  ProcessorStateParameters    The processor state parameters (PSP)
-  @param  MinstateBase                Base address of the min-state
-  @param  McaInProgress               This flag indicates if an MCA is in progress
-  @param  CpuIndex                    Index of the logical processor
-  @param  McaCountStructure           Pointer to the MCA records structure
-  @param  DumpSwitchPressed           This flag indicates the crash dump switch has been pressed
-
-  @retval EFI_SUCCESS                 Handler successfully returned
-
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_SAL_INIT_HANDLER)(
-  IN  VOID                     *ModuleGlobal,
-  IN  UINT64                   ProcessorStateParameters,
-  IN  EFI_PHYSICAL_ADDRESS     MinstateBase,
-  IN  BOOLEAN                  McaInProgress,
-  IN  UINT64                   CpuIndex,
-  IN  SAL_MCA_COUNT_STRUCTURE  *McaCountStructure,
-  OUT BOOLEAN                  *DumpSwitchPressed
-  );
-
-/**
-  Prototype of PMI handler
-
-  @param  ModuleGlobal                The context of PMI Handler
-  @param  CpuIndex                    Index of the logical processor
-  @param  PmiVector                   The PMI vector number as received from the PALE_PMI exit state (GR24)
-
-  @retval EFI_SUCCESS                 Handler successfully returned
-
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_SAL_PMI_HANDLER)(
-  IN VOID          *ModuleGlobal,
-  IN UINT64        CpuIndex,
-  IN UINT64        PmiVector
-  );
-
-/**
-  Register a MCA handler with the MCA dispatcher.
-
-  @param  This                        The EFI_SAL_MCA_INIT_PMI_PROTOCOL instance
-  @param  McaHandler                  The MCA handler to register
-  @param  ModuleGlobal                The context of MCA Handler
-  @param  MakeFirst                   This flag specifies the handler should be made first in the list
-  @param  MakeLast                    This flag specifies the handler should be made last in the list
-
-  @retval EFI_SUCCESS                 MCA Handle was registered
-  @retval EFI_OUT_OF_RESOURCES        No more resources to register an MCA handler
-  @retval EFI_INVALID_PARAMETER       Invalid parameters were passed
-
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_SAL_REGISTER_MCA_HANDLER)(
-  IN  EFI_SAL_MCA_INIT_PMI_PROTOCOL         *This,
-  IN  EFI_SAL_MCA_HANDLER                   McaHandler,
-  IN  VOID                                  *ModuleGlobal,
-  IN  BOOLEAN                               MakeFirst,
-  IN  BOOLEAN                               MakeLast
-  );
-
-/**
-  Register an INIT handler with the INIT dispatcher.
-
-  @param  This                        The EFI_SAL_MCA_INIT_PMI_PROTOCOL instance
-  @param  InitHandler                 The INIT handler to register
-  @param  ModuleGlobal                The context of INIT Handler
-  @param  MakeFirst                   This flag specifies the handler should be made first in the list
-  @param  MakeLast                    This flag specifies the handler should be made last in the list
-
-  @retval EFI_SUCCESS                 INIT Handle was registered
-  @retval EFI_OUT_OF_RESOURCES        No more resources to register an INIT handler
-  @retval EFI_INVALID_PARAMETER       Invalid parameters were passed
-
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_SAL_REGISTER_INIT_HANDLER)(
-  IN  EFI_SAL_MCA_INIT_PMI_PROTOCOL         *This,
-  IN  EFI_SAL_INIT_HANDLER                  InitHandler,
-  IN  VOID                                  *ModuleGlobal,
-  IN  BOOLEAN                               MakeFirst,
-  IN  BOOLEAN                               MakeLast
-  );
-
-/**
-  Register a PMI handler with the PMI dispatcher.
-
-  @param  This                        The EFI_SAL_MCA_INIT_PMI_PROTOCOL instance
-  @param  PmiHandler                  The PMI handler to register
-  @param  ModuleGlobal                The context of PMI Handler
-  @param  MakeFirst                   This flag specifies the handler should be made first in the list
-  @param  MakeLast                    This flag specifies the handler should be made last in the list
-
-  @retval EFI_SUCCESS                 PMI Handle was registered
-  @retval EFI_OUT_OF_RESOURCES        No more resources to register an PMI handler
-  @retval EFI_INVALID_PARAMETER       Invalid parameters were passed
-
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_SAL_REGISTER_PMI_HANDLER)(
-  IN  EFI_SAL_MCA_INIT_PMI_PROTOCOL         *This,
-  IN  EFI_SAL_PMI_HANDLER                   PmiHandler,
-  IN  VOID                                  *ModuleGlobal,
-  IN  BOOLEAN                               MakeFirst,
-  IN  BOOLEAN                               MakeLast
-  );
-
-///
-/// This protocol is used to register MCA, INIT and PMI handlers with their respective dispatcher
-///
-struct _EFI_SAL_MCA_INIT_PMI_PROTOCOL {
-  EFI_SAL_REGISTER_MCA_HANDLER  RegisterMcaHandler;
-  EFI_SAL_REGISTER_INIT_HANDLER RegisterInitHandler;
-  EFI_SAL_REGISTER_PMI_HANDLER  RegisterPmiHandler;
-  BOOLEAN                       McaInProgress;       ///< Whether MCA handler is in progress
-  BOOLEAN                       InitInProgress;      ///< Whether Init handler is in progress
-  BOOLEAN                       PmiInProgress;       ///< Whether Pmi handler is in progress
-};
-
-extern EFI_GUID gEfiSalMcaInitPmiProtocolGuid;
-
-#endif
-
diff --git a/MdePkg/Include/Protocol/Metronome.h b/MdePkg/Include/Protocol/Metronome.h
index 358d94b722ce..624c387c58a9 100644
--- a/MdePkg/Include/Protocol/Metronome.h
+++ b/MdePkg/Include/Protocol/Metronome.h
@@ -3,14 +3,8 @@
 
   This code abstracts the DXE core to provide delay services.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -29,17 +23,17 @@
 typedef struct _EFI_METRONOME_ARCH_PROTOCOL   EFI_METRONOME_ARCH_PROTOCOL;
 
 /**
-  The WaitForTick() function waits for the number of ticks specified by 
-  TickNumber from a known time source in the platform.  If TickNumber of 
-  ticks are detected, then EFI_SUCCESS is returned.  The actual time passed 
-  between entry of this function and the first tick is between 0 and 
-  TickPeriod 100 nS units.  If you want to guarantee that at least TickPeriod 
-  time has elapsed, wait for two ticks.  This function waits for a hardware 
-  event to determine when a tick occurs.  It is possible for interrupt 
-  processing, or exception processing to interrupt the execution of the 
-  WaitForTick() function.  Depending on the hardware source for the ticks, it 
-  is possible for a tick to be missed.  This function cannot guarantee that 
-  ticks will not be missed.  If a timeout occurs waiting for the specified 
+  The WaitForTick() function waits for the number of ticks specified by
+  TickNumber from a known time source in the platform.  If TickNumber of
+  ticks are detected, then EFI_SUCCESS is returned.  The actual time passed
+  between entry of this function and the first tick is between 0 and
+  TickPeriod 100 nS units.  If you want to guarantee that at least TickPeriod
+  time has elapsed, wait for two ticks.  This function waits for a hardware
+  event to determine when a tick occurs.  It is possible for interrupt
+  processing, or exception processing to interrupt the execution of the
+  WaitForTick() function.  Depending on the hardware source for the ticks, it
+  is possible for a tick to be missed.  This function cannot guarantee that
+  ticks will not be missed.  If a timeout occurs waiting for the specified
   number of ticks, then EFI_TIMEOUT is returned.
 
   @param  This             The EFI_METRONOME_ARCH_PROTOCOL instance.
@@ -50,7 +44,7 @@ typedef struct _EFI_METRONOME_ARCH_PROTOCOL   EFI_METRONOME_ARCH_PROTOCOL;
   @retval EFI_TIMEOUT           A timeout occurred waiting for the specified number of ticks.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_METRONOME_WAIT_FOR_TICK)(
    IN EFI_METRONOME_ARCH_PROTOCOL   *This,
@@ -59,18 +53,18 @@ EFI_STATUS
 
 ///
 /// This protocol provides access to a known time source in the platform to the
-/// core.  The core uses this known time source to produce core services that 
-/// require calibrated delays.  
+/// core.  The core uses this known time source to produce core services that
+/// require calibrated delays.
 ///
 struct _EFI_METRONOME_ARCH_PROTOCOL {
   EFI_METRONOME_WAIT_FOR_TICK  WaitForTick;
-  
+
   ///
-  /// The period of platform's known time source in 100 nS units.  
-  /// This value on any platform must be at least 10 uS, and must not 
-  /// exceed 200 uS.  The value in this field is a constant that must 
-  /// not be modified after the Metronome architectural protocol is 
-  /// installed.  All consumers must treat this as a read-only field.  
+  /// The period of platform's known time source in 100 nS units.
+  /// This value on any platform must be at least 10 uS, and must not
+  /// exceed 200 uS.  The value in this field is a constant that must
+  /// not be modified after the Metronome architectural protocol is
+  /// installed.  All consumers must treat this as a read-only field.
   ///
   UINT32                       TickPeriod;
 };
diff --git a/MdePkg/Include/Protocol/MmAccess.h b/MdePkg/Include/Protocol/MmAccess.h
new file mode 100644
index 000000000000..39c379560362
--- /dev/null
+++ b/MdePkg/Include/Protocol/MmAccess.h
@@ -0,0 +1,127 @@
+/** @file
+  EFI MM Access Protocol as defined in the PI 1.5 specification.
+
+  This protocol is used to control the visibility of the MMRAM on the platform.
+  It abstracts the location and characteristics of MMRAM.  The expectation is
+  that the north bridge or memory controller would publish this protocol.
+
+  The principal functionality found in the memory controller includes the following:
+  - Exposing the MMRAM to all non-MM agents, or the "open" state
+  - Shrouding the MMRAM to all but the MM agents, or the "closed" state
+  - Preserving the system integrity, or "locking" the MMRAM, such that the settings cannot be
+    perturbed by either boot service or runtime agents
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _MM_ACCESS_H_
+#define _MM_ACCESS_H_
+
+#define EFI_MM_ACCESS_PROTOCOL_GUID \
+  { \
+     0xc2702b74, 0x800c, 0x4131, {0x87, 0x46, 0x8f, 0xb5, 0xb8, 0x9c, 0xe4, 0xac } \
+  }
+
+
+typedef struct _EFI_MM_ACCESS_PROTOCOL  EFI_MM_ACCESS_PROTOCOL;
+
+/**
+  Opens the MMRAM area to be accessible by a boot-service driver.
+
+  This function "opens" MMRAM so that it is visible while not inside of MM. The function should
+  return EFI_UNSUPPORTED if the hardware does not support hiding of MMRAM. The function
+  should return EFI_DEVICE_ERROR if the MMRAM configuration is locked.
+
+  @param[in] This           The EFI_MM_ACCESS_PROTOCOL instance.
+
+  @retval EFI_SUCCESS       The operation was successful.
+  @retval EFI_UNSUPPORTED   The system does not support opening and closing of MMRAM.
+  @retval EFI_DEVICE_ERROR  MMRAM cannot be opened, perhaps because it is locked.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_OPEN)(
+  IN EFI_MM_ACCESS_PROTOCOL  *This
+  );
+
+/**
+  Inhibits access to the MMRAM.
+
+  This function "closes" MMRAM so that it is not visible while outside of MM. The function should
+  return EFI_UNSUPPORTED if the hardware does not support hiding of MMRAM.
+
+  @param[in] This           The EFI_MM_ACCESS_PROTOCOL instance.
+
+  @retval EFI_SUCCESS       The operation was successful.
+  @retval EFI_UNSUPPORTED   The system does not support opening and closing of MMRAM.
+  @retval EFI_DEVICE_ERROR  MMRAM cannot be closed.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_CLOSE)(
+  IN EFI_MM_ACCESS_PROTOCOL  *This
+  );
+
+/**
+  Inhibits access to the MMRAM.
+
+  This function prohibits access to the MMRAM region.  This function is usually implemented such
+  that it is a write-once operation.
+
+  @param[in] This          The EFI_MM_ACCESS_PROTOCOL instance.
+
+  @retval EFI_SUCCESS      The device was successfully locked.
+  @retval EFI_UNSUPPORTED  The system does not support locking of MMRAM.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_LOCK)(
+  IN EFI_MM_ACCESS_PROTOCOL  *This
+  );
+
+/**
+  Queries the memory controller for the possible regions that will support MMRAM.
+
+  @param[in]     This           The EFI_MM_ACCESS_PROTOCOL instance.
+  @param[in,out] MmramMapSize   A pointer to the size, in bytes, of the MmramMemoryMap buffer.
+  @param[in,out] MmramMap       A pointer to the buffer in which firmware places the current memory map.
+
+  @retval EFI_SUCCESS           The chipset supported the given resource.
+  @retval EFI_BUFFER_TOO_SMALL  The MmramMap parameter was too small.  The current buffer size
+                                needed to hold the memory map is returned in MmramMapSize.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_CAPABILITIES)(
+  IN CONST EFI_MM_ACCESS_PROTOCOL    *This,
+  IN OUT UINTN                       *MmramMapSize,
+  IN OUT EFI_MMRAM_DESCRIPTOR        *MmramMap
+  );
+
+///
+///  EFI MM Access Protocol is used to control the visibility of the MMRAM on the platform.
+///  It abstracts the location and characteristics of MMRAM. The platform should report all
+///  MMRAM via EFI_MM_ACCESS_PROTOCOL. The expectation is that the north bridge or memory
+///  controller would publish this protocol.
+///
+struct _EFI_MM_ACCESS_PROTOCOL {
+  EFI_MM_OPEN          Open;
+  EFI_MM_CLOSE         Close;
+  EFI_MM_LOCK          Lock;
+  EFI_MM_CAPABILITIES  GetCapabilities;
+  ///
+  /// Indicates the current state of the MMRAM. Set to TRUE if MMRAM is locked.
+  ///
+  BOOLEAN               LockState;
+  ///
+  /// Indicates the current state of the MMRAM. Set to TRUE if MMRAM is open.
+  ///
+  BOOLEAN               OpenState;
+};
+
+extern EFI_GUID gEfiMmAccessProtocolGuid;
+
+#endif
+
diff --git a/MdePkg/Include/Protocol/MmBase.h b/MdePkg/Include/Protocol/MmBase.h
new file mode 100644
index 000000000000..3a8f3e69bb19
--- /dev/null
+++ b/MdePkg/Include/Protocol/MmBase.h
@@ -0,0 +1,81 @@
+/** @file
+  EFI MM Base Protocol as defined in the PI 1.5 specification.
+
+  This protocol is utilized by all MM drivers to locate the MM infrastructure services and determine
+  whether the driver is being invoked inside MMRAM or outside of MMRAM.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _MM_BASE_H_
+#define _MM_BASE_H_
+
+#include <Pi/PiMmCis.h>
+
+#define EFI_MM_BASE_PROTOCOL_GUID \
+  { \
+    0xf4ccbfb7, 0xf6e0, 0x47fd, {0x9d, 0xd4, 0x10, 0xa8, 0xf1, 0x50, 0xc1, 0x91 }  \
+  }
+
+typedef struct _EFI_MM_BASE_PROTOCOL  EFI_MM_BASE_PROTOCOL;
+
+/**
+  Service to indicate whether the driver is currently executing in the MM Initialization phase.
+
+  This service is used to indicate whether the driver is currently executing in the MM Initialization
+  phase. For MM drivers, this will return TRUE in InMmram while inside the driver's entry point and
+  otherwise FALSE. For combination MM/DXE drivers, this will return FALSE in the DXE launch. For the
+  MM launch, it behaves as an MM driver.
+
+  @param[in]  This               The EFI_MM_BASE_PROTOCOL instance.
+  @param[out] InMmram            Pointer to a Boolean which, on return, indicates that the driver is
+                                 currently executing inside of MMRAM (TRUE) or outside of MMRAM (FALSE).
+
+  @retval EFI_SUCCESS            The call returned successfully.
+  @retval EFI_INVALID_PARAMETER  InMmram was NULL.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_INSIDE_OUT)(
+  IN CONST EFI_MM_BASE_PROTOCOL    *This,
+  OUT BOOLEAN                      *InMmram
+  )
+;
+
+/**
+  Returns the location of the Management Mode Service Table (MMST).
+
+  This function returns the location of the Management Mode Service Table (MMST).  The use of the
+  API is such that a driver can discover the location of the MMST in its entry point and then cache it in
+  some driver global variable so that the MMST can be invoked in subsequent handlers.
+
+  @param[in]     This            The EFI_MM_BASE_PROTOCOL instance.
+  @param[in,out] Mmst            On return, points to a pointer to the Management Mode Service Table (MMST).
+
+  @retval EFI_SUCCESS            The operation was successful.
+  @retval EFI_INVALID_PARAMETER  Mmst was invalid.
+  @retval EFI_UNSUPPORTED        Not in MM.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_GET_MMST_LOCATION)(
+  IN CONST EFI_MM_BASE_PROTOCOL  *This,
+  IN OUT EFI_MM_SYSTEM_TABLE     **Mmst
+  )
+;
+
+///
+/// EFI MM Base Protocol is utilized by all MM drivers to locate the MM infrastructure
+/// services and determine whether the driver is being invoked inside MMRAM or outside of MMRAM.
+///
+struct _EFI_MM_BASE_PROTOCOL {
+  EFI_MM_INSIDE_OUT         InMm;
+  EFI_MM_GET_MMST_LOCATION  GetMmstLocation;
+};
+
+extern EFI_GUID gEfiMmBaseProtocolGuid;
+
+#endif
+
diff --git a/MdePkg/Include/Protocol/MmCommunication.h b/MdePkg/Include/Protocol/MmCommunication.h
new file mode 100644
index 000000000000..f6e2a6f43ffe
--- /dev/null
+++ b/MdePkg/Include/Protocol/MmCommunication.h
@@ -0,0 +1,87 @@
+/** @file
+  EFI MM Communication Protocol as defined in the PI 1.5 specification.
+
+  This protocol provides a means of communicating between drivers outside of MM and MMI
+  handlers inside of MM.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _MM_COMMUNICATION_H_
+#define _MM_COMMUNICATION_H_
+
+#pragma pack(1)
+
+///
+/// To avoid confusion in interpreting frames, the communication buffer should always
+/// begin with EFI_MM_COMMUNICATE_HEADER
+///
+typedef struct {
+  ///
+  /// Allows for disambiguation of the message format.
+  ///
+  EFI_GUID  HeaderGuid;
+  ///
+  /// Describes the size of Data (in bytes) and does not include the size of the header.
+  ///
+  UINTN     MessageLength;
+  ///
+  /// Designates an array of bytes that is MessageLength in size.
+  ///
+  UINT8     Data[1];
+} EFI_MM_COMMUNICATE_HEADER;
+
+#pragma pack()
+
+#define EFI_MM_COMMUNICATION_PROTOCOL_GUID \
+  { \
+    0xc68ed8e2, 0x9dc6, 0x4cbd, { 0x9d, 0x94, 0xdb, 0x65, 0xac, 0xc5, 0xc3, 0x32 } \
+  }
+
+typedef struct _EFI_MM_COMMUNICATION_PROTOCOL  EFI_MM_COMMUNICATION_PROTOCOL;
+
+/**
+  Communicates with a registered handler.
+
+  This function provides a service to send and receive messages from a registered UEFI service.
+
+  @param[in] This                The EFI_MM_COMMUNICATION_PROTOCOL instance.
+  @param[in] CommBuffer          A pointer to the buffer to convey into MMRAM.
+  @param[in] CommSize            The size of the data buffer being passed in. On exit, the size of data
+                                 being returned. Zero if the handler does not wish to reply with any data.
+                                 This parameter is optional and may be NULL.
+
+  @retval EFI_SUCCESS            The message was successfully posted.
+  @retval EFI_INVALID_PARAMETER  The CommBuffer was NULL.
+  @retval EFI_BAD_BUFFER_SIZE    The buffer is too large for the MM implementation.
+                                 If this error is returned, the MessageLength field
+                                 in the CommBuffer header or the integer pointed by
+                                 CommSize, are updated to reflect the maximum payload
+                                 size the implementation can accommodate.
+  @retval EFI_ACCESS_DENIED      The CommunicateBuffer parameter or CommSize parameter,
+                                 if not omitted, are in address range that cannot be
+                                 accessed by the MM environment.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_COMMUNICATE)(
+  IN CONST EFI_MM_COMMUNICATION_PROTOCOL   *This,
+  IN OUT VOID                              *CommBuffer,
+  IN OUT UINTN                             *CommSize OPTIONAL
+  );
+
+///
+/// EFI MM Communication Protocol provides runtime services for communicating
+/// between DXE drivers and a registered MMI handler.
+///
+struct _EFI_MM_COMMUNICATION_PROTOCOL {
+  EFI_MM_COMMUNICATE  Communicate;
+};
+
+extern EFI_GUID gEfiMmCommunicationProtocolGuid;
+
+#endif
+
diff --git a/MdePkg/Include/Protocol/MmCommunication2.h b/MdePkg/Include/Protocol/MmCommunication2.h
new file mode 100644
index 000000000000..2e02dbc452a4
--- /dev/null
+++ b/MdePkg/Include/Protocol/MmCommunication2.h
@@ -0,0 +1,69 @@
+/** @file
+  EFI MM Communication Protocol 2 as defined in the PI 1.7 errata A specification.
+
+  This protocol provides a means of communicating between drivers outside of MM and MMI
+  handlers inside of MM.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2019, Arm Limited. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _MM_COMMUNICATION2_H_
+#define _MM_COMMUNICATION2_H_
+
+#include <Protocol/MmCommunication.h>
+
+#define EFI_MM_COMMUNICATION2_PROTOCOL_GUID \
+  { \
+    0x378daedc, 0xf06b, 0x4446, { 0x83, 0x14, 0x40, 0xab, 0x93, 0x3c, 0x87, 0xa3 } \
+  }
+
+typedef struct _EFI_MM_COMMUNICATION2_PROTOCOL  EFI_MM_COMMUNICATION2_PROTOCOL;
+
+/**
+  Communicates with a registered handler.
+
+  This function provides a service to send and receive messages from a registered UEFI service.
+
+  @param[in] This                The EFI_MM_COMMUNICATION_PROTOCOL instance.
+  @param[in] CommBufferPhysical  Physical address of the MM communication buffer
+  @param[in] CommBufferVirtual   Virtual address of the MM communication buffer
+  @param[in] CommSize            The size of the data buffer being passed in. On exit, the size of data
+                                 being returned. Zero if the handler does not wish to reply with any data.
+                                 This parameter is optional and may be NULL.
+
+  @retval EFI_SUCCESS            The message was successfully posted.
+  @retval EFI_INVALID_PARAMETER  CommBufferPhysical was NULL or CommBufferVirtual was NULL.
+  @retval EFI_BAD_BUFFER_SIZE    The buffer is too large for the MM implementation.
+                                 If this error is returned, the MessageLength field
+                                 in the CommBuffer header or the integer pointed by
+                                 CommSize, are updated to reflect the maximum payload
+                                 size the implementation can accommodate.
+  @retval EFI_ACCESS_DENIED      The CommunicateBuffer parameter or CommSize parameter,
+                                 if not omitted, are in address range that cannot be
+                                 accessed by the MM environment.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_COMMUNICATE2)(
+  IN CONST EFI_MM_COMMUNICATION2_PROTOCOL   *This,
+  IN OUT VOID                               *CommBufferPhysical,
+  IN OUT VOID                               *CommBufferVirtual,
+  IN OUT UINTN                              *CommSize OPTIONAL
+  );
+
+///
+/// EFI MM Communication Protocol provides runtime services for communicating
+/// between DXE drivers and a registered MMI handler.
+///
+struct _EFI_MM_COMMUNICATION2_PROTOCOL {
+  EFI_MM_COMMUNICATE2  Communicate;
+};
+
+extern EFI_GUID gEfiMmCommunication2ProtocolGuid;
+
+#endif
+
diff --git a/MdePkg/Include/Protocol/MmConfiguration.h b/MdePkg/Include/Protocol/MmConfiguration.h
new file mode 100644
index 000000000000..bca926621358
--- /dev/null
+++ b/MdePkg/Include/Protocol/MmConfiguration.h
@@ -0,0 +1,80 @@
+/** @file
+  EFI MM Configuration Protocol as defined in the PI 1.5 specification.
+
+  This protocol is used to:
+  1) report the portions of MMRAM regions which cannot be used for the MMRAM heap.
+  2) register the MM Foundation entry point with the processor code. The entry
+     point will be invoked by the MM processor entry code.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _MM_CONFIGURATION_H_
+#define _MM_CONFIGURATION_H_
+
+#include <Pi/PiMmCis.h>
+
+#define EFI_MM_CONFIGURATION_PROTOCOL_GUID \
+  { \
+    0x26eeb3de, 0xb689, 0x492e, {0x80, 0xf0, 0xbe, 0x8b, 0xd7, 0xda, 0x4b, 0xa7 }  \
+  }
+
+///
+/// Structure describing a MMRAM region which cannot be used for the MMRAM heap.
+///
+typedef struct _EFI_MM_RESERVED_MMRAM_REGION {
+  ///
+  /// Starting address of the reserved MMRAM area, as it appears while MMRAM is open.
+  /// Ignored if MmramReservedSize is 0.
+  ///
+  EFI_PHYSICAL_ADDRESS    MmramReservedStart;
+  ///
+  /// Number of bytes occupied by the reserved MMRAM area. A size of zero indicates the
+  /// last MMRAM area.
+  ///
+  UINT64                  MmramReservedSize;
+} EFI_MM_RESERVED_MMRAM_REGION;
+
+typedef struct _EFI_MM_CONFIGURATION_PROTOCOL  EFI_MM_CONFIGURATION_PROTOCOL;
+
+/**
+  Register the MM Foundation entry point.
+
+  This function registers the MM Foundation entry point with the processor code. This entry point
+  will be invoked by the MM Processor entry code.
+
+  @param[in] This                The EFI_MM_CONFIGURATION_PROTOCOL instance.
+  @param[in] MmEntryPoint        MM Foundation entry point.
+
+  @retval EFI_SUCCESS            Success to register MM Entry Point.
+  @retval EFI_INVALID_PARAMETER  MmEntryPoint is NULL.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_REGISTER_MM_ENTRY)(
+  IN CONST EFI_MM_CONFIGURATION_PROTOCOL  *This,
+  IN EFI_MM_ENTRY_POINT                   MmEntryPoint
+  );
+
+///
+/// The EFI MM Configuration Protocol is a mandatory protocol published by a DXE CPU driver to
+/// indicate which areas within MMRAM are reserved for use by the CPU for any purpose,
+/// such as stack, save state or MM entry point.
+///
+/// The RegistermmEntry() function allows the MM IPL DXE driver to register the MM
+/// Foundation entry point with the MM entry vector code.
+///
+struct _EFI_MM_CONFIGURATION_PROTOCOL {
+  ///
+  /// A pointer to an array MMRAM ranges used by the initial MM entry code.
+  ///
+  EFI_MM_RESERVED_MMRAM_REGION  *MmramReservedRegions;
+  EFI_MM_REGISTER_MM_ENTRY      RegisterMmEntry;
+};
+
+extern EFI_GUID gEfiMmConfigurationProtocolGuid;
+
+#endif
+
diff --git a/MdePkg/Include/Protocol/MmControl.h b/MdePkg/Include/Protocol/MmControl.h
new file mode 100644
index 000000000000..92a5b10efb3d
--- /dev/null
+++ b/MdePkg/Include/Protocol/MmControl.h
@@ -0,0 +1,100 @@
+/** @file
+  EFI MM Control Protocol as defined in the PI 1.5 specification.
+
+  This protocol is used initiate synchronous MMI activations. This protocol could be published by a
+  processor driver to abstract the MMI IPI or a driver which abstracts the ASIC that is supporting the
+  APM port. Because of the possibility of performing MMI IPI transactions, the ability to generate this
+  event from a platform chipset agent is an optional capability for both IA-32 and x64-based systems.
+
+  The EFI_MM_CONTROL_PROTOCOL is produced by a runtime driver. It provides  an
+  abstraction of the platform hardware that generates an MMI.  There are often I/O ports that, when
+  accessed, will generate the MMI.  Also, the hardware optionally supports the periodic generation of
+  these signals.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _MM_CONTROL_H_
+#define _MM_CONTROL_H_
+
+#include <PiDxe.h>
+
+#define EFI_MM_CONTROL_PROTOCOL_GUID \
+  { \
+    0x843dc720, 0xab1e, 0x42cb, {0x93, 0x57, 0x8a, 0x0, 0x78, 0xf3, 0x56, 0x1b}  \
+  }
+
+typedef struct _EFI_MM_CONTROL_PROTOCOL  EFI_MM_CONTROL_PROTOCOL;
+typedef UINTN  EFI_MM_PERIOD;
+
+/**
+  Invokes MMI activation from either the preboot or runtime environment.
+
+  This function generates an MMI.
+
+  @param[in]     This                The EFI_MM_CONTROL_PROTOCOL instance.
+  @param[in,out] CommandPort         The value written to the command port.
+  @param[in,out] DataPort            The value written to the data port.
+  @param[in]     Periodic            Optional mechanism to engender a periodic stream.
+  @param[in]     ActivationInterval  Optional parameter to repeat at this period one
+                                     time or, if the Periodic Boolean is set, periodically.
+
+  @retval EFI_SUCCESS            The MMI/PMI has been engendered.
+  @retval EFI_DEVICE_ERROR       The timing is unsupported.
+  @retval EFI_INVALID_PARAMETER  The activation period is unsupported.
+  @retval EFI_INVALID_PARAMETER  The last periodic activation has not been cleared.
+  @retval EFI_NOT_STARTED        The MM base service has not been initialized.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_ACTIVATE)(
+  IN CONST EFI_MM_CONTROL_PROTOCOL    *This,
+  IN OUT UINT8                        *CommandPort       OPTIONAL,
+  IN OUT UINT8                        *DataPort          OPTIONAL,
+  IN BOOLEAN                          Periodic           OPTIONAL,
+  IN UINTN                            ActivationInterval OPTIONAL
+  );
+
+/**
+  Clears any system state that was created in response to the Trigger() call.
+
+  This function acknowledges and causes the deassertion of the MMI activation source.
+
+  @param[in] This                The EFI_MM_CONTROL_PROTOCOL instance.
+  @param[in] Periodic            Optional parameter to repeat at this period one time
+
+  @retval EFI_SUCCESS            The MMI/PMI has been engendered.
+  @retval EFI_DEVICE_ERROR       The source could not be cleared.
+  @retval EFI_INVALID_PARAMETER  The service did not support the Periodic input argument.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_DEACTIVATE)(
+  IN CONST EFI_MM_CONTROL_PROTOCOL    *This,
+  IN BOOLEAN                          Periodic OPTIONAL
+  );
+
+///
+/// The EFI_MM_CONTROL_PROTOCOL is produced by a runtime driver. It provides  an
+/// abstraction of the platform hardware that generates an MMI.  There are often I/O ports that, when
+/// accessed, will generate the MMI.  Also, the hardware optionally supports the periodic generation of
+/// these signals.
+///
+struct _EFI_MM_CONTROL_PROTOCOL {
+  EFI_MM_ACTIVATE    Trigger;
+  EFI_MM_DEACTIVATE  Clear;
+  ///
+  /// Minimum interval at which the platform can set the period.  A maximum is not
+  /// specified in that the MM infrastructure code can emulate a maximum interval that is
+  /// greater than the hardware capabilities by using software emulation in the MM
+  /// infrastructure code.
+  ///
+  EFI_MM_PERIOD      MinimumTriggerPeriod;
+};
+
+extern EFI_GUID gEfiMmControlProtocolGuid;
+
+#endif
+
diff --git a/MdePkg/Include/Protocol/MmCpu.h b/MdePkg/Include/Protocol/MmCpu.h
new file mode 100644
index 000000000000..37df7a5fb758
--- /dev/null
+++ b/MdePkg/Include/Protocol/MmCpu.h
@@ -0,0 +1,241 @@
+/** @file
+  EFI MM CPU Protocol as defined in the PI 1.5 specification.
+
+  This protocol allows MM drivers to access architecture-standard registers from any of the CPU
+  save state areas. In some cases, difference processors provide the same information in the save state,
+  but not in the same format. These so-called pseudo-registers provide this information in a standard
+  format.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _MM_CPU_H_
+#define _MM_CPU_H_
+
+#define EFI_MM_CPU_PROTOCOL_GUID \
+  { \
+    0xeb346b97, 0x975f, 0x4a9f, { 0x8b, 0x22, 0xf8, 0xe9, 0x2b, 0xb3, 0xd5, 0x69 } \
+  }
+
+///
+/// Save State register index
+///
+typedef enum {
+  ///
+  /// x86/X64 standard registers
+  ///
+  EFI_MM_SAVE_STATE_REGISTER_GDTBASE       = 4,
+  EFI_MM_SAVE_STATE_REGISTER_IDTBASE       = 5,
+  EFI_MM_SAVE_STATE_REGISTER_LDTBASE       = 6,
+  EFI_MM_SAVE_STATE_REGISTER_GDTLIMIT      = 7,
+  EFI_MM_SAVE_STATE_REGISTER_IDTLIMIT      = 8,
+  EFI_MM_SAVE_STATE_REGISTER_LDTLIMIT      = 9,
+  EFI_MM_SAVE_STATE_REGISTER_LDTINFO       = 10,
+  EFI_MM_SAVE_STATE_REGISTER_ES            = 20,
+  EFI_MM_SAVE_STATE_REGISTER_CS            = 21,
+  EFI_MM_SAVE_STATE_REGISTER_SS            = 22,
+  EFI_MM_SAVE_STATE_REGISTER_DS            = 23,
+  EFI_MM_SAVE_STATE_REGISTER_FS            = 24,
+  EFI_MM_SAVE_STATE_REGISTER_GS            = 25,
+  EFI_MM_SAVE_STATE_REGISTER_LDTR_SEL      = 26,
+  EFI_MM_SAVE_STATE_REGISTER_TR_SEL        = 27,
+  EFI_MM_SAVE_STATE_REGISTER_DR7           = 28,
+  EFI_MM_SAVE_STATE_REGISTER_DR6           = 29,
+  EFI_MM_SAVE_STATE_REGISTER_R8            = 30,
+  EFI_MM_SAVE_STATE_REGISTER_R9            = 31,
+  EFI_MM_SAVE_STATE_REGISTER_R10           = 32,
+  EFI_MM_SAVE_STATE_REGISTER_R11           = 33,
+  EFI_MM_SAVE_STATE_REGISTER_R12           = 34,
+  EFI_MM_SAVE_STATE_REGISTER_R13           = 35,
+  EFI_MM_SAVE_STATE_REGISTER_R14           = 36,
+  EFI_MM_SAVE_STATE_REGISTER_R15           = 37,
+  EFI_MM_SAVE_STATE_REGISTER_RAX           = 38,
+  EFI_MM_SAVE_STATE_REGISTER_RBX           = 39,
+  EFI_MM_SAVE_STATE_REGISTER_RCX           = 40,
+  EFI_MM_SAVE_STATE_REGISTER_RDX           = 41,
+  EFI_MM_SAVE_STATE_REGISTER_RSP           = 42,
+  EFI_MM_SAVE_STATE_REGISTER_RBP           = 43,
+  EFI_MM_SAVE_STATE_REGISTER_RSI           = 44,
+  EFI_MM_SAVE_STATE_REGISTER_RDI           = 45,
+  EFI_MM_SAVE_STATE_REGISTER_RIP           = 46,
+  EFI_MM_SAVE_STATE_REGISTER_RFLAGS        = 51,
+  EFI_MM_SAVE_STATE_REGISTER_CR0           = 52,
+  EFI_MM_SAVE_STATE_REGISTER_CR3           = 53,
+  EFI_MM_SAVE_STATE_REGISTER_CR4           = 54,
+  EFI_MM_SAVE_STATE_REGISTER_FCW           = 256,
+  EFI_MM_SAVE_STATE_REGISTER_FSW           = 257,
+  EFI_MM_SAVE_STATE_REGISTER_FTW           = 258,
+  EFI_MM_SAVE_STATE_REGISTER_OPCODE        = 259,
+  EFI_MM_SAVE_STATE_REGISTER_FP_EIP        = 260,
+  EFI_MM_SAVE_STATE_REGISTER_FP_CS         = 261,
+  EFI_MM_SAVE_STATE_REGISTER_DATAOFFSET    = 262,
+  EFI_MM_SAVE_STATE_REGISTER_FP_DS         = 263,
+  EFI_MM_SAVE_STATE_REGISTER_MM0           = 264,
+  EFI_MM_SAVE_STATE_REGISTER_MM1           = 265,
+  EFI_MM_SAVE_STATE_REGISTER_MM2           = 266,
+  EFI_MM_SAVE_STATE_REGISTER_MM3           = 267,
+  EFI_MM_SAVE_STATE_REGISTER_MM4           = 268,
+  EFI_MM_SAVE_STATE_REGISTER_MM5           = 269,
+  EFI_MM_SAVE_STATE_REGISTER_MM6           = 270,
+  EFI_MM_SAVE_STATE_REGISTER_MM7           = 271,
+  EFI_MM_SAVE_STATE_REGISTER_XMM0          = 272,
+  EFI_MM_SAVE_STATE_REGISTER_XMM1          = 273,
+  EFI_MM_SAVE_STATE_REGISTER_XMM2          = 274,
+  EFI_MM_SAVE_STATE_REGISTER_XMM3          = 275,
+  EFI_MM_SAVE_STATE_REGISTER_XMM4          = 276,
+  EFI_MM_SAVE_STATE_REGISTER_XMM5          = 277,
+  EFI_MM_SAVE_STATE_REGISTER_XMM6          = 278,
+  EFI_MM_SAVE_STATE_REGISTER_XMM7          = 279,
+  EFI_MM_SAVE_STATE_REGISTER_XMM8          = 280,
+  EFI_MM_SAVE_STATE_REGISTER_XMM9          = 281,
+  EFI_MM_SAVE_STATE_REGISTER_XMM10         = 282,
+  EFI_MM_SAVE_STATE_REGISTER_XMM11         = 283,
+  EFI_MM_SAVE_STATE_REGISTER_XMM12         = 284,
+  EFI_MM_SAVE_STATE_REGISTER_XMM13         = 285,
+  EFI_MM_SAVE_STATE_REGISTER_XMM14         = 286,
+  EFI_MM_SAVE_STATE_REGISTER_XMM15         = 287,
+  ///
+  /// Pseudo-Registers
+  ///
+  EFI_MM_SAVE_STATE_REGISTER_IO            = 512,
+  EFI_MM_SAVE_STATE_REGISTER_LMA           = 513,
+  EFI_MM_SAVE_STATE_REGISTER_PROCESSOR_ID  = 514
+} EFI_MM_SAVE_STATE_REGISTER;
+
+///
+/// The EFI_MM_SAVE_STATE_REGISTER_LMA pseudo-register values
+/// If the processor acts in 32-bit mode at the time the MMI occurred, the pseudo register value
+/// EFI_MM_SAVE_STATE_REGISTER_LMA_32BIT is returned in Buffer. Otherwise,
+/// EFI_MM_SAVE_STATE_REGISTER_LMA_64BIT is returned in Buffer.
+///
+#define EFI_MM_SAVE_STATE_REGISTER_LMA_32BIT  32
+#define EFI_MM_SAVE_STATE_REGISTER_LMA_64BIT  64
+
+///
+/// Size width of I/O instruction
+///
+typedef enum {
+  EFI_MM_SAVE_STATE_IO_WIDTH_UINT8      = 0,
+  EFI_MM_SAVE_STATE_IO_WIDTH_UINT16     = 1,
+  EFI_MM_SAVE_STATE_IO_WIDTH_UINT32     = 2,
+  EFI_MM_SAVE_STATE_IO_WIDTH_UINT64     = 3
+} EFI_MM_SAVE_STATE_IO_WIDTH;
+
+///
+/// Types of I/O instruction
+///
+typedef enum {
+  EFI_MM_SAVE_STATE_IO_TYPE_INPUT       = 1,
+  EFI_MM_SAVE_STATE_IO_TYPE_OUTPUT      = 2,
+  EFI_MM_SAVE_STATE_IO_TYPE_STRING      = 4,
+  EFI_MM_SAVE_STATE_IO_TYPE_REP_PREFIX  = 8
+} EFI_MM_SAVE_STATE_IO_TYPE;
+
+///
+/// Structure of the data which is returned when ReadSaveState() is called with
+/// EFI_MM_SAVE_STATE_REGISTER_IO. If there was no I/O then ReadSaveState() will
+/// return EFI_NOT_FOUND.
+///
+/// This structure describes the I/O operation which was in process when the MMI was generated.
+///
+typedef struct _EFI_MM_SAVE_STATE_IO_INFO {
+  ///
+  /// For input instruction (IN, INS), this is data read before the MMI occurred. For output
+  /// instructions (OUT, OUTS) this is data that was written before the MMI occurred. The
+  /// width of the data is specified by IoWidth.
+  ///
+  UINT64                        IoData;
+  ///
+  /// The I/O port that was being accessed when the MMI was triggered.
+  ///
+  UINT16                        IoPort;
+  ///
+  /// Defines the size width (UINT8, UINT16, UINT32, UINT64) for IoData.
+  ///
+  EFI_MM_SAVE_STATE_IO_WIDTH    IoWidth;
+  ///
+  /// Defines type of I/O instruction.
+  ///
+  EFI_MM_SAVE_STATE_IO_TYPE     IoType;
+} EFI_MM_SAVE_STATE_IO_INFO;
+
+typedef struct _EFI_MM_CPU_PROTOCOL  EFI_MM_CPU_PROTOCOL;
+
+/**
+  Read data from the CPU save state.
+
+  This function is used to read the specified number of bytes of the specified register from the CPU
+  save state of the specified CPU and place the value into the buffer. If the CPU does not support the
+  specified register Register, then EFI_NOT_FOUND  should be returned. If the CPU does not
+  support the specified register width Width, then EFI_INVALID_PARAMETER is returned.
+
+  @param[in]  This               The EFI_MM_CPU_PROTOCOL instance.
+  @param[in]  Width              The number of bytes to read from the CPU save state.
+  @param[in]  Register           Specifies the CPU register to read form the save state.
+  @param[in]  CpuIndex           Specifies the zero-based index of the CPU save state.
+  @param[out] Buffer             Upon return, this holds the CPU register value read from the save state.
+
+  @retval EFI_SUCCESS            The register was read from Save State.
+  @retval EFI_NOT_FOUND          The register is not defined for the Save State of Processor.
+  @retval EFI_INVALID_PARAMETER  Input parameters are not valid, for example, Processor No or register width
+                                 is not correct.This or Buffer is NULL.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_READ_SAVE_STATE)(
+  IN CONST EFI_MM_CPU_PROTOCOL    *This,
+  IN UINTN                        Width,
+  IN EFI_MM_SAVE_STATE_REGISTER   Register,
+  IN UINTN                        CpuIndex,
+  OUT VOID                        *Buffer
+  );
+
+
+/**
+  Write data to the CPU save state.
+
+  This function is used to write the specified number of bytes of the specified register to the CPU save
+  state of the specified CPU and place the value into the buffer. If the CPU does not support the
+  specified register Register, then EFI_UNSUPPORTED should be returned. If the CPU does not
+  support the specified register width Width, then EFI_INVALID_PARAMETER is returned.
+
+  @param[in]  This               The EFI_MM_CPU_PROTOCOL instance.
+  @param[in]  Width              The number of bytes to write to the CPU save state.
+  @param[in]  Register           Specifies the CPU register to write to the save state.
+  @param[in]  CpuIndex           Specifies the zero-based index of the CPU save state.
+  @param[in]  Buffer             Upon entry, this holds the new CPU register value.
+
+  @retval EFI_SUCCESS            The register was written to Save State.
+  @retval EFI_NOT_FOUND          The register is not defined for the Save State of Processor.
+  @retval EFI_INVALID_PARAMETER  Input parameters are not valid. For example:
+                                 ProcessorIndex or Width is not correct.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_WRITE_SAVE_STATE)(
+  IN CONST EFI_MM_CPU_PROTOCOL    *This,
+  IN UINTN                        Width,
+  IN EFI_MM_SAVE_STATE_REGISTER   Register,
+  IN UINTN                        CpuIndex,
+  IN CONST VOID                   *Buffer
+  );
+
+///
+/// EFI MM CPU Protocol provides access to CPU-related information while in MM.
+///
+/// This protocol allows MM drivers to access architecture-standard registers from any of the CPU
+/// save state areas. In some cases, difference processors provide the same information in the save state,
+/// but not in the same format. These so-called pseudo-registers provide this information in a standard
+/// format.
+///
+struct _EFI_MM_CPU_PROTOCOL {
+  EFI_MM_READ_SAVE_STATE   ReadSaveState;
+  EFI_MM_WRITE_SAVE_STATE  WriteSaveState;
+};
+
+extern EFI_GUID gEfiMmCpuProtocolGuid;
+
+#endif
+
diff --git a/MdePkg/Include/Protocol/MmCpuIo.h b/MdePkg/Include/Protocol/MmCpuIo.h
new file mode 100644
index 000000000000..f0e7ec6e877b
--- /dev/null
+++ b/MdePkg/Include/Protocol/MmCpuIo.h
@@ -0,0 +1,90 @@
+/** @file
+  MM CPU I/O 2 protocol as defined in the PI 1.5 specification.
+
+  This protocol provides CPU I/O and memory access within MM.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _MM_CPU_IO_H_
+#define _MM_CPU_IO_H_
+
+#define EFI_MM_CPU_IO_PROTOCOL_GUID \
+  { \
+    0x3242A9D8, 0xCE70, 0x4AA0, { 0x95, 0x5D, 0x5E, 0x7B, 0x14, 0x0D, 0xE4, 0xD2 } \
+  }
+
+typedef struct _EFI_MM_CPU_IO_PROTOCOL  EFI_MM_CPU_IO_PROTOCOL;
+
+///
+/// Width of the MM CPU I/O operations
+///
+typedef enum {
+  MM_IO_UINT8  = 0,
+  MM_IO_UINT16 = 1,
+  MM_IO_UINT32 = 2,
+  MM_IO_UINT64 = 3
+} EFI_MM_IO_WIDTH;
+
+/**
+  Provides the basic memory and I/O interfaces used toabstract accesses to devices.
+
+  The I/O operations are carried out exactly as requested.  The caller is
+  responsible for any alignment and I/O width issues that the bus, device,
+  platform, or type of I/O might require.
+
+  @param[in]      This     The EFI_MM_CPU_IO_PROTOCOL instance.
+  @param[in]      Width    Signifies the width of the I/O operations.
+  @param[in]      Address  The base address of the I/O operations.  The caller is
+                           responsible for aligning the Address if required.
+  @param[in]      Count    The number of I/O operations to perform.
+  @param[in,out]  Buffer   For read operations, the destination buffer to store
+                           the results.  For write operations, the source buffer
+                           from which to write data.
+
+  @retval EFI_SUCCESS            The data was read from or written to the device.
+  @retval EFI_UNSUPPORTED        The Address is not valid for this system.
+  @retval EFI_INVALID_PARAMETER  Width or Count, or both, were invalid.
+  @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack
+                                 of resources.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_CPU_IO)(
+  IN     CONST EFI_MM_CPU_IO_PROTOCOL    *This,
+  IN     EFI_MM_IO_WIDTH                 Width,
+  IN     UINT64                          Address,
+  IN     UINTN                           Count,
+  IN OUT VOID                            *Buffer
+  );
+
+typedef struct {
+  ///
+  /// This service provides the various modalities of memory and I/O read.
+  ///
+  EFI_MM_CPU_IO  Read;
+  ///
+  /// This service provides the various modalities of memory and I/O write.
+  ///
+  EFI_MM_CPU_IO  Write;
+} EFI_MM_IO_ACCESS;
+
+///
+/// MM CPU I/O Protocol provides CPU I/O and memory access within MM.
+///
+struct _EFI_MM_CPU_IO_PROTOCOL {
+  ///
+  /// Allows reads and writes to memory-mapped I/O space.
+  ///
+  EFI_MM_IO_ACCESS Mem;
+  ///
+  /// Allows reads and writes to I/O space.
+  ///
+  EFI_MM_IO_ACCESS Io;
+};
+
+extern EFI_GUID gEfiMmCpuIoProtocolGuid;
+
+#endif
diff --git a/MdePkg/Include/Protocol/MmEndOfDxe.h b/MdePkg/Include/Protocol/MmEndOfDxe.h
new file mode 100644
index 000000000000..74f8427efe85
--- /dev/null
+++ b/MdePkg/Include/Protocol/MmEndOfDxe.h
@@ -0,0 +1,24 @@
+/** @file
+  MM End Of Dxe protocol introduced in the PI 1.5 specification.
+
+  This protocol is a mandatory protocol published by MM Foundation code.
+  This protocol is an MM counterpart of the End of DXE Event.
+  This protocol prorogates End of DXE notification into MM environment.
+  This protocol is installed prior to installation of the MM Ready to Lock Protocol.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _MM_END_OF_DXE_H_
+#define _MM_END_OF_DXE_H_
+
+#define EFI_MM_END_OF_DXE_PROTOCOL_GUID \
+  { \
+    0x24e70042, 0xd5c5, 0x4260, { 0x8c, 0x39, 0xa, 0xd3, 0xaa, 0x32, 0xe9, 0x3d } \
+  }
+
+extern EFI_GUID gEfiMmEndOfDxeProtocolGuid;
+
+#endif
diff --git a/MdePkg/Include/Protocol/MmGpiDispatch.h b/MdePkg/Include/Protocol/MmGpiDispatch.h
new file mode 100644
index 000000000000..877c0e2a2400
--- /dev/null
+++ b/MdePkg/Include/Protocol/MmGpiDispatch.h
@@ -0,0 +1,119 @@
+/** @file
+  MM General Purpose Input (GPI) Dispatch Protocol as defined in PI 1.5 Specification
+  Volume 4 Management Mode Core Interface.
+
+  This protocol provides the parent dispatch service for the General Purpose Input
+  (GPI) MMI source generator.
+
+  The EFI_MM_GPI_DISPATCH_PROTOCOL provides the ability to install child handlers for the
+  given event types.  Several inputs can be enabled.  This purpose of this interface is to generate an
+  MMI in response to any of these inputs having a true value provided.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  This protocol is from PI Version 1.5.
+
+**/
+
+#ifndef _MM_GPI_DISPATCH_H_
+#define _MM_GPI_DISPATCH_H_
+
+#include <Pi/PiMmCis.h>
+
+#define EFI_MM_GPI_DISPATCH_PROTOCOL_GUID \
+  { \
+    0x25566b03, 0xb577, 0x4cbf, {0x95, 0x8c, 0xed, 0x66, 0x3e, 0xa2, 0x43, 0x80 } \
+  }
+
+///
+/// The dispatch function's context.
+///
+typedef struct {
+  ///
+  /// A number from one of 2^64 possible GPIs that can generate an MMI. A
+  /// 0 corresponds to logical GPI[0]; 1 corresponds to logical GPI[1]; and
+  /// GpiNum of N corresponds to GPI[N], where N can span from 0 to 2^64-1.
+  ///
+  UINT64 GpiNum;
+} EFI_MM_GPI_REGISTER_CONTEXT;
+
+typedef struct _EFI_MM_GPI_DISPATCH_PROTOCOL EFI_MM_GPI_DISPATCH_PROTOCOL;
+
+/**
+  Registers a child MMI source dispatch function with a parent MM driver.
+
+  This service registers a function (DispatchFunction) which will be called when an MMI is
+  generated because of one or more of the GPIs specified by RegisterContext. On return,
+  DispatchHandle contains a unique handle which may be used later to unregister the function
+  using UnRegister().
+  The DispatchFunction will be called with Context set to the same value as was passed into
+  this function in RegisterContext and with CommBuffer pointing to another instance of
+  EFI_MM_GPI_REGISTER_CONTEXT describing the GPIs which actually caused the MMI and
+  CommBufferSize pointing to the size of the structure.
+
+  @param[in]  This               Pointer to the EFI_MM_GPI_DISPATCH_PROTOCOL instance.
+  @param[in]  DispatchFunction   Function to register for handler when the specified GPI causes an MMI.
+  @param[in]  RegisterContext    Pointer to the dispatch function's context.
+                                 The caller fills this context in before calling
+                                 the register function to indicate to the register
+                                 function the GPI(s) for which the dispatch function
+                                 should be invoked.
+  @param[out] DispatchHandle     Handle generated by the dispatcher to track the
+                                 function instance.
+
+  @retval EFI_SUCCESS            The dispatch function has been successfully
+                                 registered and the MMI source has been enabled.
+  @retval EFI_DEVICE_ERROR       The driver was unable to enable the MMI source.
+  @retval EFI_INVALID_PARAMETER  RegisterContext is invalid. The GPI input value
+                                 is not within valid range.
+  @retval EFI_OUT_OF_RESOURCES   There is not enough memory (system or MM) to manage this child.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_GPI_REGISTER)(
+  IN CONST EFI_MM_GPI_DISPATCH_PROTOCOL    *This,
+  IN       EFI_MM_HANDLER_ENTRY_POINT      DispatchFunction,
+  IN CONST EFI_MM_GPI_REGISTER_CONTEXT     *RegisterContext,
+  OUT      EFI_HANDLE                      *DispatchHandle
+  );
+
+/**
+  Unregisters a General Purpose Input (GPI) service.
+
+  This service removes the handler associated with DispatchHandle so that it will no longer be
+  called when the GPI triggers an MMI.
+
+  @param[in]  This               Pointer to the EFI_MM_GPI_DISPATCH_PROTOCOL instance.
+  @param[in]  DispatchHandle     Handle of the service to remove.
+
+  @retval EFI_SUCCESS            Handle of the service to remove.
+  @retval EFI_INVALID_PARAMETER  The DispatchHandle was not valid.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_GPI_UNREGISTER)(
+  IN CONST EFI_MM_GPI_DISPATCH_PROTOCOL    *This,
+  IN       EFI_HANDLE                      DispatchHandle
+  );
+
+///
+/// Interface structure for the MM GPI MMI Dispatch Protocol
+///
+/// The MM GPI MMI Dispatch Protocol provides the parent dispatch service
+/// for the General Purpose Input (GPI) MMI source generator.
+///
+struct _EFI_MM_GPI_DISPATCH_PROTOCOL {
+  EFI_MM_GPI_REGISTER    Register;
+  EFI_MM_GPI_UNREGISTER  UnRegister;
+  ///
+  /// Denotes the maximum value of inputs that can have handlers attached.
+  ///
+  UINTN                   NumSupportedGpis;
+};
+
+extern EFI_GUID gEfiMmGpiDispatchProtocolGuid;
+
+#endif
+
diff --git a/MdePkg/Include/Protocol/MmIoTrapDispatch.h b/MdePkg/Include/Protocol/MmIoTrapDispatch.h
new file mode 100644
index 000000000000..4434645035e3
--- /dev/null
+++ b/MdePkg/Include/Protocol/MmIoTrapDispatch.h
@@ -0,0 +1,130 @@
+/** @file
+  MM IO Trap Dispatch Protocol as defined in PI 1.5 Specification
+  Volume 4 Management Mode Core Interface.
+
+  This protocol provides a parent dispatch service for IO trap MMI sources.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  This protocol is from PI Version 1.5.
+
+**/
+
+#ifndef _MM_IO_TRAP_DISPATCH_H_
+#define _MM_IO_TRAP_DISPATCH_H_
+
+#include <Pi/PiMmCis.h>
+
+#define EFI_MM_IO_TRAP_DISPATCH_PROTOCOL_GUID \
+  { \
+    0x58dc368d, 0x7bfa, 0x4e77, {0xab, 0xbc, 0xe, 0x29, 0x41, 0x8d, 0xf9, 0x30 } \
+  }
+
+///
+/// IO Trap valid types
+///
+typedef enum {
+  WriteTrap,
+  ReadTrap,
+  ReadWriteTrap,
+  IoTrapTypeMaximum
+} EFI_MM_IO_TRAP_DISPATCH_TYPE;
+
+///
+/// IO Trap context structure containing information about the
+/// IO trap event that should invoke the handler
+///
+typedef struct {
+  UINT16                         Address;
+  UINT16                         Length;
+  EFI_MM_IO_TRAP_DISPATCH_TYPE   Type;
+} EFI_MM_IO_TRAP_REGISTER_CONTEXT;
+
+///
+/// IO Trap context structure containing information about the IO trap that occurred
+///
+typedef struct {
+  UINT32  WriteData;
+} EFI_MM_IO_TRAP_CONTEXT;
+
+typedef struct _EFI_MM_IO_TRAP_DISPATCH_PROTOCOL EFI_MM_IO_TRAP_DISPATCH_PROTOCOL;
+
+/**
+  Register an IO trap MMI child handler for a specified MMI.
+
+  This service registers a function (DispatchFunction) which will be called when an MMI is
+  generated because of an access to an I/O port specified by RegisterContext. On return,
+  DispatchHandle contains a unique handle which may be used later to unregister the function
+  using UnRegister(). If the base of the I/O range specified is zero, then an I/O range with the
+  specified length and characteristics will be allocated and the Address field in RegisterContext
+  updated. If no range could be allocated, then EFI_OUT_OF_RESOURCES will be returned.
+
+  The service will not perform GCD allocation if the base address is non-zero or
+  EFI_MM_READY_TO_LOCK has been installed.  In this case, the caller is responsible for the
+  existence and allocation of the specific IO range.
+  An error may be returned if some or all of the requested resources conflict with an existing IO trap
+  child handler.
+
+  It is not required that implementations will allow multiple children for a single IO trap MMI source.
+  Some implementations may support multiple children.
+  The DispatchFunction will be called with Context updated to contain information
+  concerning the I/O action that actually happened and is passed in RegisterContext, with
+  CommBuffer pointing to the data actually written and CommBufferSize pointing to the size of
+  the data in CommBuffer.
+
+  @param[in]  This               Pointer to the EFI_MM_IO_TRAP_DISPATCH_PROTOCOL instance.
+  @param[in]  DispatchFunction   Function to register for handler when I/O trap location is accessed.
+  @param[in]  RegisterContext    Pointer to the dispatch function's context.  The caller fills this
+                                 context in before calling the register function to indicate to the register
+                                 function the IO trap MMI source for which the dispatch function should be invoked.
+  @param[out] DispatchHandle     Handle of the dispatch function, for when interfacing with the parent MM driver.
+
+  @retval EFI_SUCCESS            The dispatch function has been successfully registered.
+  @retval EFI_DEVICE_ERROR       The driver was unable to complete due to hardware error.
+  @retval EFI_OUT_OF_RESOURCES   Insufficient resources are available to fulfill the IO trap range request.
+  @retval EFI_INVALID_PARAMETER  RegisterContext is invalid.  The input value is not within a valid range.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_IO_TRAP_DISPATCH_REGISTER)(
+  IN CONST EFI_MM_IO_TRAP_DISPATCH_PROTOCOL    *This,
+  IN       EFI_MM_HANDLER_ENTRY_POINT          DispatchFunction,
+  IN OUT   EFI_MM_IO_TRAP_REGISTER_CONTEXT     *RegisterContext,
+     OUT   EFI_HANDLE                          *DispatchHandle
+  );
+
+/**
+  Unregister a child MMI source dispatch function with a parent MM driver.
+
+  This service removes a previously installed child dispatch handler. This does not guarantee that the
+  system resources will be freed from the GCD.
+
+  @param[in] This                Pointer to the EFI_MM_IO_TRAP_DISPATCH_PROTOCOL instance.
+  @param[in] DispatchHandle      Handle of the child service to remove.
+
+  @retval EFI_SUCCESS            The dispatch function has been successfully unregistered.
+  @retval EFI_INVALID_PARAMETER  The DispatchHandle was not valid.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_IO_TRAP_DISPATCH_UNREGISTER)(
+  IN CONST EFI_MM_IO_TRAP_DISPATCH_PROTOCOL    *This,
+  IN       EFI_HANDLE                          DispatchHandle
+  );
+
+///
+/// Interface structure for the MM IO Trap Dispatch Protocol.
+///
+/// This protocol provides a parent dispatch service for IO trap MMI sources.
+///
+struct _EFI_MM_IO_TRAP_DISPATCH_PROTOCOL {
+  EFI_MM_IO_TRAP_DISPATCH_REGISTER    Register;
+  EFI_MM_IO_TRAP_DISPATCH_UNREGISTER  UnRegister;
+};
+
+extern EFI_GUID gEfiMmIoTrapDispatchProtocolGuid;
+
+#endif
+
diff --git a/MdePkg/Include/Protocol/MmMp.h b/MdePkg/Include/Protocol/MmMp.h
new file mode 100644
index 000000000000..4f67ffcf3011
--- /dev/null
+++ b/MdePkg/Include/Protocol/MmMp.h
@@ -0,0 +1,333 @@
+/** @file
+  EFI MM MP Protocol is defined in the PI 1.5 specification.
+
+  The MM MP protocol provides a set of functions to allow execution of procedures on processors that
+  have entered MM. This protocol has the following properties:
+  1. The caller can only invoke execution of a procedure on a processor, other than the caller, that
+     has also entered MM.
+  2. It is possible to invoke a procedure on multiple processors. Supports blocking and non-blocking
+     modes of operation.
+
+  Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _MM_MP_H_
+#define _MM_MP_H_
+
+#include <Pi/PiMmCis.h>
+
+#define EFI_MM_MP_PROTOCOL_GUID \
+  { \
+    0x5d5450d7, 0x990c, 0x4180, {0xa8, 0x3, 0x8e, 0x63, 0xf0, 0x60, 0x83, 0x7  }  \
+  }
+
+//
+// Revision definition.
+//
+#define EFI_MM_MP_PROTOCOL_REVISION    0x00
+
+//
+// Attribute flags
+//
+#define EFI_MM_MP_TIMEOUT_SUPPORTED    0x01
+
+//
+// Completion token
+//
+typedef VOID* MM_COMPLETION;
+
+typedef struct {
+  MM_COMPLETION  Completion;
+  EFI_STATUS     Status;
+} MM_DISPATCH_COMPLETION_TOKEN;
+
+typedef struct _EFI_MM_MP_PROTOCOL  EFI_MM_MP_PROTOCOL;
+
+/**
+  Service to retrieves the number of logical processor in the platform.
+
+  @param[in]  This                The EFI_MM_MP_PROTOCOL instance.
+  @param[out] NumberOfProcessors  Pointer to the total number of logical processors in the system,
+                                  including the BSP and all APs.
+
+  @retval EFI_SUCCESS             The number of processors was retrieved successfully
+  @retval EFI_INVALID_PARAMETER   NumberOfProcessors is NULL
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_GET_NUMBER_OF_PROCESSORS) (
+  IN CONST EFI_MM_MP_PROTOCOL  *This,
+  OUT      UINTN               *NumberOfProcessors
+);
+
+
+/**
+  This service allows the caller to invoke a procedure one of the application processors (AP). This
+  function uses an optional token parameter to support blocking and non-blocking modes. If the token
+  is passed into the call, the function will operate in a non-blocking fashion and the caller can
+  check for completion with CheckOnProcedure or WaitForProcedure.
+
+  @param[in]     This                   The EFI_MM_MP_PROTOCOL instance.
+  @param[in]     Procedure              A pointer to the procedure to be run on the designated target
+                                        AP of the system. Type EFI_AP_PROCEDURE2 is defined below in
+                                        related definitions.
+  @param[in]     CpuNumber              The zero-based index of the processor number of the target
+                                        AP, on which the code stream is supposed to run. If the number
+                                        points to the calling processor then it will not run the
+                                        supplied code.
+  @param[in]     TimeoutInMicroseconds  Indicates the time limit in microseconds for this AP to
+                                        finish execution of Procedure, either for blocking or
+                                        non-blocking mode. Zero means infinity. If the timeout
+                                        expires before this AP returns from Procedure, then Procedure
+                                        on the AP is terminated. If the timeout expires in blocking
+                                        mode, the call returns EFI_TIMEOUT. If the timeout expires
+                                        in non-blocking mode, the timeout determined can be through
+                                        CheckOnProcedure or WaitForProcedure.
+                                        Note that timeout support is optional. Whether an
+                                        implementation supports this feature, can be determined via
+                                        the Attributes data member.
+  @param[in,out] ProcedureArguments     Allows the caller to pass a list of parameters to the code
+                                        that is run by the AP. It is an optional common mailbox
+                                        between APs and the caller to share information.
+  @param[in,out] Token                  This is parameter is broken into two components:
+                                        1.Token->Completion is an optional parameter that allows the
+                                        caller to execute the procedure in a blocking or non-blocking
+                                        fashion. If it is NULL the call is blocking, and the call will
+                                        not return until the AP has completed the procedure. If the
+                                        token is not NULL, the call will return immediately. The caller
+                                        can check whether the procedure has completed with
+                                        CheckOnProcedure or WaitForProcedure.
+                                        2.Token->Status The implementation updates the address pointed
+                                        at by this variable with the status code returned by Procedure
+                                        when it completes execution on the target AP, or with EFI_TIMEOUT
+                                        if the Procedure fails to complete within the optional timeout.
+                                        The implementation will update this variable with EFI_NOT_READY
+                                        prior to starting Procedure on the target AP.
+  @param[in,out] CPUStatus              This optional pointer may be used to get the status code returned
+                                        by Procedure when it completes execution on the target AP, or with
+                                        EFI_TIMEOUT if the Procedure fails to complete within the optional
+                                        timeout. The implementation will update this variable with
+                                        EFI_NOT_READY prior to starting Procedure on the target AP.
+
+  @retval EFI_SUCCESS                   In the blocking case, this indicates that Procedure has completed
+                                        execution on the target AP.
+                                        In the non-blocking case this indicates that the procedure has
+                                        been successfully scheduled for execution on the target AP.
+  @retval EFI_INVALID_PARAMETER         The input arguments are out of range. Either the target AP is the
+                                        caller of the function, or the Procedure or Token is NULL
+  @retval EFI_NOT_READY                 If the target AP is busy executing another procedure
+  @retval EFI_ALREADY_STARTED           Token is already in use for another procedure
+  @retval EFI_TIMEOUT                   In blocking mode, the timeout expired before the specified AP
+                                        has finished
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_DISPATCH_PROCEDURE) (
+  IN CONST EFI_MM_MP_PROTOCOL            *This,
+  IN       EFI_AP_PROCEDURE2             Procedure,
+  IN       UINTN                         CpuNumber,
+  IN       UINTN                         TimeoutInMicroseconds,
+  IN OUT   VOID                          *ProcedureArguments OPTIONAL,
+  IN OUT   MM_COMPLETION                 *Token,
+  IN OUT   EFI_STATUS                    *CPUStatus
+);
+
+/**
+  This service allows the caller to invoke a procedure on all running application processors (AP)
+  except the caller. This function uses an optional token parameter to support blocking and
+  nonblocking modes. If the token is passed into the call, the function will operate in a non-blocking
+  fashion and the caller can check for completion with CheckOnProcedure or WaitForProcedure.
+
+  It is not necessary for the implementation to run the procedure on every processor on the platform.
+  Processors that are powered down in such a way that they cannot respond to interrupts, may be
+  excluded from the broadcast.
+
+
+  @param[in]     This                   The EFI_MM_MP_PROTOCOL instance.
+  @param[in]     Procedure              A pointer to the code stream to be run on the APs that have
+                                        entered MM. Type EFI_AP_PROCEDURE is defined below in related
+                                        definitions.
+  @param[in]     TimeoutInMicroseconds  Indicates the time limit in microseconds for the APs to finish
+                                        execution of Procedure, either for blocking or non-blocking mode.
+                                        Zero means infinity. If the timeout expires before all APs return
+                                        from Procedure, then Procedure on the failed APs is terminated. If
+                                        the timeout expires in blocking mode, the call returns EFI_TIMEOUT.
+                                        If the timeout expires in non-blocking mode, the timeout determined
+                                        can be through CheckOnProcedure or WaitForProcedure.
+                                        Note that timeout support is optional. Whether an implementation
+                                        supports this feature can be determined via the Attributes data
+                                        member.
+  @param[in,out] ProcedureArguments     Allows the caller to pass a list of parameters to the code
+                                        that is run by the AP. It is an optional common mailbox
+                                        between APs and the caller to share information.
+  @param[in,out] Token                  This is parameter is broken into two components:
+                                        1.Token->Completion is an optional parameter that allows the
+                                        caller to execute the procedure in a blocking or non-blocking
+                                        fashion. If it is NULL the call is blocking, and the call will
+                                        not return until the AP has completed the procedure. If the
+                                        token is not NULL, the call will return immediately. The caller
+                                        can check whether the procedure has completed with
+                                        CheckOnProcedure or WaitForProcedure.
+                                        2.Token->Status The implementation updates the address pointed
+                                        at by this variable with the status code returned by Procedure
+                                        when it completes execution on the target AP, or with EFI_TIMEOUT
+                                        if the Procedure fails to complete within the optional timeout.
+                                        The implementation will update this variable with EFI_NOT_READY
+                                        prior to starting Procedure on the target AP
+  @param[in,out] CPUStatus              This optional pointer may be used to get the individual status
+                                        returned by every AP that participated in the broadcast. This
+                                        parameter if used provides the base address of an array to hold
+                                        the EFI_STATUS value of each AP in the system. The size of the
+                                        array can be ascertained by the GetNumberOfProcessors function.
+                                        As mentioned above, the broadcast may not include every processor
+                                        in the system. Some implementations may exclude processors that
+                                        have been powered down in such a way that they are not responsive
+                                        to interrupts. Additionally the broadcast excludes the processor
+                                        which is making the BroadcastProcedure call. For every excluded
+                                        processor, the array entry must contain a value of EFI_NOT_STARTED
+
+  @retval EFI_SUCCESS                   In the blocking case, this indicates that Procedure has completed
+                                        execution on the APs. In the non-blocking case this indicates that
+                                        the procedure has been successfully scheduled for execution on the
+                                        APs.
+  @retval EFI_INVALID_PARAMETER         Procedure or Token is NULL.
+  @retval EFI_NOT_READY                 If a target AP is busy executing another procedure.
+  @retval EFI_TIMEOUT                   In blocking mode, the timeout expired before all enabled APs have
+                                        finished.
+  @retval EFI_ALREADY_STARTED           Before the AP procedure associated with the Token is finished, the
+                                        same Token cannot be used to dispatch or broadcast another procedure.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_BROADCAST_PROCEDURE) (
+  IN CONST EFI_MM_MP_PROTOCOL            *This,
+  IN       EFI_AP_PROCEDURE2             Procedure,
+  IN       UINTN                         TimeoutInMicroseconds,
+  IN OUT   VOID                          *ProcedureArguments OPTIONAL,
+  IN OUT   MM_COMPLETION                 *Token,
+  IN OUT   EFI_STATUS                    *CPUStatus
+);
+
+
+/**
+  This service allows the caller to set a startup procedure that will be executed when an AP powers
+  up from a state where core configuration and context is lost. The procedure is execution has the
+  following properties:
+  1. The procedure executes before the processor is handed over to the operating system.
+  2. All processors execute the same startup procedure.
+  3. The procedure may run in parallel with other procedures invoked through the functions in this
+  protocol, or with processors that are executing an MM handler or running in the operating system.
+
+
+  @param[in]      This                 The EFI_MM_MP_PROTOCOL instance.
+  @param[in]      Procedure            A pointer to the code stream to be run on the designated target AP
+                                       of the system. Type EFI_AP_PROCEDURE is defined below in Volume 2
+                                       with the related definitions of
+                                       EFI_MP_SERVICES_PROTOCOL.StartupAllAPs.
+                                       If caller may pass a value of NULL to deregister any existing
+                                       startup procedure.
+  @param[in,out]  ProcedureArguments   Allows the caller to pass a list of parameters to the code that is
+                                       run by the AP. It is an optional common mailbox between APs and
+                                       the caller to share information
+
+  @retval EFI_SUCCESS                  The Procedure has been set successfully.
+  @retval EFI_INVALID_PARAMETER        The Procedure is NULL.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_SET_STARTUP_PROCEDURE) (
+  IN CONST EFI_MM_MP_PROTOCOL *This,
+  IN       EFI_AP_PROCEDURE   Procedure,
+  IN OUT   VOID               *ProcedureArguments OPTIONAL
+);
+
+/**
+  When non-blocking execution of a procedure on an AP is invoked with DispatchProcedure,
+  via the use of a token, this function can be used to check for completion of the procedure on the AP.
+  The function takes the token that was passed into the DispatchProcedure call. If the procedure
+  is complete, and therefore it is now possible to run another procedure on the same AP, this function
+  returns EFI_SUCESS. In this case the status returned by the procedure that executed on the AP is
+  returned in the token's Status field. If the procedure has not yet completed, then this function
+  returns EFI_NOT_READY.
+
+  When a non-blocking execution of a procedure is invoked with BroadcastProcedure, via the
+  use of a token, this function can be used to check for completion of the procedure on all the
+  broadcast APs. The function takes the token that was passed into the BroadcastProcedure
+  call. If the procedure is complete on all broadcast APs this function returns EFI_SUCESS. In this
+  case the Status field in the token passed into the function reflects the overall result of the
+  invocation, which may be EFI_SUCCESS, if all executions succeeded, or the first observed failure.
+  If the procedure has not yet completed on the broadcast APs, the function returns
+  EFI_NOT_READY.
+
+  @param[in]      This                 The EFI_MM_MP_PROTOCOL instance.
+  @param[in]      Token                This parameter describes the token that was passed into
+                                       DispatchProcedure or BroadcastProcedure.
+
+  @retval EFI_SUCCESS                  Procedure has completed.
+  @retval EFI_NOT_READY                The Procedure has not completed.
+  @retval EFI_INVALID_PARAMETER        Token or Token->Completion is NULL
+  @retval EFI_NOT_FOUND                Token is not currently in use for a non-blocking call
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_CHECK_FOR_PROCEDURE) (
+  IN CONST EFI_MM_MP_PROTOCOL            *This,
+  IN       MM_COMPLETION                 Token
+);
+
+/**
+  When a non-blocking execution of a procedure on an AP is invoked via DispatchProcedure,
+  this function will block the caller until the remote procedure has completed on the designated AP.
+  The non-blocking procedure invocation is identified by the Token parameter, which must match the
+  token that used when DispatchProcedure was called. Upon completion the status returned by
+  the procedure that executed on the AP is used to update the token's Status field.
+
+  When a non-blocking execution of a procedure on an AP is invoked via BroadcastProcedure
+  this function will block the caller until the remote procedure has completed on all of the APs that
+  entered MM. The non-blocking procedure invocation is identified by the Token parameter, which
+  must match the token that used when BroadcastProcedure was called. Upon completion the
+  overall status returned by the procedures that executed on the broadcast AP is used to update the
+  token's Status field. The overall status may be EFI_SUCCESS, if all executions succeeded, or the
+  first observed failure.
+
+
+  @param[in]      This                 The EFI_MM_MP_PROTOCOL instance.
+  @param[in]      Token                This parameter describes the token that was passed into
+                                       DispatchProcedure or BroadcastProcedure.
+
+  @retval EFI_SUCCESS                  Procedure has completed.
+  @retval EFI_INVALID_PARAMETER        Token or Token->Completion is NULL
+  @retval EFI_NOT_FOUND                Token is not currently in use for a non-blocking call
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_WAIT_FOR_PROCEDURE) (
+  IN CONST EFI_MM_MP_PROTOCOL            *This,
+  IN       MM_COMPLETION                 Token
+);
+
+
+
+///
+/// The MM MP protocol provides a set of functions to allow execution of procedures on processors that
+/// have entered MM.
+///
+struct _EFI_MM_MP_PROTOCOL {
+  UINT32                            Revision;
+  UINT32                            Attributes;
+  EFI_MM_GET_NUMBER_OF_PROCESSORS   GetNumberOfProcessors;
+  EFI_MM_DISPATCH_PROCEDURE         DispatchProcedure;
+  EFI_MM_BROADCAST_PROCEDURE        BroadcastProcedure;
+  EFI_MM_SET_STARTUP_PROCEDURE      SetStartupProcedure;
+  EFI_CHECK_FOR_PROCEDURE           CheckForProcedure;
+  EFI_WAIT_FOR_PROCEDURE            WaitForProcedure;
+};
+
+extern EFI_GUID gEfiMmMpProtocolGuid;
+
+#endif
diff --git a/MdePkg/Include/Protocol/MmPciRootBridgeIo.h b/MdePkg/Include/Protocol/MmPciRootBridgeIo.h
new file mode 100644
index 000000000000..cb5f569eec73
--- /dev/null
+++ b/MdePkg/Include/Protocol/MmPciRootBridgeIo.h
@@ -0,0 +1,31 @@
+/** @file
+  MM PCI Root Bridge IO protocol as defined in the PI 1.5 specification.
+
+  This protocol provides PCI I/O and memory access within MM.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _MM_PCI_ROOT_BRIDGE_IO_H_
+#define _MM_PCI_ROOT_BRIDGE_IO_H_
+
+#include <Protocol/PciRootBridgeIo.h>
+
+#define EFI_MM_PCI_ROOT_BRIDGE_IO_PROTOCOL_GUID \
+  { \
+    0x8bc1714d, 0xffcb, 0x41c3, { 0x89, 0xdc, 0x6c, 0x74, 0xd0, 0x6d, 0x98, 0xea } \
+  }
+
+///
+/// This protocol provides the same functionality as the PCI Root Bridge I/O Protocol defined in the
+/// UEFI 2.1 Specifcation, section 13.2, except that the functions for Map() and Unmap() may return
+/// EFI_UNSUPPORTED.
+///
+typedef EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  EFI_MM_PCI_ROOT_BRIDGE_IO_PROTOCOL;
+
+extern EFI_GUID gEfiMmPciRootBridgeIoProtocolGuid;
+
+#endif
+
diff --git a/MdePkg/Include/Protocol/MmPeriodicTimerDispatch.h b/MdePkg/Include/Protocol/MmPeriodicTimerDispatch.h
new file mode 100644
index 000000000000..74b6c0062041
--- /dev/null
+++ b/MdePkg/Include/Protocol/MmPeriodicTimerDispatch.h
@@ -0,0 +1,164 @@
+/** @file
+  MM Periodic Timer Dispatch Protocol as defined in PI 1.5 Specification
+  Volume 4 Management Mode Core Interface.
+
+  This protocol provides the parent dispatch service for the periodical timer MMI source generator.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  This protocol is from PI Version 1.5.
+
+**/
+
+#ifndef _MM_PERIODIC_TIMER_DISPATCH_H_
+#define _MM_PERIODIC_TIMER_DISPATCH_H_
+
+#include <Pi/PiMmCis.h>
+
+#define EFI_MM_PERIODIC_TIMER_DISPATCH_PROTOCOL_GUID \
+  { \
+    0x4cec368e, 0x8e8e, 0x4d71, {0x8b, 0xe1, 0x95, 0x8c, 0x45, 0xfc, 0x8a, 0x53 } \
+  }
+
+///
+/// Example: A chipset supports periodic MMIs on every 64ms or 2 seconds.
+///   A child wishes schedule a period MMI to fire on a period of 3 seconds, there
+///   are several ways to approach the problem:
+///   1. The child may accept a 4 second periodic rate, in which case it registers with
+///        Period = 40000
+///        MmiTickInterval = 20000
+///      The resulting MMI will occur every 2 seconds with the child called back on
+///      every 2nd MMI.
+///      NOTE: the same result would occur if the child set MmiTickInterval = 0.
+///   2. The child may choose the finer granularity MMI (64ms):
+///        Period = 30000
+///        MmiTickInterval = 640
+///      The resulting MMI will occur every 64ms with the child called back on
+///      every 47th MMI.
+///      NOTE: the child driver should be aware that this will result in more
+///        MMIs occuring during system runtime which can negatively impact system
+///        performance.
+///
+typedef struct {
+  ///
+  /// The minimum period of time in 100 nanosecond units that the child gets called. The
+  /// child will be called back after a time greater than the time Period.
+  ///
+  UINT64  Period;
+  ///
+  /// The period of time interval between MMIs. Children of this interface should use this
+  /// field when registering for periodic timer intervals when a finer granularity periodic
+  /// MMI is desired.
+  ///
+  UINT64  MmiTickInterval;
+} EFI_MM_PERIODIC_TIMER_REGISTER_CONTEXT;
+
+///
+/// The DispatchFunction will be called with Context set to the same value as was passed into
+/// Register() in RegisterContext and with CommBuffer pointing to an instance of
+/// EFI_MM_PERIODIC_TIMER_CONTEXT and CommBufferSize pointing to its size.
+///
+typedef struct {
+  ///
+  /// ElapsedTime is the actual time in 100 nanosecond units elapsed since last called, a
+  /// value of 0 indicates an unknown amount of time.
+  ///
+  UINT64  ElapsedTime;
+} EFI_MM_PERIODIC_TIMER_CONTEXT;
+
+typedef struct _EFI_MM_PERIODIC_TIMER_DISPATCH_PROTOCOL  EFI_MM_PERIODIC_TIMER_DISPATCH_PROTOCOL;
+
+/**
+  Register a child MMI source dispatch function for MM periodic timer.
+
+  This service registers a function (DispatchFunction) which will be called when at least the
+  amount of time specified by RegisterContext has elapsed. On return, DispatchHandle
+  contains a unique handle which may be used later to unregister the function using UnRegister().
+  The DispatchFunction will be called with Context set to the same value as was passed into
+  this function in RegisterContext and with CommBuffer pointing to an instance of
+  EFI_MM_PERIODIC_TIMER_CONTEXT and CommBufferSize pointing to its size.
+
+  @param[in]  This               Pointer to the EFI_MM_PERIODIC_TIMER_DISPATCH_PROTOCOL instance.
+  @param[in]  DispatchFunction   Function to register for handler when at least the specified amount
+                                 of time has elapsed.
+  @param[in]  RegisterContext    Pointer to the dispatch function's context.
+                                 The caller fills this context in before calling
+                                 the register function to indicate to the register
+                                 function the period at which the dispatch function
+                                 should be invoked.
+  @param[out] DispatchHandle     Handle generated by the dispatcher to track the function instance.
+
+  @retval EFI_SUCCESS            The dispatch function has been successfully
+                                 registered and the MMI source has been enabled.
+  @retval EFI_DEVICE_ERROR       The driver was unable to enable the MMI source.
+  @retval EFI_INVALID_PARAMETER  RegisterContext is invalid. The period input value
+                                 is not within valid range.
+  @retval EFI_OUT_OF_RESOURCES   There is not enough memory (system or MM) to manage this child.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_PERIODIC_TIMER_REGISTER)(
+  IN CONST EFI_MM_PERIODIC_TIMER_DISPATCH_PROTOCOL    *This,
+  IN       EFI_MM_HANDLER_ENTRY_POINT                 DispatchFunction,
+  IN CONST EFI_MM_PERIODIC_TIMER_REGISTER_CONTEXT     *RegisterContext,
+  OUT      EFI_HANDLE                                 *DispatchHandle
+  );
+
+/**
+  Unregisters a periodic timer service.
+
+  This service removes the handler associated with DispatchHandle so that it will no longer be
+  called when the time has elapsed.
+
+  @param[in] This                Pointer to the EFI_MM_PERIODIC_TIMER_DISPATCH_PROTOCOL instance.
+  @param[in] DispatchHandle      Handle of the service to remove.
+
+  @retval EFI_SUCCESS            The service has been successfully removed.
+  @retval EFI_INVALID_PARAMETER  The DispatchHandle was not valid.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_PERIODIC_TIMER_UNREGISTER)(
+  IN CONST EFI_MM_PERIODIC_TIMER_DISPATCH_PROTOCOL  *This,
+  IN       EFI_HANDLE                               DispatchHandle
+  );
+
+/**
+  Returns the next MMI tick period supported by the chipset.
+
+  The order returned is from longest to shortest interval period.
+
+  @param[in]     This             Pointer to the EFI_MM_PERIODIC_TIMER_DISPATCH_PROTOCOL instance.
+  @param[in,out] MmiTickInterval  Pointer to pointer of next shorter MMI interval
+                                  period supported by the child. This parameter works as a get-first,
+                                  get-next field.The first time this function is called, *MmiTickInterval
+                                  should be set to NULL to get the longest MMI interval.The returned
+                                  *MmiTickInterval should be passed in on subsequent calls to get the
+                                  next shorter interval period until *MmiTickInterval = NULL.
+
+  @retval EFI_SUCCESS             The service returned successfully.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_PERIODIC_TIMER_INTERVAL)(
+  IN CONST EFI_MM_PERIODIC_TIMER_DISPATCH_PROTOCOL  *This,
+  IN OUT UINT64                                     **MmiTickInterval
+  );
+
+///
+/// Interface structure for the MM Periodic Timer Dispatch Protocol
+///
+/// This protocol provides the parent dispatch service for the periodical timer MMI source generator.
+///
+struct _EFI_MM_PERIODIC_TIMER_DISPATCH_PROTOCOL {
+  EFI_MM_PERIODIC_TIMER_REGISTER    Register;
+  EFI_MM_PERIODIC_TIMER_UNREGISTER  UnRegister;
+  EFI_MM_PERIODIC_TIMER_INTERVAL    GetNextShorterInterval;
+};
+
+extern EFI_GUID gEfiMmPeriodicTimerDispatchProtocolGuid;
+
+#endif
+
diff --git a/MdePkg/Include/Protocol/MmPowerButtonDispatch.h b/MdePkg/Include/Protocol/MmPowerButtonDispatch.h
new file mode 100644
index 000000000000..f46501dc1c1e
--- /dev/null
+++ b/MdePkg/Include/Protocol/MmPowerButtonDispatch.h
@@ -0,0 +1,111 @@
+/** @file
+  MM Power Button Dispatch Protocol as defined in PI 1.5 Specification
+  Volume 4 Management Mode Core Interface.
+
+  This protocol provides the parent dispatch service for the power button MMI source generator.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  This protocol is from PI Version 1.5.
+
+**/
+
+#ifndef _MM_POWER_BUTTON_DISPATCH_H_
+#define _MM_POWER_BUTTON_DISPATCH_H_
+
+#include <Pi/PiMmCis.h>
+
+#define EFI_MM_POWER_BUTTON_DISPATCH_PROTOCOL_GUID \
+  { \
+    0x1b1183fa, 0x1823, 0x46a7, {0x88, 0x72, 0x9c, 0x57, 0x87, 0x55, 0x40, 0x9d } \
+  }
+
+///
+/// Power Button phases.
+///
+typedef enum {
+  EfiPowerButtonEntry,
+  EfiPowerButtonExit,
+  EfiPowerButtonMax
+} EFI_POWER_BUTTON_PHASE;
+
+///
+/// The dispatch function's context.
+///
+typedef struct {
+  ///
+  /// Designates whether this handler should be invoked upon entry or exit.
+  ///
+  EFI_POWER_BUTTON_PHASE  Phase;
+} EFI_MM_POWER_BUTTON_REGISTER_CONTEXT;
+
+typedef struct _EFI_MM_POWER_BUTTON_DISPATCH_PROTOCOL EFI_MM_POWER_BUTTON_DISPATCH_PROTOCOL;
+
+/**
+  Provides the parent dispatch service for a power button event.
+
+  This service registers a function (DispatchFunction) which will be called when an MMI is
+  generated because the power button was pressed or released, as specified by RegisterContext.
+  On return, DispatchHandle contains a unique handle which may be used later to unregister the
+  function using UnRegister().
+  The DispatchFunction will be called with Context set to the same value as was passed into
+  this function in RegisterContext and with CommBuffer and CommBufferSize set to NULL.
+
+  @param[in]  This               Pointer to the EFI_MM_POWER_BUTTON_DISPATCH_PROTOCOL instance.
+  @param[in]  DispatchFunction   Function to register for handler when power button is pressed or released.
+  @param[in]  RegisterContext    Pointer to the dispatch function's context. The caller fills in this context
+                                 before calling the Register() function to indicate to the Register() function
+                                 the power button MMI phase for which the dispatch function should be invoked.
+  @param[out] DispatchHandle     Handle generated by the dispatcher to track the function instance.
+
+  @retval EFI_SUCCESS            The dispatch function has been successfully
+                                 registered and the MMI source has been enabled.
+  @retval EFI_DEVICE_ERROR       The driver was unable to enable the MMI source.
+  @retval EFI_INVALID_PARAMETER  RegisterContext is invalid. The power button input value
+                                 is not within valid range.
+  @retval EFI_OUT_OF_RESOURCES   There is not enough memory (system or MM) to manage this child.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_POWER_BUTTON_REGISTER)(
+  IN CONST EFI_MM_POWER_BUTTON_DISPATCH_PROTOCOL  *This,
+  IN       EFI_MM_HANDLER_ENTRY_POINT             DispatchFunction,
+  IN       EFI_MM_POWER_BUTTON_REGISTER_CONTEXT   *RegisterContext,
+  OUT      EFI_HANDLE                             *DispatchHandle
+  );
+
+/**
+  Unregisters a power-button service.
+
+  This service removes the handler associated with DispatchHandle so that it will no longer be
+  called when the standby button is pressed or released.
+
+  @param[in] This                Pointer to the EFI_MM_POWER_BUTTON_DISPATCH_PROTOCOL instance.
+  @param[in] DispatchHandle      Handle of the service to remove.
+
+  @retval EFI_SUCCESS            The service has been successfully removed.
+  @retval EFI_INVALID_PARAMETER  The DispatchHandle was not valid.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_POWER_BUTTON_UNREGISTER)(
+  IN CONST EFI_MM_POWER_BUTTON_DISPATCH_PROTOCOL  *This,
+  IN       EFI_HANDLE                             DispatchHandle
+  );
+
+///
+/// Interface structure for the MM Power Button Dispatch Protocol.
+///
+/// This protocol provides the parent dispatch service for the power button MMI source generator.
+///
+struct _EFI_MM_POWER_BUTTON_DISPATCH_PROTOCOL {
+  EFI_MM_POWER_BUTTON_REGISTER    Register;
+  EFI_MM_POWER_BUTTON_UNREGISTER  UnRegister;
+};
+
+extern EFI_GUID gEfiMmPowerButtonDispatchProtocolGuid;
+
+#endif
+
diff --git a/MdePkg/Include/Protocol/MmReadyToLock.h b/MdePkg/Include/Protocol/MmReadyToLock.h
new file mode 100644
index 000000000000..092fcfdcc0c1
--- /dev/null
+++ b/MdePkg/Include/Protocol/MmReadyToLock.h
@@ -0,0 +1,26 @@
+/** @file
+  MM Ready To Lock protocol introduced in the PI 1.5 specification.
+
+  This protocol is a mandatory protocol published by the MM Foundation
+  code when the system is preparing to lock certain resources and interfaces
+  in anticipation of the invocation of 3rd party extensible modules.
+  This protocol is an MM counterpart of the DXE MM Ready to Lock Protocol.
+  This protocol prorogates resource locking notification into MM environment.
+  This protocol is installed after installation of the MM End of DXE Protocol.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _MM_READY_TO_LOCK_H_
+#define _MM_READY_TO_LOCK_H_
+
+#define EFI_MM_READY_TO_LOCK_PROTOCOL_GUID \
+  { \
+    0x47b7fa8c, 0xf4bd, 0x4af6, { 0x82, 0x00, 0x33, 0x30, 0x86, 0xf0, 0xd2, 0xc8 } \
+  }
+
+extern EFI_GUID gEfiMmReadyToLockProtocolGuid;
+
+#endif
diff --git a/MdePkg/Include/Protocol/MmReportStatusCodeHandler.h b/MdePkg/Include/Protocol/MmReportStatusCodeHandler.h
new file mode 100644
index 000000000000..f8e67ac4e310
--- /dev/null
+++ b/MdePkg/Include/Protocol/MmReportStatusCodeHandler.h
@@ -0,0 +1,78 @@
+/** @file
+  This protocol provides registering and unregistering services to status code consumers while in DXE MM.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  This Protocol was introduced in PI Specification 1.1.
+
+**/
+
+#ifndef __MM_REPORT_STATUS_CODE_HANDLER_PROTOCOL_H__
+#define __MM_REPORT_STATUS_CODE_HANDLER_PROTOCOL_H__
+
+#define EFI_MM_RSC_HANDLER_PROTOCOL_GUID \
+  { \
+    0x2ff29fa7, 0x5e80, 0x4ed9, {0xb3, 0x80, 0x1, 0x7d, 0x3c, 0x55, 0x4f, 0xf4} \
+  }
+
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_RSC_HANDLER_CALLBACK)(
+  IN EFI_STATUS_CODE_TYPE   CodeType,
+  IN EFI_STATUS_CODE_VALUE  Value,
+  IN UINT32                 Instance,
+  IN EFI_GUID               *CallerId,
+  IN EFI_STATUS_CODE_DATA   *Data
+);
+
+/**
+  Register the callback function for ReportStatusCode() notification.
+
+  When this function is called the function pointer is added to an internal list and any future calls to
+  ReportStatusCode() will be forwarded to the Callback function.
+
+  @param[in] Callback               A pointer to a function of type EFI_MM_RSC_HANDLER_CALLBACK that is
+                                    called when a call to ReportStatusCode() occurs.
+
+  @retval EFI_SUCCESS               Function was successfully registered.
+  @retval EFI_INVALID_PARAMETER     The callback function was NULL.
+  @retval EFI_OUT_OF_RESOURCES      The internal buffer ran out of space. No more functions can be
+                                    registered.
+  @retval EFI_ALREADY_STARTED       The function was already registered. It can't be registered again.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_RSC_HANDLER_REGISTER)(
+  IN EFI_MM_RSC_HANDLER_CALLBACK Callback
+);
+
+/**
+  Remove a previously registered callback function from the notification list.
+
+  A callback function must be unregistered before it is deallocated. It is important that any registered
+  callbacks that are not runtime complaint be unregistered when ExitBootServices() is called.
+
+  @param[in] Callback           A pointer to a function of type EFI_MM_RSC_HANDLER_CALLBACK that is to be
+                                unregistered.
+
+  @retval EFI_SUCCESS           The function was successfully unregistered.
+  @retval EFI_INVALID_PARAMETER The callback function was NULL.
+  @retval EFI_NOT_FOUND         The callback function was not found to be unregistered.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_RSC_HANDLER_UNREGISTER)(
+  IN EFI_MM_RSC_HANDLER_CALLBACK Callback
+);
+
+typedef struct _EFI_MM_RSC_HANDLER_PROTOCOL {
+  EFI_MM_RSC_HANDLER_REGISTER      Register;
+  EFI_MM_RSC_HANDLER_UNREGISTER    Unregister;
+} EFI_MM_RSC_HANDLER_PROTOCOL;
+
+extern EFI_GUID gEfiMmRscHandlerProtocolGuid;
+
+#endif
diff --git a/MdePkg/Include/Protocol/MmStandbyButtonDispatch.h b/MdePkg/Include/Protocol/MmStandbyButtonDispatch.h
new file mode 100644
index 000000000000..430237862a7e
--- /dev/null
+++ b/MdePkg/Include/Protocol/MmStandbyButtonDispatch.h
@@ -0,0 +1,113 @@
+/** @file
+  MM Standby Button Dispatch Protocol as defined in PI 1.5 Specification
+  Volume 4 Management Mode Core Interface.
+
+  This protocol provides the parent dispatch service for the standby button MMI source generator.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  This protocol is from PI Version 1.5.
+
+**/
+
+#ifndef _MM_STANDBY_BUTTON_DISPATCH_H_
+#define _MM_STANDBY_BUTTON_DISPATCH_H_
+
+#include <Pi/PiMmCis.h>
+
+#define EFI_MM_STANDBY_BUTTON_DISPATCH_PROTOCOL_GUID \
+  { \
+    0x7300c4a1, 0x43f2, 0x4017, {0xa5, 0x1b, 0xc8, 0x1a, 0x7f, 0x40, 0x58, 0x5b } \
+  }
+
+///
+/// Standby Button phases
+///
+typedef enum {
+  EfiStandbyButtonEntry,
+  EfiStandbyButtonExit,
+  EfiStandbyButtonMax
+} EFI_STANDBY_BUTTON_PHASE;
+
+///
+/// The dispatch function's context.
+///
+typedef struct {
+  ///
+  /// Describes whether the child handler should be invoked upon the entry to the button
+  /// activation or upon exit.
+  ///
+  EFI_STANDBY_BUTTON_PHASE  Phase;
+} EFI_MM_STANDBY_BUTTON_REGISTER_CONTEXT;
+
+typedef struct _EFI_MM_STANDBY_BUTTON_DISPATCH_PROTOCOL EFI_MM_STANDBY_BUTTON_DISPATCH_PROTOCOL;
+
+/**
+  Provides the parent dispatch service for a standby button event.
+
+  This service registers a function (DispatchFunction) which will be called when an MMI is
+  generated because the standby button was pressed or released, as specified by
+  RegisterContext. On return, DispatchHandle contains a unique handle which may be used
+  later to unregister the function using UnRegister().
+  The DispatchFunction will be called with Context set to the same value as was passed into
+  this function in RegisterContext and with CommBuffer and CommBufferSize set to NULL.
+
+  @param[in]  This               Pointer to the EFI_MM_STANDBY_BUTTON_DISPATCH_PROTOCOL instance.
+  @param[in]  DispatchFunction   Function to register for handler when the standby button is pressed or released.
+  @param[in]  RegisterContext    Pointer to the dispatch function's context. The caller fills in this context
+                                 before calling the register function to indicate to the register function the
+                                 standby button MMI source for which the dispatch function should be invoked.
+  @param[out] DispatchHandle     Handle generated by the dispatcher to track the function instance.
+
+  @retval EFI_SUCCESS            The dispatch function has been successfully
+                                 registered and the MMI source has been enabled.
+  @retval EFI_DEVICE_ERROR       The driver was unable to enable the MMI source.
+  @retval EFI_INVALID_PARAMETER  RegisterContext is invalid. The standby button input value
+                                 is not within valid range.
+  @retval EFI_OUT_OF_RESOURCES   There is not enough memory (system or MM) to manage this child.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_STANDBY_BUTTON_REGISTER)(
+  IN CONST EFI_MM_STANDBY_BUTTON_DISPATCH_PROTOCOL  *This,
+  IN       EFI_MM_HANDLER_ENTRY_POINT               DispatchFunction,
+  IN       EFI_MM_STANDBY_BUTTON_REGISTER_CONTEXT   *RegisterContext,
+  OUT      EFI_HANDLE                               *DispatchHandle
+  );
+
+/**
+  Unregisters a child MMI source dispatch function with a parent MM driver.
+
+  This service removes the handler associated with DispatchHandle so that it will no longer be
+  called when the standby button is pressed or released.
+
+  @param[in] This                Pointer to the EFI_MM_STANDBY_BUTTON_DISPATCH_PROTOCOL instance.
+  @param[in] DispatchHandle      Handle of the service to remove.
+
+  @retval EFI_SUCCESS            The service has been successfully removed.
+  @retval EFI_INVALID_PARAMETER  The DispatchHandle was not valid.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_STANDBY_BUTTON_UNREGISTER)(
+  IN CONST EFI_MM_STANDBY_BUTTON_DISPATCH_PROTOCOL  *This,
+  IN       EFI_HANDLE                               DispatchHandle
+  );
+
+///
+/// Interface structure for the MM Standby Button Dispatch Protocol.
+///
+/// This protocol provides the parent dispatch service for the standby
+/// button MMI source generator.
+///
+struct _EFI_MM_STANDBY_BUTTON_DISPATCH_PROTOCOL {
+  EFI_MM_STANDBY_BUTTON_REGISTER    Register;
+  EFI_MM_STANDBY_BUTTON_UNREGISTER  UnRegister;
+};
+
+extern EFI_GUID gEfiMmStandbyButtonDispatchProtocolGuid;
+
+#endif
+
diff --git a/MdePkg/Include/Protocol/MmStatusCode.h b/MdePkg/Include/Protocol/MmStatusCode.h
new file mode 100644
index 000000000000..3ff1a31aa4ee
--- /dev/null
+++ b/MdePkg/Include/Protocol/MmStatusCode.h
@@ -0,0 +1,59 @@
+/** @file
+  EFI MM Status Code Protocol as defined in the PI 1.5 specification.
+
+  This protocol provides the basic status code services while in MM.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _MM_STATUS_CODE_H__
+#define _MM_STATUS_CODE_H__
+
+
+#define EFI_MM_STATUS_CODE_PROTOCOL_GUID \
+  { \
+    0x6afd2b77, 0x98c1, 0x4acd, {0xa6, 0xf9, 0x8a, 0x94, 0x39, 0xde, 0xf, 0xb1} \
+  }
+
+typedef struct _EFI_MM_STATUS_CODE_PROTOCOL  EFI_MM_STATUS_CODE_PROTOCOL;
+
+/**
+  Service to emit the status code in MM.
+
+  The EFI_MM_STATUS_CODE_PROTOCOL.ReportStatusCode() function enables a driver
+  to emit a status code while in MM.  The reason that there is a separate protocol definition from the
+  DXE variant of this service is that the publisher of this protocol will provide a service that is
+  capability of coexisting with a foreground operational environment, such as an operating system
+  after the termination of boot services.
+
+  @param[in] This                Points to this instance of the EFI_MM_STATUS_CODE_PROTOCOL.
+  @param[in] CodeType            DIndicates the type of status code being reported.
+  @param[in] Value               Describes the current status of a hardware or software entity.
+  @param[in] Instance            The enumeration of a hardware or software entity within the system.
+  @param[in] CallerId            This optional parameter may be used to identify the caller.
+  @param[in] Data                This optional parameter may be used to pass additional data.
+
+  @retval EFI_SUCCESS            The function completed successfully.
+  @retval EFI_INVALID_PARAMETER  The function should not be completed due to a device error.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_REPORT_STATUS_CODE)(
+  IN CONST EFI_MM_STATUS_CODE_PROTOCOL   *This,
+  IN EFI_STATUS_CODE_TYPE                CodeType,
+  IN EFI_STATUS_CODE_VALUE               Value,
+  IN UINT32                              Instance,
+  IN CONST EFI_GUID                      *CallerId,
+  IN EFI_STATUS_CODE_DATA                *Data OPTIONAL
+  );
+
+struct _EFI_MM_STATUS_CODE_PROTOCOL {
+  EFI_MM_REPORT_STATUS_CODE  ReportStatusCode;
+};
+
+extern EFI_GUID gEfiMmStatusCodeProtocolGuid;
+
+#endif
+
diff --git a/MdePkg/Include/Protocol/MmSwDispatch.h b/MdePkg/Include/Protocol/MmSwDispatch.h
new file mode 100644
index 000000000000..49957de65622
--- /dev/null
+++ b/MdePkg/Include/Protocol/MmSwDispatch.h
@@ -0,0 +1,130 @@
+/** @file
+  MM Software Dispatch Protocol introduced from PI 1.5 Specification
+  Volume 4 Management Mode Core Interface.
+
+  This protocol provides the parent dispatch service for a given MMI source generator.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _MM_SW_DISPATCH_H_
+#define _MM_SW_DISPATCH_H_
+
+#include <Pi/PiMmCis.h>
+
+#define EFI_MM_SW_DISPATCH_PROTOCOL_GUID \
+  { \
+    0x18a3c6dc, 0x5eea, 0x48c8, {0xa1, 0xc1, 0xb5, 0x33, 0x89, 0xf9, 0x89, 0x99 } \
+  }
+
+///
+/// A particular chipset may not support all possible software MMI input values.
+/// For example, the ICH supports only values 00h to 0FFh.  The parent only allows a single
+/// child registration for each SwMmiInputValue.
+///
+typedef struct {
+  UINTN SwMmiInputValue;
+} EFI_MM_SW_REGISTER_CONTEXT;
+
+///
+/// The DispatchFunction will be called with Context set to the same value as was passed into
+/// this function in RegisterContext and with CommBuffer (and CommBufferSize) pointing
+/// to an instance of EFI_MM_SW_CONTEXT indicating the index of the CPU which generated the
+/// software MMI.
+///
+typedef struct {
+  ///
+  /// The 0-based index of the CPU which generated the software MMI.
+  ///
+  UINTN SwMmiCpuIndex;
+  ///
+  /// This value corresponds directly to the CommandPort parameter used in the call to Trigger().
+  ///
+  UINT8 CommandPort;
+  ///
+  /// This value corresponds directly to the DataPort parameter used in the call to Trigger().
+  ///
+  UINT8 DataPort;
+} EFI_MM_SW_CONTEXT;
+
+typedef struct _EFI_MM_SW_DISPATCH_PROTOCOL  EFI_MM_SW_DISPATCH_PROTOCOL;
+
+/**
+  Register a child MMI source dispatch function for the specified software MMI.
+
+  This service registers a function (DispatchFunction) which will be called when the software
+  MMI source specified by RegisterContext->SwMmiCpuIndex is detected. On return,
+  DispatchHandle contains a unique handle which may be used later to unregister the function
+  using UnRegister().
+
+  @param[in]  This                 Pointer to the EFI_MM_SW_DISPATCH_PROTOCOL instance.
+  @param[in]  DispatchFunction     Function to register for handler when the specified software
+                                   MMI is generated.
+  @param[in, out] RegisterContext  Pointer to the dispatch function's context.
+                                   The caller fills this context in before calling
+                                   the register function to indicate to the register
+                                   function which Software MMI input value the
+                                   dispatch function should be invoked for.
+  @param[out] DispatchHandle       Handle generated by the dispatcher to track the
+                                   function instance.
+
+  @retval EFI_SUCCESS            The dispatch function has been successfully
+                                 registered and the MMI source has been enabled.
+  @retval EFI_DEVICE_ERROR       The SW driver was unable to enable the MMI source.
+  @retval EFI_INVALID_PARAMETER  RegisterContext is invalid. The SW MMI input value
+                                 is not within a valid range or is already in use.
+  @retval EFI_OUT_OF_RESOURCES   There is not enough memory (system or MM) to manage this
+                                 child.
+  @retval EFI_OUT_OF_RESOURCES   A unique software MMI value could not be assigned
+                                 for this dispatch.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_SW_REGISTER)(
+  IN  CONST EFI_MM_SW_DISPATCH_PROTOCOL  *This,
+  IN        EFI_MM_HANDLER_ENTRY_POINT   DispatchFunction,
+  IN  OUT   EFI_MM_SW_REGISTER_CONTEXT   *RegisterContext,
+  OUT       EFI_HANDLE                   *DispatchHandle
+  );
+
+/**
+  Unregister a child MMI source dispatch function for the specified software MMI.
+
+  This service removes the handler associated with DispatchHandle so that it will no longer be
+  called in response to a software MMI.
+
+  @param[in] This                Pointer to the EFI_MM_SW_DISPATCH_PROTOCOL instance.
+  @param[in] DispatchHandle      Handle of dispatch function to deregister.
+
+  @retval EFI_SUCCESS            The dispatch function has been successfully unregistered.
+  @retval EFI_INVALID_PARAMETER  The DispatchHandle was not valid.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_SW_UNREGISTER)(
+  IN CONST EFI_MM_SW_DISPATCH_PROTOCOL  *This,
+  IN       EFI_HANDLE                   DispatchHandle
+);
+
+///
+/// Interface structure for the MM Software MMI Dispatch Protocol.
+///
+/// The EFI_MM_SW_DISPATCH_PROTOCOL provides the ability to install child handlers for the
+/// given software.  These handlers will respond to software interrupts, and the maximum software
+/// interrupt in the EFI_MM_SW_REGISTER_CONTEXT is denoted by MaximumSwiValue.
+///
+struct _EFI_MM_SW_DISPATCH_PROTOCOL {
+  EFI_MM_SW_REGISTER    Register;
+  EFI_MM_SW_UNREGISTER  UnRegister;
+  ///
+  /// A read-only field that describes the maximum value that can be used in the
+  /// EFI_MM_SW_DISPATCH_PROTOCOL.Register() service.
+  ///
+  UINTN                 MaximumSwiValue;
+};
+
+extern EFI_GUID gEfiMmSwDispatchProtocolGuid;
+
+#endif
diff --git a/MdePkg/Include/Protocol/MmSxDispatch.h b/MdePkg/Include/Protocol/MmSxDispatch.h
new file mode 100644
index 000000000000..db008e96fa28
--- /dev/null
+++ b/MdePkg/Include/Protocol/MmSxDispatch.h
@@ -0,0 +1,129 @@
+/** @file
+  MM Sx Dispatch Protocol as defined in PI 1.5 Specification
+  Volume 4 Management Mode Core Interface.
+
+  Provides the parent dispatch service for a given Sx-state source generator.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _MM_SX_DISPATCH_H_
+#define _MM_SX_DISPATCH_H_
+
+#include <Pi/PiMmCis.h>
+
+#define EFI_MM_SX_DISPATCH_PROTOCOL_GUID \
+  { \
+    0x456d2859, 0xa84b, 0x4e47, {0xa2, 0xee, 0x32, 0x76, 0xd8, 0x86, 0x99, 0x7d } \
+  }
+
+///
+/// Sleep states S0-S5
+///
+typedef enum {
+  SxS0,
+  SxS1,
+  SxS2,
+  SxS3,
+  SxS4,
+  SxS5,
+  EfiMaximumSleepType
+} EFI_SLEEP_TYPE;
+
+///
+/// Sleep state phase: entry or exit
+///
+typedef enum {
+  SxEntry,
+  SxExit,
+  EfiMaximumPhase
+} EFI_SLEEP_PHASE;
+
+///
+/// The dispatch function's context
+///
+typedef struct {
+  EFI_SLEEP_TYPE  Type;
+  EFI_SLEEP_PHASE Phase;
+} EFI_MM_SX_REGISTER_CONTEXT;
+
+typedef struct _EFI_MM_SX_DISPATCH_PROTOCOL  EFI_MM_SX_DISPATCH_PROTOCOL;
+
+/**
+  Provides the parent dispatch service for a given Sx source generator.
+
+  This service registers a function (DispatchFunction) which will be called when the sleep state
+  event specified by RegisterContext is detected. On return, DispatchHandle contains a
+  unique handle which may be used later to unregister the function using UnRegister().
+  The DispatchFunction will be called with Context set to the same value as was passed into
+  this function in RegisterContext and with CommBuffer and CommBufferSize set to
+  NULL and 0 respectively.
+
+  @param[in] This                Pointer to the EFI_MM_SX_DISPATCH_PROTOCOL instance.
+  @param[in] DispatchFunction    Function to register for handler when the specified sleep state event occurs.
+  @param[in] RegisterContext     Pointer to the dispatch function's context.
+                                 The caller fills this context in before calling
+                                 the register function to indicate to the register
+                                 function which Sx state type and phase the caller
+                                 wishes to be called back on. For this intertace,
+                                 the Sx driver will call the registered handlers for
+                                 all Sx type and phases, so the Sx state handler(s)
+                                 must check the Type and Phase field of the Dispatch
+                                 context and act accordingly.
+  @param[out]  DispatchHandle    Handle of dispatch function, for when interfacing
+                                 with the parent Sx state MM driver.
+
+  @retval EFI_SUCCESS            The dispatch function has been successfully
+                                 registered and the MMI source has been enabled.
+  @retval EFI_UNSUPPORTED        The Sx driver or hardware does not support that
+                                 Sx Type/Phase.
+  @retval EFI_DEVICE_ERROR       The Sx driver was unable to enable the MMI source.
+  @retval EFI_INVALID_PARAMETER  RegisterContext is invalid. Type & Phase are not
+                                 within valid range.
+  @retval EFI_OUT_OF_RESOURCES   There is not enough memory (system or MM) to manage this
+                                 child.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_SX_REGISTER)(
+  IN  CONST EFI_MM_SX_DISPATCH_PROTOCOL  *This,
+  IN        EFI_MM_HANDLER_ENTRY_POINT   DispatchFunction,
+  IN  CONST EFI_MM_SX_REGISTER_CONTEXT   *RegisterContext,
+  OUT       EFI_HANDLE                   *DispatchHandle
+  );
+
+/**
+  Unregisters an Sx-state service.
+
+  This service removes the handler associated with DispatchHandle so that it will no longer be
+  called in response to sleep event.
+
+  @param[in] This                Pointer to the EFI_MM_SX_DISPATCH_PROTOCOL instance.
+  @param[in] DispatchHandle      Handle of the service to remove.
+
+  @retval EFI_SUCCESS            The service has been successfully removed.
+  @retval EFI_INVALID_PARAMETER  The DispatchHandle was not valid.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_SX_UNREGISTER)(
+  IN CONST EFI_MM_SX_DISPATCH_PROTOCOL  *This,
+  IN       EFI_HANDLE                   DispatchHandle
+  );
+
+///
+/// Interface structure for the MM Sx Dispatch Protocol
+///
+/// The EFI_MM_SX_DISPATCH_PROTOCOL provides the ability to install child handlers to
+/// respond to sleep state related events.
+///
+struct _EFI_MM_SX_DISPATCH_PROTOCOL {
+  EFI_MM_SX_REGISTER    Register;
+  EFI_MM_SX_UNREGISTER  UnRegister;
+};
+
+extern EFI_GUID gEfiMmSxDispatchProtocolGuid;
+
+#endif
diff --git a/MdePkg/Include/Protocol/MmUsbDispatch.h b/MdePkg/Include/Protocol/MmUsbDispatch.h
new file mode 100644
index 000000000000..75abb270b1a5
--- /dev/null
+++ b/MdePkg/Include/Protocol/MmUsbDispatch.h
@@ -0,0 +1,124 @@
+/** @file
+  MM USB Dispatch Protocol as defined in PI 1.5 Specification
+  Volume 4 Management Mode Core Interface.
+
+  Provides the parent dispatch service for the USB MMI source generator.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  This protocol is from PI Version 1.5.
+
+**/
+
+#ifndef _MM_USB_DISPATCH_H_
+#define _MM_USB_DISPATCH_H_
+
+#include <Pi/PiMmCis.h>
+
+#define EFI_MM_USB_DISPATCH_PROTOCOL_GUID \
+  { \
+    0xee9b8d90, 0xc5a6, 0x40a2, {0xbd, 0xe2, 0x52, 0x55, 0x8d, 0x33, 0xcc, 0xa1 } \
+  }
+
+///
+/// USB MMI event types
+///
+typedef enum {
+  UsbLegacy,
+  UsbWake
+} EFI_USB_MMI_TYPE;
+
+///
+/// The dispatch function's context.
+///
+typedef struct {
+  ///
+  /// Describes whether this child handler will be invoked in response to a USB legacy
+  /// emulation event, such as port-trap on the PS/2* keyboard control registers, or to a
+  /// USB wake event, such as resumption from a sleep state.
+  ///
+  EFI_USB_MMI_TYPE          Type;
+  ///
+  /// The device path is part of the context structure and describes the location of the
+  /// particular USB host controller in the system for which this register event will occur.
+  /// This location is important because of the possible integration of several USB host
+  /// controllers in a system.
+  ///
+  EFI_DEVICE_PATH_PROTOCOL  *Device;
+} EFI_MM_USB_REGISTER_CONTEXT;
+
+typedef struct _EFI_MM_USB_DISPATCH_PROTOCOL EFI_MM_USB_DISPATCH_PROTOCOL;
+
+/**
+  Provides the parent dispatch service for the USB MMI source generator.
+
+  This service registers a function (DispatchFunction) which will be called when the USB-
+  related MMI specified by RegisterContext has occurred. On return, DispatchHandle
+  contains a unique handle which may be used later to unregister the function using UnRegister().
+  The DispatchFunction will be called with Context set to the same value as was passed into
+  this function in RegisterContext and with CommBuffer containing NULL and
+  CommBufferSize containing zero.
+
+  @param[in]  This               Pointer to the EFI_MM_USB_DISPATCH_PROTOCOL instance.
+  @param[in]  DispatchFunction   Function to register for handler when a USB-related MMI occurs.
+  @param[in]  RegisterContext    Pointer to the dispatch function's context.
+                                 The caller fills this context in before calling
+                                 the register function to indicate to the register
+                                 function the USB MMI types for which the dispatch
+                                 function should be invoked.
+  @param[out] DispatchHandle     Handle generated by the dispatcher to track the function instance.
+
+  @retval EFI_SUCCESS            The dispatch function has been successfully
+                                 registered and the MMI source has been enabled.
+  @retval EFI_DEVICE_ERROR       The driver was unable to enable the MMI source.
+  @retval EFI_INVALID_PARAMETER  RegisterContext is invalid. The USB MMI type
+                                 is not within valid range.
+  @retval EFI_OUT_OF_RESOURCES   There is not enough memory (system or MM) to manage this child.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_USB_REGISTER)(
+  IN  CONST EFI_MM_USB_DISPATCH_PROTOCOL  *This,
+  IN        EFI_MM_HANDLER_ENTRY_POINT    DispatchFunction,
+  IN  CONST EFI_MM_USB_REGISTER_CONTEXT   *RegisterContext,
+  OUT       EFI_HANDLE                    *DispatchHandle
+  );
+
+/**
+  Unregisters a USB service.
+
+  This service removes the handler associated with DispatchHandle so that it will no longer be
+  called when the USB event occurs.
+
+  @param[in]  This               Pointer to the EFI_MM_USB_DISPATCH_PROTOCOL instance.
+  @param[in]  DispatchHandle     Handle of the service to remove.
+
+  @retval EFI_SUCCESS            The dispatch function has been successfully
+                                 unregistered and the MMI source has been disabled
+                                 if there are no other registered child dispatch
+                                 functions for this MMI source.
+  @retval EFI_INVALID_PARAMETER  The DispatchHandle was not valid.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_MM_USB_UNREGISTER)(
+  IN CONST EFI_MM_USB_DISPATCH_PROTOCOL  *This,
+  IN       EFI_HANDLE                    DispatchHandle
+  );
+
+///
+/// Interface structure for the MM USB MMI Dispatch Protocol
+///
+/// This protocol provides the parent dispatch service for the USB MMI source generator.
+///
+struct _EFI_MM_USB_DISPATCH_PROTOCOL {
+  EFI_MM_USB_REGISTER    Register;
+  EFI_MM_USB_UNREGISTER  UnRegister;
+};
+
+extern EFI_GUID gEfiMmUsbDispatchProtocolGuid;
+
+#endif
+
diff --git a/MdePkg/Include/Protocol/MonotonicCounter.h b/MdePkg/Include/Protocol/MonotonicCounter.h
index 1409be2e5f3d..5d56ca788fea 100644
--- a/MdePkg/Include/Protocol/MonotonicCounter.h
+++ b/MdePkg/Include/Protocol/MonotonicCounter.h
@@ -3,14 +3,8 @@
 
   This code provides the services required to access the system's monotonic counter
 
-Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -22,7 +16,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 ///
 #define EFI_MONOTONIC_COUNTER_ARCH_PROTOCOL_GUID \
   {0x1da97072, 0xbddc, 0x4b30, {0x99, 0xf1, 0x72, 0xa0, 0xb5, 0x6f, 0xff, 0x2a} }
-  
+
 extern EFI_GUID gEfiMonotonicCounterArchProtocolGuid;
 
 #endif
diff --git a/MdePkg/Include/Protocol/MpService.h b/MdePkg/Include/Protocol/MpService.h
index e61caebc5816..697d99ebe531 100644
--- a/MdePkg/Include/Protocol/MpService.h
+++ b/MdePkg/Include/Protocol/MpService.h
@@ -27,14 +27,8 @@
   APs to help test system memory in parallel with other device initialization.
   Diagnostics applications may also use this protocol for multi-processor.
 
-Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under
-the terms and conditions of the BSD License that accompanies this distribution.
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This Protocol is defined in the UEFI Platform Initialization Specification 1.2,
@@ -54,6 +48,11 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   }
 
 ///
+/// Value used in the NumberProcessors parameter of the GetProcessorInfo function
+///
+#define CPU_V2_EXTENDED_TOPOLOGY BIT24
+
+///
 /// Forward declaration for the EFI_MP_SERVICES_PROTOCOL.
 ///
 typedef struct _EFI_MP_SERVICES_PROTOCOL EFI_MP_SERVICES_PROTOCOL;
@@ -103,6 +102,47 @@ typedef struct {
 } EFI_CPU_PHYSICAL_LOCATION;
 
 ///
+///  Structure that defines the 6-level physical location of the processor
+///
+typedef struct {
+///
+///    Package     Zero-based physical package number that identifies the cartridge of the processor.
+///
+UINT32  Package;
+///
+///    Module      Zero-based physical module number within package of the processor.
+///
+UINT32  Module;
+///
+///    Tile        Zero-based physical tile number within module of the processor.
+///
+UINT32  Tile;
+///
+///    Die         Zero-based physical die number within tile of the processor.
+///
+UINT32  Die;
+///
+///     Core        Zero-based physical core number within die of the processor.
+///
+UINT32  Core;
+///
+///     Thread      Zero-based logical thread number within core of the processor.
+///
+UINT32  Thread;
+} EFI_CPU_PHYSICAL_LOCATION2;
+
+
+typedef union {
+  /// The 6-level physical location of the processor, including the
+  /// physical package number that identifies the cartridge, the physical
+  /// module number within package, the physical tile number within the module,
+  /// the physical die number within the tile, the physical core number within
+  /// package, and logical thread number within core.
+  EFI_CPU_PHYSICAL_LOCATION2  Location2;
+} EXTENDED_PROCESSOR_INFORMATION;
+
+
+///
 /// Structure that describes information about a logical CPU.
 ///
 typedef struct {
@@ -138,6 +178,10 @@ typedef struct {
   /// logical thread number within core.
   ///
   EFI_CPU_PHYSICAL_LOCATION  Location;
+  ///
+  /// The extended information of the processor. This field is filled only when
+  /// CPU_V2_EXTENDED_TOPOLOGY is set in parameter ProcessorNumber.
+  EXTENDED_PROCESSOR_INFORMATION ExtendedInformation;
 } EFI_PROCESSOR_INFORMATION;
 
 /**
@@ -491,7 +535,7 @@ EFI_STATUS
   @retval EFI_UNSUPPORTED         Switching the BSP cannot be completed prior to
                                   this service returning.
   @retval EFI_UNSUPPORTED         Switching the BSP is not supported.
-  @retval EFI_SUCCESS             The calling processor is an AP.
+  @retval EFI_DEVICE_ERROR        The calling processor is an AP.
   @retval EFI_NOT_FOUND           The processor with the handle specified by
                                   ProcessorNumber does not exist.
   @retval EFI_INVALID_PARAMETER   ProcessorNumber specifies the current BSP or
diff --git a/MdePkg/Include/Protocol/Mtftp4.h b/MdePkg/Include/Protocol/Mtftp4.h
index e24751dd5a04..ce7e940229c8 100644
--- a/MdePkg/Include/Protocol/Mtftp4.h
+++ b/MdePkg/Include/Protocol/Mtftp4.h
@@ -1,14 +1,8 @@
 /** @file
   EFI Multicast Trivial File Transfer Protocol Definition
 
-Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This Protocol is introduced in UEFI Specification 2.0
diff --git a/MdePkg/Include/Protocol/Mtftp6.h b/MdePkg/Include/Protocol/Mtftp6.h
index 3273550e3369..c15d45fcfd82 100644
--- a/MdePkg/Include/Protocol/Mtftp6.h
+++ b/MdePkg/Include/Protocol/Mtftp6.h
@@ -6,13 +6,7 @@
   Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.<BR>
   (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
 
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This Protocol is introduced in UEFI Specification 2.2
diff --git a/MdePkg/Include/Protocol/NetworkInterfaceIdentifier.h b/MdePkg/Include/Protocol/NetworkInterfaceIdentifier.h
index 1b7654503da0..f80374a07667 100644
--- a/MdePkg/Include/Protocol/NetworkInterfaceIdentifier.h
+++ b/MdePkg/Include/Protocol/NetworkInterfaceIdentifier.h
@@ -1,14 +1,8 @@
 /** @file
   EFI Network Interface Identifier Protocol.
 
-Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under
-the terms and conditions of the BSD License that accompanies this distribution.
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This Protocol is introduced in EFI Specification 1.10.
@@ -74,8 +68,8 @@ struct _EFI_NETWORK_INTERFACE_IDENTIFIER_PROTOCOL {
   UINT8     MajorVer;   ///< Major version number.
   UINT8     MinorVer;   ///< Minor version number.
   BOOLEAN   Ipv6Supported; ///< TRUE if the network interface supports IPv6; otherwise FALSE.
-  UINT16    IfNum;      ///< The network interface number that is being identified by this Network 
-                        ///< Interface Identifier Protocol. This field must be less than or 
+  UINT16    IfNum;      ///< The network interface number that is being identified by this Network
+                        ///< Interface Identifier Protocol. This field must be less than or
                         ///< equal to the (IFcnt | IFcntExt <<8 ) fields in the !PXE structure.
 
 };
@@ -109,7 +103,7 @@ struct undiconfig_table {
   struct {
     VOID             *NII_InterfacePointer; ///< Pointer to the NII interface structure.
     VOID             *DevicePathPointer;    ///< Pointer to the device path for this NIC.
-  } NII_entry[1]; 
+  } NII_entry[1];
 };
 
 extern EFI_GUID gEfiNetworkInterfaceIdentifierProtocolGuid;
diff --git a/MdePkg/Include/Protocol/NvdimmLabel.h b/MdePkg/Include/Protocol/NvdimmLabel.h
new file mode 100644
index 000000000000..c9b5642bc396
--- /dev/null
+++ b/MdePkg/Include/Protocol/NvdimmLabel.h
@@ -0,0 +1,345 @@
+/** @file
+  EFI NVDIMM Label Protocol Definition
+
+  The EFI NVDIMM Label Protocol is used to Provides services that allow management
+  of labels contained in a Label Storage Area that are associated with a specific
+  NVDIMM Device Path.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  This Protocol was introduced in UEFI Specification 2.7.
+
+**/
+
+#ifndef __EFI_NVDIMM_LABEL_PROTOCOL_H__
+#define __EFI_NVDIMM_LABEL_PROTOCOL_H__
+
+#define EFI_NVDIMM_LABEL_PROTOCOL_GUID \
+  { \
+    0xd40b6b80, 0x97d5, 0x4282, {0xbb, 0x1d, 0x22, 0x3a, 0x16, 0x91, 0x80, 0x58 } \
+  }
+
+typedef struct _EFI_NVDIMM_LABEL_PROTOCOL EFI_NVDIMM_LABEL_PROTOCOL;
+
+#define EFI_NVDIMM_LABEL_INDEX_SIG_LEN 16
+#define EFI_NVDIMM_LABEL_INDEX_ALIGN   256
+typedef struct {
+  ///
+  /// Signature of the Index Block data structure. Must be "NAMESPACE_INDEX\0".
+  ///
+  CHAR8  Sig[EFI_NVDIMM_LABEL_INDEX_SIG_LEN];
+
+  ///
+  /// Attributes of this Label Storage Area.
+  ///
+  UINT8  Flags[3];
+
+  ///
+  /// Size of each label in bytes, 128 bytes << LabelSize.
+  /// 1 means 256 bytes, 2 means 512 bytes, etc. Shall be 1 or greater.
+  ///
+  UINT8  LabelSize;
+
+  ///
+  /// Sequence number used to identify which of the two Index Blocks is current.
+  ///
+  UINT32 Seq;
+
+  ///
+  /// The offset of this Index Block in the Label Storage Area.
+  ///
+  UINT64 MyOff;
+
+  ///
+  /// The size of this Index Block in bytes.
+  /// This field must be a multiple of the EFI_NVDIMM_LABEL_INDEX_ALIGN.
+  ///
+  UINT64 MySize;
+
+  ///
+  /// The offset of the other Index Block paired with this one.
+  ///
+  UINT64 OtherOff;
+
+  ///
+  /// The offset of the first slot where labels are stored in this Label Storage Area.
+  ///
+  UINT64 LabelOff;
+
+  ///
+  /// The total number of slots for storing labels in this Label Storage Area.
+  ///
+  UINT32 NSlot;
+
+  ///
+  /// Major version number. Value shall be 1.
+  ///
+  UINT16 Major;
+
+  ///
+  /// Minor version number. Value shall be 2.
+  ///
+  UINT16 Minor;
+
+  ///
+  /// 64-bit Fletcher64 checksum of all fields in this Index Block.
+  ///
+  UINT64 Checksum;
+
+  ///
+  /// Array of unsigned bytes implementing a bitmask that tracks which label slots are free.
+  /// A bit value of 0 indicates in use, 1 indicates free.
+  /// The size of this field is the number of bytes required to hold the bitmask with NSlot bits,
+  /// padded with additional zero bytes to make the Index Block size a multiple of EFI_NVDIMM_LABEL_INDEX_ALIGN.
+  /// Any bits allocated beyond NSlot bits must be zero.
+  ///
+  UINT8  Free[];
+} EFI_NVDIMM_LABEL_INDEX_BLOCK;
+
+#define EFI_NVDIMM_LABEL_NAME_LEN 64
+
+///
+/// The label is read-only.
+///
+#define EFI_NVDIMM_LABEL_FLAGS_ROLABEL 0x00000001
+
+///
+/// When set, the complete label set is local to a single NVDIMM Label Storage Area.
+/// When clear, the complete label set is contained on multiple NVDIMM Label Storage Areas.
+///
+#define EFI_NVDIMM_LABEL_FLAGS_LOCAL 0x00000002
+
+///
+/// This reserved flag is utilized on older implementations and has been deprecated.
+/// Do not use.
+//
+#define EFI_NVDIMM_LABEL_FLAGS_RESERVED 0x00000004
+
+///
+/// When set, the label set is being updated.
+///
+#define EFI_NVDIMM_LABEL_FLAGS_UPDATING 0x00000008
+
+typedef struct {
+  ///
+  /// Unique Label Identifier UUID per RFC 4122.
+  ///
+  EFI_GUID Uuid;
+
+  ///
+  /// NULL-terminated string using UTF-8 character formatting.
+  ///
+  CHAR8    Name[EFI_NVDIMM_LABEL_NAME_LEN];
+
+  ///
+  /// Attributes of this namespace.
+  ///
+  UINT32   Flags;
+
+  ///
+  /// Total number of labels describing this namespace.
+  ///
+  UINT16   NLabel;
+
+  ///
+  /// Position of this label in list of labels for this namespace.
+  ///
+  UINT16   Position;
+
+  ///
+  /// The SetCookie is utilized by SW to perform consistency checks on the Interleave Set to verify the current
+  /// physical device configuration matches the original physical configuration when the labels were created
+  /// for the set.The label is considered invalid if the actual label set cookie doesn't match the cookie stored here.
+  ///
+  UINT64   SetCookie;
+
+  ///
+  /// This is the default logical block size in bytes and may be superseded by a block size that is specified
+  /// in the AbstractionGuid.
+  ///
+  UINT64   LbaSize;
+
+  ///
+  /// The DPA is the DIMM Physical address where the NVM contributing to this namespace begins on this NVDIMM.
+  ///
+  UINT64   Dpa;
+
+  ///
+  /// The extent of the DPA contributed by this label.
+  ///
+  UINT64   RawSize;
+
+  ///
+  /// Current slot in the Label Storage Area where this label is stored.
+  ///
+  UINT32   Slot;
+
+  ///
+  /// Alignment hint used to advertise the preferred alignment of the data from within the namespace defined by this label.
+  ///
+  UINT8    Alignment;
+
+  ///
+  /// Shall be 0.
+  ///
+  UINT8    Reserved[3];
+
+  ///
+  /// Range Type GUID that describes the access mechanism for the specified DPA range.
+  ///
+  EFI_GUID TypeGuid;
+
+  ///
+  /// Identifies the address abstraction mechanism for this namespace. A value of 0 indicates no mechanism used.
+  ///
+  EFI_GUID AddressAbstractionGuid;
+
+  ///
+  /// Shall be 0.
+  ///
+  UINT8    Reserved1[88];
+
+  ///
+  /// 64-bit Fletcher64 checksum of all fields in this Label.
+  /// This field is considered zero when the checksum is computed.
+  ///
+  UINT64   Checksum;
+} EFI_NVDIMM_LABEL;
+
+typedef struct  {
+  ///
+  /// The Region Offset field from the ACPI NFIT NVDIMM Region Mapping Structure for a given entry.
+  ///
+  UINT64 RegionOffset;
+
+  ///
+  /// The serial number of the NVDIMM, assigned by the module vendor.
+  ///
+  UINT32 SerialNumber;
+
+  ///
+  /// The identifier indicating the vendor of the NVDIMM.
+  ///
+  UINT16 VendorId;
+
+  ///
+  /// The manufacturing date of the NVDIMM, assigned by the module vendor.
+  ///
+  UINT16 ManufacturingDate;
+
+  ///
+  /// The manufacturing location from for the NVDIMM, assigned by the module vendor.
+  ///
+  UINT8  ManufacturingLocation;
+
+  ///
+  /// Shall be 0.
+  ///
+  UINT8  Reserved[31];
+} EFI_NVDIMM_LABEL_SET_COOKIE_MAP;
+
+typedef struct {
+  ///
+  /// Array size is 1 if EFI_NVDIMM_LABEL_FLAGS_LOCAL is set indicating a Local Namespaces.
+  ///
+  EFI_NVDIMM_LABEL_SET_COOKIE_MAP Mapping[0];
+} EFI_NVDIMM_LABEL_SET_COOKIE_INFO;
+
+/**
+  Retrieves the Label Storage Area size and the maximum transfer size for the LabelStorageRead and
+  LabelStorageWrite methods.
+
+  @param  This                   A pointer to the EFI_NVDIMM_LABEL_PROTOCOL instance.
+  @param  SizeOfLabelStorageArea The size of the Label Storage Area for the NVDIMM in bytes.
+  @param  MaxTransferLength      The maximum number of bytes that can be transferred in a single call to
+                                 LabelStorageRead or LabelStorageWrite.
+
+  @retval EFI_SUCCESS            The size of theLabel Storage Area and maximum transfer size returned are valid.
+  @retval EFI_ACCESS_DENIED      The Label Storage Area for the NVDIMM device is not currently accessible.
+  @retval EFI_DEVICE_ERROR       A physical device error occurred and the data transfer failed to complete.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_NVDIMM_LABEL_STORAGE_INFORMATION) (
+  IN  EFI_NVDIMM_LABEL_PROTOCOL *This,
+  OUT UINT32                    *SizeOfLabelStorageArea,
+  OUT UINT32                    *MaxTransferLength
+  );
+
+/**
+  Retrieves the label data for the requested offset and length from within the Label Storage Area for
+  the NVDIMM.
+
+  @param  This                   A pointer to the EFI_NVDIMM_LABEL_PROTOCOL instance.
+  @param  Offset                 The byte offset within the Label Storage Area to read from.
+  @param  TransferLength         Number of bytes to read from the Label Storage Area beginning at the byte
+                                 Offset specified. A TransferLength of 0 reads no data.
+  @param  LabelData              The return label data read at the requested offset and length from within
+                                 the Label Storage Area.
+
+  @retval EFI_SUCCESS            The label data from the Label Storage Area for the NVDIMM was read successfully
+                                 at the specified Offset and TransferLength and LabelData contains valid data.
+  @retval EFI_INVALID_PARAMETER  Any of the following are true:
+                                 - Offset > SizeOfLabelStorageArea reported in the LabelStorageInformation return data.
+                                 - Offset + TransferLength is > SizeOfLabelStorageArea reported in the
+                                   LabelStorageInformation return data.
+                                 - TransferLength is > MaxTransferLength reported in the LabelStorageInformation return
+                                   data.
+  @retval EFI_ACCESS_DENIED      The Label Storage Area for the NVDIMM device is not currently accessible and labels
+                                 cannot be read at this time.
+  @retval EFI_DEVICE_ERROR       A physical device error occurred and the data transfer failed to complete.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_NVDIMM_LABEL_STORAGE_READ) (
+  IN CONST EFI_NVDIMM_LABEL_PROTOCOL *This,
+  IN UINT32                          Offset,
+  IN UINT32                          TransferLength,
+  OUT UINT8                          *LabelData
+  );
+
+/**
+  Writes the label data for the requested offset and length in to the Label Storage Area for the NVDIMM.
+
+  @param  This                   A pointer to the EFI_NVDIMM_LABEL_PROTOCOL instance.
+  @param  Offset                 The byte offset within the Label Storage Area to write to.
+  @param  TransferLength         Number of bytes to write to the Label Storage Area beginning at the byte
+                                 Offset specified. A TransferLength of 0 writes no data.
+  @param  LabelData              The return label data write at the requested offset and length from within
+                                 the Label Storage Area.
+
+  @retval EFI_SUCCESS            The label data from the Label Storage Area for the NVDIMM written read successfully
+                                 at the specified Offset and TransferLength.
+  @retval EFI_INVALID_PARAMETER  Any of the following are true:
+                                 - Offset > SizeOfLabelStorageArea reported in the LabelStorageInformation return data.
+                                 - Offset + TransferLength is > SizeOfLabelStorageArea reported in the
+                                   LabelStorageInformation return data.
+                                 - TransferLength is > MaxTransferLength reported in the LabelStorageInformation return
+                                   data.
+  @retval EFI_ACCESS_DENIED      The Label Storage Area for the NVDIMM device is not currently accessible and labels
+                                 cannot be written at this time.
+  @retval EFI_DEVICE_ERROR       A physical device error occurred and the data transfer failed to complete.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_NVDIMM_LABEL_STORAGE_WRITE) (
+  IN CONST EFI_NVDIMM_LABEL_PROTOCOL *This,
+  IN UINT32                          Offset,
+  IN UINT32                          TransferLength,
+  IN UINT8                           *LabelData
+  );
+
+///
+/// Provides services that allow management of labels contained in a Label Storage Area.
+///
+struct _EFI_NVDIMM_LABEL_PROTOCOL {
+  EFI_NVDIMM_LABEL_STORAGE_INFORMATION LabelStorageInformation;
+  EFI_NVDIMM_LABEL_STORAGE_READ        LabelStorageRead;
+  EFI_NVDIMM_LABEL_STORAGE_WRITE       LabelStorageWrite;
+};
+
+extern EFI_GUID gEfiNvdimmLabelProtocolGuid;
+
+#endif
diff --git a/MdePkg/Include/Protocol/NvmExpressPassthru.h b/MdePkg/Include/Protocol/NvmExpressPassthru.h
index 15879e578d59..f804d0f88d0c 100644
--- a/MdePkg/Include/Protocol/NvmExpressPassthru.h
+++ b/MdePkg/Include/Protocol/NvmExpressPassthru.h
@@ -3,14 +3,11 @@
   NVM Express controller or to a specific namespace in a NVM Express controller.
   This protocol interface is optimized for storage.
 
-  Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php.
+  Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  @par Revision Reference:
+  This Protocol was introduced in UEFI Specification 2.5.
 
 **/
 
@@ -132,7 +129,7 @@ typedef struct {
   @param[in]     Event               If non-blocking I/O is not supported then Event is ignored, and blocking I/O is performed.
                                      If Event is NULL, then blocking I/O is performed. If Event is not NULL and non-blocking I/O
                                      is supported, then non-blocking I/O is performed, and Event will be signaled when the NVM
-                                     Express Command Packet completes. 
+                                     Express Command Packet completes.
 
   @retval EFI_SUCCESS                The NVM Express Command Packet was sent by the host. TransferLength bytes were transferred
                                      to, or from DataBuffer.
@@ -162,7 +159,7 @@ EFI_STATUS
   Used to retrieve the next namespace ID for this NVM Express controller.
 
   The EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNextNamespace() function retrieves the next valid
-  namespace ID on this NVM Express controller. 
+  namespace ID on this NVM Express controller.
 
   If on input the value pointed to by NamespaceId is 0xFFFFFFFF, then the first valid namespace
   ID defined on the NVM Express controller is returned in the location pointed to by NamespaceId
@@ -206,7 +203,7 @@ EFI_STATUS
 
   If the NamespaceId is not valid, then EFI_NOT_FOUND is returned.
 
-  If DevicePath is NULL, then EFI_INVALID_PARAMETER is returned. 
+  If DevicePath is NULL, then EFI_INVALID_PARAMETER is returned.
 
   If there are not enough resources to allocate the device path node, then EFI_OUT_OF_RESOURCES is returned.
 
@@ -217,7 +214,7 @@ EFI_STATUS
   @param[in]     NamespaceId         The NVM Express namespace ID  for which a device path node is to be
                                      allocated and built. Caller must set the NamespaceId to zero if the
                                      device path node will contain a valid UUID.
-  @param[in,out] DevicePath          A pointer to a single device path node that describes the NVM Express
+  @param[out]    DevicePath          A pointer to a single device path node that describes the NVM Express
                                      namespace specified by NamespaceId. This function is responsible for
                                      allocating the buffer DevicePath with the boot service AllocatePool().
                                      It is the caller's responsibility to free DevicePath when the caller
@@ -234,7 +231,7 @@ EFI_STATUS
 (EFIAPI *EFI_NVM_EXPRESS_PASS_THRU_BUILD_DEVICE_PATH)(
   IN     EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL          *This,
   IN     UINT32                                      NamespaceId,
-  IN OUT EFI_DEVICE_PATH_PROTOCOL                    **DevicePath
+  OUT    EFI_DEVICE_PATH_PROTOCOL                    **DevicePath
   );
 
 /**
diff --git a/MdePkg/Include/Protocol/PartitionInfo.h b/MdePkg/Include/Protocol/PartitionInfo.h
new file mode 100644
index 000000000000..cabf140eb3e9
--- /dev/null
+++ b/MdePkg/Include/Protocol/PartitionInfo.h
@@ -0,0 +1,68 @@
+/** @file
+  This file defines the EFI Partition Information Protocol.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  This Protocol is introduced in UEFI Specification 2.7
+
+**/
+
+#ifndef __PARTITION_INFO_PROTOCOL_H__
+#define __PARTITION_INFO_PROTOCOL_H__
+
+#include <IndustryStandard/Mbr.h>
+#include <Uefi/UefiGpt.h>
+
+//
+// EFI Partition Information Protocol GUID value
+//
+#define EFI_PARTITION_INFO_PROTOCOL_GUID \
+  { 0x8cf2f62c, 0xbc9b, 0x4821, { 0x80, 0x8d, 0xec, 0x9e, 0xc4, 0x21, 0xa1, 0xa0 }};
+
+
+#define EFI_PARTITION_INFO_PROTOCOL_REVISION     0x0001000
+#define PARTITION_TYPE_OTHER                     0x00
+#define PARTITION_TYPE_MBR                       0x01
+#define PARTITION_TYPE_GPT                       0x02
+
+#pragma pack(1)
+
+///
+/// Partition Information Protocol structure.
+///
+typedef struct {
+  //
+  // Set to EFI_PARTITION_INFO_PROTOCOL_REVISION.
+  //
+  UINT32                     Revision;
+  //
+  // Partition info type (PARTITION_TYPE_MBR, PARTITION_TYPE_GPT, or PARTITION_TYPE_OTHER).
+  //
+  UINT32                     Type;
+  //
+  // If 1, partition describes an EFI System Partition.
+  //
+  UINT8                      System;
+  UINT8                      Reserved[7];
+  union {
+    ///
+    /// MBR data
+    ///
+    MBR_PARTITION_RECORD     Mbr;
+    ///
+    /// GPT data
+    ///
+    EFI_PARTITION_ENTRY      Gpt;
+  } Info;
+} EFI_PARTITION_INFO_PROTOCOL;
+
+#pragma pack()
+
+///
+/// Partition Information Protocol GUID variable.
+///
+extern EFI_GUID gEfiPartitionInfoProtocolGuid;
+
+#endif
diff --git a/MdePkg/Include/Protocol/Pcd.h b/MdePkg/Include/Protocol/Pcd.h
index e75b4e513bbc..e0eb679e745d 100644
--- a/MdePkg/Include/Protocol/Pcd.h
+++ b/MdePkg/Include/Protocol/Pcd.h
@@ -2,18 +2,15 @@
   Native Platform Configuration Database (PCD) Protocol
 
   Different with the EFI_PCD_PROTOCOL defined in PI 1.2 specification, the native
-  PCD protocol provide interfaces for dynamic and dynamic-ex type PCD. 
+  PCD protocol provide interfaces for dynamic and dynamic-ex type PCD.
   The interfaces in dynamic type PCD do not require the token space guid as parameter,
   but interfaces in dynamic-ex type PCD require token space guid as parameter.
-  
-Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  This Protocol was introduced in PI Specification 1.2.
 
 **/
 
@@ -31,26 +28,26 @@ extern EFI_GUID gPcdProtocolGuid;
 /**
   Sets the SKU value for subsequent calls to set or get PCD token values.
 
-  SetSku() sets the SKU Id to be used for subsequent calls to set or get PCD values. 
+  SetSku() sets the SKU Id to be used for subsequent calls to set or get PCD values.
   SetSku() is normally called only once by the system.
 
-  For each item (token), the database can hold a single value that applies to all SKUs, 
-  or multiple values, where each value is associated with a specific SKU Id. Items with multiple, 
-  SKU-specific values are called SKU enabled. 
-  
-  The SKU Id of zero is reserved as a default. The valid SkuId range is 1 to 255.  
-  For tokens that are not SKU enabled, the system ignores any set SKU Id and works with the 
-  single value for that token. For SKU-enabled tokens, the system will use the SKU Id set by the 
-  last call to SetSku(). If no SKU Id is set or the currently set SKU Id isn't valid for the specified token, 
-  the system uses the default SKU Id. If the system attempts to use the default SKU Id and no value has been 
+  For each item (token), the database can hold a single value that applies to all SKUs,
+  or multiple values, where each value is associated with a specific SKU Id. Items with multiple,
+  SKU-specific values are called SKU enabled.
+
+  The SKU Id of zero is reserved as a default. The valid SkuId range is 1 to 255.
+  For tokens that are not SKU enabled, the system ignores any set SKU Id and works with the
+  single value for that token. For SKU-enabled tokens, the system will use the SKU Id set by the
+  last call to SetSku(). If no SKU Id is set or the currently set SKU Id isn't valid for the specified token,
+  the system uses the default SKU Id. If the system attempts to use the default SKU Id and no value has been
   set for that Id, the results are unpredictable.
 
-  @param[in]  SkuId The SKU value that will be used when the PCD service will retrieve and 
+  @param[in]  SkuId The SKU value that will be used when the PCD service will retrieve and
                     set values associated with a PCD token.
 
 
 **/
-typedef 
+typedef
 VOID
 (EFIAPI *PCD_PROTOCOL_SET_SKU)(
   IN  UINTN                  SkuId
@@ -61,13 +58,13 @@ VOID
 /**
   Retrieves an 8-bit value for a given PCD token.
 
-  Retrieves the current byte-sized value for a PCD token number.  
+  Retrieves the current byte-sized value for a PCD token number.
   If the TokenNumber is invalid, the results are unpredictable.
-  
-  @param[in]  TokenNumber The PCD token number. 
+
+  @param[in]  TokenNumber The PCD token number.
 
   @return The UINT8 value.
-  
+
 **/
 typedef
 UINT8
@@ -80,13 +77,13 @@ UINT8
 /**
   Retrieves a 16-bit value for a given PCD token.
 
-  Retrieves the current 16-bit value for a PCD token number.  
+  Retrieves the current 16-bit value for a PCD token number.
   If the TokenNumber is invalid, the results are unpredictable.
-  
-  @param[in]  TokenNumber The PCD token number. 
+
+  @param[in]  TokenNumber The PCD token number.
 
   @return The UINT16 value.
-  
+
 **/
 typedef
 UINT16
@@ -99,13 +96,13 @@ UINT16
 /**
   Retrieves a 32-bit value for a given PCD token.
 
-  Retrieves the current 32-bit value for a PCD token number.  
+  Retrieves the current 32-bit value for a PCD token number.
   If the TokenNumber is invalid, the results are unpredictable.
-  
-  @param[in]  TokenNumber The PCD token number. 
+
+  @param[in]  TokenNumber The PCD token number.
 
   @return The UINT32 value.
-  
+
 **/
 typedef
 UINT32
@@ -118,13 +115,13 @@ UINT32
 /**
   Retrieves a 64-bit value for a given PCD token.
 
-  Retrieves the current 64-bit value for a PCD token number.  
+  Retrieves the current 64-bit value for a PCD token number.
   If the TokenNumber is invalid, the results are unpredictable.
-  
-  @param[in]  TokenNumber The PCD token number. 
+
+  @param[in]  TokenNumber The PCD token number.
 
   @return The UINT64 value.
-  
+
 **/
 typedef
 UINT64
@@ -137,15 +134,15 @@ UINT64
 /**
   Retrieves a pointer to a value for a given PCD token.
 
-  Retrieves the current pointer to the buffer for a PCD token number.  
-  Do not make any assumptions about the alignment of the pointer that 
-  is returned by this function call.  If the TokenNumber is invalid, 
+  Retrieves the current pointer to the buffer for a PCD token number.
+  Do not make any assumptions about the alignment of the pointer that
+  is returned by this function call.  If the TokenNumber is invalid,
   the results are unpredictable.
 
-  @param[in]  TokenNumber The PCD token number. 
+  @param[in]  TokenNumber The PCD token number.
 
   @return The pointer to the buffer to be retrived.
-  
+
 **/
 typedef
 VOID *
@@ -158,15 +155,15 @@ VOID *
 /**
   Retrieves a Boolean value for a given PCD token.
 
-  Retrieves the current boolean value for a PCD token number.  
-  Do not make any assumptions about the alignment of the pointer that 
-  is returned by this function call.  If the TokenNumber is invalid, 
+  Retrieves the current boolean value for a PCD token number.
+  Do not make any assumptions about the alignment of the pointer that
+  is returned by this function call.  If the TokenNumber is invalid,
   the results are unpredictable.
 
-  @param[in]  TokenNumber The PCD token number. 
+  @param[in]  TokenNumber The PCD token number.
 
   @return The Boolean value.
-  
+
 **/
 typedef
 BOOLEAN
@@ -179,13 +176,13 @@ BOOLEAN
 /**
   Retrieves the size of the value for a given PCD token.
 
-  Retrieves the current size of a particular PCD token.  
+  Retrieves the current size of a particular PCD token.
   If the TokenNumber is invalid, the results are unpredictable.
 
-  @param[in]  TokenNumber The PCD token number. 
+  @param[in]  TokenNumber The PCD token number.
 
   @return The size of the value for the PCD token.
-  
+
 **/
 typedef
 UINTN
@@ -198,16 +195,16 @@ UINTN
 /**
   Retrieves an 8-bit value for a given PCD token.
 
-  Retrieves the 8-bit value of a particular PCD token.  
+  Retrieves the 8-bit value of a particular PCD token.
   If the TokenNumber is invalid or the token space
-  specified by Guid does not exist, the results are 
+  specified by Guid does not exist, the results are
   unpredictable.
 
   @param[in]  Guid        The token space for the token number.
-  @param[in]  TokenNumber The PCD token number. 
+  @param[in]  TokenNumber The PCD token number.
 
   @return The size 8-bit value for the PCD token.
-  
+
 **/
 typedef
 UINT8
@@ -221,16 +218,16 @@ UINT8
 /**
   Retrieves a 16-bit value for a given PCD token.
 
-  Retrieves the 16-bit value of a particular PCD token.  
+  Retrieves the 16-bit value of a particular PCD token.
   If the TokenNumber is invalid or the token space
-  specified by Guid does not exist, the results are 
+  specified by Guid does not exist, the results are
   unpredictable.
 
   @param[in]  Guid        The token space for the token number.
-  @param[in]  TokenNumber The PCD token number. 
+  @param[in]  TokenNumber The PCD token number.
 
   @return The size 16-bit value for the PCD token.
-  
+
 **/
 typedef
 UINT16
@@ -244,16 +241,16 @@ UINT16
 /**
   Retrieves a 32-bit value for a given PCD token.
 
-  Retrieves the 32-bit value of a particular PCD token.  
+  Retrieves the 32-bit value of a particular PCD token.
   If the TokenNumber is invalid or the token space
-  specified by Guid does not exist, the results are 
+  specified by Guid does not exist, the results are
   unpredictable.
 
   @param[in]  Guid        The token space for the token number.
-  @param[in]  TokenNumber The PCD token number. 
+  @param[in]  TokenNumber The PCD token number.
 
   @return The size 32-bit value for the PCD token.
-  
+
 **/
 typedef
 UINT32
@@ -267,16 +264,16 @@ UINT32
 /**
   Retrieves an 64-bit value for a given PCD token.
 
-  Retrieves the 64-bit value of a particular PCD token.  
+  Retrieves the 64-bit value of a particular PCD token.
   If the TokenNumber is invalid or the token space
-  specified by Guid does not exist, the results are 
+  specified by Guid does not exist, the results are
   unpredictable.
 
   @param[in]  Guid        The token space for the token number.
-  @param[in]  TokenNumber The PCD token number. 
+  @param[in]  TokenNumber The PCD token number.
 
   @return The size 64-bit value for the PCD token.
-  
+
 **/
 typedef
 UINT64
@@ -290,16 +287,16 @@ UINT64
 /**
   Retrieves a pointer to a value for a given PCD token.
 
-  Retrieves the current pointer to the buffer for a PCD token number.  
-  Do not make any assumptions about the alignment of the pointer that 
-  is returned by this function call.  If the TokenNumber is invalid, 
+  Retrieves the current pointer to the buffer for a PCD token number.
+  Do not make any assumptions about the alignment of the pointer that
+  is returned by this function call.  If the TokenNumber is invalid,
   the results are unpredictable.
 
   @param[in]  Guid        The token space for the token number.
-  @param[in]  TokenNumber The PCD token number. 
+  @param[in]  TokenNumber The PCD token number.
 
   @return The pointer to the buffer to be retrieved.
-  
+
 **/
 typedef
 VOID *
@@ -313,16 +310,16 @@ VOID *
 /**
   Retrieves a Boolean value for a given PCD token.
 
-  Retrieves the Boolean value of a particular PCD token.  
+  Retrieves the Boolean value of a particular PCD token.
   If the TokenNumber is invalid or the token space
-  specified by Guid does not exist, the results are 
+  specified by Guid does not exist, the results are
   unpredictable.
 
   @param[in]  Guid        The token space for the token number.
-  @param[in]  TokenNumber The PCD token number. 
+  @param[in]  TokenNumber The PCD token number.
 
   @return The size Boolean value for the PCD token.
-  
+
 **/
 typedef
 BOOLEAN
@@ -336,14 +333,14 @@ BOOLEAN
 /**
   Retrieves the size of the value for a given PCD token.
 
-  Retrieves the current size of a particular PCD token.  
+  Retrieves the current size of a particular PCD token.
   If the TokenNumber is invalid, the results are unpredictable.
 
   @param[in]  Guid        The token space for the token number.
-  @param[in]  TokenNumber The PCD token number. 
+  @param[in]  TokenNumber The PCD token number.
 
   @return The size of the value for the PCD token.
-  
+
 **/
 typedef
 UINTN
@@ -357,19 +354,19 @@ UINTN
 /**
   Sets an 8-bit value for a given PCD token.
 
-  When the PCD service sets a value, it will check to ensure that the 
-  size of the value being set is compatible with the Token's existing definition.  
+  When the PCD service sets a value, it will check to ensure that the
+  size of the value being set is compatible with the Token's existing definition.
   If it is not, an error will be returned.
 
-  @param[in]  TokenNumber The PCD token number. 
+  @param[in]  TokenNumber The PCD token number.
   @param[in]  Value       The value to set for the PCD token.
 
   @retval EFI_SUCCESS  The procedure returned successfully.
-  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data 
-                                  being set was incompatible with a call to this function.  
+  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data
+                                  being set was incompatible with a call to this function.
                                   Use GetSize() to retrieve the size of the target data.
   @retval EFI_NOT_FOUND The PCD service could not find the requested token number.
-  
+
 **/
 typedef
 EFI_STATUS
@@ -383,19 +380,19 @@ EFI_STATUS
 /**
   Sets a 16-bit value for a given PCD token.
 
-  When the PCD service sets a value, it will check to ensure that the 
-  size of the value being set is compatible with the Token's existing definition.  
+  When the PCD service sets a value, it will check to ensure that the
+  size of the value being set is compatible with the Token's existing definition.
   If it is not, an error will be returned.
 
-  @param[in]  TokenNumber The PCD token number. 
+  @param[in]  TokenNumber The PCD token number.
   @param[in]  Value       The value to set for the PCD token.
 
   @retval EFI_SUCCESS  The procedure returned successfully.
-  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data 
-                                  being set was incompatible with a call to this function.  
+  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data
+                                  being set was incompatible with a call to this function.
                                   Use GetSize() to retrieve the size of the target data.
   @retval EFI_NOT_FOUND The PCD service could not find the requested token number.
-  
+
 **/
 typedef
 EFI_STATUS
@@ -409,19 +406,19 @@ EFI_STATUS
 /**
   Sets a 32-bit value for a given PCD token.
 
-  When the PCD service sets a value, it will check to ensure that the 
-  size of the value being set is compatible with the Token's existing definition.  
+  When the PCD service sets a value, it will check to ensure that the
+  size of the value being set is compatible with the Token's existing definition.
   If it is not, an error will be returned.
 
-  @param[in]  TokenNumber The PCD token number. 
+  @param[in]  TokenNumber The PCD token number.
   @param[in]  Value       The value to set for the PCD token.
 
   @retval EFI_SUCCESS  The procedure returned successfully.
-  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data 
-                                  being set was incompatible with a call to this function.  
+  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data
+                                  being set was incompatible with a call to this function.
                                   Use GetSize() to retrieve the size of the target data.
   @retval EFI_NOT_FOUND The PCD service could not find the requested token number.
-  
+
 **/
 typedef
 EFI_STATUS
@@ -435,19 +432,19 @@ EFI_STATUS
 /**
   Sets a 64-bit value for a given PCD token.
 
-  When the PCD service sets a value, it will check to ensure that the 
-  size of the value being set is compatible with the Token's existing definition.  
+  When the PCD service sets a value, it will check to ensure that the
+  size of the value being set is compatible with the Token's existing definition.
   If it is not, an error will be returned.
 
-  @param[in]  TokenNumber The PCD token number. 
+  @param[in]  TokenNumber The PCD token number.
   @param[in]  Value       The value to set for the PCD token.
 
   @retval EFI_SUCCESS  The procedure returned successfully.
-  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data 
-                                  being set was incompatible with a call to this function.  
+  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data
+                                  being set was incompatible with a call to this function.
                                   Use GetSize() to retrieve the size of the target data.
   @retval EFI_NOT_FOUND The PCD service could not find the requested token number.
-  
+
 **/
 typedef
 EFI_STATUS
@@ -461,23 +458,23 @@ EFI_STATUS
 /**
   Sets a value of a specified size for a given PCD token.
 
-  When the PCD service sets a value, it will check to ensure that the 
-  size of the value being set is compatible with the Token's existing definition.  
+  When the PCD service sets a value, it will check to ensure that the
+  size of the value being set is compatible with the Token's existing definition.
   If it is not, an error will be returned.
 
-  @param[in]      TokenNumber  The PCD token number. 
-  @param[in, out] SizeOfBuffer A pointer to the length of the value being set for the PCD token.  
-                               On input, if the SizeOfValue is greater than the maximum size supported 
-                               for this TokenNumber then the output value of SizeOfValue will reflect 
+  @param[in]      TokenNumber  The PCD token number.
+  @param[in, out] SizeOfBuffer A pointer to the length of the value being set for the PCD token.
+                               On input, if the SizeOfValue is greater than the maximum size supported
+                               for this TokenNumber then the output value of SizeOfValue will reflect
                                the maximum size supported for this TokenNumber.
   @param[in]      Buffer       The buffer to set for the PCD token.
 
   @retval EFI_SUCCESS  The procedure returned successfully.
-  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data 
-                                  being set was incompatible with a call to this function.  
+  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data
+                                  being set was incompatible with a call to this function.
                                   Use GetSize() to retrieve the size of the target data.
   @retval EFI_NOT_FOUND The PCD service could not find the requested token number.
-  
+
 **/
 typedef
 EFI_STATUS
@@ -492,19 +489,19 @@ EFI_STATUS
 /**
   Sets a Boolean value for a given PCD token.
 
-  When the PCD service sets a value, it will check to ensure that the 
-  size of the value being set is compatible with the Token's existing definition.  
+  When the PCD service sets a value, it will check to ensure that the
+  size of the value being set is compatible with the Token's existing definition.
   If it is not, an error will be returned.
 
-  @param[in]  TokenNumber The PCD token number. 
+  @param[in]  TokenNumber The PCD token number.
   @param[in]  Value       The value to set for the PCD token.
 
   @retval EFI_SUCCESS  The procedure returned successfully.
-  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data 
-                                  being set was incompatible with a call to this function.  
+  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data
+                                  being set was incompatible with a call to this function.
                                   Use GetSize() to retrieve the size of the target data.
   @retval EFI_NOT_FOUND The PCD service could not find the requested token number.
-  
+
 **/
 typedef
 EFI_STATUS
@@ -518,20 +515,20 @@ EFI_STATUS
 /**
   Sets an 8-bit value for a given PCD token.
 
-  When the PCD service sets a value, it will check to ensure that the 
-  size of the value being set is compatible with the Token's existing definition.  
+  When the PCD service sets a value, it will check to ensure that the
+  size of the value being set is compatible with the Token's existing definition.
   If it is not, an error will be returned.
 
   @param[in]  Guid        The 128-bit unique value that designates the namespace from which to extract the value.
-  @param[in]  TokenNumber The PCD token number. 
+  @param[in]  TokenNumber The PCD token number.
   @param[in]  Value       The value to set for the PCD token.
 
   @retval EFI_SUCCESS  The procedure returned successfully.
-  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data 
-                                  being set was incompatible with a call to this function.  
+  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data
+                                  being set was incompatible with a call to this function.
                                   Use GetSize() to retrieve the size of the target data.
   @retval EFI_NOT_FOUND The PCD service could not find the requested token number.
-  
+
 **/
 typedef
 EFI_STATUS
@@ -546,20 +543,20 @@ EFI_STATUS
 /**
   Sets an 16-bit value for a given PCD token.
 
-  When the PCD service sets a value, it will check to ensure that the 
-  size of the value being set is compatible with the Token's existing definition.  
+  When the PCD service sets a value, it will check to ensure that the
+  size of the value being set is compatible with the Token's existing definition.
   If it is not, an error will be returned.
 
   @param[in]  Guid        The 128-bit unique value that designates the namespace from which to extract the value.
-  @param[in]  TokenNumber The PCD token number. 
+  @param[in]  TokenNumber The PCD token number.
   @param[in]  Value       The value to set for the PCD token.
 
   @retval EFI_SUCCESS  The procedure returned successfully.
-  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data 
-                                  being set was incompatible with a call to this function.  
+  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data
+                                  being set was incompatible with a call to this function.
                                   Use GetSize() to retrieve the size of the target data.
   @retval EFI_NOT_FOUND The PCD service could not find the requested token number.
-  
+
 **/
 typedef
 EFI_STATUS
@@ -574,20 +571,20 @@ EFI_STATUS
 /**
   Sets a 32-bit value for a given PCD token.
 
-  When the PCD service sets a value, it will check to ensure that the 
-  size of the value being set is compatible with the Token's existing definition.  
+  When the PCD service sets a value, it will check to ensure that the
+  size of the value being set is compatible with the Token's existing definition.
   If it is not, an error will be returned.
 
   @param[in]  Guid        The 128-bit unique value that designates the namespace from which to extract the value.
-  @param[in]  TokenNumber The PCD token number. 
+  @param[in]  TokenNumber The PCD token number.
   @param[in]  Value       The value to set for the PCD token.
 
   @retval EFI_SUCCESS  The procedure returned successfully.
-  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data 
-                                  being set was incompatible with a call to this function.  
+  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data
+                                  being set was incompatible with a call to this function.
                                   Use GetSize() to retrieve the size of the target data.
   @retval EFI_NOT_FOUND The PCD service could not find the requested token number.
-  
+
 **/
 typedef
 EFI_STATUS
@@ -602,20 +599,20 @@ EFI_STATUS
 /**
   Sets a 64-bit value for a given PCD token.
 
-  When the PCD service sets a value, it will check to ensure that the 
-  size of the value being set is compatible with the Token's existing definition.  
+  When the PCD service sets a value, it will check to ensure that the
+  size of the value being set is compatible with the Token's existing definition.
   If it is not, an error will be returned.
 
   @param[in]  Guid        The 128-bit unique value that designates the namespace from which to extract the value.
-  @param[in]  TokenNumber The PCD token number. 
+  @param[in]  TokenNumber The PCD token number.
   @param[in]  Value       The value to set for the PCD token.
 
   @retval EFI_SUCCESS  The procedure returned successfully.
-  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data 
-                                  being set was incompatible with a call to this function.  
+  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data
+                                  being set was incompatible with a call to this function.
                                   Use GetSize() to retrieve the size of the target data.
   @retval EFI_NOT_FOUND The PCD service could not find the requested token number.
-  
+
 **/
 typedef
 EFI_STATUS
@@ -630,24 +627,24 @@ EFI_STATUS
 /**
   Sets a value of a specified size for a given PCD token.
 
-  When the PCD service sets a value, it will check to ensure that the 
-  size of the value being set is compatible with the Token's existing definition.  
+  When the PCD service sets a value, it will check to ensure that the
+  size of the value being set is compatible with the Token's existing definition.
   If it is not, an error will be returned.
 
   @param[in]  Guid            The 128-bit unique value that designates the namespace from which to extract the value.
-  @param[in]  TokenNumber     The PCD token number. 
-  @param[in, out] SizeOfBuffer A pointer to the length of the value being set for the PCD token.  
-                              On input, if the SizeOfValue is greater than the maximum size supported 
-                              for this TokenNumber then the output value of SizeOfValue will reflect 
+  @param[in]  TokenNumber     The PCD token number.
+  @param[in, out] SizeOfBuffer A pointer to the length of the value being set for the PCD token.
+                              On input, if the SizeOfValue is greater than the maximum size supported
+                              for this TokenNumber then the output value of SizeOfValue will reflect
                               the maximum size supported for this TokenNumber.
   @param[in]  Buffer          The buffer to set for the PCD token.
 
   @retval EFI_SUCCESS  The procedure returned successfully.
-  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data 
-                                  being set was incompatible with a call to this function.  
+  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data
+                                  being set was incompatible with a call to this function.
                                   Use GetSize() to retrieve the size of the target data.
   @retval EFI_NOT_FOUND The PCD service could not find the requested token number.
-  
+
 **/
 typedef
 EFI_STATUS
@@ -663,20 +660,20 @@ EFI_STATUS
 /**
   Sets a Boolean value for a given PCD token.
 
-  When the PCD service sets a value, it will check to ensure that the 
-  size of the value being set is compatible with the Token's existing definition.  
+  When the PCD service sets a value, it will check to ensure that the
+  size of the value being set is compatible with the Token's existing definition.
   If it is not, an error will be returned.
 
   @param[in]  Guid        The 128-bit unique value that designates the namespace from which to extract the value.
-  @param[in]  TokenNumber The PCD token number. 
+  @param[in]  TokenNumber The PCD token number.
   @param[in]  Value       The value to set for the PCD token.
 
   @retval EFI_SUCCESS  The procedure returned successfully.
-  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data 
-                                  being set was incompatible with a call to this function.  
+  @retval EFI_INVALID_PARAMETER The PCD service determined that the size of the data
+                                  being set was incompatible with a call to this function.
                                   Use GetSize() to retrieve the size of the target data.
   @retval EFI_NOT_FOUND The PCD service could not find the requested token number.
-  
+
 **/
 typedef
 EFI_STATUS
@@ -685,18 +682,18 @@ EFI_STATUS
   IN UINTN             TokenNumber,
   IN BOOLEAN           Value
   );
-  
+
 
 
 /**
   Callback on SET function prototype definition.
 
-  This notification function serves two purposes. 
-  Firstly, it notifies the module which did the registration that the value 
-  of this PCD token has been set. Secondly, it provides a mechanism for the 
-  module that did the registration to intercept the set operation and override 
-  the value that has been set, if necessary. After the invocation of the callback function, 
-  TokenData will be used by PCD service DXE driver to modify the internal data in 
+  This notification function serves two purposes.
+  Firstly, it notifies the module which did the registration that the value
+  of this PCD token has been set. Secondly, it provides a mechanism for the
+  module that did the registration to intercept the set operation and override
+  the value that has been set, if necessary. After the invocation of the callback function,
+  TokenData will be used by PCD service DXE driver to modify the internal data in
   PCD database.
 
   @param[in]  CallBackGuid    The PCD token GUID being set.
@@ -721,11 +718,11 @@ VOID
 /**
   Specifies a function to be called anytime the value of a designated token is changed.
 
-  @param[in]  TokenNumber       The PCD token number. 
+  @param[in]  TokenNumber       The PCD token number.
   @param[in]  Guid              The 128-bit unique value that designates the namespace from which to extract the value.
-  @param[in]  CallBackFunction  The function prototype called when the value associated with the CallBackToken is set.  
+  @param[in]  CallBackFunction  The function prototype called when the value associated with the CallBackToken is set.
 
-  @retval EFI_SUCCESS   The PCD service has successfully established a call event 
+  @retval EFI_SUCCESS   The PCD service has successfully established a call event
                         for the CallBackToken requested.
   @retval EFI_NOT_FOUND The PCD service could not find the referenced token number.
 
@@ -743,11 +740,11 @@ EFI_STATUS
 /**
   Cancels a previously set callback function for a particular PCD token number.
 
-  @param[in]  TokenNumber      The PCD token number. 
+  @param[in]  TokenNumber      The PCD token number.
   @param[in]  Guid             The 128-bit unique value that designates the namespace from which to extract the value.
-  @param[in]  CallBackFunction The function prototype called when the value associated with the CallBackToken is set.  
+  @param[in]  CallBackFunction The function prototype called when the value associated with the CallBackToken is set.
 
-  @retval EFI_SUCCESS   The PCD service has successfully established a call event 
+  @retval EFI_SUCCESS   The PCD service has successfully established a call event
                         for the CallBackToken requested.
   @retval EFI_NOT_FOUND The PCD service could not find the referenced token number.
 
@@ -763,32 +760,32 @@ EFI_STATUS
 
 
 /**
-  Retrieves the next valid token number in a given namespace.  
-  
-  This is useful since the PCD infrastructure contains a sparse list of token numbers, 
+  Retrieves the next valid token number in a given namespace.
+
+  This is useful since the PCD infrastructure contains a sparse list of token numbers,
   and one cannot a priori know what token numbers are valid in the database.
-  
-  If TokenNumber is 0 and Guid is not NULL, then the first token from the token space specified by Guid is returned.  
-  If TokenNumber is not 0 and Guid is not NULL, then the next token in the token space specified by Guid is returned.  
-  If TokenNumber is 0 and Guid is NULL, then the first token in the default token space is returned.  
-  If TokenNumber is not 0 and Guid is NULL, then the next token in the default token space is returned.  
-  The token numbers in the default token space may not be related to token numbers in token spaces that are named by Guid.  
-  If the next token number can be retrieved, then it is returned in TokenNumber, and EFI_SUCCESS is returned.  
-  If TokenNumber represents the last token number in the token space specified by Guid, then EFI_NOT_FOUND is returned.  
+
+  If TokenNumber is 0 and Guid is not NULL, then the first token from the token space specified by Guid is returned.
+  If TokenNumber is not 0 and Guid is not NULL, then the next token in the token space specified by Guid is returned.
+  If TokenNumber is 0 and Guid is NULL, then the first token in the default token space is returned.
+  If TokenNumber is not 0 and Guid is NULL, then the next token in the default token space is returned.
+  The token numbers in the default token space may not be related to token numbers in token spaces that are named by Guid.
+  If the next token number can be retrieved, then it is returned in TokenNumber, and EFI_SUCCESS is returned.
+  If TokenNumber represents the last token number in the token space specified by Guid, then EFI_NOT_FOUND is returned.
   If TokenNumber is not present in the token space specified by Guid, then EFI_NOT_FOUND is returned.
 
 
-  @param[in]      Guid    The 128-bit unique value that designates the namespace from which to retrieve the next token. 
-                          This is an optional parameter that may be NULL. If this parameter is NULL, then a request is 
+  @param[in]      Guid    The 128-bit unique value that designates the namespace from which to retrieve the next token.
+                          This is an optional parameter that may be NULL. If this parameter is NULL, then a request is
                           being made to retrieve tokens from the default token space.
-  @param[in,out]  TokenNumber 
-                          A pointer to the PCD token number to use to find the subsequent token number.  
+  @param[in,out]  TokenNumber
+                          A pointer to the PCD token number to use to find the subsequent token number.
 
   @retval EFI_SUCCESS   The PCD service has retrieved the next valid token number.
   @retval EFI_NOT_FOUND The PCD service could not find data from the requested token number.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *PCD_PROTOCOL_GET_NEXT_TOKEN)(
   IN      CONST EFI_GUID      *Guid, OPTIONAL
@@ -813,7 +810,7 @@ EFI_STATUS
   @retval   EFI_NOT_FOUND The PCD service could not find the next valid token namespace.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *PCD_PROTOCOL_GET_NEXT_TOKENSPACE)(
   IN  OUT    CONST EFI_GUID      **Guid
diff --git a/MdePkg/Include/Protocol/PcdInfo.h b/MdePkg/Include/Protocol/PcdInfo.h
index e34967e0a3e8..3f461b978acd 100644
--- a/MdePkg/Include/Protocol/PcdInfo.h
+++ b/MdePkg/Include/Protocol/PcdInfo.h
@@ -4,18 +4,15 @@
   The protocol that provides additional information about items that reside in the PCD database.
 
   Different with the EFI_GET_PCD_INFO_PROTOCOL defined in PI 1.2.1 specification,
-  the native PCD INFO PROTOCOL provide interfaces for dynamic and dynamic-ex type PCD. 
+  the native PCD INFO PROTOCOL provide interfaces for dynamic and dynamic-ex type PCD.
   The interfaces for dynamic type PCD do not require the token space guid as parameter,
   but interfaces for dynamic-ex type PCD require token space guid as parameter.
 
-  Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
+  Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  @par Revision Reference:
+  This Protocol was introduced in PI Specification 1.2.
 
 **/
 
diff --git a/MdePkg/Include/Protocol/PciEnumerationComplete.h b/MdePkg/Include/Protocol/PciEnumerationComplete.h
index c817774cb3c5..8054c48b6af4 100644
--- a/MdePkg/Include/Protocol/PciEnumerationComplete.h
+++ b/MdePkg/Include/Protocol/PciEnumerationComplete.h
@@ -3,13 +3,7 @@
   This protocol indicates that pci enumeration complete
 
   Copyright (c) 2009, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This Protocol is defined in UEFI Platform Initialization Specification 1.2
diff --git a/MdePkg/Include/Protocol/PciHostBridgeResourceAllocation.h b/MdePkg/Include/Protocol/PciHostBridgeResourceAllocation.h
index 2d41ac152990..744c47aaac72 100644
--- a/MdePkg/Include/Protocol/PciHostBridgeResourceAllocation.h
+++ b/MdePkg/Include/Protocol/PciHostBridgeResourceAllocation.h
@@ -1,21 +1,15 @@
 /** @file
-  This file declares PCI Host Bridge Resource Allocation Protocol which 
-  provides the basic interfaces to abstract a PCI host bridge resource allocation. 
+  This file declares PCI Host Bridge Resource Allocation Protocol which
+  provides the basic interfaces to abstract a PCI host bridge resource allocation.
   This protocol is mandatory if the system includes PCI devices.
-  
-Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
-  This Protocol is defined in UEFI Platform Initialization Specification 1.2 
+  This Protocol is defined in UEFI Platform Initialization Specification 1.2
   Volume 5: Standards.
-  
+
 **/
 
 #ifndef _PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_H_
@@ -56,14 +50,14 @@ typedef struct _EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL EFI_PCI_HOST_BR
 #define EFI_PCI_HOST_BRIDGE_MEM64_DECODE   2
 
 ///
-/// A UINT64 value that contains the status of a PCI resource requested 
+/// A UINT64 value that contains the status of a PCI resource requested
 /// in the Configuration parameter returned by GetProposedResources()
 /// The legal values are EFI_RESOURCE_SATISFIED and EFI_RESOURCE_NOT_SATISFIED
 ///
 typedef UINT64 EFI_RESOURCE_ALLOCATION_STATUS;
 
 ///
-/// The request of this resource type could be fulfilled.  Used in the 
+/// The request of this resource type could be fulfilled.  Used in the
 /// Configuration parameter returned by GetProposedResources() to identify
 /// a PCI resources request that can be satisfied.
 ///
@@ -71,7 +65,7 @@ typedef UINT64 EFI_RESOURCE_ALLOCATION_STATUS;
 
 ///
 /// The request of this resource type could not be fulfilled for its
-/// absence in the host bridge resource pool.  Used in the Configuration parameter 
+/// absence in the host bridge resource pool.  Used in the Configuration parameter
 /// returned by GetProposedResources() to identify a PCI resources request that
 /// can not be satisfied.
 ///
@@ -92,45 +86,45 @@ typedef enum {
   ///
   /// The bus allocation phase is about to begin. No specific action
   /// is required here. This notification can be used to perform any
-  /// chipset specific programming.  
+  /// chipset specific programming.
   ///
   EfiPciHostBridgeBeginBusAllocation,
 
   ///
   /// The bus allocation and bus programming phase is complete. No specific
   /// action is required here. This notification can be used to perform any
-  /// chipset specific programming.  
+  /// chipset specific programming.
   ///
   EfiPciHostBridgeEndBusAllocation,
-  
+
   ///
   /// The resource allocation phase is about to begin.No specific action is
-  /// required here. This notification can be used to perform any chipset specific programming.  
+  /// required here. This notification can be used to perform any chipset specific programming.
   ///
   EfiPciHostBridgeBeginResourceAllocation,
-  
+
   ///
   /// Allocate resources per previously submitted requests for all the PCI Root
   /// Bridges. These resource settings are returned on the next call to
-  /// GetProposedResources().  
+  /// GetProposedResources().
   ///
   EfiPciHostBridgeAllocateResources,
-  
+
   ///
   /// Program the Host Bridge hardware to decode previously allocated resources
   /// (proposed resources) for all the PCI Root Bridges.
   ///
   EfiPciHostBridgeSetResources,
-  
+
   ///
   /// De-allocate previously allocated resources previously for all the PCI
-  /// Root Bridges and reset the I/O and memory apertures to initial state.  
+  /// Root Bridges and reset the I/O and memory apertures to initial state.
   ///
   EfiPciHostBridgeFreeResources,
-  
+
   ///
   /// The resource allocation phase is completed.  No specific action is required
-  /// here. This notification can be used to perform any chipset specific programming.  
+  /// here. This notification can be used to perform any chipset specific programming.
   ///
   EfiPciHostBridgeEndResourceAllocation,
 
@@ -158,30 +152,30 @@ typedef enum {
 
   ///
   /// This notification is sent before the PCI enumerator probes BAR registers
-  /// for every valid PCI function.  
+  /// for every valid PCI function.
   ///
   EfiPciBeforeResourceCollection
 } EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE;
 
 /**
-  These are the notifications from the PCI bus driver that it is about to enter a certain phase of the PCI 
+  These are the notifications from the PCI bus driver that it is about to enter a certain phase of the PCI
   enumeration process.
 
-  @param[in] This    The pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL 
+  @param[in] This    The pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
                      instance.
   @param[in] Phase   The phase during enumeration.
 
   @retval EFI_SUCCESS             The notification was accepted without any errors.
   @retval EFI_INVALID_PARAMETER   The Phase is invalid.
-  @retval EFI_NOT_READY           This phase cannot be entered at this time. For example, this error 
-                                  is valid for a Phase of EfiPciHostBridgeAllocateResources if 
-                                  SubmitResources() has not been called for one or more 
+  @retval EFI_NOT_READY           This phase cannot be entered at this time. For example, this error
+                                  is valid for a Phase of EfiPciHostBridgeAllocateResources if
+                                  SubmitResources() has not been called for one or more
                                   PCI root bridges before this call.
-  @retval EFI_DEVICE_ERROR        Programming failed due to a hardware error. This error is valid for 
+  @retval EFI_DEVICE_ERROR        Programming failed due to a hardware error. This error is valid for
                                   a Phase of EfiPciHostBridgeSetResources.
-  @retval EFI_OUT_OF_RESOURCES    The request could not be completed due to a lack of resources. 
+  @retval EFI_OUT_OF_RESOURCES    The request could not be completed due to a lack of resources.
                                   This error is valid for a Phase of EfiPciHostBridgeAllocateResources
-                                  if the previously submitted resource requests cannot be fulfilled or were only 
+                                  if the previously submitted resource requests cannot be fulfilled or were only
                                   partially fulfilled
 
 **/
@@ -195,15 +189,15 @@ EFI_STATUS
 /**
   Returns the device handle of the next PCI root bridge that is associated with this host bridge.
 
-  @param[in]     This               The pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL 
+  @param[in]     This               The pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
                                     instance.
-  @param[in,out] RootBridgeHandle   Returns the device handle of the next PCI root bridge. On input, it holds the 
-                                    RootBridgeHandle that was returned by the most recent call to 
-                                    GetNextRootBridge(). If RootBridgeHandle is NULL on input, the handle 
+  @param[in,out] RootBridgeHandle   Returns the device handle of the next PCI root bridge. On input, it holds the
+                                    RootBridgeHandle that was returned by the most recent call to
+                                    GetNextRootBridge(). If RootBridgeHandle is NULL on input, the handle
                                     for the first PCI root bridge is returned.
 
   @retval EFI_SUCCESS             The requested attribute information was returned.
-  @retval EFI_INVALID_PARAMETER   RootBridgeHandle is not an EFI_HANDLE that was returned 
+  @retval EFI_INVALID_PARAMETER   RootBridgeHandle is not an EFI_HANDLE that was returned
                                   on a previous call to GetNextRootBridge().
   @retval EFI_NOT_FOUND           There are no more PCI root bridge device handles.
 
@@ -218,7 +212,7 @@ EFI_STATUS
 /**
   Returns the allocation attributes of a PCI root bridge.
 
-  @param[in]  This               The pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL 
+  @param[in]  This               The pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
                                  instance.
   @param[in]  RootBridgeHandle   The device handle of the PCI root bridge in which the caller is interested.
   @param[out] Attribute          The pointer to attributes of the PCI root bridge.
@@ -239,12 +233,12 @@ EFI_STATUS
 /**
   Sets up the specified PCI root bridge for the bus enumeration process.
 
-  @param[in]  This               The pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL 
+  @param[in]  This               The pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
                                  instance.
   @param[in]  RootBridgeHandle   The PCI root bridge to be set up.
   @param[out] Configuration      The pointer to the pointer to the PCI bus resource descriptor.
 
-  @retval EFI_SUCCESS             The PCI root bridge was set up and the bus range was returned in 
+  @retval EFI_SUCCESS             The PCI root bridge was set up and the bus range was returned in
                                   Configuration.
   @retval EFI_INVALID_PARAMETER   RootBridgeHandle is not a valid root bridge handle.
   @retval EFI_DEVICE_ERROR        Programming failed due to a hardware error.
@@ -263,20 +257,20 @@ EFI_STATUS
   Programs the PCI root bridge hardware so that it decodes the specified PCI bus range.
 
   @param[in] This               The pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
-                                instance.  
+                                instance.
   @param[in] RootBridgeHandle   The PCI root bridge whose bus range is to be programmed.
   @param[in] Configuration      The pointer to the PCI bus resource descriptor.
 
   @retval EFI_SUCCESS             The bus range for the PCI root bridge was programmed.
   @retval EFI_INVALID_PARAMETER   RootBridgeHandle is not a valid root bridge handle.
   @retval EFI_INVALID_PARAMETER   Configuration is NULL
-  @retval EFI_INVALID_PARAMETER   Configuration does not point to a valid ACPI (2.0 & 3.0) 
+  @retval EFI_INVALID_PARAMETER   Configuration does not point to a valid ACPI (2.0 & 3.0)
                                   resource descriptor.
   @retval EFI_INVALID_PARAMETER   Configuration does not include a valid ACPI 2.0 bus resource
                                   descriptor.
-  @retval EFI_INVALID_PARAMETER   Configuration includes valid ACPI (2.0 & 3.0) resource 
+  @retval EFI_INVALID_PARAMETER   Configuration includes valid ACPI (2.0 & 3.0) resource
                                   descriptors other than bus descriptors.
-  @retval EFI_INVALID_PARAMETER   Configuration contains one or more invalid ACPI resource 
+  @retval EFI_INVALID_PARAMETER   Configuration contains one or more invalid ACPI resource
                                   descriptors.
   @retval EFI_INVALID_PARAMETER   "Address Range Minimum" is invalid for this root bridge.
   @retval EFI_INVALID_PARAMETER   "Address Range Length" is invalid for this root bridge.
@@ -294,26 +288,26 @@ EFI_STATUS
 /**
   Submits the I/O and memory resource requirements for the specified PCI root bridge.
 
-  @param[in] This               The pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL 
+  @param[in] This               The pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
                                 instance.
-  @param[in] RootBridgeHandle   The PCI root bridge whose I/O and memory resource requirements are being 
+  @param[in] RootBridgeHandle   The PCI root bridge whose I/O and memory resource requirements are being
                                 submitted.
   @param[in] Configuration      The pointer to the PCI I/O and PCI memory resource descriptor.
 
-  @retval EFI_SUCCESS             The I/O and memory resource requests for a PCI root bridge were 
+  @retval EFI_SUCCESS             The I/O and memory resource requests for a PCI root bridge were
                                   accepted.
   @retval EFI_INVALID_PARAMETER   RootBridgeHandle is not a valid root bridge handle.
   @retval EFI_INVALID_PARAMETER   Configuration is NULL.
-  @retval EFI_INVALID_PARAMETER   Configuration does not point to a valid ACPI (2.0 & 3.0) 
+  @retval EFI_INVALID_PARAMETER   Configuration does not point to a valid ACPI (2.0 & 3.0)
                                   resource descriptor.
-  @retval EFI_INVALID_PARAMETER   Configuration includes requests for one or more resource 
-                                  types that are not supported by this PCI root bridge. This error will 
-                                  happen if the caller did not combine resources according to 
+  @retval EFI_INVALID_PARAMETER   Configuration includes requests for one or more resource
+                                  types that are not supported by this PCI root bridge. This error will
+                                  happen if the caller did not combine resources according to
                                   Attributes that were returned by GetAllocAttributes().
   @retval EFI_INVALID_PARAMETER   "Address Range Maximum" is invalid.
   @retval EFI_INVALID_PARAMETER   "Address Range Length" is invalid for this PCI root bridge.
   @retval EFI_INVALID_PARAMETER   "Address Space Granularity" is invalid for this PCI root bridge.
-  
+
 **/
 typedef
 EFI_STATUS
@@ -326,7 +320,7 @@ EFI_STATUS
 /**
   Returns the proposed resource settings for the specified PCI root bridge.
 
-  @param[in]  This               The pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL 
+  @param[in]  This               The pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
                                  instance.
   @param[in]  RootBridgeHandle   The PCI root bridge handle.
   @param[out] Configuration      The pointer to the pointer to the PCI I/O and memory resource descriptor.
@@ -346,8 +340,8 @@ EFI_STATUS
   );
 
 /**
-  Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various 
-  stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual 
+  Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various
+  stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual
   PCI controllers before enumeration.
 
   @param[in]  This                  The pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
@@ -357,10 +351,10 @@ EFI_STATUS
 
   @retval EFI_SUCCESS             The requested parameters were returned.
   @retval EFI_INVALID_PARAMETER   RootBridgeHandle is not a valid root bridge handle.
-  @retval EFI_INVALID_PARAMETER   Phase is not a valid phase that is defined in 
+  @retval EFI_INVALID_PARAMETER   Phase is not a valid phase that is defined in
                                   EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.
-  @retval EFI_DEVICE_ERROR        Programming failed due to a hardware error. The PCI enumerator 
-                                  should not enumerate this device, including its child devices if it is 
+  @retval EFI_DEVICE_ERROR        Programming failed due to a hardware error. The PCI enumerator
+                                  should not enumerate this device, including its child devices if it is
                                   a PCI-to-PCI bridge.
 
 **/
@@ -382,43 +376,43 @@ struct _EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL {
   /// a certain phase during the enumeration process.
   ///
   EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_NOTIFY_PHASE           NotifyPhase;
-  
+
   ///
   /// Retrieves the device handle for the next PCI root bridge that is produced by the
-  /// host bridge to which this instance of the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is attached.  
+  /// host bridge to which this instance of the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is attached.
   ///
   EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_NEXT_ROOT_BRIDGE   GetNextRootBridge;
-  
+
   ///
   /// Retrieves the allocation-related attributes of a PCI root bridge.
   ///
   EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_ATTRIBUTES         GetAllocAttributes;
-  
+
   ///
   /// Sets up a PCI root bridge for bus enumeration.
   ///
   EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_START_BUS_ENUMERATION  StartBusEnumeration;
-  
+
   ///
   /// Sets up the PCI root bridge so that it decodes a specific range of bus numbers.
   ///
   EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_SET_BUS_NUMBERS        SetBusNumbers;
-  
+
   ///
   /// Submits the resource requirements for the specified PCI root bridge.
   ///
   EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_SUBMIT_RESOURCES       SubmitResources;
-  
+
   ///
   /// Returns the proposed resource assignment for the specified PCI root bridges.
   ///
   EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_PROPOSED_RESOURCES GetProposedResources;
-  
+
   ///
   /// Provides hooks from the PCI bus driver to every PCI controller
   /// (device/function) at various stages of the PCI enumeration process that
   /// allow the host bridge driver to preinitialize individual PCI controllers
-  /// before enumeration.  
+  /// before enumeration.
   ///
   EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_PREPROCESS_CONTROLLER  PreprocessController;
 };
diff --git a/MdePkg/Include/Protocol/PciHotPlugInit.h b/MdePkg/Include/Protocol/PciHotPlugInit.h
index 65701773825d..9cf91479ad84 100644
--- a/MdePkg/Include/Protocol/PciHotPlugInit.h
+++ b/MdePkg/Include/Protocol/PciHotPlugInit.h
@@ -1,56 +1,50 @@
 /** @file
   This file declares EFI PCI Hot Plug Init Protocol.
-  
-  This protocol provides the necessary functionality to initialize the Hot Plug 
-  Controllers (HPCs) and the buses that they control. This protocol also provides 
+
+  This protocol provides the necessary functionality to initialize the Hot Plug
+  Controllers (HPCs) and the buses that they control. This protocol also provides
   information regarding resource padding.
-  
-  @par Note: 
+
+  @par Note:
     This protocol is required only on platforms that support one or more PCI Hot
-    Plug* slots or CardBus sockets.  
+    Plug* slots or CardBus sockets.
 
   The EFI_PCI_HOT_PLUG_INIT_PROTOCOL provides a mechanism for the PCI bus enumerator
-  to properly initialize the HPCs and CardBus sockets that require initialization. 
-  The HPC initialization takes place before the PCI enumeration process is complete. 
-  There cannot be more than one instance of this protocol in a system. This protocol 
-  is installed on its own separate handle.  
-  
-  Because the system may include multiple HPCs, one instance of this protocol 
-  should represent all of them. The protocol functions use the device path of 
-  the HPC to identify the HPC. When the PCI bus enumerator finds a root HPC, it 
+  to properly initialize the HPCs and CardBus sockets that require initialization.
+  The HPC initialization takes place before the PCI enumeration process is complete.
+  There cannot be more than one instance of this protocol in a system. This protocol
+  is installed on its own separate handle.
+
+  Because the system may include multiple HPCs, one instance of this protocol
+  should represent all of them. The protocol functions use the device path of
+  the HPC to identify the HPC. When the PCI bus enumerator finds a root HPC, it
   will call EFI_PCI_HOT_PLUG_INIT_PROTOCOL.InitializeRootHpc(). If InitializeRootHpc()
-  is unable to initialize a root HPC, the PCI enumerator will ignore that root HPC 
-  and continue the enumeration process. If the HPC is not initialized, the devices 
+  is unable to initialize a root HPC, the PCI enumerator will ignore that root HPC
+  and continue the enumeration process. If the HPC is not initialized, the devices
   that it controls may not be initialized, and no resource padding will be provided.
 
-  From the standpoint of the PCI bus enumerator, HPCs are divided into the following 
+  From the standpoint of the PCI bus enumerator, HPCs are divided into the following
   two classes:
 
     - Root HPC:
-        These HPCs must be initialized by calling InitializeRootHpc() during the 
-        enumeration process. These HPCs will also require resource padding. The 
-        platform code must have a priori knowledge of these devices and must know 
-        how to initialize them. There may not be any way to access their PCI 
+        These HPCs must be initialized by calling InitializeRootHpc() during the
+        enumeration process. These HPCs will also require resource padding. The
+        platform code must have a priori knowledge of these devices and must know
+        how to initialize them. There may not be any way to access their PCI
         configuration space before the PCI enumerator programs all the upstream
-        bridges and thus enables the path to these devices. The PCI bus enumerator 
-        is responsible for determining the PCI bus address of the HPC before it 
+        bridges and thus enables the path to these devices. The PCI bus enumerator
+        is responsible for determining the PCI bus address of the HPC before it
         calls InitializeRootHpc().
     - Nonroot HPC:
-        These HPCs will not need explicit initialization during enumeration process. 
-        These HPCs will require resource padding. The platform code does not have 
+        These HPCs will not need explicit initialization during enumeration process.
+        These HPCs will require resource padding. The platform code does not have
         to have a priori knowledge of these devices.
 
-  Copyright (c) 2007 - 2009, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
-  This Protocol is defined in UEFI Platform Initialization Specification 1.2 
+  This Protocol is defined in UEFI Platform Initialization Specification 1.2
   Volume 5: Standards
 
 **/
@@ -77,15 +71,15 @@ typedef struct _EFI_PCI_HOT_PLUG_INIT_PROTOCOL EFI_PCI_HOT_PLUG_INIT_PROTOCOL;
 typedef UINT16 EFI_HPC_STATE;
 
 ///
-/// The HPC initialization function was called and the HPC completed 
-/// initialization, but it was not enabled for some reason. The HPC may be 
-/// disabled in hardware, or it may be disabled due to user preferences, 
+/// The HPC initialization function was called and the HPC completed
+/// initialization, but it was not enabled for some reason. The HPC may be
+/// disabled in hardware, or it may be disabled due to user preferences,
 /// hardware failure, or other reasons. No resource padding is required.
 ///
 #define  EFI_HPC_STATE_INITIALIZED    0x01
 
 ///
-/// The HPC initialization function was called, the HPC completed 
+/// The HPC initialization function was called, the HPC completed
 /// initialization, and it was enabled. Resource padding is required.
 ///
 #define  EFI_HPC_STATE_ENABLED        0x02
@@ -95,18 +89,18 @@ typedef UINT16 EFI_HPC_STATE;
 ///
 typedef struct{
   ///
-  /// 
+  ///
   /// The device path to the root HPC. An HPC cannot control its parent buses.
-  /// The PCI bus driver requires this information so that it can pass the 
-  /// correct HpcPciAddress to the InitializeRootHpc() and GetResourcePadding() 
-  /// functions. 
+  /// The PCI bus driver requires this information so that it can pass the
+  /// correct HpcPciAddress to the InitializeRootHpc() and GetResourcePadding()
+  /// functions.
   ///
   EFI_DEVICE_PATH_PROTOCOL  *HpcDevicePath;
   ///
-  /// The device path to the Hot Plug Bus (HPB) that is controlled by the root 
-  /// HPC. The PCI bus driver uses this information to check if a particular PCI 
-  /// bus has hot-plug slots.  The device path of a PCI bus is the same as the 
-  /// device path of its parent. For Standard(PCI) Hot Plug Controllers (SHPCs) 
+  /// The device path to the Hot Plug Bus (HPB) that is controlled by the root
+  /// HPC. The PCI bus driver uses this information to check if a particular PCI
+  /// bus has hot-plug slots.  The device path of a PCI bus is the same as the
+  /// device path of its parent. For Standard(PCI) Hot Plug Controllers (SHPCs)
   /// and PCI Express*, HpbDevicePath is the same as HpcDevicePath.
   ///
   EFI_DEVICE_PATH_PROTOCOL  *HpbDevicePath;
@@ -131,7 +125,7 @@ typedef enum {
   /// strategy may reduce the total amount of padding, but requires
   /// reprogramming of PCI-to-PCI bridges in a hot-add event. If the hotplug
   /// bus is behind a PCI-to-PCI bridge, the PCI-to-PCI bridge
-  /// apertures do not indicate the padding for that bus.  
+  /// apertures do not indicate the padding for that bus.
   ///
   EfiPaddingPciRootBridge
 } EFI_HPC_PADDING_ATTRIBUTES;
@@ -140,14 +134,14 @@ typedef enum {
   Returns a list of root Hot Plug Controllers (HPCs) that require initialization
   during the boot process.
 
-  This procedure returns a list of root HPCs. The PCI bus driver must initialize 
-  these controllers during the boot process. The PCI bus driver may or may not be 
-  able to detect these HPCs. If the platform includes a PCI-to-CardBus bridge, it 
-  can be included in this list if it requires initialization.  The HpcList must be 
-  self consistent. An HPC cannot control any of its parent buses. Only one HPC can 
-  control a PCI bus. Because this list includes only root HPCs, no HPC in the list 
-  can be a child of another HPC. This policy must be enforced by the 
-  EFI_PCI_HOT_PLUG_INIT_PROTOCOL.   The PCI bus driver may not check for such 
+  This procedure returns a list of root HPCs. The PCI bus driver must initialize
+  these controllers during the boot process. The PCI bus driver may or may not be
+  able to detect these HPCs. If the platform includes a PCI-to-CardBus bridge, it
+  can be included in this list if it requires initialization.  The HpcList must be
+  self consistent. An HPC cannot control any of its parent buses. Only one HPC can
+  control a PCI bus. Because this list includes only root HPCs, no HPC in the list
+  can be a child of another HPC. This policy must be enforced by the
+  EFI_PCI_HOT_PLUG_INIT_PROTOCOL.   The PCI bus driver may not check for such
   invalid conditions.  The callee allocates the buffer HpcList
 
   @param[in]  This       Pointer to the EFI_PCI_HOT_PLUG_INIT_PROTOCOL instance.
@@ -156,7 +150,7 @@ typedef enum {
                          elements in this list.
 
   @retval EFI_SUCCESS             HpcList was returned.
-  @retval EFI_OUT_OF_RESOURCES    HpcList was not returned due to insufficient 
+  @retval EFI_OUT_OF_RESOURCES    HpcList was not returned due to insufficient
                                   resources.
   @retval EFI_INVALID_PARAMETER   HpcCount is NULL or HpcList is NULL.
 
@@ -172,26 +166,26 @@ EFI_STATUS
 /**
   Initializes one root Hot Plug Controller (HPC). This process may causes
   initialization of its subordinate buses.
-  
-  This function initializes the specified HPC. At the end of initialization, 
-  the hot-plug slots or sockets (controlled by this HPC) are powered and are 
-  connected to the bus. All the necessary registers in the HPC are set up. For 
-  a Standard (PCI) Hot Plug Controller (SHPC), the registers that must be set 
-  up are defined in the PCI Standard Hot Plug Controller and Subsystem 
-  Specification.  
+
+  This function initializes the specified HPC. At the end of initialization,
+  the hot-plug slots or sockets (controlled by this HPC) are powered and are
+  connected to the bus. All the necessary registers in the HPC are set up. For
+  a Standard (PCI) Hot Plug Controller (SHPC), the registers that must be set
+  up are defined in the PCI Standard Hot Plug Controller and Subsystem
+  Specification.
 
   @param[in]  This            Pointer to the EFI_PCI_HOT_PLUG_INIT_PROTOCOL instance.
   @param[in]  HpcDevicePath   The device path to the HPC that is being initialized.
   @param[in]  HpcPciAddress   The address of the HPC function on the PCI bus.
-  @param[in]  Event           The event that should be signaled when the HPC 
-                              initialization is complete.  Set to NULL if the 
-                              caller wants to wait until the entire initialization 
+  @param[in]  Event           The event that should be signaled when the HPC
+                              initialization is complete.  Set to NULL if the
+                              caller wants to wait until the entire initialization
                               process is complete.
-  @param[out] HpcState        The state of the HPC hardware. The state is 
+  @param[out] HpcState        The state of the HPC hardware. The state is
                               EFI_HPC_STATE_INITIALIZED or EFI_HPC_STATE_ENABLED.
 
   @retval EFI_SUCCESS             If Event is NULL, the specific HPC was successfully
-                                  initialized. If Event is not NULL, Event will be 
+                                  initialized. If Event is not NULL, Event will be
                                   signaled at a later time when initialization is complete.
   @retval EFI_UNSUPPORTED         This instance of EFI_PCI_HOT_PLUG_INIT_PROTOCOL
                                   does not support the specified HPC.
@@ -215,10 +209,10 @@ EFI_STATUS
   by the specified Hot Plug Controller (HPC).
 
   This function returns the resource padding that is required by the PCI bus that
-  is controlled by the specified HPC. This member function is called for all the 
-  root HPCs and nonroot HPCs that are detected by the PCI bus enumerator. This 
-  function will be called before PCI resource allocation is completed. This function 
-  must be called after all the root HPCs, with the possible exception of a 
+  is controlled by the specified HPC. This member function is called for all the
+  root HPCs and nonroot HPCs that are detected by the PCI bus enumerator. This
+  function will be called before PCI resource allocation is completed. This function
+  must be called after all the root HPCs, with the possible exception of a
   PCI-to-CardBus bridge, have completed initialization.
 
   @param[in]  This            Pointer to the EFI_PCI_HOT_PLUG_INIT_PROTOCOL instance.
@@ -261,12 +255,12 @@ struct _EFI_PCI_HOT_PLUG_INIT_PROTOCOL {
   /// Returns a list of root HPCs and the buses that they control.
   ///
   EFI_GET_ROOT_HPC_LIST     GetRootHpcList;
-  
+
   ///
   /// Initializes the specified root HPC.
   ///
   EFI_INITIALIZE_ROOT_HPC   InitializeRootHpc;
-  
+
   ///
   /// Returns the resource padding that is required by the HPC.
   ///
diff --git a/MdePkg/Include/Protocol/PciHotPlugRequest.h b/MdePkg/Include/Protocol/PciHotPlugRequest.h
index c96b789b5695..dff7f6e98039 100644
--- a/MdePkg/Include/Protocol/PciHotPlugRequest.h
+++ b/MdePkg/Include/Protocol/PciHotPlugRequest.h
@@ -1,46 +1,40 @@
 /** @file
-  Provides services to notify the PCI bus driver that some events have happened 
-  in a hot-plug controller (such as a PC Card socket, or PHPC), and to ask the 
+  Provides services to notify the PCI bus driver that some events have happened
+  in a hot-plug controller (such as a PC Card socket, or PHPC), and to ask the
   PCI bus driver to create or destroy handles for PCI-like devices.
 
-  A hot-plug capable PCI bus driver should produce the EFI PCI Hot Plug Request 
+  A hot-plug capable PCI bus driver should produce the EFI PCI Hot Plug Request
   protocol. When a PCI device or a PCI-like device (for example, 32-bit PC Card)
-  is installed after PCI bus does the enumeration, the PCI bus driver can be 
+  is installed after PCI bus does the enumeration, the PCI bus driver can be
   notified through this protocol. For example, when a 32-bit PC Card is inserted
   into the PC Card socket, the PC Card bus driver can call interface of this
   protocol to notify PCI bus driver to allocate resource and create handles for
   this PC Card.
-  
-  The EFI_PCI_HOTPLUG_REQUEST_PROTOCOL is installed by the PCI bus driver on a 
-  separate handle when PCI bus driver starts up. There is only one instance in 
+
+  The EFI_PCI_HOTPLUG_REQUEST_PROTOCOL is installed by the PCI bus driver on a
+  separate handle when PCI bus driver starts up. There is only one instance in
   the system.  Any driver that wants to use this protocol must locate it globally.
-  The EFI_PCI_HOTPLUG_REQUEST_PROTOCOL allows the driver of hot-plug controller, 
-  for example, PC Card Bus driver, to notify PCI bus driver that an event has 
-  happened in the hot-plug controller, and the PCI bus driver is requested to 
-  create (add) or destroy (remove) handles for the specified PCI-like devices. 
-  For example, when a 32-bit PC Card is inserted, this protocol interface will 
-  be called with an add operation, and the PCI bus driver will enumerate and 
-  start the devices inserted; when a 32-bit PC Card is removed, this protocol 
-  interface will be called with a remove operation, and the PCI bus driver will 
-  stop the devices and destroy their handles.  The existence of this protocol 
+  The EFI_PCI_HOTPLUG_REQUEST_PROTOCOL allows the driver of hot-plug controller,
+  for example, PC Card Bus driver, to notify PCI bus driver that an event has
+  happened in the hot-plug controller, and the PCI bus driver is requested to
+  create (add) or destroy (remove) handles for the specified PCI-like devices.
+  For example, when a 32-bit PC Card is inserted, this protocol interface will
+  be called with an add operation, and the PCI bus driver will enumerate and
+  start the devices inserted; when a 32-bit PC Card is removed, this protocol
+  interface will be called with a remove operation, and the PCI bus driver will
+  stop the devices and destroy their handles.  The existence of this protocol
   represents the capability of the PCI bus driver. If this protocol exists in
-  system, it means PCI bus driver is hot-plug capable, thus together with the 
+  system, it means PCI bus driver is hot-plug capable, thus together with the
   effort of PC Card bus driver, hot-plug of PC Card can be supported. Otherwise,
-  the hot-plug capability is not provided.  
-  
-  Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-                                                                                            
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  the hot-plug capability is not provided.
+
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
-  This Protocol is defined in UEFI Platform Initialization Specification 1.2 
+  This Protocol is defined in UEFI Platform Initialization Specification 1.2
   Volume 5: Standards
-  
+
 **/
 
 #ifndef __PCI_HOTPLUG_REQUEST_H_
@@ -61,7 +55,7 @@ typedef struct _EFI_PCI_HOTPLUG_REQUEST_PROTOCOL  EFI_PCI_HOTPLUG_REQUEST_PROTOC
 
 ///
 /// Enumeration of PCI hot plug operations
-/// 
+///
 typedef enum {
   ///
   /// The PCI bus driver is requested to create handles for the specified devices.
@@ -78,65 +72,65 @@ typedef enum {
 
 /**
   This function is used to notify PCI bus driver that some events happened in a
-  hot-plug controller, and the PCI bus driver is requested to start or stop 
+  hot-plug controller, and the PCI bus driver is requested to start or stop
   specified PCI-like devices.
-  
+
   This function allows the PCI bus driver to be notified to act as requested when
-  a hot-plug event has happened on the hot-plug controller. Currently, the 
+  a hot-plug event has happened on the hot-plug controller. Currently, the
   operations include add operation and remove operation.  If it is a add operation,
-  the PCI bus driver will enumerate, allocate resources for devices behind the 
+  the PCI bus driver will enumerate, allocate resources for devices behind the
   hot-plug controller, and create handle for the device specified by RemainingDevicePath.
-  The RemainingDevicePath is an optional parameter. If it is not NULL, only the 
-  specified device is started; if it is NULL, all devices behind the hot-plug 
-  controller are started.  The newly created handles of PC Card functions are 
+  The RemainingDevicePath is an optional parameter. If it is not NULL, only the
+  specified device is started; if it is NULL, all devices behind the hot-plug
+  controller are started.  The newly created handles of PC Card functions are
   returned in the ChildHandleBuffer, together with the number of child handle in
   NumberOfChildren.  If it is a remove operation, when NumberOfChildren contains
   a non-zero value, child handles specified in ChildHandleBuffer are stopped and
   destroyed; otherwise, PCI bus driver is notified to stop managing the controller
-  handle.  
-    
-    @param[in] This                    A pointer to the EFI_PCI_HOTPLUG_REQUEST_PROTOCOL 
+  handle.
+
+    @param[in] This                    A pointer to the EFI_PCI_HOTPLUG_REQUEST_PROTOCOL
                                        instance.
-    @param[in] Operation               The operation the PCI bus driver is requested 
-                                       to make. 
+    @param[in] Operation               The operation the PCI bus driver is requested
+                                       to make.
     @param[in] Controller              The handle of the hot-plug controller.
     @param[in] RemainingDevicePath     The remaining device path for the PCI-like
                                        hot-plug device.  It only contains device
-                                       path nodes behind the hot-plug controller. 
+                                       path nodes behind the hot-plug controller.
                                        It is an optional parameter and only valid
-                                       when the Operation is a add operation. If 
-                                       it is NULL, all devices behind the PC Card 
+                                       when the Operation is a add operation. If
+                                       it is NULL, all devices behind the PC Card
                                        socket are started.
-    @param[in,out] NumberOfChildren    The number of child handles. For an add 
+    @param[in,out] NumberOfChildren    The number of child handles. For an add
                                        operation, it is an output parameter.  For
                                        a remove operation, it's an input parameter.
                                        When it contains a non-zero value, children
                                        handles specified in ChildHandleBuffer are
-                                       destroyed.  Otherwise, PCI bus driver is 
-                                       notified to stop managing the controller 
+                                       destroyed.  Otherwise, PCI bus driver is
+                                       notified to stop managing the controller
                                        handle.
-    @param[in,out] ChildHandleBuffer   The buffer which contains the child handles. 
-                                       For an add operation, it is an output 
-                                       parameter and contains all newly created 
+    @param[in,out] ChildHandleBuffer   The buffer which contains the child handles.
+                                       For an add operation, it is an output
+                                       parameter and contains all newly created
                                        child handles.  For a remove operation, it
                                        contains child handles to be destroyed when
                                        NumberOfChildren contains a non-zero value.
                                        It can be NULL when NumberOfChildren is 0.
                                        It's the caller's responsibility to allocate
                                        and free memory for this buffer.
-  
-  @retval EFI_SUCCESS             The handles for the specified device have been 
-                                  created or destroyed as requested, and for an 
-                                  add operation, the new handles are returned in 
+
+  @retval EFI_SUCCESS             The handles for the specified device have been
+                                  created or destroyed as requested, and for an
+                                  add operation, the new handles are returned in
                                   ChildHandleBuffer.
   @retval EFI_INVALID_PARAMETER   Operation is not a legal value.
   @retval EFI_INVALID_PARAMETER   Controller is NULL or not a valid handle.
   @retval EFI_INVALID_PARAMETER   NumberOfChildren is NULL.
-  @retval EFI_INVALID_PARAMETER   ChildHandleBuffer is NULL while Operation is 
-                                  remove and NumberOfChildren contains a non-zero 
+  @retval EFI_INVALID_PARAMETER   ChildHandleBuffer is NULL while Operation is
+                                  remove and NumberOfChildren contains a non-zero
                                   value.
   @retval EFI_INVALID_PARAMETER   ChildHandleBuffer is NULL while Operation is add.
-  @retval EFI_OUT_OF_RESOURCES    There are no enough resources to start the 
+  @retval EFI_OUT_OF_RESOURCES    There are no enough resources to start the
                                   devices.
 **/
 typedef
@@ -151,15 +145,15 @@ EFI_STATUS
   );
 
 ///
-/// Provides services to notify PCI bus driver that some events have happened in 
-/// a hot-plug controller (for example, PC Card socket, or PHPC), and ask PCI bus 
+/// Provides services to notify PCI bus driver that some events have happened in
+/// a hot-plug controller (for example, PC Card socket, or PHPC), and ask PCI bus
 /// driver to create or destroy handles for the PCI-like devices.
 ///
 struct _EFI_PCI_HOTPLUG_REQUEST_PROTOCOL {
   ///
-  /// Notify the PCI bus driver that some events have happened in a hot-plug 
-  /// controller (for example, PC Card socket, or PHPC), and ask PCI bus driver 
-  /// to create or destroy handles for the PCI-like devices. See Section 0 for 
+  /// Notify the PCI bus driver that some events have happened in a hot-plug
+  /// controller (for example, PC Card socket, or PHPC), and ask PCI bus driver
+  /// to create or destroy handles for the PCI-like devices. See Section 0 for
   /// a detailed description.
   ///
   EFI_PCI_HOTPLUG_REQUEST_NOTIFY  Notify;
diff --git a/MdePkg/Include/Protocol/PciIo.h b/MdePkg/Include/Protocol/PciIo.h
index 5bbc54350149..420b8cba6f4e 100644
--- a/MdePkg/Include/Protocol/PciIo.h
+++ b/MdePkg/Include/Protocol/PciIo.h
@@ -1,15 +1,9 @@
 /** @file
-  EFI PCI I/O Protocol provides the basic Memory, I/O, PCI configuration, 
+  EFI PCI I/O Protocol provides the basic Memory, I/O, PCI configuration,
   and DMA interfaces that a driver uses to access its PCI controller.
 
-  Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -126,27 +120,27 @@ typedef enum {
   EfiPciIoAttributeOperationMaximum
 } EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION;
 
-/**                                                                 
+/**
   Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is
-  satisfied or after a defined duration.                                                           
-          
+  satisfied or after a defined duration.
+
   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
   @param  Width                 Signifies the width of the memory or I/O operations.
   @param  BarIndex              The BAR index of the standard PCI Configuration header to use as the
-                                base address for the memory operation to perform.                   
+                                base address for the memory operation to perform.
   @param  Offset                The offset within the selected BAR to start the memory operation.
   @param  Mask                  Mask used for the polling criteria.
   @param  Value                 The comparison value used for the polling exit criteria.
   @param  Delay                 The number of 100 ns units to poll.
   @param  Result                Pointer to the last value read from the memory location.
-                                
+
   @retval EFI_SUCCESS           The last data returned from the access matched the poll exit criteria.
   @retval EFI_UNSUPPORTED       BarIndex not valid for this PCI controller.
   @retval EFI_UNSUPPORTED       Offset is not valid for the BarIndex of this PCI controller.
   @retval EFI_TIMEOUT           Delay expired before a match occurred.
   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
-                                   
+
 **/
 typedef
 EFI_STATUS
@@ -161,25 +155,25 @@ EFI_STATUS
   OUT UINT64                       *Result
   );
 
-/**                                                                 
+/**
   Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.
-          
+
   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
   @param  Width                 Signifies the width of the memory or I/O operations.
   @param  BarIndex              The BAR index of the standard PCI Configuration header to use as the
-                                base address for the memory or I/O operation to perform.                    
-  @param  Offset                The offset within the selected BAR to start the memory or I/O operation.                                
+                                base address for the memory or I/O operation to perform.
+  @param  Offset                The offset within the selected BAR to start the memory or I/O operation.
   @param  Count                 The number of memory or I/O operations to perform.
   @param  Buffer                For read operations, the destination buffer to store the results. For write
-                                operations, the source buffer to write data from.                          
-  
+                                operations, the source buffer to write data from.
+
   @retval EFI_SUCCESS           The data was read from or written to the PCI controller.
   @retval EFI_UNSUPPORTED       BarIndex not valid for this PCI controller.
   @retval EFI_UNSUPPORTED       The address range specified by Offset, Width, and Count is not
-                                valid for the PCI BAR specified by BarIndex.                  
+                                valid for the PCI BAR specified by BarIndex.
   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
-                                   
+
 **/
 typedef
 EFI_STATUS
@@ -203,23 +197,23 @@ typedef struct {
   EFI_PCI_IO_PROTOCOL_IO_MEM  Write;
 } EFI_PCI_IO_PROTOCOL_ACCESS;
 
-/**                                                                 
+/**
   Enable a PCI driver to access PCI controller registers in PCI configuration space.
-            
-  @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.  
+
+  @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
   @param  Width                 Signifies the width of the memory operations.
   @param  Offset                The offset within the PCI configuration space for the PCI controller.
   @param  Count                 The number of PCI configuration operations to perform.
   @param  Buffer                For read operations, the destination buffer to store the results. For write
                                 operations, the source buffer to write data from.
-  
-                                  
+
+
   @retval EFI_SUCCESS           The data was read from or written to the PCI controller.
   @retval EFI_UNSUPPORTED       The address range specified by Offset, Width, and Count is not
                                 valid for the PCI configuration header of the PCI controller.
-  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.                                 
-  @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.                                
-                                     
+  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
+  @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
+
 **/
 typedef
 EFI_STATUS
@@ -242,33 +236,33 @@ typedef struct {
   EFI_PCI_IO_PROTOCOL_CONFIG  Write;
 } EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS;
 
-/**                                                                 
+/**
   Enables a PCI driver to copy one region of PCI memory space to another region of PCI
   memory space.
-            
+
   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
   @param  Width                 Signifies the width of the memory operations.
   @param  DestBarIndex          The BAR index in the standard PCI Configuration header to use as the
-                                base address for the memory operation to perform.                   
+                                base address for the memory operation to perform.
   @param  DestOffset            The destination offset within the BAR specified by DestBarIndex to
-                                start the memory writes for the copy operation.                   
+                                start the memory writes for the copy operation.
   @param  SrcBarIndex           The BAR index in the standard PCI Configuration header to use as the
-                                base address for the memory operation to perform.                   
+                                base address for the memory operation to perform.
   @param  SrcOffset             The source offset within the BAR specified by SrcBarIndex to start
-                                the memory reads for the copy operation.                          
+                                the memory reads for the copy operation.
   @param  Count                 The number of memory operations to perform. Bytes moved is Width
-                                size * Count, starting at DestOffset and SrcOffset.             
-                                
+                                size * Count, starting at DestOffset and SrcOffset.
+
   @retval EFI_SUCCESS           The data was copied from one memory region to another memory region.
   @retval EFI_UNSUPPORTED       DestBarIndex not valid for this PCI controller.
   @retval EFI_UNSUPPORTED       SrcBarIndex not valid for this PCI controller.
   @retval EFI_UNSUPPORTED       The address range specified by DestOffset, Width, and Count
-                                is not valid for the PCI BAR specified by DestBarIndex.    
+                                is not valid for the PCI BAR specified by DestBarIndex.
   @retval EFI_UNSUPPORTED       The address range specified by SrcOffset, Width, and Count is
-                                not valid for the PCI BAR specified by SrcBarIndex.          
+                                not valid for the PCI BAR specified by SrcBarIndex.
   @retval EFI_INVALID_PARAMETER Width is invalid.
   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
-                                   
+
 **/
 typedef
 EFI_STATUS
@@ -282,24 +276,24 @@ EFI_STATUS
   IN     UINTN                        Count
   );
 
-/**                                                                 
+/**
   Provides the PCI controller-specific addresses needed to access system memory.
-            
+
   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
   @param  Operation             Indicates if the bus master is going to read or write to system memory.
   @param  HostAddress           The system memory address to map to the PCI controller.
   @param  NumberOfBytes         On input the number of bytes to map. On output the number of bytes
-                                that were mapped.                                                 
+                                that were mapped.
   @param  DeviceAddress         The resulting map address for the bus master PCI controller to use to
-                                access the hosts HostAddress.                                        
+                                access the hosts HostAddress.
   @param  Mapping               A resulting value to pass to Unmap().
-                                  
+
   @retval EFI_SUCCESS           The range was mapped for the returned NumberOfBytes.
-  @retval EFI_UNSUPPORTED       The HostAddress cannot be mapped as a common buffer.                                
+  @retval EFI_UNSUPPORTED       The HostAddress cannot be mapped as a common buffer.
   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
   @retval EFI_DEVICE_ERROR      The system hardware could not map the requested address.
-                                   
+
 **/
 typedef
 EFI_STATUS
@@ -312,15 +306,15 @@ EFI_STATUS
   OUT    VOID                           **Mapping
   );
 
-/**                                                                 
+/**
   Completes the Map() operation and releases any corresponding resources.
-            
-  @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.                                      
+
+  @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
   @param  Mapping               The mapping value returned from Map().
-                                  
+
   @retval EFI_SUCCESS           The range was unmapped.
   @retval EFI_DEVICE_ERROR      The data was not committed to the target system memory.
-                                   
+
 **/
 typedef
 EFI_STATUS
@@ -329,25 +323,25 @@ EFI_STATUS
   IN  VOID                         *Mapping
   );
 
-/**                                                                 
+/**
   Allocates pages that are suitable for an EfiPciIoOperationBusMasterCommonBuffer
-  mapping.                                                                       
-            
+  or EfiPciOperationBusMasterCommonBuffer64 mapping.
+
   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
   @param  Type                  This parameter is not used and must be ignored.
   @param  MemoryType            The type of memory to allocate, EfiBootServicesData or
-                                EfiRuntimeServicesData.                               
-  @param  Pages                 The number of pages to allocate.                                
+                                EfiRuntimeServicesData.
+  @param  Pages                 The number of pages to allocate.
   @param  HostAddress           A pointer to store the base system memory address of the
-                                allocated range.                                        
+                                allocated range.
   @param  Attributes            The requested bit mask of attributes for the allocated range.
-                                  
+
   @retval EFI_SUCCESS           The requested memory pages were allocated.
   @retval EFI_UNSUPPORTED       Attributes is unsupported. The only legal attribute bits are
-                                MEMORY_WRITE_COMBINE and MEMORY_CACHED.                     
+                                MEMORY_WRITE_COMBINE, MEMORY_CACHED and DUAL_ADDRESS_CYCLE.
   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
-  @retval EFI_OUT_OF_RESOURCES  The memory pages could not be allocated.  
-                                   
+  @retval EFI_OUT_OF_RESOURCES  The memory pages could not be allocated.
+
 **/
 typedef
 EFI_STATUS
@@ -360,17 +354,17 @@ EFI_STATUS
   IN  UINT64                       Attributes
   );
 
-/**                                                                 
+/**
   Frees memory that was allocated with AllocateBuffer().
-            
-  @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.  
-  @param  Pages                 The number of pages to free.                                
-  @param  HostAddress           The base system memory address of the allocated range.                                    
-                                  
+
+  @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
+  @param  Pages                 The number of pages to free.
+  @param  HostAddress           The base system memory address of the allocated range.
+
   @retval EFI_SUCCESS           The requested memory pages were freed.
   @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
                                 was not allocated with AllocateBuffer().
-                                     
+
 **/
 typedef
 EFI_STATUS
@@ -380,16 +374,16 @@ EFI_STATUS
   IN  VOID                         *HostAddress
   );
 
-/**                                                                 
+/**
   Flushes all PCI posted write transactions from a PCI host bridge to system memory.
-            
-  @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.  
-                                  
+
+  @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
+
   @retval EFI_SUCCESS           The PCI posted write transactions were flushed from the PCI host
-                                bridge to system memory.                                        
+                                bridge to system memory.
   @retval EFI_DEVICE_ERROR      The PCI posted write transactions were not flushed from the PCI
-                                host bridge due to a hardware error.                           
-                                     
+                                host bridge due to a hardware error.
+
 **/
 typedef
 EFI_STATUS
@@ -397,18 +391,18 @@ EFI_STATUS
   IN EFI_PCI_IO_PROTOCOL  *This
   );
 
-/**                                                                 
+/**
   Retrieves this PCI controller's current PCI bus number, device number, and function number.
-            
-  @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.  
+
+  @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
   @param  SegmentNumber         The PCI controller's current PCI segment number.
   @param  BusNumber             The PCI controller's current PCI bus number.
   @param  DeviceNumber          The PCI controller's current PCI device number.
   @param  FunctionNumber        The PCI controller's current PCI function number.
-                                  
-  @retval EFI_SUCCESS           The PCI controller location was returned.                                                       
-  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.                              
-                                     
+
+  @retval EFI_SUCCESS           The PCI controller location was returned.
+  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+
 **/
 typedef
 EFI_STATUS
@@ -420,24 +414,24 @@ EFI_STATUS
   OUT UINTN                       *FunctionNumber
   );
 
-/**                                                                 
+/**
   Performs an operation on the attributes that this PCI controller supports. The operations include
-  getting the set of supported attributes, retrieving the current attributes, setting the current  
-  attributes, enabling attributes, and disabling attributes.                                       
-            
-  @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.  
+  getting the set of supported attributes, retrieving the current attributes, setting the current
+  attributes, enabling attributes, and disabling attributes.
+
+  @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
   @param  Operation             The operation to perform on the attributes for this PCI controller.
   @param  Attributes            The mask of attributes that are used for Set, Enable, and Disable
-                                operations.                                                      
+                                operations.
   @param  Result                A pointer to the result mask of attributes that are returned for the Get
-                                and Supported operations.                                               
-                                  
+                                and Supported operations.
+
   @retval EFI_SUCCESS           The operation on the PCI controller's attributes was completed.
-  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.                              
-  @retval EFI_UNSUPPORTED       one or more of the bits set in                               
+  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+  @retval EFI_UNSUPPORTED       one or more of the bits set in
                                 Attributes are not supported by this PCI controller or one of
                                 its parent bridges when Operation is Set, Enable or Disable.
-                                       
+
 **/
 typedef
 EFI_STATUS
@@ -448,27 +442,26 @@ EFI_STATUS
   OUT UINT64                                   *Result OPTIONAL
   );
 
-/**                                                                 
+/**
   Gets the attributes that this PCI controller supports setting on a BAR using
   SetBarAttributes(), and retrieves the list of resource descriptors for a BAR.
-            
-  @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.  
+
+  @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
   @param  BarIndex              The BAR index of the standard PCI Configuration header to use as the
                                 base address for resource range. The legal range for this field is 0..5.
   @param  Supports              A pointer to the mask of attributes that this PCI controller supports
-                                setting for this BAR with SetBarAttributes().                        
-  @param  Resources             A pointer to the ACPI 2.0 resource descriptors that describe the current
-                                configuration of this BAR of the PCI controller.                        
-                                  
-  @retval EFI_SUCCESS           If Supports is not NULL, then the attributes that the PCI       
-                                controller supports are returned in Supports. If Resources      
-                                is not NULL, then the ACPI 2.0 resource descriptors that the PCI
-                                controller is currently using are returned in Resources.          
+                                setting for this BAR with SetBarAttributes().
+  @param  Resources             A pointer to the resource descriptors that describe the current
+                                configuration of this BAR of the PCI controller.
+
+  @retval EFI_SUCCESS           If Supports is not NULL, then the attributes that the PCI
+                                controller supports are returned in Supports. If Resources
+                                is not NULL, then the resource descriptors that the PCI
+                                controller is currently using are returned in Resources.
   @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.
   @retval EFI_UNSUPPORTED       BarIndex not valid for this PCI controller.
   @retval EFI_OUT_OF_RESOURCES  There are not enough resources available to allocate
-                                Resources.                                                 
-                                
+                                Resources.
 **/
 typedef
 EFI_STATUS
@@ -479,29 +472,29 @@ EFI_STATUS
   OUT VOID                           **Resources OPTIONAL
   );
 
-/**                                                                 
+/**
   Sets the attributes for a range of a BAR on a PCI controller.
-            
-  @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.  
+
+  @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
   @param  Attributes            The mask of attributes to set for the resource range specified by
-                                BarIndex, Offset, and Length.                                    
+                                BarIndex, Offset, and Length.
   @param  BarIndex              The BAR index of the standard PCI Configuration header to use as the
                                 base address for resource range. The legal range for this field is 0..5.
   @param  Offset                A pointer to the BAR relative base address of the resource range to be
-                                modified by the attributes specified by Attributes.                   
+                                modified by the attributes specified by Attributes.
   @param  Length                A pointer to the length of the resource range to be modified by the
-                                attributes specified by Attributes.                                
-                                  
-  @retval EFI_SUCCESS           The set of attributes specified by Attributes for the resource      
-                                range specified by BarIndex, Offset, and Length were                
+                                attributes specified by Attributes.
+
+  @retval EFI_SUCCESS           The set of attributes specified by Attributes for the resource
+                                range specified by BarIndex, Offset, and Length were
                                 set on the PCI controller, and the actual resource range is returned
-                                in Offset and Length.                                               
+                                in Offset and Length.
   @retval EFI_INVALID_PARAMETER Offset or Length is NULL.
   @retval EFI_UNSUPPORTED       BarIndex not valid for this PCI controller.
   @retval EFI_OUT_OF_RESOURCES  There are not enough resources to set the attributes on the
-                                resource range specified by BarIndex, Offset, and          
-                                Length.                                                    
-                                
+                                resource range specified by BarIndex, Offset, and
+                                Length.
+
 **/
 typedef
 EFI_STATUS
@@ -514,11 +507,11 @@ EFI_STATUS
   );
 
 ///
-/// The EFI_PCI_IO_PROTOCOL provides the basic Memory, I/O, PCI configuration, 
-/// and DMA interfaces used to abstract accesses to PCI controllers. 
-/// There is one EFI_PCI_IO_PROTOCOL instance for each PCI controller on a PCI bus. 
-/// A device driver that wishes to manage a PCI controller in a system will have to 
-/// retrieve the EFI_PCI_IO_PROTOCOL instance that is associated with the PCI controller. 
+/// The EFI_PCI_IO_PROTOCOL provides the basic Memory, I/O, PCI configuration,
+/// and DMA interfaces used to abstract accesses to PCI controllers.
+/// There is one EFI_PCI_IO_PROTOCOL instance for each PCI controller on a PCI bus.
+/// A device driver that wishes to manage a PCI controller in a system will have to
+/// retrieve the EFI_PCI_IO_PROTOCOL instance that is associated with the PCI controller.
 ///
 struct _EFI_PCI_IO_PROTOCOL {
   EFI_PCI_IO_PROTOCOL_POLL_IO_MEM         PollMem;
@@ -536,20 +529,20 @@ struct _EFI_PCI_IO_PROTOCOL {
   EFI_PCI_IO_PROTOCOL_ATTRIBUTES          Attributes;
   EFI_PCI_IO_PROTOCOL_GET_BAR_ATTRIBUTES  GetBarAttributes;
   EFI_PCI_IO_PROTOCOL_SET_BAR_ATTRIBUTES  SetBarAttributes;
-  
+
   ///
   /// The size, in bytes, of the ROM image.
   ///
   UINT64                                  RomSize;
 
   ///
-  /// A pointer to the in memory copy of the ROM image. The PCI Bus Driver is responsible 
-  /// for allocating memory for the ROM image, and copying the contents of the ROM to memory. 
-  /// The contents of this buffer are either from the PCI option ROM that can be accessed 
-  /// through the ROM BAR of the PCI controller, or it is from a platform-specific location. 
-  /// The Attributes() function can be used to determine from which of these two sources 
+  /// A pointer to the in memory copy of the ROM image. The PCI Bus Driver is responsible
+  /// for allocating memory for the ROM image, and copying the contents of the ROM to memory.
+  /// The contents of this buffer are either from the PCI option ROM that can be accessed
+  /// through the ROM BAR of the PCI controller, or it is from a platform-specific location.
+  /// The Attributes() function can be used to determine from which of these two sources
   /// the RomImage buffer was initialized.
-  /// 
+  ///
   VOID                                    *RomImage;
 };
 
diff --git a/MdePkg/Include/Protocol/PciOverride.h b/MdePkg/Include/Protocol/PciOverride.h
index c1edcc52fa5f..e5b797177f9c 100644
--- a/MdePkg/Include/Protocol/PciOverride.h
+++ b/MdePkg/Include/Protocol/PciOverride.h
@@ -5,13 +5,7 @@
   This protocol is optional.
 
   Copyright (c) 2009, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This Protocol is defined in UEFI Platform Initialization Specification 1.2
diff --git a/MdePkg/Include/Protocol/PciPlatform.h b/MdePkg/Include/Protocol/PciPlatform.h
index 056f92b1ef53..1f514e2d77de 100644
--- a/MdePkg/Include/Protocol/PciPlatform.h
+++ b/MdePkg/Include/Protocol/PciPlatform.h
@@ -1,20 +1,14 @@
 /** @file
-  This file declares PlatfromOpRom protocols that provide the interface between 
-  the PCI bus driver/PCI Host Bridge Resource Allocation driver and a platform-specific 
-  driver to describe the unique features of a platform. 
+  This file declares PlatfromOpRom protocols that provide the interface between
+  the PCI bus driver/PCI Host Bridge Resource Allocation driver and a platform-specific
+  driver to describe the unique features of a platform.
   This protocol is optional.
-  
-Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
-  This Protocol is defined in UEFI Platform Initialization Specification 1.2 
+  This Protocol is defined in UEFI Platform Initialization Specification 1.2
   Volume 5: Standards
 
 **/
@@ -320,16 +314,16 @@ EFI_STATUS
 ///
 struct _EFI_PCI_PLATFORM_PROTOCOL {
   ///
-  /// The notification from the PCI bus enumerator to the platform that it is about to 
+  /// The notification from the PCI bus enumerator to the platform that it is about to
   /// enter a certain phase during the enumeration process.
   ///
   EFI_PCI_PLATFORM_PHASE_NOTIFY          PlatformNotify;
   ///
-  /// The notification from the PCI bus enumerator to the platform for each PCI 
+  /// The notification from the PCI bus enumerator to the platform for each PCI
   /// controller at several predefined points during PCI controller initialization.
-  /// 
+  ///
   EFI_PCI_PLATFORM_PREPROCESS_CONTROLLER PlatformPrepController;
-  /// 
+  ///
   /// Retrieves the platform policy regarding enumeration.
   ///
   EFI_PCI_PLATFORM_GET_PLATFORM_POLICY   GetPlatformPolicy;
diff --git a/MdePkg/Include/Protocol/PciRootBridgeIo.h b/MdePkg/Include/Protocol/PciRootBridgeIo.h
index 382dae7b97bd..dffb8a9dee31 100644
--- a/MdePkg/Include/Protocol/PciRootBridgeIo.h
+++ b/MdePkg/Include/Protocol/PciRootBridgeIo.h
@@ -1,18 +1,12 @@
 /** @file
   PCI Root Bridge I/O protocol as defined in the UEFI 2.0 specification.
 
-  PCI Root Bridge I/O protocol is used by PCI Bus Driver to perform PCI Memory, PCI I/O, 
-  and PCI Configuration cycles on a PCI Root Bridge. It also provides services to perform 
+  PCI Root Bridge I/O protocol is used by PCI Bus Driver to perform PCI Memory, PCI I/O,
+  and PCI Configuration cycles on a PCI Root Bridge. It also provides services to perform
   defferent types of bus mastering DMA.
 
-  Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -122,23 +116,23 @@ typedef struct {
   UINT32  ExtendedRegister;
 } EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS;
 
-/**                                                                 
+/**
   Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is
   satisfied or after a defined duration.
-          
+
   @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
   @param  Width                 Signifies the width of the memory or I/O operations.
-  @param  Address               The base address of the memory or I/O operations.  
+  @param  Address               The base address of the memory or I/O operations.
   @param  Mask                  Mask used for the polling criteria.
   @param  Value                 The comparison value used for the polling exit criteria.
   @param  Delay                 The number of 100 ns units to poll.
   @param  Result                Pointer to the last value read from the memory location.
-                                
+
   @retval EFI_SUCCESS           The last data returned from the access matched the poll exit criteria.
   @retval EFI_TIMEOUT           Delay expired before a match occurred.
   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
-                                   
+
 **/
 typedef
 EFI_STATUS
@@ -152,20 +146,20 @@ EFI_STATUS
   OUT UINT64                                   *Result
   );
 
-/**                                                                 
+/**
   Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
-          
+
   @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
   @param  Width                 Signifies the width of the memory operations.
-  @param  Address               The base address of the memory operations.                                  
+  @param  Address               The base address of the memory operations.
   @param  Count                 The number of memory operations to perform.
   @param  Buffer                For read operations, the destination buffer to store the results. For write
-                                operations, the source buffer to write data from.                          
-  
-  @retval EFI_SUCCESS           The data was read from or written to the PCI root bridge.  
+                                operations, the source buffer to write data from.
+
+  @retval EFI_SUCCESS           The data was read from or written to the PCI root bridge.
   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
-                                   
+
 **/
 typedef
 EFI_STATUS
@@ -188,20 +182,20 @@ typedef struct {
   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_IO_MEM  Write;
 } EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_ACCESS;
 
-/**                                                                 
+/**
   Enables a PCI driver to copy one region of PCI root bridge memory space to another region of PCI
-  root bridge memory space.                                                                       
-            
+  root bridge memory space.
+
   @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.
   @param  Width                 Signifies the width of the memory operations.
-  @param  DestAddress           The destination address of the memory operation.                                
-  @param  SrcAddress            The source address of the memory operation.                                
-  @param  Count                 The number of memory operations to perform.    
-                                
-  @retval EFI_SUCCESS           The data was copied from one memory region to another memory region.  
+  @param  DestAddress           The destination address of the memory operation.
+  @param  SrcAddress            The source address of the memory operation.
+  @param  Count                 The number of memory operations to perform.
+
+  @retval EFI_SUCCESS           The data was copied from one memory region to another memory region.
   @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
-                                   
+
 **/
 typedef
 EFI_STATUS
@@ -213,25 +207,25 @@ EFI_STATUS
   IN     UINTN                                    Count
   );
 
-/**                                                                 
+/**
   Provides the PCI controller-specific addresses required to access system memory from a
-  DMA bus master.                                                                        
-            
+  DMA bus master.
+
   @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
   @param  Operation             Indicates if the bus master is going to read or write to system memory.
   @param  HostAddress           The system memory address to map to the PCI controller.
   @param  NumberOfBytes         On input the number of bytes to map. On output the number of bytes
-                                that were mapped.                                                 
+                                that were mapped.
   @param  DeviceAddress         The resulting map address for the bus master PCI controller to use to
-                                access the hosts HostAddress.                                        
+                                access the hosts HostAddress.
   @param  Mapping               A resulting value to pass to Unmap().
-                                  
+
   @retval EFI_SUCCESS           The range was mapped for the returned NumberOfBytes.
-  @retval EFI_UNSUPPORTED       The HostAddress cannot be mapped as a common buffer.                                
+  @retval EFI_UNSUPPORTED       The HostAddress cannot be mapped as a common buffer.
   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
   @retval EFI_DEVICE_ERROR      The system hardware could not map the requested address.
-                                   
+
 **/
 typedef
 EFI_STATUS
@@ -244,16 +238,16 @@ EFI_STATUS
   OUT    VOID                                       **Mapping
   );
 
-/**                                                                 
+/**
   Completes the Map() operation and releases any corresponding resources.
-            
+
   @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
   @param  Mapping               The mapping value returned from Map().
-                                  
+
   @retval EFI_SUCCESS           The range was unmapped.
   @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().
   @retval EFI_DEVICE_ERROR      The data was not committed to the target system memory.
-                                   
+
 **/
 typedef
 EFI_STATUS
@@ -262,25 +256,25 @@ EFI_STATUS
   IN  VOID                                     *Mapping
   );
 
-/**                                                                 
+/**
   Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer or
-  EfiPciOperationBusMasterCommonBuffer64 mapping.                                 
-            
+  EfiPciOperationBusMasterCommonBuffer64 mapping.
+
   @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
   @param  Type                  This parameter is not used and must be ignored.
   @param  MemoryType            The type of memory to allocate, EfiBootServicesData or
-                                EfiRuntimeServicesData.                               
-  @param  Pages                 The number of pages to allocate.                                
+                                EfiRuntimeServicesData.
+  @param  Pages                 The number of pages to allocate.
   @param  HostAddress           A pointer to store the base system memory address of the
-                                allocated range.                                        
+                                allocated range.
   @param  Attributes            The requested bit mask of attributes for the allocated range.
-                                  
+
   @retval EFI_SUCCESS           The requested memory pages were allocated.
   @retval EFI_UNSUPPORTED       Attributes is unsupported. The only legal attribute bits are
-                                MEMORY_WRITE_COMBINE and MEMORY_CACHED.                     
+                                MEMORY_WRITE_COMBINE and MEMORY_CACHED.
   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
-  @retval EFI_OUT_OF_RESOURCES  The memory pages could not be allocated.  
-                                   
+  @retval EFI_OUT_OF_RESOURCES  The memory pages could not be allocated.
+
 **/
 typedef
 EFI_STATUS
@@ -293,17 +287,17 @@ EFI_STATUS
   IN     UINT64                                   Attributes
   );
 
-/**                                                                 
+/**
   Frees memory that was allocated with AllocateBuffer().
-            
+
   @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-  @param  Pages                 The number of pages to free.                                
-  @param  HostAddress           The base system memory address of the allocated range.                                    
-                                  
+  @param  Pages                 The number of pages to free.
+  @param  HostAddress           The base system memory address of the allocated range.
+
   @retval EFI_SUCCESS           The requested memory pages were freed.
   @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
                                 was not allocated with AllocateBuffer().
-                                     
+
 **/
 typedef
 EFI_STATUS
@@ -313,16 +307,16 @@ EFI_STATUS
   IN  VOID                                     *HostAddress
   );
 
-/**                                                                 
+/**
   Flushes all PCI posted write transactions from a PCI host bridge to system memory.
-            
+
   @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-                                  
+
   @retval EFI_SUCCESS           The PCI posted write transactions were flushed from the PCI host
-                                bridge to system memory.                                        
+                                bridge to system memory.
   @retval EFI_DEVICE_ERROR      The PCI posted write transactions were not flushed from the PCI
-                                host bridge due to a hardware error.                           
-                                     
+                                host bridge due to a hardware error.
+
 **/
 typedef
 EFI_STATUS
@@ -330,23 +324,23 @@ EFI_STATUS
   IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This
   );
 
-/**                                                                 
+/**
   Gets the attributes that a PCI root bridge supports setting with SetAttributes(), and the
-  attributes that a PCI root bridge is currently using.                                    
-            
+  attributes that a PCI root bridge is currently using.
+
   @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
   @param  Supports              A pointer to the mask of attributes that this PCI root bridge supports
-                                setting with SetAttributes().                                         
+                                setting with SetAttributes().
   @param  Attributes            A pointer to the mask of attributes that this PCI root bridge is currently
-                                using.                                                                      
-                                
-  @retval EFI_SUCCESS           If Supports is not NULL, then the attributes that the PCI root     
-                                bridge supports is returned in Supports. If Attributes is          
+                                using.
+
+  @retval EFI_SUCCESS           If Supports is not NULL, then the attributes that the PCI root
+                                bridge supports is returned in Supports. If Attributes is
                                 not NULL, then the attributes that the PCI root bridge is currently
-                                using is returned in Attributes.                                   
+                                using is returned in Attributes.
   @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.
-                                
-                                     
+
+
 **/
 typedef
 EFI_STATUS
@@ -356,26 +350,26 @@ EFI_STATUS
   OUT UINT64                                   *Attributes
   );
 
-/**                                                                 
+/**
   Sets attributes for a resource range on a PCI root bridge.
-            
+
   @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
   @param  Attributes            The mask of attributes to set.
   @param  ResourceBase          A pointer to the base address of the resource range to be modified by the
                                 attributes specified by Attributes.
   @param  ResourceLength        A pointer to the length of the resource range to be modified by the
-                                attributes specified by Attributes.                                                                                                              
-                                
-  @retval EFI_SUCCESS           The set of attributes specified by Attributes for the resource   
-                                range specified by ResourceBase and ResourceLength               
+                                attributes specified by Attributes.
+
+  @retval EFI_SUCCESS           The set of attributes specified by Attributes for the resource
+                                range specified by ResourceBase and ResourceLength
                                 were set on the PCI root bridge, and the actual resource range is
-                                returned in ResuourceBase and ResourceLength.                    
+                                returned in ResuourceBase and ResourceLength.
   @retval EFI_UNSUPPORTED       A bit is set in Attributes that is not supported by the PCI Root
-                                Bridge.                                                         
-  @retval EFI_OUT_OF_RESOURCES  There are not enough resources to set the attributes on the                              
-                                resource range specified by BaseAddress and Length.        
-  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.                               
-                                     
+                                Bridge.
+  @retval EFI_OUT_OF_RESOURCES  There are not enough resources to set the attributes on the
+                                resource range specified by BaseAddress and Length.
+  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+
 **/
 typedef
 EFI_STATUS
@@ -386,19 +380,19 @@ EFI_STATUS
   IN OUT UINT64                                   *ResourceLength
   );
 
-/**                                                                 
-  Retrieves the current resource settings of this PCI root bridge in the form of a set of ACPI 2.0
-  resource descriptors.                                                                           
-            
+/**
+  Retrieves the current resource settings of this PCI root bridge in the form of a set of ACPI
+  resource descriptors.
+
   @param  This                  A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
-  @param  Resources             A pointer to the ACPI 2.0 resource descriptors that describe the current
-                                configuration of this PCI root bridge.                                  
-                                
+  @param  Resources             A pointer to the resource descriptors that describe the current
+                                configuration of this PCI root bridge.
+
   @retval EFI_SUCCESS           The current configuration of this PCI root bridge was returned in
-                                Resources.                                                                                                                       
+                                Resources.
   @retval EFI_UNSUPPORTED       The current configuration of this PCI root bridge could not be
-                                retrieved.                                                                          
-                                       
+                                retrieved.
+
 **/
 typedef
 EFI_STATUS
@@ -408,8 +402,8 @@ EFI_STATUS
   );
 
 ///
-/// Provides the basic Memory, I/O, PCI configuration, and DMA interfaces that are 
-/// used to abstract accesses to PCI controllers behind a PCI Root Bridge Controller. 
+/// Provides the basic Memory, I/O, PCI configuration, and DMA interfaces that are
+/// used to abstract accesses to PCI controllers behind a PCI Root Bridge Controller.
 ///
 struct _EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL {
   ///
@@ -430,7 +424,7 @@ struct _EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL {
   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GET_ATTRIBUTES  GetAttributes;
   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_SET_ATTRIBUTES  SetAttributes;
   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_CONFIGURATION   Configuration;
-  
+
   ///
   /// The segment number that this PCI root bridge resides.
   ///
diff --git a/MdePkg/Include/Protocol/PiPcd.h b/MdePkg/Include/Protocol/PiPcd.h
index 84d2aa444bd5..b409ba614f79 100644
--- a/MdePkg/Include/Protocol/PiPcd.h
+++ b/MdePkg/Include/Protocol/PiPcd.h
@@ -13,13 +13,7 @@
   firmware component to monitor specific settings and be alerted when a setting is changed.
 
   Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   PI Version 1.2 Vol 3.
diff --git a/MdePkg/Include/Protocol/PiPcdInfo.h b/MdePkg/Include/Protocol/PiPcdInfo.h
index 1b39f0de520a..b8c313312231 100644
--- a/MdePkg/Include/Protocol/PiPcdInfo.h
+++ b/MdePkg/Include/Protocol/PiPcdInfo.h
@@ -4,13 +4,7 @@
   The protocol that provides additional information about items that reside in the PCD database.
 
   Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   PI Version 1.2.1 Vol 3.
diff --git a/MdePkg/Include/Protocol/Pkcs7Verify.h b/MdePkg/Include/Protocol/Pkcs7Verify.h
index 267cbc81fa13..5cf1ffda1332 100644
--- a/MdePkg/Include/Protocol/Pkcs7Verify.h
+++ b/MdePkg/Include/Protocol/Pkcs7Verify.h
@@ -6,14 +6,8 @@
   PKCS#7 is a general-purpose cryptographic standard (defined by RFC2315,
   available at http://tools.ietf.org/html/rfc2315).
 
-Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under
-the terms and conditions of the BSD License that accompanies this distribution.
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -140,6 +134,14 @@ EFI_STATUS
   verifies the signature of the content is valid and signing certificate was not revoked
   and is contained within a list of trusted signers.
 
+  Note: because this function uses hashes and the specification contains a variety of
+        hash choices, you should be aware that the check against the RevokedDb list
+        will improperly succeed if the signature is revoked using a different hash
+        algorithm.  For this reason, you should either cycle through all UEFI supported
+        hashes to see if one is forbidden, or rely on a single hash choice only if the
+        UEFI signature authority only signs and revokes with a single hash (at time
+        of writing, this hash choice is SHA256).
+
   @param[in]     This                 Pointer to EFI_PKCS7_VERIFY_PROTOCOL instance.
   @param[in]     Signature            Points to buffer containing ASN.1 DER-encoded PKCS
                                       detached signature.
diff --git a/MdePkg/Include/Protocol/PlatformDriverOverride.h b/MdePkg/Include/Protocol/PlatformDriverOverride.h
index c84d12d1f02f..e60ca5a82a73 100644
--- a/MdePkg/Include/Protocol/PlatformDriverOverride.h
+++ b/MdePkg/Include/Protocol/PlatformDriverOverride.h
@@ -1,14 +1,8 @@
 /** @file
   Platform Driver Override protocol as defined in the UEFI 2.1 specification.
 
-  Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -29,24 +23,24 @@ typedef struct _EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL  EFI_PLATFORM_DRIVER_OVERR
 // Prototypes for the Platform Driver Override Protocol
 //
 
-/**                                                                 
+/**
   Retrieves the image handle of the platform override driver for a controller in the system.
-    
+
   @param  This                  A pointer to the EFI_PLATFORM_DRIVER_OVERRIDE_
-                                PROTOCOL instance.                            
+                                PROTOCOL instance.
   @param  ControllerHandle      The device handle of the controller to check if a driver override
-                                exists.                                                          
+                                exists.
   @param  DriverImageHandle     On input, a pointer to the previous driver image handle returned
-                                by GetDriver(). On output, a pointer to the next driver         
-                                image handle.                                                   
-                                
+                                by GetDriver(). On output, a pointer to the next driver
+                                image handle.
+
   @retval EFI_SUCCESS           The driver override for ControllerHandle was returned in
-                                DriverImageHandle.                                      
+                                DriverImageHandle.
   @retval EFI_NOT_FOUND         A driver override for ControllerHandle was not found.
   @retval EFI_INVALID_PARAMETER The handle specified by ControllerHandle is NULL.
   @retval EFI_INVALID_PARAMETER DriverImageHandle is not a handle that was returned on a
-                                previous call to GetDriver().                           
-                                   
+                                previous call to GetDriver().
+
 **/
 typedef
 EFI_STATUS
@@ -56,25 +50,25 @@ EFI_STATUS
   IN OUT EFI_HANDLE                                     *DriverImageHandle
   );
 
-/**                                                                 
+/**
   Retrieves the device path of the platform override driver for a controller in the system.
-    
+
   @param  This                  A pointer to the EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL instance.
   @param  ControllerHandle      The device handle of the controller to check if a driver override
-                                exists.                                                          
+                                exists.
   @param  DriverImagePath       On input, a pointer to the previous driver device path returned by
                                 GetDriverPath(). On output, a pointer to the next driver
                                 device path. Passing in a pointer to NULL will return the first
                                 driver device path for ControllerHandle.
-                                
+
   @retval EFI_SUCCESS           The driver override for ControllerHandle was returned in
-                                DriverImageHandle.                                      
-  @retval EFI_UNSUPPORTED       The operation is not supported.                                
+                                DriverImageHandle.
+  @retval EFI_UNSUPPORTED       The operation is not supported.
   @retval EFI_NOT_FOUND         A driver override for ControllerHandle was not found.
   @retval EFI_INVALID_PARAMETER The handle specified by ControllerHandle is NULL.
   @retval EFI_INVALID_PARAMETER DriverImagePath is not a device path that was returned on a
-                                previous call to GetDriverPath().                          
-                                   
+                                previous call to GetDriverPath().
+
 **/
 typedef
 EFI_STATUS
@@ -84,31 +78,31 @@ EFI_STATUS
   IN OUT EFI_DEVICE_PATH_PROTOCOL                       **DriverImagePath
   );
 
-/**                                                                 
+/**
   Used to associate a driver image handle with a device path that was returned on a prior call to the
-  GetDriverPath() service. This driver image handle will then be available through the               
-  GetDriver() service.                                                                               
-    
+  GetDriverPath() service. This driver image handle will then be available through the
+  GetDriver() service.
+
   @param  This                  A pointer to the EFI_PLATFORM_DRIVER_OVERRIDE_
-                                PROTOCOL instance.                            
-  @param  ControllerHandle      The device handle of the controller.                                                             
+                                PROTOCOL instance.
+  @param  ControllerHandle      The device handle of the controller.
   @param  DriverImagePath       A pointer to the driver device path that was returned in a prior
-                                call to GetDriverPath().                                                                        
+                                call to GetDriverPath().
   @param  DriverImageHandle     The driver image handle that was returned by LoadImage()
-                                when the driver specified by DriverImagePath was loaded 
-                                into memory.                                            
-                                
-  @retval EFI_SUCCESS           The association between DriverImagePath and                   
+                                when the driver specified by DriverImagePath was loaded
+                                into memory.
+
+  @retval EFI_SUCCESS           The association between DriverImagePath and
                                 DriverImageHandle was established for the controller specified
-                                by ControllerHandle.                                                                            
-  @retval EFI_UNSUPPORTED       The operation is not supported.                                
+                                by ControllerHandle.
+  @retval EFI_UNSUPPORTED       The operation is not supported.
   @retval EFI_NOT_FOUND         DriverImagePath is not a device path that was returned on a prior
-                                call to GetDriverPath() for the controller specified by          
-                                ControllerHandle.                                                
+                                call to GetDriverPath() for the controller specified by
+                                ControllerHandle.
   @retval EFI_INVALID_PARAMETER ControllerHandle is NULL.
   @retval EFI_INVALID_PARAMETER DriverImagePath is not a valid device path.
   @retval EFI_INVALID_PARAMETER DriverImageHandle is not a valid image handle.
-                                   
+
 **/
 typedef
 EFI_STATUS
@@ -120,13 +114,13 @@ EFI_STATUS
   );
 
 ///
-/// This protocol matches one or more drivers to a controller. A platform driver 
-/// produces this protocol, and it is installed on a separate handle. This protocol 
-/// is used by the ConnectController() boot service to select the best driver 
-/// for a controller. All of the drivers returned by this protocol have a higher 
-/// precedence than drivers found from an EFI Bus Specific Driver Override Protocol 
-/// or drivers found from the general UEFI driver Binding search algorithm. If more 
-/// than one driver is returned by this protocol, then the drivers are returned in 
+/// This protocol matches one or more drivers to a controller. A platform driver
+/// produces this protocol, and it is installed on a separate handle. This protocol
+/// is used by the ConnectController() boot service to select the best driver
+/// for a controller. All of the drivers returned by this protocol have a higher
+/// precedence than drivers found from an EFI Bus Specific Driver Override Protocol
+/// or drivers found from the general UEFI driver Binding search algorithm. If more
+/// than one driver is returned by this protocol, then the drivers are returned in
 /// order from highest precedence to lowest precedence.
 ///
 struct _EFI_PLATFORM_DRIVER_OVERRIDE_PROTOCOL {
diff --git a/MdePkg/Include/Protocol/PlatformToDriverConfiguration.h b/MdePkg/Include/Protocol/PlatformToDriverConfiguration.h
index 8343cb8beaf9..55d1962d6168 100644
--- a/MdePkg/Include/Protocol/PlatformToDriverConfiguration.h
+++ b/MdePkg/Include/Protocol/PlatformToDriverConfiguration.h
@@ -1,18 +1,12 @@
 /** @file
   UEFI Platform to Driver Configuration Protocol is defined in UEFI specification.
-  
-  This is a protocol that is optionally produced by the platform and optionally consumed 
-  by a UEFI Driver in its Start() function. This protocol allows the driver to receive 
-  configuration information as part of being started.
 
-  Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
+  This is a protocol that is optionally produced by the platform and optionally consumed
+  by a UEFI Driver in its Start() function. This protocol allows the driver to receive
+  configuration information as part of being started.
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -58,10 +52,10 @@ typedef struct _EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL EFI_PLATFORM_TO_DR
   increment the Instance value by one for each successive call to Query.
 
   @param This                 A pointer to the EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL instance.
-  
+
   @param ControllerHandle     The handle the platform will return
                               configuration information about.
-  
+
   @param ChildHandle          The handle of the child controller to
                               return information on. This is an optional
                               parameter that may be NULL. It will be
@@ -70,8 +64,8 @@ typedef struct _EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL EFI_PLATFORM_TO_DR
                               the bus controller. It will not be NULL
                               for a bus driver that attempts to get
                               options for one of its child controllers.
-  
-  
+
+
   @param Instance             Pointer to the Instance value. Zero means
                               return the first query data. The caller should
                               increment this value by one each time to retrieve
@@ -148,26 +142,26 @@ typedef enum {
   ///  configuration settings.
   ///
   EfiPlatformConfigurationActionNone              = 0,
-  
+
   ///
   ///  The driver has detected that the controller specified
-  ///  by ControllerHandle is not in a usable state and 
+  ///  by ControllerHandle is not in a usable state and
   ///  needs to be stopped. The calling agent can use the
   ///  DisconnectControservice to perform this operation, and
-  ///  it should be performed as soon as possible.  
+  ///  it should be performed as soon as possible.
   ///
   EfiPlatformConfigurationActionStopController    = 1,
-  
+
   ///
   ///  This controller specified by ControllerHandle needs to
   ///  be stopped and restarted before it can be used again.
   ///  The calling agent can use the DisconnectController()
   ///  and ConnectController() services to perform this
   ///  operation. The restart operation can be delayed until
-  ///  all of the configuration options have been set.  
+  ///  all of the configuration options have been set.
   ///
   EfiPlatformConfigurationActionRestartController = 2,
-  
+
   ///
   ///  A configuration change has been made that requires the
   ///  platform to be restarted before the controller
@@ -175,7 +169,7 @@ typedef enum {
   ///  calling agent can use the ResetSystem() services to
   ///  perform this operation. The restart operation can be
   ///  delayed until all of the configuration options have
-  ///  been set.  
+  ///  been set.
   ///
   EfiPlatformConfigurationActionRestartPlatform   = 3,
 
@@ -188,8 +182,8 @@ typedef enum {
   ///  are required before this controller can be used again
   ///  with the updated configuration settings, but these
   ///  configuration settings are not guaranteed to persist
-  ///  after ControllerHandle is stopped. 
-  /// 
+  ///  after ControllerHandle is stopped.
+  ///
   EfiPlatformConfigurationActionNvramFailed       = 4,
 
   ///
@@ -249,17 +243,17 @@ typedef enum {
   @param ConfigurationAction The driver tells the platform what
                              action is required for ParameterBlock to
                              take effect.
-  
-  
+
+
   @retval EFI_SUCCESS           The platform return parameter information
                                 for ControllerHandle.
-  
+
   @retval EFI_NOT_FOUND         Instance was not found.
-  
+
   @retval EFI_INVALID_PARAMETER ControllerHandle is NULL.
- 
+
   @retval EFI_INVALID_PARAMETER Instance is zero.
-  
+
 **/
 typedef
 EFI_STATUS
@@ -298,7 +292,7 @@ struct _EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL {
   {0x345ecc0e, 0xcb6, 0x4b75, { 0xbb, 0x57, 0x1b, 0x12, 0x9c, 0x47, 0x33,0x3e } }
 
 /**
-   
+
   ParameterTypeGuid provides the support for parameters
   communicated through the DMTF SM CLP Specification 1.0 Final
   Standard to be used to configure the UEFI driver. In this
@@ -311,8 +305,8 @@ struct _EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL {
 **/
 typedef struct {
   CHAR8   *CLPCommand;        ///<  A pointer to the null-terminated UTF-8 string that specifies the DMTF SM CLP command
-                              ///<  line that the driver is required to parse and process when this function is called. 
-                              ///<  See the DMTF SM CLP Specification 1.0 Final Standard for details on the 
+                              ///<  line that the driver is required to parse and process when this function is called.
+                              ///<  See the DMTF SM CLP Specification 1.0 Final Standard for details on the
                               ///<  format and syntax of the CLP command line string. CLPCommand buffer
                               ///<  is allocated by the producer of the EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOOL.
   UINT32  CLPCommandLength;   ///< The length of the CLP Command in bytes.
@@ -329,20 +323,20 @@ typedef struct {
                               ///<  the SM CLP Coutput option requested by the caller is not supported by the
                               ///<  UEFI Driver). CLPReturnString buffer is allocated by the consumer of the
                               ///<  EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOC OL and undefined prior to the call to
-                              ///<  Response().  
+                              ///<  Response().
   UINT32  CLPReturnStringLength; ///< The length of the CLP return status string in bytes.
   UINT8   CLPCmdStatus;       ///<  SM CLP Command Status (see DMTF SM CLP Specification 1.0 Final Standard -
                               ///<  Table 4) CLPErrorValue SM CLP Processing Error Value (see DMTF SM
                               ///<  CLP Specification 1.0 Final Standard - Table 6). This field is filled in by
-                              ///<  the consumer of the EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOC 
-                              ///<  OL and undefined prior to the call to Response().  
+                              ///<  the consumer of the EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOC
+                              ///<  OL and undefined prior to the call to Response().
   UINT8   CLPErrorValue;      ///<  SM CLP Processing Error Value (see DMTF SM CLP Specification 1.0 Final Standard - Table 6).
-                              ///<  This field is filled in by the consumer of the EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL and undefined prior to the call to Response().                              
+                              ///<  This field is filled in by the consumer of the EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOCOL and undefined prior to the call to Response().
   UINT16  CLPMsgCode;         ///<  Bit 15: OEM Message Code Flag 0 = Message Code is an SM CLP Probable
                               ///<  Cause Value. (see SM CLP Specification Table 11) 1 = Message Code is OEM
                               ///<  Specific Bits 14-0: Message Code This field is filled in by the consumer of
                               ///<  the EFI_PLATFORM_TO_DRIVER_CONFIGURATION_PROTOC OL and undefined prior to the call to
-                              ///<  Response(). 
+                              ///<  Response().
 
 } EFI_CONFIGURE_CLP_PARAMETER_BLK;
 
diff --git a/MdePkg/Include/Protocol/PxeBaseCode.h b/MdePkg/Include/Protocol/PxeBaseCode.h
index 497d97204712..388a83a09079 100644
--- a/MdePkg/Include/Protocol/PxeBaseCode.h
+++ b/MdePkg/Include/Protocol/PxeBaseCode.h
@@ -1,18 +1,14 @@
 /** @file
-  EFI PXE Base Code Protocol definitions, which is used to access PXE-compatible 
+  EFI PXE Base Code Protocol definitions, which is used to access PXE-compatible
   devices for network access and network booting.
 
-Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
 
-  @par Revision Reference:          
-  This Protocol is introduced in EFI Specification 1.10.           
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  This Protocol is introduced in EFI Specification 1.10.
 
 **/
 #ifndef __PXE_BASE_CODE_PROTOCOL_H__
@@ -30,7 +26,7 @@ typedef struct _EFI_PXE_BASE_CODE_PROTOCOL  EFI_PXE_BASE_CODE_PROTOCOL;
 
 ///
 /// Protocol defined in EFI1.1.
-/// 
+///
 typedef EFI_PXE_BASE_CODE_PROTOCOL  EFI_PXE_BASE_CODE;
 
 ///
@@ -146,21 +142,21 @@ typedef UINT16  EFI_PXE_BASE_CODE_UDP_PORT;
 #define EFI_PXE_BASE_CODE_BOOT_LAYER_INITIAL  0x0000
 
 //
-// PXE Tag definition that identifies the processor 
+// PXE Tag definition that identifies the processor
 // and programming environment of the client system.
 // These identifiers are defined by IETF:
 // http://www.ietf.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xml
 //
 #if defined (MDE_CPU_IA32)
 #define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE    0x0006
-#elif defined (MDE_CPU_IPF) 
-#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE    0x0002
 #elif defined (MDE_CPU_X64)
 #define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE    0x0007
 #elif defined (MDE_CPU_ARM)
 #define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE    0x000A
 #elif defined (MDE_CPU_AARCH64)
 #define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE    0x000B
+#elif defined (MDE_CPU_RISCV64)
+#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE    0x001B
 #endif
 
 
@@ -263,7 +259,7 @@ typedef union {
 
 ///
 /// EFI_PXE_BASE_CODE_MODE.
-/// The data values in this structure are read-only and 
+/// The data values in this structure are read-only and
 /// are updated by the code that produces the
 /// EFI_PXE_BASE_CODE_PROTOCOL functions.
 ///
@@ -308,7 +304,7 @@ typedef struct {
 // PXE Base Code Interface Function definitions
 //
 
-/**                                                                 
+/**
   Enables the use of the PXE Base Code Protocol functions.
 
   This function enables the use of the PXE Base Code Protocol functions. If the
@@ -355,22 +351,22 @@ typedef struct {
     TftpErrorZero-filled.
     MakeCallbacksSet to TRUE if the PXE Base Code Callback Protocol is available.
     Set to FALSE if the PXE Base Code Callback Protocol is not available.
-    
+
   @param  This                  The pointer to the EFI_PXE_BASE_CODE_PROTOCOL instance.
   @param  UseIpv6               Specifies the type of IP addresses that are to be used during the session
-                                that is being started. Set to TRUE for IPv6 addresses, and FALSE for     
-                                IPv4 addresses.                                                                                                   
-                                
+                                that is being started. Set to TRUE for IPv6 addresses, and FALSE for
+                                IPv4 addresses.
+
   @retval EFI_SUCCESS           The PXE Base Code Protocol was started.
-  @retval EFI_DEVICE_ERROR      The network device encountered an error during this oper  
+  @retval EFI_DEVICE_ERROR      The network device encountered an error during this oper
   @retval EFI_UNSUPPORTED       UseIpv6 is TRUE, but the Ipv6Supported field of the
-                                EFI_PXE_BASE_CODE_MODE structure is FALSE.  
-  @retval EFI_ALREADY_STARTED   The PXE Base Code Protocol is already in the started state.                                   
+                                EFI_PXE_BASE_CODE_MODE structure is FALSE.
+  @retval EFI_ALREADY_STARTED   The PXE Base Code Protocol is already in the started state.
   @retval EFI_INVALID_PARAMETER The This parameter is NULL or does not point to a valid
-                                EFI_PXE_BASE_CODE_PROTOCOL structure.      
-  @retval EFI_OUT_OF_RESOURCES  Could not allocate enough memory or other resources to start the                                          
-                                PXE Base Code Protocol.                                         
-                                     
+                                EFI_PXE_BASE_CODE_PROTOCOL structure.
+  @retval EFI_OUT_OF_RESOURCES  Could not allocate enough memory or other resources to start the
+                                PXE Base Code Protocol.
+
 **/
 typedef
 EFI_STATUS
@@ -379,22 +375,22 @@ EFI_STATUS
   IN BOOLEAN                               UseIpv6
   );
 
-/**                                                                 
+/**
   Disables the use of the PXE Base Code Protocol functions.
 
   This function stops all activity on the network device. All the resources allocated
   in Start() are released, the Started field of the EFI_PXE_BASE_CODE_MODE structure is
   set to FALSE and EFI_SUCCESS is returned. If the Started field of the EFI_PXE_BASE_CODE_MODE
   structure is already FALSE, then EFI_NOT_STARTED will be returned.
-  
+
   @param  This                  The pointer to the EFI_PXE_BASE_CODE_PROTOCOL instance.
- 
+
   @retval EFI_SUCCESS           The PXE Base Code Protocol was stopped.
-  @retval EFI_NOT_STARTED       The PXE Base Code Protocol is already in the stopped state.  
+  @retval EFI_NOT_STARTED       The PXE Base Code Protocol is already in the stopped state.
   @retval EFI_INVALID_PARAMETER The This parameter is NULL or does not point to a valid
-                                EFI_PXE_BASE_CODE_PROTOCOL structure.                  
-  @retval EFI_DEVICE_ERROR      The network device encountered an error during this operation.                                
-                                     
+                                EFI_PXE_BASE_CODE_PROTOCOL structure.
+  @retval EFI_DEVICE_ERROR      The network device encountered an error during this operation.
+
 **/
 typedef
 EFI_STATUS
@@ -402,7 +398,7 @@ EFI_STATUS
   IN EFI_PXE_BASE_CODE_PROTOCOL    *This
   );
 
-/**                                                                 
+/**
   Attempts to complete a DHCPv4 D.O.R.A. (discover / offer / request / acknowledge) or DHCPv6
   S.A.R.R (solicit / advertise / request / reply) sequence.
 
@@ -418,22 +414,22 @@ EFI_STATUS
   caller. If the DHCP sequence does not complete, then EFI_TIMEOUT will be returned.
   If the Callback Protocol does not return EFI_PXE_BASE_CODE_CALLBACK_STATUS_CONTINUE,
   then the DHCP sequence will be stopped and EFI_ABORTED will be returned.
-    
+
   @param  This                  The pointer to the EFI_PXE_BASE_CODE_PROTOCOL instance.
   @param  SortOffers            TRUE if the offers received should be sorted. Set to FALSE to try the
-                                offers in the order that they are received.                          
- 
+                                offers in the order that they are received.
+
   @retval EFI_SUCCESS           Valid DHCP has completed.
   @retval EFI_NOT_STARTED       The PXE Base Code Protocol is in the stopped state.
   @retval EFI_INVALID_PARAMETER The This parameter is NULL or does not point to a valid
-                                EFI_PXE_BASE_CODE_PROTOCOL structure.                  
-  @retval EFI_DEVICE_ERROR      The network device encountered an error during this operation.                                
+                                EFI_PXE_BASE_CODE_PROTOCOL structure.
+  @retval EFI_DEVICE_ERROR      The network device encountered an error during this operation.
   @retval EFI_OUT_OF_RESOURCES  Could not allocate enough memory to complete the DHCP Protocol.
   @retval EFI_ABORTED           The callback function aborted the DHCP Protocol.
   @retval EFI_TIMEOUT           The DHCP Protocol timed out.
   @retval EFI_ICMP_ERROR        An ICMP error packet was received during the DHCP session.
   @retval EFI_NO_RESPONSE       Valid PXE offer was not received.
-                                     
+
 **/
 typedef
 EFI_STATUS
@@ -442,7 +438,7 @@ EFI_STATUS
   IN BOOLEAN                               SortOffers
   );
 
-/**                                                                 
+/**
   Attempts to complete the PXE Boot Server and/or boot image discovery sequence.
 
   This function attempts to complete the PXE Boot Server and/or boot image discovery
@@ -464,26 +460,26 @@ EFI_STATUS
   additional details on the implementation of the Discovery sequence.
   If the Callback Protocol does not return EFI_PXE_BASE_CODE_CALLBACK_STATUS_CONTINUE,
   then the Discovery sequence is stopped and EFI_ABORTED will be returned.
-    
+
   @param  This                  The pointer to the EFI_PXE_BASE_CODE_PROTOCOL instance.
   @param  Type                  The type of bootstrap to perform.
   @param  Layer                 The pointer to the boot server layer number to discover, which must be
-                                PXE_BOOT_LAYER_INITIAL when a new server type is being            
-                                discovered.                                                       
-  @param  UseBis                TRUE if Boot Integrity Services are to be used. FALSE otherwise.                                
+                                PXE_BOOT_LAYER_INITIAL when a new server type is being
+                                discovered.
+  @param  UseBis                TRUE if Boot Integrity Services are to be used. FALSE otherwise.
   @param  Info                  The pointer to a data structure that contains additional information on the
-                                type of discovery operation that is to be performed.                   
-                                  
+                                type of discovery operation that is to be performed.
+
   @retval EFI_SUCCESS           The Discovery sequence has been completed.
   @retval EFI_NOT_STARTED       The PXE Base Code Protocol is in the stopped state.
-  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.                                
-  @retval EFI_DEVICE_ERROR      The network device encountered an error during this operation.                                
+  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+  @retval EFI_DEVICE_ERROR      The network device encountered an error during this operation.
   @retval EFI_OUT_OF_RESOURCES  Could not allocate enough memory to complete Discovery.
   @retval EFI_ABORTED           The callback function aborted the Discovery sequence.
   @retval EFI_TIMEOUT           The Discovery sequence timed out.
   @retval EFI_ICMP_ERROR        An ICMP error packet was received during the PXE discovery
-                                session.                                                  
-                                       
+                                session.
+
 **/
 typedef
 EFI_STATUS
@@ -495,7 +491,7 @@ EFI_STATUS
   IN EFI_PXE_BASE_CODE_DISCOVER_INFO      *Info   OPTIONAL
   );
 
-/**                                                                 
+/**
   Used to perform TFTP and MTFTP services.
 
   This function is used to perform TFTP and MTFTP services. This includes the
@@ -540,31 +536,31 @@ EFI_STATUS
   IP address preceding the filename of the form %d.%d.%d.%d for IP v4. The final
   entry is itself null-terminated, so that the final information string is terminated
   with two null octets.
-    
+
   @param  This                  The pointer to the EFI_PXE_BASE_CODE_PROTOCOL instance.
   @param  Operation             The type of operation to perform.
-  @param  BufferPtr             A pointer to the data buffer.                                                                     
+  @param  BufferPtr             A pointer to the data buffer.
   @param  Overwrite             Only used on write file operations. TRUE if a file on a remote server can
-                                be overwritten.                                                          
+                                be overwritten.
   @param  BufferSize            For get-file-size operations, *BufferSize returns the size of the
-                                requested file.                                                  
+                                requested file.
   @param  BlockSize             The requested block size to be used during a TFTP transfer.
   @param  ServerIp              The TFTP / MTFTP server IP address.
   @param  Filename              A Null-terminated ASCII string that specifies a directory name or a file
-                                name.                                                                   
+                                name.
   @param  Info                  The pointer to the MTFTP information.
-  @param  DontUseBuffer         Set to FALSE for normal TFTP and MTFTP read file operation.                       
-                                  
+  @param  DontUseBuffer         Set to FALSE for normal TFTP and MTFTP read file operation.
+
   @retval EFI_SUCCESS           The TFTP/MTFTP operation was completed.
   @retval EFI_NOT_STARTED       The PXE Base Code Protocol is in the stopped state.
-  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.                                
-  @retval EFI_DEVICE_ERROR      The network device encountered an error during this operation.                                
-  @retval EFI_BUFFER_TOO_SMALL  The buffer is not large enough to complete the read operation.   
+  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+  @retval EFI_DEVICE_ERROR      The network device encountered an error during this operation.
+  @retval EFI_BUFFER_TOO_SMALL  The buffer is not large enough to complete the read operation.
   @retval EFI_ABORTED           The callback function aborted the TFTP/MTFTP operation.
   @retval EFI_TIMEOUT           The TFTP/MTFTP operation timed out.
   @retval EFI_ICMP_ERROR        An ICMP error packet was received during the MTFTP session.
   @retval EFI_TFTP_ERROR        A TFTP error packet was received during the MTFTP session.
-                                                                      
+
 **/
 typedef
 EFI_STATUS
@@ -581,7 +577,7 @@ EFI_STATUS
   IN BOOLEAN                                   DontUseBuffer
   );
 
-/**                                                                 
+/**
   Writes a UDP packet to the network interface.
 
   This function writes a UDP packet specified by the (optional HeaderPtr and)
@@ -594,29 +590,29 @@ EFI_STATUS
   the IcmpErrorReceived field is set to TRUE, the IcmpError field is filled in and
   EFI_ICMP_ERROR will be returned. If the Callback Protocol does not return
   EFI_PXE_BASE_CODE_CALLBACK_STATUS_CONTINUE, then EFI_ABORTED will be returned.
-    
+
   @param  This                  The pointer to the EFI_PXE_BASE_CODE_PROTOCOL instance.
-  @param  OpFlags               The UDP operation flags. 
+  @param  OpFlags               The UDP operation flags.
   @param  DestIp                The destination IP address.
-  @param  DestPort              The destination UDP port number.                                                                         
-  @param  GatewayIp             The gateway IP address.                                                 
+  @param  DestPort              The destination UDP port number.
+  @param  GatewayIp             The gateway IP address.
   @param  SrcIp                 The source IP address.
   @param  SrcPort               The source UDP port number.
   @param  HeaderSize            An optional field which may be set to the length of a header at
-                                HeaderPtr to be prefixed to the data at BufferPtr.             
+                                HeaderPtr to be prefixed to the data at BufferPtr.
   @param  HeaderPtr             If HeaderSize is not NULL, a pointer to a header to be prefixed to the
-                                data at BufferPtr.                                                    
+                                data at BufferPtr.
   @param  BufferSize            A pointer to the size of the data at BufferPtr.
   @param  BufferPtr             A pointer to the data to be written.
-                                  
+
   @retval EFI_SUCCESS           The UDP Write operation was completed.
   @retval EFI_NOT_STARTED       The PXE Base Code Protocol is in the stopped state.
-  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.                                
-  @retval EFI_BAD_BUFFER_SIZE   The buffer is too long to be transmitted.  
+  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+  @retval EFI_BAD_BUFFER_SIZE   The buffer is too long to be transmitted.
   @retval EFI_ABORTED           The callback function aborted the UDP Write operation.
   @retval EFI_TIMEOUT           The UDP Write operation timed out.
-  @retval EFI_ICMP_ERROR        An ICMP error packet was received during the UDP write session.  
-                                                                      
+  @retval EFI_ICMP_ERROR        An ICMP error packet was received during the UDP write session.
+
 **/
 typedef
 EFI_STATUS
@@ -634,7 +630,7 @@ EFI_STATUS
   IN VOID                                      *BufferPtr
   );
 
-/**                                                                 
+/**
   Reads a UDP packet from the network interface.
 
   This function reads a UDP packet from a network interface. The data contents
@@ -649,28 +645,28 @@ EFI_STATUS
   Depending on the values of OpFlags and the DestIp, DestPort, SrcIp, and SrcPort
   input values, different types of UDP packet receive filtering will be performed.
   The following tables summarize these receive filter operations.
-    
+
   @param  This                  The pointer to the EFI_PXE_BASE_CODE_PROTOCOL instance.
-  @param  OpFlags               The UDP operation flags. 
+  @param  OpFlags               The UDP operation flags.
   @param  DestIp                The destination IP address.
   @param  DestPort              The destination UDP port number.
   @param  SrcIp                 The source IP address.
   @param  SrcPort               The source UDP port number.
   @param  HeaderSize            An optional field which may be set to the length of a header at
-                                HeaderPtr to be prefixed to the data at BufferPtr.             
+                                HeaderPtr to be prefixed to the data at BufferPtr.
   @param  HeaderPtr             If HeaderSize is not NULL, a pointer to a header to be prefixed to the
-                                data at BufferPtr.                                                    
+                                data at BufferPtr.
   @param  BufferSize            A pointer to the size of the data at BufferPtr.
   @param  BufferPtr             A pointer to the data to be read.
-                                  
+
   @retval EFI_SUCCESS           The UDP Read operation was completed.
   @retval EFI_NOT_STARTED       The PXE Base Code Protocol is in the stopped state.
-  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.                                
+  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
   @retval EFI_DEVICE_ERROR      The network device encountered an error during this operation.
   @retval EFI_BUFFER_TOO_SMALL  The packet is larger than Buffer can hold.
   @retval EFI_ABORTED           The callback function aborted the UDP Read operation.
-  @retval EFI_TIMEOUT           The UDP Read operation timed out.  
-                                                                      
+  @retval EFI_TIMEOUT           The UDP Read operation timed out.
+
 **/
 typedef
 EFI_STATUS
@@ -687,9 +683,9 @@ EFI_STATUS
   IN VOID                                      *BufferPtr
   );
 
-/**                                                                 
+/**
   Updates the IP receive filters of a network device and enables software filtering.
-  
+
   The NewFilter field is used to modify the network device's current IP receive
   filter settings and to enable a software filter. This function updates the IpFilter
   field of the EFI_PXE_BASE_CODE_MODE structure with the contents of NewIpFilter.
@@ -710,14 +706,14 @@ EFI_STATUS
   The IPlist field is used to enable IPs other than the StationIP. They may be
   multicast or unicast. If IPcnt is set as well as EFI_PXE_BASE_CODE_IP_FILTER_STATION_IP,
   then both the StationIP and the IPs from the IPlist will be used.
-    
+
   @param  This                  The pointer to the EFI_PXE_BASE_CODE_PROTOCOL instance.
   @param  NewFilter             The pointer to the new set of IP receive filters.
-  
+
   @retval EFI_SUCCESS           The IP receive filter settings were updated.
   @retval EFI_NOT_STARTED       The PXE Base Code Protocol is in the stopped state.
-  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.                                  
-                                                                      
+  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+
 **/
 typedef
 EFI_STATUS
@@ -726,9 +722,9 @@ EFI_STATUS
   IN EFI_PXE_BASE_CODE_IP_FILTER           *NewFilter
   );
 
-/**                                                                 
+/**
   Uses the ARP protocol to resolve a MAC address.
-  
+
   This function uses the ARP protocol to resolve a MAC address. The UsingIpv6 field
   of the EFI_PXE_BASE_CODE_MODE structure is used to determine if IPv4 or IPv6
   addresses are being used. The IP address specified by IpAddr is used to resolve
@@ -741,19 +737,19 @@ EFI_STATUS
   to resolve an address, then EFI_TIMEOUT is returned. If the Callback Protocol
   does not return EFI_PXE_BASE_CODE_CALLBACK_STATUS_CONTINUE, then EFI_ABORTED is
   returned.
-    
+
   @param  This                  The pointer to the EFI_PXE_BASE_CODE_PROTOCOL instance.
   @param  IpAddr                The pointer to the IP address that is used to resolve a MAC address.
   @param  MacAddr               If not NULL, a pointer to the MAC address that was resolved with the
-                                ARP protocol.                                                       
-                                  
+                                ARP protocol.
+
   @retval EFI_SUCCESS           The IP or MAC address was resolved.
   @retval EFI_NOT_STARTED       The PXE Base Code Protocol is in the stopped state.
-  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.                                
-  @retval EFI_DEVICE_ERROR      The network device encountered an error during this operation.  
+  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+  @retval EFI_DEVICE_ERROR      The network device encountered an error during this operation.
   @retval EFI_ABORTED           The callback function aborted the ARP Protocol.
   @retval EFI_TIMEOUT           The ARP Protocol encountered a timeout condition.
-                                                                      
+
 **/
 typedef
 EFI_STATUS
@@ -763,9 +759,9 @@ EFI_STATUS
   IN EFI_MAC_ADDRESS                       *MacAddr OPTIONAL
   );
 
-/**                                                                 
+/**
   Updates the parameters that affect the operation of the PXE Base Code Protocol.
-  
+
   This function sets parameters that affect the operation of the PXE Base Code Protocol.
   The parameter specified by NewAutoArp is used to control the generation of ARP
   protocol packets. If NewAutoArp is TRUE, then ARP Protocol packets will be generated
@@ -777,23 +773,23 @@ EFI_STATUS
   the EFI_PXE_BASE_CODE_MODE structure to NewAutoArp.
   The SetParameters() call must be invoked after a Callback Protocol is installed
   to enable the use of callbacks.
-    
+
   @param  This                  The pointer to the EFI_PXE_BASE_CODE_PROTOCOL instance.
   @param  NewAutoArp            If not NULL, a pointer to a value that specifies whether to replace the
-                                current value of AutoARP.                                              
+                                current value of AutoARP.
   @param  NewSendGUID           If not NULL, a pointer to a value that specifies whether to replace the
-                                current value of SendGUID.                                             
+                                current value of SendGUID.
   @param  NewTTL                If not NULL, a pointer to be used in place of the current value of TTL,
-                                the "time to live" field of the IP header.                           
+                                the "time to live" field of the IP header.
   @param  NewToS                If not NULL, a pointer to be used in place of the current value of ToS,
-                                the "type of service" field of the IP header.                        
+                                the "type of service" field of the IP header.
   @param  NewMakeCallback       If not NULL, a pointer to a value that specifies whether to replace the
-                                current value of the MakeCallback field of the Mode structure.                                                                
-                                  
+                                current value of the MakeCallback field of the Mode structure.
+
   @retval EFI_SUCCESS           The new parameters values were updated.
   @retval EFI_NOT_STARTED       The PXE Base Code Protocol is in the stopped state.
-  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.                                  
-                                                                      
+  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+
 **/
 typedef
 EFI_STATUS
@@ -806,9 +802,9 @@ EFI_STATUS
   IN BOOLEAN                               *NewMakeCallback OPTIONAL
   );
 
-/**                                                                 
+/**
   Updates the station IP address and/or subnet mask values of a network device.
-  
+
   This function updates the station IP address and/or subnet mask values of a network
   device.
   The NewStationIp field is used to modify the network device's current IP address.
@@ -819,15 +815,15 @@ EFI_STATUS
   mask. If NewSubnetMask is NULL, then the current subnet mask will not be modified.
   Otherwise, this function updates the SubnetMask field of the EFI_PXE_BASE_CODE_MODE
   structure with NewSubnetMask.
-    
+
   @param  This                  The pointer to the EFI_PXE_BASE_CODE_PROTOCOL instance.
-  @param  NewStationIp          The pointer to the new IP address to be used by the network device.  
-  @param  NewSubnetMask         The pointer to the new subnet mask to be used by the network device.                                 
-                                  
+  @param  NewStationIp          The pointer to the new IP address to be used by the network device.
+  @param  NewSubnetMask         The pointer to the new subnet mask to be used by the network device.
+
   @retval EFI_SUCCESS           The new station IP address and/or subnet mask were updated.
   @retval EFI_NOT_STARTED       The PXE Base Code Protocol is in the stopped state.
-  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.                                  
-                                                                      
+  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+
 **/
 typedef
 EFI_STATUS
@@ -837,36 +833,36 @@ EFI_STATUS
   IN EFI_IP_ADDRESS                        *NewSubnetMask   OPTIONAL
   );
 
-/**                                                                 
+/**
   Updates the contents of the cached DHCP and Discover packets.
-  
+
   The pointers to the new packets are used to update the contents of the cached
   packets in the EFI_PXE_BASE_CODE_MODE structure.
-    
+
   @param  This                   The pointer to the EFI_PXE_BASE_CODE_PROTOCOL instance.
   @param  NewDhcpDiscoverValid   The pointer to a value that will replace the current
-                                 DhcpDiscoverValid field.                        
+                                 DhcpDiscoverValid field.
   @param  NewDhcpAckReceived     The pointer to a value that will replace the current
-                                 DhcpAckReceived field.                          
+                                 DhcpAckReceived field.
   @param  NewProxyOfferReceived  The pointer to a value that will replace the current
-                                 ProxyOfferReceived field.                       
-  @param  NewPxeDiscoverValid    The pointer to a value that will replace the current     
-                                 ProxyOfferReceived field.                       
+                                 ProxyOfferReceived field.
+  @param  NewPxeDiscoverValid    The pointer to a value that will replace the current
+                                 ProxyOfferReceived field.
   @param  NewPxeReplyReceived    The pointer to a value that will replace the current
-                                 PxeReplyReceived field.                         
+                                 PxeReplyReceived field.
   @param  NewPxeBisReplyReceived The pointer to a value that will replace the current
-                                 PxeBisReplyReceived field.                      
-  @param  NewDhcpDiscover        The pointer to the new cached DHCP Discover packet contents.   
+                                 PxeBisReplyReceived field.
+  @param  NewDhcpDiscover        The pointer to the new cached DHCP Discover packet contents.
   @param  NewDhcpAck             The pointer to the new cached DHCP Ack packet contents.
   @param  NewProxyOffer          The pointer to the new cached Proxy Offer packet contents.
   @param  NewPxeDiscover         The pointer to the new cached PXE Discover packet contents.
   @param  NewPxeReply            The pointer to the new cached PXE Reply packet contents.
   @param  NewPxeBisReply         The pointer to the new cached PXE BIS Reply packet contents.
-                                   
+
   @retval EFI_SUCCESS            The cached packet contents were updated.
   @retval EFI_NOT_STARTED        The PXE Base Code Protocol is in the stopped state.
   @retval EFI_INVALID_PARAMETER  This is NULL or not point to a valid EFI_PXE_BASE_CODE_PROTOCOL structure.
-                                                                      
+
 **/
 typedef
 EFI_STATUS
@@ -893,7 +889,7 @@ EFI_STATUS
 
 //
 // Revision defined in EFI1.1
-// 
+//
 #define EFI_PXE_BASE_CODE_INTERFACE_REVISION  EFI_PXE_BASE_CODE_PROTOCOL_REVISION
 
 ///
@@ -906,8 +902,8 @@ EFI_STATUS
 ///
 struct _EFI_PXE_BASE_CODE_PROTOCOL {
   ///
-  ///  The revision of the EFI_PXE_BASE_CODE_PROTOCOL. All future revisions must 
-  ///  be backwards compatible. If a future version is not backwards compatible 
+  ///  The revision of the EFI_PXE_BASE_CODE_PROTOCOL. All future revisions must
+  ///  be backwards compatible. If a future version is not backwards compatible
   ///  it is not the same GUID.
   ///
   UINT64                            Revision;
@@ -931,4 +927,4 @@ struct _EFI_PXE_BASE_CODE_PROTOCOL {
 
 extern EFI_GUID gEfiPxeBaseCodeProtocolGuid;
 
-#endif 
+#endif
diff --git a/MdePkg/Include/Protocol/PxeBaseCodeCallBack.h b/MdePkg/Include/Protocol/PxeBaseCodeCallBack.h
index f653fdf7ff2c..2640a1c2bab5 100644
--- a/MdePkg/Include/Protocol/PxeBaseCodeCallBack.h
+++ b/MdePkg/Include/Protocol/PxeBaseCodeCallBack.h
@@ -1,17 +1,11 @@
 /** @file
-  It is invoked when the PXE Base Code Protocol is about to transmit, has received, 
+  It is invoked when the PXE Base Code Protocol is about to transmit, has received,
   or is waiting to receive a packet.
 
-Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
-  @par Revision Reference:          
+  @par Revision Reference:
   This Protocol is introduced in EFI Specification 1.10
 
 **/
@@ -45,7 +39,7 @@ typedef struct _EFI_PXE_BASE_CODE_CALLBACK_PROTOCOL  EFI_PXE_BASE_CODE_CALLBACK_
 
 ///
 /// EFI1.1 Protocol name.
-/// 
+///
 typedef EFI_PXE_BASE_CODE_CALLBACK_PROTOCOL   EFI_PXE_BASE_CODE_CALLBACK;
 
 ///
@@ -73,10 +67,10 @@ typedef enum {
   EFI_PXE_BASE_CODE_CALLBACK_STATUS_LAST
 } EFI_PXE_BASE_CODE_CALLBACK_STATUS;
 
-/**                                                                 
+/**
   Callback function that is invoked when the PXE Base Code Protocol is about to transmit, has
-  received, or is waiting to receive a packet.                                                 
-  
+  received, or is waiting to receive a packet.
+
   This function is invoked when the PXE Base Code Protocol is about to transmit, has received,
   or is waiting to receive a packet. Parameters Function and Received specify the type of event.
   Parameters PacketLen and Packet specify the packet that generated the event. If these fields
@@ -86,22 +80,22 @@ typedef enum {
   the polling nature of UEFI device drivers, a callback function should not execute for more than 5 ms.
   The SetParameters() function must be called after a Callback Protocol is installed to enable the
   use of callbacks.
-  
+
   @param  This                  The pointer to the EFI_PXE_BASE_CODE_CALLBACK_PROTOCOL instance.
-  @param  Function              The PXE Base Code Protocol function that is waiting for an event.                                                              
+  @param  Function              The PXE Base Code Protocol function that is waiting for an event.
   @param  Received              TRUE if the callback is being invoked due to a receive event. FALSE if
-                                the callback is being invoked due to a transmit event.                
+                                the callback is being invoked due to a transmit event.
   @param  PacketLen             The length, in bytes, of Packet. This field will have a value of zero if
-                                this is a wait for receive event.                                       
+                                this is a wait for receive event.
   @param  Packet                If Received is TRUE, a pointer to the packet that was just received;
-                                otherwise a pointer to the packet that is about to be transmitted.  
-                                  
-  @retval EFI_PXE_BASE_CODE_CALLBACK_STATUS_CONTINUE if Function specifies a continue operation    
+                                otherwise a pointer to the packet that is about to be transmitted.
+
+  @retval EFI_PXE_BASE_CODE_CALLBACK_STATUS_CONTINUE if Function specifies a continue operation
   @retval EFI_PXE_BASE_CODE_CALLBACK_STATUS_ABORT    if Function specifies an abort operation
-                                   
+
 **/
-typedef 
-EFI_PXE_BASE_CODE_CALLBACK_STATUS 
+typedef
+EFI_PXE_BASE_CODE_CALLBACK_STATUS
 (EFIAPI *EFI_PXE_CALLBACK)(
   IN EFI_PXE_BASE_CODE_CALLBACK_PROTOCOL  *This,
   IN EFI_PXE_BASE_CODE_FUNCTION           Function,
@@ -111,13 +105,13 @@ EFI_PXE_BASE_CODE_CALLBACK_STATUS
   );
 
 ///
-/// Protocol that is invoked when the PXE Base Code Protocol is about 
+/// Protocol that is invoked when the PXE Base Code Protocol is about
 /// to transmit, has received, or is waiting to receive a packet.
 ///
 struct _EFI_PXE_BASE_CODE_CALLBACK_PROTOCOL {
   ///
-  ///  The revision of the EFI_PXE_BASE_CODE_PROTOCOL. All future revisions must 
-  ///  be backwards compatible. If a future version is not backwards compatible 
+  ///  The revision of the EFI_PXE_BASE_CODE_PROTOCOL. All future revisions must
+  ///  be backwards compatible. If a future version is not backwards compatible
   ///  it is not the same GUID.
   ///
   UINT64            Revision;
@@ -126,5 +120,5 @@ struct _EFI_PXE_BASE_CODE_CALLBACK_PROTOCOL {
 
 extern EFI_GUID gEfiPxeBaseCodeCallbackProtocolGuid;
 
-#endif 
+#endif
 
diff --git a/MdePkg/Include/Protocol/RamDisk.h b/MdePkg/Include/Protocol/RamDisk.h
index 61353fbbd7c9..9861ec64e634 100644
--- a/MdePkg/Include/Protocol/RamDisk.h
+++ b/MdePkg/Include/Protocol/RamDisk.h
@@ -2,13 +2,7 @@
   This file defines the EFI RAM Disk Protocol.
 
   Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This Protocol is introduced in UEFI Specification 2.6
diff --git a/MdePkg/Include/Protocol/RealTimeClock.h b/MdePkg/Include/Protocol/RealTimeClock.h
index 7a70ae37a5aa..a80ffc305893 100644
--- a/MdePkg/Include/Protocol/RealTimeClock.h
+++ b/MdePkg/Include/Protocol/RealTimeClock.h
@@ -5,20 +5,14 @@
   Time and date related EFI runtime services.
 
   The GetTime (), SetTime (), GetWakeupTime (), and SetWakeupTime () UEFI 2.0
-  services are added to the EFI system table and the 
-  EFI_REAL_TIME_CLOCK_ARCH_PROTOCOL_GUID protocol is registered with a NULL 
+  services are added to the EFI system table and the
+  EFI_REAL_TIME_CLOCK_ARCH_PROTOCOL_GUID protocol is registered with a NULL
   pointer.
 
   No CRC of the EFI system table is required, since that is done in the DXE core.
 
-  Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/Protocol/RegularExpressionProtocol.h b/MdePkg/Include/Protocol/RegularExpressionProtocol.h
index 5582e12d36e8..4baf644b8bdd 100644
--- a/MdePkg/Include/Protocol/RegularExpressionProtocol.h
+++ b/MdePkg/Include/Protocol/RegularExpressionProtocol.h
@@ -2,14 +2,11 @@
   This section defines the Regular Expression Protocol. This protocol isused to match
   Unicode strings against Regular Expression patterns.
 
-Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under
-the terms and conditions of the BSD License that accompanies this distribution.
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2015-2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  This Protocol was introduced in UEFI Specification 2.5.
 
 **/
 
diff --git a/MdePkg/Include/Protocol/ReportStatusCodeHandler.h b/MdePkg/Include/Protocol/ReportStatusCodeHandler.h
index 5926e551d85c..7d2fceed55ce 100644
--- a/MdePkg/Include/Protocol/ReportStatusCodeHandler.h
+++ b/MdePkg/Include/Protocol/ReportStatusCodeHandler.h
@@ -1,15 +1,12 @@
 /** @file
-  This protocol provide registering and unregistering services to status code 
+  This protocol provide registering and unregistering services to status code
   consumers while in DXE.
-  
-  Copyright (c) 2007 - 2009, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  This Protocol was introduced in PI Specification 1.2.
 
 **/
 
@@ -33,7 +30,7 @@ EFI_STATUS
 
 /**
   Register the callback function for ReportStatusCode() notification.
-  
+
   When this function is called the function pointer is added to an internal list and any future calls to
   ReportStatusCode() will be forwarded to the Callback function. During the bootservices,
   this is the callback for which this service can be invoked. The report status code router
@@ -47,16 +44,16 @@ EFI_STATUS
   2. not unregister at exit boot services so that the router will still have its callback address
   3. the caller must be self-contained (eg. Not call out into any boot-service interfaces) and be
   runtime safe, in general.
-  
+
   @param[in] Callback   A pointer to a function of type EFI_RSC_HANDLER_CALLBACK that is called when
                         a call to ReportStatusCode() occurs.
-  @param[in] Tpl        TPL at which callback can be safely invoked.   
-  
+  @param[in] Tpl        TPL at which callback can be safely invoked.
+
   @retval  EFI_SUCCESS              Function was successfully registered.
   @retval  EFI_INVALID_PARAMETER    The callback function was NULL.
   @retval  EFI_OUT_OF_RESOURCES     The internal buffer ran out of space. No more functions can be
                                     registered.
-  @retval  EFI_ALREADY_STARTED      The function was already registered. It can't be registered again.                              
+  @retval  EFI_ALREADY_STARTED      The function was already registered. It can't be registered again.
 **/
 typedef
 EFI_STATUS
@@ -67,16 +64,16 @@ EFI_STATUS
 
 /**
   Remove a previously registered callback function from the notification list.
-  
+
   A callback function must be unregistered before it is deallocated. It is important that any registered
   callbacks that are not runtime complaint be unregistered when ExitBootServices() is called.
-  
+
   @param[in]  Callback  A pointer to a function of type EFI_RSC_HANDLER_CALLBACK that is to be
                         unregistered.
-                        
+
   @retval EFI_SUCCESS           The function was successfully unregistered.
   @retval EFI_INVALID_PARAMETER The callback function was NULL.
-  @retval EFI_NOT_FOUND         The callback function was not found to be unregistered.                        
+  @retval EFI_NOT_FOUND         The callback function was not found to be unregistered.
 **/
 typedef
 EFI_STATUS
diff --git a/MdePkg/Include/Protocol/Reset.h b/MdePkg/Include/Protocol/Reset.h
index bcd9329ba091..6b96b20f7247 100644
--- a/MdePkg/Include/Protocol/Reset.h
+++ b/MdePkg/Include/Protocol/Reset.h
@@ -3,17 +3,11 @@
 
   Used to provide ResetSystem runtime services
 
-  The ResetSystem () UEFI 2.0 service is added to the EFI system table and the 
+  The ResetSystem () UEFI 2.0 service is added to the EFI system table and the
   EFI_RESET_ARCH_PROTOCOL_GUID protocol is registered with a NULL pointer.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/Protocol/ResetNotification.h b/MdePkg/Include/Protocol/ResetNotification.h
new file mode 100644
index 000000000000..23cb6fac5b38
--- /dev/null
+++ b/MdePkg/Include/Protocol/ResetNotification.h
@@ -0,0 +1,80 @@
+/** @file
+  EFI Reset Notification Protocol as defined in UEFI 2.7.
+  This protocol provides services to register for a notification when ResetSystem is called.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  This Protocol is introduced in UEFI Specification 2.7
+
+**/
+
+#ifndef __EFI_RESET_NOTIFICATION_H__
+#define __EFI_RESET_NOTIFICATION_H__
+
+#define EFI_RESET_NOTIFICATION_PROTOCOL_GUID \
+  { 0x9da34ae0, 0xeaf9, 0x4bbf, { 0x8e, 0xc3, 0xfd, 0x60, 0x22, 0x6c, 0x44, 0xbe } }
+
+typedef struct _EFI_RESET_NOTIFICATION_PROTOCOL EFI_RESET_NOTIFICATION_PROTOCOL;
+
+/**
+  Register a notification function to be called when ResetSystem() is called.
+
+  The RegisterResetNotify() function registers a notification function that is called when
+  ResetSystem()is called and prior to completing the reset of the platform.
+  The registered functions must not perform a platform reset themselves. These
+  notifications are intended only for the notification of components which may need some
+  special-purpose maintenance prior to the platform resetting.
+  The list of registered reset notification functions are processed if ResetSystem()is called
+  before ExitBootServices(). The list of registered reset notification functions is ignored if
+  ResetSystem()is called after ExitBootServices().
+
+  @param[in]  This              A pointer to the EFI_RESET_NOTIFICATION_PROTOCOL instance.
+  @param[in]  ResetFunction     Points to the function to be called when a ResetSystem() is executed.
+
+  @retval EFI_SUCCESS           The reset notification function was successfully registered.
+  @retval EFI_INVALID_PARAMETER ResetFunction is NULL.
+  @retval EFI_OUT_OF_RESOURCES  There are not enough resources available to register the reset notification function.
+  @retval EFI_ALREADY_STARTED   The reset notification function specified by ResetFunction has already been registered.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_REGISTER_RESET_NOTIFY) (
+  IN EFI_RESET_NOTIFICATION_PROTOCOL *This,
+  IN EFI_RESET_SYSTEM                ResetFunction
+);
+
+/**
+  Unregister a notification function.
+
+  The UnregisterResetNotify() function removes the previously registered
+  notification using RegisterResetNotify().
+
+  @param[in]  This              A pointer to the EFI_RESET_NOTIFICATION_PROTOCOL instance.
+  @param[in]  ResetFunction     The pointer to the ResetFunction being unregistered.
+
+  @retval EFI_SUCCESS           The reset notification function was unregistered.
+  @retval EFI_INVALID_PARAMETER ResetFunction is NULL.
+  @retval EFI_INVALID_PARAMETER The reset notification function specified by ResetFunction was not previously
+                                registered using RegisterResetNotify().
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_UNREGISTER_RESET_NOTIFY) (
+  IN EFI_RESET_NOTIFICATION_PROTOCOL *This,
+  IN EFI_RESET_SYSTEM                ResetFunction
+);
+
+typedef struct _EFI_RESET_NOTIFICATION_PROTOCOL {
+  EFI_REGISTER_RESET_NOTIFY   RegisterResetNotify;
+  EFI_UNREGISTER_RESET_NOTIFY UnregisterResetNotify;
+} EFI_RESET_NOTIFICATION_PROTOCOL;
+
+
+extern EFI_GUID gEfiResetNotificationProtocolGuid;
+
+#endif
+
diff --git a/MdePkg/Include/Protocol/Rest.h b/MdePkg/Include/Protocol/Rest.h
index 512dd08ec230..57ab880667f9 100644
--- a/MdePkg/Include/Protocol/Rest.h
+++ b/MdePkg/Include/Protocol/Rest.h
@@ -2,13 +2,7 @@
   This file defines the EFI REST Protocol interface.
 
   Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution. The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This Protocol is introduced in UEFI Specification 2.5
diff --git a/MdePkg/Include/Protocol/Rng.h b/MdePkg/Include/Protocol/Rng.h
index 95cfdc95d7ce..2db8e9fdc50e 100644
--- a/MdePkg/Include/Protocol/Rng.h
+++ b/MdePkg/Include/Protocol/Rng.h
@@ -1,16 +1,10 @@
 /** @file
   EFI_RNG_PROTOCOL as defined in UEFI 2.4.
-  The UEFI Random Number Generator Protocol is used to provide random bits for use 
+  The UEFI Random Number Generator Protocol is used to provide random bits for use
   in applications, or entropy for seeding other random number generators.
 
-Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under
-the terms and conditions of the BSD License that accompanies this distribution.
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -29,7 +23,7 @@ typedef struct _EFI_RNG_PROTOCOL EFI_RNG_PROTOCOL;
 
 ///
 /// A selection of EFI_RNG_PROTOCOL algorithms.
-/// The algorithms listed are optional, not meant to be exhaustive and be argmented by 
+/// The algorithms listed are optional, not meant to be exhaustive and be argmented by
 /// vendors or other industry standards.
 ///
 
@@ -78,7 +72,7 @@ typedef EFI_GUID EFI_RNG_ALGORITHM;
   Returns information about the random number generation implementation.
 
   @param[in]     This                 A pointer to the EFI_RNG_PROTOCOL instance.
-  @param[in,out] RNGAlgorithmListSize On input, the size in bytes of RNGAlgorithmList. 
+  @param[in,out] RNGAlgorithmListSize On input, the size in bytes of RNGAlgorithmList.
                                       On output with a return code of EFI_SUCCESS, the size
                                       in bytes of the data returned in RNGAlgorithmList. On output
                                       with a return code of EFI_BUFFER_TOO_SMALL,
@@ -137,7 +131,7 @@ EFI_STATUS
   );
 
 ///
-/// The Random Number Generator (RNG) protocol provides random bits for use in 
+/// The Random Number Generator (RNG) protocol provides random bits for use in
 /// applications, or entropy for seeding other random number generators.
 ///
 struct _EFI_RNG_PROTOCOL {
diff --git a/MdePkg/Include/Protocol/Runtime.h b/MdePkg/Include/Protocol/Runtime.h
index 21e9b75fb756..4986a3979562 100644
--- a/MdePkg/Include/Protocol/Runtime.h
+++ b/MdePkg/Include/Protocol/Runtime.h
@@ -1,23 +1,17 @@
 /** @file
   Runtime Architectural Protocol as defined in PI Specification VOLUME 2 DXE
 
-  Allows the runtime functionality of the DXE Foundation to be contained 
-  in a separate driver. It also provides hooks for the DXE Foundation to 
-  export information that is needed at runtime. As such, this protocol allows 
-  services to the DXE Foundation to manage runtime drivers and events. 
-  This protocol also implies that the runtime services required to transition 
-  to virtual mode, SetVirtualAddressMap() and ConvertPointer(), have been 
-  registered into the UEFI Runtime Table in the UEFI System Table. This protocol 
+  Allows the runtime functionality of the DXE Foundation to be contained
+  in a separate driver. It also provides hooks for the DXE Foundation to
+  export information that is needed at runtime. As such, this protocol allows
+  services to the DXE Foundation to manage runtime drivers and events.
+  This protocol also implies that the runtime services required to transition
+  to virtual mode, SetVirtualAddressMap() and ConvertPointer(), have been
+  registered into the UEFI Runtime Table in the UEFI System Table. This protocol
   must be produced by a runtime DXE driver and may only be consumed by the DXE Foundation.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -33,7 +27,7 @@
 typedef struct _EFI_RUNTIME_ARCH_PROTOCOL  EFI_RUNTIME_ARCH_PROTOCOL;
 
 ///
-/// LIST_ENTRY from BaseType 
+/// LIST_ENTRY from BaseType
 ///
 typedef LIST_ENTRY EFI_LIST_ENTRY;
 
@@ -44,7 +38,7 @@ typedef struct _EFI_RUNTIME_IMAGE_ENTRY  EFI_RUNTIME_IMAGE_ENTRY;
 ///
 struct _EFI_RUNTIME_IMAGE_ENTRY {
   ///
-  /// Start of image that has been loaded in memory. It is a pointer 
+  /// Start of image that has been loaded in memory. It is a pointer
   /// to either the DOS header or PE header of the image.
   ///
   VOID                    *ImageBase;
@@ -101,13 +95,13 @@ struct _EFI_RUNTIME_EVENT_ENTRY {
 };
 
 ///
-/// Allows the runtime functionality of the DXE Foundation to be contained in a 
-/// separate driver. It also provides hooks for the DXE Foundation to export 
-/// information that is needed at runtime. As such, this protocol allows the DXE 
-/// Foundation to manage runtime drivers and events. This protocol also implies 
-/// that the runtime services required to transition to virtual mode, 
-/// SetVirtualAddressMap() and ConvertPointer(), have been registered into the 
-/// EFI Runtime Table in the EFI System Partition.  This protocol must be produced 
+/// Allows the runtime functionality of the DXE Foundation to be contained in a
+/// separate driver. It also provides hooks for the DXE Foundation to export
+/// information that is needed at runtime. As such, this protocol allows the DXE
+/// Foundation to manage runtime drivers and events. This protocol also implies
+/// that the runtime services required to transition to virtual mode,
+/// SetVirtualAddressMap() and ConvertPointer(), have been registered into the
+/// EFI Runtime Table in the EFI System Partition.  This protocol must be produced
 /// by a runtime DXE driver and may only be consumed by the DXE Foundation.
 ///
 struct _EFI_RUNTIME_ARCH_PROTOCOL {
@@ -115,8 +109,8 @@ struct _EFI_RUNTIME_ARCH_PROTOCOL {
   EFI_LIST_ENTRY          EventHead;    ///< A list of type EFI_RUNTIME_EVENT_ENTRY.
   UINTN                   MemoryDescriptorSize;   ///< Size of a memory descriptor that is returned by GetMemoryMap().
   UINT32                  MemoryDesciptorVersion; ///< Version of a memory descriptor that is returned by GetMemoryMap().
-  UINTN                   MemoryMapSize;///< Size of the memory map in bytes contained in MemoryMapPhysical and MemoryMapVirtual. 
-  EFI_MEMORY_DESCRIPTOR   *MemoryMapPhysical;     ///< Pointer to a runtime buffer that contains a copy of 
+  UINTN                   MemoryMapSize;///< Size of the memory map in bytes contained in MemoryMapPhysical and MemoryMapVirtual.
+  EFI_MEMORY_DESCRIPTOR   *MemoryMapPhysical;     ///< Pointer to a runtime buffer that contains a copy of
                                                   ///< the memory map returned via GetMemoryMap().
   EFI_MEMORY_DESCRIPTOR   *MemoryMapVirtual;      ///< Pointer to MemoryMapPhysical that is updated to virtual mode after SetVirtualAddressMap().
   BOOLEAN                 VirtualMode;  ///< Boolean that is TRUE if SetVirtualAddressMap() has been called.
diff --git a/MdePkg/Include/Protocol/S3SaveState.h b/MdePkg/Include/Protocol/S3SaveState.h
index c25e103f7692..7e7d5cadfd21 100644
--- a/MdePkg/Include/Protocol/S3SaveState.h
+++ b/MdePkg/Include/Protocol/S3SaveState.h
@@ -1,21 +1,15 @@
 /** @file
-  S3 Save State Protocol as defined in PI1.2 Specification VOLUME 5 Standard.
+  S3 Save State Protocol as defined in PI 1.6(Errata A) Specification VOLUME 5 Standard.
 
-  This protocol is used by DXE PI module to store or record various IO operations 
+  This protocol is used by DXE PI module to store or record various IO operations
   to be replayed during an S3 resume.
   This protocol is not required for all platforms.
-  
-  Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2009 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
-  This PPI is defined in UEFI Platform Initialization Specification 1.2 Volume 5: 
+  This PPI is defined in UEFI Platform Initialization Specification 1.2 Volume 5:
   Standards
 
 **/
@@ -33,32 +27,32 @@ typedef struct _EFI_S3_SAVE_STATE_PROTOCOL  EFI_S3_SAVE_STATE_PROTOCOL;
 
 /**
   Record operations that need to be replayed during an S3 resume.
-  
+
   This function is used to store an OpCode to be replayed as part of the S3 resume boot path. It is
   assumed this protocol has platform specific mechanism to store the OpCode set and replay them
   during the S3 resume.
-  
+
   @param[in]    This    A pointer to the EFI_S3_SAVE_STATE_PROTOCOL instance.
   @param[in]    OpCode  The operation code (opcode) number.
   @param[in]    ...     Argument list that is specific to each opcode. See the following subsections for the
                         definition of each opcode.
-                        
+
   @retval EFI_SUCCESS           The operation succeeded. A record was added into the specified
-                                script table.                    
+                                script table.
   @retval EFI_INVALID_PARAMETER The parameter is illegal or the given boot script is not supported.
-  @retval EFI_OUT_OF_RESOURCES  There is insufficient memory to store the boot script.                       
+  @retval EFI_OUT_OF_RESOURCES  There is insufficient memory to store the boot script.
 **/
 typedef
 EFI_STATUS
 (EFIAPI *EFI_S3_SAVE_STATE_WRITE)(
    IN CONST EFI_S3_SAVE_STATE_PROTOCOL  *This,
-   IN       UINT16                      OpCode,
+   IN       UINTN                       OpCode,
    ...
 );
 
 /**
   Record operations that need to be replayed during an S3 resume.
-  
+
   This function is used to store an OpCode to be replayed as part of the S3 resume boot path. It is
   assumed this protocol has platform specific mechanism to store the OpCode set and replay them
   during the S3 resume.
@@ -66,14 +60,14 @@ EFI_STATUS
   NULL then that position is after the last opcode in the table (BeforeOrAfter is TRUE) or before
   the first opcode in the table (BeforeOrAfter is FALSE). The position which is pointed to by
   Position upon return can be used for subsequent insertions.
-  
+
   This function has a variable parameter list. The exact parameter list depends on the OpCode that is
   passed into the function. If an unsupported OpCode or illegal parameter list is passed in, this
   function returns EFI_INVALID_PARAMETER.
   If there are not enough resources available for storing more scripts, this function returns
   EFI_OUT_OF_RESOURCES.
   OpCode values of 0x80 - 0xFE are reserved for implementation specific functions.
-  
+
   @param[in]        This            A pointer to the EFI_S3_SAVE_STATE_PROTOCOL instance.
   @param[in]        BeforeOrAfter   Specifies whether the opcode is stored before (TRUE) or after (FALSE) the position
                                     in the boot script table specified by Position. If Position is NULL or points to
@@ -85,12 +79,12 @@ EFI_STATUS
   @param[in]        OpCode          The operation code (opcode) number. See "Related Definitions" in Write() for the
                                     defined opcode types.
   @param[in]        ...             Argument list that is specific to each opcode. See the following subsections for the
-                                    definition of each opcode. 
-                                    
+                                    definition of each opcode.
+
   @retval EFI_SUCCESS               The operation succeeded. An opcode was added into the script.
   @retval EFI_INVALID_PARAMETER     The Opcode is an invalid opcode value.
   @retval EFI_INVALID_PARAMETER     The Position is not a valid position in the boot script table.
-  @retval EFI_OUT_OF_RESOURCES      There is insufficient memory to store the boot script table.                                                                       
+  @retval EFI_OUT_OF_RESOURCES      There is insufficient memory to store the boot script table.
 **/
 typedef
 EFI_STATUS
@@ -98,20 +92,20 @@ EFI_STATUS
    IN CONST EFI_S3_SAVE_STATE_PROTOCOL  *This,
    IN       BOOLEAN                     BeforeOrAfter,
    IN OUT   EFI_S3_BOOT_SCRIPT_POSITION *Position       OPTIONAL,
-   IN       UINT16                      OpCode,
+   IN       UINTN                       OpCode,
    ...
 );
 
 /**
   Find a label within the boot script table and, if not present, optionally create it.
-  
+
   If the label Label is already exists in the boot script table, then no new label is created, the
   position of the Label is returned in *Position and EFI_SUCCESS is returned.
   If the label Label does not already exist and CreateIfNotFound is TRUE, then it will be
   created before or after the specified position and EFI_SUCCESS is returned.
   If the label Label does not already exist and CreateIfNotFound is FALSE, then
   EFI_NOT_FOUND is returned.
-  
+
   @param[in]      This                A pointer to the EFI_S3_SAVE_STATE_PROTOCOL instance.
   @param[in]      BeforeOrAfter       Specifies whether the label is stored before (TRUE) or after (FALSE) the position in
                                       the boot script table specified by Position. If Position is NULL or points to
@@ -122,7 +116,7 @@ EFI_STATUS
                                       either before or after, depending on BeforeOrAfter. On exit, specifies the position
                                       of the inserted label in the boot script table.
   @param[in]      Label               Points to the label which will be inserted in the boot script table.
-  
+
   @retval    EFI_SUCCESS              The label already exists or was inserted.
   @retval    EFI_NOT_FOUND            The label did not already exist and CreateifNotFound was FALSE.
   @retval    EFI_INVALID_PARAMETER    The Label is NULL or points to an empty string.
@@ -141,16 +135,16 @@ EFI_STATUS
 
 /**
   Compare two positions in the boot script table and return their relative position.
-  
+
   This function compares two positions in the boot script table and returns their relative positions. If
   Position1 is before Position2, then -1 is returned. If Position1 is equal to Position2,
   then 0 is returned. If Position1 is after Position2, then 1 is returned.
-  
+
   @param[in]    This                A pointer to the EFI_S3_SAVE_STATE_PROTOCOL instance.
   @param[in]    Position1           The positions in the boot script table to compare.
   @param[in]    Position2           The positions in the boot script table to compare.
   @param[out]   RelativePosition    On return, points to the result of the comparison.
-  
+
   @retval   EFI_SUCCESS             The operation succeeded.
   @retval   EFI_INVALID_PARAMETER   The Position1 or Position2 is not a valid position in the boot script table.
   @retval   EFI_INVALID_PARAMETER   The RelativePosition is NULL.
diff --git a/MdePkg/Include/Protocol/S3SmmSaveState.h b/MdePkg/Include/Protocol/S3SmmSaveState.h
index 3cdfec7a1701..07f82db05035 100644
--- a/MdePkg/Include/Protocol/S3SmmSaveState.h
+++ b/MdePkg/Include/Protocol/S3SmmSaveState.h
@@ -13,19 +13,13 @@
   EFI_OUT_OF_RESOURCES may be returned from a runtime call. It is the responsibility of the
   platform to ensure enough memory resource exists to save the system state. It is recommended that
   runtime calls be minimized by the caller.
-  
-  Copyright (c) 2009, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.   
+  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
-  This PPI is defined in UEFI Platform Initialization Specification 1.2 Volume 5: 
-  Standards          
+  This PPI is defined in UEFI Platform Initialization Specification 1.2 Volume 5:
+  Standards
 
 **/
 
@@ -36,11 +30,11 @@
 
 #define EFI_S3_SMM_SAVE_STATE_PROTOCOL_GUID \
     {0x320afe62, 0xe593, 0x49cb, { 0xa9, 0xf1, 0xd4, 0xc2, 0xf4, 0xaf, 0x1, 0x4c }}
-    
+
 
 typedef EFI_S3_SAVE_STATE_PROTOCOL EFI_S3_SMM_SAVE_STATE_PROTOCOL;
 
 extern EFI_GUID gEfiS3SmmSaveStateProtocolGuid;
-    
+
 #endif // __S3_SMM_SAVE_STATE_H__
 
diff --git a/MdePkg/Include/Protocol/ScsiIo.h b/MdePkg/Include/Protocol/ScsiIo.h
index 833fb1ceeffa..d3db297a97db 100644
--- a/MdePkg/Include/Protocol/ScsiIo.h
+++ b/MdePkg/Include/Protocol/ScsiIo.h
@@ -1,17 +1,11 @@
 /** @file
   EFI_SCSI_IO_PROTOCOL as defined in UEFI 2.0.
-  This protocol is used by code, typically drivers, running in the EFI boot 
-  services environment to access SCSI devices. In particular, functions for 
+  This protocol is used by code, typically drivers, running in the EFI boot
+  services environment to access SCSI devices. In particular, functions for
   managing devices on SCSI buses are defined here.
 
-  Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -301,12 +295,12 @@ struct _EFI_SCSI_IO_PROTOCOL {
   EFI_SCSI_IO_PROTOCOL_GET_DEVICE_LOCATION  GetDeviceLocation;
   EFI_SCSI_IO_PROTOCOL_RESET_BUS            ResetBus;
   EFI_SCSI_IO_PROTOCOL_RESET_DEVICE         ResetDevice;
-  EFI_SCSI_IO_PROTOCOL_EXEC_SCSI_COMMAND    ExecuteScsiCommand;    
+  EFI_SCSI_IO_PROTOCOL_EXEC_SCSI_COMMAND    ExecuteScsiCommand;
 
   ///
-  /// Supplies the alignment requirement for any buffer used in a data transfer. 
-  /// IoAlign values of 0 and 1 mean that the buffer can be placed anywhere in memory. 
-  /// Otherwise, IoAlign must be a power of 2, and the requirement is that the 
+  /// Supplies the alignment requirement for any buffer used in a data transfer.
+  /// IoAlign values of 0 and 1 mean that the buffer can be placed anywhere in memory.
+  /// Otherwise, IoAlign must be a power of 2, and the requirement is that the
   /// start address of a buffer must be evenly divisible by IoAlign with no remainder.
   ///
   UINT32                                    IoAlign;
diff --git a/MdePkg/Include/Protocol/ScsiPassThru.h b/MdePkg/Include/Protocol/ScsiPassThru.h
index baf0d2bfc7fe..1666b248e76d 100644
--- a/MdePkg/Include/Protocol/ScsiPassThru.h
+++ b/MdePkg/Include/Protocol/ScsiPassThru.h
@@ -1,21 +1,15 @@
 /** @file
   SCSI Pass Through protocol as defined in EFI 1.1.
-  This protocol allows information about a SCSI channel to be collected, 
+  This protocol allows information about a SCSI channel to be collected,
   and allows SCSI Request Packets to be sent to any SCSI devices on a SCSI
-  channel even if those devices are not boot devices. This protocol is attached 
-  to the device handle of each SCSI channel in a system that the protocol 
-  supports, and can be used for diagnostics. It may also be used to build 
+  channel even if those devices are not boot devices. This protocol is attached
+  to the device handle of each SCSI channel in a system that the protocol
+  supports, and can be used for diagnostics. It may also be used to build
   a Block I/O driver for SCSI hard drives and SCSI CD-ROM or DVD drives to
   allow those devices to become boot devices.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -149,9 +143,9 @@ typedef struct {
 } EFI_SCSI_PASS_THRU_MODE;
 
 /**
-  Sends a SCSI Request Packet to a SCSI device that is attached to 
-  the SCSI channel. This function supports both blocking I/O and 
-  non-blocking I/O.  The blocking I/O functionality is required, 
+  Sends a SCSI Request Packet to a SCSI device that is attached to
+  the SCSI channel. This function supports both blocking I/O and
+  non-blocking I/O.  The blocking I/O functionality is required,
   and the non-blocking I/O functionality is optional.
 
   @param  This   Protocol instance pointer.
@@ -198,7 +192,7 @@ typedef struct {
                                     Request Packet to execute. See HostAdapterStatus,
                                     TargetStatus, SenseDataLength, and SenseData in
                                     that order for additional status information.
-                                    
+
 **/
 typedef
 EFI_STATUS
@@ -211,7 +205,7 @@ EFI_STATUS
   );
 
 /**
-  Used to retrieve the list of legal Target IDs for SCSI devices 
+  Used to retrieve the list of legal Target IDs for SCSI devices
   on a SCSI channel.
 
   @param  This   Protocol instance pointer.
@@ -243,7 +237,7 @@ EFI_STATUS
   );
 
 /**
-  Used to allocate and build a device path node for a SCSI device 
+  Used to allocate and build a device path node for a SCSI device
   on a SCSI channel.
 
   @param  This       Protocol instance pointer.
@@ -311,7 +305,7 @@ EFI_STATUS
   );
 
 /**
-  Resets a SCSI channel.This operation resets all the 
+  Resets a SCSI channel.This operation resets all the
   SCSI devices connected to the SCSI channel.
 
   @param  This Protocol instance pointer.
diff --git a/MdePkg/Include/Protocol/ScsiPassThruExt.h b/MdePkg/Include/Protocol/ScsiPassThruExt.h
index a9d4047e0e7a..49e16feb1a4e 100644
--- a/MdePkg/Include/Protocol/ScsiPassThruExt.h
+++ b/MdePkg/Include/Protocol/ScsiPassThruExt.h
@@ -1,16 +1,10 @@
 /** @file
   EFI_EXT_SCSI_PASS_THRU_PROTOCOL as defined in UEFI 2.0.
-  This protocol provides services that allow SCSI Pass Thru commands 
+  This protocol provides services that allow SCSI Pass Thru commands
   to be sent to SCSI devices attached to a SCSI channel.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -148,9 +142,9 @@ typedef struct {
 } EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET;
 
 /**
-  Sends a SCSI Request Packet to a SCSI device that is attached to the SCSI channel. This function   
+  Sends a SCSI Request Packet to a SCSI device that is attached to the SCSI channel. This function
   supports both blocking I/O and nonblocking I/O. The blocking I/O functionality is required, and the
-  nonblocking I/O functionality is optional.                                                             
+  nonblocking I/O functionality is optional.
 
   @param  This    A pointer to the EFI_EXT_SCSI_PASS_THRU_PROTOCOL instance.
   @param  Target  The Target is an array of size TARGET_MAX_BYTES and it represents
@@ -196,14 +190,14 @@ EFI_STATUS
   IN UINT64                                         Lun,
   IN OUT EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET *Packet,
   IN EFI_EVENT                                      Event     OPTIONAL
-  );      
+  );
 
 /**
-  Used to retrieve the list of legal Target IDs and LUNs for SCSI devices on a SCSI channel. These       
+  Used to retrieve the list of legal Target IDs and LUNs for SCSI devices on a SCSI channel. These
   can either be the list SCSI devices that are actually present on the SCSI channel, or the list of legal
-  Target Ids and LUNs for the SCSI channel. Regardless, the caller of this function must probe the       
-  Target ID and LUN returned to see if a SCSI device is actually present at that location on the SCSI    
-  channel.                                                                                               
+  Target Ids and LUNs for the SCSI channel. Regardless, the caller of this function must probe the
+  Target ID and LUN returned to see if a SCSI device is actually present at that location on the SCSI
+  channel.
 
   @param  This   A pointer to the EFI_EXT_SCSI_PASS_THRU_PROTOCOL instance.
   @param  Target On input, a pointer to the Target ID (an array of size
@@ -230,7 +224,7 @@ EFI_STATUS
   IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL                *This,
   IN OUT UINT8                                      **Target,
   IN OUT UINT64                                     *Lun
-  );   
+  );
 
 /**
   Used to allocate and build a device path node for a SCSI device on a SCSI channel.
@@ -265,7 +259,7 @@ EFI_STATUS
   IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL               *This,
   IN UINT8                                         *Target,
   IN UINT64                                        Lun,
-  IN OUT EFI_DEVICE_PATH_PROTOCOL                  **DevicePath
+  OUT EFI_DEVICE_PATH_PROTOCOL                     **DevicePath
   );
 
 /**
@@ -294,7 +288,7 @@ EFI_STATUS
   IN EFI_DEVICE_PATH_PROTOCOL                      *DevicePath,
   OUT UINT8                                        **Target,
   OUT UINT64                                       *Lun
-  );       
+  );
 
 /**
   Resets a SCSI channel. This operation resets all the SCSI devices connected to the SCSI channel.
@@ -311,8 +305,8 @@ typedef
 EFI_STATUS
 (EFIAPI *EFI_EXT_SCSI_PASS_THRU_RESET_CHANNEL)(
   IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL               *This
-  );    
-  
+  );
+
 /**
   Resets a SCSI logical unit that is connected to a SCSI channel.
 
@@ -338,13 +332,13 @@ EFI_STATUS
   IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL               *This,
   IN UINT8                                         *Target,
   IN UINT64                                        Lun
-  );         
+  );
 
 /**
-  Used to retrieve the list of legal Target IDs for SCSI devices on a SCSI channel. These can either     
+  Used to retrieve the list of legal Target IDs for SCSI devices on a SCSI channel. These can either
   be the list SCSI devices that are actually present on the SCSI channel, or the list of legal Target IDs
-  for the SCSI channel. Regardless, the caller of this function must probe the Target ID returned to     
-  see if a SCSI device is actually present at that location on the SCSI channel.                         
+  for the SCSI channel. Regardless, the caller of this function must probe the Target ID returned to
+  see if a SCSI device is actually present at that location on the SCSI channel.
 
   @param  This   A pointer to the EFI_EXT_SCSI_PASS_THRU_PROTOCOL instance.
   @param  Target (TARGET_MAX_BYTES) of a SCSI device present on the SCSI channel.
@@ -367,12 +361,12 @@ EFI_STATUS
 (EFIAPI *EFI_EXT_SCSI_PASS_THRU_GET_NEXT_TARGET)(
   IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL               *This,
   IN OUT UINT8                                     **Target
-  );          
+  );
 
 ///
-/// The EFI_EXT_SCSI_PASS_THRU_PROTOCOL provides information about a SCSI channel 
-/// and the ability to send SCI Request Packets to any SCSI device attached to 
-/// that SCSI channel. The information includes the Target ID of the host controller 
+/// The EFI_EXT_SCSI_PASS_THRU_PROTOCOL provides information about a SCSI channel
+/// and the ability to send SCI Request Packets to any SCSI device attached to
+/// that SCSI channel. The information includes the Target ID of the host controller
 /// on the SCSI channel and the attributes of the SCSI channel.
 ///
 struct _EFI_EXT_SCSI_PASS_THRU_PROTOCOL {
diff --git a/MdePkg/Include/Protocol/SdMmcPassThru.h b/MdePkg/Include/Protocol/SdMmcPassThru.h
index ddbf45632cc5..4135a3ba9e51 100644
--- a/MdePkg/Include/Protocol/SdMmcPassThru.h
+++ b/MdePkg/Include/Protocol/SdMmcPassThru.h
@@ -3,13 +3,7 @@
   to any SD/MMC device attached to the SD compatible pci host controller.
 
   Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -170,7 +164,7 @@ EFI_STATUS
   @param[in]     This           A pointer to the EFI_SD_MMMC_PASS_THRU_PROTOCOL instance.
   @param[in]     Slot           Specifies the slot number of the SD card for which a device
                                 path node is to be allocated and built.
-  @param[in,out] DevicePath     A pointer to a single device path node that describes the SD
+  @param[out]    DevicePath     A pointer to a single device path node that describes the SD
                                 card specified by Slot. This function is responsible for
                                 allocating the buffer DevicePath with the boot service
                                 AllocatePool(). It is the caller's responsibility to free
@@ -188,7 +182,7 @@ EFI_STATUS
 (EFIAPI *EFI_SD_MMC_PASS_THRU_BUILD_DEVICE_PATH) (
   IN     EFI_SD_MMC_PASS_THRU_PROTOCOL       *This,
   IN     UINT8                               Slot,
-  IN OUT EFI_DEVICE_PATH_PROTOCOL            **DevicePath
+  OUT    EFI_DEVICE_PATH_PROTOCOL            **DevicePath
 );
 
 /**
diff --git a/MdePkg/Include/Protocol/Security.h b/MdePkg/Include/Protocol/Security.h
index 54c51fa43209..392db311aeab 100644
--- a/MdePkg/Include/Protocol/Security.h
+++ b/MdePkg/Include/Protocol/Security.h
@@ -1,9 +1,9 @@
 /** @file
   Security Architectural Protocol as defined in PI Specification VOLUME 2 DXE
 
-  Used to provide Security services.  Specifically, dependening upon the 
-  authentication state of a discovered driver in a Firmware Volume, the 
-  portable DXE Core Dispatcher will call into the Security Architectural 
+  Used to provide Security services.  Specifically, dependening upon the
+  authentication state of a discovered driver in a Firmware Volume, the
+  portable DXE Core Dispatcher will call into the Security Architectural
   Protocol (SAP) with the authentication state of the driver.
 
   This call-out allows for OEM-specific policy decisions to be made, such
@@ -11,17 +11,11 @@
   an unsigned driver or failed signature check, or other exception response.
 
   The SAP can also change system behavior by having the DXE core put a driver
-  in the Schedule-On-Request (SOR) state.  This will allow for later disposition 
+  in the Schedule-On-Request (SOR) state.  This will allow for later disposition
   of the driver by platform agent, such as Platform BDS.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -37,31 +31,31 @@
 typedef struct _EFI_SECURITY_ARCH_PROTOCOL    EFI_SECURITY_ARCH_PROTOCOL;
 
 /**
-  The EFI_SECURITY_ARCH_PROTOCOL (SAP) is used to abstract platform-specific 
-  policy from the DXE core response to an attempt to use a file that returns a 
-  given status for the authentication check from the section extraction protocol.  
+  The EFI_SECURITY_ARCH_PROTOCOL (SAP) is used to abstract platform-specific
+  policy from the DXE core response to an attempt to use a file that returns a
+  given status for the authentication check from the section extraction protocol.
 
-  The possible responses in a given SAP implementation may include locking 
-  flash upon failure to authenticate, attestation logging for all signed drivers, 
-  and other exception operations.  The File parameter allows for possible logging 
+  The possible responses in a given SAP implementation may include locking
+  flash upon failure to authenticate, attestation logging for all signed drivers,
+  and other exception operations.  The File parameter allows for possible logging
   within the SAP of the driver.
 
   If File is NULL, then EFI_INVALID_PARAMETER is returned.
 
-  If the file specified by File with an authentication status specified by 
+  If the file specified by File with an authentication status specified by
   AuthenticationStatus is safe for the DXE Core to use, then EFI_SUCCESS is returned.
 
-  If the file specified by File with an authentication status specified by 
-  AuthenticationStatus is not safe for the DXE Core to use under any circumstances, 
+  If the file specified by File with an authentication status specified by
+  AuthenticationStatus is not safe for the DXE Core to use under any circumstances,
   then EFI_ACCESS_DENIED is returned.
 
-  If the file specified by File with an authentication status specified by 
-  AuthenticationStatus is not safe for the DXE Core to use right now, but it 
-  might be possible to use it at a future time, then EFI_SECURITY_VIOLATION is 
+  If the file specified by File with an authentication status specified by
+  AuthenticationStatus is not safe for the DXE Core to use right now, but it
+  might be possible to use it at a future time, then EFI_SECURITY_VIOLATION is
   returned.
 
   @param  This             The EFI_SECURITY_ARCH_PROTOCOL instance.
-  @param  AuthenticationStatus 
+  @param  AuthenticationStatus
                            This is the authentication type returned from the Section
                            Extraction protocol. See the Section Extraction Protocol
                            Specification for details on this type.
@@ -81,7 +75,7 @@ typedef struct _EFI_SECURITY_ARCH_PROTOCOL    EFI_SECURITY_ARCH_PROTOCOL;
                                 used for any purpose.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_SECURITY_FILE_AUTHENTICATION_STATE)(
   IN  CONST EFI_SECURITY_ARCH_PROTOCOL *This,
@@ -91,7 +85,7 @@ EFI_STATUS
 
 ///
 /// The EFI_SECURITY_ARCH_PROTOCOL is used to abstract platform-specific policy
-/// from the DXE core.  This includes locking flash upon failure to authenticate, 
+/// from the DXE core.  This includes locking flash upon failure to authenticate,
 /// attestation logging, and other exception operations.
 ///
 struct _EFI_SECURITY_ARCH_PROTOCOL {
diff --git a/MdePkg/Include/Protocol/Security2.h b/MdePkg/Include/Protocol/Security2.h
index a8d79156907c..95c5dc1b3a81 100644
--- a/MdePkg/Include/Protocol/Security2.h
+++ b/MdePkg/Include/Protocol/Security2.h
@@ -4,27 +4,21 @@
   Abstracts security-specific functions from the DXE Foundation of UEFI Image Verification,
   Trusted Computing Group (TCG) measured boot, and User Identity policy for image loading and
   consoles. This protocol must be produced by a boot service or runtime DXE driver.
-  
+
   This protocol is optional and must be published prior to the EFI_SECURITY_ARCH_PROTOCOL.
   As a result, the same driver must publish both of these interfaces.
-  
+
   When both Security and Security2 Architectural Protocols are published, LoadImage must use
   them in accordance with the following rules:
     The Security2 protocol must be used on every image being loaded.
-    The Security protocol must be used after the Securiy2 protocol and only on images that 
+    The Security protocol must be used after the Securiy2 protocol and only on images that
     have been read using Firmware Volume protocol.
 
   When only Security architectural protocol is published, LoadImage must use it on every image
   being loaded.
 
-  Copyright (c) 2012, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -36,7 +30,7 @@
 ///
 #define EFI_SECURITY2_ARCH_PROTOCOL_GUID \
   { 0x94ab2f58, 0x1438, 0x4ef1, {0x91, 0x52, 0x18, 0x94, 0x1a, 0x3a, 0x0e, 0x68 } }
-  
+
 typedef struct _EFI_SECURITY2_ARCH_PROTOCOL    EFI_SECURITY2_ARCH_PROTOCOL;
 
 /**
@@ -51,7 +45,7 @@ typedef struct _EFI_SECURITY2_ARCH_PROTOCOL    EFI_SECURITY2_ARCH_PROTOCOL;
   these cases.
   If the FileBuffer is NULL, the interface will determine if the DevicePath can be connected
   in order to support the User Identification policy.
-  
+
   @param  This             The EFI_SECURITY2_ARCH_PROTOCOL instance.
   @param  File             A pointer to the device path of the file that is
                            being dispatched. This will optionally be used for logging.
@@ -60,7 +54,7 @@ typedef struct _EFI_SECURITY2_ARCH_PROTOCOL    EFI_SECURITY2_ARCH_PROTOCOL;
   @param  BootPolicy       A boot policy that was used to call LoadImage() UEFI service. If
                            FileAuthentication() is invoked not from the LoadImage(),
                            BootPolicy must be set to FALSE.
-  
+
   @retval EFI_SUCCESS             The file specified by DevicePath and non-NULL
                                   FileBuffer did authenticate, and the platform policy dictates
                                   that the DXE Foundation may use the file.
@@ -84,9 +78,9 @@ typedef struct _EFI_SECURITY2_ARCH_PROTOCOL    EFI_SECURITY2_ARCH_PROTOCOL;
                                   drivers from the device path specified by DevicePath. The
                                   image has been added into the list of the deferred images.
 **/
-typedef EFI_STATUS (EFIAPI *EFI_SECURITY2_FILE_AUTHENTICATION) (  
+typedef EFI_STATUS (EFIAPI *EFI_SECURITY2_FILE_AUTHENTICATION) (
   IN CONST EFI_SECURITY2_ARCH_PROTOCOL *This,
-  IN CONST EFI_DEVICE_PATH_PROTOCOL    *DevicePath,
+  IN CONST EFI_DEVICE_PATH_PROTOCOL    *File, OPTIONAL
   IN VOID                              *FileBuffer,
   IN UINTN                             FileSize,
   IN BOOLEAN                           BootPolicy
diff --git a/MdePkg/Include/Protocol/SecurityPolicy.h b/MdePkg/Include/Protocol/SecurityPolicy.h
index ceff5ac22752..d36e588d8734 100644
--- a/MdePkg/Include/Protocol/SecurityPolicy.h
+++ b/MdePkg/Include/Protocol/SecurityPolicy.h
@@ -1,14 +1,8 @@
 /** @file
   Security Policy protocol as defined in PI Specification VOLUME 2 DXE
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/Protocol/SerialIo.h b/MdePkg/Include/Protocol/SerialIo.h
index 8371f42b2ec9..8d788306e54e 100644
--- a/MdePkg/Include/Protocol/SerialIo.h
+++ b/MdePkg/Include/Protocol/SerialIo.h
@@ -4,14 +4,8 @@
   Abstraction of a basic serial device. Targeted at 16550 UART, but
   could be much more generic.
 
-  Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -25,7 +19,7 @@
 
 ///
 /// Protocol GUID defined in EFI1.1.
-/// 
+///
 #define SERIAL_IO_PROTOCOL  EFI_SERIAL_IO_PROTOCOL_GUID
 
 typedef struct _EFI_SERIAL_IO_PROTOCOL EFI_SERIAL_IO_PROTOCOL;
@@ -33,7 +27,7 @@ typedef struct _EFI_SERIAL_IO_PROTOCOL EFI_SERIAL_IO_PROTOCOL;
 
 ///
 /// Backward-compatible with EFI1.1.
-/// 
+///
 typedef EFI_SERIAL_IO_PROTOCOL  SERIAL_IO_INTERFACE;
 
 ///
@@ -92,7 +86,7 @@ typedef enum {
   Reset the serial device.
 
   @param  This              Protocol instance pointer.
-                            
+
   @retval EFI_SUCCESS       The device was reset.
   @retval EFI_DEVICE_ERROR  The serial device could not be reset.
 
@@ -104,7 +98,7 @@ EFI_STATUS
   );
 
 /**
-  Sets the baud rate, receive FIFO depth, transmit/receice time out, parity, 
+  Sets the baud rate, receive FIFO depth, transmit/receice time out, parity,
   data bits, and stop bits on a serial device.
 
   @param  This             Protocol instance pointer.
@@ -125,8 +119,9 @@ EFI_STATUS
                            value of DefaultStopBits will use the device's default number of
                            stop bits.
 
-  @retval EFI_SUCCESS      The device was reset.
-  @retval EFI_DEVICE_ERROR The serial device could not be reset.
+  @retval EFI_SUCCESS           The device was reset.
+  @retval EFI_INVALID_PARAMETER One or more attributes has an unsupported value.
+  @retval EFI_DEVICE_ERROR      The serial device is not functioning correctly.
 
 **/
 typedef
@@ -164,7 +159,7 @@ EFI_STATUS
 
   @param  This              Protocol instance pointer.
   @param  Control           A pointer to return the current Control signals from the serial device.
-                            
+
   @retval EFI_SUCCESS       The control bits were read from the serial device.
   @retval EFI_DEVICE_ERROR  The serial device is not functioning correctly.
 
@@ -220,33 +215,33 @@ EFI_STATUS
 
 /**
   @par Data Structure Description:
-  The data values in SERIAL_IO_MODE are read-only and are updated by the code 
+  The data values in SERIAL_IO_MODE are read-only and are updated by the code
   that produces the SERIAL_IO_PROTOCOL member functions.
 
   @param ControlMask
   A mask for the Control bits that the device supports. The device
   must always support the Input Buffer Empty control bit.
-  
+
   @param TimeOut
   If applicable, the number of microseconds to wait before timing out
   a Read or Write operation.
-  
+
   @param BaudRate
   If applicable, the current baud rate setting of the device; otherwise,
   baud rate has the value of zero to indicate that device runs at the
   device's designed speed.
-  
+
   @param ReceiveFifoDepth
   The number of characters the device will buffer on input
-  
+
   @param DataBits
   The number of characters the device will buffer on input
-  
+
   @param Parity
-  If applicable, this is the EFI_PARITY_TYPE that is computed or 
+  If applicable, this is the EFI_PARITY_TYPE that is computed or
   checked as each character is transmitted or reveived. If the device
   does not support parity the value is the default parity value.
-  
+
   @param StopBits
   If applicable, the EFI_STOP_BITS_TYPE number of stop bits per
   character. If the device does not support stop bits the value is
@@ -268,17 +263,18 @@ typedef struct {
 } EFI_SERIAL_IO_MODE;
 
 #define EFI_SERIAL_IO_PROTOCOL_REVISION    0x00010000
+#define EFI_SERIAL_IO_PROTOCOL_REVISION1p1 0x00010001
 #define SERIAL_IO_INTERFACE_REVISION  EFI_SERIAL_IO_PROTOCOL_REVISION
 
 ///
-/// The Serial I/O protocol is used to communicate with UART-style serial devices. 
-/// These can be standard UART serial ports in PC-AT systems, serial ports attached 
+/// The Serial I/O protocol is used to communicate with UART-style serial devices.
+/// These can be standard UART serial ports in PC-AT systems, serial ports attached
 /// to a USB interface, or potentially any character-based I/O device.
 ///
 struct _EFI_SERIAL_IO_PROTOCOL {
   ///
-  /// The revision to which the EFI_SERIAL_IO_PROTOCOL adheres. All future revisions 
-  /// must be backwards compatible. If a future version is not backwards compatible, 
+  /// The revision to which the EFI_SERIAL_IO_PROTOCOL adheres. All future revisions
+  /// must be backwards compatible. If a future version is not backwards compatible,
   /// it is not the same GUID.
   ///
   UINT32                      Revision;
@@ -292,6 +288,14 @@ struct _EFI_SERIAL_IO_PROTOCOL {
   /// Pointer to SERIAL_IO_MODE data.
   ///
   EFI_SERIAL_IO_MODE          *Mode;
+  ///
+  /// Pointer to a GUID identifying the device connected to the serial port.
+  /// This field is NULL when the protocol is installed by the serial port
+  /// driver and may be populated by a platform driver for a serial port
+  /// with a known device attached. The field will remain NULL if there is
+  /// no platform serial device identification information available.
+  ///
+  CONST EFI_GUID              *DeviceTypeGuid; // Revision 1.1
 };
 
 extern EFI_GUID gEfiSerialIoProtocolGuid;
diff --git a/MdePkg/Include/Protocol/ServiceBinding.h b/MdePkg/Include/Protocol/ServiceBinding.h
index 546a0d0973d2..37f44c554ced 100644
--- a/MdePkg/Include/Protocol/ServiceBinding.h
+++ b/MdePkg/Include/Protocol/ServiceBinding.h
@@ -1,18 +1,12 @@
-/** @file  
+/** @file
   UEFI Service Binding Protocol is defined in UEFI specification.
 
   The file defines the generic Service Binding Protocol functions.
-  It provides services that are required to create and destroy child 
+  It provides services that are required to create and destroy child
   handles that support a given set of protocols.
 
-  Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -26,14 +20,14 @@ typedef struct _EFI_SERVICE_BINDING_PROTOCOL EFI_SERVICE_BINDING_PROTOCOL;
 
 /**
   Creates a child handle and installs a protocol.
-  
-  The CreateChild() function installs a protocol on ChildHandle. 
-  If ChildHandle is a pointer to NULL, then a new handle is created and returned in ChildHandle. 
+
+  The CreateChild() function installs a protocol on ChildHandle.
+  If ChildHandle is a pointer to NULL, then a new handle is created and returned in ChildHandle.
   If ChildHandle is not a pointer to NULL, then the protocol installs on the existing ChildHandle.
 
   @param  This        Pointer to the EFI_SERVICE_BINDING_PROTOCOL instance.
   @param  ChildHandle Pointer to the handle of the child to create. If it is NULL,
-                      then a new handle is created. If it is a pointer to an existing UEFI handle, 
+                      then a new handle is created. If it is a pointer to an existing UEFI handle,
                       then the protocol is added to the existing UEFI handle.
 
   @retval EFI_SUCCES            The protocol was added to ChildHandle.
@@ -52,9 +46,9 @@ EFI_STATUS
 
 /**
   Destroys a child handle with a protocol installed on it.
-  
-  The DestroyChild() function does the opposite of CreateChild(). It removes a protocol 
-  that was installed by CreateChild() from ChildHandle. If the removed protocol is the 
+
+  The DestroyChild() function does the opposite of CreateChild(). It removes a protocol
+  that was installed by CreateChild() from ChildHandle. If the removed protocol is the
   last protocol on ChildHandle, then ChildHandle is destroyed.
 
   @param  This        Pointer to the EFI_SERVICE_BINDING_PROTOCOL instance.
@@ -76,14 +70,14 @@ EFI_STATUS
   );
 
 ///
-/// The EFI_SERVICE_BINDING_PROTOCOL provides member functions to create and destroy 
-/// child handles. A driver is responsible for adding protocols to the child handle 
-/// in CreateChild() and removing protocols in DestroyChild(). It is also required 
-/// that the CreateChild() function opens the parent protocol BY_CHILD_CONTROLLER 
+/// The EFI_SERVICE_BINDING_PROTOCOL provides member functions to create and destroy
+/// child handles. A driver is responsible for adding protocols to the child handle
+/// in CreateChild() and removing protocols in DestroyChild(). It is also required
+/// that the CreateChild() function opens the parent protocol BY_CHILD_CONTROLLER
 /// to establish the parent-child relationship, and closes the protocol in DestroyChild().
-/// The pseudo code for CreateChild() and DestroyChild() is provided to specify the 
-/// required behavior, not to specify the required implementation. Each consumer of 
-/// a software protocol is responsible for calling CreateChild() when it requires the 
+/// The pseudo code for CreateChild() and DestroyChild() is provided to specify the
+/// required behavior, not to specify the required implementation. Each consumer of
+/// a software protocol is responsible for calling CreateChild() when it requires the
 /// protocol and calling DestroyChild() when it is finished with that protocol.
 ///
 struct _EFI_SERVICE_BINDING_PROTOCOL {
diff --git a/MdePkg/Include/Protocol/Shell.h b/MdePkg/Include/Protocol/Shell.h
index c16da382b2a6..9047060ae32e 100644
--- a/MdePkg/Include/Protocol/Shell.h
+++ b/MdePkg/Include/Protocol/Shell.h
@@ -2,14 +2,8 @@
   EFI Shell protocol as defined in the UEFI Shell 2.0 specification including errata.
 
   (C) Copyright 2014 Hewlett-Packard Development Company, L.P.<BR>
-  Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -547,7 +541,7 @@ CONST CHAR16 *
   );
 
 /**
-  Gets the environment variable and Attributes, or list of environment variables.  Can be 
+  Gets the environment variable and Attributes, or list of environment variables.  Can be
   used instead of GetEnv().
 
   This function returns the current value of the specified environment variable and
@@ -555,18 +549,18 @@ CONST CHAR16 *
   variables will be returned.
 
   @param[in] Name               A pointer to the environment variable name. If Name is NULL,
-                                then the function will return all of the defined shell 
+                                then the function will return all of the defined shell
                                 environment variables. In the case where multiple environment
-                                variables are being returned, each variable will be terminated 
+                                variables are being returned, each variable will be terminated
                                 by a NULL, and the list will be terminated by a double NULL.
   @param[out] Attributes        If not NULL, a pointer to the returned attributes bitmask for
                                 the environment variable. In the case where Name is NULL, and
                                 multiple environment variables are being returned, Attributes
                                 is undefined.
 
-  @retval NULL                  The environment variable doesn't exist.  
-  @return                       The environment variable's value. The returned pointer does not 
-                                need to be freed by the caller.  
+  @retval NULL                  The environment variable doesn't exist.
+  @return                       The environment variable's value. The returned pointer does not
+                                need to be freed by the caller.
 **/
 typedef
 CONST CHAR16 *
@@ -1011,7 +1005,7 @@ EFI_STATUS
                                 aliases will be returned in ReturnedData.
   @param[out] Volatile          Upon return of a single command if TRUE indicates
                                 this is stored in a volatile fashion.  FALSE otherwise.
-  @return                      	If Alias is not NULL, it will return a pointer to
+  @return                        If Alias is not NULL, it will return a pointer to
                                 the NULL-terminated command for that alias.
                                 If Alias is NULL, ReturnedData points to a ';'
                                 delimited list of alias (e.g.
@@ -1262,7 +1256,7 @@ extern EFI_GUID gEfiShellProtocolGuid;
 
 enum ShellVersion {
   SHELL_MAJOR_VERSION = 2,
-  SHELL_MINOR_VERSION = 1
+  SHELL_MINOR_VERSION = 2
 };
 
 #endif
diff --git a/MdePkg/Include/Protocol/ShellDynamicCommand.h b/MdePkg/Include/Protocol/ShellDynamicCommand.h
index da2055d2d506..58ae0b844760 100644
--- a/MdePkg/Include/Protocol/ShellDynamicCommand.h
+++ b/MdePkg/Include/Protocol/ShellDynamicCommand.h
@@ -2,14 +2,8 @@
   EFI Shell Dynamic Command registration protocol
 
   (C) Copyright 2012-2014 Hewlett-Packard Development Company, L.P.<BR>
-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -73,7 +67,7 @@ CHAR16*
 
 /// EFI_SHELL_DYNAMIC_COMMAND_PROTOCOL protocol structure.
 struct _EFI_SHELL_DYNAMIC_COMMAND_PROTOCOL {
-  
+
   CONST CHAR16           *CommandName;
   SHELL_COMMAND_HANDLER  Handler;
   SHELL_COMMAND_GETHELP  GetHelp;
diff --git a/MdePkg/Include/Protocol/ShellParameters.h b/MdePkg/Include/Protocol/ShellParameters.h
index e9c0ee5f634e..20091a1537e0 100644
--- a/MdePkg/Include/Protocol/ShellParameters.h
+++ b/MdePkg/Include/Protocol/ShellParameters.h
@@ -2,13 +2,7 @@
   EFI Shell protocol as defined in the UEFI Shell 2.0 specification.
 
   Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/Protocol/SimpleFileSystem.h b/MdePkg/Include/Protocol/SimpleFileSystem.h
index cf39e83c2c33..7762d34ac217 100644
--- a/MdePkg/Include/Protocol/SimpleFileSystem.h
+++ b/MdePkg/Include/Protocol/SimpleFileSystem.h
@@ -1,20 +1,14 @@
 /** @file
   SimpleFileSystem protocol as defined in the UEFI 2.0 specification.
 
-  The SimpleFileSystem protocol is the programmatic access to the FAT (12,16,32) 
-  file system specified in UEFI 2.0. It can also be used to abstract a file  
+  The SimpleFileSystem protocol is the programmatic access to the FAT (12,16,32)
+  file system specified in UEFI 2.0. It can also be used to abstract a file
   system other than FAT.
 
   UEFI 2.0 can boot from any valid EFI image contained in a SimpleFileSystem.
 
-Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -33,12 +27,12 @@ typedef struct _EFI_FILE_PROTOCOL         *EFI_FILE_HANDLE;
 
 ///
 /// Protocol GUID name defined in EFI1.1.
-/// 
+///
 #define SIMPLE_FILE_SYSTEM_PROTOCOL       EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID
 
 ///
 /// Protocol name defined in EFI1.1.
-/// 
+///
 typedef EFI_SIMPLE_FILE_SYSTEM_PROTOCOL   EFI_FILE_IO_INTERFACE;
 typedef EFI_FILE_PROTOCOL                 EFI_FILE;
 
@@ -73,7 +67,7 @@ EFI_STATUS
 
 ///
 /// Revision defined in EFI1.1
-/// 
+///
 #define EFI_FILE_IO_INTERFACE_REVISION  EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_REVISION
 
 struct _EFI_SIMPLE_FILE_SYSTEM_PROTOCOL {
@@ -99,7 +93,7 @@ struct _EFI_SIMPLE_FILE_SYSTEM_PROTOCOL {
                      and "..".
   @param  OpenMode   The mode to open the file. The only valid combinations that the
                      file may be opened with are: Read, Read/Write, or Create/Read/Write.
-  @param  Attributes Only valid for EFI_FILE_MODE_CREATE, in which case these are the 
+  @param  Attributes Only valid for EFI_FILE_MODE_CREATE, in which case these are the
                      attribute bits for the newly created file.
 
   @retval EFI_SUCCESS          The file was opened.
@@ -147,7 +141,7 @@ EFI_STATUS
 /**
   Closes a specified file handle.
 
-  @param  This          A pointer to the EFI_FILE_PROTOCOL instance that is the file 
+  @param  This          A pointer to the EFI_FILE_PROTOCOL instance that is the file
                         handle to close.
 
   @retval EFI_SUCCESS   The file was closed.
@@ -345,7 +339,7 @@ EFI_STATUS
 /**
   Flushes all modified data associated with a file to a device.
 
-  @param  This A pointer to the EFI_FILE_PROTOCOL instance that is the file 
+  @param  This A pointer to the EFI_FILE_PROTOCOL instance that is the file
                handle to flush.
 
   @retval EFI_SUCCESS          The data was flushed.
@@ -409,7 +403,7 @@ typedef struct {
                      and "..".
   @param  OpenMode   The mode to open the file. The only valid combinations that the
                      file may be opened with are: Read, Read/Write, or Create/Read/Write.
-  @param  Attributes Only valid for EFI_FILE_MODE_CREATE, in which case these are the 
+  @param  Attributes Only valid for EFI_FILE_MODE_CREATE, in which case these are the
                      attribute bits for the newly created file.
   @param  Token      A pointer to the token associated with the transaction.
 
@@ -488,13 +482,13 @@ typedef
 EFI_STATUS
 (EFIAPI *EFI_FILE_WRITE_EX) (
   IN EFI_FILE_PROTOCOL        *This,
-  IN OUT EFI_FILE_IO_TOKEN    *Token 
+  IN OUT EFI_FILE_IO_TOKEN    *Token
 );
 
 /**
   Flushes all modified data associated with a file to a device.
 
-  @param  This  A pointer to the EFI_FILE_PROTOCOL instance that is the file 
+  @param  This  A pointer to the EFI_FILE_PROTOCOL instance that is the file
                 handle to flush.
   @param  Token A pointer to the token associated with the transaction.
 
@@ -523,19 +517,19 @@ EFI_STATUS
 
 //
 // Revision defined in EFI1.1.
-// 
+//
 #define EFI_FILE_REVISION   EFI_FILE_PROTOCOL_REVISION
 
 ///
 /// The EFI_FILE_PROTOCOL provides file IO access to supported file systems.
-/// An EFI_FILE_PROTOCOL provides access to a file's or directory's contents, 
-/// and is also a reference to a location in the directory tree of the file system 
-/// in which the file resides. With any given file handle, other files may be opened 
+/// An EFI_FILE_PROTOCOL provides access to a file's or directory's contents,
+/// and is also a reference to a location in the directory tree of the file system
+/// in which the file resides. With any given file handle, other files may be opened
 /// relative to this file's location, yielding new file handles.
 ///
 struct _EFI_FILE_PROTOCOL {
   ///
-  /// The version of the EFI_FILE_PROTOCOL interface. The version specified 
+  /// The version of the EFI_FILE_PROTOCOL interface. The version specified
   /// by this specification is EFI_FILE_PROTOCOL_LATEST_REVISION.
   /// Future versions are required to be backward compatible to version 1.0.
   ///
diff --git a/MdePkg/Include/Protocol/SimpleNetwork.h b/MdePkg/Include/Protocol/SimpleNetwork.h
index 0dda83aaafd9..a367fa2e3111 100644
--- a/MdePkg/Include/Protocol/SimpleNetwork.h
+++ b/MdePkg/Include/Protocol/SimpleNetwork.h
@@ -1,5 +1,5 @@
 /** @file
-  The EFI_SIMPLE_NETWORK_PROTOCOL provides services to initialize a network interface, 
+  The EFI_SIMPLE_NETWORK_PROTOCOL provides services to initialize a network interface,
   transmit packets, receive packets, and close a network interface.
 
   Basic network device abstraction.
@@ -9,17 +9,11 @@
   MCast - MultiCast
   ...
 
-Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.   
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
-  @par Revision Reference:          
-  This Protocol is introduced in EFI Specification 1.10.          
+  @par Revision Reference:
+  This Protocol is introduced in EFI Specification 1.10.
 
 **/
 
@@ -36,7 +30,7 @@ typedef struct _EFI_SIMPLE_NETWORK_PROTOCOL  EFI_SIMPLE_NETWORK_PROTOCOL;
 
 ///
 /// Protocol defined in EFI1.1.
-/// 
+///
 typedef EFI_SIMPLE_NETWORK_PROTOCOL   EFI_SIMPLE_NETWORK;
 
 ///
@@ -288,8 +282,8 @@ EFI_STATUS
   );
 
 /**
-  Resets a network adapter and allocates the transmit and receive buffers 
-  required by the network interface; optionally, also requests allocation 
+  Resets a network adapter and allocates the transmit and receive buffers
+  required by the network interface; optionally, also requests allocation
   of additional transmit and receive buffers.
 
   @param  This              The protocol instance pointer.
@@ -322,8 +316,8 @@ EFI_STATUS
   );
 
 /**
-  Resets a network adapter and re-initializes it with the parameters that were 
-  provided in the previous call to Initialize().  
+  Resets a network adapter and re-initializes it with the parameters that were
+  provided in the previous call to Initialize().
 
   @param  This                 The protocol instance pointer.
   @param  ExtendedVerification Indicates that the driver may perform a more
@@ -345,7 +339,7 @@ EFI_STATUS
   );
 
 /**
-  Resets a network adapter and leaves it in a state that is safe for 
+  Resets a network adapter and leaves it in a state that is safe for
   another driver to initialize.
 
   @param  This Protocol instance pointer.
@@ -482,7 +476,7 @@ EFI_STATUS
   );
 
 /**
-  Performs read and write operations on the NVRAM device attached to a 
+  Performs read and write operations on the NVRAM device attached to a
   network interface.
 
   @param  This       The protocol instance pointer.
@@ -512,7 +506,7 @@ EFI_STATUS
   );
 
 /**
-  Reads the current interrupt status and recycled transmit buffer status from 
+  Reads the current interrupt status and recycled transmit buffer status from
   a network interface.
 
   @param  This            The protocol instance pointer.
@@ -570,7 +564,7 @@ EFI_STATUS
 
   @retval EFI_SUCCESS           The packet was placed on the transmit queue.
   @retval EFI_NOT_STARTED       The network interface has not been started.
-  @retval EFI_NOT_READY         The network interface is too busy to accept this transmit request.                      
+  @retval EFI_NOT_READY         The network interface is too busy to accept this transmit request.
   @retval EFI_BUFFER_TOO_SMALL  The BufferSize parameter is too small.
   @retval EFI_INVALID_PARAMETER One or more of the parameters has an unsupported value.
   @retval EFI_DEVICE_ERROR      The command could not be sent to the network interface.
@@ -637,19 +631,19 @@ EFI_STATUS
 
 //
 // Revision defined in EFI1.1
-// 
+//
 #define EFI_SIMPLE_NETWORK_INTERFACE_REVISION   EFI_SIMPLE_NETWORK_PROTOCOL_REVISION
 
 ///
-/// The EFI_SIMPLE_NETWORK_PROTOCOL protocol is used to initialize access 
-/// to a network adapter. Once the network adapter initializes, 
-/// the EFI_SIMPLE_NETWORK_PROTOCOL protocol provides services that 
+/// The EFI_SIMPLE_NETWORK_PROTOCOL protocol is used to initialize access
+/// to a network adapter. Once the network adapter initializes,
+/// the EFI_SIMPLE_NETWORK_PROTOCOL protocol provides services that
 /// allow packets to be transmitted and received.
 ///
 struct _EFI_SIMPLE_NETWORK_PROTOCOL {
   ///
-  /// Revision of the EFI_SIMPLE_NETWORK_PROTOCOL. All future revisions must 
-  /// be backwards compatible. If a future version is not backwards compatible 
+  /// Revision of the EFI_SIMPLE_NETWORK_PROTOCOL. All future revisions must
+  /// be backwards compatible. If a future version is not backwards compatible
   /// it is not the same GUID.
   ///
   UINT64                              Revision;
diff --git a/MdePkg/Include/Protocol/SimplePointer.h b/MdePkg/Include/Protocol/SimplePointer.h
index d8c0757f6243..cb52ad9ddfb9 100644
--- a/MdePkg/Include/Protocol/SimplePointer.h
+++ b/MdePkg/Include/Protocol/SimplePointer.h
@@ -3,14 +3,8 @@
 
   Abstraction of a very simple pointer device like a mouse or trackball.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -78,17 +72,17 @@ typedef struct {
   BOOLEAN RightButton;
 } EFI_SIMPLE_POINTER_MODE;
 
-/**                                                                 
+/**
   Resets the pointer device hardware.
-    
+
   @param  This                  A pointer to the EFI_SIMPLE_POINTER_PROTOCOL
-                                instance.                                   
+                                instance.
   @param  ExtendedVerification  Indicates that the driver may perform a more exhaustive
-                                verification operation of the device during reset.                                       
-                                
+                                verification operation of the device during reset.
+
   @retval EFI_SUCCESS           The device was reset.
-  @retval EFI_DEVICE_ERROR      The device is not functioning correctly and could not be reset.  
-                                   
+  @retval EFI_DEVICE_ERROR      The device is not functioning correctly and could not be reset.
+
 **/
 typedef
 EFI_STATUS
@@ -97,32 +91,32 @@ EFI_STATUS
   IN BOOLEAN                                ExtendedVerification
   );
 
-/**                                                                 
+/**
   Retrieves the current state of a pointer device.
-    
+
   @param  This                  A pointer to the EFI_SIMPLE_POINTER_PROTOCOL
-                                instance.                                   
+                                instance.
   @param  State                 A pointer to the state information on the pointer device.
-                                
+
   @retval EFI_SUCCESS           The state of the pointer device was returned in State.
   @retval EFI_NOT_READY         The state of the pointer device has not changed since the last call to
-                                GetState().                                                           
+                                GetState().
   @retval EFI_DEVICE_ERROR      A device error occurred while attempting to retrieve the pointer device's
-                                current state.                                                           
-                                   
+                                current state.
+
 **/
 typedef
 EFI_STATUS
 (EFIAPI *EFI_SIMPLE_POINTER_GET_STATE)(
   IN EFI_SIMPLE_POINTER_PROTOCOL          *This,
-  IN OUT EFI_SIMPLE_POINTER_STATE         *State
+  OUT EFI_SIMPLE_POINTER_STATE            *State
   );
 
 ///
-/// The EFI_SIMPLE_POINTER_PROTOCOL provides a set of services for a pointer 
-/// device that can use used as an input device from an application written 
-/// to this specification. The services include the ability to reset the 
-/// pointer device, retrieve get the state of the pointer device, and 
+/// The EFI_SIMPLE_POINTER_PROTOCOL provides a set of services for a pointer
+/// device that can use used as an input device from an application written
+/// to this specification. The services include the ability to reset the
+/// pointer device, retrieve get the state of the pointer device, and
 /// retrieve the capabilities of the pointer device.
 ///
 struct _EFI_SIMPLE_POINTER_PROTOCOL {
diff --git a/MdePkg/Include/Protocol/SimpleTextIn.h b/MdePkg/Include/Protocol/SimpleTextIn.h
index d8df5537aa1e..e6884d89c1c8 100644
--- a/MdePkg/Include/Protocol/SimpleTextIn.h
+++ b/MdePkg/Include/Protocol/SimpleTextIn.h
@@ -5,13 +5,7 @@
   terminal.
 
   Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/Protocol/SimpleTextInEx.h b/MdePkg/Include/Protocol/SimpleTextInEx.h
index 5524c720a713..f6a80e7c4f4d 100644
--- a/MdePkg/Include/Protocol/SimpleTextInEx.h
+++ b/MdePkg/Include/Protocol/SimpleTextInEx.h
@@ -5,14 +5,8 @@
   which exposes much more state and modifier information from the input device,
   also allows one to register a notification for a particular keystroke.
 
-  Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -190,13 +184,10 @@ typedef struct {
                   pressed.
 
 
-  @retval EFI_SUCCESS     The keystroke information was
-                          returned.
-
-  @retval EFI_NOT_READY   There was no keystroke data available.
-                          EFI_DEVICE_ERROR The keystroke
-                          information was not returned due to
-                          hardware errors.
+  @retval EFI_SUCCESS      The keystroke information was returned.
+  @retval EFI_NOT_READY    There was no keystroke data available.
+  @retval EFI_DEVICE_ERROR The keystroke information was not returned due to
+                           hardware errors.
 
 
 **/
@@ -251,18 +242,19 @@ EFI_STATUS
 
   @param KeyData                  A pointer to a buffer that is filled in with
                                   the keystroke information for the key that was
-                                  pressed.
+                                  pressed. If KeyData.Key, KeyData.KeyState.KeyToggleState
+                                  and KeyData.KeyState.KeyShiftState are 0, then any incomplete
+                                  keystroke will trigger a notification of the KeyNotificationFunction.
 
-  @param KeyNotificationFunction  Points to the function to be
-                                  called when the key sequence
-                                  is typed specified by KeyData.
+  @param KeyNotificationFunction  Points to the function to be called when the key sequence
+                                  is typed specified by KeyData. This notification function
+                                  should be called at <=TPL_CALLBACK.
 
 
   @param NotifyHandle             Points to the unique handle assigned to
                                   the registered notification.
 
-  @retval EFI_SUCCESS           The device state was set
-                                appropriately.
+  @retval EFI_SUCCESS           Key notify was registered successfully.
 
   @retval EFI_OUT_OF_RESOURCES  Unable to allocate necessary
                                 data structures.
@@ -286,7 +278,7 @@ EFI_STATUS
   @param NotificationHandle The handle of the notification
                             function being unregistered.
 
-  @retval EFI_SUCCESS The device state was set appropriately.
+  @retval EFI_SUCCESS           Key notify was unregistered successfully.
 
   @retval EFI_INVALID_PARAMETER The NotificationHandle is
                                 invalid.
diff --git a/MdePkg/Include/Protocol/SimpleTextOut.h b/MdePkg/Include/Protocol/SimpleTextOut.h
index 4d2612c0a91d..18438d3533ef 100644
--- a/MdePkg/Include/Protocol/SimpleTextOut.h
+++ b/MdePkg/Include/Protocol/SimpleTextOut.h
@@ -6,14 +6,8 @@
   a single hardware device or a virtual device that is an aggregation
   of multiple physical devices.
 
-Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -27,14 +21,14 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
 ///
 /// Protocol GUID defined in EFI1.1.
-/// 
+///
 #define SIMPLE_TEXT_OUTPUT_PROTOCOL   EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL_GUID
 
 typedef struct _EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL;
 
 ///
 /// Backward-compatible with EFI1.1.
-/// 
+///
 typedef EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL   SIMPLE_TEXT_OUTPUT_INTERFACE;
 
 //
@@ -125,8 +119,8 @@ typedef EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL   SIMPLE_TEXT_OUTPUT_INTERFACE;
 #define EFI_WHITE                 (EFI_BLUE | EFI_GREEN | EFI_RED | EFI_BRIGHT)
 
 //
-// Macro to accept color values in their raw form to create 
-// a value that represents both a foreground and background 
+// Macro to accept color values in their raw form to create
+// a value that represents both a foreground and background
 // color in a single byte.
 // For Foreground, and EFI_* value is valid from EFI_BLACK(0x00) to
 // EFI_WHITE (0x0F).
@@ -148,7 +142,7 @@ typedef EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL   SIMPLE_TEXT_OUTPUT_INTERFACE;
 
 //
 // We currently define attributes from 0 - 7F for color manipulations
-// To internally handle the local display characteristics for a particular character, 
+// To internally handle the local display characteristics for a particular character,
 // Bit 7 signifies the local glyph representation for a character.  If turned on, glyphs will be
 // pulled from the wide glyph database and will display locally as a wide character (16 X 19 versus 8 X 19)
 // If bit 7 is off, the narrow glyph database will be used.  This does NOT affect information that is sent to
@@ -201,7 +195,7 @@ EFI_STATUS
   );
 
 /**
-  Verifies that all characters in a string can be output to the 
+  Verifies that all characters in a string can be output to the
   target device.
 
   @param  This   The protocol instance pointer.
@@ -231,7 +225,7 @@ EFI_STATUS
                      requested ModeNumber.
   @param  Rows       Returns the geometry of the text output device for the
                      requested ModeNumber.
-                                          
+
   @retval EFI_SUCCESS      The requested mode information was returned.
   @retval EFI_DEVICE_ERROR The device had an error and could not complete the request.
   @retval EFI_UNSUPPORTED  The mode number was not valid.
@@ -286,11 +280,11 @@ EFI_STATUS
   );
 
 /**
-  Clears the output device(s) display to the currently selected background 
+  Clears the output device(s) display to the currently selected background
   color.
 
   @param  This              The protocol instance pointer.
-                           
+
   @retval  EFI_SUCCESS      The operation completed successfully.
   @retval  EFI_DEVICE_ERROR The device had an error and could not complete the request.
   @retval  EFI_UNSUPPORTED  The output device is not in a valid text mode.
@@ -385,9 +379,9 @@ typedef struct {
 } EFI_SIMPLE_TEXT_OUTPUT_MODE;
 
 ///
-/// The SIMPLE_TEXT_OUTPUT protocol is used to control text-based output devices. 
-/// It is the minimum required protocol for any handle supplied as the ConsoleOut 
-/// or StandardError device. In addition, the minimum supported text mode of such 
+/// The SIMPLE_TEXT_OUTPUT protocol is used to control text-based output devices.
+/// It is the minimum required protocol for any handle supplied as the ConsoleOut
+/// or StandardError device. In addition, the minimum supported text mode of such
 /// devices is at least 80 x 25 characters.
 ///
 struct _EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL {
diff --git a/MdePkg/Include/Protocol/SmartCardEdge.h b/MdePkg/Include/Protocol/SmartCardEdge.h
index ac5095c375fc..3107070ee997 100644
--- a/MdePkg/Include/Protocol/SmartCardEdge.h
+++ b/MdePkg/Include/Protocol/SmartCardEdge.h
@@ -6,14 +6,11 @@
   boot process for authentication or data signing/decryption, especially if the
   application has to make use of PKI.
 
-  Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2015-2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  This Protocol was introduced in UEFI Specification 2.5.
 
 **/
 
diff --git a/MdePkg/Include/Protocol/SmartCardReader.h b/MdePkg/Include/Protocol/SmartCardReader.h
index a39b379c5eaf..e1344902fb1b 100644
--- a/MdePkg/Include/Protocol/SmartCardReader.h
+++ b/MdePkg/Include/Protocol/SmartCardReader.h
@@ -5,13 +5,7 @@
   smart card or a smart card reader.
 
   Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/Protocol/Smbios.h b/MdePkg/Include/Protocol/Smbios.h
index 1860ba50259e..1ef57a665a49 100644
--- a/MdePkg/Include/Protocol/Smbios.h
+++ b/MdePkg/Include/Protocol/Smbios.h
@@ -1,7 +1,7 @@
 /** @file
   SMBIOS Protocol as defined in PI1.2 Specification VOLUME 5 Standard.
 
-  SMBIOS protocol allows consumers to log SMBIOS data records, and enables the producer 
+  SMBIOS protocol allows consumers to log SMBIOS data records, and enables the producer
   to create the SMBIOS tables for a platform.
 
   This protocol provides an interface to add, remove or discover SMBIOS records. The driver which
@@ -13,14 +13,8 @@
   requiring an update to MajorVersion and MinorVersion.
   The SMBIOS protocol can only be called a TPL < TPL_NOTIFY.
 
-  Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -84,12 +78,12 @@ typedef SMBIOS_TABLE_STRING EFI_SMBIOS_STRING;
 typedef SMBIOS_TYPE         EFI_SMBIOS_TYPE;
 typedef SMBIOS_HANDLE       EFI_SMBIOS_HANDLE;
 typedef SMBIOS_STRUCTURE    EFI_SMBIOS_TABLE_HEADER;
-    
+
 typedef struct _EFI_SMBIOS_PROTOCOL EFI_SMBIOS_PROTOCOL;
 
 /**
   Add an SMBIOS record.
-  
+
   This function allows any agent to add SMBIOS records. The caller is responsible for ensuring
   Record is formatted in a way that matches the version of the SMBIOS specification as defined in
   the MajorRevision and MinorRevision fields of the EFI_SMBIOS_PROTOCOL.
@@ -100,7 +94,7 @@ typedef struct _EFI_SMBIOS_PROTOCOL EFI_SMBIOS_PROTOCOL;
   directly following the last string. The number of optional strings is not defined by the formatted area,
   but is fixed by the call to Add(). A string can be a place holder, but it must not be a NULL string as
   two NULL strings look like the double-null that terminates the structure.
-  
+
   @param[in]        This                The EFI_SMBIOS_PROTOCOL instance.
   @param[in]        ProducerHandle      The handle of the controller or driver associated with the SMBIOS information. NULL means no handle.
   @param[in, out]   SmbiosHandle        On entry, the handle of the SMBIOS record to add. If FFFEh, then a unique handle
@@ -110,7 +104,7 @@ typedef struct _EFI_SMBIOS_PROTOCOL EFI_SMBIOS_PROTOCOL;
                                         determined by EFI_SMBIOS_TABLE_HEADER.Type. The size of the formatted
                                         area is defined by EFI_SMBIOS_TABLE_HEADER.Length and either followed
                                         by a double-null (0x0000) or a set of null terminated strings and a null.
-  
+
   @retval EFI_SUCCESS                   Record was added.
   @retval EFI_OUT_OF_RESOURCES          Record was not added.
   @retval EFI_ALREADY_STARTED           The SmbiosHandle passed in was already in use.
@@ -126,19 +120,19 @@ EFI_STATUS
 
 /**
   Update the string associated with an existing SMBIOS record.
-  
+
   This function allows the update of specific SMBIOS strings. The number of valid strings for any
   SMBIOS record is defined by how many strings were present when Add() was called.
-  
+
   @param[in]    This            The EFI_SMBIOS_PROTOCOL instance.
   @param[in]    SmbiosHandle    SMBIOS Handle of structure that will have its string updated.
   @param[in]    StringNumber    The non-zero string number of the string to update.
   @param[in]    String          Update the StringNumber string with String.
-  
+
   @retval EFI_SUCCESS           SmbiosHandle had its StringNumber String updated.
   @retval EFI_INVALID_PARAMETER SmbiosHandle does not exist.
   @retval EFI_UNSUPPORTED       String was not added because it is longer than the SMBIOS Table supports.
-  @retval EFI_NOT_FOUND         The StringNumber.is not valid for this SMBIOS record.    
+  @retval EFI_NOT_FOUND         The StringNumber.is not valid for this SMBIOS record.
 **/
 typedef
 EFI_STATUS
@@ -151,12 +145,12 @@ EFI_STATUS
 
 /**
   Remove an SMBIOS record.
-  
+
   This function removes an SMBIOS record using the handle specified by SmbiosHandle.
-  
+
   @param[in]    This                The EFI_SMBIOS_PROTOCOL instance.
   @param[in]    SmbiosHandle        The handle of the SMBIOS record to remove.
-  
+
   @retval EFI_SUCCESS               SMBIOS record was removed.
   @retval EFI_INVALID_PARAMETER     SmbiosHandle does not specify a valid SMBIOS record.
 **/
@@ -169,10 +163,10 @@ EFI_STATUS
 
 /**
   Allow the caller to discover all or some of the SMBIOS records.
-  
+
   This function allows all of the SMBIOS records to be discovered. It's possible to find
   only the SMBIOS records that match the optional Type argument.
-  
+
   @param[in]        This            The EFI_SMBIOS_PROTOCOL instance.
   @param[in, out]   SmbiosHandle    On entry, points to the previous handle of the SMBIOS record. On exit, points to the
                                     next SMBIOS record handle. If it is FFFEh on entry, then the first SMBIOS record
@@ -207,7 +201,7 @@ struct _EFI_SMBIOS_PROTOCOL {
   UINT8                    MajorVersion;    ///< The major revision of the SMBIOS specification supported.
   UINT8                    MinorVersion;    ///< The minor revision of the SMBIOS specification supported.
 };
-    
+
 extern EFI_GUID gEfiSmbiosProtocolGuid;
-    
+
 #endif // __SMBIOS_PROTOCOL_H__
diff --git a/MdePkg/Include/Protocol/SmbusHc.h b/MdePkg/Include/Protocol/SmbusHc.h
index d5620d7a6c89..219a5cbe0c0c 100644
--- a/MdePkg/Include/Protocol/SmbusHc.h
+++ b/MdePkg/Include/Protocol/SmbusHc.h
@@ -1,15 +1,9 @@
 /** @file
-  The file provides basic SMBus host controller management 
+  The file provides basic SMBus host controller management
   and basic data transactions over the SMBus.
 
-  Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference: PI
   Version 1.00.
@@ -27,13 +21,13 @@
 typedef struct _EFI_SMBUS_HC_PROTOCOL EFI_SMBUS_HC_PROTOCOL;
 
 /**
-     
+
   The Execute() function provides a standard way to execute an
   operation as defined in the System Management Bus (SMBus)
   Specification. The resulting transaction will be either that
   the SMBus slave devices accept this transaction or that this
-  function returns with error. 
-  
+  function returns with error.
+
   @param This     A pointer to the EFI_SMBUS_HC_PROTOCOL instance.
                   SlaveAddress The SMBus slave address of the device
                   with which to communicate. Type
@@ -65,8 +59,8 @@ typedef struct _EFI_SMBUS_HC_PROTOCOL EFI_SMBUS_HC_PROTOCOL;
   @param PecCheck Defines if Packet Error Code (PEC) checking
                   is required for this operation. SMBus Host
                   Controller Code Definitions Version 1.0
-                  August 21, 2006 13 
-                  
+                  August 21, 2006 13
+
  @param Length    Signifies the number of bytes that this operation will do.
                   The maximum number of bytes can be revision
                   specific and operation specific. This field
@@ -78,8 +72,8 @@ typedef struct _EFI_SMBUS_HC_PROTOCOL EFI_SMBUS_HC_PROTOCOL;
                   SMBus slave device. Not all operations require
                   this argument. The length of this buffer is
                   identified by Length.
-  
-  
+
+
   @retval EFI_SUCCESS           The last data that was returned from the
                                 access matched the poll exit criteria.
 
@@ -113,7 +107,7 @@ typedef struct _EFI_SMBUS_HC_PROTOCOL EFI_SMBUS_HC_PROTOCOL;
                                 values.
 
   @retval EFI_UNSUPPORTED       The SMBus operation or PEC is not
-                                supported. 
+                                supported.
 
   @retval EFI_BUFFER_TOO_SMALL  Buffer is not sufficient for
                                 this operation.
@@ -134,10 +128,10 @@ EFI_STATUS
 
 
 /**
-   
-  The ArpDevice() function provides a standard way for a device driver to 
+
+  The ArpDevice() function provides a standard way for a device driver to
   enumerate the entire SMBus or specific devices on the bus.
-  
+
   @param This           A pointer to the EFI_SMBUS_HC_PROTOCOL instance.
 
   @param ArpAll         A Boolean expression that indicates if the
@@ -183,7 +177,7 @@ EFI_STATUS
 
   @retval EFI_UNSUPPORTED       ArpDevice, GetArpMap, and Notify are
                                 not implemented by this driver.
-   
+
 **/
 typedef
 EFI_STATUS
@@ -196,23 +190,23 @@ EFI_STATUS
 
 
 /**
-  The GetArpMap() function returns the mapping of all the SMBus devices 
+  The GetArpMap() function returns the mapping of all the SMBus devices
   that were enumerated by the SMBus host driver.
-  
+
   @param This           A pointer to the EFI_SMBUS_HC_PROTOCOL instance.
-  
+
   @param Length         Size of the buffer that contains the SMBus
                         device map.
-  
+
   @param SmbusDeviceMap The pointer to the device map as
                         enumerated by the SMBus controller
                         driver.
-  
+
   @retval EFI_SUCCESS       The SMBus returned the current device map.
-  
+
   @retval EFI_UNSUPPORTED   ArpDevice, GetArpMap, and Notify are
                             not implemented by this driver.
-  
+
 **/
 typedef
 EFI_STATUS
@@ -224,13 +218,13 @@ EFI_STATUS
 
 /**
   The notify function does some actions.
-  
+
   @param SlaveAddress
   The SMBUS hardware address to which the SMBUS device is preassigned or allocated.
 
   @param Data
   Data of the SMBus host notify command that the caller wants to be called.
-  
+
   @return EFI_STATUS
 **/
 typedef
@@ -242,13 +236,13 @@ EFI_STATUS
 
 
 /**
-   
+
   The Notify() function registers all the callback functions to
-  allow the bus driver to call these functions when the 
+  allow the bus driver to call these functions when the
   SlaveAddress/Data pair happens.
-  
+
   @param  This            A pointer to the EFI_SMBUS_HC_PROTOCOL instance.
-  
+
   @param  SlaveAddress    Address that the host controller detects
                           as sending a message and calls all the registered function.
 
@@ -261,7 +255,7 @@ EFI_STATUS
                           Data pair.
 
   @retval EFI_SUCCESS       NotifyFunction was registered.
-  
+
   @retval EFI_UNSUPPORTED   ArpDevice, GetArpMap, and Notify are
                             not implemented by this driver.
 
diff --git a/MdePkg/Include/Protocol/SmmAccess2.h b/MdePkg/Include/Protocol/SmmAccess2.h
index 66cdf0c50abd..06475e172205 100644
--- a/MdePkg/Include/Protocol/SmmAccess2.h
+++ b/MdePkg/Include/Protocol/SmmAccess2.h
@@ -5,127 +5,33 @@
   It abstracts the location and characteristics of SMRAM.  The expectation is
   that the north bridge or memory controller would publish this protocol.
 
-  The principal functionality found in the memory controller includes the following: 
+  The principal functionality found in the memory controller includes the following:
   - Exposing the SMRAM to all non-SMM agents, or the "open" state
   - Shrouding the SMRAM to all but the SMM agents, or the "closed" state
-  - Preserving the system integrity, or "locking" the SMRAM, such that the settings cannot be 
-    perturbed by either boot service or runtime agents 
+  - Preserving the system integrity, or "locking" the SMRAM, such that the settings cannot be
+    perturbed by either boot service or runtime agents
 
-  Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
 #ifndef _SMM_ACCESS2_H_
 #define _SMM_ACCESS2_H_
 
-#define EFI_SMM_ACCESS2_PROTOCOL_GUID \
-  { \
-     0xc2702b74, 0x800c, 0x4131, {0x87, 0x46, 0x8f, 0xb5, 0xb8, 0x9c, 0xe4, 0xac } \
-  }
-
-
-typedef struct _EFI_SMM_ACCESS2_PROTOCOL  EFI_SMM_ACCESS2_PROTOCOL;
-
-/**
-  Opens the SMRAM area to be accessible by a boot-service driver.
-
-  This function "opens" SMRAM so that it is visible while not inside of SMM. The function should 
-  return EFI_UNSUPPORTED if the hardware does not support hiding of SMRAM. The function 
-  should return EFI_DEVICE_ERROR if the SMRAM configuration is locked.
-
-  @param[in] This           The EFI_SMM_ACCESS2_PROTOCOL instance.
-
-  @retval EFI_SUCCESS       The operation was successful.
-  @retval EFI_UNSUPPORTED   The system does not support opening and closing of SMRAM.
-  @retval EFI_DEVICE_ERROR  SMRAM cannot be opened, perhaps because it is locked.
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_SMM_OPEN2)(
-  IN EFI_SMM_ACCESS2_PROTOCOL  *This
-  );
-
-/**
-  Inhibits access to the SMRAM.
+#include <Protocol/MmAccess.h>
 
-  This function "closes" SMRAM so that it is not visible while outside of SMM. The function should 
-  return EFI_UNSUPPORTED if the hardware does not support hiding of SMRAM.
+#define EFI_SMM_ACCESS2_PROTOCOL_GUID       EFI_MM_ACCESS_PROTOCOL_GUID
 
-  @param[in] This           The EFI_SMM_ACCESS2_PROTOCOL instance.
+typedef EFI_MM_ACCESS_PROTOCOL  EFI_SMM_ACCESS2_PROTOCOL;
 
-  @retval EFI_SUCCESS       The operation was successful.
-  @retval EFI_UNSUPPORTED   The system does not support opening and closing of SMRAM.
-  @retval EFI_DEVICE_ERROR  SMRAM cannot be closed.
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_SMM_CLOSE2)(
-  IN EFI_SMM_ACCESS2_PROTOCOL  *This
-  );
-
-/**
-  Inhibits access to the SMRAM.
-
-  This function prohibits access to the SMRAM region.  This function is usually implemented such 
-  that it is a write-once operation. 
+typedef EFI_MM_OPEN EFI_SMM_OPEN2;
 
-  @param[in] This          The EFI_SMM_ACCESS2_PROTOCOL instance.
-
-  @retval EFI_SUCCESS      The device was successfully locked.
-  @retval EFI_UNSUPPORTED  The system does not support locking of SMRAM.
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_SMM_LOCK2)(
-  IN EFI_SMM_ACCESS2_PROTOCOL  *This
-  );
-
-/**
-  Queries the memory controller for the possible regions that will support SMRAM.
-
-  @param[in]     This           The EFI_SMM_ACCESS2_PROTOCOL instance.
-  @param[in,out] SmramMapSize   A pointer to the size, in bytes, of the SmramMemoryMap buffer.
-  @param[in,out] SmramMap       A pointer to the buffer in which firmware places the current memory map.
-
-  @retval EFI_SUCCESS           The chipset supported the given resource.
-  @retval EFI_BUFFER_TOO_SMALL  The SmramMap parameter was too small.  The current buffer size 
-                                needed to hold the memory map is returned in SmramMapSize.
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_SMM_CAPABILITIES2)(
-  IN CONST EFI_SMM_ACCESS2_PROTOCOL  *This,
-  IN OUT UINTN                       *SmramMapSize,
-  IN OUT EFI_SMRAM_DESCRIPTOR        *SmramMap
-  );
+typedef EFI_MM_CLOSE EFI_SMM_CLOSE2;
 
-///
-///  EFI SMM Access2 Protocol is used to control the visibility of the SMRAM on the platform.
-///  It abstracts the location and characteristics of SMRAM.  The expectation is
-///  that the north bridge or memory controller would publish this protocol.
-/// 
-struct _EFI_SMM_ACCESS2_PROTOCOL {
-  EFI_SMM_OPEN2          Open;
-  EFI_SMM_CLOSE2         Close;
-  EFI_SMM_LOCK2          Lock;
-  EFI_SMM_CAPABILITIES2  GetCapabilities;
-  ///
-  /// Indicates the current state of the SMRAM. Set to TRUE if SMRAM is locked.
-  ///
-  BOOLEAN               LockState;
-  ///
-  /// Indicates the current state of the SMRAM. Set to TRUE if SMRAM is open.
-  ///
-  BOOLEAN               OpenState;
-};
+typedef EFI_MM_LOCK EFI_SMM_LOCK2;
 
+typedef EFI_MM_CAPABILITIES EFI_SMM_CAPABILITIES2;
 extern EFI_GUID gEfiSmmAccess2ProtocolGuid;
 
 #endif
diff --git a/MdePkg/Include/Protocol/SmmBase2.h b/MdePkg/Include/Protocol/SmmBase2.h
index 3a1947c43870..492f4001221d 100644
--- a/MdePkg/Include/Protocol/SmmBase2.h
+++ b/MdePkg/Include/Protocol/SmmBase2.h
@@ -4,14 +4,8 @@
   This protocol is utilized by all SMM drivers to locate the SMM infrastructure services and determine
   whether the driver is being invoked inside SMRAM or outside of SMRAM.
 
-  Copyright (c) 2009, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -19,23 +13,21 @@
 #define _SMM_BASE2_H_
 
 #include <Pi/PiSmmCis.h>
+#include <Protocol/MmBase.h>
 
-#define EFI_SMM_BASE2_PROTOCOL_GUID \
-  { \
-    0xf4ccbfb7, 0xf6e0, 0x47fd, {0x9d, 0xd4, 0x10, 0xa8, 0xf1, 0x50, 0xc1, 0x91 }  \
-  }
+#define EFI_SMM_BASE2_PROTOCOL_GUID  EFI_MM_BASE_PROTOCOL_GUID
 
 typedef struct _EFI_SMM_BASE2_PROTOCOL  EFI_SMM_BASE2_PROTOCOL;
 
 /**
   Service to indicate whether the driver is currently executing in the SMM Initialization phase.
-  
-  This service is used to indicate whether the driver is currently executing in the SMM Initialization 
-  phase. For SMM drivers, this will return TRUE in InSmram while inside the driver's entry point and 
+
+  This service is used to indicate whether the driver is currently executing in the SMM Initialization
+  phase. For SMM drivers, this will return TRUE in InSmram while inside the driver's entry point and
   otherwise FALSE. For combination SMM/DXE drivers, this will return FALSE in the DXE launch. For the
   SMM launch, it behaves as an SMM driver.
 
-  @param[in]  This               The EFI_SMM_BASE2_PROTOCOL instance. 
+  @param[in]  This               The EFI_SMM_BASE2_PROTOCOL instance.
   @param[out] InSmram            Pointer to a Boolean which, on return, indicates that the driver is
                                  currently executing inside of SMRAM (TRUE) or outside of SMRAM (FALSE).
 
@@ -53,8 +45,8 @@ EFI_STATUS
 /**
   Returns the location of the System Management Service Table (SMST).
 
-  This function returns the location of the System Management Service Table (SMST).  The use of the 
-  API is such that a driver can discover the location of the SMST in its entry point and then cache it in 
+  This function returns the location of the System Management Service Table (SMST).  The use of the
+  API is such that a driver can discover the location of the SMST in its entry point and then cache it in
   some driver global variable so that the SMST can be invoked in subsequent handlers.
 
   @param[in]     This            The EFI_SMM_BASE2_PROTOCOL instance.
diff --git a/MdePkg/Include/Protocol/SmmCommunication.h b/MdePkg/Include/Protocol/SmmCommunication.h
index acd7a27d6ec5..13b0d29e4b59 100644
--- a/MdePkg/Include/Protocol/SmmCommunication.h
+++ b/MdePkg/Include/Protocol/SmmCommunication.h
@@ -1,63 +1,25 @@
 /** @file
   EFI SMM Communication Protocol as defined in the PI 1.2 specification.
 
-  This protocol provides a means of communicating between drivers outside of SMM and SMI 
-  handlers inside of SMM.  
+  This protocol provides a means of communicating between drivers outside of SMM and SMI
+  handlers inside of SMM.
 
-  Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
 #ifndef _SMM_COMMUNICATION_H_
 #define _SMM_COMMUNICATION_H_
 
-//
-// Need include this header file for EFI_SMM_COMMUNICATE_HEADER data structure.
-//
-#include <Uefi/UefiAcpiDataTable.h>
-
-#define EFI_SMM_COMMUNICATION_PROTOCOL_GUID \
-  { \
-    0xc68ed8e2, 0x9dc6, 0x4cbd, { 0x9d, 0x94, 0xdb, 0x65, 0xac, 0xc5, 0xc3, 0x32 } \
-  }
+#include <Protocol/MmCommunication.h>
 
-typedef struct _EFI_SMM_COMMUNICATION_PROTOCOL  EFI_SMM_COMMUNICATION_PROTOCOL;
 
-/**
-  Communicates with a registered handler.
-  
-  This function provides a service to send and receive messages from a registered UEFI service.
+typedef EFI_MM_COMMUNICATE_HEADER EFI_SMM_COMMUNICATE_HEADER;
 
-  @param[in] This                The EFI_SMM_COMMUNICATION_PROTOCOL instance.
-  @param[in] CommBuffer          A pointer to the buffer to convey into SMRAM.
-  @param[in] CommSize            The size of the data buffer being passed in.On exit, the size of data
-                                 being returned. Zero if the handler does not wish to reply with any data.
-
-  @retval EFI_SUCCESS            The message was successfully posted.
-  @retval EFI_INVALID_PARAMETER  The CommBuffer was NULL.
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_SMM_COMMUNICATE2)(
-  IN CONST EFI_SMM_COMMUNICATION_PROTOCOL  *This,
-  IN OUT VOID                              *CommBuffer,
-  IN OUT UINTN                             *CommSize
-  );
+#define EFI_SMM_COMMUNICATION_PROTOCOL_GUID EFI_MM_COMMUNICATION_PROTOCOL_GUID
 
-///
-/// EFI SMM Communication Protocol provides runtime services for communicating
-/// between DXE drivers and a registered SMI handler.
-///
-struct _EFI_SMM_COMMUNICATION_PROTOCOL {
-  EFI_SMM_COMMUNICATE2  Communicate;
-};
+typedef EFI_MM_COMMUNICATION_PROTOCOL EFI_SMM_COMMUNICATION_PROTOCOL;
 
 extern EFI_GUID gEfiSmmCommunicationProtocolGuid;
 
diff --git a/MdePkg/Include/Protocol/SmmConfiguration.h b/MdePkg/Include/Protocol/SmmConfiguration.h
index f138fde877ee..af6d380947ca 100644
--- a/MdePkg/Include/Protocol/SmmConfiguration.h
+++ b/MdePkg/Include/Protocol/SmmConfiguration.h
@@ -5,39 +5,31 @@
   1) report the portions of SMRAM regions which cannot be used for the SMRAM heap.
   2) register the SMM Foundation entry point with the processor code. The entry
      point will be invoked by the SMM processor entry code.
-  
-  Copyright (c) 2009, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
 #ifndef _SMM_CONFIGURATION_H_
 #define _SMM_CONFIGURATION_H_
 
+#include <Protocol/MmConfiguration.h>
 #include <Pi/PiSmmCis.h>
 
-#define EFI_SMM_CONFIGURATION_PROTOCOL_GUID \
-  { \
-    0x26eeb3de, 0xb689, 0x492e, {0x80, 0xf0, 0xbe, 0x8b, 0xd7, 0xda, 0x4b, 0xa7 }  \
-  }
+#define EFI_SMM_CONFIGURATION_PROTOCOL_GUID EFI_MM_CONFIGURATION_PROTOCOL_GUID
 
 ///
 /// Structure describing a SMRAM region which cannot be used for the SMRAM heap.
 ///
 typedef struct _EFI_SMM_RESERVED_SMRAM_REGION {
   ///
-  /// Starting address of the reserved SMRAM area, as it appears while SMRAM is open. 
+  /// Starting address of the reserved SMRAM area, as it appears while SMRAM is open.
   /// Ignored if SmramReservedSize is 0.
   ///
   EFI_PHYSICAL_ADDRESS    SmramReservedStart;
   ///
-  /// Number of bytes occupied by the reserved SMRAM area. A size of zero indicates the 
+  /// Number of bytes occupied by the reserved SMRAM area. A size of zero indicates the
   /// last SMRAM area.
   ///
   UINT64                  SmramReservedSize;
@@ -47,13 +39,13 @@ typedef struct _EFI_SMM_CONFIGURATION_PROTOCOL  EFI_SMM_CONFIGURATION_PROTOCOL;
 
 /**
   Register the SMM Foundation entry point.
-  
-  This function registers the SMM Foundation entry point with the processor code. This entry point 
+
+  This function registers the SMM Foundation entry point with the processor code. This entry point
   will be invoked by the SMM Processor entry code.
 
   @param[in] This                The EFI_SMM_CONFIGURATION_PROTOCOL instance.
   @param[in] SmmEntryPoint       SMM Foundation entry point.
-  
+
   @retval EFI_SUCCESS            Success to register SMM Entry Point.
   @retval EFI_INVALID_PARAMETER  SmmEntryPoint is NULL.
 **/
@@ -66,10 +58,10 @@ EFI_STATUS
 
 ///
 /// The EFI SMM Configuration Protocol is a mandatory protocol published by a DXE CPU driver to
-/// indicate which areas within SMRAM are reserved for use by the CPU for any purpose, 
+/// indicate which areas within SMRAM are reserved for use by the CPU for any purpose,
 /// such as stack, save state or SMM entry point.
 ///
-/// The RegisterSmmEntry() function allows the SMM IPL DXE driver to register the SMM 
+/// The RegisterSmmEntry() function allows the SMM IPL DXE driver to register the SMM
 /// Foundation entry point with the SMM entry vector code.
 ///
 struct _EFI_SMM_CONFIGURATION_PROTOCOL {
diff --git a/MdePkg/Include/Protocol/SmmControl2.h b/MdePkg/Include/Protocol/SmmControl2.h
index 5908fef945a4..d75efeed4297 100644
--- a/MdePkg/Include/Protocol/SmmControl2.h
+++ b/MdePkg/Include/Protocol/SmmControl2.h
@@ -3,103 +3,32 @@
 
   This protocol is used initiate synchronous SMI activations. This protocol could be published by a
   processor driver to abstract the SMI IPI or a driver which abstracts the ASIC that is supporting the
-  APM port. Because of the possibility of performing SMI IPI transactions, the ability to generate this 
+  APM port. Because of the possibility of performing SMI IPI transactions, the ability to generate this
   event from a platform chipset agent is an optional capability for both IA-32 and x64-based systems.
 
-  The EFI_SMM_CONTROL2_PROTOCOL is produced by a runtime driver. It provides  an 
-  abstraction of the platform hardware that generates an SMI.  There are often I/O ports that, when 
-  accessed, will generate the SMI.  Also, the hardware optionally supports the periodic generation of 
+  The EFI_SMM_CONTROL2_PROTOCOL is produced by a runtime driver. It provides  an
+  abstraction of the platform hardware that generates an SMI.  There are often I/O ports that, when
+  accessed, will generate the SMI.  Also, the hardware optionally supports the periodic generation of
   these signals.
 
-  Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
 #ifndef _SMM_CONTROL2_H_
 #define _SMM_CONTROL2_H_
 
-#include <PiDxe.h>
-
-#define EFI_SMM_CONTROL2_PROTOCOL_GUID \
-  { \
-    0x843dc720, 0xab1e, 0x42cb, {0x93, 0x57, 0x8a, 0x0, 0x78, 0xf3, 0x56, 0x1b}  \
-  }
-
-typedef struct _EFI_SMM_CONTROL2_PROTOCOL  EFI_SMM_CONTROL2_PROTOCOL;
-typedef UINTN  EFI_SMM_PERIOD;
+#include <Protocol/MmControl.h>
 
-/**
-  Invokes SMI activation from either the preboot or runtime environment.
+#define EFI_SMM_CONTROL2_PROTOCOL_GUID EFI_MM_CONTROL_PROTOCOL_GUID
 
-  This function generates an SMI.
-
-  @param[in]     This                The EFI_SMM_CONTROL2_PROTOCOL instance.
-  @param[in,out] CommandPort         The value written to the command port.
-  @param[in,out] DataPort            The value written to the data port.
-  @param[in]     Periodic            Optional mechanism to engender a periodic stream.
-  @param[in]     ActivationInterval  Optional parameter to repeat at this period one
-                                     time or, if the Periodic Boolean is set, periodically.
-
-  @retval EFI_SUCCESS            The SMI/PMI has been engendered.
-  @retval EFI_DEVICE_ERROR       The timing is unsupported.
-  @retval EFI_INVALID_PARAMETER  The activation period is unsupported.
-  @retval EFI_INVALID_PARAMETER  The last periodic activation has not been cleared. 
-  @retval EFI_NOT_STARTED        The SMM base service has not been initialized.
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_SMM_ACTIVATE2)(
-  IN CONST EFI_SMM_CONTROL2_PROTOCOL  *This,
-  IN OUT UINT8                        *CommandPort       OPTIONAL,
-  IN OUT UINT8                        *DataPort          OPTIONAL,
-  IN BOOLEAN                          Periodic           OPTIONAL,
-  IN UINTN                            ActivationInterval OPTIONAL
-  );
-
-/**
-  Clears any system state that was created in response to the Trigger() call.
-
-  This function acknowledges and causes the deassertion of the SMI activation source.
-
-  @param[in] This                The EFI_SMM_CONTROL2_PROTOCOL instance.
-  @param[in] Periodic            Optional parameter to repeat at this period one time
-
-  @retval EFI_SUCCESS            The SMI/PMI has been engendered.
-  @retval EFI_DEVICE_ERROR       The source could not be cleared.
-  @retval EFI_INVALID_PARAMETER  The service did not support the Periodic input argument.
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_SMM_DEACTIVATE2)(
-  IN CONST EFI_SMM_CONTROL2_PROTOCOL  *This,
-  IN BOOLEAN                          Periodic OPTIONAL
-  );
+typedef EFI_MM_CONTROL_PROTOCOL  EFI_SMM_CONTROL2_PROTOCOL;
+typedef EFI_MM_PERIOD  EFI_SMM_PERIOD;
 
-///
-/// The EFI_SMM_CONTROL2_PROTOCOL is produced by a runtime driver. It provides  an 
-/// abstraction of the platform hardware that generates an SMI.  There are often I/O ports that, when 
-/// accessed, will generate the SMI.  Also, the hardware optionally supports the periodic generation of 
-/// these signals.
-///
-struct _EFI_SMM_CONTROL2_PROTOCOL {
-  EFI_SMM_ACTIVATE2    Trigger;
-  EFI_SMM_DEACTIVATE2  Clear;
-  ///
-  /// Minimum interval at which the platform can set the period.  A maximum is not 
-  /// specified in that the SMM infrastructure code can emulate a maximum interval that is 
-  /// greater than the hardware capabilities by using software emulation in the SMM 
-  /// infrastructure code.
-  ///
-  EFI_SMM_PERIOD      MinimumTriggerPeriod;
-};
+typedef EFI_MM_ACTIVATE EFI_SMM_ACTIVATE2;
 
+typedef EFI_MM_DEACTIVATE EFI_SMM_DEACTIVATE2;
 extern EFI_GUID gEfiSmmControl2ProtocolGuid;
 
 #endif
diff --git a/MdePkg/Include/Protocol/SmmCpu.h b/MdePkg/Include/Protocol/SmmCpu.h
index 9990dd25adfa..62144fd55fe8 100644
--- a/MdePkg/Include/Protocol/SmmCpu.h
+++ b/MdePkg/Include/Protocol/SmmCpu.h
@@ -1,246 +1,129 @@
 /** @file
   EFI SMM CPU Protocol as defined in the PI 1.2 specification.
 
-  This protocol allows SMM drivers to access architecture-standard registers from any of the CPU 
-  save state areas. In some cases, difference processors provide the same information in the save state, 
-  but not in the same format. These so-called pseudo-registers provide this information in a standard 
-  format.  
+  This protocol allows SMM drivers to access architecture-standard registers from any of the CPU
+  save state areas. In some cases, difference processors provide the same information in the save state,
+  but not in the same format. These so-called pseudo-registers provide this information in a standard
+  format.
 
-  Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
 #ifndef _SMM_CPU_H_
 #define _SMM_CPU_H_
 
-#define EFI_SMM_CPU_PROTOCOL_GUID \
-  { \
-    0xeb346b97, 0x975f, 0x4a9f, { 0x8b, 0x22, 0xf8, 0xe9, 0x2b, 0xb3, 0xd5, 0x69 } \
-  }
-
-///
-/// Save State register index
-///
-typedef enum {
-  ///
-  /// x86/X64 standard registers
-  ///
-  EFI_SMM_SAVE_STATE_REGISTER_GDTBASE       = 4,
-  EFI_SMM_SAVE_STATE_REGISTER_IDTBASE       = 5,
-  EFI_SMM_SAVE_STATE_REGISTER_LDTBASE       = 6,
-  EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT      = 7,
-  EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT      = 8,
-  EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT      = 9,
-  EFI_SMM_SAVE_STATE_REGISTER_LDTINFO       = 10,
-  EFI_SMM_SAVE_STATE_REGISTER_ES            = 20,
-  EFI_SMM_SAVE_STATE_REGISTER_CS            = 21,
-  EFI_SMM_SAVE_STATE_REGISTER_SS            = 22,
-  EFI_SMM_SAVE_STATE_REGISTER_DS            = 23,
-  EFI_SMM_SAVE_STATE_REGISTER_FS            = 24,
-  EFI_SMM_SAVE_STATE_REGISTER_GS            = 25,
-  EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL      = 26,
-  EFI_SMM_SAVE_STATE_REGISTER_TR_SEL        = 27,
-  EFI_SMM_SAVE_STATE_REGISTER_DR7           = 28,
-  EFI_SMM_SAVE_STATE_REGISTER_DR6           = 29,
-  EFI_SMM_SAVE_STATE_REGISTER_R8            = 30,
-  EFI_SMM_SAVE_STATE_REGISTER_R9            = 31,
-  EFI_SMM_SAVE_STATE_REGISTER_R10           = 32,
-  EFI_SMM_SAVE_STATE_REGISTER_R11           = 33,
-  EFI_SMM_SAVE_STATE_REGISTER_R12           = 34,
-  EFI_SMM_SAVE_STATE_REGISTER_R13           = 35,
-  EFI_SMM_SAVE_STATE_REGISTER_R14           = 36,
-  EFI_SMM_SAVE_STATE_REGISTER_R15           = 37,  
-  EFI_SMM_SAVE_STATE_REGISTER_RAX           = 38,
-  EFI_SMM_SAVE_STATE_REGISTER_RBX           = 39,
-  EFI_SMM_SAVE_STATE_REGISTER_RCX           = 40,
-  EFI_SMM_SAVE_STATE_REGISTER_RDX           = 41,
-  EFI_SMM_SAVE_STATE_REGISTER_RSP           = 42,
-  EFI_SMM_SAVE_STATE_REGISTER_RBP           = 43,
-  EFI_SMM_SAVE_STATE_REGISTER_RSI           = 44,
-  EFI_SMM_SAVE_STATE_REGISTER_RDI           = 45,
-  EFI_SMM_SAVE_STATE_REGISTER_RIP           = 46,
-  EFI_SMM_SAVE_STATE_REGISTER_RFLAGS        = 51,
-  EFI_SMM_SAVE_STATE_REGISTER_CR0           = 52,
-  EFI_SMM_SAVE_STATE_REGISTER_CR3           = 53,
-  EFI_SMM_SAVE_STATE_REGISTER_CR4           = 54,
-  EFI_SMM_SAVE_STATE_REGISTER_FCW           = 256,
-  EFI_SMM_SAVE_STATE_REGISTER_FSW           = 257,
-  EFI_SMM_SAVE_STATE_REGISTER_FTW           = 258,  
-  EFI_SMM_SAVE_STATE_REGISTER_OPCODE        = 259,
-  EFI_SMM_SAVE_STATE_REGISTER_FP_EIP        = 260,
-  EFI_SMM_SAVE_STATE_REGISTER_FP_CS         = 261,
-  EFI_SMM_SAVE_STATE_REGISTER_DATAOFFSET    = 262,
-  EFI_SMM_SAVE_STATE_REGISTER_FP_DS         = 263,
-  EFI_SMM_SAVE_STATE_REGISTER_MM0           = 264,
-  EFI_SMM_SAVE_STATE_REGISTER_MM1           = 265,
-  EFI_SMM_SAVE_STATE_REGISTER_MM2           = 266,
-  EFI_SMM_SAVE_STATE_REGISTER_MM3           = 267,
-  EFI_SMM_SAVE_STATE_REGISTER_MM4           = 268,
-  EFI_SMM_SAVE_STATE_REGISTER_MM5           = 269,
-  EFI_SMM_SAVE_STATE_REGISTER_MM6           = 270,
-  EFI_SMM_SAVE_STATE_REGISTER_MM7           = 271,
-  EFI_SMM_SAVE_STATE_REGISTER_XMM0          = 272,
-  EFI_SMM_SAVE_STATE_REGISTER_XMM1          = 273,
-  EFI_SMM_SAVE_STATE_REGISTER_XMM2          = 274,
-  EFI_SMM_SAVE_STATE_REGISTER_XMM3          = 275,
-  EFI_SMM_SAVE_STATE_REGISTER_XMM4          = 276,
-  EFI_SMM_SAVE_STATE_REGISTER_XMM5          = 277,
-  EFI_SMM_SAVE_STATE_REGISTER_XMM6          = 278,
-  EFI_SMM_SAVE_STATE_REGISTER_XMM7          = 279,
-  EFI_SMM_SAVE_STATE_REGISTER_XMM8          = 280,
-  EFI_SMM_SAVE_STATE_REGISTER_XMM9          = 281,
-  EFI_SMM_SAVE_STATE_REGISTER_XMM10         = 282,
-  EFI_SMM_SAVE_STATE_REGISTER_XMM11         = 283,
-  EFI_SMM_SAVE_STATE_REGISTER_XMM12         = 284,
-  EFI_SMM_SAVE_STATE_REGISTER_XMM13         = 285,
-  EFI_SMM_SAVE_STATE_REGISTER_XMM14         = 286,
-  EFI_SMM_SAVE_STATE_REGISTER_XMM15         = 287,  
-  ///
-  /// Pseudo-Registers
-  ///
-  EFI_SMM_SAVE_STATE_REGISTER_IO            = 512,
-  EFI_SMM_SAVE_STATE_REGISTER_LMA           = 513,
-  EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID  = 514
-} EFI_SMM_SAVE_STATE_REGISTER;  
+#include <Protocol/MmCpu.h>
+
+#define EFI_SMM_CPU_PROTOCOL_GUID  EFI_MM_CPU_PROTOCOL_GUID
+
+#define EFI_SMM_SAVE_STATE_REGISTER_GDTBASE       EFI_MM_SAVE_STATE_REGISTER_GDTBASE
+#define EFI_SMM_SAVE_STATE_REGISTER_IDTBASE       EFI_MM_SAVE_STATE_REGISTER_IDTBASE
+#define EFI_SMM_SAVE_STATE_REGISTER_LDTBASE       EFI_MM_SAVE_STATE_REGISTER_LDTBASE
+#define EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT      EFI_MM_SAVE_STATE_REGISTER_GDTLIMIT
+#define EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT      EFI_MM_SAVE_STATE_REGISTER_IDTLIMIT
+#define EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT      EFI_MM_SAVE_STATE_REGISTER_LDTLIMIT
+#define EFI_SMM_SAVE_STATE_REGISTER_LDTINFO       EFI_MM_SAVE_STATE_REGISTER_LDTINFO
+#define EFI_SMM_SAVE_STATE_REGISTER_ES            EFI_MM_SAVE_STATE_REGISTER_ES
+#define EFI_SMM_SAVE_STATE_REGISTER_CS            EFI_MM_SAVE_STATE_REGISTER_CS
+#define EFI_SMM_SAVE_STATE_REGISTER_SS            EFI_MM_SAVE_STATE_REGISTER_SS
+#define EFI_SMM_SAVE_STATE_REGISTER_DS            EFI_MM_SAVE_STATE_REGISTER_DS
+#define EFI_SMM_SAVE_STATE_REGISTER_FS            EFI_MM_SAVE_STATE_REGISTER_FS
+#define EFI_SMM_SAVE_STATE_REGISTER_GS            EFI_MM_SAVE_STATE_REGISTER_GS
+#define EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL      EFI_MM_SAVE_STATE_REGISTER_LDTR_SEL
+#define EFI_SMM_SAVE_STATE_REGISTER_TR_SEL        EFI_MM_SAVE_STATE_REGISTER_TR_SEL
+#define EFI_SMM_SAVE_STATE_REGISTER_DR7           EFI_MM_SAVE_STATE_REGISTER_DR7
+#define EFI_SMM_SAVE_STATE_REGISTER_DR6           EFI_MM_SAVE_STATE_REGISTER_DR6
+#define EFI_SMM_SAVE_STATE_REGISTER_R8            EFI_MM_SAVE_STATE_REGISTER_R8
+#define EFI_SMM_SAVE_STATE_REGISTER_R9            EFI_MM_SAVE_STATE_REGISTER_R9
+#define EFI_SMM_SAVE_STATE_REGISTER_R10           EFI_MM_SAVE_STATE_REGISTER_R10
+#define EFI_SMM_SAVE_STATE_REGISTER_R11           EFI_MM_SAVE_STATE_REGISTER_R11
+#define EFI_SMM_SAVE_STATE_REGISTER_R12           EFI_MM_SAVE_STATE_REGISTER_R12
+#define EFI_SMM_SAVE_STATE_REGISTER_R13           EFI_MM_SAVE_STATE_REGISTER_R13
+#define EFI_SMM_SAVE_STATE_REGISTER_R14           EFI_MM_SAVE_STATE_REGISTER_R14
+#define EFI_SMM_SAVE_STATE_REGISTER_R15           EFI_MM_SAVE_STATE_REGISTER_R15
+#define EFI_SMM_SAVE_STATE_REGISTER_RAX           EFI_MM_SAVE_STATE_REGISTER_RAX
+#define EFI_SMM_SAVE_STATE_REGISTER_RBX           EFI_MM_SAVE_STATE_REGISTER_RBX
+#define EFI_SMM_SAVE_STATE_REGISTER_RCX           EFI_MM_SAVE_STATE_REGISTER_RCX
+#define EFI_SMM_SAVE_STATE_REGISTER_RDX           EFI_MM_SAVE_STATE_REGISTER_RDX
+#define EFI_SMM_SAVE_STATE_REGISTER_RSP           EFI_MM_SAVE_STATE_REGISTER_RSP
+#define EFI_SMM_SAVE_STATE_REGISTER_RBP           EFI_MM_SAVE_STATE_REGISTER_RBP
+#define EFI_SMM_SAVE_STATE_REGISTER_RSI           EFI_MM_SAVE_STATE_REGISTER_RSI
+#define EFI_SMM_SAVE_STATE_REGISTER_RDI           EFI_MM_SAVE_STATE_REGISTER_RDI
+#define EFI_SMM_SAVE_STATE_REGISTER_RIP           EFI_MM_SAVE_STATE_REGISTER_RIP
+#define EFI_SMM_SAVE_STATE_REGISTER_RFLAGS        EFI_MM_SAVE_STATE_REGISTER_RFLAGS
+#define EFI_SMM_SAVE_STATE_REGISTER_CR0           EFI_MM_SAVE_STATE_REGISTER_CR0
+#define EFI_SMM_SAVE_STATE_REGISTER_CR3           EFI_MM_SAVE_STATE_REGISTER_CR3
+#define EFI_SMM_SAVE_STATE_REGISTER_CR4           EFI_MM_SAVE_STATE_REGISTER_CR4
+#define EFI_SMM_SAVE_STATE_REGISTER_FCW           EFI_MM_SAVE_STATE_REGISTER_FCW
+#define EFI_SMM_SAVE_STATE_REGISTER_FSW           EFI_MM_SAVE_STATE_REGISTER_FSW
+#define EFI_SMM_SAVE_STATE_REGISTER_FTW           EFI_MM_SAVE_STATE_REGISTER_FTW
+#define EFI_SMM_SAVE_STATE_REGISTER_OPCODE        EFI_MM_SAVE_STATE_REGISTER_OPCODE
+#define EFI_SMM_SAVE_STATE_REGISTER_FP_EIP        EFI_MM_SAVE_STATE_REGISTER_FP_EIP
+#define EFI_SMM_SAVE_STATE_REGISTER_FP_CS         EFI_MM_SAVE_STATE_REGISTER_FP_CS
+#define EFI_SMM_SAVE_STATE_REGISTER_DATAOFFSET    EFI_MM_SAVE_STATE_REGISTER_DATAOFFSET
+#define EFI_SMM_SAVE_STATE_REGISTER_FP_DS         EFI_MM_SAVE_STATE_REGISTER_FP_DS
+#define EFI_SMM_SAVE_STATE_REGISTER_MM0           EFI_MM_SAVE_STATE_REGISTER_MM0
+#define EFI_SMM_SAVE_STATE_REGISTER_MM1           EFI_MM_SAVE_STATE_REGISTER_MM1
+#define EFI_SMM_SAVE_STATE_REGISTER_MM2           EFI_MM_SAVE_STATE_REGISTER_MM2
+#define EFI_SMM_SAVE_STATE_REGISTER_MM3           EFI_MM_SAVE_STATE_REGISTER_MM3
+#define EFI_SMM_SAVE_STATE_REGISTER_MM4           EFI_MM_SAVE_STATE_REGISTER_MM4
+#define EFI_SMM_SAVE_STATE_REGISTER_MM5           EFI_MM_SAVE_STATE_REGISTER_MM5
+#define EFI_SMM_SAVE_STATE_REGISTER_MM6           EFI_MM_SAVE_STATE_REGISTER_MM6
+#define EFI_SMM_SAVE_STATE_REGISTER_MM7           EFI_MM_SAVE_STATE_REGISTER_MM7
+#define EFI_SMM_SAVE_STATE_REGISTER_XMM0          EFI_MM_SAVE_STATE_REGISTER_XMM0
+#define EFI_SMM_SAVE_STATE_REGISTER_XMM1          EFI_MM_SAVE_STATE_REGISTER_XMM1
+#define EFI_SMM_SAVE_STATE_REGISTER_XMM2          EFI_MM_SAVE_STATE_REGISTER_XMM2
+#define EFI_SMM_SAVE_STATE_REGISTER_XMM3          EFI_MM_SAVE_STATE_REGISTER_XMM3
+#define EFI_SMM_SAVE_STATE_REGISTER_XMM4          EFI_MM_SAVE_STATE_REGISTER_XMM4
+#define EFI_SMM_SAVE_STATE_REGISTER_XMM5          EFI_MM_SAVE_STATE_REGISTER_XMM5
+#define EFI_SMM_SAVE_STATE_REGISTER_XMM6          EFI_MM_SAVE_STATE_REGISTER_XMM6
+#define EFI_SMM_SAVE_STATE_REGISTER_XMM7          EFI_MM_SAVE_STATE_REGISTER_XMM7
+#define EFI_SMM_SAVE_STATE_REGISTER_XMM8          EFI_MM_SAVE_STATE_REGISTER_XMM8
+#define EFI_SMM_SAVE_STATE_REGISTER_XMM9          EFI_MM_SAVE_STATE_REGISTER_XMM9
+#define EFI_SMM_SAVE_STATE_REGISTER_XMM10         EFI_MM_SAVE_STATE_REGISTER_XMM10
+#define EFI_SMM_SAVE_STATE_REGISTER_XMM11         EFI_MM_SAVE_STATE_REGISTER_XMM11
+#define EFI_SMM_SAVE_STATE_REGISTER_XMM12         EFI_MM_SAVE_STATE_REGISTER_XMM12
+#define EFI_SMM_SAVE_STATE_REGISTER_XMM13         EFI_MM_SAVE_STATE_REGISTER_XMM13
+#define EFI_SMM_SAVE_STATE_REGISTER_XMM14         EFI_MM_SAVE_STATE_REGISTER_XMM14
+#define EFI_SMM_SAVE_STATE_REGISTER_XMM15         EFI_MM_SAVE_STATE_REGISTER_XMM15
+#define EFI_SMM_SAVE_STATE_REGISTER_IO            EFI_MM_SAVE_STATE_REGISTER_IO
+#define EFI_SMM_SAVE_STATE_REGISTER_LMA           EFI_MM_SAVE_STATE_REGISTER_LMA
+#define EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID  EFI_MM_SAVE_STATE_REGISTER_PROCESSOR_ID
+
+typedef EFI_MM_SAVE_STATE_REGISTER  EFI_SMM_SAVE_STATE_REGISTER;
+
+
+#define EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT EFI_MM_SAVE_STATE_REGISTER_LMA_32BIT
+#define EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT EFI_MM_SAVE_STATE_REGISTER_LMA_64BIT
 
-///
-/// The EFI_SMM_SAVE_STATE_REGISTER_LMA pseudo-register values
-/// If the processor acts in 32-bit mode at the time the SMI occurred, the pseudo register value 
-/// EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT is returned in Buffer. Otherwise, 
-/// EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT is returned in Buffer.
-///
-#define EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT  32
-#define EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT  64
 
 ///
 /// Size width of I/O instruction
 ///
-typedef enum {
-  EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8      = 0,
-  EFI_SMM_SAVE_STATE_IO_WIDTH_UINT16     = 1,
-  EFI_SMM_SAVE_STATE_IO_WIDTH_UINT32     = 2,
-  EFI_SMM_SAVE_STATE_IO_WIDTH_UINT64     = 3
-} EFI_SMM_SAVE_STATE_IO_WIDTH;
+#define EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 EFI_MM_SAVE_STATE_IO_WIDTH_UINT8
+#define EFI_SMM_SAVE_STATE_IO_WIDTH_UINT16 EFI_MM_SAVE_STATE_IO_WIDTH_UINT16
+#define EFI_SMM_SAVE_STATE_IO_WIDTH_UINT32 EFI_MM_SAVE_STATE_IO_WIDTH_UINT32
+#define EFI_SMM_SAVE_STATE_IO_WIDTH_UINT64 EFI_MM_SAVE_STATE_IO_WIDTH_UINT64
+typedef EFI_MM_SAVE_STATE_IO_WIDTH EFI_SMM_SAVE_STATE_IO_WIDTH;
 
 ///
 /// Types of I/O instruction
 ///
-typedef enum {
-  EFI_SMM_SAVE_STATE_IO_TYPE_INPUT       = 1,
-  EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT      = 2,
-  EFI_SMM_SAVE_STATE_IO_TYPE_STRING      = 4,
-  EFI_SMM_SAVE_STATE_IO_TYPE_REP_PREFIX  = 8
-} EFI_SMM_SAVE_STATE_IO_TYPE;
+#define EFI_SMM_SAVE_STATE_IO_TYPE_INPUT EFI_MM_SAVE_STATE_IO_TYPE_INPUT
+#define EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT EFI_MM_SAVE_STATE_IO_TYPE_OUTPUT
+#define EFI_SMM_SAVE_STATE_IO_TYPE_STRING EFI_MM_SAVE_STATE_IO_TYPE_STRING
+#define EFI_SMM_SAVE_STATE_IO_TYPE_REP_PREFIX EFI_MM_SAVE_STATE_IO_TYPE_REP_PREFIX
+typedef  EFI_MM_SAVE_STATE_IO_TYPE EFI_SMM_SAVE_STATE_IO_TYPE;
 
-///
-/// Structure of the data which is returned when ReadSaveState() is called with 
-/// EFI_SMM_SAVE_STATE_REGISTER_IO. If there was no I/O then ReadSaveState() will 
-/// return EFI_NOT_FOUND.
-///
-/// This structure describes the I/O operation which was in process when the SMI was generated.
-///
-typedef struct _EFI_SMM_SAVE_STATE_IO_INFO {
-  ///
-  /// For input instruction (IN, INS), this is data read before the SMI occurred. For output 
-  /// instructions (OUT, OUTS) this is data that was written before the SMI occurred. The 
-  /// width of the data is specified by IoWidth.
-  ///
-  UINT64                        IoData;
-  ///
-  /// The I/O port that was being accessed when the SMI was triggered.
-  ///
-  UINT16                        IoPort;
-  ///
-  /// Defines the size width (UINT8, UINT16, UINT32, UINT64) for IoData.
-  ///
-  EFI_SMM_SAVE_STATE_IO_WIDTH   IoWidth;
-  ///
-  /// Defines type of I/O instruction.
-  ///
-  EFI_SMM_SAVE_STATE_IO_TYPE    IoType;
-} EFI_SMM_SAVE_STATE_IO_INFO;
-  
-typedef struct _EFI_SMM_CPU_PROTOCOL  EFI_SMM_CPU_PROTOCOL;
-
-/**
-  Read data from the CPU save state.
-
-  This function is used to read the specified number of bytes of the specified register from the CPU 
-  save state of the specified CPU and place the value into the buffer. If the CPU does not support the
-  specified register Register, then EFI_NOT_FOUND  should be returned. If the CPU does not 
-  support the specified register width Width, then EFI_INVALID_PARAMETER is returned.
-
-  @param[in]  This               The EFI_SMM_CPU_PROTOCOL instance.
-  @param[in]  Width              The number of bytes to read from the CPU save state.
-  @param[in]  Register           Specifies the CPU register to read form the save state.
-  @param[in]  CpuIndex           Specifies the zero-based index of the CPU save state.
-  @param[out] Buffer             Upon return, this holds the CPU register value read from the save state.
-    
-  @retval EFI_SUCCESS            The register was read from Save State.
-  @retval EFI_NOT_FOUND          The register is not defined for the Save State of Processor.
-  @retval EFI_INVALID_PARAMETER  Input parameters are not valid, for example, Processor No or register width 
-                                 is not correct.This or Buffer is NULL.
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_SMM_READ_SAVE_STATE)(
-  IN CONST EFI_SMM_CPU_PROTOCOL   *This,
-  IN UINTN                        Width,
-  IN EFI_SMM_SAVE_STATE_REGISTER  Register,
-  IN UINTN                        CpuIndex,
-  OUT VOID                        *Buffer
-  );
-
-
-/**
-  Write data to the CPU save state.
-
-  This function is used to write the specified number of bytes of the specified register to the CPU save 
-  state of the specified CPU and place the value into the buffer. If the CPU does not support the 
-  specified register Register, then EFI_UNSUPPORTED should be returned. If the CPU does not 
-  support the specified register width Width, then EFI_INVALID_PARAMETER is returned.
-
-  @param[in]  This               The EFI_SMM_CPU_PROTOCOL instance.
-  @param[in]  Width              The number of bytes to write to the CPU save state.
-  @param[in]  Register           Specifies the CPU register to write to the save state.
-  @param[in]  CpuIndex           Specifies the zero-based index of the CPU save state.
-  @param[in]  Buffer             Upon entry, this holds the new CPU register value.
-  
-  @retval EFI_SUCCESS            The register was written to Save State.
-  @retval EFI_NOT_FOUND          The register is not defined for the Save State of Processor.
-  @retval EFI_INVALID_PARAMETER  Input parameters are not valid. For example: 
-                                 ProcessorIndex or Width is not correct.
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_SMM_WRITE_SAVE_STATE)(
-  IN CONST EFI_SMM_CPU_PROTOCOL   *This,
-  IN UINTN                        Width, 
-  IN EFI_SMM_SAVE_STATE_REGISTER  Register,
-  IN UINTN                        CpuIndex,
-  IN CONST VOID                   *Buffer
-  );
+typedef  EFI_MM_SAVE_STATE_IO_INFO EFI_SMM_SAVE_STATE_IO_INFO;
 
-///
-/// EFI SMM CPU Protocol provides access to CPU-related information while in SMM.
-///
-/// This protocol allows SMM drivers to access architecture-standard registers from any of the CPU 
-/// save state areas. In some cases, difference processors provide the same information in the save state, 
-/// but not in the same format. These so-called pseudo-registers provide this information in a standard 
-/// format.  
-///
-struct _EFI_SMM_CPU_PROTOCOL {
-  EFI_SMM_READ_SAVE_STATE   ReadSaveState;
-  EFI_SMM_WRITE_SAVE_STATE  WriteSaveState;
-};
+typedef  EFI_MM_CPU_PROTOCOL EFI_SMM_CPU_PROTOCOL;
+
+typedef EFI_MM_READ_SAVE_STATE EFI_SMM_READ_SAVE_STATE;
 
+typedef EFI_MM_WRITE_SAVE_STATE EFI_SMM_WRITE_SAVE_STATE;
 extern EFI_GUID gEfiSmmCpuProtocolGuid;
 
 #endif
diff --git a/MdePkg/Include/Protocol/SmmCpuIo2.h b/MdePkg/Include/Protocol/SmmCpuIo2.h
index b580faf3cb55..b9d12bca74ef 100644
--- a/MdePkg/Include/Protocol/SmmCpuIo2.h
+++ b/MdePkg/Include/Protocol/SmmCpuIo2.h
@@ -3,93 +3,32 @@
 
   This protocol provides CPU I/O and memory access within SMM.
 
-  Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
 #ifndef _SMM_CPU_IO2_H_
 #define _SMM_CPU_IO2_H_
 
-#define EFI_SMM_CPU_IO2_PROTOCOL_GUID \
-  { \
-    0x3242A9D8, 0xCE70, 0x4AA0, { 0x95, 0x5D, 0x5E, 0x7B, 0x14, 0x0D, 0xE4, 0xD2 } \
-  }
+#include <Protocol/MmCpuIo.h>
+
+#define EFI_SMM_CPU_IO2_PROTOCOL_GUID EFI_MM_CPU_IO_PROTOCOL_GUID
 
-typedef struct _EFI_SMM_CPU_IO2_PROTOCOL  EFI_SMM_CPU_IO2_PROTOCOL;
+typedef EFI_MM_CPU_IO_PROTOCOL  EFI_SMM_CPU_IO2_PROTOCOL;
 
 ///
 /// Width of the SMM CPU I/O operations
 ///
-typedef enum {
-  SMM_IO_UINT8  = 0,
-  SMM_IO_UINT16 = 1,
-  SMM_IO_UINT32 = 2,
-  SMM_IO_UINT64 = 3
-} EFI_SMM_IO_WIDTH;
-
-/**
-  Provides the basic memory and I/O interfaces used toabstract accesses to devices.
+#define SMM_IO_UINT8  MM_IO_UINT8
+#define SMM_IO_UINT16 MM_IO_UINT16
+#define SMM_IO_UINT32 MM_IO_UINT32
+#define SMM_IO_UINT64 MM_IO_UINT64
 
-  The I/O operations are carried out exactly as requested.  The caller is 
-  responsible for any alignment and I/O width issues that the bus, device, 
-  platform, or type of I/O might require.
+typedef EFI_MM_IO_WIDTH EFI_SMM_IO_WIDTH;
+typedef EFI_MM_CPU_IO EFI_SMM_CPU_IO2;
 
-  @param[in]      This     The EFI_SMM_CPU_IO2_PROTOCOL instance.
-  @param[in]      Width    Signifies the width of the I/O operations.
-  @param[in]      Address  The base address of the I/O operations.  The caller is 
-                           responsible for aligning the Address if required. 
-  @param[in]      Count    The number of I/O operations to perform.
-  @param[in,out]  Buffer   For read operations, the destination buffer to store 
-                           the results.  For write operations, the source buffer 
-                           from which to write data.
-
-  @retval EFI_SUCCESS            The data was read from or written to the device.
-  @retval EFI_UNSUPPORTED        The Address is not valid for this system.
-  @retval EFI_INVALID_PARAMETER  Width or Count, or both, were invalid.
-  @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack
-                                 of resources.
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_SMM_CPU_IO2)(
-  IN     CONST EFI_SMM_CPU_IO2_PROTOCOL  *This,
-  IN     EFI_SMM_IO_WIDTH                Width,
-  IN     UINT64                          Address,
-  IN     UINTN                           Count,
-  IN OUT VOID                            *Buffer
-  );
-
-typedef struct {
-  ///
-  /// This service provides the various modalities of memory and I/O read.
-  ///
-  EFI_SMM_CPU_IO2  Read;
-  ///
-  /// This service provides the various modalities of memory and I/O write.
-  ///
-  EFI_SMM_CPU_IO2  Write;
-} EFI_SMM_IO_ACCESS2;
-
-///
-/// SMM CPU I/O Protocol provides CPU I/O and memory access within SMM.
-///
-struct _EFI_SMM_CPU_IO2_PROTOCOL {
-  ///
-  /// Allows reads and writes to memory-mapped I/O space.
-  ///
-  EFI_SMM_IO_ACCESS2 Mem;
-  ///
-  /// Allows reads and writes to I/O space.
-  ///
-  EFI_SMM_IO_ACCESS2 Io;
-};
+typedef EFI_MM_IO_ACCESS EFI_SMM_IO_ACCESS2;
 
 extern EFI_GUID gEfiSmmCpuIo2ProtocolGuid;
 
diff --git a/MdePkg/Include/Protocol/SmmEndOfDxe.h b/MdePkg/Include/Protocol/SmmEndOfDxe.h
index 3f92ffc40cc3..aa693ef3eb93 100644
--- a/MdePkg/Include/Protocol/SmmEndOfDxe.h
+++ b/MdePkg/Include/Protocol/SmmEndOfDxe.h
@@ -9,24 +9,17 @@
   This protocol prorogates End of DXE notification into SMM environment.
   This protocol is installed prior to installation of the SMM Ready to Lock Protocol.
 
-  Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2012 - 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
 #ifndef _SMM_END_OF_DXE_H_
 #define _SMM_END_OF_DXE_H_
 
-#define EFI_SMM_END_OF_DXE_PROTOCOL_GUID \
-  { \
-    0x24e70042, 0xd5c5, 0x4260, { 0x8c, 0x39, 0xa, 0xd3, 0xaa, 0x32, 0xe9, 0x3d } \
-  }
+#include <Protocol/MmEndOfDxe.h>
+
+#define EFI_SMM_END_OF_DXE_PROTOCOL_GUID EFI_MM_END_OF_DXE_PROTOCOL_GUID
 
 extern EFI_GUID gEfiSmmEndOfDxeProtocolGuid;
 
diff --git a/MdePkg/Include/Protocol/SmmGpiDispatch2.h b/MdePkg/Include/Protocol/SmmGpiDispatch2.h
index da1868f446e6..2faec309f102 100644
--- a/MdePkg/Include/Protocol/SmmGpiDispatch2.h
+++ b/MdePkg/Include/Protocol/SmmGpiDispatch2.h
@@ -2,21 +2,15 @@
   SMM General Purpose Input (GPI) Dispatch2 Protocol as defined in PI 1.1 Specification
   Volume 4 System Management Mode Core Interface.
 
-  This protocol provides the parent dispatch service for the General Purpose Input 
+  This protocol provides the parent dispatch service for the General Purpose Input
   (GPI) SMI source generator.
 
-  The EFI_SMM_GPI_DISPATCH2_PROTOCOL provides the ability to install child handlers for the 
-  given event types.  Several inputs can be enabled.  This purpose of this interface is to generate an 
+  The EFI_SMM_GPI_DISPATCH2_PROTOCOL provides the ability to install child handlers for the
+  given event types.  Several inputs can be enabled.  This purpose of this interface is to generate an
   SMI in response to any of these inputs having a true value provided.
 
-  Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This protocol is from PI Version 1.1.
@@ -26,98 +20,22 @@
 #ifndef _SMM_GPI_DISPATCH2_H_
 #define _SMM_GPI_DISPATCH2_H_
 
+#include <Protocol/MmGpiDispatch.h>
 #include <Pi/PiSmmCis.h>
 
-#define EFI_SMM_GPI_DISPATCH2_PROTOCOL_GUID \
-  { \
-    0x25566b03, 0xb577, 0x4cbf, {0x95, 0x8c, 0xed, 0x66, 0x3e, 0xa2, 0x43, 0x80 } \
-  }
-
+#define EFI_SMM_GPI_DISPATCH2_PROTOCOL_GUID    EFI_MM_GPI_DISPATCH_PROTOCOL_GUID
 ///
 /// The dispatch function's context.
 ///
-typedef struct {
-  ///
-  /// A number from one of 2^64 possible GPIs that can generate an SMI. A
-  /// 0 corresponds to logical GPI[0]; 1 corresponds to logical GPI[1]; and
-  /// GpiNum of N corresponds to GPI[N], where N can span from 0 to 2^64-1.
-  ///
-  UINT64 GpiNum;
-} EFI_SMM_GPI_REGISTER_CONTEXT;
-
-typedef struct _EFI_SMM_GPI_DISPATCH2_PROTOCOL EFI_SMM_GPI_DISPATCH2_PROTOCOL;
-
-/**
-  Registers a child SMI source dispatch function with a parent SMM driver.
-
-  This service registers a function (DispatchFunction) which will be called when an SMI is 
-  generated because of one or more of the GPIs specified by RegisterContext. On return, 
-  DispatchHandle contains a unique handle which may be used later to unregister the function 
-  using UnRegister().
-  The DispatchFunction will be called with Context set to the same value as was passed into 
-  this function in RegisterContext and with CommBuffer pointing to another instance of 
-  EFI_SMM_GPI_REGISTER_CONTEXT describing the GPIs which actually caused the SMI and 
-  CommBufferSize pointing to the size of the structure.
-
-  @param[in]  This               Pointer to the EFI_SMM_GPI_DISPATCH2_PROTOCOL instance.
-  @param[in]  DispatchFunction   Function to register for handler when the specified GPI causes an SMI.
-  @param[in]  RegisterContext    Pointer to the dispatch function's context.
-                                 The caller fills this context in before calling
-                                 the register function to indicate to the register
-                                 function the GPI(s) for which the dispatch function
-                                 should be invoked.
-  @param[out] DispatchHandle     Handle generated by the dispatcher to track the
-                                 function instance.
-
-  @retval EFI_SUCCESS            The dispatch function has been successfully
-                                 registered and the SMI source has been enabled.
-  @retval EFI_DEVICE_ERROR       The driver was unable to enable the SMI source.
-  @retval EFI_INVALID_PARAMETER  RegisterContext is invalid. The GPI input value
-                                 is not within valid range.
-  @retval EFI_OUT_OF_RESOURCES   There is not enough memory (system or SMM) to manage this child.
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_SMM_GPI_REGISTER2)(
-  IN CONST EFI_SMM_GPI_DISPATCH2_PROTOCOL  *This,
-  IN       EFI_SMM_HANDLER_ENTRY_POINT2    DispatchFunction,
-  IN CONST EFI_SMM_GPI_REGISTER_CONTEXT    *RegisterContext,
-  OUT      EFI_HANDLE                      *DispatchHandle
-  );
-
-/**
-  Unregisters a General Purpose Input (GPI) service.
-
-  This service removes the handler associated with DispatchHandle so that it will no longer be 
-  called when the GPI triggers an SMI. 
-
-  @param[in]  This               Pointer to the EFI_SMM_GPI_DISPATCH2_PROTOCOL instance.
-  @param[in]  DispatchHandle     Handle of the service to remove.
-
-  @retval EFI_SUCCESS            Handle of the service to remove.
-  @retval EFI_INVALID_PARAMETER  The DispatchHandle was not valid.
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_SMM_GPI_UNREGISTER2)(
-  IN CONST EFI_SMM_GPI_DISPATCH2_PROTOCOL  *This,
-  IN       EFI_HANDLE                      DispatchHandle
-  );
+typedef EFI_MM_GPI_REGISTER_CONTEXT  EFI_SMM_GPI_REGISTER_CONTEXT;
+
+typedef EFI_MM_GPI_REGISTER EFI_SMM_GPI_REGISTER2;
+
+typedef EFI_MM_GPI_UNREGISTER EFI_SMM_GPI_UNREGISTER2;
+
+typedef EFI_MM_GPI_DISPATCH_PROTOCOL EFI_SMM_GPI_DISPATCH2_PROTOCOL;
+
 
-///
-/// Interface structure for the SMM GPI SMI Dispatch Protocol
-///
-/// The SMM GPI SMI Dispatch Protocol provides the parent dispatch service
-/// for the General Purpose Input (GPI) SMI source generator.
-///
-struct _EFI_SMM_GPI_DISPATCH2_PROTOCOL {
-  EFI_SMM_GPI_REGISTER2    Register;
-  EFI_SMM_GPI_UNREGISTER2  UnRegister;
-  ///
-  /// Denotes the maximum value of inputs that can have handlers attached.
-  ///
-  UINTN                   NumSupportedGpis;
-};
 
 extern EFI_GUID gEfiSmmGpiDispatch2ProtocolGuid;
 
diff --git a/MdePkg/Include/Protocol/SmmIoTrapDispatch2.h b/MdePkg/Include/Protocol/SmmIoTrapDispatch2.h
index f57ae522fa1b..a4aea7c6576e 100644
--- a/MdePkg/Include/Protocol/SmmIoTrapDispatch2.h
+++ b/MdePkg/Include/Protocol/SmmIoTrapDispatch2.h
@@ -4,14 +4,8 @@
 
   This protocol provides a parent dispatch service for IO trap SMI sources.
 
-  Copyright (c) 2009, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This protocol is from PI Version 1.1.
@@ -21,114 +15,31 @@
 #ifndef _SMM_IO_TRAP_DISPATCH2_H_
 #define _SMM_IO_TRAP_DISPATCH2_H_
 
-#include <Pi/PiSmmCis.h>
+#include <Protocol/MmIoTrapDispatch.h>
 
-#define EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL_GUID \
-  { \
-    0x58dc368d, 0x7bfa, 0x4e77, {0xab, 0xbc, 0xe, 0x29, 0x41, 0x8d, 0xf9, 0x30 } \
-  }
+#define EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL_GUID  EFI_MM_IO_TRAP_DISPATCH_PROTOCOL_GUID
 
 ///
 /// IO Trap valid types
 ///
-typedef enum {
-  WriteTrap,
-  ReadTrap,
-  ReadWriteTrap,
-  IoTrapTypeMaximum
-} EFI_SMM_IO_TRAP_DISPATCH_TYPE;
+typedef EFI_MM_IO_TRAP_DISPATCH_TYPE EFI_SMM_IO_TRAP_DISPATCH_TYPE;
 
 ///
 /// IO Trap context structure containing information about the
 /// IO trap event that should invoke the handler
 ///
-typedef struct {
-  UINT16                         Address;
-  UINT16                         Length;
-  EFI_SMM_IO_TRAP_DISPATCH_TYPE  Type;
-} EFI_SMM_IO_TRAP_REGISTER_CONTEXT;
+typedef EFI_MM_IO_TRAP_REGISTER_CONTEXT EFI_SMM_IO_TRAP_REGISTER_CONTEXT;
 
 ///
 /// IO Trap context structure containing information about the IO trap that occurred
 ///
-typedef struct {
-  UINT32  WriteData;
-} EFI_SMM_IO_TRAP_CONTEXT;
-
-typedef struct _EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL;
-
-/**
-  Register an IO trap SMI child handler for a specified SMI.
-
-  This service registers a function (DispatchFunction) which will be called when an SMI is 
-  generated because of an access to an I/O port specified by RegisterContext. On return, 
-  DispatchHandle contains a unique handle which may be used later to unregister the function 
-  using UnRegister(). If the base of the I/O range specified is zero, then an I/O range with the 
-  specified length and characteristics will be allocated and the Address field in RegisterContext 
-  updated. If no range could be allocated, then EFI_OUT_OF_RESOURCES will be returned. 
-
-  The service will not perform GCD allocation if the base address is non-zero or 
-  EFI_SMM_READY_TO_LOCK has been installed.  In this case, the caller is responsible for the 
-  existence and allocation of the specific IO range.
-  An error may be returned if some or all of the requested resources conflict with an existing IO trap 
-  child handler.
-
-  It is not required that implementations will allow multiple children for a single IO trap SMI source.  
-  Some implementations may support multiple children.
-  The DispatchFunction will be called with Context updated to contain information 
-  concerning the I/O action that actually happened and is passed in RegisterContext, with 
-  CommBuffer pointing to the data actually written and CommBufferSize pointing to the size of 
-  the data in CommBuffer.
-
-  @param[in]  This               Pointer to the EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL instance.
-  @param[in]  DispatchFunction   Function to register for handler when I/O trap location is accessed.
-  @param[in]  RegisterContext    Pointer to the dispatch function's context.  The caller fills this
-                                 context in before calling the register function to indicate to the register
-                                 function the IO trap SMI source for which the dispatch function should be invoked.
-  @param[out] DispatchHandle     Handle of the dispatch function, for when interfacing with the parent SMM driver.
-
-  @retval EFI_SUCCESS            The dispatch function has been successfully registered.
-  @retval EFI_DEVICE_ERROR       The driver was unable to complete due to hardware error.
-  @retval EFI_OUT_OF_RESOURCES   Insufficient resources are available to fulfill the IO trap range request.
-  @retval EFI_INVALID_PARAMETER  RegisterContext is invalid.  The input value is not within a valid range.
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_SMM_IO_TRAP_DISPATCH2_REGISTER)(
-  IN CONST EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL  *This,
-  IN       EFI_SMM_HANDLER_ENTRY_POINT2        DispatchFunction,
-  IN OUT   EFI_SMM_IO_TRAP_REGISTER_CONTEXT    *RegisterContext,
-     OUT   EFI_HANDLE                          *DispatchHandle
-  );
-
-/**
-  Unregister a child SMI source dispatch function with a parent SMM driver.
-
-  This service removes a previously installed child dispatch handler. This does not guarantee that the 
-  system resources will be freed from the GCD.
-
-  @param[in] This                Pointer to the EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL instance. 
-  @param[in] DispatchHandle      Handle of the child service to remove.
-
-  @retval EFI_SUCCESS            The dispatch function has been successfully unregistered.
-  @retval EFI_INVALID_PARAMETER  The DispatchHandle was not valid.
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_SMM_IO_TRAP_DISPATCH2_UNREGISTER)(
-  IN CONST EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL  *This,
-  IN       EFI_HANDLE                          DispatchHandle
-  );
+typedef EFI_MM_IO_TRAP_CONTEXT EFI_SMM_IO_TRAP_CONTEXT;
 
-///
-/// Interface structure for the SMM IO Trap Dispatch2 Protocol.
-///
-/// This protocol provides a parent dispatch service for IO trap SMI sources.
-///
-struct _EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL {
-  EFI_SMM_IO_TRAP_DISPATCH2_REGISTER    Register;
-  EFI_SMM_IO_TRAP_DISPATCH2_UNREGISTER  UnRegister;
-};
+typedef EFI_MM_IO_TRAP_DISPATCH_PROTOCOL EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL;
+
+typedef EFI_MM_IO_TRAP_DISPATCH_REGISTER   EFI_SMM_IO_TRAP_DISPATCH2_REGISTER;
+
+typedef EFI_MM_IO_TRAP_DISPATCH_UNREGISTER EFI_SMM_IO_TRAP_DISPATCH2_UNREGISTER;
 
 extern EFI_GUID gEfiSmmIoTrapDispatch2ProtocolGuid;
 
diff --git a/MdePkg/Include/Protocol/SmmPciRootBridgeIo.h b/MdePkg/Include/Protocol/SmmPciRootBridgeIo.h
index 847418f73c01..02109f8fd1f2 100644
--- a/MdePkg/Include/Protocol/SmmPciRootBridgeIo.h
+++ b/MdePkg/Include/Protocol/SmmPciRootBridgeIo.h
@@ -3,33 +3,24 @@
 
   This protocol provides PCI I/O and memory access within SMM.
 
-  Copyright (c) 2009, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
 #ifndef _SMM_PCI_ROOT_BRIDGE_IO_H_
 #define _SMM_PCI_ROOT_BRIDGE_IO_H_
 
-#include <Protocol/PciRootBridgeIo.h>
+#include <Protocol/MmPciRootBridgeIo.h>
 
-#define EFI_SMM_PCI_ROOT_BRIDGE_IO_PROTOCOL_GUID \
-  { \
-    0x8bc1714d, 0xffcb, 0x41c3, { 0x89, 0xdc, 0x6c, 0x74, 0xd0, 0x6d, 0x98, 0xea } \
-  }
+#define EFI_SMM_PCI_ROOT_BRIDGE_IO_PROTOCOL_GUID EFI_MM_PCI_ROOT_BRIDGE_IO_PROTOCOL_GUID
 
 ///
-/// This protocol provides the same functionality as the PCI Root Bridge I/O Protocol defined in the 
-/// UEFI 2.1 Specifcation, section 13.2, except that the functions for Map() and Unmap() may return 
+/// This protocol provides the same functionality as the PCI Root Bridge I/O Protocol defined in the
+/// UEFI 2.1 Specifcation, section 13.2, except that the functions for Map() and Unmap() may return
 /// EFI_UNSUPPORTED.
 ///
-typedef EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  EFI_SMM_PCI_ROOT_BRIDGE_IO_PROTOCOL;
+typedef EFI_MM_PCI_ROOT_BRIDGE_IO_PROTOCOL  EFI_SMM_PCI_ROOT_BRIDGE_IO_PROTOCOL;
 
 extern EFI_GUID gEfiSmmPciRootBridgeIoProtocolGuid;
 
diff --git a/MdePkg/Include/Protocol/SmmPeriodicTimerDispatch2.h b/MdePkg/Include/Protocol/SmmPeriodicTimerDispatch2.h
index d0aae046741f..a82ef427612d 100644
--- a/MdePkg/Include/Protocol/SmmPeriodicTimerDispatch2.h
+++ b/MdePkg/Include/Protocol/SmmPeriodicTimerDispatch2.h
@@ -4,14 +4,8 @@
 
   This protocol provides the parent dispatch service for the periodical timer SMI source generator.
 
-  Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This protocol is from PI Version 1.1.
@@ -22,11 +16,9 @@
 #define _SMM_PERIODIC_TIMER_DISPATCH2_H_
 
 #include <Pi/PiSmmCis.h>
+#include <Protocol/MmPeriodicTimerDispatch.h>
 
-#define EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL_GUID \
-  { \
-    0x4cec368e, 0x8e8e, 0x4d71, {0x8b, 0xe1, 0x95, 0x8c, 0x45, 0xfc, 0x8a, 0x53 } \
-  }
+#define EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL_GUID EFI_MM_PERIODIC_TIMER_DISPATCH_PROTOCOL_GUID
 
 ///
 /// Example: A chipset supports periodic SMIs on every 64ms or 2 seconds.
@@ -49,52 +41,46 @@
 ///
 typedef struct {
   ///
-  /// The minimum period of time in 100 nanosecond units that the child gets called. The 
+  /// The minimum period of time in 100 nanosecond units that the child gets called. The
   /// child will be called back after a time greater than the time Period.
   ///
   UINT64  Period;
   ///
-  /// The period of time interval between SMIs. Children of this interface should use this 
-  /// field when registering for periodic timer intervals when a finer granularity periodic 
+  /// The period of time interval between SMIs. Children of this interface should use this
+  /// field when registering for periodic timer intervals when a finer granularity periodic
   /// SMI is desired.
   ///
   UINT64  SmiTickInterval;
 } EFI_SMM_PERIODIC_TIMER_REGISTER_CONTEXT;
 
 ///
-/// The DispatchFunction will be called with Context set to the same value as was passed into 
-/// Register() in RegisterContext and with CommBuffer pointing to an instance of 
+/// The DispatchFunction will be called with Context set to the same value as was passed into
+/// Register() in RegisterContext and with CommBuffer pointing to an instance of
 /// EFI_SMM_PERIODIC_TIMER_CONTEXT and CommBufferSize pointing to its size.
 ///
-typedef struct {
-  ///
-  /// ElapsedTime is the actual time in 100 nanosecond units elapsed since last called, a
-  /// value of 0 indicates an unknown amount of time.
-  ///
-  UINT64  ElapsedTime;
-} EFI_SMM_PERIODIC_TIMER_CONTEXT;
+typedef EFI_MM_PERIODIC_TIMER_CONTEXT EFI_SMM_PERIODIC_TIMER_CONTEXT;
 
 typedef struct _EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL  EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL;
 
 /**
   Register a child SMI source dispatch function for SMM periodic timer.
 
-  This service registers a function (DispatchFunction) which will be called when at least the 
-  amount of time specified by RegisterContext has elapsed. On return, DispatchHandle 
+  This service registers a function (DispatchFunction) which will be called when at least the
+  amount of time specified by RegisterContext has elapsed. On return, DispatchHandle
   contains a unique handle which may be used later to unregister the function using UnRegister().
-  The DispatchFunction will be called with Context set to the same value as was passed into 
-  this function in RegisterContext and with CommBuffer pointing to an instance of 
+  The DispatchFunction will be called with Context set to the same value as was passed into
+  this function in RegisterContext and with CommBuffer pointing to an instance of
   EFI_SMM_PERIODIC_TIMER_CONTEXT and CommBufferSize pointing to its size.
 
   @param[in]  This               Pointer to the EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL instance.
   @param[in]  DispatchFunction   Function to register for handler when at least the specified amount
-                                 of time has elapsed. 
+                                 of time has elapsed.
   @param[in]  RegisterContext    Pointer to the dispatch function's context.
                                  The caller fills this context in before calling
                                  the register function to indicate to the register
                                  function the period at which the dispatch function
                                  should be invoked.
-  @param[out] DispatchHandle     Handle generated by the dispatcher to track the function instance. 
+  @param[out] DispatchHandle     Handle generated by the dispatcher to track the function instance.
 
   @retval EFI_SUCCESS            The dispatch function has been successfully
                                  registered and the SMI source has been enabled.
@@ -115,7 +101,7 @@ EFI_STATUS
 /**
   Unregisters a periodic timer service.
 
-  This service removes the handler associated with DispatchHandle so that it will no longer be 
+  This service removes the handler associated with DispatchHandle so that it will no longer be
   called when the time has elapsed.
 
   @param[in] This                Pointer to the EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL instance.
diff --git a/MdePkg/Include/Protocol/SmmPowerButtonDispatch2.h b/MdePkg/Include/Protocol/SmmPowerButtonDispatch2.h
index 0bedee8666d5..5fe84b00f2c2 100644
--- a/MdePkg/Include/Protocol/SmmPowerButtonDispatch2.h
+++ b/MdePkg/Include/Protocol/SmmPowerButtonDispatch2.h
@@ -4,14 +4,8 @@
 
   This protocol provides the parent dispatch service for the power button SMI source generator.
 
-  Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This protocol is from PI Version 1.1.
@@ -21,95 +15,20 @@
 #ifndef _SMM_POWER_BUTTON_DISPATCH2_H_
 #define _SMM_POWER_BUTTON_DISPATCH2_H_
 
-#include <Pi/PiSmmCis.h>
-
-#define EFI_SMM_POWER_BUTTON_DISPATCH2_PROTOCOL_GUID \
-  { \
-    0x1b1183fa, 0x1823, 0x46a7, {0x88, 0x72, 0x9c, 0x57, 0x87, 0x55, 0x40, 0x9d } \
-  }
+#include <Protocol/MmPowerButtonDispatch.h>
 
-///
-/// Power Button phases.
-///
-typedef enum {
-  EfiPowerButtonEntry,
-  EfiPowerButtonExit,
-  EfiPowerButtonMax
-} EFI_POWER_BUTTON_PHASE;
+#define EFI_SMM_POWER_BUTTON_DISPATCH2_PROTOCOL_GUID EFI_MM_POWER_BUTTON_DISPATCH_PROTOCOL_GUID
 
 ///
 /// The dispatch function's context.
 ///
-typedef struct {
-  ///
-  /// Designates whether this handler should be invoked upon entry or exit.
-  ///
-  EFI_POWER_BUTTON_PHASE  Phase;
-} EFI_SMM_POWER_BUTTON_REGISTER_CONTEXT;
-
-typedef struct _EFI_SMM_POWER_BUTTON_DISPATCH2_PROTOCOL EFI_SMM_POWER_BUTTON_DISPATCH2_PROTOCOL;
-
-/**
-  Provides the parent dispatch service for a power button event.
-
-  This service registers a function (DispatchFunction) which will be called when an SMI is 
-  generated because the power button was pressed or released, as specified by RegisterContext. 
-  On return, DispatchHandle contains a unique handle which may be used later to unregister the 
-  function using UnRegister().
-  The DispatchFunction will be called with Context set to the same value as was passed into 
-  this function in RegisterContext and with CommBuffer and CommBufferSize set to NULL.
-
-  @param[in]  This               Pointer to the EFI_SMM_POWER_BUTTON_DISPATCH2_PROTOCOL instance.
-  @param[in]  DispatchFunction   Function to register for handler when power button is pressed or released.
-  @param[in]  RegisterContext    Pointer to the dispatch function's context. The caller fills in this context
-                                 before calling the Register() function to indicate to the Register() function
-                                 the power button SMI phase for which the dispatch function should be invoked.
-  @param[out] DispatchHandle     Handle generated by the dispatcher to track the function instance. 
+typedef EFI_MM_POWER_BUTTON_REGISTER_CONTEXT EFI_SMM_POWER_BUTTON_REGISTER_CONTEXT;
 
-  @retval EFI_SUCCESS            The dispatch function has been successfully
-                                 registered and the SMI source has been enabled.
-  @retval EFI_DEVICE_ERROR       The driver was unable to enable the SMI source.
-  @retval EFI_INVALID_PARAMETER  RegisterContext is invalid. The power button input value
-                                 is not within valid range.
-  @retval EFI_OUT_OF_RESOURCES   There is not enough memory (system or SMM) to manage this child.
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_SMM_POWER_BUTTON_REGISTER2)(
-  IN CONST EFI_SMM_POWER_BUTTON_DISPATCH2_PROTOCOL  *This,
-  IN       EFI_SMM_HANDLER_ENTRY_POINT2             DispatchFunction,
-  IN       EFI_SMM_POWER_BUTTON_REGISTER_CONTEXT    *RegisterContext,
-  OUT      EFI_HANDLE                               *DispatchHandle
-  );
-
-/**
-  Unregisters a power-button service.
-
-  This service removes the handler associated with DispatchHandle so that it will no longer be 
-  called when the standby button is pressed or released. 
-
-  @param[in] This                Pointer to the EFI_SMM_POWER_BUTTON_DISPATCH2_PROTOCOL instance.
-  @param[in] DispatchHandle      Handle of the service to remove.
+typedef EFI_MM_POWER_BUTTON_DISPATCH_PROTOCOL EFI_SMM_POWER_BUTTON_DISPATCH2_PROTOCOL;
 
-  @retval EFI_SUCCESS            The service has been successfully removed.
-  @retval EFI_INVALID_PARAMETER  The DispatchHandle was not valid.
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_SMM_POWER_BUTTON_UNREGISTER2)(
-  IN CONST EFI_SMM_POWER_BUTTON_DISPATCH2_PROTOCOL  *This,
-  IN       EFI_HANDLE                               DispatchHandle
-  );
+typedef EFI_MM_POWER_BUTTON_REGISTER EFI_SMM_POWER_BUTTON_REGISTER2;
 
-///
-/// Interface structure for the SMM Power Button Dispatch2 Protocol.
-///
-/// This protocol provides the parent dispatch service for the power button SMI source generator.
-///
-struct _EFI_SMM_POWER_BUTTON_DISPATCH2_PROTOCOL {
-  EFI_SMM_POWER_BUTTON_REGISTER2    Register;
-  EFI_SMM_POWER_BUTTON_UNREGISTER2  UnRegister;
-};
+typedef EFI_MM_POWER_BUTTON_UNREGISTER EFI_SMM_POWER_BUTTON_UNREGISTER2;
 
 extern EFI_GUID gEfiSmmPowerButtonDispatch2ProtocolGuid;
 
diff --git a/MdePkg/Include/Protocol/SmmReadyToLock.h b/MdePkg/Include/Protocol/SmmReadyToLock.h
index a55606deb457..f2661397c303 100644
--- a/MdePkg/Include/Protocol/SmmReadyToLock.h
+++ b/MdePkg/Include/Protocol/SmmReadyToLock.h
@@ -12,23 +12,16 @@
   This protocol is installed after installation of the SMM End of DXE Protocol.
 
   Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
 #ifndef _SMM_READY_TO_LOCK_H_
 #define _SMM_READY_TO_LOCK_H_
 
-#define EFI_SMM_READY_TO_LOCK_PROTOCOL_GUID \
-  { \
-    0x47b7fa8c, 0xf4bd, 0x4af6, { 0x82, 0x00, 0x33, 0x30, 0x86, 0xf0, 0xd2, 0xc8 } \
-  }
+#include <Protocol/MmReadyToLock.h>
+
+#define EFI_SMM_READY_TO_LOCK_PROTOCOL_GUID EFI_MM_READY_TO_LOCK_PROTOCOL_GUID
 
 extern EFI_GUID gEfiSmmReadyToLockProtocolGuid;
 
diff --git a/MdePkg/Include/Protocol/SmmReportStatusCodeHandler.h b/MdePkg/Include/Protocol/SmmReportStatusCodeHandler.h
index ca290c7437ed..008d8c9bc84e 100644
--- a/MdePkg/Include/Protocol/SmmReportStatusCodeHandler.h
+++ b/MdePkg/Include/Protocol/SmmReportStatusCodeHandler.h
@@ -1,80 +1,28 @@
 /** @file
   This protocol provides registering and unregistering services to status code consumers while in DXE SMM.
-  
-  Copyright (c) 2007 - 2009, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  This Protocol was introduced in PI Specification 1.1.
 
 **/
 
 #ifndef __SMM_REPORT_STATUS_CODE_HANDLER_PROTOCOL_H__
 #define __SMM_REPORT_STATUS_CODE_HANDLER_PROTOCOL_H__
 
-#define EFI_SMM_RSC_HANDLER_PROTOCOL_GUID \
-  { \
-    0x2ff29fa7, 0x5e80, 0x4ed9, {0xb3, 0x80, 0x1, 0x7d, 0x3c, 0x55, 0x4f, 0xf4} \
-  }
-
-typedef
-EFI_STATUS
-(EFIAPI *EFI_SMM_RSC_HANDLER_CALLBACK)(
-  IN EFI_STATUS_CODE_TYPE   CodeType,
-  IN EFI_STATUS_CODE_VALUE  Value,
-  IN UINT32                 Instance,
-  IN EFI_GUID               *CallerId,
-  IN EFI_STATUS_CODE_DATA   *Data
-);
+#include <Protocol/MmReportStatusCodeHandler.h>
 
-/**
-  Register the callback function for ReportStatusCode() notification.
-  
-  When this function is called the function pointer is added to an internal list and any future calls to
-  ReportStatusCode() will be forwarded to the Callback function.
-  
-  @param[in] Callback               A pointer to a function of type EFI_RSC_HANDLER_CALLBACK that is called when
-                                    a call to ReportStatusCode() occurs.
+#define EFI_SMM_RSC_HANDLER_PROTOCOL_GUID EFI_MM_RSC_HANDLER_PROTOCOL_GUID
 
-  @retval EFI_SUCCESS               Function was successfully registered.
-  @retval EFI_INVALID_PARAMETER     The callback function was NULL.
-  @retval EFI_OUT_OF_RESOURCES      The internal buffer ran out of space. No more functions can be
-                                    registered.
-  @retval EFI_ALREADY_STARTED       The function was already registered. It can't be registered again.
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_SMM_RSC_HANDLER_REGISTER)(
-  IN EFI_SMM_RSC_HANDLER_CALLBACK Callback
-);
+typedef EFI_MM_RSC_HANDLER_CALLBACK EFI_SMM_RSC_HANDLER_CALLBACK;
 
-/**
-  Remove a previously registered callback function from the notification list.
-  
-  A callback function must be unregistered before it is deallocated. It is important that any registered
-  callbacks that are not runtime complaint be unregistered when ExitBootServices() is called.
+typedef EFI_MM_RSC_HANDLER_REGISTER EFI_SMM_RSC_HANDLER_REGISTER;
 
-  @param[in] Callback           A pointer to a function of type EFI_SMM_RSC_HANDLER_CALLBACK that is to be
-                                unregistered.
-                        
-  @retval EFI_SUCCESS           The function was successfully unregistered.
-  @retval EFI_INVALID_PARAMETER The callback function was NULL.
-  @retval EFI_NOT_FOUND         The callback function was not found to be unregistered.
-                            
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_SMM_RSC_HANDLER_UNREGISTER)(
-  IN EFI_SMM_RSC_HANDLER_CALLBACK Callback
-);
+typedef EFI_MM_RSC_HANDLER_UNREGISTER EFI_SMM_RSC_HANDLER_UNREGISTER;
 
-typedef struct _EFI_SMM_RSC_HANDLER_PROTOCOL {
-  EFI_SMM_RSC_HANDLER_REGISTER      Register;
-  EFI_SMM_RSC_HANDLER_UNREGISTER    Unregister;
-} EFI_SMM_RSC_HANDLER_PROTOCOL;
+typedef EFI_MM_RSC_HANDLER_PROTOCOL EFI_SMM_RSC_HANDLER_PROTOCOL;
 
 extern EFI_GUID gEfiSmmRscHandlerProtocolGuid;
 
diff --git a/MdePkg/Include/Protocol/SmmStandbyButtonDispatch2.h b/MdePkg/Include/Protocol/SmmStandbyButtonDispatch2.h
index e8249495d2a6..dfe9305fc29f 100644
--- a/MdePkg/Include/Protocol/SmmStandbyButtonDispatch2.h
+++ b/MdePkg/Include/Protocol/SmmStandbyButtonDispatch2.h
@@ -5,13 +5,7 @@
   This protocol provides the parent dispatch service for the standby button SMI source generator.
 
   Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This protocol is from PI Version 1.1.
@@ -21,97 +15,20 @@
 #ifndef _SMM_STANDBY_BUTTON_DISPATCH2_H_
 #define _SMM_STANDBY_BUTTON_DISPATCH2_H_
 
-#include <Pi/PiSmmCis.h>
-
-#define EFI_SMM_STANDBY_BUTTON_DISPATCH2_PROTOCOL_GUID \
-  { \
-    0x7300c4a1, 0x43f2, 0x4017, {0xa5, 0x1b, 0xc8, 0x1a, 0x7f, 0x40, 0x58, 0x5b } \
-  }
+#include <Protocol/MmStandbyButtonDispatch.h>
 
-///
-/// Standby Button phases
-///
-typedef enum {
-  EfiStandbyButtonEntry,
-  EfiStandbyButtonExit,
-  EfiStandbyButtonMax
-} EFI_STANDBY_BUTTON_PHASE;
+#define EFI_SMM_STANDBY_BUTTON_DISPATCH2_PROTOCOL_GUID EFI_MM_STANDBY_BUTTON_DISPATCH_PROTOCOL_GUID
 
 ///
 /// The dispatch function's context.
 ///
-typedef struct {
-  ///
-  /// Describes whether the child handler should be invoked upon the entry to the button 
-  /// activation or upon exit.
-  ///
-  EFI_STANDBY_BUTTON_PHASE  Phase;
-} EFI_SMM_STANDBY_BUTTON_REGISTER_CONTEXT;
-
-typedef struct _EFI_SMM_STANDBY_BUTTON_DISPATCH2_PROTOCOL EFI_SMM_STANDBY_BUTTON_DISPATCH2_PROTOCOL;
-
-/**
-  Provides the parent dispatch service for a standby button event.
-
-  This service registers a function (DispatchFunction) which will be called when an SMI is 
-  generated because the standby button was pressed or released, as specified by 
-  RegisterContext. On return, DispatchHandle contains a unique handle which may be used 
-  later to unregister the function using UnRegister().
-  The DispatchFunction will be called with Context set to the same value as was passed into 
-  this function in RegisterContext and with CommBuffer and CommBufferSize set to NULL. 
-
-  @param[in]  This               Pointer to the EFI_SMM_STANDBY_BUTTON_DISPATCH2_PROTOCOL instance.
-  @param[in]  DispatchFunction   Function to register for handler when the standby button is pressed or released.
-  @param[in]  RegisterContext    Pointer to the dispatch function's context. The caller fills in this context
-                                 before calling the register function to indicate to the register function the 
-                                 standby button SMI source for which the dispatch function should be invoked.
-  @param[out] DispatchHandle     Handle generated by the dispatcher to track the function instance. 
+typedef EFI_MM_STANDBY_BUTTON_REGISTER_CONTEXT EFI_SMM_STANDBY_BUTTON_REGISTER_CONTEXT;
 
-  @retval EFI_SUCCESS            The dispatch function has been successfully
-                                 registered and the SMI source has been enabled.
-  @retval EFI_DEVICE_ERROR       The driver was unable to enable the SMI source.
-  @retval EFI_INVALID_PARAMETER  RegisterContext is invalid. The standby button input value
-                                 is not within valid range.
-  @retval EFI_OUT_OF_RESOURCES   There is not enough memory (system or SMM) to manage this child.
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_SMM_STANDBY_BUTTON_REGISTER2)(
-  IN CONST EFI_SMM_STANDBY_BUTTON_DISPATCH2_PROTOCOL  *This,
-  IN       EFI_SMM_HANDLER_ENTRY_POINT2               DispatchFunction,
-  IN       EFI_SMM_STANDBY_BUTTON_REGISTER_CONTEXT    *RegisterContext,
-  OUT      EFI_HANDLE                                 *DispatchHandle
-  );
-
-/**
-  Unregisters a child SMI source dispatch function with a parent SMM driver.
-
-  This service removes the handler associated with DispatchHandle so that it will no longer be 
-  called when the standby button is pressed or released.
-
-  @param[in] This                Pointer to the EFI_SMM_STANDBY_BUTTON_DISPATCH2_PROTOCOL instance.
-  @param[in] DispatchHandle      Handle of the service to remove.
+typedef EFI_MM_STANDBY_BUTTON_DISPATCH_PROTOCOL EFI_SMM_STANDBY_BUTTON_DISPATCH2_PROTOCOL;
 
-  @retval EFI_SUCCESS            The service has been successfully removed.
-  @retval EFI_INVALID_PARAMETER  The DispatchHandle was not valid.
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_SMM_STANDBY_BUTTON_UNREGISTER2)(
-  IN CONST EFI_SMM_STANDBY_BUTTON_DISPATCH2_PROTOCOL  *This,
-  IN       EFI_HANDLE                                 DispatchHandle
-  );
+typedef EFI_MM_STANDBY_BUTTON_REGISTER EFI_SMM_STANDBY_BUTTON_REGISTER2;
 
-///
-/// Interface structure for the SMM Standby Button Dispatch2 Protocol.
-///
-/// This protocol provides the parent dispatch service for the standby
-/// button SMI source generator.
-///
-struct _EFI_SMM_STANDBY_BUTTON_DISPATCH2_PROTOCOL {
-  EFI_SMM_STANDBY_BUTTON_REGISTER2    Register;
-  EFI_SMM_STANDBY_BUTTON_UNREGISTER2  UnRegister;
-};
+typedef EFI_MM_STANDBY_BUTTON_UNREGISTER EFI_SMM_STANDBY_BUTTON_UNREGISTER2;
 
 extern EFI_GUID gEfiSmmStandbyButtonDispatch2ProtocolGuid;
 
diff --git a/MdePkg/Include/Protocol/SmmStatusCode.h b/MdePkg/Include/Protocol/SmmStatusCode.h
index cf9740737df8..da396cc11541 100644
--- a/MdePkg/Include/Protocol/SmmStatusCode.h
+++ b/MdePkg/Include/Protocol/SmmStatusCode.h
@@ -1,63 +1,23 @@
 /** @file
   EFI SMM Status Code Protocol as defined in the PI 1.2 specification.
 
-  This protocol provides the basic status code services while in SMM. 
+  This protocol provides the basic status code services while in SMM.
 
-  Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
 #ifndef _SMM_STATUS_CODE_H__
 #define _SMM_STATUS_CODE_H__
 
+#include <Protocol/MmStatusCode.h>
 
-#define EFI_SMM_STATUS_CODE_PROTOCOL_GUID \
-  { \
-    0x6afd2b77, 0x98c1, 0x4acd, {0xa6, 0xf9, 0x8a, 0x94, 0x39, 0xde, 0xf, 0xb1} \
-  }
-
-typedef struct _EFI_SMM_STATUS_CODE_PROTOCOL  EFI_SMM_STATUS_CODE_PROTOCOL;
-
-/**
-  Service to emit the status code in SMM.    
+#define EFI_SMM_STATUS_CODE_PROTOCOL_GUID EFI_MM_STATUS_CODE_PROTOCOL_GUID
 
-  The EFI_SMM_STATUS_CODE_PROTOCOL.ReportStatusCode() function enables a driver 
-  to emit a status code while in SMM.  The reason that there is a separate protocol definition from the 
-  DXE variant of this service is that the publisher of this protocol will provide a service that is 
-  capability of coexisting with a foreground operational environment, such as an operating system 
-  after the termination of boot services.  
-
-  @param[in] This                Points to this instance of the EFI_SMM_STATUS_CODE_PROTOCOL.
-  @param[in] CodeType            DIndicates the type of status code being reported. 
-  @param[in] Value               Describes the current status of a hardware or software entity. 
-  @param[in] Instance            The enumeration of a hardware or software entity within the system.
-  @param[in] CallerId            This optional parameter may be used to identify the caller.
-  @param[in] Data                This optional parameter may be used to pass additional data.
-
-  @retval EFI_SUCCESS            The function completed successfully.
-  @retval EFI_INVALID_PARAMETER  The function should not be completed due to a device error.
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_SMM_REPORT_STATUS_CODE)(
-  IN CONST EFI_SMM_STATUS_CODE_PROTOCOL  *This,
-  IN EFI_STATUS_CODE_TYPE                CodeType,
-  IN EFI_STATUS_CODE_VALUE               Value,
-  IN UINT32                              Instance,
-  IN CONST EFI_GUID                      *CallerId,
-  IN EFI_STATUS_CODE_DATA                *Data OPTIONAL
-  );
+typedef EFI_MM_STATUS_CODE_PROTOCOL  EFI_SMM_STATUS_CODE_PROTOCOL;
 
-struct _EFI_SMM_STATUS_CODE_PROTOCOL {
-  EFI_SMM_REPORT_STATUS_CODE  ReportStatusCode;
-};
+typedef EFI_MM_REPORT_STATUS_CODE EFI_SMM_REPORT_STATUS_CODE;
 
 extern EFI_GUID gEfiSmmStatusCodeProtocolGuid;
 
diff --git a/MdePkg/Include/Protocol/SmmSwDispatch2.h b/MdePkg/Include/Protocol/SmmSwDispatch2.h
index 3b2969b9769a..95e7db404837 100644
--- a/MdePkg/Include/Protocol/SmmSwDispatch2.h
+++ b/MdePkg/Include/Protocol/SmmSwDispatch2.h
@@ -4,26 +4,18 @@
 
   This protocol provides the parent dispatch service for a given SMI source generator.
 
-  Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
 #ifndef _SMM_SW_DISPATCH2_H_
 #define _SMM_SW_DISPATCH2_H_
 
+#include <Protocol/MmSwDispatch.h>
 #include <Pi/PiSmmCis.h>
 
-#define EFI_SMM_SW_DISPATCH2_PROTOCOL_GUID \
-  { \
-    0x18a3c6dc, 0x5eea, 0x48c8, {0xa1, 0xc1, 0xb5, 0x33, 0x89, 0xf9, 0x89, 0x99 } \
-  }
+#define EFI_SMM_SW_DISPATCH2_PROTOCOL_GUID EFI_MM_SW_DISPATCH_PROTOCOL_GUID
 
 ///
 /// A particular chipset may not support all possible software SMI input values.
@@ -35,9 +27,9 @@ typedef struct {
 } EFI_SMM_SW_REGISTER_CONTEXT;
 
 ///
-/// The DispatchFunction will be called with Context set to the same value as was passed into 
+/// The DispatchFunction will be called with Context set to the same value as was passed into
 /// this function in RegisterContext and with CommBuffer (and CommBufferSize) pointing
-/// to an instance of EFI_SMM_SW_CONTEXT indicating the index of the CPU which generated the 
+/// to an instance of EFI_SMM_SW_CONTEXT indicating the index of the CPU which generated the
 /// software SMI.
 ///
 typedef struct {
@@ -60,14 +52,14 @@ typedef struct _EFI_SMM_SW_DISPATCH2_PROTOCOL  EFI_SMM_SW_DISPATCH2_PROTOCOL;
 /**
   Register a child SMI source dispatch function for the specified software SMI.
 
-  This service registers a function (DispatchFunction) which will be called when the software 
-  SMI source specified by RegisterContext->SwSmiCpuIndex is detected. On return, 
-  DispatchHandle contains a unique handle which may be used later to unregister the function 
+  This service registers a function (DispatchFunction) which will be called when the software
+  SMI source specified by RegisterContext->SwSmiCpuIndex is detected. On return,
+  DispatchHandle contains a unique handle which may be used later to unregister the function
   using UnRegister().
 
   @param[in]  This                 Pointer to the EFI_SMM_SW_DISPATCH2_PROTOCOL instance.
-  @param[in]  DispatchFunction     Function to register for handler when the specified software 
-                                   SMI is generated. 
+  @param[in]  DispatchFunction     Function to register for handler when the specified software
+                                   SMI is generated.
   @param[in, out] RegisterContext  Pointer to the dispatch function's context.
                                    The caller fills this context in before calling
                                    the register function to indicate to the register
@@ -98,7 +90,7 @@ EFI_STATUS
 /**
   Unregister a child SMI source dispatch function for the specified software SMI.
 
-  This service removes the handler associated with DispatchHandle so that it will no longer be 
+  This service removes the handler associated with DispatchHandle so that it will no longer be
   called in response to a software SMI.
 
   @param[in] This                Pointer to the EFI_SMM_SW_DISPATCH2_PROTOCOL instance.
@@ -117,15 +109,15 @@ EFI_STATUS
 ///
 /// Interface structure for the SMM Software SMI Dispatch Protocol.
 ///
-/// The EFI_SMM_SW_DISPATCH2_PROTOCOL provides the ability to install child handlers for the 
-/// given software.  These handlers will respond to software interrupts, and the maximum software 
+/// The EFI_SMM_SW_DISPATCH2_PROTOCOL provides the ability to install child handlers for the
+/// given software.  These handlers will respond to software interrupts, and the maximum software
 /// interrupt in the EFI_SMM_SW_REGISTER_CONTEXT is denoted by MaximumSwiValue.
 ///
 struct _EFI_SMM_SW_DISPATCH2_PROTOCOL {
   EFI_SMM_SW_REGISTER2    Register;
   EFI_SMM_SW_UNREGISTER2  UnRegister;
   ///
-  /// A read-only field that describes the maximum value that can be used in the 
+  /// A read-only field that describes the maximum value that can be used in the
   /// EFI_SMM_SW_DISPATCH2_PROTOCOL.Register() service.
   ///
   UINTN                  MaximumSwiValue;
diff --git a/MdePkg/Include/Protocol/SmmSxDispatch2.h b/MdePkg/Include/Protocol/SmmSxDispatch2.h
index 94508f3a3973..d4e3020bd1d1 100644
--- a/MdePkg/Include/Protocol/SmmSxDispatch2.h
+++ b/MdePkg/Include/Protocol/SmmSxDispatch2.h
@@ -4,131 +4,28 @@
 
   Provides the parent dispatch service for a given Sx-state source generator.
 
-  Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
 #ifndef _SMM_SX_DISPATCH2_H_
 #define _SMM_SX_DISPATCH2_H_
 
-#include <Pi/PiSmmCis.h>
-
-#define EFI_SMM_SX_DISPATCH2_PROTOCOL_GUID \
-  { \
-    0x456d2859, 0xa84b, 0x4e47, {0xa2, 0xee, 0x32, 0x76, 0xd8, 0x86, 0x99, 0x7d } \
-  }
-
-///
-/// Sleep states S0-S5
-///
-typedef enum {
-  SxS0,
-  SxS1,
-  SxS2,
-  SxS3,
-  SxS4,
-  SxS5,
-  EfiMaximumSleepType
-} EFI_SLEEP_TYPE;
+#include <Protocol/MmSxDispatch.h>
 
-///
-/// Sleep state phase: entry or exit
-///
-typedef enum {
-  SxEntry,
-  SxExit,
-  EfiMaximumPhase
-} EFI_SLEEP_PHASE;
+#define EFI_SMM_SX_DISPATCH2_PROTOCOL_GUID EFI_MM_SX_DISPATCH_PROTOCOL_GUID
 
 ///
 /// The dispatch function's context
 ///
-typedef struct {
-  EFI_SLEEP_TYPE  Type;
-  EFI_SLEEP_PHASE Phase;
-} EFI_SMM_SX_REGISTER_CONTEXT;
-
-typedef struct _EFI_SMM_SX_DISPATCH2_PROTOCOL  EFI_SMM_SX_DISPATCH2_PROTOCOL;
+typedef EFI_MM_SX_REGISTER_CONTEXT EFI_SMM_SX_REGISTER_CONTEXT;
 
-/**
-  Provides the parent dispatch service for a given Sx source generator.
+typedef EFI_MM_SX_DISPATCH_PROTOCOL  EFI_SMM_SX_DISPATCH2_PROTOCOL;
 
-  This service registers a function (DispatchFunction) which will be called when the sleep state 
-  event specified by RegisterContext is detected. On return, DispatchHandle contains a 
-  unique handle which may be used later to unregister the function using UnRegister().
-  The DispatchFunction will be called with Context set to the same value as was passed into 
-  this function in RegisterContext and with CommBuffer and CommBufferSize set to 
-  NULL and 0 respectively.
+typedef EFI_MM_SX_REGISTER EFI_SMM_SX_REGISTER2;
 
-  @param[in] This                Pointer to the EFI_SMM_SX_DISPATCH2_PROTOCOL instance.
-  @param[in] DispatchFunction    Function to register for handler when the specified sleep state event occurs.
-  @param[in] RegisterContext     Pointer to the dispatch function's context.
-                                 The caller fills this context in before calling
-                                 the register function to indicate to the register
-                                 function which Sx state type and phase the caller
-                                 wishes to be called back on. For this intertace,
-                                 the Sx driver will call the registered handlers for
-                                 all Sx type and phases, so the Sx state handler(s)
-                                 must check the Type and Phase field of the Dispatch
-                                 context and act accordingly.
-  @param[out]  DispatchHandle    Handle of dispatch function, for when interfacing
-                                 with the parent Sx state SMM driver.
-
-  @retval EFI_SUCCESS            The dispatch function has been successfully
-                                 registered and the SMI source has been enabled.
-  @retval EFI_UNSUPPORTED        The Sx driver or hardware does not support that
-                                 Sx Type/Phase.
-  @retval EFI_DEVICE_ERROR       The Sx driver was unable to enable the SMI source.
-  @retval EFI_INVALID_PARAMETER  RegisterContext is invalid. Type & Phase are not
-                                 within valid range.
-  @retval EFI_OUT_OF_RESOURCES   There is not enough memory (system or SMM) to manage this
-                                 child.
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_SMM_SX_REGISTER2)(
-  IN  CONST EFI_SMM_SX_DISPATCH2_PROTOCOL  *This,
-  IN        EFI_SMM_HANDLER_ENTRY_POINT2   DispatchFunction,
-  IN  CONST EFI_SMM_SX_REGISTER_CONTEXT    *RegisterContext,
-  OUT       EFI_HANDLE                     *DispatchHandle
-  );
-
-/**
-  Unregisters an Sx-state service.
-
-  This service removes the handler associated with DispatchHandle so that it will no longer be 
-  called in response to sleep event.
-
-  @param[in] This                Pointer to the EFI_SMM_SX_DISPATCH2_PROTOCOL instance.
-  @param[in] DispatchHandle      Handle of the service to remove. 
-
-  @retval EFI_SUCCESS            The service has been successfully removed.
-  @retval EFI_INVALID_PARAMETER  The DispatchHandle was not valid.
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_SMM_SX_UNREGISTER2)(
-  IN CONST EFI_SMM_SX_DISPATCH2_PROTOCOL  *This,
-  IN       EFI_HANDLE                     DispatchHandle
-  );
-
-///
-/// Interface structure for the SMM Sx Dispatch Protocol
-///
-/// The EFI_SMM_SX_DISPATCH2_PROTOCOL provides the ability to install child handlers to 
-/// respond to sleep state related events.
-///
-struct _EFI_SMM_SX_DISPATCH2_PROTOCOL {
-  EFI_SMM_SX_REGISTER2    Register;
-  EFI_SMM_SX_UNREGISTER2  UnRegister;
-};
+typedef EFI_MM_SX_UNREGISTER EFI_SMM_SX_UNREGISTER2;
 
 extern EFI_GUID gEfiSmmSxDispatch2ProtocolGuid;
 
diff --git a/MdePkg/Include/Protocol/SmmUsbDispatch2.h b/MdePkg/Include/Protocol/SmmUsbDispatch2.h
index 75a7a7c0bc7f..8ac127a8bb98 100644
--- a/MdePkg/Include/Protocol/SmmUsbDispatch2.h
+++ b/MdePkg/Include/Protocol/SmmUsbDispatch2.h
@@ -4,14 +4,8 @@
 
   Provides the parent dispatch service for the USB SMI source generator.
 
-  Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This protocol is from PI Version 1.1.
@@ -21,108 +15,25 @@
 #ifndef _SMM_USB_DISPATCH2_H_
 #define _SMM_USB_DISPATCH2_H_
 
-#include <Pi/PiSmmCis.h>
+#include <Protocol/MmUsbDispatch.h>
 
-#define EFI_SMM_USB_DISPATCH2_PROTOCOL_GUID \
-  { \
-    0xee9b8d90, 0xc5a6, 0x40a2, {0xbd, 0xe2, 0x52, 0x55, 0x8d, 0x33, 0xcc, 0xa1 } \
-  }
+#define EFI_SMM_USB_DISPATCH2_PROTOCOL_GUID EFI_MM_USB_DISPATCH_PROTOCOL_GUID
 
 ///
 /// USB SMI event types
 ///
-typedef enum {
-  UsbLegacy,
-  UsbWake
-} EFI_USB_SMI_TYPE;
+typedef EFI_USB_MMI_TYPE EFI_USB_SMI_TYPE;
 
 ///
 /// The dispatch function's context.
 ///
-typedef struct {
-  ///
-  /// Describes whether this child handler will be invoked in response to a USB legacy 
-  /// emulation event, such as port-trap on the PS/2* keyboard control registers, or to a 
-  /// USB wake event, such as resumption from a sleep state.
-  ///
-  EFI_USB_SMI_TYPE          Type;
-  ///
-  /// The device path is part of the context structure and describes the location of the 
-  /// particular USB host controller in the system for which this register event will occur.
-  /// This location is important because of the possible integration of several USB host 
-  /// controllers in a system.
-  ///
-  EFI_DEVICE_PATH_PROTOCOL  *Device;
-} EFI_SMM_USB_REGISTER_CONTEXT;
-
-typedef struct _EFI_SMM_USB_DISPATCH2_PROTOCOL EFI_SMM_USB_DISPATCH2_PROTOCOL;
-
-/**
-  Provides the parent dispatch service for the USB SMI source generator.
-
-  This service registers a function (DispatchFunction) which will be called when the USB-
-  related SMI specified by RegisterContext has occurred. On return, DispatchHandle 
-  contains a unique handle which may be used later to unregister the function using UnRegister().
-  The DispatchFunction will be called with Context set to the same value as was passed into 
-  this function in RegisterContext and with CommBuffer containing NULL and 
-  CommBufferSize containing zero.
-
-  @param[in]  This               Pointer to the EFI_SMM_USB_DISPATCH2_PROTOCOL instance.
-  @param[in]  DispatchFunction   Function to register for handler when a USB-related SMI occurs. 
-  @param[in]  RegisterContext    Pointer to the dispatch function's context.
-                                 The caller fills this context in before calling
-                                 the register function to indicate to the register
-                                 function the USB SMI types for which the dispatch
-                                 function should be invoked.
-  @param[out] DispatchHandle     Handle generated by the dispatcher to track the function instance.
-
-  @retval EFI_SUCCESS            The dispatch function has been successfully
-                                 registered and the SMI source has been enabled.
-  @retval EFI_DEVICE_ERROR       The driver was unable to enable the SMI source.
-  @retval EFI_INVALID_PARAMETER  RegisterContext is invalid. The USB SMI type
-                                 is not within valid range.
-  @retval EFI_OUT_OF_RESOURCES   There is not enough memory (system or SMM) to manage this child.
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_SMM_USB_REGISTER2)(
-  IN  CONST EFI_SMM_USB_DISPATCH2_PROTOCOL  *This,
-  IN        EFI_SMM_HANDLER_ENTRY_POINT2    DispatchFunction,
-  IN  CONST EFI_SMM_USB_REGISTER_CONTEXT    *RegisterContext,
-  OUT       EFI_HANDLE                      *DispatchHandle
-  );
-
-/**
-  Unregisters a USB service.
+typedef EFI_MM_USB_REGISTER_CONTEXT EFI_SMM_USB_REGISTER_CONTEXT;
 
-  This service removes the handler associated with DispatchHandle so that it will no longer be 
-  called when the USB event occurs.
+typedef EFI_MM_USB_DISPATCH_PROTOCOL EFI_SMM_USB_DISPATCH2_PROTOCOL;
 
-  @param[in]  This               Pointer to the EFI_SMM_USB_DISPATCH2_PROTOCOL instance.
-  @param[in]  DispatchHandle     Handle of the service to remove. 
-
-  @retval EFI_SUCCESS            The dispatch function has been successfully
-                                 unregistered and the SMI source has been disabled
-                                 if there are no other registered child dispatch
-                                 functions for this SMI source.
-  @retval EFI_INVALID_PARAMETER  The DispatchHandle was not valid.
-**/
-typedef
-EFI_STATUS
-(EFIAPI *EFI_SMM_USB_UNREGISTER2)(
-  IN CONST EFI_SMM_USB_DISPATCH2_PROTOCOL  *This,
-  IN       EFI_HANDLE                      DispatchHandle
-  );
+typedef EFI_MM_USB_REGISTER EFI_SMM_USB_REGISTER2;
 
-///
-/// Interface structure for the SMM USB SMI Dispatch2 Protocol
-///
-/// This protocol provides the parent dispatch service for the USB SMI source generator.
-///
-struct _EFI_SMM_USB_DISPATCH2_PROTOCOL {
-  EFI_SMM_USB_REGISTER2    Register;
-  EFI_SMM_USB_UNREGISTER2  UnRegister;
-};
+typedef EFI_MM_USB_UNREGISTER EFI_SMM_USB_UNREGISTER2;
 
 extern EFI_GUID gEfiSmmUsbDispatch2ProtocolGuid;
 
diff --git a/MdePkg/Include/Protocol/SpiConfiguration.h b/MdePkg/Include/Protocol/SpiConfiguration.h
new file mode 100644
index 000000000000..c09784b7354e
--- /dev/null
+++ b/MdePkg/Include/Protocol/SpiConfiguration.h
@@ -0,0 +1,287 @@
+/** @file
+  This file defines the SPI Configuration Protocol.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+    This Protocol was introduced in UEFI PI Specification 1.6.
+
+**/
+
+#ifndef __SPI_CONFIGURATION_PROTOCOL_H__
+#define __SPI_CONFIGURATION_PROTOCOL_H__
+
+///
+/// Global ID for the SPI Configuration Protocol
+///
+#define EFI_SPI_CONFIGURATION_GUID  \
+  { 0x85a6d3e6, 0xb65b, 0x4afc,     \
+    { 0xb3, 0x8f, 0xc6, 0xd5, 0x4a, 0xf6, 0xdd, 0xc8 }}
+
+///
+/// Macros to easily specify frequencies in hertz, kilohertz and megahertz.
+///
+#define Hz(Frequency)   (Frequency)
+#define KHz(Frequency)  (1000 * Hz (Frequency))
+#define MHz(Frequency)  (1000 * KHz (Frequency))
+
+typedef struct _EFI_SPI_PERIPHERAL EFI_SPI_PERIPHERAL;
+
+/**
+  Manipulate the chip select for a SPI device.
+
+  This routine must be called at or below TPL_NOTIFY.
+  Update the value of the chip select line for a SPI peripheral.
+  The SPI bus layer calls this routine either in the board layer or in the SPI
+  controller to manipulate the chip select pin at the start and end of a SPI
+  transaction.
+
+  @param[in] SpiPeripheral  The address of an EFI_SPI_PERIPHERAL data structure
+                            describing the SPI peripheral whose chip select pin
+                            is to be manipulated. The routine may access the
+                            ChipSelectParameter field to gain sufficient
+                            context to complete the operation.
+  @param[in] PinValue       The value to be applied to the chip select line of
+                            the SPI peripheral.
+
+  @retval EFI_SUCCESS            The chip select was set successfully
+  @retval EFI_NOT_READY          Support for the chip select is not properly
+                                 initialized
+  @retval EFI_INVALID_PARAMETER  The SpiPeripheral->ChipSelectParameter value
+                                 is invalid
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SPI_CHIP_SELECT) (
+  IN CONST EFI_SPI_PERIPHERAL  *SpiPeripheral,
+  IN BOOLEAN                   PinValue
+  );
+
+/**
+  Set up the clock generator to produce the correct clock frequency, phase and
+  polarity for a SPI chip.
+
+  This routine must be called at or below TPL_NOTIFY.
+  This routine updates the clock generator to generate the correct frequency
+  and polarity for the SPI clock.
+
+  @param[in] SpiPeripheral  Pointer to a EFI_SPI_PERIPHERAL data structure from
+                            which the routine can access the ClockParameter,
+                            ClockPhase and ClockPolarity fields. The routine
+                            also has access to the names for the SPI bus and
+                            chip which can be used during debugging.
+  @param[in] ClockHz        Pointer to the requested clock frequency. The clock
+                            generator will choose a supported clock frequency
+                            which is less then or equal to this value.
+                            Specify zero to turn the clock generator off.
+                            The actual clock frequency supported by the clock
+                            generator will be returned.
+
+  @retval EFI_SUCCESS      The clock was set up successfully
+  @retval EFI_UNSUPPORTED  The SPI controller was not able to support the
+                           frequency requested by CLockHz
+
+**/
+typedef EFI_STATUS
+(EFIAPI *EFI_SPI_CLOCK) (
+  IN CONST EFI_SPI_PERIPHERAL  *SpiPeripheral,
+  IN UINT32                    *ClockHz
+  );
+
+///
+/// The EFI_SPI_PART data structure provides a description of a SPI part which
+/// is independent of the use on the board. This data is available directly
+/// from the part's datasheet and may be provided by the vendor.
+///
+typedef struct _EFI_SPI_PART {
+  ///
+  /// A Unicode string specifying the SPI chip vendor.
+  ///
+  CONST CHAR16 *Vendor;
+
+  ///
+  /// A Unicode string specifying the SPI chip part number.
+  ///
+  CONST CHAR16 *PartNumber;
+
+  ///
+  /// The minimum SPI bus clock frequency used to access this chip. This value
+  /// may be specified in the chip's datasheet. If not, use the value of zero.
+  ///
+  UINT32       MinClockHz;
+
+  ///
+  /// The maximum SPI bus clock frequency used to access this chip. This value
+  /// is found in the chip's datasheet.
+  ///
+  UINT32       MaxClockHz;
+
+  ///
+  /// Specify the polarity of the chip select pin. This value can be found in
+  /// the SPI chip's datasheet. Specify TRUE when a one asserts the chip select
+  ///and FALSE when a zero asserts the chip select.
+  ///
+  BOOLEAN      ChipSelectPolarity;
+} EFI_SPI_PART;
+
+///
+/// The EFI_SPI_BUS data structure provides the connection details between the
+/// physical SPI bus and the EFI_SPI_HC_PROTOCOL instance which controls that
+/// SPI bus. This data structure also describes the details of how the clock is
+/// generated for that SPI bus. Finally this data structure provides the list
+/// of physical SPI devices which are attached to the SPI bus.
+///
+typedef struct _EFI_SPI_BUS {
+  ///
+  /// A Unicode string describing the SPI bus
+  ///
+  CONST CHAR16                   *FriendlyName;
+
+  ///
+  /// Address of the first EFI_SPI_PERIPHERAL data structure connected to this
+  /// bus. Specify NULL if there are no SPI peripherals connected to this bus.
+  ///
+  CONST EFI_SPI_PERIPHERAL       *Peripherallist;
+
+  ///
+  /// Address of an EFI_DEVICE_PATH_PROTOCOL data structure which uniquely
+  /// describes the SPI controller.
+  ///
+  CONST EFI_DEVICE_PATH_PROTOCOL *ControllerPath;
+
+  ///
+  /// Address of the routine which controls the clock used by the SPI bus for
+  /// this SPI peripheral. The SPI host co ntroller's clock routine is called
+  /// when this value is set to NULL.
+  ///
+  EFI_SPI_CLOCK                  Clock;
+
+  ///
+  /// Address of a data structure containing the additional values which
+  /// describe the necessary control for the clock. When Clock is NULL,
+  /// the declaration for this data structure is provided by the vendor of the
+  /// host's SPI controller driver. When Clock is not NULL, the declaration for
+  /// this data structure is provided by the board layer.
+  ///
+  VOID                           *ClockParameter;
+} EFI_SPI_BUS;
+
+///
+/// The EFI_SPI_PERIPHERAL data structure describes how a specific block of
+/// logic which is connected to the SPI bus. This data structure also selects
+/// which upper level driver is used to manipulate this SPI device.
+/// The SpiPeripheraLDriverGuid is available from the vendor of the SPI
+/// peripheral driver.
+///
+struct _EFI_SPI_PERIPHERAL {
+  ///
+  /// Address of the next EFI_SPI_PERIPHERAL data structure. Specify NULL if
+  /// the current data structure is the last one on the SPI bus.
+  ///
+  CONST EFI_SPI_PERIPHERAL *NextSpiPeripheral;
+
+  ///
+  /// A unicode string describing the function of the SPI part.
+  ///
+  CONST CHAR16             *FriendlyName;
+
+  ///
+  /// Address of a GUID provided by the vendor of the SPI peripheral driver.
+  /// Instead of using a " EFI_SPI_IO_PROTOCOL" GUID, the SPI bus driver uses
+  /// this GUID to identify an EFI_SPI_IO_PROTOCOL data structure and to
+  /// provide the connection points for the SPI peripheral drivers.
+  /// This reduces the comparison logic in the SPI peripheral driver's
+  /// Supported routine.
+  ///
+  CONST GUID               *SpiPeripheralDriverGuid;
+
+  ///
+  /// The address of an EFI_SPI_PART data structure which describes this chip.
+  ///
+  CONST EFI_SPI_PART       *SpiPart;
+
+  ///
+  /// The maximum clock frequency is specified in the EFI_SPI_P ART. When this
+  /// this value is non-zero and less than the value in the EFI_SPI_PART then
+  /// this value is used for the maximum clock frequency for the SPI part.
+  ///
+  UINT32                   MaxClockHz;
+
+  ///
+  /// Specify the idle value of the clock as found in the datasheet.
+  /// Use zero (0) if the clock'S idle value is low or one (1) if the the
+  /// clock's idle value is high.
+  ///
+  BOOLEAN                  ClockPolarity;
+
+  ///
+  /// Specify the clock delay after chip select. Specify zero (0) to delay an
+  /// entire clock cycle or one (1) to delay only half a clock cycle.
+  ///
+  BOOLEAN                  ClockPhase;
+
+  ///
+  /// SPI peripheral attributes, select zero or more of:
+  /// * SPI_PART_SUPPORTS_2_B1T_DATA_BUS_W1DTH - The SPI peripheral is wired to
+  ///   support a 2-bit data bus
+  /// * SPI_PART_SUPPORTS_4_B1T_DATA_BUS_W1DTH - The SPI peripheral is wired to
+  ///   support a 4-bit data bus
+  ///
+  UINT32                   Attributes;
+
+  ///
+  /// Address of a vendor specific data structure containing additional board
+  /// configuration details related to the SPI chip. The SPI peripheral layer
+  /// uses this data structure when configuring the chip.
+  ///
+  CONST VOID               *ConfigurationData;
+
+  ///
+  /// The address of an EFI_SPI_BUS data structure which describes the SPI bus
+  /// to which this chip is connected.
+  ///
+  CONST EFI_SPI_BUS        *SpiBus;
+
+  ///
+  /// Address of the routine which controls the chip select pin for this SPI
+  /// peripheral. Call the SPI host controller's chip select routine when this
+  /// value is set to NULL.
+  ///
+  EFI_SPI_CHIP_SELECT      ChipSelect;
+
+  ///
+  /// Address of a data structure containing the additional values which
+  /// describe the necessary control for the chip select. When ChipSelect is
+  /// NULL, the declaration for this data structure is provided by the vendor
+  /// of the host's SPI controller driver. The vendor's documentation specifies
+  /// the necessary values to use for the chip select pin selection and
+  /// control. When Chipselect is not NULL, the declaration for this data
+  /// structure is provided by the board layer.
+  ///
+  VOID                     *ChipSelectParameter;
+};
+
+///
+/// Describe the details of the board's SPI busses to the SPI driver stack.
+/// The board layer uses the EFI_SPI_CONFIGURATION_PROTOCOL to expose the data
+/// tables which describe the board's SPI busses, The SPI bus layer uses these
+/// tables to configure the clock, chip select and manage the SPI transactions
+/// on the SPI controllers.
+///
+typedef struct _EFI_SPI_CONFIGURATION_PROTOCOL {
+  ///
+  /// The number of SPI busses on the board.
+  ///
+  UINT32                          BusCount;
+
+  ///
+  /// The address of an array of EFI_SPI_BUS data structure addresses.
+  ///
+  CONST EFI_SPI_BUS *CONST *CONST Buslist;
+} EFI_SPI_CONFIGURATION_PROTOCOL;
+
+extern EFI_GUID gEfiSpiConfigurationProtocolGuid;
+
+#endif // __SPI_CONFIGURATION_PROTOCOL_H__
diff --git a/MdePkg/Include/Protocol/SpiHc.h b/MdePkg/Include/Protocol/SpiHc.h
new file mode 100644
index 000000000000..f875bc706be2
--- /dev/null
+++ b/MdePkg/Include/Protocol/SpiHc.h
@@ -0,0 +1,188 @@
+/** @file
+  This file defines the SPI Host Controller Protocol.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+    This Protocol was introduced in UEFI PI Specification 1.6.
+
+**/
+
+#ifndef __SPI_HC_PROTOCOL_H__
+#define __SPI_HC_PROTOCOL_H__
+
+#include <Protocol/SpiConfiguration.h>
+#include <Protocol/SpiIo.h>
+
+///
+/// Global ID for the SPI Host Controller Protocol
+///
+#define EFI_SPI_HOST_GUID  \
+  { 0xc74e5db2, 0xfa96, 0x4ae2,   \
+    { 0xb3, 0x99, 0x15, 0x97, 0x7f, 0xe3, 0x0, 0x2d }}
+
+///
+/// EDK2-style name
+///
+#define EFI_SPI_HC_PROTOCOL_GUID  EFI_SPI_HOST_GUID
+
+typedef struct _EFI_SPI_HC_PROTOCOL EFI_SPI_HC_PROTOCOL;
+
+/**
+  Assert or deassert the SPI chip select.
+
+  This routine is called at TPL_NOTIFY.
+  Update the value of the chip select line for a SPI peripheral. The SPI bus
+  layer calls this routine either in the board layer or in the SPI controller
+  to manipulate the chip select pin at the start and end of a SPI transaction.
+
+  @param[in] This           Pointer to an EFI_SPI_HC_PROTOCOL structure.
+  @param[in] SpiPeripheral  The address of an EFI_SPI_PERIPHERAL data structure
+                            describing the SPI peripheral whose chip select pin
+                            is to be manipulated. The routine may access the
+                            ChipSelectParameter field to gain sufficient
+                            context to complete the operati on.
+  @param[in] PinValue       The value to be applied to the chip select line of
+                            the SPI peripheral.
+
+  @retval EFI_SUCCESS            The chip select was set as requested
+  @retval EFI_NOT_READY          Support for the chip select is not properly
+                                 initialized
+  @retval EFI_INVALID_PARAMETER  The ChipSeLect value or its contents are
+                                 invalid
+
+**/
+typedef EFI_STATUS
+(EFIAPI *EFI_SPI_HC_PROTOCOL_CHIP_SELECT) (
+  IN CONST EFI_SPI_HC_PROTOCOL  *This,
+  IN CONST EFI_SPI_PERIPHERAL   *SpiPeripheral,
+  IN BOOLEAN                    PinValue
+  );
+
+/**
+  Set up the clock generator to produce the correct clock frequency, phase and
+  polarity for a SPI chip.
+
+  This routine is called at TPL_NOTIFY.
+  This routine updates the clock generator to generate the correct frequency
+  and polarity for the SPI clock.
+
+  @param[in] This           Pointer to an EFI_SPI_HC_PROTOCOL structure.
+  @param[in] SpiPeripheral  Pointer to a EFI_SPI_PERIPHERAL data structure from
+                            which the routine can access the ClockParameter,
+                            ClockPhase and ClockPolarity fields. The routine
+                            also has access to the names for the SPI bus and
+                            chip which can be used during debugging.
+  @param[in] ClockHz        Pointer to the requested clock frequency. The SPI
+                            host controller will choose a supported clock
+                            frequency which is less then or equal to this
+                            value. Specify zero to turn the clock generator
+                            off. The actual clock frequency supported by the
+                            SPI host controller will be returned.
+
+  @retval EFI_SUCCESS      The clock was set up successfully
+  @retval EFI_UNSUPPORTED  The SPI controller was not able to support the
+                           frequency requested by ClockHz
+
+**/
+typedef EFI_STATUS
+(EFIAPI *EFI_SPI_HC_PROTOCOL_CLOCK) (
+  IN CONST EFI_SPI_HC_PROTOCOL  *This,
+  IN CONST EFI_SPI_PERIPHERAL   *SpiPeripheral,
+  IN UINT32                      *ClockHz
+  );
+
+/**
+  Perform the SPI transaction on the SPI peripheral using the SPI host
+  controller.
+
+  This routine is called at TPL_NOTIFY.
+  This routine synchronously returns EFI_SUCCESS indicating that the
+  asynchronous SPI transaction was started. The routine then waits for
+  completion of the SPI transaction prior to returning the final transaction
+  status.
+
+  @param[in] This            Pointer to an EFI_SPI_HC_PROTOCOL structure.
+  @param[in] BusTransaction  Pointer to a EFI_SPI_BUS_ TRANSACTION containing
+                             the description of the SPI transaction to perform.
+
+  @retval EFI_SUCCESS          The transaction completed successfully
+  @retval EFI_BAD_BUFFER_SIZE  The BusTransaction->WriteBytes value is invalid,
+                               or the BusTransaction->ReadinBytes value is
+                               invalid
+  @retval EFI_UNSUPPORTED      The BusTransaction-> Transaction Type is
+                               unsupported
+
+**/
+typedef EFI_STATUS
+(EFIAPI *EFI_SPI_HC_PROTOCOL_TRANSACTION) (
+  IN CONST EFI_SPI_HC_PROTOCOL  *This,
+  IN EFI_SPI_BUS_TRANSACTION    *BusTransaction
+  );
+
+///
+/// Support a SPI data transaction between the SPI controller and a SPI chip.
+///
+struct _EFI_SPI_HC_PROTOCOL {
+  ///
+  /// Host control attributes, may have zero or more of the following set:
+  /// * HC_SUPPORTS_WRITE_ONLY_OPERATIONS
+  /// * HC_SUPPORTS_READ_ONLY_OPERATIONS
+  /// * HC_SUPPORTS_WRITE_THEN_READ_OPERATIONS
+  /// * HC_TX_FRAME_IN_MOST_SIGNIFICANT_BITS
+  ///   - The SPI host controller requires the transmit frame to be in most
+  ///     significant bits instead of least significant bits.The host driver
+  ///     will adjust the frames if necessary.
+  /// * HC_RX_FRAME_IN_MOST_SIGNIFICANT_BITS
+  ///   - The SPI host controller places the receive frame to be in most
+  ///     significant bits instead of least significant bits.The host driver
+  ///     will adjust the frames to be in the least significant bits if
+  ///     necessary.
+  /// * HC_SUPPORTS_2_BIT_DATA_BUS_W1DTH
+  ///   - The SPI controller supports a 2 - bit data bus
+  /// * HC_SUPPORTS_4_B1T_DATA_BUS_WIDTH
+  ///   - The SPI controller supports a 4 - bit data bus
+  /// * HC_TRANSFER_SIZE_INCLUDES_OPCODE
+  ///   - Transfer size includes the opcode byte
+  /// * HC_TRANSFER_SIZE_INCLUDES_ADDRESS
+  ///   - Transfer size includes the 3 address bytes
+  /// The SPI host controller must support full - duplex (receive while
+  /// sending) operation.The SPI host controller must support a 1 - bit bus
+  /// width.
+  ///
+  UINT32                          Attributes;
+
+  ///
+  /// Mask of frame sizes which the SPI host controller supports. Frame size of
+  /// N-bits is supported when bit N-1 is set. The host controller must support
+  /// a frame size of 8-bits.
+  ///
+  UINT32                          FrameSizeSupportMask;
+
+  ///
+  /// Maximum transfer size in bytes: 1 - Oxffffffff
+  ///
+  UINT32                          MaximumTransferBytes;
+
+  ///
+  /// Assert or deassert the SPI chip select.
+  ///
+  EFI_SPI_HC_PROTOCOL_CHIP_SELECT ChipSelect;
+
+  ///
+  /// Set up the clock generator to produce the correct clock frequency, phase
+  /// and polarity for a SPI chip.
+  ///
+  EFI_SPI_HC_PROTOCOL_CLOCK       Clock;
+
+  ///
+  /// Perform the SPI transaction on the SPI peripheral using the SPI host
+  /// controller.
+  ///
+  EFI_SPI_HC_PROTOCOL_TRANSACTION Transaction;
+};
+
+extern EFI_GUID gEfiSpiHcProtocolGuid;
+
+#endif // __SPI_HC_PROTOCOL_H__
diff --git a/MdePkg/Include/Protocol/SpiIo.h b/MdePkg/Include/Protocol/SpiIo.h
new file mode 100644
index 000000000000..449707e098e1
--- /dev/null
+++ b/MdePkg/Include/Protocol/SpiIo.h
@@ -0,0 +1,286 @@
+/** @file
+  This file defines the SPI I/O Protocol.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+    This Protocol was introduced in UEFI PI Specification 1.6.
+
+**/
+
+#ifndef __SPI_IO_PROTOCOL_H__
+#define __SPI_IO_PROTOCOL_H__
+
+#include <Protocol/LegacySpiController.h>
+#include <Protocol/SpiConfiguration.h>
+
+typedef struct _EFI_SPI_IO_PROTOCOL EFI_SPI_IO_PROTOCOL;
+
+///
+/// Note: The UEFI PI 1.6 specification does not specify values for the
+///       members below. The order matches the specification.
+///
+typedef enum {
+  ///
+  /// Data flowing in both direction between the host and
+  /// SPI peripheral.ReadBytes must equal WriteBytes and both ReadBuffer and
+  /// WriteBuffer must be provided.
+  ///
+  SPI_TRANSACTION_FULL_DUPLEX,
+
+  ///
+  /// Data flowing from the host to the SPI peripheral.ReadBytes must be
+  /// zero.WriteBytes must be non - zero and WriteBuffer must be provided.
+  ///
+  SPI_TRANSACTION_WRITE_ONLY,
+
+  ///
+  /// Data flowing from the SPI peripheral to the host.WriteBytes must be
+  /// zero.ReadBytes must be non - zero and ReadBuffer must be provided.
+  ///
+  SPI_TRANSACTION_READ_ONLY,
+
+  ///
+  /// Data first flowing from the host to the SPI peripheral and then data
+  /// flows from the SPI peripheral to the host.These types of operations get
+  /// used for SPI flash devices when control data (opcode, address) must be
+  /// passed to the SPI peripheral to specify the data to be read.
+  ///
+  SPI_TRANSACTION_WRITE_THEN_READ
+} EFI_SPI_TRANSACTION_TYPE;
+
+/**
+  Initiate a SPI transaction between the host and a SPI peripheral.
+
+  This routine must be called at or below TPL_NOTIFY.
+  This routine works with the SPI bus layer to pass the SPI transaction to the
+  SPI controller for execution on the SPI bus. There are four types of
+  supported transactions supported by this routine:
+  * Full Duplex: WriteBuffer and ReadBuffer are the same size.
+  * Write Only: WriteBuffer contains data for SPI peripheral, ReadBytes = 0
+  * Read Only: ReadBuffer to receive data from SPI peripheral, WriteBytes = 0
+  * Write Then Read: WriteBuffer contains control data to write to SPI
+                     peripheral before data is placed into the ReadBuffer.
+                     Both WriteBytes and ReadBytes must be non-zero.
+
+  @param[in]  This              Pointer to an EFI_SPI_IO_PROTOCOL structure.
+  @param[in]  TransactionType   Type of SPI transaction.
+  @param[in]  DebugTransaction  Set TRUE only when debugging is desired.
+                                Debugging may be turned on for a single SPI
+                                transaction. Only this transaction will display
+                                debugging messages. All other transactions with
+                                this value set to FALSE will not display any
+                                debugging messages.
+  @param[in]  ClockHz           Specify the ClockHz value as zero (0) to use
+                                the maximum clock frequency supported by the
+                                SPI controller and part. Specify a non-zero
+                                value only when a specific SPI transaction
+                                requires a reduced clock rate.
+  @param[in]  BusWidth          Width of the SPI bus in bits: 1, 2, 4
+  @param[in]  FrameSize         Frame size in bits, range: 1 - 32
+  @param[in]  WriteBytes        The length of the WriteBuffer in bytes.
+                                Specify zero for read-only operations.
+  @param[in]  WriteBuffer       The buffer containing data to be sent from the
+                                host to the SPI chip. Specify NULL for read
+                                only operations.
+                                * Frame sizes 1-8 bits: UINT8 (one byte) per
+                                  frame
+                                * Frame sizes 7-16 bits: UINT16 (two bytes) per
+                                  frame
+                                * Frame sizes 17-32 bits: UINT32 (four bytes)
+                                  per frame The transmit frame is in the least
+                                  significant N bits.
+  @param[in]  ReadBytes         The length of the ReadBuffer in bytes.
+                                Specify zero for write-only operations.
+  @param[out] ReadBuffer        The buffer to receeive data from the SPI chip
+                                during the transaction. Specify NULL for write
+                                only operations.
+                                * Frame sizes 1-8 bits: UINT8 (one byte) per
+                                  frame
+                                * Frame sizes 7-16 bits: UINT16 (two bytes) per
+                                  frame
+                                * Frame sizes 17-32 bits: UINT32 (four bytes)
+                                  per frame The received frame is in the least
+                                  significant N bits.
+
+  @retval EFI_SUCCESS            The SPI transaction completed successfully
+  @retval EFI_BAD_BUFFER_SIZE    The writeBytes value was invalid
+  @retval EFI_BAD_BUFFER_SIZE    The ReadBytes value was invalid
+  @retval EFI_INVALID_PARAMETER  TransactionType is not valid,
+                                 or BusWidth not supported by SPI peripheral or
+                                 SPI host controller,
+                                 or WriteBytes non-zero and WriteBuffer is
+                                 NULL,
+                                 or ReadBytes non-zero and ReadBuffer is NULL,
+                                 or ReadBuffer != WriteBuffer for full-duplex
+                                 type,
+                                 or WriteBuffer was NULL,
+                                 or TPL is too high
+  @retval EFI_OUT_OF_RESOURCES   Insufficient memory for SPI transaction
+  @retval EFI_UNSUPPORTED        The FrameSize is not supported by the SPI bus
+                                 layer or the SPI host controller
+  @retval EFI_UNSUPPORTED        The SPI controller was not able to support
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SPI_IO_PROTOCOL_TRANSACTION) (
+  IN  CONST EFI_SPI_IO_PROTOCOL  *This,
+  IN  EFI_SPI_TRANSACTION_TYPE   TransactionType,
+  IN  BOOLEAN                    DebugTransaction,
+  IN  UINT32                     ClockHz OPTIONAL,
+  IN  UINT32                     BusWidth,
+  IN  UINT32                     FrameSize,
+  IN  UINT32                     WriteBytes,
+  IN  UINT8                      *WriteBuffer,
+  IN  UINT32                     ReadBytes,
+  OUT UINT8                      *ReadBuffer
+  );
+
+/**
+  Update the SPI peripheral associated with this SPI 10 instance.
+
+  Support socketed SPI parts by allowing the SPI peripheral driver to replace
+  the SPI peripheral after the connection is made. An example use is socketed
+  SPI NOR flash parts, where the size and parameters change depending upon
+  device is in the socket.
+
+  @param[in] This           Pointer to an EFI_SPI_IO_PROTOCOL structure.
+  @param[in] SpiPeripheral  Pointer to an EFI_SPI_PERIPHERAL structure.
+
+  @retval EFI_SUCCESS            The SPI peripheral was updated successfully
+  @retval EFI_INVALID_PARAMETER  The SpiPeripheral value is NULL,
+                                 or the SpiPeripheral->SpiBus is NULL,
+                                 or the SpiP eripheral - >SpiBus pointing at
+                                 wrong bus,
+                                 or the SpiP eripheral - >SpiPart is NULL
+
+**/
+typedef EFI_STATUS
+(EFIAPI *EFI_SPI_IO_PROTOCOL_UPDATE_SPI_PERIPHERAL) (
+  IN CONST EFI_SPI_IO_PROTOCOL  *This,
+  IN CONST EFI_SPI_PERIPHERAL   *SpiPeripheral
+  );
+
+///
+/// The EFI_SPI_BUS_ TRANSACTION data structure contains the description of the
+/// SPI transaction to perform on the host controller.
+///
+typedef struct _EFI_SPI_BUS_TRANSACTION {
+  ///
+  /// Pointer to the SPI peripheral being manipulated.
+  ///
+  CONST EFI_SPI_PERIPHERAL *SpiPeripheral;
+
+  ///
+  /// Type of transaction specified by one of the EFI_SPI_TRANSACTION_TYPE
+  /// values.
+  ///
+  EFI_SPI_TRANSACTION_TYPE TransactionType;
+
+  ///
+  /// TRUE if the transaction is being debugged. Debugging may be turned on for
+  /// a single SPI transaction. Only this transaction will display debugging
+  /// messages. All other transactions with this value set to FALSE will not
+  /// display any debugging messages.
+  ///
+  BOOLEAN                  DebugTransaction;
+
+  ///
+  /// SPI bus width in bits: 1, 2, 4
+  ///
+  UINT32                   BusWidth;
+
+  ///
+  /// Frame size in bits, range: 1 - 32
+  ///
+  UINT32                   FrameSize;
+
+  ///
+  /// Length of the write buffer in bytes
+  ///
+  UINT32                   WriteBytes;
+
+  ///
+  /// Buffer containing data to send to the SPI peripheral
+  /// Frame sizes 1 - 8 bits: UINT8 (one byte) per frame
+  /// Frame sizes 7 - 16 bits : UINT16 (two bytes) per frame
+  ///
+  UINT8                    *WriteBuffer;
+
+  ///
+  /// Length of the read buffer in bytes
+  ///
+  UINT32                   ReadBytes;
+
+  ///
+  /// Buffer to receive the data from the SPI peripheral
+  /// * Frame sizes 1 - 8 bits: UINT8 (one byte) per frame
+  /// * Frame sizes 7 - 16 bits : UINT16 (two bytes) per frame
+  /// * Frame sizes 17 - 32 bits : UINT32 (four bytes) per frame
+  ///
+  UINT8                    *ReadBuffer;
+} EFI_SPI_BUS_TRANSACTION;
+
+///
+/// Support managed SPI data transactions between the SPI controller and a SPI
+/// chip.
+///
+struct _EFI_SPI_IO_PROTOCOL {
+  ///
+  /// Address of an EFI_SPI_PERIPHERAL data structure associated with this
+  /// protocol instance.
+  ///
+  CONST EFI_SPI_PERIPHERAL                  *SpiPeripheral;
+
+  ///
+  /// Address of the original EFI_SPI_PERIPHERAL data structure associated with
+  /// this protocol instance.
+  ///
+  CONST EFI_SPI_PERIPHERAL                  *OriginalSpiPeripheral;
+
+  ///
+  /// Mask of frame sizes which the SPI 10 layer supports. Frame size of N-bits
+  /// is supported when bit N-1 is set. The host controller must support a
+  /// frame size of 8-bits. Frame sizes of 16, 24 and 32-bits are converted to
+  /// 8-bit frame sizes by the SPI bus layer if the frame size is not supported
+  /// by the SPI host controller.
+  ///
+  UINT32                                    FrameSizeSupportMask;
+
+  ///
+  /// Maximum transfer size in bytes: 1 - Oxffffffff
+  ///
+  UINT32                                    MaximumTransferBytes;
+
+  ///
+  /// Transaction attributes: One or more from:
+  /// * SPI_10_SUPPORTS_2_B1T_DATA_BUS_W1DTH
+  ///   - The SPI host and peripheral supports a 2-bit data bus
+  /// * SPI_IO_SUPPORTS_4_BIT_DATA_BUS_W1DTH
+  ///   - The SPI host and peripheral supports a 4-bit data bus
+  /// * SPI_IO_TRANSFER_SIZE_INCLUDES_OPCODE
+  ///   - Transfer size includes the opcode byte
+  /// * SPI_IO_TRANSFER_SIZE_INCLUDES_ADDRESS
+  ///   - Transfer size includes the 3 address bytes
+  ///
+  UINT32                                    Attributes;
+
+  ///
+  /// Pointer to legacy SPI controller protocol
+  ///
+  CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL  *LegacySpiProtocol;
+
+  ///
+  /// Initiate a SPI transaction between the host and a SPI peripheral.
+  ///
+  EFI_SPI_IO_PROTOCOL_TRANSACTION           Transaction;
+
+  ///
+  /// Update the SPI peripheral associated with this SPI 10 instance.
+  ///
+  EFI_SPI_IO_PROTOCOL_UPDATE_SPI_PERIPHERAL UpdateSpiPeripheral;
+};
+
+#endif // __SPI_IO_PROTOCOL_H__
diff --git a/MdePkg/Include/Protocol/SpiNorFlash.h b/MdePkg/Include/Protocol/SpiNorFlash.h
new file mode 100644
index 000000000000..0c9dca79e6f4
--- /dev/null
+++ b/MdePkg/Include/Protocol/SpiNorFlash.h
@@ -0,0 +1,256 @@
+/** @file
+  This file defines the SPI NOR Flash Protocol.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+    This Protocol was introduced in UEFI PI Specification 1.6.
+
+**/
+
+#ifndef __SPI_NOR_FLASH_PROTOCOL_H__
+#define __SPI_NOR_FLASH_PROTOCOL_H__
+
+#include <Protocol/SpiConfiguration.h>
+
+///
+/// Global ID for the SPI NOR Flash Protocol
+///
+#define EFI_SPI_NOR_FLASH_PROTOCOL_GUID  \
+  { 0xb57ec3fe, 0xf833, 0x4ba6,          \
+    { 0x85, 0x78, 0x2a, 0x7d, 0x6a, 0x87, 0x44, 0x4b }}
+
+typedef struct _EFI_SPI_NOR_FLASH_PROTOCOL EFI_SPI_NOR_FLASH_PROTOCOL;
+
+/**
+  Read the 3 byte manufacture and device ID from the SPI flash.
+
+  This routine must be called at or below TPL_NOTIFY.
+  This routine reads the 3 byte manufacture and device ID from the flash part
+  filling the buffer provided.
+
+  @param[in]  This    Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data structure.
+  @param[out] Buffer  Pointer to a 3 byte buffer to receive the manufacture and
+                      device ID.
+
+
+
+  @retval EFI_SUCCESS            The manufacture and device ID was read
+                                 successfully.
+  @retval EFI_INVALID_PARAMETER  Buffer is NULL
+  @retval EFI_DEVICE_ERROR       Invalid data received from SPI flash part.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SPI_NOR_FLASH_PROTOCOL_GET_FLASH_ID) (
+  IN  CONST EFI_SPI_NOR_FLASH_PROTOCOL  *This,
+  OUT UINT8                             *Buffer
+  );
+
+/**
+  Read data from the SPI flash.
+
+  This routine must be called at or below TPL_NOTIFY.
+  This routine reads data from the SPI part in the buffer provided.
+
+  @param[in]  This           Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data
+                             structure.
+  @param[in]  FlashAddress   Address in the flash to start reading
+  @param[in]  LengthInBytes  Read length in bytes
+  @param[out] Buffer         Address of a buffer to receive the data
+
+  @retval EFI_SUCCESS            The data was read successfully.
+  @retval EFI_INVALID_PARAMETER  Buffer is NULL, or
+                                 FlashAddress >= This->FlashSize, or
+                                 LengthInBytes > This->FlashSize - FlashAddress
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SPI_NOR_FLASH_PROTOCOL_READ_DATA) (
+  IN  CONST EFI_SPI_NOR_FLASH_PROTOCOL  *This,
+  IN  UINT32                            FlashAddress,
+  IN  UINT32                            LengthInBytes,
+  OUT UINT8                             *Buffer
+  );
+
+/**
+  Read the flash status register.
+
+  This routine must be called at or below TPL_NOTIFY.
+  This routine reads the flash part status register.
+
+  @param[in]  This           Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data
+                             structure.
+  @param[in]  LengthInBytes  Number of status bytes to read.
+  @param[out] FlashStatus    Pointer to a buffer to receive the flash status.
+
+  @retval EFI_SUCCESS  The status register was read successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SPI_NOR_FLASH_PROTOCOL_READ_STATUS) (
+  IN  CONST EFI_SPI_NOR_FLASH_PROTOCOL  *This,
+  IN  UINT32                            LengthInBytes,
+  OUT UINT8                             *FlashStatus
+  );
+
+/**
+  Write the flash status register.
+
+  This routine must be called at or below TPL_N OTIFY.
+  This routine writes the flash part status register.
+
+  @param[in] This           Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data
+                            structure.
+  @param[in] LengthInBytes  Number of status bytes to write.
+  @param[in] FlashStatus    Pointer to a buffer containing the new status.
+
+  @retval EFI_SUCCESS           The status write was successful.
+  @retval EFI_OUT_OF_RESOURCES  Failed to allocate the write buffer.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SPI_NOR_FLASH_PROTOCOL_WRITE_STATUS) (
+  IN CONST EFI_SPI_NOR_FLASH_PROTOCOL  *This,
+  IN UINT32                            LengthInBytes,
+  IN UINT8                             *FlashStatus
+  );
+
+/**
+  Write data to the SPI flash.
+
+  This routine must be called at or below TPL_NOTIFY.
+  This routine breaks up the write operation as necessary to write the data to
+  the SPI part.
+
+  @param[in] This           Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data
+                            structure.
+  @param[in] FlashAddress   Address in the flash to start writing
+  @param[in] LengthInBytes  Write length in bytes
+  @param[in] Buffer         Address of a buffer containing the data
+
+  @retval EFI_SUCCESS            The data was written successfully.
+  @retval EFI_INVALID_PARAMETER  Buffer is NULL, or
+                                 FlashAddress >= This->FlashSize, or
+                                 LengthInBytes > This->FlashSize - FlashAddress
+  @retval EFI_OUT_OF_RESOURCES   Insufficient memory to copy buffer.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SPI_NOR_FLASH_PROTOCOL_WRITE_DATA) (
+  IN CONST EFI_SPI_NOR_FLASH_PROTOCOL  *This,
+  IN UINT32                            FlashAddress,
+  IN UINT32                            LengthInBytes,
+  IN UINT8                             *Buffer
+  );
+
+/**
+  Efficiently erases one or more 4KiB regions in the SPI flash.
+
+  This routine must be called at or below TPL_NOTIFY.
+  This routine uses a combination of 4 KiB and larger blocks to erase the
+  specified area.
+
+  @param[in] This          Pointer to an EFI_SPI_NOR_FLASH_PROTOCOL data
+                           structure.
+  @param[in] FlashAddress  Address within a 4 KiB block to start erasing
+  @param[in] BlockCount    Number of 4 KiB blocks to erase
+
+  @retval EFI_SUCCESS            The erase was completed successfully.
+  @retval EFI_INVALID_PARAMETER  FlashAddress >= This->FlashSize, or
+                                 BlockCount * 4 KiB
+                                   > This->FlashSize - FlashAddress
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_SPI_NOR_FLASH_PROTOCOL_ERASE) (
+  IN CONST EFI_SPI_NOR_FLASH_PROTOCOL  *This,
+  IN UINT32                            FlashAddress,
+  IN UINT32                            BlockCount
+  );
+
+///
+/// The EFI_SPI_NOR_FLASH_PROTOCOL exists in the SPI peripheral layer.
+/// This protocol manipulates the SPI NOR flash parts using a common set of
+/// commands. The board layer provides the interconnection and configuration
+/// details for the SPI NOR flash part. The SPI NOR flash driver uses this
+/// configuration data to expose a generic interface which provides the
+/// following APls:
+/// * Read manufacture and device ID
+/// * Read data
+/// * Read data using low frequency
+/// * Read status
+/// * Write data
+/// * Erase 4 KiB blocks
+/// * Erase 32 or 64 KiB blocks
+/// * Write status
+/// The EFI_SPI_NOR_FLASH_PROTOCOL also exposes some APls to set the security
+/// features on the legacy SPI flash controller.
+///
+struct _EFI_SPI_NOR_FLASH_PROTOCOL {
+  ///
+  /// Pointer to an EFI_SPI_PERIPHERAL data structure
+  ///
+  CONST EFI_SPI_PERIPHERAL                *SpiPeripheral;
+
+  ///
+  /// Flash size in bytes
+  ///
+  UINT32                                  FlashSize;
+
+  ///
+  /// Manufacture and Device ID
+  ///
+  UINT8                                   Deviceid[3];
+
+  ///
+  /// Erase block size in bytes
+  ///
+  UINT32                                  EraseBlockBytes;
+
+  ///
+  /// Read the 3 byte manufacture and device ID from the SPI flash.
+  ///
+  EFI_SPI_NOR_FLASH_PROTOCOL_GET_FLASH_ID GetFlashid;
+
+  ///
+  /// Read data from the SPI flash.
+  ///
+  EFI_SPI_NOR_FLASH_PROTOCOL_READ_DATA    ReadData;
+
+  ///
+  /// Low frequency read data from the SPI flash.
+  ///
+  EFI_SPI_NOR_FLASH_PROTOCOL_READ_DATA    LfReadData;
+
+  ///
+  /// Read the flash status register.
+  ///
+  EFI_SPI_NOR_FLASH_PROTOCOL_READ_STATUS  ReadStatus;
+
+  ///
+  /// Write the flash status register.
+  ///
+  EFI_SPI_NOR_FLASH_PROTOCOL_WRITE_STATUS WriteStatus;
+
+  ///
+  /// Write data to the SPI flash.
+  ///
+  EFI_SPI_NOR_FLASH_PROTOCOL_WRITE_DATA   WriteData;
+
+  ///
+  /// Efficiently erases one or more 4KiB regions in the SPI flash.
+  ///
+  EFI_SPI_NOR_FLASH_PROTOCOL_ERASE        Erase;
+};
+
+extern EFI_GUID gEfiSpiNorFlashProtocolGuid;
+
+#endif // __SPI_NOR_FLASH_PROTOCOL_H__
diff --git a/MdePkg/Include/Protocol/SpiSmmConfiguration.h b/MdePkg/Include/Protocol/SpiSmmConfiguration.h
new file mode 100644
index 000000000000..8bb713c80e4c
--- /dev/null
+++ b/MdePkg/Include/Protocol/SpiSmmConfiguration.h
@@ -0,0 +1,30 @@
+/** @file
+  This file defines the SPI SMM Configuration Protocol.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+    This Protocol was introduced in UEFI PI Specification 1.6.
+
+**/
+
+#ifndef __SPI_SMM_CONFIGURATION_PROTOCOL_H__
+#define __SPI_SMM_CONFIGURATION_PROTOCOL_H__
+
+#include <Protocol/SpiConfiguration.h>
+
+///
+/// Global ID for the SPI SMM Configuration Protocol
+///
+#define EFI_SPI_SMM_CONFIGURATION_PROTOCOL_GUID  \
+  { 0x995c6eca, 0x171b, 0x45fd,                  \
+    { 0xa3, 0xaa, 0xfd, 0x4c, 0x9c, 0x9d, 0xef, 0x59 }}
+
+typedef
+struct _EFI_SPI_CONFIGURATION_PROTOCOL
+EFI_SPI_SMM_CONFIGURATION_PROTOCOL;
+
+extern EFI_GUID gEfiSpiSmmConfigurationProtocolGuid;
+
+#endif // __SPI_SMM_CONFIGURATION_H__
diff --git a/MdePkg/Include/Protocol/SpiSmmHc.h b/MdePkg/Include/Protocol/SpiSmmHc.h
new file mode 100644
index 000000000000..fb7a25957107
--- /dev/null
+++ b/MdePkg/Include/Protocol/SpiSmmHc.h
@@ -0,0 +1,30 @@
+/** @file
+  This file defines the SPI SMM Host Controller Protocol.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+    This Protocol was introduced in UEFI PI Specification 1.6.
+
+**/
+
+#ifndef __SPI_SMM_HC_H__
+#define __SPI_SMM_HC_H__
+
+#include <Protocol/SpiHc.h>
+
+///
+/// Global ID for the SPI SMM Host Controller Protocol
+///
+#define EFI_SPI_SMM_HC_PROTOCOL_GUID  \
+  { 0xe9f02217, 0x2093, 0x4470,       \
+    { 0x8a, 0x54, 0x5c, 0x2c, 0xff, 0xe7, 0x3e, 0xcb }}
+
+typedef
+struct _EFI_SPI_HC_PROTOCOL
+EFI_SPI_SMM_HC_PROTOCOL;
+
+extern EFI_GUID gEfiSpiSmmHcProtocolGuid;
+
+#endif // __SPI_SMM_HC_H__
diff --git a/MdePkg/Include/Protocol/SpiSmmNorFlash.h b/MdePkg/Include/Protocol/SpiSmmNorFlash.h
new file mode 100644
index 000000000000..dfb61f359ef8
--- /dev/null
+++ b/MdePkg/Include/Protocol/SpiSmmNorFlash.h
@@ -0,0 +1,30 @@
+/** @file
+  This file defines the SPI SMM NOR Flash Protocol.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+    This Protocol was introduced in UEFI PI Specification 1.6.
+
+**/
+
+#ifndef __SPI_SMM_NOR_FLASH_PROTOCOL_H__
+#define __SPI_SMM_NOR_FLASH_PROTOCOL_H__
+
+#include <Protocol/SpiNorFlash.h>
+
+///
+/// Global ID for the SPI SMM NOR Flash Protocol
+///
+#define EFI_SPI_SMM_NOR_FLASH_PROTOCOL_GUID  \
+  { 0xaab18f19, 0xfe14, 0x4666,              \
+    { 0x86, 0x04, 0x87, 0xff, 0x6d, 0x66, 0x2c, 0x9a } }
+
+typedef
+struct _EFI_SPI_NOR_FLASH_PROTOCOL
+EFI_SPI_SMM_NOR_FLASH_PROTOCOL;
+
+extern EFI_GUID gEfiSpiSmmNorFlashProtocolGuid;
+
+#endif // __SPI_SMM_NOR_FLASH_PROTOCOL_H__
diff --git a/MdePkg/Include/Protocol/StatusCode.h b/MdePkg/Include/Protocol/StatusCode.h
index d5c62260a01d..90b1f63d3b67 100644
--- a/MdePkg/Include/Protocol/StatusCode.h
+++ b/MdePkg/Include/Protocol/StatusCode.h
@@ -1,14 +1,8 @@
 /** @file
   Status code Runtime Protocol as defined in PI Specification 1.4a VOLUME 2 DXE
 
-  Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/Protocol/StorageSecurityCommand.h b/MdePkg/Include/Protocol/StorageSecurityCommand.h
index 3fa6cbcd8e3b..db38fb491e02 100644
--- a/MdePkg/Include/Protocol/StorageSecurityCommand.h
+++ b/MdePkg/Include/Protocol/StorageSecurityCommand.h
@@ -5,14 +5,8 @@
   storage devices without specific knowledge of the type of device or controller
   that manages the device.
 
-  Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -149,7 +143,7 @@ EFI_STATUS
                                        of the security protocol command. A Timeout value of 0
                                        means that this function will wait indefinitely for the
                                        security protocol command to execute. If Timeout is greater
-                                       than zero, then this function will return EFI_TIMEOUT if the 
+                                       than zero, then this function will return EFI_TIMEOUT if the
                                        time required to execute the receive data command is greater than Timeout.
   @param  SecurityProtocolId           The value of the "Security Protocol" parameter of
                                        the security protocol command to be sent.
diff --git a/MdePkg/Include/Protocol/SuperIo.h b/MdePkg/Include/Protocol/SuperIo.h
index f9714e2d1f87..fb5ea855c970 100644
--- a/MdePkg/Include/Protocol/SuperIo.h
+++ b/MdePkg/Include/Protocol/SuperIo.h
@@ -5,14 +5,8 @@
   Super I/O is powered up, enabled, and assigned with the default set of resources. In the Stop()
   routine of the Super I/O driver, the device is disabled and Super I/O protocol is uninstalled.
 
-  Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -33,12 +27,12 @@ typedef struct {
   UINT8 AndMask;        ///< Bitwise AND mask.
   UINT8 OrMask;         ///< Bitwise OR mask.
 } EFI_SIO_REGISTER_MODIFY;
-  
+
 typedef struct _EFI_SIO_PROTOCOL  EFI_SIO_PROTOCOL;
-  
+
 /**
   Provides a low level access to the registers for the Super I/O.
-  
+
   @param[in]        This        Indicates a pointer to the calling context.
   @param[in]        Write       Specifies the type of the register operation. If this parameter is TRUE, Value is
                                 interpreted as an input parameter and the operation is a register write. If this parameter
@@ -53,13 +47,13 @@ typedef struct _EFI_SIO_PROTOCOL  EFI_SIO_PROTOCOL;
   @param[in]        Register    Register number.
   @param[in, out]   Value       If Write is TRUE, Value is a pointer to the buffer containing the byte of data to be
                                 written to the Super I/O register. If Write is FALSE, Value is a pointer to the
-                                destination buffer for the byte of data to be read from the Super I/O register. 
+                                destination buffer for the byte of data to be read from the Super I/O register.
 
   @retval EFI_SUCCESS           The operation completed successfully
   @retval EFI_INVALID_PARAMETER The Value is NULL
   @retval EFI_INVALID_PARAMETER Invalid Register number
-  
-**/  
+
+**/
 typedef
 EFI_STATUS
 (EFIAPI *EFI_SIO_REGISTER_ACCESS)(
@@ -69,36 +63,36 @@ EFI_STATUS
   IN          UINT8             Register,
   IN OUT      UINT8             *Value
 );
-  
+
 /**
   Provides an interface to get a list of the current resources consumed by the device in the ACPI
   Resource Descriptor format.
-  
+
   GetResources() returns a list of resources currently consumed by the device. The
   ResourceList is a pointer to the buffer containing resource descriptors for the device. The
   descriptors are in the format of Small or Large ACPI resource descriptor as defined by ACPI
   specification (2.0 & 3.0). The buffer of resource descriptors is terminated with the 'End tag'
   resource descriptor.
-  
+
   @param[in]    This            Indicates a pointer to the calling context.
   @param[out]   ResourceList    A pointer to an ACPI resource descriptor list that defines the current resources used by
                                 the device. Type ACPI_RESOURCE_HEADER_PTR is defined in the "Related
                                 Definitions" below.
-                                
+
   @retval EFI_SUCCESS           The operation completed successfully
   @retval EFI_INVALID_PARAMETER ResourceList is NULL
-                                
-**/  
+
+**/
 typedef
 EFI_STATUS
 (EFIAPI *EFI_SIO_GET_RESOURCES)(
   IN  CONST EFI_SIO_PROTOCOL            *This,
   OUT       ACPI_RESOURCE_HEADER_PTR    *ResourceList
 );
-  
+
 /**
   Sets the resources for the device.
-  
+
   @param[in]  This          Indicates a pointer to the calling context.
   @param[in]  ResourceList  Pointer to the ACPI resource descriptor list. Type ACPI_RESOURCE_HEADER_PTR
                             is defined in the "Related Definitions" section of
@@ -107,35 +101,35 @@ EFI_STATUS
   @retval EFI_SUCCESS           The operation completed successfully
   @retval EFI_INVALID_PARAMETER ResourceList is invalid
   @retval EFI_ACCESS_DENIED     Some of the resources in ResourceList are in use
-                            
-**/  
+
+**/
 typedef
 EFI_STATUS
 (EFIAPI *EFI_SIO_SET_RESOURCES)(
   IN CONST  EFI_SIO_PROTOCOL        *This,
   IN        ACPI_RESOURCE_HEADER_PTR ResourceList
 );
-  
+
 /**
   Provides a collection of resource descriptor lists. Each resource descriptor list in the collection
   defines a combination of resources that can potentially be used by the device.
-  
+
   @param[in]  This                  Indicates a pointer to the calling context.
   @param[out] ResourceCollection    Collection of the resource descriptor lists.
-  
+
   @retval EFI_SUCCESS               The operation completed successfully
   @retval EFI_INVALID_PARAMETER     ResourceCollection is NULL
-**/  
+**/
 typedef
 EFI_STATUS
 (EFIAPI *EFI_SIO_POSSIBLE_RESOURCES)(
   IN  CONST EFI_SIO_PROTOCOL         *This,
   OUT       ACPI_RESOURCE_HEADER_PTR *ResourceCollection
 );
-  
+
 /**
   Provides an interface for a table based programming of the Super I/O registers.
-  
+
   The Modify() function provides an interface for table based programming of the Super I/O
   registers. This function can be used to perform programming of multiple Super I/O registers with a
   single function call. For each table entry, the Register is read, its content is bitwise ANDed with
@@ -148,12 +142,12 @@ EFI_STATUS
   @param[in] Command    A pointer to an array of NumberOfCommands EFI_SIO_REGISTER_MODIFY
                         structures. Each structure specifies a single Super I/O register modify operation. Type
                         EFI_SIO_REGISTER_MODIFY is defined in the "Related Definitions" below.
-  @param[in] NumberOfCommands Number of elements in the Command array.  
-  
+  @param[in] NumberOfCommands Number of elements in the Command array.
+
   @retval EFI_SUCCESS           The operation completed successfully
   @retval EFI_INVALID_PARAMETER Command is NULL
-  
-**/  
+
+**/
 typedef
 EFI_STATUS
 (EFIAPI *EFI_SIO_MODIFY)(
@@ -161,14 +155,14 @@ EFI_STATUS
   IN CONST EFI_SIO_REGISTER_MODIFY  *Command,
   IN       UINTN                    NumberOfCommands
 );
-  
+
 struct _EFI_SIO_PROTOCOL {
   EFI_SIO_REGISTER_ACCESS       RegisterAccess;
   EFI_SIO_GET_RESOURCES         GetResources;
   EFI_SIO_SET_RESOURCES         SetResources;
   EFI_SIO_POSSIBLE_RESOURCES    PossibleResources;
   EFI_SIO_MODIFY Modify;
-};  
+};
 
 extern EFI_GUID gEfiSioProtocolGuid;
 
diff --git a/MdePkg/Include/Protocol/SuperIoControl.h b/MdePkg/Include/Protocol/SuperIoControl.h
index 0bcfb5a47388..1f2f62345ac5 100644
--- a/MdePkg/Include/Protocol/SuperIoControl.h
+++ b/MdePkg/Include/Protocol/SuperIoControl.h
@@ -3,14 +3,8 @@
   the low-level services for SIO devices that enable them to be used in the UEFI
   driver model.
 
-  Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This protocol is from PI Version 1.2.1.
@@ -38,7 +32,7 @@ typedef struct _EFI_SIO_CONTROL_PROTOCOL *PEFI_SIO_CONTROL_PROTOCOL;
 
   @retval EFI_SUCCESS          The device is enabled successfully.
   @retval EFI_OUT_OF_RESOURCES The device could not be enabled because there
-                               were insufficient resources either for the device 
+                               were insufficient resources either for the device
                                itself or for the records needed to track the device.
   @retval EFI_ALREADY_STARTED  The device is already enabled.
   @retval EFI_UNSUPPORTED      The device cannot be enabled.
@@ -61,7 +55,7 @@ EFI_STATUS
 
   @retval EFI_SUCCESS          The device is disabled successfully.
   @retval EFI_OUT_OF_RESOURCES The device could not be disabled because there
-                               were insufficient resources either for the device 
+                               were insufficient resources either for the device
                                itself or for the records needed to track the device.
   @retval EFI_ALREADY_STARTED  The device is already disabled.
   @retval EFI_UNSUPPORTED      The device cannot be disabled.
diff --git a/MdePkg/Include/Protocol/Supplicant.h b/MdePkg/Include/Protocol/Supplicant.h
index 6376823c29ed..d7cfc2ad26af 100644
--- a/MdePkg/Include/Protocol/Supplicant.h
+++ b/MdePkg/Include/Protocol/Supplicant.h
@@ -1,14 +1,8 @@
 /** @file
   This file defines the EFI Supplicant Protocol.
 
-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution. The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This Protocol is introduced in UEFI Specification 2.6
@@ -152,6 +146,10 @@ typedef enum {
   // EFI_SUPPLICANT_GTK_LIST.
   //
   EfiSupplicant80211IGTK,
+  //
+  // 802.11 PMK. The corresponding Data is 32 bytes pairwise master key.
+  //
+  EfiSupplicant80211PMK,
   EfiSupplicantDataTypeMaximum
 } EFI_SUPPLICANT_DATA_TYPE;
 
diff --git a/MdePkg/Include/Protocol/TapeIo.h b/MdePkg/Include/Protocol/TapeIo.h
index 74c7b3f6587d..1eac48c2d78a 100644
--- a/MdePkg/Include/Protocol/TapeIo.h
+++ b/MdePkg/Include/Protocol/TapeIo.h
@@ -2,14 +2,8 @@
   EFI_TAPE_IO_PROTOCOL as defined in the UEFI 2.0.
   Provide services to control and access a tape device.
 
-Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -70,13 +64,13 @@ typedef struct _EFI_TAPE_HEADER {
                                 from the media.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_TAPE_READ)(
   IN EFI_TAPE_IO_PROTOCOL *This,
   IN OUT UINTN            *BufferSize,
   OUT VOID                *Buffer
-  );    
+  );
 
 /**
   Writes to the tape.
@@ -106,14 +100,14 @@ EFI_STATUS
                                 from the media.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_TAPE_WRITE)(
   IN EFI_TAPE_IO_PROTOCOL *This,
   IN UINTN                *BufferSize,
   IN VOID                 *Buffer
-  ); 
-  
+  );
+
 
 /**
   Rewinds the tape.
@@ -129,11 +123,11 @@ EFI_STATUS
   @retval EFI_DEVICE_ERROR A device error occurred while attempting to reposition the media.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_TAPE_REWIND)(
   IN EFI_TAPE_IO_PROTOCOL *This
-  );   
+  );
 
 
 /**
@@ -143,7 +137,7 @@ EFI_STATUS
   @param  Direction Direction and number of data blocks or filemarks to space over on media.
   @param  Type      Type of mark to space over on media.
                     The following Type marks are mandatory:
-                    BLOCK type    : 0 
+                    BLOCK type    : 0
                     FILEMARK type : 1
 
   @retval EFI_SUCCESS       The media was successfully repositioned.
@@ -166,7 +160,7 @@ EFI_STATUS
   IN EFI_TAPE_IO_PROTOCOL *This,
   IN INTN                 Direction,
   IN UINTN                Type
-  );   
+  );
 
 
 /**
@@ -187,12 +181,12 @@ EFI_STATUS
   @retval EFI_DEVICE_ERROR  A device error occurred while attempting to transfer data from the media.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_TAPE_WRITEFM)(
   IN EFI_TAPE_IO_PROTOCOL *This,
   IN UINTN                Count
-  );   
+  );
 
 
 /**
@@ -210,17 +204,17 @@ EFI_STATUS
   @retval  EFI_DEVICE_ERROR A device error occurred while attempting to reset the bus and/or device.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_TAPE_RESET)(
   IN EFI_TAPE_IO_PROTOCOL *This,
   IN BOOLEAN              ExtendedVerification
-  );    
+  );
 
 ///
-/// The EFI_TAPE_IO_PROTOCOL provides basic sequential operations for tape devices. 
-/// These include read, write, rewind, space, write filemarks and reset functions. 
-/// Per this specification, a boot application uses the services of this protocol 
+/// The EFI_TAPE_IO_PROTOCOL provides basic sequential operations for tape devices.
+/// These include read, write, rewind, space, write filemarks and reset functions.
+/// Per this specification, a boot application uses the services of this protocol
 /// to load the bootloader image from tape.
 ///
 struct _EFI_TAPE_IO_PROTOCOL {
diff --git a/MdePkg/Include/Protocol/Tcg2Protocol.h b/MdePkg/Include/Protocol/Tcg2Protocol.h
index 042bdffa1f71..04a209cfdfe6 100644
--- a/MdePkg/Include/Protocol/Tcg2Protocol.h
+++ b/MdePkg/Include/Protocol/Tcg2Protocol.h
@@ -2,14 +2,8 @@
   TPM2 Protocol as defined in TCG PC Client Platform EFI Protocol Specification Family "2.0".
   See http://trustedcomputinggroup.org for the latest specification
 
-Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials 
-are licensed and made available under the terms and conditions of the BSD License 
-which accompanies this distribution.  The full text of the license may be found at 
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -44,13 +38,13 @@ typedef struct tdEFI_TCG2_BOOT_SERVICE_CAPABILITY {
   //
   // Version of the EFI_TCG2_BOOT_SERVICE_CAPABILITY structure itself.
   // For this version of the protocol, the Major version shall be set to 1
-  // and the Minor version shall be set to 1. 
+  // and the Minor version shall be set to 1.
   //
   EFI_TCG2_VERSION                 StructureVersion;
   //
   // Version of the EFI TCG2 protocol.
   // For this version of the protocol, the Major version shall be set to 1
-  // and the Minor version shall be set to 1. 
+  // and the Minor version shall be set to 1.
   //
   EFI_TCG2_VERSION                 ProtocolVersion;
   //
@@ -116,7 +110,7 @@ typedef struct tdEFI_TCG2_BOOT_SERVICE_CAPABILITY {
 
 typedef struct {
   //
-  // Size of the event header itself (sizeof(EFI_TCG2_EVENT_HEADER)). 
+  // Size of the event header itself (sizeof(EFI_TCG2_EVENT_HEADER)).
   //
   UINT32            HeaderSize;
   //
@@ -124,18 +118,18 @@ typedef struct {
   //
   UINT16            HeaderVersion;
   //
-  // Index of the PCR that shall be extended (0 - 23). 
+  // Index of the PCR that shall be extended (0 - 23).
   //
   TCG_PCRINDEX      PCRIndex;
   //
-  // Type of the event that shall be extended (and optionally logged). 
+  // Type of the event that shall be extended (and optionally logged).
   //
   TCG_EVENTTYPE     EventType;
 } EFI_TCG2_EVENT_HEADER;
 
 typedef struct tdEFI_TCG2_EVENT {
   //
-  // Total size of the event including the Size component, the header and the Event data. 
+  // Total size of the event including the Size component, the header and the Event data.
   //
   UINT32                Size;
   EFI_TCG2_EVENT_HEADER Header;
@@ -157,11 +151,11 @@ typedef struct tdEFI_TCG2_EVENT {
 
   @retval EFI_SUCCESS            Operation completed successfully.
   @retval EFI_DEVICE_ERROR       The command was unsuccessful.
-                                 The ProtocolCapability variable will not be populated. 
+                                 The ProtocolCapability variable will not be populated.
   @retval EFI_INVALID_PARAMETER  One or more of the parameters are incorrect.
                                  The ProtocolCapability variable will not be populated.
   @retval EFI_BUFFER_TOO_SMALL   The ProtocolCapability variable is too small to hold the full response.
-                                 It will be partially populated (required Size field will be set). 
+                                 It will be partially populated (required Size field will be set).
 **/
 typedef
 EFI_STATUS
@@ -172,7 +166,7 @@ EFI_STATUS
 
 /**
   The EFI_TCG2_PROTOCOL Get Event Log function call allows a caller to
-  retrieve the address of a given event log and its last entry. 
+  retrieve the address of a given event log and its last entry.
 
   @param[in]  This               Indicates the calling context
   @param[in]  EventLogFormat     The type of the event log for which the information is requested.
@@ -200,13 +194,13 @@ EFI_STATUS
 /**
   The EFI_TCG2_PROTOCOL HashLogExtendEvent function call provides callers with
   an opportunity to extend and optionally log events without requiring
-  knowledge of actual TPM commands. 
+  knowledge of actual TPM commands.
   The extend operation will occur even if this function cannot create an event
-  log entry (e.g. due to the event log being full). 
+  log entry (e.g. due to the event log being full).
 
   @param[in]  This               Indicates the calling context
   @param[in]  Flags              Bitmap providing additional information.
-  @param[in]  DataToHash         Physical address of the start of the data buffer to be hashed. 
+  @param[in]  DataToHash         Physical address of the start of the data buffer to be hashed.
   @param[in]  DataToHashLen      The length in bytes of the buffer referenced by DataToHash.
   @param[in]  EfiTcgEvent        Pointer to data buffer containing information about the event.
 
@@ -238,7 +232,7 @@ EFI_STATUS
   @retval EFI_SUCCESS            The command byte stream was successfully sent to the device and a response was successfully received.
   @retval EFI_DEVICE_ERROR       The command was not successfully sent to the device or a response was not successfully received from the device.
   @retval EFI_INVALID_PARAMETER  One or more of the parameters are incorrect.
-  @retval EFI_BUFFER_TOO_SMALL   The output parameter block is too small. 
+  @retval EFI_BUFFER_TOO_SMALL   The output parameter block is too small.
 **/
 typedef
 EFI_STATUS
@@ -257,7 +251,7 @@ EFI_STATUS
   @param[out] ActivePcrBanks  Pointer to the variable receiving the bitmap of currently active PCR banks.
 
   @retval EFI_SUCCESS           The bitmap of active PCR banks was stored in the ActivePcrBanks parameter.
-  @retval EFI_INVALID_PARAMETER One or more of the parameters are incorrect. 
+  @retval EFI_INVALID_PARAMETER One or more of the parameters are incorrect.
 **/
 typedef
 EFI_STATUS
diff --git a/MdePkg/Include/Protocol/TcgService.h b/MdePkg/Include/Protocol/TcgService.h
index 7e8ba0c25669..937bd12f2410 100644
--- a/MdePkg/Include/Protocol/TcgService.h
+++ b/MdePkg/Include/Protocol/TcgService.h
@@ -2,14 +2,8 @@
   TCG Service Protocol as defined in TCG_EFI_Protocol_1_22_Final
   See http://trustedcomputinggroup.org for the latest specification
 
-Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -19,7 +13,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #include <IndustryStandard/UefiTcgPlatform.h>
 
 #define EFI_TCG_PROTOCOL_GUID  \
-  {0xf541796d, 0xa62e, 0x4954, { 0xa7, 0x75, 0x95, 0x84, 0xf6, 0x1b, 0x9c, 0xdd } } 
+  {0xf541796d, 0xa62e, 0x4954, { 0xa7, 0x75, 0x95, 0x84, 0xf6, 0x1b, 0x9c, 0xdd } }
 
 typedef struct _EFI_TCG_PROTOCOL EFI_TCG_PROTOCOL;
 
@@ -32,9 +26,9 @@ typedef struct {
 
 typedef struct _TCG_EFI_BOOT_SERVICE_CAPABILITY {
   UINT8          Size;                /// Size of this structure.
-  TCG_VERSION    StructureVersion;    
+  TCG_VERSION    StructureVersion;
   TCG_VERSION    ProtocolSpecVersion;
-  UINT8          HashAlgorithmBitmap; /// Hash algorithms . 
+  UINT8          HashAlgorithmBitmap; /// Hash algorithms .
                                       /// This protocol is capable of : 01=SHA-1.
   BOOLEAN        TPMPresentFlag;      /// 00h = TPM not present.
   BOOLEAN        TPMDeactivatedFlag;  /// 01h = TPM currently deactivated.
@@ -43,22 +37,22 @@ typedef struct _TCG_EFI_BOOT_SERVICE_CAPABILITY {
 typedef UINT32   TCG_ALGORITHM_ID;
 
 /**
-  This service provides EFI protocol capability information, state information 
+  This service provides EFI protocol capability information, state information
   about the TPM, and Event Log state information.
 
   @param  This                   Indicates the calling context
-  @param  ProtocolCapability     The callee allocates memory for a TCG_BOOT_SERVICE_CAPABILITY 
-                                 structure and fills in the fields with the EFI protocol 
+  @param  ProtocolCapability     The callee allocates memory for a TCG_BOOT_SERVICE_CAPABILITY
+                                 structure and fills in the fields with the EFI protocol
                                  capability information and the current TPM state information.
-  @param  TCGFeatureFlags        This is a pointer to the feature flags. No feature 
-                                 flags are currently defined so this parameter 
-                                 MUST be set to 0. However, in the future, 
-                                 feature flags may be defined that, for example, 
+  @param  TCGFeatureFlags        This is a pointer to the feature flags. No feature
+                                 flags are currently defined so this parameter
+                                 MUST be set to 0. However, in the future,
+                                 feature flags may be defined that, for example,
                                  enable hash algorithm agility.
   @param  EventLogLocation       This is a pointer to the address of the event log in memory.
-  @param  EventLogLastEntry      If the Event Log contains more than one entry, 
-                                 this is a pointer to the address of the start of 
-                                 the last entry in the event log in memory. 
+  @param  EventLogLastEntry      If the Event Log contains more than one entry,
+                                 this is a pointer to the address of the start of
+                                 the last entry in the event log in memory.
 
   @retval EFI_SUCCESS            The operation completed successfully.
   @retval EFI_INVALID_PARAMETER  ProtocolCapability does not match TCG capability.
@@ -76,14 +70,14 @@ EFI_STATUS
 
 /**
   This service abstracts the capability to do a hash operation on a data buffer.
-  
+
   @param  This                   Indicates the calling context.
   @param  HashData               The pointer to the data buffer to be hashed.
   @param  HashDataLen            The length of the data buffer to be hashed.
   @param  AlgorithmId            Identification of the Algorithm to use for the hashing operation.
   @param  HashedDataLen          Resultant length of the hashed data.
   @param  HashedDataResult       Resultant buffer of the hashed data.
-  
+
   @retval EFI_SUCCESS            The operation completed successfully.
   @retval EFI_INVALID_PARAMETER  HashDataLen is NULL.
   @retval EFI_INVALID_PARAMETER  HashDataLenResult is NULL.
@@ -106,15 +100,15 @@ EFI_STATUS
   This service abstracts the capability to add an entry to the Event Log.
 
   @param  This                   Indicates the calling context
-  @param  TCGLogData             The pointer to the start of the data buffer containing 
-                                 the TCG_PCR_EVENT data structure. All fields in 
+  @param  TCGLogData             The pointer to the start of the data buffer containing
+                                 the TCG_PCR_EVENT data structure. All fields in
                                  this structure are properly filled by the caller.
   @param  EventNumber            The event number of the event just logged.
-  @param  Flags                  Indicates additional flags. Only one flag has been 
-                                 defined at this time, which is 0x01 and means the 
-                                 extend operation should not be performed. All 
-                                 other bits are reserved. 
- 
+  @param  Flags                  Indicates additional flags. Only one flag has been
+                                 defined at this time, which is 0x01 and means the
+                                 extend operation should not be performed. All
+                                 other bits are reserved.
+
   @retval EFI_SUCCESS            The operation completed successfully.
   @retval EFI_OUT_OF_RESOURCES   Insufficient memory in the event log to complete this action.
 **/
@@ -155,17 +149,17 @@ EFI_STATUS
   This service abstracts the capability to do a hash operation on a data buffer, extend a specific TPM PCR with the hash result, and add an entry to the Event Log
 
   @param  This                   Indicates the calling context
-  @param  HashData               The physical address of the start of the data buffer 
+  @param  HashData               The physical address of the start of the data buffer
                                  to be hashed, extended, and logged.
   @param  HashDataLen            The length, in bytes, of the buffer referenced by HashData
   @param  AlgorithmId            Identification of the Algorithm to use for the hashing operation
-  @param  TCGLogData             The physical address of the start of the data 
+  @param  TCGLogData             The physical address of the start of the data
                                  buffer containing the TCG_PCR_EVENT data structure.
   @param  EventNumber            The event number of the event just logged.
-  @param  EventLogLastEntry      The physical address of the first byte of the entry 
-                                 just placed in the Event Log. If the Event Log was 
-                                 empty when this function was called then this physical 
-                                 address will be the same as the physical address of 
+  @param  EventLogLastEntry      The physical address of the first byte of the entry
+                                 just placed in the Event Log. If the Event Log was
+                                 empty when this function was called then this physical
+                                 address will be the same as the physical address of
                                  the start of the Event Log.
 
   @retval EFI_SUCCESS            The operation completed successfully.
diff --git a/MdePkg/Include/Protocol/Tcp4.h b/MdePkg/Include/Protocol/Tcp4.h
index 49d279b013fb..d1fef270f663 100644
--- a/MdePkg/Include/Protocol/Tcp4.h
+++ b/MdePkg/Include/Protocol/Tcp4.h
@@ -4,14 +4,8 @@
   and destroy child of the driver to communicate with other host using TCP protocol.
   The EFI TCPv4 Protocol provides services to send and receive data stream.
 
-Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This Protocol is introduced in UEFI Specification 2.0.
diff --git a/MdePkg/Include/Protocol/Tcp6.h b/MdePkg/Include/Protocol/Tcp6.h
index b725391518f2..4b3e471b4479 100644
--- a/MdePkg/Include/Protocol/Tcp6.h
+++ b/MdePkg/Include/Protocol/Tcp6.h
@@ -5,13 +5,7 @@
   The EFI TCPv6 Protocol provides services to send and receive data stream.
 
   Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This Protocol is introduced in UEFI Specification 2.2
diff --git a/MdePkg/Include/Protocol/Timer.h b/MdePkg/Include/Protocol/Timer.h
index 29d65215b184..38c0ffe1d998 100644
--- a/MdePkg/Include/Protocol/Timer.h
+++ b/MdePkg/Include/Protocol/Timer.h
@@ -3,14 +3,8 @@
 
   This code is used to provide the timer tick for the DXE core.
 
-  Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -29,10 +23,10 @@
 typedef struct _EFI_TIMER_ARCH_PROTOCOL   EFI_TIMER_ARCH_PROTOCOL;
 
 /**
-  This function of this type is called when a timer interrupt fires.  This 
+  This function of this type is called when a timer interrupt fires.  This
   function executes at TPL_HIGH_LEVEL.  The DXE Core will register a function
-  of this type to be called for the timer interrupt, so it can know how much 
-  time has passed.  This information is used to signal timer based events.  
+  of this type to be called for the timer interrupt, so it can know how much
+  time has passed.  This information is used to signal timer based events.
 
   @param  Time   Time since the last timer interrupt in 100 ns units. This will
                  typically be TimerPeriod, but if a timer interrupt is missed, and the
@@ -49,16 +43,16 @@ VOID
   );
 
 /**
-  This function registers the handler NotifyFunction so it is called every time 
-  the timer interrupt fires.  It also passes the amount of time since the last 
-  handler call to the NotifyFunction.  If NotifyFunction is NULL, then the 
-  handler is unregistered.  If the handler is registered, then EFI_SUCCESS is 
-  returned.  If the CPU does not support registering a timer interrupt handler, 
-  then EFI_UNSUPPORTED is returned.  If an attempt is made to register a handler 
-  when a handler is already registered, then EFI_ALREADY_STARTED is returned.  
-  If an attempt is made to unregister a handler when a handler is not registered, 
-  then EFI_INVALID_PARAMETER is returned.  If an error occurs attempting to 
-  register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR 
+  This function registers the handler NotifyFunction so it is called every time
+  the timer interrupt fires.  It also passes the amount of time since the last
+  handler call to the NotifyFunction.  If NotifyFunction is NULL, then the
+  handler is unregistered.  If the handler is registered, then EFI_SUCCESS is
+  returned.  If the CPU does not support registering a timer interrupt handler,
+  then EFI_UNSUPPORTED is returned.  If an attempt is made to register a handler
+  when a handler is already registered, then EFI_ALREADY_STARTED is returned.
+  If an attempt is made to unregister a handler when a handler is not registered,
+  then EFI_INVALID_PARAMETER is returned.  If an error occurs attempting to
+  register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR
   is returned.
 
   @param  This             The EFI_TIMER_ARCH_PROTOCOL instance.
@@ -77,7 +71,7 @@ VOID
   @retval EFI_DEVICE_ERROR      The timer handler could not be registered.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_TIMER_REGISTER_HANDLER)(
   IN EFI_TIMER_ARCH_PROTOCOL    *This,
@@ -85,17 +79,17 @@ EFI_STATUS
 );
 
 /**
-  This function adjusts the period of timer interrupts to the value specified 
-  by TimerPeriod.  If the timer period is updated, then the selected timer 
-  period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned.  If 
-  the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.  
-  If an error occurs while attempting to update the timer period, then the 
-  timer hardware will be put back in its state prior to this call, and 
-  EFI_DEVICE_ERROR is returned.  If TimerPeriod is 0, then the timer interrupt 
-  is disabled.  This is not the same as disabling the CPU's interrupts.  
-  Instead, it must either turn off the timer hardware, or it must adjust the 
-  interrupt controller so that a CPU interrupt is not generated when the timer 
-  interrupt fires. 
+  This function adjusts the period of timer interrupts to the value specified
+  by TimerPeriod.  If the timer period is updated, then the selected timer
+  period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned.  If
+  the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.
+  If an error occurs while attempting to update the timer period, then the
+  timer hardware will be put back in its state prior to this call, and
+  EFI_DEVICE_ERROR is returned.  If TimerPeriod is 0, then the timer interrupt
+  is disabled.  This is not the same as disabling the CPU's interrupts.
+  Instead, it must either turn off the timer hardware, or it must adjust the
+  interrupt controller so that a CPU interrupt is not generated when the timer
+  interrupt fires.
 
   @param  This             The EFI_TIMER_ARCH_PROTOCOL instance.
   @param  TimerPeriod      The rate to program the timer interrupt in 100 nS units. If
@@ -110,7 +104,7 @@ EFI_STATUS
   @retval EFI_DEVICE_ERROR      The timer period could not be changed due to a device error.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_TIMER_SET_TIMER_PERIOD)(
   IN EFI_TIMER_ARCH_PROTOCOL    *This,
@@ -118,9 +112,9 @@ EFI_STATUS
   );
 
 /**
-  This function retrieves the period of timer interrupts in 100 ns units, 
-  returns that value in TimerPeriod, and returns EFI_SUCCESS.  If TimerPeriod 
-  is NULL, then EFI_INVALID_PARAMETER is returned.  If a TimerPeriod of 0 is 
+  This function retrieves the period of timer interrupts in 100 ns units,
+  returns that value in TimerPeriod, and returns EFI_SUCCESS.  If TimerPeriod
+  is NULL, then EFI_INVALID_PARAMETER is returned.  If a TimerPeriod of 0 is
   returned, then the timer is currently disabled.
 
   @param  This             The EFI_TIMER_ARCH_PROTOCOL instance.
@@ -131,7 +125,7 @@ EFI_STATUS
   @retval EFI_INVALID_PARAMETER TimerPeriod is NULL.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_TIMER_GET_TIMER_PERIOD)(
   IN EFI_TIMER_ARCH_PROTOCOL      *This,
@@ -139,12 +133,12 @@ EFI_STATUS
   );
 
 /**
-  This function generates a soft timer interrupt. If the platform does not support soft 
-  timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCESS is returned. 
-  If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.RegisterHandler() 
-  service, then a soft timer interrupt will be generated. If the timer interrupt is 
-  enabled when this service is called, then the registered handler will be invoked. The 
-  registered handler should not be able to distinguish a hardware-generated timer 
+  This function generates a soft timer interrupt. If the platform does not support soft
+  timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCESS is returned.
+  If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.RegisterHandler()
+  service, then a soft timer interrupt will be generated. If the timer interrupt is
+  enabled when this service is called, then the registered handler will be invoked. The
+  registered handler should not be able to distinguish a hardware-generated timer
   interrupt from a software-generated timer interrupt.
 
   @param  This                  The EFI_TIMER_ARCH_PROTOCOL instance.
@@ -153,7 +147,7 @@ EFI_STATUS
   @retval EFI_UNSUPPORTED       The platform does not support the generation of soft timer interrupts.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_TIMER_GENERATE_SOFT_INTERRUPT)(
   IN EFI_TIMER_ARCH_PROTOCOL    *This
@@ -161,11 +155,11 @@ EFI_STATUS
 
 
 ///
-/// This protocol provides the services to initialize a periodic timer 
+/// This protocol provides the services to initialize a periodic timer
 /// interrupt, and to register a handler that is called each time the timer
 /// interrupt fires.  It may also provide a service to adjust the rate of the
-/// periodic timer interrupt.  When a timer interrupt occurs, the handler is 
-/// passed the amount of time that has passed since the previous timer 
+/// periodic timer interrupt.  When a timer interrupt occurs, the handler is
+/// passed the amount of time that has passed since the previous timer
 /// interrupt.
 ///
 struct _EFI_TIMER_ARCH_PROTOCOL {
diff --git a/MdePkg/Include/Protocol/Timestamp.h b/MdePkg/Include/Protocol/Timestamp.h
index 9746903922e3..38f60bc8768e 100644
--- a/MdePkg/Include/Protocol/Timestamp.h
+++ b/MdePkg/Include/Protocol/Timestamp.h
@@ -1,19 +1,13 @@
 /** @file
-  EFI Timestamp Protocol as defined in UEFI2.4 Specification. 
+  EFI Timestamp Protocol as defined in UEFI2.4 Specification.
   Used to provide a platform independent interface for retrieving a high resolution timestamp counter.
-  
-  Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution. The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.    
-  
-  @par Revision Reference:          
-  This Protocol is introduced in UEFI Specification 2.4    
-       
+
+  Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  This Protocol is introduced in UEFI Specification 2.4
+
 **/
 
 #ifndef __EFI_TIME_STAMP_PROTOCOL_H__
@@ -32,30 +26,30 @@ typedef struct _EFI_TIMESTAMP_PROTOCOL  EFI_TIMESTAMP_PROTOCOL;
 /// EFI_TIMESTAMP_PROPERTIES
 ///
 typedef struct {
-  /// 
+  ///
   /// The frequency of the timestamp counter in Hz.
-  /// 
+  ///
   UINT64                               Frequency;
-  /// 
+  ///
   /// The value that the timestamp counter ends with immediately before it rolls over.
   /// For example, a 64-bit free running counter would have an EndValue of 0xFFFFFFFFFFFFFFFF.
   /// A 24-bit free running counter would have an EndValue of 0xFFFFFF.
   ///
   UINT64                               EndValue;
 } EFI_TIMESTAMP_PROPERTIES;
- 
+
 /**
   Retrieves the current value of a 64-bit free running timestamp counter.
-  
+
   The counter shall count up in proportion to the amount of time that has passed. The counter value
   will always roll over to zero. The properties of the counter can be retrieved from GetProperties().
   The caller should be prepared for the function to return the same value twice across successive calls.
   The counter value will not go backwards other than when wrapping, as defined by EndValue in GetProperties().
-  The frequency of the returned timestamp counter value must remain constant. Power management operations that 
-  affect clocking must not change the returned counter frequency. The quantization of counter value updates may 
+  The frequency of the returned timestamp counter value must remain constant. Power management operations that
+  affect clocking must not change the returned counter frequency. The quantization of counter value updates may
   vary as long as the value reflecting time passed remains consistent.
 
-  @param  None.             
+  @param  None.
 
   @retval The current value of the free running timestamp counter.
 
@@ -71,13 +65,13 @@ UINT64
 
   @param[out]  Properties              The properties of the timestamp counter.
 
-  @retval      EFI_SUCCESS             The properties were successfully retrieved. 
-  @retval      EFI_DEVICE_ERROR        An error occurred trying to retrieve the properties of the timestamp 
-                                       counter subsystem. Properties is not pedated.                                
+  @retval      EFI_SUCCESS             The properties were successfully retrieved.
+  @retval      EFI_DEVICE_ERROR        An error occurred trying to retrieve the properties of the timestamp
+                                       counter subsystem. Properties is not pedated.
   @retval      EFI_INVALID_PARAMETER   Properties is NULL.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *TIMESTAMP_GET_PROPERTIES)(
   OUT   EFI_TIMESTAMP_PROPERTIES       *Properties
@@ -87,7 +81,7 @@ EFI_STATUS
 
 ///
 /// EFI_TIMESTAMP_PROTOCOL
-/// The protocol provides a platform independent interface for retrieving a high resolution 
+/// The protocol provides a platform independent interface for retrieving a high resolution
 /// timestamp counter.
 ///
 struct _EFI_TIMESTAMP_PROTOCOL {
diff --git a/MdePkg/Include/Protocol/Tls.h b/MdePkg/Include/Protocol/Tls.h
index f3cfccc9538f..954918ea5343 100644
--- a/MdePkg/Include/Protocol/Tls.h
+++ b/MdePkg/Include/Protocol/Tls.h
@@ -7,13 +7,7 @@
   The EFI TLS Protocol provides the ability to manage TLS session.
 
   Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution. The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This Protocol is introduced in UEFI Specification 2.5
@@ -48,10 +42,6 @@ typedef struct _EFI_TLS_PROTOCOL EFI_TLS_PROTOCOL;
 ///
 typedef enum {
   ///
-  /// Session Configuration
-  ///
-
-  ///
   /// TLS session Version. The corresponding Data is of type EFI_TLS_VERSION.
   ///
   EfiTlsVersion,
@@ -92,11 +82,6 @@ typedef enum {
   /// The corresponding Data is of type EFI_TLS_SESSION_STATE.
   ///
   EfiTlsSessionState,
-
-  ///
-  /// Session information
-  ///
-
   ///
   /// TLS session data client random.
   /// The corresponding Data is of type EFI_TLS_RANDOM.
@@ -112,9 +97,15 @@ typedef enum {
   /// The corresponding Data is of type EFI_TLS_MASTER_SECRET.
   ///
   EfiTlsKeyMaterial,
+  ///
+  /// TLS session hostname for validation which is used to verify whether the name
+  /// within the peer certificate matches a given host name.
+  /// This parameter is invalid when EfiTlsVerifyMethod is EFI_TLS_VERIFY_NONE.
+  /// The corresponding Data is of type EFI_TLS_VERIFY_HOST.
+  ///
+  EfiTlsVerifyHost,
 
   EfiTlsSessionDataTypeMaximum
-
 } EFI_TLS_SESSION_DATA_TYPE;
 
 ///
@@ -141,10 +132,12 @@ typedef enum {
 ///       Hello Messages". The value of EFI_TLS_CIPHER is from TLS Cipher
 ///       Suite Registry of IANA.
 ///
+#pragma pack (1)
 typedef struct {
   UINT8                         Data1;
   UINT8                         Data2;
 } EFI_TLS_CIPHER;
+#pragma pack ()
 
 ///
 /// EFI_TLS_COMPRESSION
@@ -157,11 +150,13 @@ typedef UINT8 EFI_TLS_COMPRESSION;
 /// Note: The definition of EFI_TLS_EXTENSION if from "RFC 5246 A.4.1.
 ///       Hello Messages".
 ///
+#pragma pack (1)
 typedef struct {
   UINT16                        ExtensionType;
   UINT16                        Length;
   UINT8                         Data[1];
 } EFI_TLS_EXTENSION;
+#pragma pack ()
 
 ///
 /// EFI_TLS_VERIFY
@@ -180,7 +175,8 @@ typedef UINT32  EFI_TLS_VERIFY;
 ///
 #define EFI_TLS_VERIFY_PEER                  0x1
 ///
-/// TLS session will fail peer certificate is absent.
+/// EFI_TLS_VERIFY_FAIL_IF_NO_PEER_CERT is only meaningful in the server mode.
+/// TLS session will fail if client certificate is absent.
 ///
 #define EFI_TLS_VERIFY_FAIL_IF_NO_PEER_CERT  0x2
 ///
@@ -190,33 +186,87 @@ typedef UINT32  EFI_TLS_VERIFY;
 #define EFI_TLS_VERIFY_CLIENT_ONCE           0x4
 
 ///
+/// EFI_TLS_VERIFY_HOST_FLAG
+///
+typedef UINT32 EFI_TLS_VERIFY_HOST_FLAG;
+///
+/// There is no additional flags set for hostname validation.
+/// Wildcards are supported and they match only in the left-most label.
+///
+#define EFI_TLS_VERIFY_FLAG_NONE                    0x00
+///
+/// Always check the Subject Distinguished Name (DN) in the peer certificate even if the
+/// certificate contains Subject Alternative Name (SAN).
+///
+#define EFI_TLS_VERIFY_FLAG_ALWAYS_CHECK_SUBJECT    0x01
+///
+/// Disable the match of all wildcards.
+///
+#define EFI_TLS_VERIFY_FLAG_NO_WILDCARDS            0x02
+///
+/// Disable the "*" as wildcard in labels that have a prefix or suffix (e.g. "www*" or "*www").
+///
+#define EFI_TLS_VERIFY_FLAG_NO_PARTIAL_WILDCARDS    0x04
+///
+/// Allow the "*" to match more than one labels. Otherwise, only matches a single label.
+///
+#define EFI_TLS_VERIFY_FLAG_MULTI_LABEL_WILDCARDS   0x08
+///
+/// Restrict to only match direct child sub-domains which start with ".".
+/// For example, a name of ".example.com" would match "www.example.com" with this flag,
+/// but would not match "www.sub.example.com".
+///
+#define EFI_TLS_VERIFY_FLAG_SINGLE_LABEL_SUBDOMAINS 0x10
+///
+/// Never check the Subject Distinguished Name (DN) even there is no
+/// Subject Alternative Name (SAN) in the certificate.
+///
+#define EFI_TLS_VERIFY_FLAG_NEVER_CHECK_SUBJECT     0x20
+
+///
+/// EFI_TLS_VERIFY_HOST
+///
+#pragma pack (1)
+typedef struct {
+  EFI_TLS_VERIFY_HOST_FLAG Flags;
+  CHAR8                    *HostName;
+} EFI_TLS_VERIFY_HOST;
+#pragma pack ()
+
+///
 /// EFI_TLS_RANDOM
 /// Note: The definition of EFI_TLS_RANDOM is from "RFC 5246 A.4.1.
 ///       Hello Messages".
 ///
+#pragma pack (1)
 typedef struct {
   UINT32                        GmtUnixTime;
   UINT8                         RandomBytes[28];
 } EFI_TLS_RANDOM;
+#pragma pack ()
 
 ///
 /// EFI_TLS_MASTER_SECRET
 /// Note: The definition of EFI_TLS_MASTER_SECRET is from "RFC 5246 8.1.
 ///       Computing the Master Secret".
 ///
+#pragma pack (1)
 typedef struct {
   UINT8                         Data[48];
 } EFI_TLS_MASTER_SECRET;
+#pragma pack ()
 
 ///
 /// EFI_TLS_SESSION_ID
 /// Note: The definition of EFI_TLS_SESSION_ID is from "RFC 5246 A.4.1. Hello Messages".
 ///
 #define MAX_TLS_SESSION_ID_LENGTH  32
+#pragma pack (1)
 typedef struct {
   UINT16                        Length;
   UINT8                         Data[MAX_TLS_SESSION_ID_LENGTH];
 } EFI_TLS_SESSION_ID;
+#pragma pack ()
 
 ///
 /// EFI_TLS_SESSION_STATE
@@ -458,3 +508,4 @@ extern EFI_GUID gEfiTlsServiceBindingProtocolGuid;
 extern EFI_GUID gEfiTlsProtocolGuid;
 
 #endif  // __EFI_TLS_PROTOCOL_H__
+
diff --git a/MdePkg/Include/Protocol/TlsConfig.h b/MdePkg/Include/Protocol/TlsConfig.h
index 012f4ce75e77..367a13751cd8 100644
--- a/MdePkg/Include/Protocol/TlsConfig.h
+++ b/MdePkg/Include/Protocol/TlsConfig.h
@@ -3,13 +3,7 @@
   The EFI TLS Configuration Protocol provides a way to set and get TLS configuration.
 
   Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution. The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This Protocol is introduced in UEFI Specification 2.5
@@ -34,7 +28,7 @@ typedef struct _EFI_TLS_CONFIGURATION_PROTOCOL EFI_TLS_CONFIGURATION_PROTOCOL;
 typedef enum {
   ///
   /// Local host configuration data: public certificate data.
-  /// This data should be DER-encoded binary X.509 certificate 
+  /// This data should be DER-encoded binary X.509 certificate
   /// or PEM-encoded X.509 certificate.
   ///
   EfiTlsConfigDataTypeHostPublicCert,
@@ -43,7 +37,7 @@ typedef enum {
   ///
   EfiTlsConfigDataTypeHostPrivateKey,
   ///
-  /// CA certificate to verify peer. This data should be PEM-encoded 
+  /// CA certificate to verify peer. This data should be PEM-encoded
   /// RSA or PKCS#8 private key.
   ///
   EfiTlsConfigDataTypeCACertificate,
@@ -130,3 +124,4 @@ struct _EFI_TLS_CONFIGURATION_PROTOCOL {
 extern EFI_GUID gEfiTlsConfigurationProtocolGuid;
 
 #endif  //__EFI_TLS_CONFIGURATION_PROTOCOL_H__
+
diff --git a/MdePkg/Include/Protocol/TrEEProtocol.h b/MdePkg/Include/Protocol/TrEEProtocol.h
index d98cedcee692..db86c1cdc2ad 100644
--- a/MdePkg/Include/Protocol/TrEEProtocol.h
+++ b/MdePkg/Include/Protocol/TrEEProtocol.h
@@ -1,14 +1,8 @@
 /** @file
   This protocol is defined to abstract TPM2 hardware access in boot phase.
 
-Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials 
-are licensed and made available under the terms and conditions of the BSD License 
-which accompanies this distribution.  The full text of the license may be found at 
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -35,19 +29,19 @@ typedef UINT32 TREE_EVENT_LOG_FORMAT;
 
 typedef struct _TREE_BOOT_SERVICE_CAPABILITY {
   //
-  // Allocated size of the structure passed in 
+  // Allocated size of the structure passed in
   //
   UINT8                 Size;
   //
   // Version of the TREE_BOOT_SERVICE_CAPABILITY structure itself.
   // For this version of the protocol, the Major version shall be set to 1
-  // and the Minor version shall be set to 0. 
+  // and the Minor version shall be set to 0.
   //
   TREE_VERSION          StructureVersion;
   //
   // Version of the TrEE protocol.
   // For this version of the protocol, the Major version shall be set to 1
-  // and the Minor version shall be set to 0. 
+  // and the Minor version shall be set to 0.
   //
   TREE_VERSION          ProtocolVersion;
   //
@@ -59,20 +53,20 @@ typedef struct _TREE_BOOT_SERVICE_CAPABILITY {
   //
   TREE_EVENT_LOG_BITMAP SupportedEventLogs;
   //
-  // False = TrEE not present 
+  // False = TrEE not present
   //
   BOOLEAN               TrEEPresentFlag;
   //
-  // Max size (in bytes) of a command that can be sent to the TrEE 
+  // Max size (in bytes) of a command that can be sent to the TrEE
   //
   UINT16                MaxCommandSize;
   //
-  // Max size (in bytes) of a response that can be provided by the TrEE 
+  // Max size (in bytes) of a response that can be provided by the TrEE
   //
   UINT16                MaxResponseSize;
   //
   // 4-byte Vendor ID (see Trusted Computing Group, "TCG Vendor ID Registry,"
-  // Version 1.0, Revision 0.1, August 31, 2007, "TPM Capabilities Vendor ID" section) 
+  // Version 1.0, Revision 0.1, August 31, 2007, "TPM Capabilities Vendor ID" section)
   //
   UINT32                ManufacturerID;
 } TREE_BOOT_SERVICE_CAPABILITY_1_0;
@@ -103,7 +97,7 @@ typedef UINT32 TrEE_EVENTTYPE;
 
 typedef struct {
   //
-  // Size of the event header itself (sizeof(TrEE_EVENT_HEADER)). 
+  // Size of the event header itself (sizeof(TrEE_EVENT_HEADER)).
   //
   UINT32            HeaderSize;
   //
@@ -111,18 +105,18 @@ typedef struct {
   //
   UINT16            HeaderVersion;
   //
-  // Index of the PCR that shall be extended (0 - 23). 
+  // Index of the PCR that shall be extended (0 - 23).
   //
   TrEE_PCRINDEX     PCRIndex;
   //
-  // Type of the event that shall be extended (and optionally logged). 
+  // Type of the event that shall be extended (and optionally logged).
   //
   TrEE_EVENTTYPE    EventType;
 } TrEE_EVENT_HEADER;
 
 typedef struct {
   //
-  // Total size of the event including the Size component, the header and the Event data. 
+  // Total size of the event including the Size component, the header and the Event data.
   //
   UINT32            Size;
   TrEE_EVENT_HEADER Header;
@@ -144,11 +138,11 @@ typedef struct {
 
   @retval EFI_SUCCESS            Operation completed successfully.
   @retval EFI_DEVICE_ERROR       The command was unsuccessful.
-                                 The ProtocolCapability variable will not be populated. 
+                                 The ProtocolCapability variable will not be populated.
   @retval EFI_INVALID_PARAMETER  One or more of the parameters are incorrect.
                                  The ProtocolCapability variable will not be populated.
   @retval EFI_BUFFER_TOO_SMALL   The ProtocolCapability variable is too small to hold the full response.
-                                 It will be partially populated (required Size field will be set). 
+                                 It will be partially populated (required Size field will be set).
 **/
 typedef
 EFI_STATUS
@@ -159,7 +153,7 @@ EFI_STATUS
 
 /**
   The EFI_TREE_PROTOCOL Get Event Log function call allows a caller to
-  retrieve the address of a given event log and its last entry. 
+  retrieve the address of a given event log and its last entry.
 
   @param[in]  This               Indicates the calling context
   @param[in]  EventLogFormat     The type of the event log for which the information is requested.
@@ -187,13 +181,13 @@ EFI_STATUS
 /**
   The EFI_TREE_PROTOCOL HashLogExtendEvent function call provides callers with
   an opportunity to extend and optionally log events without requiring
-  knowledge of actual TPM commands. 
+  knowledge of actual TPM commands.
   The extend operation will occur even if this function cannot create an event
-  log entry (e.g. due to the event log being full). 
+  log entry (e.g. due to the event log being full).
 
   @param[in]  This               Indicates the calling context
   @param[in]  Flags              Bitmap providing additional information.
-  @param[in]  DataToHash         Physical address of the start of the data buffer to be hashed. 
+  @param[in]  DataToHash         Physical address of the start of the data buffer to be hashed.
   @param[in]  DataToHashLen      The length in bytes of the buffer referenced by DataToHash.
   @param[in]  Event              Pointer to data buffer containing information about the event.
 
@@ -225,7 +219,7 @@ EFI_STATUS
   @retval EFI_SUCCESS            The command byte stream was successfully sent to the device and a response was successfully received.
   @retval EFI_DEVICE_ERROR       The command was not successfully sent to the device or a response was not successfully received from the device.
   @retval EFI_INVALID_PARAMETER  One or more of the parameters are incorrect.
-  @retval EFI_BUFFER_TOO_SMALL   The output parameter block is too small. 
+  @retval EFI_BUFFER_TOO_SMALL   The output parameter block is too small.
 **/
 typedef
 EFI_STATUS
diff --git a/MdePkg/Include/Protocol/Udp4.h b/MdePkg/Include/Protocol/Udp4.h
index 9163866a0b83..7a3bc418cb31 100644
--- a/MdePkg/Include/Protocol/Udp4.h
+++ b/MdePkg/Include/Protocol/Udp4.h
@@ -1,20 +1,14 @@
 /** @file
   UDP4 Service Binding Protocol as defined in UEFI specification.
 
-  The EFI UDPv4 Protocol provides simple packet-oriented services 
-  to transmit and receive UDP packets.  
+  The EFI UDPv4 Protocol provides simple packet-oriented services
+  to transmit and receive UDP packets.
 
-Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.      
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
-  @par Revision Reference:          
-  This Protocol is introduced in UEFI Specification 2.0.       
+  @par Revision Reference:
+  This Protocol is introduced in UEFI Specification 2.0.
 
 **/
 
@@ -35,8 +29,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
     0x3ad9df29, 0x4501, 0x478d, {0xb1, 0xf8, 0x7f, 0x7f, 0xe7, 0x0e, 0x50, 0xf3 } \
   }
 
-typedef struct _EFI_UDP4_PROTOCOL EFI_UDP4_PROTOCOL; 
-  
+typedef struct _EFI_UDP4_PROTOCOL EFI_UDP4_PROTOCOL;
+
 ///
 /// EFI_UDP4_SERVICE_POINT is deprecated in the UEFI 2.4B and should not be used any more.
 /// The definition in here is only present to provide backwards compatability.
@@ -47,7 +41,7 @@ typedef struct {
   UINT16                  LocalPort;
   EFI_IPv4_ADDRESS        RemoteAddress;
   UINT16                  RemotePort;
-} EFI_UDP4_SERVICE_POINT; 
+} EFI_UDP4_SERVICE_POINT;
 
 ///
 /// EFI_UDP4_VARIABLE_DATA is deprecated in the UEFI 2.4B and should not be used any more.
@@ -101,7 +95,7 @@ typedef struct {
   EFI_UDP4_SESSION_DATA     *UdpSessionData;       //OPTIONAL
   EFI_IPv4_ADDRESS          *GatewayAddress;       //OPTIONAL
   UINT32                    DataLength;
-  UINT32                    FragmentCount; 
+  UINT32                    FragmentCount;
   EFI_UDP4_FRAGMENT_DATA    FragmentTable[1];
 } EFI_UDP4_TRANSMIT_DATA;
 
@@ -152,13 +146,13 @@ EFI_STATUS
   OUT EFI_IP4_MODE_DATA                *Ip4ModeData    OPTIONAL,
   OUT EFI_MANAGED_NETWORK_CONFIG_DATA  *MnpConfigData  OPTIONAL,
   OUT EFI_SIMPLE_NETWORK_MODE          *SnpModeData    OPTIONAL
-  );  
-  
+  );
+
 
 /**
   Initializes, changes, or resets the operational parameters for this instance of the EFI UDPv4
   Protocol.
-  
+
   The Configure() function is used to do the following:
   * Initialize and start this instance of the EFI UDPv4 Protocol.
   * Change the filtering rules and operational parameters.
@@ -190,7 +184,7 @@ EFI_STATUS
   @retval EFI_OUT_OF_RESOURCES  The EFI UDPv4 Protocol driver cannot allocate memory for this
                                 EFI UDPv4 Protocol instance.
   @retval EFI_DEVICE_ERROR      An unexpected network or system error occurred and this instance
-                                 was not opened. 
+                                 was not opened.
 
 **/
 typedef
@@ -198,11 +192,11 @@ EFI_STATUS
 (EFIAPI *EFI_UDP4_CONFIGURE)(
   IN EFI_UDP4_PROTOCOL      *This,
   IN EFI_UDP4_CONFIG_DATA   *UdpConfigData OPTIONAL
-  );  
+  );
 
 /**
   Joins and leaves multicast groups.
-  
+
   The Groups() function is used to enable and disable the multicast group
   filtering. If the JoinFlag is FALSE and the MulticastAddress is NULL, then all
   currently joined groups are left.
@@ -235,11 +229,11 @@ EFI_STATUS
   IN EFI_UDP4_PROTOCOL      *This,
   IN BOOLEAN                JoinFlag,
   IN EFI_IPv4_ADDRESS       *MulticastAddress    OPTIONAL
-  );   
+  );
 
 /**
   Adds and deletes routing table entries.
-  
+
   The Routes() function adds a route to or deletes a route from the routing table.
   Routes are determined by comparing the SubnetAddress with the destination IP
   address and arithmetically AND-ing it with the SubnetMask. The gateway address
@@ -283,11 +277,11 @@ EFI_STATUS
   IN EFI_IPv4_ADDRESS       *SubnetAddress,
   IN EFI_IPv4_ADDRESS       *SubnetMask,
   IN EFI_IPv4_ADDRESS       *GatewayAddress
-  );     
+  );
 
 /**
   Polls for incoming data packets and processes outgoing data packets.
-  
+
   The Poll() function can be used by network drivers and applications to increase
   the rate that data packets are moved between the communications device and the
   transmit and receive queues.
@@ -309,11 +303,11 @@ typedef
 EFI_STATUS
 (EFIAPI *EFI_UDP4_POLL)(
   IN EFI_UDP4_PROTOCOL      *This
-  );   
+  );
 
 /**
   Places an asynchronous receive request into the receiving queue.
-  
+
   The Receive() function places a completion token into the receive packet queue.
   This function is always asynchronous.
   The caller must fill in the Token.Event field in the completion token, and this
@@ -347,11 +341,11 @@ EFI_STATUS
 (EFIAPI *EFI_UDP4_RECEIVE)(
   IN EFI_UDP4_PROTOCOL          *This,
   IN EFI_UDP4_COMPLETION_TOKEN  *Token
-  );   
+  );
 
 /**
   Queues outgoing data packets into the transmit queue.
-  
+
   The Transmit() function places a sending request to this instance of the EFI
   UDPv4 Protocol, alongside the transmit data that was filled by the user. Whenever
   the packet in the token is sent out or some errors occur, the Token.Event will
@@ -384,11 +378,11 @@ EFI_STATUS
 (EFIAPI *EFI_UDP4_TRANSMIT)(
   IN EFI_UDP4_PROTOCOL           *This,
   IN EFI_UDP4_COMPLETION_TOKEN   *Token
-  );     
+  );
 
 /**
   Aborts an asynchronous transmit or receive request.
-  
+
   The Cancel() function is used to abort a pending transmit or receive request.
   If the token is in the transmit or receive request queues, after calling this
   function, Token.Status will be set to EFI_ABORTED and then Token.Event will be
@@ -419,13 +413,13 @@ EFI_STATUS
 (EFIAPI *EFI_UDP4_CANCEL)(
   IN EFI_UDP4_PROTOCOL          *This,
   IN EFI_UDP4_COMPLETION_TOKEN  *Token  OPTIONAL
-  );       
+  );
 
 ///
-/// The EFI_UDP4_PROTOCOL defines an EFI UDPv4 Protocol session that can be used 
-/// by any network drivers, applications, or daemons to transmit or receive UDP packets. 
-/// This protocol instance can either be bound to a specified port as a service or 
-/// connected to some remote peer as an active client. Each instance has its own settings, 
+/// The EFI_UDP4_PROTOCOL defines an EFI UDPv4 Protocol session that can be used
+/// by any network drivers, applications, or daemons to transmit or receive UDP packets.
+/// This protocol instance can either be bound to a specified port as a service or
+/// connected to some remote peer as an active client. Each instance has its own settings,
 /// such as the routing table and group table, which are independent from each other.
 ///
 struct _EFI_UDP4_PROTOCOL {
diff --git a/MdePkg/Include/Protocol/Udp6.h b/MdePkg/Include/Protocol/Udp6.h
index e1e1dc694e86..276392e14ee8 100644
--- a/MdePkg/Include/Protocol/Udp6.h
+++ b/MdePkg/Include/Protocol/Udp6.h
@@ -3,16 +3,10 @@
   the EFI IPv6 Protocol and provides simple packet-oriented services to transmit and receive
   UDP packets.
 
-  Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-                                                                                            
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 
-
-  @par Revision Reference:          
+  Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
   This Protocol is introduced in UEFI Specification 2.2
 
 **/
@@ -57,7 +51,7 @@ typedef struct {
   ///
   EFI_IPv6_ADDRESS    RemoteAddress;
   ///
-  /// The port number in host byte order on which the remote host is 
+  /// The port number in host byte order on which the remote host is
   /// listening. Maybe zero if it is not connected to any remote host.
   ///
   UINT16              RemotePort;
@@ -115,7 +109,7 @@ typedef struct {
   ///
   EFI_IPv6_ADDRESS   DestinationAddress;
   ///
-  /// Port to which this packet is sent. When sending packet, it'll be 
+  /// Port to which this packet is sent. When sending packet, it'll be
   /// ignored if it is zero.
   ///
   UINT16             DestinationPort;
@@ -168,7 +162,7 @@ typedef struct {
   ///
   /// The port number to which this EFI UDPv6 Protocol instance is bound. If a client
   /// of the EFI UDPv6 Protocol does not care about the port number, set StationPort
-  /// to zero. The EFI UDPv6 Protocol driver will assign a random port number to transmitted 
+  /// to zero. The EFI UDPv6 Protocol driver will assign a random port number to transmitted
   /// UDP packets. Ignored it if AcceptAnyPort is TRUE.
   ///
   UINT16            StationPort;
@@ -219,8 +213,8 @@ typedef struct {
 /// packets, the CompletionToken.Packet.RxData field is updated to this incoming packet and
 /// the CompletionToken.Event is signaled. The EFI UDPv6 Protocol client must signal the
 /// RecycleSignal after processing the packet.
-/// FragmentTable could contain multiple buffers that are not in the continuous memory locations. 
-/// The EFI UDPv6 Protocol client might need to combine two or more buffers in FragmentTable to 
+/// FragmentTable could contain multiple buffers that are not in the continuous memory locations.
+/// The EFI UDPv6 Protocol client might need to combine two or more buffers in FragmentTable to
 /// form their own protocol header.
 ///
 typedef struct {
@@ -271,15 +265,15 @@ typedef struct {
   ///   - EFI_SUCCESS: The receive or transmit operation completed successfully.
   ///   - EFI_ABORTED: The receive or transmit was aborted.
   ///   - EFI_TIMEOUT: The transmit timeout expired.
-  ///   - EFI_NETWORK_UNREACHABLE: The destination network is unreachable. RxData is set to 
+  ///   - EFI_NETWORK_UNREACHABLE: The destination network is unreachable. RxData is set to
   ///     NULL in this situation.
-  ///   - EFI_HOST_UNREACHABLE: The destination host is unreachable. RxData is set to NULL in 
+  ///   - EFI_HOST_UNREACHABLE: The destination host is unreachable. RxData is set to NULL in
   ///     this situation.
-  ///   - EFI_PROTOCOL_UNREACHABLE: The UDP protocol is unsupported in the remote system. 
+  ///   - EFI_PROTOCOL_UNREACHABLE: The UDP protocol is unsupported in the remote system.
   ///     RxData is set to NULL in this situation.
-  ///   - EFI_PORT_UNREACHABLE: No service is listening on the remote port. RxData is set to 
+  ///   - EFI_PORT_UNREACHABLE: No service is listening on the remote port. RxData is set to
   ///     NULL in this situation.
-  ///   - EFI_ICMP_ERROR: Some other Internet Control Message Protocol (ICMP) error report was 
+  ///   - EFI_ICMP_ERROR: Some other Internet Control Message Protocol (ICMP) error report was
   ///     received. For example, packets are being sent too fast for the destination to receive them
   ///     and the destination sent an ICMP source quench report. RxData is set to NULL in this situation.
   ///   - EFI_DEVICE_ERROR: An unexpected system or network error occurred.
@@ -304,7 +298,7 @@ typedef struct {
 
   The GetModeData() function copies the current operational settings of this EFI UDPv6 Protocol
   instance into user-supplied buffers. This function is used optionally to retrieve the operational
-  mode data of underlying networks or drivers. 
+  mode data of underlying networks or drivers.
 
   @param[in]   This             Pointer to the EFI_UDP6_PROTOCOL instance.
   @param[out]  Udp6ConfigData   The buffer in which the current UDP configuration data is returned.
@@ -330,13 +324,13 @@ EFI_STATUS
 );
 
 /**
-  Initializes, changes, or resets the operational parameters for this instance of the EFI UDPv6 
+  Initializes, changes, or resets the operational parameters for this instance of the EFI UDPv6
   Protocol.
 
   The Configure() function is used to do the following:
   - Initialize and start this instance of the EFI UDPv6 Protocol.
   - Change the filtering rules and operational parameters.
-  - Reset this instance of the EFI UDPv6 Protocol. 
+  - Reset this instance of the EFI UDPv6 Protocol.
 
   Until these parameters are initialized, no network traffic can be sent or received by this instance.
   This instance can be also reset by calling Configure() with UdpConfigData set to NULL.
@@ -350,7 +344,7 @@ EFI_STATUS
   @param[in]   UdpConfigData    Pointer to the buffer contained the configuration data.
 
   @retval EFI_SUCCESS           The configuration settings were set, changed, or reset successfully.
-  @retval EFI_NO_MAPPING        The underlying IPv6 driver was responsible for choosing a source 
+  @retval EFI_NO_MAPPING        The underlying IPv6 driver was responsible for choosing a source
                                 address for this instance, but no source address was available for use.
   @retval EFI_INVALID_PARAMETER One or more following conditions are TRUE:
                                 - This is NULL.
@@ -363,7 +357,7 @@ EFI_STATUS
                                 ReceiveTimeout, and TransmitTimeout can be reconfigured without stopping
                                 the current instance of the EFI UDPv6 Protocol.
   @retval EFI_ACCESS_DENIED     UdpConfigData.AllowDuplicatePort is FALSE and UdpConfigData.StationPort
-                                is already used by other instance. 
+                                is already used by other instance.
   @retval EFI_OUT_OF_RESOURCES  The EFI UDPv6 Protocol driver cannot allocate memory for this EFI UDPv6
                                 Protocol instance.
   @retval EFI_DEVICE_ERROR      An unexpected network or system error occurred and this instance was not
@@ -418,7 +412,7 @@ EFI_STATUS
   receive the notification and transmitting status.
 
   @param[in]   This             Pointer to the EFI_UDP6_PROTOCOL instance.
-  @param[in]   Token            Pointer to the completion token that will be placed into the 
+  @param[in]   Token            Pointer to the completion token that will be placed into the
                                 transmit queue.
 
   @retval EFI_SUCCESS           The data has been queued for transmission.
@@ -440,12 +434,12 @@ EFI_STATUS
                                   fields is NULL.
                                 - Token.Packet.TxData.UdpSessionData.DestinationAddress is not zero
                                   and is not valid unicast Ipv6 address if UdpSessionData is not NULL.
-                                - Token.Packet.TxData.UdpSessionData is NULL and this instance's 
+                                - Token.Packet.TxData.UdpSessionData is NULL and this instance's
                                   UdpConfigData.RemoteAddress is unspecified.
                                 - Token.Packet.TxData.UdpSessionData.DestinationAddress is non-zero
                                   when DestinationAddress is configured as non-zero when doing Configure()
                                   for this EFI Udp6 protocol instance.
-                                - Token.Packet.TxData.UdpSesionData.DestinationAddress is zero when 
+                                - Token.Packet.TxData.UdpSesionData.DestinationAddress is zero when
                                   DestinationAddress is unspecified when doing Configure() for this
                                   EFI Udp6 protocol instance.
   @retval EFI_ACCESS_DENIED     The transmit completion token with the same Token.Event was already
@@ -469,7 +463,7 @@ EFI_STATUS
 
   The Receive() function places a completion token into the receive packet queue. This function is
   always asynchronous.
-  The caller must fill in the Token.Event field in the completion token, and this field cannot be 
+  The caller must fill in the Token.Event field in the completion token, and this field cannot be
   NULL. When the receive operation completes, the EFI UDPv6 Protocol driver updates the Token.Status
   and Token.Packet.RxData fields and the Token.Event is signaled.
   Providing a proper notification function and context for the event will enable the user to receive
@@ -487,11 +481,11 @@ EFI_STATUS
                                 - This is NULL.
                                 - Token is NULL.
                                 - Token.Event is NULL.
-  @retval EFI_OUT_OF_RESOURCES  The receive completion token could not be queued due to a lack of system 
+  @retval EFI_OUT_OF_RESOURCES  The receive completion token could not be queued due to a lack of system
                                 resources (usually memory).
   @retval EFI_DEVICE_ERROR      An unexpected system or network error occurred. The EFI UDPv6 Protocol
                                 instance has been reset to startup defaults.
-  @retval EFI_ACCESS_DENIED     A receive completion token with the same Token.Event was already in 
+  @retval EFI_ACCESS_DENIED     A receive completion token with the same Token.Event was already in
                                 the receive queue.
   @retval EFI_NOT_READY         The receive request could not be queued because the receive queue is full.
 
@@ -547,7 +541,7 @@ EFI_STATUS
 
   @retval EFI_SUCCESS           Incoming or outgoing data was processed.
   @retval EFI_INVALID_PARAMETER This is NULL.
-  @retval EFI_DEVICE_ERROR      An unexpected system or network error occurred. 
+  @retval EFI_DEVICE_ERROR      An unexpected system or network error occurred.
   @retval EFI_TIMEOUT           Data was dropped out of the transmit and/or receive queue.
                                 Consider increasing the polling rate.
 
@@ -563,7 +557,7 @@ EFI_STATUS
 /// applications, or daemons to transmit or receive UDP packets. This protocol instance can either be
 /// bound to a specified port as a service or connected to some remote peer as an active client.
 /// Each instance has its own settings, such as group table, that are independent from each other.
-/// 
+///
 struct _EFI_UDP6_PROTOCOL {
   EFI_UDP6_GET_MODE_DATA  GetModeData;
   EFI_UDP6_CONFIGURE      Configure;
diff --git a/MdePkg/Include/Protocol/UfsDeviceConfig.h b/MdePkg/Include/Protocol/UfsDeviceConfig.h
new file mode 100644
index 000000000000..33ba120866fc
--- /dev/null
+++ b/MdePkg/Include/Protocol/UfsDeviceConfig.h
@@ -0,0 +1,137 @@
+/** @file
+  This file defines the EFI UFS Device Config Protocol.
+
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Revision Reference:
+  This Protocol is introduced in UEFI Specification 2.7
+
+**/
+
+#ifndef __UFS_DEVICE_CONFIG_PROTOCOL_H__
+#define __UFS_DEVICE_CONFIG_PROTOCOL_H__
+
+//
+// EFI UFS Device Config Protocol GUID value
+//
+#define EFI_UFS_DEVICE_CONFIG_GUID \
+  { 0xb81bfab0, 0xeb3, 0x4cf9, { 0x84, 0x65, 0x7f, 0xa9, 0x86, 0x36, 0x16, 0x64 }};
+
+//
+// Forward reference for pure ANSI compatability
+//
+typedef struct _EFI_UFS_DEVICE_CONFIG_PROTOCOL  EFI_UFS_DEVICE_CONFIG_PROTOCOL;
+
+/**
+  Read or write specified device descriptor of a UFS device.
+
+  The service is used to read/write UFS device descriptors. The consumer of this API is responsible
+  for allocating the data buffer pointed by Descriptor.
+
+  @param[in]      This          The pointer to the EFI_UFS_DEVICE_CONFIG_PROTOCOL instance.
+  @param[in]      Read          The boolean variable to show r/w direction.
+  @param[in]      DescId        The ID of device descriptor.
+  @param[in]      Index         The Index of device descriptor.
+  @param[in]      Selector      The Selector of device descriptor.
+  @param[in, out] Descriptor    The buffer of device descriptor to be read or written.
+  @param[in, out] DescSize      The size of device descriptor buffer. On input, the size, in bytes,
+                                of the data buffer specified by Descriptor. On output, the number
+                                of bytes that were actually transferred.
+
+  @retval EFI_SUCCESS           The device descriptor is read/written successfully.
+  @retval EFI_INVALID_PARAMETER This is NULL or Descriptor is NULL or DescSize is NULL.
+                                DescId, Index and Selector are invalid combination to point to a
+                                type of UFS device descriptor.
+  @retval EFI_DEVICE_ERROR      The device descriptor is not read/written successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_UFS_DEVICE_CONFIG_RW_DESCRIPTOR) (
+  IN EFI_UFS_DEVICE_CONFIG_PROTOCOL    *This,
+  IN BOOLEAN                           Read,
+  IN UINT8                             DescId,
+  IN UINT8                             Index,
+  IN UINT8                             Selector,
+  IN OUT UINT8                         *Descriptor,
+  IN OUT UINT32                        *DescSize
+  );
+
+/**
+  Read or write specified flag of a UFS device.
+
+  The service is used to read/write UFS flag descriptors. The consumer of this API is responsible
+  for allocating the buffer pointed by Flag. The buffer size is 1 byte as UFS flag descriptor is
+  just a single Boolean value that represents a TRUE or FALSE, '0' or '1', ON or OFF type of value.
+
+  @param[in]      This          The pointer to the EFI_UFS_DEVICE_CONFIG_PROTOCOL instance.
+  @param[in]      Read          The boolean variable to show r/w direction.
+  @param[in]      FlagId        The ID of flag to be read or written.
+  @param[in, out] Flag          The buffer to set or clear flag.
+
+  @retval EFI_SUCCESS           The flag descriptor is set/clear successfully.
+  @retval EFI_INVALID_PARAMETER This is NULL or Flag is NULL.
+                                FlagId is an invalid UFS flag ID.
+  @retval EFI_DEVICE_ERROR      The flag is not set/clear successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_UFS_DEVICE_CONFIG_RW_FLAG) (
+  IN EFI_UFS_DEVICE_CONFIG_PROTOCOL    *This,
+  IN BOOLEAN                           Read,
+  IN UINT8                             FlagId,
+  IN OUT UINT8                         *Flag
+  );
+
+/**
+  Read or write specified attribute of a UFS device.
+
+  The service is used to read/write UFS attributes. The consumer of this API is responsible for
+  allocating the data buffer pointed by Attribute.
+
+  @param[in]      This          The pointer to the EFI_UFS_DEVICE_CONFIG_PROTOCOL instance.
+  @param[in]      Read          The boolean variable to show r/w direction.
+  @param[in]      AttrId        The ID of Attribute.
+  @param[in]      Index         The Index of Attribute.
+  @param[in]      Selector      The Selector of Attribute.
+  @param[in, out] Attribute     The buffer of Attribute to be read or written.
+  @param[in, out] AttrSize      The size of Attribute buffer. On input, the size, in bytes, of the
+                                data buffer specified by Attribute. On output, the number of bytes
+                                that were actually transferred.
+
+  @retval EFI_SUCCESS           The attribute is read/written successfully.
+  @retval EFI_INVALID_PARAMETER This is NULL or Attribute is NULL or AttrSize is NULL.
+                                AttrId, Index and Selector are invalid combination to point to a
+                                type of UFS attribute.
+  @retval EFI_DEVICE_ERROR      The attribute is not read/written successfully.
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *EFI_UFS_DEVICE_CONFIG_RW_ATTRIBUTE) (
+  IN EFI_UFS_DEVICE_CONFIG_PROTOCOL    *This,
+  IN BOOLEAN                           Read,
+  IN UINT8                             AttrId,
+  IN UINT8                             Index,
+  IN UINT8                             Selector,
+  IN OUT UINT8                         *Attribute,
+  IN OUT UINT32                        *AttrSize
+  );
+
+///
+/// UFS Device Config Protocol structure.
+///
+struct _EFI_UFS_DEVICE_CONFIG_PROTOCOL {
+  EFI_UFS_DEVICE_CONFIG_RW_DESCRIPTOR    RwUfsDescriptor;
+  EFI_UFS_DEVICE_CONFIG_RW_FLAG          RwUfsFlag;
+  EFI_UFS_DEVICE_CONFIG_RW_ATTRIBUTE     RwUfsAttribute;
+};
+
+///
+/// UFS Device Config Protocol GUID variable.
+///
+extern EFI_GUID gEfiUfsDeviceConfigProtocolGuid;
+
+#endif
diff --git a/MdePkg/Include/Protocol/UgaDraw.h b/MdePkg/Include/Protocol/UgaDraw.h
index f501a6c17f43..1b2bd17b4c9a 100644
--- a/MdePkg/Include/Protocol/UgaDraw.h
+++ b/MdePkg/Include/Protocol/UgaDraw.h
@@ -3,14 +3,8 @@
 
   Abstraction of a very simple graphics device.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -92,26 +86,26 @@ typedef enum {
                             ///< directly to every pixel of the video display rectangle
                             ///< (DestinationX, DestinationY) (DestinationX + Width, DestinationY + Height).
                             ///< Only one pixel will be used from the BltBuffer. Delta is NOT used.
-                            
+
   EfiUgaVideoToBltBuffer,   ///< Read data from the video display rectangle
                             ///< (SourceX, SourceY) (SourceX + Width, SourceY + Height) and place it in
                             ///< the BltBuffer rectangle (DestinationX, DestinationY )
                             ///< (DestinationX + Width, DestinationY + Height). If DestinationX or
                             ///< DestinationY is not zero then Delta must be set to the length in bytes
                             ///< of a row in the BltBuffer.
-                            
+
   EfiUgaBltBufferToVideo,   ///< Write data from the  BltBuffer rectangle
                             ///< (SourceX, SourceY) (SourceX + Width, SourceY + Height) directly to the
                             ///< video display rectangle (DestinationX, DestinationY)
                             ///< (DestinationX + Width, DestinationY + Height). If SourceX or SourceY is
                             ///< not zero then Delta must be set to the length in bytes of a row in the
                             ///< BltBuffer.
-  
+
   EfiUgaVideoToVideo,       ///< Copy from the video display rectangle (SourceX, SourceY)
                             ///< (SourceX + Width, SourceY + Height) .to the video display rectangle
                             ///< (DestinationX, DestinationY) (DestinationX + Width, DestinationY + Height).
                             ///< The BltBuffer and Delta  are not used in this mode.
-                            
+
   EfiUgaBltMax              ///< Maxmimum value for enumration value of Blt operation. If a Blt operation
                             ///< larger or equal to this enumration value, it is invalid.
 } EFI_UGA_BLT_OPERATION;
@@ -152,8 +146,8 @@ EFI_STATUS
   );
 
 ///
-/// This protocol provides a basic abstraction to set video modes and 
-/// copy pixels to and from the graphics controller's frame buffer. 
+/// This protocol provides a basic abstraction to set video modes and
+/// copy pixels to and from the graphics controller's frame buffer.
 ///
 struct _EFI_UGA_DRAW_PROTOCOL {
   EFI_UGA_DRAW_PROTOCOL_GET_MODE  GetMode;
diff --git a/MdePkg/Include/Protocol/UgaIo.h b/MdePkg/Include/Protocol/UgaIo.h
index 9638a72240e5..9bfe59683118 100644
--- a/MdePkg/Include/Protocol/UgaIo.h
+++ b/MdePkg/Include/Protocol/UgaIo.h
@@ -2,15 +2,9 @@
   UGA IO protocol from the EFI 1.10 specification.
 
   Abstraction of a very simple graphics device.
-  
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -90,15 +84,15 @@ typedef struct {
 /**
   Dynamically allocate storage for a child UGA_DEVICE.
 
-  @param[in]     This            The EFI_UGA_IO_PROTOCOL instance. 
+  @param[in]     This            The EFI_UGA_IO_PROTOCOL instance.
   @param[in]     ParentDevice    ParentDevice specifies a pointer to the parent device of Device.
   @param[in]     DeviceData      A pointer to UGA_DEVICE_DATA returned from a call to DispatchService()
-                                 with a UGA_DEVICE of Parent and an IoRequest of type UgaIoGetChildDevice.      
-  @param[in]     RunTimeContext  Context to associate with Device.  
+                                 with a UGA_DEVICE of Parent and an IoRequest of type UgaIoGetChildDevice.
+  @param[in]     RunTimeContext  Context to associate with Device.
   @param[out]    Device          The Device returns a dynamically allocated child UGA_DEVICE object
                                  for ParentDevice. The caller is responsible for deleting Device.
 
-                                 
+
   @retval  EFI_SUCCESS           Device was returned.
   @retval  EFI_INVALID_PARAMETER One of the arguments was not valid.
   @retval  EFI_DEVICE_ERROR      The device had an error and could not complete the request.
@@ -118,12 +112,12 @@ EFI_STATUS
 /**
   Delete a dynamically allocated child UGA_DEVICE object that was allocated via CreateDevice().
 
-  @param[in]     This            The EFI_UGA_IO_PROTOCOL instance. Type EFI_UGA_IO_PROTOCOL is 
+  @param[in]     This            The EFI_UGA_IO_PROTOCOL instance. Type EFI_UGA_IO_PROTOCOL is
                                  defined in Section 10.7.
   @param[in]     Device          The Device points to a UGA_DEVICE object that was dynamically
                                  allocated via a CreateDevice() call.
 
-                                 
+
   @retval  EFI_SUCCESS           Device was returned.
   @retval  EFI_INVALID_PARAMETER The Device was not allocated via CreateDevice().
 
@@ -138,23 +132,23 @@ EFI_STATUS
 /**
   This is the main UGA service dispatch routine for all UGA_IO_REQUEST s.
 
-  @param pDevice pDevice specifies a pointer to a device object associated with a 
-                 device enumerated by a pIoRequest->ioRequestCode of type 
-                 UgaIoGetChildDevice. The root device for the EFI_UGA_IO_PROTOCOL 
+  @param pDevice pDevice specifies a pointer to a device object associated with a
+                 device enumerated by a pIoRequest->ioRequestCode of type
+                 UgaIoGetChildDevice. The root device for the EFI_UGA_IO_PROTOCOL
                  is represented by pDevice being set to NULL.
 
-  @param pIoRequest 
+  @param pIoRequest
                  pIoRequest points to a caller allocated buffer that contains data
                  defined by pIoRequest->ioRequestCode. See Related Definitions for
-                 a definition of UGA_IO_REQUEST_CODE s and their associated data 
+                 a definition of UGA_IO_REQUEST_CODE s and their associated data
                  structures.
 
   @return UGA_STATUS
 
 **/
-typedef UGA_STATUS 
+typedef UGA_STATUS
 (EFIAPI *PUGA_FW_SERVICE_DISPATCH)(
-  IN PUGA_DEVICE pDevice, 
+  IN PUGA_DEVICE pDevice,
   IN OUT PUGA_IO_REQUEST pIoRequest
   );
 
diff --git a/MdePkg/Include/Protocol/UnicodeCollation.h b/MdePkg/Include/Protocol/UnicodeCollation.h
index 96cff3444e4e..a18c36c55b84 100644
--- a/MdePkg/Include/Protocol/UnicodeCollation.h
+++ b/MdePkg/Include/Protocol/UnicodeCollation.h
@@ -1,16 +1,10 @@
 /** @file
   Unicode Collation protocol that follows the UEFI 2.0 specification.
-  This protocol is used to allow code running in the boot services environment 
+  This protocol is used to allow code running in the boot services environment
   to perform lexical comparison functions on Unicode strings for given languages.
 
-Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -32,12 +26,12 @@ typedef struct _EFI_UNICODE_COLLATION_PROTOCOL  EFI_UNICODE_COLLATION_PROTOCOL;
 
 ///
 /// Protocol GUID name defined in EFI1.1.
-/// 
+///
 #define UNICODE_COLLATION_PROTOCOL              EFI_UNICODE_COLLATION_PROTOCOL_GUID
 
 ///
 /// Protocol defined in EFI1.1.
-/// 
+///
 typedef EFI_UNICODE_COLLATION_PROTOCOL          UNICODE_COLLATION_INTERFACE;
 
 ///
@@ -69,7 +63,7 @@ INTN
   );
 
 /**
-  Performs a case-insensitive comparison of a Null-terminated 
+  Performs a case-insensitive comparison of a Null-terminated
   pattern string and a Null-terminated string.
 
   @param  This    A pointer to the EFI_UNICODE_COLLATION_PROTOCOL instance.
@@ -89,7 +83,7 @@ BOOLEAN
   );
 
 /**
-  Converts all the characters in a Null-terminated string to 
+  Converts all the characters in a Null-terminated string to
   lower case characters.
 
   @param  This   A pointer to the EFI_UNICODE_COLLATION_PROTOCOL instance.
@@ -119,7 +113,7 @@ VOID
   );
 
 /**
-  Converts an 8.3 FAT file name in an OEM character set to a Null-terminated 
+  Converts an 8.3 FAT file name in an OEM character set to a Null-terminated
   string.
 
   @param  This    A pointer to the EFI_UNICODE_COLLATION_PROTOCOL instance.
@@ -140,13 +134,13 @@ VOID
   );
 
 /**
-  Converts a Null-terminated string to legal characters in a FAT 
-  filename using an OEM character set. 
+  Converts a Null-terminated string to legal characters in a FAT
+  filename using an OEM character set.
 
   @param  This    A pointer to the EFI_UNICODE_COLLATION_PROTOCOL instance.
   @param  String  A pointer to a Null-terminated string.
   @param  FatSize The size of the string Fat in bytes.
-  @param  Fat     A pointer to a string that contains the converted version of 
+  @param  Fat     A pointer to a string that contains the converted version of
                   String using legal FAT characters from an OEM character set.
 
   @retval TRUE    One or more conversions failed and were substituted with '_'
@@ -163,8 +157,8 @@ BOOLEAN
   );
 
 ///
-/// The EFI_UNICODE_COLLATION_PROTOCOL is used to perform case-insensitive 
-/// comparisons of strings. 
+/// The EFI_UNICODE_COLLATION_PROTOCOL is used to perform case-insensitive
+/// comparisons of strings.
 ///
 struct _EFI_UNICODE_COLLATION_PROTOCOL {
   EFI_UNICODE_COLLATION_STRICOLL    StriColl;
@@ -177,7 +171,7 @@ struct _EFI_UNICODE_COLLATION_PROTOCOL {
   //
   EFI_UNICODE_COLLATION_FATTOSTR    FatToStr;
   EFI_UNICODE_COLLATION_STRTOFAT    StrToFat;
-  
+
   ///
   /// A Null-terminated ASCII string array that contains one or more language codes.
   /// When this field is used for UnicodeCollation2, it is specified in RFC 4646 format.
diff --git a/MdePkg/Include/Protocol/Usb2HostController.h b/MdePkg/Include/Protocol/Usb2HostController.h
index 6a0e7be80a0c..01538095c469 100644
--- a/MdePkg/Include/Protocol/Usb2HostController.h
+++ b/MdePkg/Include/Protocol/Usb2HostController.h
@@ -1,17 +1,11 @@
 /** @file
   EFI_USB2_HC_PROTOCOL as defined in UEFI 2.0.
-  The USB Host Controller Protocol is used by code, typically USB bus drivers, 
-  running in the EFI boot services environment, to perform data transactions over 
+  The USB Host Controller Protocol is used by code, typically USB bus drivers,
+  running in the EFI boot services environment, to perform data transactions over
   a USB bus. In addition, it provides an abstraction for the root hub of the USB bus.
 
-  Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -37,7 +31,7 @@ typedef struct {
 } EFI_USB_PORT_STATUS;
 
 ///
-/// EFI_USB_PORT_STATUS.PortStatus bit definition 
+/// EFI_USB_PORT_STATUS.PortStatus bit definition
 ///
 #define USB_PORT_STAT_CONNECTION    0x0001
 #define USB_PORT_STAT_ENABLE        0x0002
@@ -51,7 +45,7 @@ typedef struct {
 #define USB_PORT_STAT_OWNER         0x2000
 
 ///
-/// EFI_USB_PORT_STATUS.PortChangeStatus bit definition 
+/// EFI_USB_PORT_STATUS.PortChangeStatus bit definition
 ///
 #define USB_PORT_STAT_C_CONNECTION  0x0001
 #define USB_PORT_STAT_C_ENABLE      0x0002
@@ -62,7 +56,7 @@ typedef struct {
 
 ///
 /// Usb port features value
-/// Each value indicates its bit index in the port status and status change bitmaps, 
+/// Each value indicates its bit index in the port status and status change bitmaps,
 /// if combines these two bitmaps into a 32-bit bitmap.
 ///
 typedef enum {
@@ -158,7 +152,7 @@ typedef enum {
                                     ///< Explicitly set by software. 3)
                                     ///< Triggered by a fatal error such as
                                     ///< consistency check failure.
-                                    
+
   EfiUsbHcStateOperational,         ///< The host controller is in an
                                     ///< operational state. When in
                                     ///< this state, the host
@@ -166,7 +160,7 @@ typedef enum {
                                     ///< traffic. This state must be
                                     ///< explicitly set to enable the
                                     ///< USB bus traffic.
-                                    
+
   EfiUsbHcStateSuspend,             ///< The host controller is in the
                                     ///< suspend state. No USB
                                     ///< transactions can occur while in
@@ -176,7 +170,7 @@ typedef enum {
                                     ///< set by software. 2) Triggered
                                     ///< when there is no bus traffic for
                                     ///< 3 microseconds.
-                                    
+
   EfiUsbHcStateMaximum              ///< Maximum value for enumration value of HC status.
 } EFI_USB_HC_STATE;
 
@@ -413,30 +407,30 @@ EFI_STATUS
 /**
   Submits isochronous transfer to an isochronous endpoint of a USB device.
 
-  This function is used to submit isochronous transfer to a target endpoint of a USB device. 
-  The target endpoint is specified by DeviceAddressand EndpointAddress. Isochronous transfers are 
-  used when working with isochronous date. It provides periodic, continuous communication between 
-  the host and a device. Isochronous transfers can beused only by full-speed, high-speed, and 
+  This function is used to submit isochronous transfer to a target endpoint of a USB device.
+  The target endpoint is specified by DeviceAddressand EndpointAddress. Isochronous transfers are
+  used when working with isochronous date. It provides periodic, continuous communication between
+  the host and a device. Isochronous transfers can beused only by full-speed, high-speed, and
   super-speed devices.
 
-  High-speed isochronous transfers can be performed using multiple data buffers. The number of 
+  High-speed isochronous transfers can be performed using multiple data buffers. The number of
   buffers that are actually prepared for the transfer is specified by DataBuffersNumber. For
   full-speed isochronous transfers this value is ignored.
 
   Data represents a list of pointers to the data buffers. For full-speed isochronous transfers
   only the data pointed by Data[0]shall be used. For high-speed isochronous transfers and for
   the split transactions depending on DataLengththere several data buffers canbe used. For the
-  high-speed isochronous transfers the total number of buffers must not exceed EFI_USB_MAX_ISO_BUFFER_NUM. 
+  high-speed isochronous transfers the total number of buffers must not exceed EFI_USB_MAX_ISO_BUFFER_NUM.
 
   For split transactions performed on full-speed device by high-speed host controller the total
   number of buffers is limited to EFI_USB_MAX_ISO_BUFFER_NUM1.
-  If the isochronous transfer is successful, then EFI_SUCCESSis returned. The isochronous transfer 
+  If the isochronous transfer is successful, then EFI_SUCCESSis returned. The isochronous transfer
   is designed to be completed within one USB frame time, if it cannot be completed, EFI_TIMEOUT
   is returned. If an error other than timeout occurs during the USB transfer, then EFI_DEVICE_ERROR
   is returned and the detailed status code will be returned in TransferResult.
 
   EFI_INVALID_PARAMETERis returned if one of the following conditionsis satisfied:
-    - Data is NULL. 
+    - Data is NULL.
     - DataLength is 0.
     - DeviceSpeed is not one of the supported values listed above.
     - MaximumPacketLength is invalid. MaximumPacketLength must be 1023 or less for full-speed devices,
@@ -447,7 +441,7 @@ EFI_STATUS
   @param  DeviceAddress         Represents the address of the target device on the USB.
   @param  EndPointAddress       The combination of an endpoint number and an endpoint direction of the
                                 target USB device.
-  @param  DeviceSpeed           Indicates device speed. The supported values are EFI_USB_SPEED_FULL, 
+  @param  DeviceSpeed           Indicates device speed. The supported values are EFI_USB_SPEED_FULL,
                                 EFI_USB_SPEED_HIGH, or EFI_USB_SPEED_SUPER.
   @param  MaximumPacketLength   Indicates the maximum packet size the target endpoint is capable of
                                 sending or receiving.
@@ -497,7 +491,7 @@ EFI_STATUS
   between the host and a device. Isochronous transfers can be used only by full-speed, high-speed,
   and super-speed devices.
 
-  High-speed isochronous transfers can be performed using multiple data buffers. The number of 
+  High-speed isochronous transfers can be performed using multiple data buffers. The number of
   buffers that are actually prepared for the transfer is specified by DataBuffersNumber. For
   full-speed isochronous transfers this value is ignored.
 
@@ -510,17 +504,17 @@ EFI_STATUS
   number of buffers is limited to EFI_USB_MAX_ISO_BUFFER_NUM1.
 
   EFI_INVALID_PARAMETER is returned if one of the following conditionsis satisfied:
-    - Data is NULL. 
+    - Data is NULL.
     - DataLength is 0.
     - DeviceSpeed is not one of the supported values listed above.
-    - MaximumPacketLength is invalid. MaximumPacketLength must be 1023 or less for full-speed 
+    - MaximumPacketLength is invalid. MaximumPacketLength must be 1023 or less for full-speed
       devices and 1024 or less for high-speed and super-speed devices.
 
   @param  This                  A pointer to the EFI_USB2_HC_PROTOCOL instance.
   @param  DeviceAddress         Represents the address of the target device on the USB.
   @param  EndPointAddress       The combination of an endpoint number and an endpoint direction of the
                                 target USB device.
-  @param  DeviceSpeed           Indicates device speed. The supported values are EFI_USB_SPEED_FULL, 
+  @param  DeviceSpeed           Indicates device speed. The supported values are EFI_USB_SPEED_FULL,
                                 EFI_USB_SPEED_HIGH, or EFI_USB_SPEED_SUPER.
   @param  MaximumPacketLength   Indicates the maximum packet size the target endpoint is capable of
                                 sending or receiving.
@@ -622,11 +616,11 @@ EFI_STATUS
   );
 
 ///
-/// The EFI_USB2_HC_PROTOCOL provides USB host controller management, basic 
-/// data transactions over a USB bus, and USB root hub access. A device driver 
-/// that wishes to manage a USB bus in a system retrieves the EFI_USB2_HC_PROTOCOL 
-/// instance that is associated with the USB bus to be managed. A device handle 
-/// for a USB host controller will minimally contain an EFI_DEVICE_PATH_PROTOCOL 
+/// The EFI_USB2_HC_PROTOCOL provides USB host controller management, basic
+/// data transactions over a USB bus, and USB root hub access. A device driver
+/// that wishes to manage a USB bus in a system retrieves the EFI_USB2_HC_PROTOCOL
+/// instance that is associated with the USB bus to be managed. A device handle
+/// for a USB host controller will minimally contain an EFI_DEVICE_PATH_PROTOCOL
 /// instance, and an EFI_USB2_HC_PROTOCOL instance.
 ///
 struct _EFI_USB2_HC_PROTOCOL {
@@ -643,18 +637,18 @@ struct _EFI_USB2_HC_PROTOCOL {
   EFI_USB2_HC_PROTOCOL_GET_ROOTHUB_PORT_STATUS     GetRootHubPortStatus;
   EFI_USB2_HC_PROTOCOL_SET_ROOTHUB_PORT_FEATURE    SetRootHubPortFeature;
   EFI_USB2_HC_PROTOCOL_CLEAR_ROOTHUB_PORT_FEATURE  ClearRootHubPortFeature;
-  
+
   ///
-  /// The major revision number of the USB host controller. The revision information 
-  /// indicates the release of the Universal Serial Bus Specification with which the 
+  /// The major revision number of the USB host controller. The revision information
+  /// indicates the release of the Universal Serial Bus Specification with which the
   /// host controller is compliant.
   ///
   UINT16                                           MajorRevision;
 
   ///
-  /// The minor revision number of the USB host controller. The revision information 
-  /// indicates the release of the Universal Serial Bus Specification with which the 
-  /// host controller is compliant.  
+  /// The minor revision number of the USB host controller. The revision information
+  /// indicates the release of the Universal Serial Bus Specification with which the
+  /// host controller is compliant.
   ///
   UINT16                                           MinorRevision;
 };
diff --git a/MdePkg/Include/Protocol/UsbFunctionIo.h b/MdePkg/Include/Protocol/UsbFunctionIo.h
index 4422567f1920..3461bfa7fb73 100644
--- a/MdePkg/Include/Protocol/UsbFunctionIo.h
+++ b/MdePkg/Include/Protocol/UsbFunctionIo.h
@@ -11,14 +11,11 @@
   or interrupt transfers, alternate interfaces, or USB 3.0 functionality.
   Future revisions of this protocol may support these or additional features.
 
-  Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
+  Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  @par Revision Reference:
+  This Protocol was introduced in UEFI Specification 2.5.
 
 **/
 
@@ -273,9 +270,13 @@ EFI_STATUS
                                 as a Unicode string.
 
   @retval EFI_SUCCESS           The function returned successfully.
-  @retval EFI_INVALID_PARAMETER A parameter is invalid.
+  @retval EFI_INVALID_PARAMETER One or more of the following conditions is TRUE:
+                                BufferSize is NULL.
+                                *BufferSize is not 0 and Buffer is NULL.
+                                Id in invalid.
   @retval EFI_DEVICE_ERROR      The physical device reported an error.
-  @retval EFI_BUFFER_TOO_SMALL  Supplied buffer isn't large enough to hold the request string.
+  @retval EFI_BUFFER_TOO_SMALL  The buffer is too small to hold the buffer.
+                                *BufferSize has been updated with the size needed to hold the request string.
 
 **/
 typedef
diff --git a/MdePkg/Include/Protocol/UsbHostController.h b/MdePkg/Include/Protocol/UsbHostController.h
index 2196903a0f32..184d2de45061 100644
--- a/MdePkg/Include/Protocol/UsbHostController.h
+++ b/MdePkg/Include/Protocol/UsbHostController.h
@@ -1,18 +1,12 @@
 /** @file
   EFI_USB_HC_PROTOCOL as defined in EFI 1.10.
 
-  The USB Host Controller Protocol is used by code, typically USB bus drivers, 
-  running in the EFI boot services environment, to perform data transactions 
+  The USB Host Controller Protocol is used by code, typically USB bus drivers,
+  running in the EFI boot services environment, to perform data transactions
   over a USB bus. In addition, it provides an abstraction for the root hub of the USB bus.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -35,18 +29,18 @@ typedef struct _EFI_USB_HC_PROTOCOL EFI_USB_HC_PROTOCOL;
 // Protocol definitions
 //
 
-/**                                                                 
+/**
   Provides software reset for the USB host controller.
-    
+
   @param  This                  A pointer to the EFI_USB_HC_PROTOCOL instance.
   @param  Attributes            A bit mask of the reset operation to perform.
-                                
+
   @retval EFI_SUCCESS           The reset operation succeeded.
   @retval EFI_UNSUPPORTED       The type of reset specified by Attributes is not currently supported
-                                by the host controller hardware.                                    
+                                by the host controller hardware.
   @retval EFI_INVALID_PARAMETER Attributes is not valid.
   @retval EFI_DEVICE_ERROR      An error was encountered while attempting to perform the reset operation.
-                                   
+
 **/
 typedef
 EFI_STATUS
@@ -55,18 +49,18 @@ EFI_STATUS
   IN UINT16                  Attributes
   );
 
-/**                                                                 
+/**
   Retrieves current state of the USB host controller.
-    
+
   @param  This                  A pointer to the EFI_USB_HC_PROTOCOL instance.
   @param  State                 A pointer to the EFI_USB_HC_STATE data structure that
-                                indicates current state of the USB host controller.  
-                                
+                                indicates current state of the USB host controller.
+
   @retval EFI_SUCCESS           The state information of the host controller was returned in State.
   @retval EFI_INVALID_PARAMETER State is NULL.
   @retval EFI_DEVICE_ERROR      An error was encountered while attempting to retrieve the host controller's
-                                current state.                                                                 
-                                
+                                current state.
+
 **/
 typedef
 EFI_STATUS
@@ -75,17 +69,17 @@ EFI_STATUS
   OUT EFI_USB_HC_STATE       *State
   );
 
-/**                                                                 
+/**
   Sets the USB host controller to a specific state.
-    
+
   @param  This                  A pointer to the EFI_USB_HC_PROTOCOL instance.
-  @param  State                 Indicates the state of the host controller that will be set.                                
-                                
+  @param  State                 Indicates the state of the host controller that will be set.
+
   @retval EFI_SUCCESS           The USB host controller was successfully placed in the state specified by
-                                State.                                                                   
+                                State.
   @retval EFI_INVALID_PARAMETER State is NULL.
-  @retval EFI_DEVICE_ERROR      Failed to set the state specified by State due to device error.                                
-                                
+  @retval EFI_DEVICE_ERROR      Failed to set the state specified by State due to device error.
+
 **/
 typedef
 EFI_STATUS
@@ -94,36 +88,36 @@ EFI_STATUS
   IN EFI_USB_HC_STATE        State
   );
 
-/**                                                                 
+/**
   Submits control transfer to a target USB device.
-    
+
   @param  This                  A pointer to the EFI_USB_HC_PROTOCOL instance.
   @param  DeviceAddress         Represents the address of the target device on the USB, which is
-                                assigned during USB enumeration.                                
+                                assigned during USB enumeration.
   @param  IsSlowDevice          Indicates whether the target device is slow device or full-speed
-                                device.                                                         
-  @param  MaximumPacketLength   Indicates the maximum packet size that the default control 
-                                transfer endpoint is capable of sending or receiving.     
+                                device.
+  @param  MaximumPacketLength   Indicates the maximum packet size that the default control
+                                transfer endpoint is capable of sending or receiving.
   @param  Request               A pointer to the USB device request that will be sent to the USB
                                 device.
-  @param  TransferDirection     Specifies the data direction for the transfer. There are three 
+  @param  TransferDirection     Specifies the data direction for the transfer. There are three
                                 values available, EfiUsbDataIn, EfiUsbDataOut and EfiUsbNoData.
-  @param  Data                  A pointer to the buffer of data that will be transmitted to USB  
-                                device or received from USB device.                            
+  @param  Data                  A pointer to the buffer of data that will be transmitted to USB
+                                device or received from USB device.
   @param  DataLength            On input, indicates the size, in bytes, of the data buffer specified
-                                by Data. On output, indicates the amount of data actually           
-                                transferred.                                                        
+                                by Data. On output, indicates the amount of data actually
+                                transferred.
   @param  TimeOut               Indicates the maximum time, in milliseconds, which the transfer
-                                is allowed to complete.                                        
-  @param  TransferResult        A pointer to the detailed result information generated by this  
+                                is allowed to complete.
+  @param  TransferResult        A pointer to the detailed result information generated by this
                                 control transfer.
-                                
+
   @retval EFI_SUCCESS           The control transfer was completed successfully.
-  @retval EFI_OUT_OF_RESOURCES  The control transfer could not be completed due to a lack of resources.                                
+  @retval EFI_OUT_OF_RESOURCES  The control transfer could not be completed due to a lack of resources.
   @retval EFI_INVALID_PARAMETER Some parameters are invalid.
   @retval EFI_TIMEOUT           The control transfer failed due to timeout.
   @retval EFI_DEVICE_ERROR      The control transfer failed due to host controller or device error.
-                                
+
 **/
 typedef
 EFI_STATUS
@@ -140,36 +134,36 @@ EFI_STATUS
   OUT    UINT32                    *TransferResult
   );
 
-/**                                                                 
+/**
   Submits bulk transfer to a bulk endpoint of a USB device.
-    
+
   @param  This                  A pointer to the EFI_USB_HC_PROTOCOL instance.
   @param  DeviceAddress         Represents the address of the target device on the USB, which is
-                                assigned during USB enumeration.                                
-  @param  EndPointAddress       The combination of an endpoint number and an endpoint 
-                                direction of the target USB device. Each endpoint address 
-                                supports data transfer in one direction except the control 
-                                endpoint (whose default endpoint address is 0). It is the 
-                                caller's responsibility to make sure that the EndPointAddress 
-                                represents a bulk endpoint.                 
-  @param  MaximumPacketLength   Indicates the maximum packet size that the default control 
-                                transfer endpoint is capable of sending or receiving.     
-  @param  Data                  A pointer to the buffer of data that will be transmitted to USB  
-                                device or received from USB device.                            
+                                assigned during USB enumeration.
+  @param  EndPointAddress       The combination of an endpoint number and an endpoint
+                                direction of the target USB device. Each endpoint address
+                                supports data transfer in one direction except the control
+                                endpoint (whose default endpoint address is 0). It is the
+                                caller's responsibility to make sure that the EndPointAddress
+                                represents a bulk endpoint.
+  @param  MaximumPacketLength   Indicates the maximum packet size that the default control
+                                transfer endpoint is capable of sending or receiving.
+  @param  Data                  A pointer to the buffer of data that will be transmitted to USB
+                                device or received from USB device.
   @param  DataLength            On input, indicates the size, in bytes, of the data buffer specified
-                                by Data. On output, indicates the amount of data actually           
-                                transferred.             
-  @param  DataToggle            A pointer to the data toggle value.                                                                           
+                                by Data. On output, indicates the amount of data actually
+                                transferred.
+  @param  DataToggle            A pointer to the data toggle value.
   @param  TimeOut               Indicates the maximum time, in milliseconds, which the transfer
-                                is allowed to complete.                                        
+                                is allowed to complete.
   @param  TransferResult        A pointer to the detailed result information of the bulk transfer.
-                                
+
   @retval EFI_SUCCESS           The bulk transfer was completed successfully.
-  @retval EFI_OUT_OF_RESOURCES  The bulk transfer could not be completed due to a lack of resources.                                
+  @retval EFI_OUT_OF_RESOURCES  The bulk transfer could not be completed due to a lack of resources.
   @retval EFI_INVALID_PARAMETER Some parameters are invalid.
   @retval EFI_TIMEOUT           The bulk transfer failed due to timeout.
   @retval EFI_DEVICE_ERROR      The bulk transfer failed due to host controller or device error.
-                                
+
 **/
 typedef
 EFI_STATUS
@@ -185,47 +179,47 @@ EFI_STATUS
   OUT    UINT32                 *TransferResult
   );
 
-/**                                                                 
+/**
   Submits an asynchronous interrupt transfer to an interrupt endpoint of a USB device.
-    
+
   @param  This                  A pointer to the EFI_USB_HC_PROTOCOL instance.
   @param  DeviceAddress         Represents the address of the target device on the USB, which is
-                                assigned during USB enumeration.                                
+                                assigned during USB enumeration.
   @param  EndPointAddress       The combination of an endpoint number and an endpoint
                                 direction of the target USB device. Each endpoint address
                                 supports data transfer in one direction except the control
                                 endpoint (whose default endpoint address is zero). It is the
                                 caller's responsibility to make sure that the
-                                EndPointAddress represents an interrupt endpoint.     
+                                EndPointAddress represents an interrupt endpoint.
   @param  IsSlowDevice          Indicates whether the target device is slow device or full-speed
-                                device.                                                                          
-  @param  MaximumPacketLength   Indicates the maximum packet size that the default control 
-                                transfer endpoint is capable of sending or receiving.     
-  @param  IsNewTransfer         If TRUE, an asynchronous interrupt pipe is built between the host                       
-                                and the target interrupt endpoint. If FALSE, the specified asynchronous 
-                                interrupt pipe is canceled. If TRUE, and an interrupt transfer exists 
-                                for the target end point, then EFI_INVALID_PARAMETER is returned.      
-  @param  DataToggle            A pointer to the data toggle value. On input, it is valid when 
-                                IsNewTransfer is TRUE, and it indicates the initial data toggle 
-                                value the asynchronous interrupt transfer should adopt. On output, 
-                                it is valid when IsNewTransfer is FALSE, and it is updated to indicate 
-                                the data toggle value of the subsequent asynchronous interrupt transfer.     
+                                device.
+  @param  MaximumPacketLength   Indicates the maximum packet size that the default control
+                                transfer endpoint is capable of sending or receiving.
+  @param  IsNewTransfer         If TRUE, an asynchronous interrupt pipe is built between the host
+                                and the target interrupt endpoint. If FALSE, the specified asynchronous
+                                interrupt pipe is canceled. If TRUE, and an interrupt transfer exists
+                                for the target end point, then EFI_INVALID_PARAMETER is returned.
+  @param  DataToggle            A pointer to the data toggle value. On input, it is valid when
+                                IsNewTransfer is TRUE, and it indicates the initial data toggle
+                                value the asynchronous interrupt transfer should adopt. On output,
+                                it is valid when IsNewTransfer is FALSE, and it is updated to indicate
+                                the data toggle value of the subsequent asynchronous interrupt transfer.
   @param  PollingInterval       Indicates the interval, in milliseconds, that the asynchronous
-                                interrupt transfer is polled. 
+                                interrupt transfer is polled.
   @param  DataLength            Indicates the length of data to be received at the rate specified by
-                                PollingInterval from the target asynchronous interrupt              
-                                endpoint. This parameter is only required when IsNewTransfer is TRUE.                                                            
-  @param  CallBackFunction      The Callback function. This function is called at the rate specified by 
-                                PollingInterval. This parameter is only required when IsNewTransfer is TRUE.                               
+                                PollingInterval from the target asynchronous interrupt
+                                endpoint. This parameter is only required when IsNewTransfer is TRUE.
+  @param  CallBackFunction      The Callback function. This function is called at the rate specified by
+                                PollingInterval. This parameter is only required when IsNewTransfer is TRUE.
   @param  Context               The context that is passed to the CallBackFunction.
-                                
+
   @retval EFI_SUCCESS           The asynchronous interrupt transfer request has been successfully
-                                submitted or canceled.    
-  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.                                
+                                submitted or canceled.
+  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
   @retval EFI_INVALID_PARAMETER Some parameters are invalid.
   @retval EFI_TIMEOUT           The bulk transfer failed due to timeout.
   @retval EFI_DEVICE_ERROR      The bulk transfer failed due to host controller or device error.
-                                
+
 **/
 typedef
 EFI_STATUS
@@ -243,41 +237,41 @@ EFI_STATUS
   IN     VOID                                                *Context         OPTIONAL
   );
 
-/**                                                                 
+/**
   Submits synchronous interrupt transfer to an interrupt endpoint of a USB device.
-    
+
   @param  This                  A pointer to the EFI_USB_HC_PROTOCOL instance.
   @param  DeviceAddress         Represents the address of the target device on the USB, which is
-                                assigned during USB enumeration.                                
+                                assigned during USB enumeration.
   @param  EndPointAddress       The combination of an endpoint number and an endpoint
                                 direction of the target USB device. Each endpoint address
                                 supports data transfer in one direction except the control
                                 endpoint (whose default endpoint address is zero). It is the
                                 caller's responsibility to make sure that the
-                                EndPointAddress represents an interrupt endpoint.  
+                                EndPointAddress represents an interrupt endpoint.
   @param  IsSlowDevice          Indicates whether the target device is slow device or full-speed
-                                device.                                                                          
-  @param  MaximumPacketLength   Indicates the maximum packet size that the default control 
-                                transfer endpoint is capable of sending or receiving.       
+                                device.
+  @param  MaximumPacketLength   Indicates the maximum packet size that the default control
+                                transfer endpoint is capable of sending or receiving.
   @param  Data                  A pointer to the buffer of data that will be transmitted to USB
-                                device or received from USB device.                                                                                            asynchronous interrupt pipe is canceled.                         
+                                device or received from USB device.                                                                                            asynchronous interrupt pipe is canceled.
   @param  DataLength            On input, the size, in bytes, of the data buffer specified by Data.
-                                On output, the number of bytes transferred.                          
-  @param  DataToggle            A pointer to the data toggle value. On input, it indicates the initial 
-                                data toggle value the synchronous interrupt transfer should adopt; 
-                                on output, it is updated to indicate the data toggle value of the 
-                                subsequent synchronous interrupt transfer.                               
-  @param  TimeOut               Indicates the maximum time, in milliseconds, which the transfer    
-                                is allowed to complete.                                            
+                                On output, the number of bytes transferred.
+  @param  DataToggle            A pointer to the data toggle value. On input, it indicates the initial
+                                data toggle value the synchronous interrupt transfer should adopt;
+                                on output, it is updated to indicate the data toggle value of the
+                                subsequent synchronous interrupt transfer.
+  @param  TimeOut               Indicates the maximum time, in milliseconds, which the transfer
+                                is allowed to complete.
   @param  TransferResult        A pointer to the detailed result information from the synchronous
                                 interrupt transfer.
-                                
+
   @retval EFI_SUCCESS           The synchronous interrupt transfer was completed successfully.
-  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.                                  
+  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
   @retval EFI_INVALID_PARAMETER Some parameters are invalid.
   @retval EFI_TIMEOUT           The synchronous interrupt transfer failed due to timeout.
   @retval EFI_DEVICE_ERROR      The synchronous interrupt transfer failed due to host controller or device error.
-                                
+
 **/
 typedef
 EFI_STATUS
@@ -294,33 +288,33 @@ EFI_STATUS
   OUT    UINT32                 *TransferResult
   );
 
-/**                                                                 
+/**
   Submits isochronous transfer to an isochronous endpoint of a USB device.
-    
+
   @param  This                  A pointer to the EFI_USB_HC_PROTOCOL instance.
   @param  DeviceAddress         Represents the address of the target device on the USB, which is
-                                assigned during USB enumeration.                                
+                                assigned during USB enumeration.
   @param  EndPointAddress       The combination of an endpoint number and an endpoint
                                 direction of the target USB device. Each endpoint address
                                 supports data transfer in one direction except the control
                                 endpoint (whose default endpoint address is 0). It is the caller's
                                 responsibility to make sure that the EndPointAddress
-                                represents an isochronous endpoint.                  
-  @param  MaximumPacketLength   Indicates the maximum packet size that the default control 
-                                transfer endpoint is capable of sending or receiving.       
+                                represents an isochronous endpoint.
+  @param  MaximumPacketLength   Indicates the maximum packet size that the default control
+                                transfer endpoint is capable of sending or receiving.
   @param  Data                  A pointer to the buffer of data that will be transmitted to USB
-                                device or received from USB device.                                                                                            asynchronous interrupt pipe is canceled.                         
+                                device or received from USB device.                                                                                            asynchronous interrupt pipe is canceled.
   @param  DataLength            Specifies the length, in bytes, of the data to be sent to or received
-                                from the USB device.                                                 
+                                from the USB device.
   @param  TransferResult        A pointer to the detailed result information from the isochronous
                                 transfer.
-                                
+
   @retval EFI_SUCCESS           The isochronous transfer was completed successfully.
-  @retval EFI_OUT_OF_RESOURCES  The isochronous could not be completed due to a lack of resources.                                  
+  @retval EFI_OUT_OF_RESOURCES  The isochronous could not be completed due to a lack of resources.
   @retval EFI_INVALID_PARAMETER Some parameters are invalid.
   @retval EFI_TIMEOUT           The isochronous transfer failed due to timeout.
   @retval EFI_DEVICE_ERROR      The isochronous transfer failed due to host controller or device error.
-                                
+
 **/
 typedef
 EFI_STATUS
@@ -334,36 +328,36 @@ EFI_STATUS
   OUT    UINT32                 *TransferResult
   );
 
-/**                                                                 
+/**
   Submits nonblocking isochronous transfer to an isochronous endpoint of a USB device.
-    
+
   @param  This                  A pointer to the EFI_USB_HC_PROTOCOL instance.
   @param  DeviceAddress         Represents the address of the target device on the USB, which is
-                                assigned during USB enumeration.                                
+                                assigned during USB enumeration.
   @param  EndPointAddress       The combination of an endpoint number and an endpoint
                                 direction of the target USB device. Each endpoint address
                                 supports data transfer in one direction except the control
                                 endpoint (whose default endpoint address is zero). It is the
                                 caller's responsibility to make sure that the
-                                EndPointAddress represents an isochronous endpoint.             
-  @param  MaximumPacketLength   Indicates the maximum packet size that the default control 
-                                transfer endpoint is capable of sending or receiving. For isochronous 
-                                endpoints, this value is used to reserve the bus time in the schedule, 
+                                EndPointAddress represents an isochronous endpoint.
+  @param  MaximumPacketLength   Indicates the maximum packet size that the default control
+                                transfer endpoint is capable of sending or receiving. For isochronous
+                                endpoints, this value is used to reserve the bus time in the schedule,
                                 required for the perframe data payloads. The pipe may, on an ongoing basis,
-                                actually use less bandwidth than that reserved.      
+                                actually use less bandwidth than that reserved.
   @param  Data                  A pointer to the buffer of data that will be transmitted to USB
-                                device or received from USB device.                                                                                            asynchronous interrupt pipe is canceled.                         
+                                device or received from USB device.                                                                                            asynchronous interrupt pipe is canceled.
   @param  DataLength            Specifies the length, in bytes, of the data to be sent to or received
-                                from the USB device.                                                 
+                                from the USB device.
   @param  IsochronousCallback   The Callback function.This function is called if the requested
                                 isochronous transfer is completed.
   @param  Context               Data passed to the IsochronousCallback function. This is
                                 an optional parameter and may be NULL.
-                                
+
   @retval EFI_SUCCESS           The asynchronous isochronous transfer was completed successfully.
-  @retval EFI_OUT_OF_RESOURCES  The asynchronous isochronous could not be completed due to a lack of resources.                                  
+  @retval EFI_OUT_OF_RESOURCES  The asynchronous isochronous could not be completed due to a lack of resources.
   @retval EFI_INVALID_PARAMETER Some parameters are invalid.
-                                
+
 **/
 typedef
 EFI_STATUS
@@ -378,16 +372,16 @@ EFI_STATUS
   IN     VOID                               *Context OPTIONAL
   );
 
-/**                                                                 
+/**
   Retrieves the number of root hub ports.
-    
+
   @param  This                  A pointer to the EFI_USB_HC_PROTOCOL instance.
-  @param  PortNumber            A pointer to the number of the root hub ports.                                
-                                
+  @param  PortNumber            A pointer to the number of the root hub ports.
+
   @retval EFI_SUCCESS           The port number was retrieved successfully.
   @retval EFI_DEVICE_ERROR      An error was encountered while attempting to retrieve the port number.
   @retval EFI_INVALID_PARAMETER PortNumber is NULL.
-                                
+
 **/
 typedef
 EFI_STATUS
@@ -396,20 +390,20 @@ EFI_STATUS
   OUT UINT8                 *PortNumber
   );
 
-/**                                                                 
+/**
   Retrieves the current status of a USB root hub port.
-    
+
   @param  This                  A pointer to the EFI_USB_HC_PROTOCOL instance.
   @param  PortNumber            Specifies the root hub port from which the status is to be retrieved.
                                 This value is zero based. For example, if a root hub has two ports,
                                 then the first port is numbered 0, and the second port is
                                 numbered 1.
-  @param  PortStatus            A pointer to the current port status bits and port status change bits.                                
-                                
+  @param  PortStatus            A pointer to the current port status bits and port status change bits.
+
   @retval EFI_SUCCESS           The status of the USB root hub port specified by PortNumber
-                                was returned in PortStatus.                                
+                                was returned in PortStatus.
   @retval EFI_INVALID_PARAMETER PortNumber is invalid.
-                                
+
 **/
 typedef
 EFI_STATUS
@@ -419,9 +413,9 @@ EFI_STATUS
   OUT EFI_USB_PORT_STATUS    *PortStatus
   );
 
-/**                                                                 
+/**
   Sets a feature for the specified root hub port.
-    
+
   @param  This                  A pointer to the EFI_USB_HC_PROTOCOL instance.
   @param  PortNumber            Specifies the root hub port from which the status is to be retrieved.
                                 This value is zero based. For example, if a root hub has two ports,
@@ -429,11 +423,11 @@ EFI_STATUS
                                 numbered 1.
   @param  PortFeature           Indicates the feature selector associated with the feature set
                                 request.
-                                
+
   @retval EFI_SUCCESS           The feature specified by PortFeature was set for the USB
-                                root hub port specified by PortNumber.                  
+                                root hub port specified by PortNumber.
   @retval EFI_INVALID_PARAMETER PortNumber is invalid or PortFeature is invalid for this function.
-                                
+
 **/
 typedef
 EFI_STATUS
@@ -443,9 +437,9 @@ EFI_STATUS
   IN EFI_USB_PORT_FEATURE    PortFeature
   );
 
-/**                                                                 
+/**
   Clears a feature for the specified root hub port.
-    
+
   @param  This                  A pointer to the EFI_USB_HC_PROTOCOL instance.
   @param  PortNumber            Specifies the root hub port from which the status is to be retrieved.
                                 This value is zero based. For example, if a root hub has two ports,
@@ -453,11 +447,11 @@ EFI_STATUS
                                 numbered 1.
   @param  PortFeature           Indicates the feature selector associated with the feature clear
                                 request.
-                                
+
   @retval EFI_SUCCESS           The feature specified by PortFeature was cleared for the USB
-                                root hub port specified by PortNumber.                  
+                                root hub port specified by PortNumber.
   @retval EFI_INVALID_PARAMETER PortNumber is invalid or PortFeature is invalid for this function.
-                                
+
 **/
 typedef
 EFI_STATUS
@@ -473,7 +467,7 @@ EFI_STATUS
 /// over a USB bus, and USB root hub access. A device driver that wishes to manage a USB bus in a
 /// system retrieves the EFI_USB_HC_PROTOCOL instance that is associated with the USB bus to be
 /// managed. A device handle for a USB host controller will minimally contain an
-/// EFI_DEVICE_PATH_PROTOCOL instance, and an EFI_USB_HC_PROTOCOL instance. 
+/// EFI_DEVICE_PATH_PROTOCOL instance, and an EFI_USB_HC_PROTOCOL instance.
 ///
 struct _EFI_USB_HC_PROTOCOL {
   EFI_USB_HC_PROTOCOL_RESET                       Reset;
@@ -490,16 +484,16 @@ struct _EFI_USB_HC_PROTOCOL {
   EFI_USB_HC_PROTOCOL_SET_ROOTHUB_PORT_FEATURE    SetRootHubPortFeature;
   EFI_USB_HC_PROTOCOL_CLEAR_ROOTHUB_PORT_FEATURE  ClearRootHubPortFeature;
   ///
-  /// The major revision number of the USB host controller. The revision information 
-  /// indicates the release of the Universal Serial Bus Specification with which the 
+  /// The major revision number of the USB host controller. The revision information
+  /// indicates the release of the Universal Serial Bus Specification with which the
   /// host controller is compliant.
-  ///  
+  ///
   UINT16                                          MajorRevision;
   ///
-  /// The minor revision number of the USB host controller. The revision information 
-  /// indicates the release of the Universal Serial Bus Specification with which the 
-  /// host controller is compliant.  
-  ///  
+  /// The minor revision number of the USB host controller. The revision information
+  /// indicates the release of the Universal Serial Bus Specification with which the
+  /// host controller is compliant.
+  ///
   UINT16                                          MinorRevision;
 };
 
diff --git a/MdePkg/Include/Protocol/UsbIo.h b/MdePkg/Include/Protocol/UsbIo.h
index cc7263b6aa67..dec246521122 100644
--- a/MdePkg/Include/Protocol/UsbIo.h
+++ b/MdePkg/Include/Protocol/UsbIo.h
@@ -1,18 +1,12 @@
 /** @file
   EFI Usb I/O Protocol as defined in UEFI specification.
-  This protocol is used by code, typically drivers, running in the EFI 
-  boot services environment to access USB devices like USB keyboards, 
-  mice and mass storage devices. In particular, functions for managing devices 
+  This protocol is used by code, typically drivers, running in the EFI
+  boot services environment to access USB devices like USB keyboards,
+  mice and mass storage devices. In particular, functions for managing devices
   on USB buses are defined here.
-  
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -134,13 +128,13 @@ EFI_STATUS
   typically used to transfer large amounts of data to/from USB devices.
 
   @param  This                  A pointer to the EFI_USB_IO_PROTOCOL instance.
-  @param  DeviceEndpoint        The destination USB device endpoint to which the 
-                                device request is being sent. DeviceEndpoint must 
-                                be between 0x01 and 0x0F or between 0x81 and 0x8F, 
-                                otherwise EFI_INVALID_PARAMETER is returned. If 
-                                the endpoint is not a BULK endpoint, EFI_INVALID_PARAMETER 
-                                is returned. The MSB of this parameter indicates 
-                                the endpoint direction. The number "1" stands for 
+  @param  DeviceEndpoint        The destination USB device endpoint to which the
+                                device request is being sent. DeviceEndpoint must
+                                be between 0x01 and 0x0F or between 0x81 and 0x8F,
+                                otherwise EFI_INVALID_PARAMETER is returned. If
+                                the endpoint is not a BULK endpoint, EFI_INVALID_PARAMETER
+                                is returned. The MSB of this parameter indicates
+                                the endpoint direction. The number "1" stands for
                                 an IN endpoint, and "0" stands for an OUT endpoint.
   @param  Data                  A pointer to the buffer of data that will be transmitted to USB
                                 device or received from USB device.
@@ -148,8 +142,8 @@ EFI_STATUS
                                 On input, the size, in bytes, of the data buffer specified by Data.
                                 On output, the number of bytes that were actually transferred.
   @param  Timeout               Indicating the transfer should be completed within this time frame.
-                                The units are in milliseconds. If Timeout is 0, then the 
-                                caller must wait for the function to be completed until 
+                                The units are in milliseconds. If Timeout is 0, then the
+                                caller must wait for the function to be completed until
                                 EFI_SUCCESS or EFI_DEVICE_ERROR is returned.
   @param  Status                This parameter indicates the USB transfer status.
 
@@ -178,27 +172,27 @@ EFI_STATUS
   a fixed rate.
 
   @param  This                  A pointer to the EFI_USB_IO_PROTOCOL instance.
-  @param  DeviceEndpoint        The destination USB device endpoint to which the 
-                                device request is being sent. DeviceEndpoint must 
-                                be between 0x01 and 0x0F or between 0x81 and 0x8F, 
-                                otherwise EFI_INVALID_PARAMETER is returned. If 
-                                the endpoint is not a BULK endpoint, EFI_INVALID_PARAMETER 
-                                is returned. The MSB of this parameter indicates 
-                                the endpoint direction. The number "1" stands for 
+  @param  DeviceEndpoint        The destination USB device endpoint to which the
+                                device request is being sent. DeviceEndpoint must
+                                be between 0x01 and 0x0F or between 0x81 and 0x8F,
+                                otherwise EFI_INVALID_PARAMETER is returned. If
+                                the endpoint is not a BULK endpoint, EFI_INVALID_PARAMETER
+                                is returned. The MSB of this parameter indicates
+                                the endpoint direction. The number "1" stands for
                                 an IN endpoint, and "0" stands for an OUT endpoint.
   @param  IsNewTransfer         If TRUE, a new transfer will be submitted to USB controller. If
                                 FALSE, the interrupt transfer is deleted from the device's interrupt
                                 transfer queue.
   @param  PollingInterval       Indicates the periodic rate, in milliseconds, that the transfer is to be
-                                executed.This parameter is required when IsNewTransfer is TRUE. The 
-                                value must be between 1 to 255, otherwise EFI_INVALID_PARAMETER is returned. 
+                                executed.This parameter is required when IsNewTransfer is TRUE. The
+                                value must be between 1 to 255, otherwise EFI_INVALID_PARAMETER is returned.
                                 The units are in milliseconds.
   @param  DataLength            Specifies the length, in bytes, of the data to be received from the
                                 USB device. This parameter is only required when IsNewTransfer is TRUE.
   @param  InterruptCallback     The Callback function. This function is called if the asynchronous
-                                interrupt transfer is completed. This parameter is required 
+                                interrupt transfer is completed. This parameter is required
                                 when IsNewTransfer is TRUE.
-  @param  Context               Data passed to the InterruptCallback function. This is an optional 
+  @param  Context               Data passed to the InterruptCallback function. This is an optional
                                 parameter and may be NULL.
 
   @retval EFI_SUCCESS           The asynchronous USB transfer request transfer has been successfully executed.
@@ -221,21 +215,21 @@ EFI_STATUS
   This function is used to manage a USB device with an interrupt transfer pipe.
 
   @param  This                  A pointer to the EFI_USB_IO_PROTOCOL instance.
-  @param  DeviceEndpoint        The destination USB device endpoint to which the 
-                                device request is being sent. DeviceEndpoint must 
-                                be between 0x01 and 0x0F or between 0x81 and 0x8F, 
-                                otherwise EFI_INVALID_PARAMETER is returned. If 
-                                the endpoint is not a BULK endpoint, EFI_INVALID_PARAMETER 
-                                is returned. The MSB of this parameter indicates 
-                                the endpoint direction. The number "1" stands for 
+  @param  DeviceEndpoint        The destination USB device endpoint to which the
+                                device request is being sent. DeviceEndpoint must
+                                be between 0x01 and 0x0F or between 0x81 and 0x8F,
+                                otherwise EFI_INVALID_PARAMETER is returned. If
+                                the endpoint is not a BULK endpoint, EFI_INVALID_PARAMETER
+                                is returned. The MSB of this parameter indicates
+                                the endpoint direction. The number "1" stands for
                                 an IN endpoint, and "0" stands for an OUT endpoint.
   @param  Data                  A pointer to the buffer of data that will be transmitted to USB
                                 device or received from USB device.
   @param  DataLength            On input, then size, in bytes, of the buffer Data. On output, the
                                 amount of data actually transferred.
-  @param  Timeout               The time out, in seconds, for this transfer. If Timeout is 0, 
-                                then the caller must wait for the function to be completed 
-                                until EFI_SUCCESS or EFI_DEVICE_ERROR is returned. If the 
+  @param  Timeout               The time out, in seconds, for this transfer. If Timeout is 0,
+                                then the caller must wait for the function to be completed
+                                until EFI_SUCCESS or EFI_DEVICE_ERROR is returned. If the
                                 transfer is not completed in this time frame, then EFI_TIMEOUT is returned.
   @param  Status                This parameter indicates the USB transfer status.
 
@@ -261,13 +255,13 @@ EFI_STATUS
   transfer is typically used to transfer streaming data.
 
   @param  This                  A pointer to the EFI_USB_IO_PROTOCOL instance.
-  @param  DeviceEndpoint        The destination USB device endpoint to which the 
-                                device request is being sent. DeviceEndpoint must 
-                                be between 0x01 and 0x0F or between 0x81 and 0x8F, 
-                                otherwise EFI_INVALID_PARAMETER is returned. If 
-                                the endpoint is not a BULK endpoint, EFI_INVALID_PARAMETER 
-                                is returned. The MSB of this parameter indicates 
-                                the endpoint direction. The number "1" stands for 
+  @param  DeviceEndpoint        The destination USB device endpoint to which the
+                                device request is being sent. DeviceEndpoint must
+                                be between 0x01 and 0x0F or between 0x81 and 0x8F,
+                                otherwise EFI_INVALID_PARAMETER is returned. If
+                                the endpoint is not a BULK endpoint, EFI_INVALID_PARAMETER
+                                is returned. The MSB of this parameter indicates
+                                the endpoint direction. The number "1" stands for
                                 an IN endpoint, and "0" stands for an OUT endpoint.
   @param  Data                  A pointer to the buffer of data that will be transmitted to USB
                                 device or received from USB device.
@@ -296,19 +290,19 @@ EFI_STATUS
   transfer is typically used to transfer streaming data.
 
   @param  This                  A pointer to the EFI_USB_IO_PROTOCOL instance.
-  @param  DeviceEndpoint        The destination USB device endpoint to which the 
-                                device request is being sent. DeviceEndpoint must 
-                                be between 0x01 and 0x0F or between 0x81 and 0x8F, 
-                                otherwise EFI_INVALID_PARAMETER is returned. If 
-                                the endpoint is not a BULK endpoint, EFI_INVALID_PARAMETER 
-                                is returned. The MSB of this parameter indicates 
-                                the endpoint direction. The number "1" stands for 
+  @param  DeviceEndpoint        The destination USB device endpoint to which the
+                                device request is being sent. DeviceEndpoint must
+                                be between 0x01 and 0x0F or between 0x81 and 0x8F,
+                                otherwise EFI_INVALID_PARAMETER is returned. If
+                                the endpoint is not a BULK endpoint, EFI_INVALID_PARAMETER
+                                is returned. The MSB of this parameter indicates
+                                the endpoint direction. The number "1" stands for
                                 an IN endpoint, and "0" stands for an OUT endpoint.
   @param  Data                  A pointer to the buffer of data that will be transmitted to USB
                                 device or received from USB device.
   @param  DataLength            The size, in bytes, of the data buffer specified by Data.
                                 This is an optional parameter and may be NULL.
-  @param  IsochronousCallback   The IsochronousCallback() function.This function is 
+  @param  IsochronousCallback   The IsochronousCallback() function.This function is
                                 called if the requested isochronous transfer is completed.
   @param  Context               Data passed to the IsochronousCallback() function.
 
@@ -432,9 +426,9 @@ EFI_STATUS
   @param  LangID                  The Language ID for the string being retrieved.
   @param  StringID                The ID of the string being retrieved.
   @param  String                  A pointer to a buffer allocated by this function with
-                                  AllocatePool() to store the string.If this function 
-                                  returns EFI_SUCCESS, it stores the string the caller 
-                                  wants to get. The caller should release the string 
+                                  AllocatePool() to store the string.If this function
+                                  returns EFI_SUCCESS, it stores the string the caller
+                                  wants to get. The caller should release the string
                                   buffer with FreePool() after the string is not used any more.
 
   @retval EFI_SUCCESS             The string was retrieved successfully.
@@ -456,9 +450,9 @@ EFI_STATUS
 
   @param  This                    A pointer to the EFI_USB_IO_PROTOCOL instance.
   @param  LangIDTable             Language ID for the string the caller wants to get.
-                                  This is a 16-bit ID defined by Microsoft. This 
-                                  buffer pointer is allocated and maintained by 
-                                  the USB Bus Driver, the caller should not modify 
+                                  This is a 16-bit ID defined by Microsoft. This
+                                  buffer pointer is allocated and maintained by
+                                  the USB Bus Driver, the caller should not modify
                                   its contents.
   @param  TableSize               The size, in bytes, of the table LangIDTable.
 
@@ -474,11 +468,11 @@ EFI_STATUS
   );
 
 ///
-/// The EFI_USB_IO_PROTOCOL provides four basic transfers types described 
-/// in the USB 1.1 Specification. These include control transfer, interrupt 
-/// transfer, bulk transfer and isochronous transfer. The EFI_USB_IO_PROTOCOL 
-/// also provides some basic USB device/controller management and configuration 
-/// interfaces. A USB device driver uses the services of this protocol to manage USB devices.  
+/// The EFI_USB_IO_PROTOCOL provides four basic transfers types described
+/// in the USB 1.1 Specification. These include control transfer, interrupt
+/// transfer, bulk transfer and isochronous transfer. The EFI_USB_IO_PROTOCOL
+/// also provides some basic USB device/controller management and configuration
+/// interfaces. A USB device driver uses the services of this protocol to manage USB devices.
 ///
 struct _EFI_USB_IO_PROTOCOL {
   //
diff --git a/MdePkg/Include/Protocol/UserCredential.h b/MdePkg/Include/Protocol/UserCredential.h
index 6dea64358732..d572f97b774b 100644
--- a/MdePkg/Include/Protocol/UserCredential.h
+++ b/MdePkg/Include/Protocol/UserCredential.h
@@ -4,14 +4,8 @@
 
   Attached to a device handle, this protocol identifies a single means of identifying the user.
 
-  Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -31,16 +25,16 @@ typedef struct _EFI_USER_CREDENTIAL_PROTOCOL  EFI_USER_CREDENTIAL_PROTOCOL;
   Enroll a user on a credential provider.
 
   This function enrolls and deletes a user profile using this credential provider. If a user profile
-  is successfully enrolled, it calls the User Manager Protocol function Notify() to notify the user 
-  manager driver that credential information has changed. If an enrolled user does exist, delete the 
+  is successfully enrolled, it calls the User Manager Protocol function Notify() to notify the user
+  manager driver that credential information has changed. If an enrolled user does exist, delete the
   user on the credential provider.
 
   @param[in] This                Points to this instance of the EFI_USER_CREDENTIAL_PROTOCOL.
   @param[in] User                The user profile to enroll.
- 
+
   @retval EFI_SUCCESS            User profile was successfully enrolled.
-  @retval EFI_ACCESS_DENIED      Current user profile does not permit enrollment on the user profile 
-                                 handle. Either the user profile cannot enroll on any user profile or 
+  @retval EFI_ACCESS_DENIED      Current user profile does not permit enrollment on the user profile
+                                 handle. Either the user profile cannot enroll on any user profile or
                                  cannot enroll on a user profile other than the current user profile.
   @retval EFI_UNSUPPORTED        This credential provider does not support enrollment in the pre-OS.
   @retval EFI_DEVICE_ERROR       The new credential could not be created because of a device error.
@@ -56,19 +50,19 @@ EFI_STATUS
 /**
   Returns the user interface information used during user identification.
 
-  This function returns information about the form used when interacting with the user during user 
-  identification. The form is the first enabled form in the form-set class 
-  EFI_HII_USER_CREDENTIAL_FORMSET_GUID installed on the HII handle HiiHandle. If 
-  the user credential provider does not require a form to identify the user, then this function should 
+  This function returns information about the form used when interacting with the user during user
+  identification. The form is the first enabled form in the form-set class
+  EFI_HII_USER_CREDENTIAL_FORMSET_GUID installed on the HII handle HiiHandle. If
+  the user credential provider does not require a form to identify the user, then this function should
   return EFI_NOT_FOUND.
 
   @param[in]  This               Points to this instance of the EFI_USER_CREDENTIAL_PROTOCOL.
   @param[out] Hii                On return, holds the HII database handle.
   @param[out] FormSetId          On return, holds the identifier of the form set which contains
                                  the form used during user identification.
-  @param[out] FormId             On return, holds the identifier of the form used during user 
+  @param[out] FormId             On return, holds the identifier of the form used during user
                                  identification.
- 
+
   @retval EFI_SUCCESS            Form returned successfully.
   @retval EFI_NOT_FOUND          Form not returned.
   @retval EFI_INVALID_PARAMETER  Hii is NULL or FormSetId is NULL or FormId is NULL.
@@ -85,19 +79,19 @@ EFI_STATUS
 /**
   Returns bitmap used to describe the credential provider type.
 
-  This optional function returns a bitmap which is less than or equal to the number of pixels specified 
-  by Width and Height. If no such bitmap exists, then EFI_NOT_FOUND is returned. 
+  This optional function returns a bitmap which is less than or equal to the number of pixels specified
+  by Width and Height. If no such bitmap exists, then EFI_NOT_FOUND is returned.
 
   @param[in]      This           Points to this instance of the EFI_USER_CREDENTIAL_PROTOCOL.
   @param[in, out] Width          On entry, points to the desired bitmap width. If NULL then no bitmap
-                                 information will be returned. On exit, points to the width of the  
+                                 information will be returned. On exit, points to the width of the
                                  bitmap returned.
-  @param[in, out] Height         On entry, points to the desired bitmap height. If NULL then no bitmap 
-                                 information will be returned. On exit, points to the height of the  
+  @param[in, out] Height         On entry, points to the desired bitmap height. If NULL then no bitmap
+                                 information will be returned. On exit, points to the height of the
                                  bitmap returned
-  @param[out]     Hii            On return, holds the HII database handle. 
-  @param[out]     Image          On return, holds the HII image identifier. 
- 
+  @param[out]     Hii            On return, holds the HII database handle.
+  @param[out]     Image          On return, holds the HII image identifier.
+
   @retval EFI_SUCCESS            Image identifier returned successfully.
   @retval EFI_NOT_FOUND          Image identifier not returned.
   @retval EFI_INVALID_PARAMETER  Hii is NULL or Image is NULL.
@@ -115,13 +109,13 @@ EFI_STATUS
 /**
   Returns string used to describe the credential provider type.
 
-  This function returns a string which describes the credential provider. If no such string exists, then 
-  EFI_NOT_FOUND is returned. 
+  This function returns a string which describes the credential provider. If no such string exists, then
+  EFI_NOT_FOUND is returned.
 
   @param[in]  This               Points to this instance of the EFI_USER_CREDENTIAL_PROTOCOL.
   @param[out] Hii                On return, holds the HII database handle.
   @param[out] String             On return, holds the HII string identifier.
- 
+
   @retval EFI_SUCCESS            String identifier returned successfully.
   @retval EFI_NOT_FOUND          String identifier not returned.
   @retval EFI_INVALID_PARAMETER  Hii is NULL or String is NULL.
@@ -137,21 +131,21 @@ EFI_STATUS
 /**
   Return the user identifier associated with the currently authenticated user.
 
-  This function returns the user identifier of the user authenticated by this credential provider. This 
-  function is called after the credential-related information has been submitted on a form OR after a 
+  This function returns the user identifier of the user authenticated by this credential provider. This
+  function is called after the credential-related information has been submitted on a form OR after a
   call to Default() has returned that this credential is ready to log on.
 
   @param[in]  This               Points to this instance of the EFI_USER_CREDENTIAL_PROTOCOL.
-  @param[in]  User               The user profile handle of the user profile currently being considered 
-                                 by the user identity manager. If NULL, then no user profile is currently 
+  @param[in]  User               The user profile handle of the user profile currently being considered
+                                 by the user identity manager. If NULL, then no user profile is currently
                                  under consideration.
-  @param[out] Identifier         On return, points to the user identifier. 
- 
+  @param[out] Identifier         On return, points to the user identifier.
+
   @retval EFI_SUCCESS            User identifier returned successfully.
   @retval EFI_NOT_READY          No user identifier can be returned.
   @retval EFI_ACCESS_DENIED      The user has been locked out of this user credential.
-  @retval EFI_NOT_FOUND          User is not NULL, and the specified user handle can't be found in user 
-                                 profile database 
+  @retval EFI_NOT_FOUND          User is not NULL, and the specified user handle can't be found in user
+                                 profile database
   @retval EFI_INVALID_PARAMETER  Identifier is NULL.
 **/
 typedef
@@ -165,13 +159,13 @@ EFI_STATUS
 /**
   Indicate that user interface interaction has begun for the specified credential.
 
-  This function is called when a credential provider is selected by the user. If AutoLogon returns 
-  FALSE, then the user interface will be constructed by the User Identity Manager. 
+  This function is called when a credential provider is selected by the user. If AutoLogon returns
+  FALSE, then the user interface will be constructed by the User Identity Manager.
 
   @param[in]  This               Points to this instance of the EFI_USER_CREDENTIAL_PROTOCOL.
-  @param[out] AutoLogon          On return, points to the credential provider's capabilities after 
-                                 the credential provider has been selected by the user. 
- 
+  @param[out] AutoLogon          On return, points to the credential provider's capabilities after
+                                 the credential provider has been selected by the user.
+
   @retval EFI_SUCCESS            Credential provider successfully selected.
   @retval EFI_INVALID_PARAMETER  AutoLogon is NULL.
 **/
@@ -180,7 +174,7 @@ EFI_STATUS
 (EFIAPI *EFI_CREDENTIAL_SELECT)(
   IN CONST EFI_USER_CREDENTIAL_PROTOCOL  *This,
   OUT      EFI_CREDENTIAL_LOGON_FLAGS    *AutoLogon
-  ); 
+  );
 
 /**
   Indicate that user interface interaction has ended for the specified credential.
@@ -188,7 +182,7 @@ EFI_STATUS
   This function is called when a credential provider is deselected by the user.
 
   @param[in] This        Points to this instance of the EFI_USER_CREDENTIAL_PROTOCOL.
- 
+
   @retval EFI_SUCCESS    Credential provider successfully deselected.
 **/
 typedef
@@ -200,16 +194,16 @@ EFI_STATUS
 /**
   Return the default logon behavior for this user credential.
 
-  This function reports the default login behavior regarding this credential provider.  
+  This function reports the default login behavior regarding this credential provider.
 
   @param[in]  This               Points to this instance of the EFI_USER_CREDENTIAL_PROTOCOL.
-  @param[out] AutoLogon          On return, holds whether the credential provider should be 
-                                 used by default to automatically log on the user.  
- 
+  @param[out] AutoLogon          On return, holds whether the credential provider should be
+                                 used by default to automatically log on the user.
+
   @retval EFI_SUCCESS            Default information successfully returned.
   @retval EFI_INVALID_PARAMETER  AutoLogon is NULL.
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_CREDENTIAL_DEFAULT)(
   IN  CONST EFI_USER_CREDENTIAL_PROTOCOL        *This,
@@ -219,22 +213,22 @@ EFI_STATUS
 /**
   Return information attached to the credential provider.
 
-  This function returns user information. 
+  This function returns user information.
 
   @param[in]     This           Points to this instance of the EFI_USER_CREDENTIAL_PROTOCOL.
-  @param[in]     UserInfo       Handle of the user information data record. 
-  @param[out]    Info           On entry, points to a buffer of at least *InfoSize bytes. On exit, holds the user 
-                                information. If the buffer is too small to hold the information, then 
-                                EFI_BUFFER_TOO_SMALL is returned and InfoSize is updated to contain the 
+  @param[in]     UserInfo       Handle of the user information data record.
+  @param[out]    Info           On entry, points to a buffer of at least *InfoSize bytes. On exit, holds the user
+                                information. If the buffer is too small to hold the information, then
+                                EFI_BUFFER_TOO_SMALL is returned and InfoSize is updated to contain the
                                 number of bytes actually required.
-  @param[in,out] InfoSize       On entry, points to the size of Info. On return, points to the size of the user 
-                                information. 
- 
+  @param[in,out] InfoSize       On entry, points to the size of Info. On return, points to the size of the user
+                                information.
+
   @retval EFI_SUCCESS           Information returned successfully.
-  @retval EFI_BUFFER_TOO_SMALL  The size specified by InfoSize is too small to hold all of the user 
+  @retval EFI_BUFFER_TOO_SMALL  The size specified by InfoSize is too small to hold all of the user
                                 information. The size required is returned in *InfoSize.
   @retval EFI_NOT_FOUND         The specified UserInfo does not refer to a valid user info handle.
-  @retval EFI_INVALID_PARAMETER Info is NULL or InfoSize is NULL.                                
+  @retval EFI_INVALID_PARAMETER Info is NULL or InfoSize is NULL.
 **/
 typedef
 EFI_STATUS
@@ -248,15 +242,15 @@ EFI_STATUS
 /**
   Enumerate all of the user information records on the credential provider.
 
-  This function returns the next user information record. To retrieve the first user information record 
-  handle, point UserInfo at a NULL. Each subsequent call will retrieve another user information 
-  record handle until there are no more, at which point UserInfo will point to NULL. 
+  This function returns the next user information record. To retrieve the first user information record
+  handle, point UserInfo at a NULL. Each subsequent call will retrieve another user information
+  record handle until there are no more, at which point UserInfo will point to NULL.
 
   @param[in]     This            Points to this instance of the EFI_USER_CREDENTIAL_PROTOCOL.
-  @param[in,out] UserInfo        On entry, points to the previous user information handle or NULL to  
-                                 start enumeration. On exit, points to the next user information handle 
+  @param[in,out] UserInfo        On entry, points to the previous user information handle or NULL to
+                                 start enumeration. On exit, points to the next user information handle
                                  or NULL if there is no more user information.
- 
+
   @retval EFI_SUCCESS            User information returned.
   @retval EFI_NOT_FOUND          No more user information found.
   @retval EFI_INVALID_PARAMETER  UserInfo is NULL.
@@ -279,7 +273,7 @@ struct _EFI_USER_CREDENTIAL_PROTOCOL {
   EFI_CREDENTIAL_TILE           Tile;
   EFI_CREDENTIAL_TITLE          Title;
   EFI_CREDENTIAL_USER           User;
-  EFI_CREDENTIAL_SELECT         Select;   
+  EFI_CREDENTIAL_SELECT         Select;
   EFI_CREDENTIAL_DESELECT       Deselect;
   EFI_CREDENTIAL_DEFAULT        Default;
   EFI_CREDENTIAL_GET_INFO       GetInfo;
diff --git a/MdePkg/Include/Protocol/UserCredential2.h b/MdePkg/Include/Protocol/UserCredential2.h
index ed3423b47f6f..e5adb66276f9 100644
--- a/MdePkg/Include/Protocol/UserCredential2.h
+++ b/MdePkg/Include/Protocol/UserCredential2.h
@@ -3,14 +3,8 @@
 
   Attached to a device handle, this protocol identifies a single means of identifying the user.
 
-  Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -29,16 +23,16 @@ typedef struct _EFI_USER_CREDENTIAL2_PROTOCOL  EFI_USER_CREDENTIAL2_PROTOCOL;
 /**
   Enroll a user on a credential provider.
 
-  This function enrolls a user on this credential provider. If the user exists on this credential 
-  provider, update the user information on this credential provider; otherwise add the user information 
+  This function enrolls a user on this credential provider. If the user exists on this credential
+  provider, update the user information on this credential provider; otherwise add the user information
   on credential provider.
 
   @param[in] This                Points to this instance of the EFI_USER_CREDENTIAL2_PROTOCOL.
   @param[in] User                The user profile to enroll.
- 
+
   @retval EFI_SUCCESS            User profile was successfully enrolled.
-  @retval EFI_ACCESS_DENIED      Current user profile does not permit enrollment on the user profile 
-                                 handle. Either the user profile cannot enroll on any user profile or 
+  @retval EFI_ACCESS_DENIED      Current user profile does not permit enrollment on the user profile
+                                 handle. Either the user profile cannot enroll on any user profile or
                                  cannot enroll on a user profile other than the current user profile.
   @retval EFI_UNSUPPORTED        This credential provider does not support enrollment in the pre-OS.
   @retval EFI_DEVICE_ERROR       The new credential could not be created because of a device error.
@@ -54,19 +48,19 @@ EFI_STATUS
 /**
   Returns the user interface information used during user identification.
 
-  This function returns information about the form used when interacting with the user during user 
-  identification. The form is the first enabled form in the form-set class 
-  EFI_HII_USER_CREDENTIAL_FORMSET_GUID installed on the HII handle HiiHandle. If 
-  the user credential provider does not require a form to identify the user, then this function should 
+  This function returns information about the form used when interacting with the user during user
+  identification. The form is the first enabled form in the form-set class
+  EFI_HII_USER_CREDENTIAL_FORMSET_GUID installed on the HII handle HiiHandle. If
+  the user credential provider does not require a form to identify the user, then this function should
   return EFI_NOT_FOUND.
 
   @param[in]  This               Points to this instance of the EFI_USER_CREDENTIAL2_PROTOCOL.
   @param[out] Hii                On return, holds the HII database handle.
   @param[out] FormSetId          On return, holds the identifier of the form set which contains
                                  the form used during user identification.
-  @param[out] FormId             On return, holds the identifier of the form used during user 
+  @param[out] FormId             On return, holds the identifier of the form used during user
                                  identification.
- 
+
   @retval EFI_SUCCESS            Form returned successfully.
   @retval EFI_NOT_FOUND          Form not returned.
   @retval EFI_INVALID_PARAMETER  Hii is NULL or FormSetId is NULL or FormId is NULL.
@@ -83,19 +77,19 @@ EFI_STATUS
 /**
   Returns bitmap used to describe the credential provider type.
 
-  This optional function returns a bitmap which is less than or equal to the number of pixels specified 
-  by Width and Height. If no such bitmap exists, then EFI_NOT_FOUND is returned. 
+  This optional function returns a bitmap which is less than or equal to the number of pixels specified
+  by Width and Height. If no such bitmap exists, then EFI_NOT_FOUND is returned.
 
   @param[in]      This           Points to this instance of the EFI_USER_CREDENTIAL2_PROTOCOL.
   @param[in, out] Width          On entry, points to the desired bitmap width. If NULL then no bitmap
-                                 information will be returned. On exit, points to the width of the  
+                                 information will be returned. On exit, points to the width of the
                                  bitmap returned.
-  @param[in, out] Height         On entry, points to the desired bitmap height. If NULL then no bitmap 
-                                 information will be returned. On exit, points to the height of the  
+  @param[in, out] Height         On entry, points to the desired bitmap height. If NULL then no bitmap
+                                 information will be returned. On exit, points to the height of the
                                  bitmap returned
-  @param[out]     Hii            On return, holds the HII database handle. 
-  @param[out]     Image          On return, holds the HII image identifier. 
- 
+  @param[out]     Hii            On return, holds the HII database handle.
+  @param[out]     Image          On return, holds the HII image identifier.
+
   @retval EFI_SUCCESS            Image identifier returned successfully.
   @retval EFI_NOT_FOUND          Image identifier not returned.
   @retval EFI_INVALID_PARAMETER  Hii is NULL or Image is NULL.
@@ -113,13 +107,13 @@ EFI_STATUS
 /**
   Returns string used to describe the credential provider type.
 
-  This function returns a string which describes the credential provider. If no such string exists, then 
-  EFI_NOT_FOUND is returned. 
+  This function returns a string which describes the credential provider. If no such string exists, then
+  EFI_NOT_FOUND is returned.
 
   @param[in]  This               Points to this instance of the EFI_USER_CREDENTIAL2_PROTOCOL.
   @param[out] Hii                On return, holds the HII database handle.
   @param[out] String             On return, holds the HII string identifier.
- 
+
   @retval EFI_SUCCESS            String identifier returned successfully.
   @retval EFI_NOT_FOUND          String identifier not returned.
   @retval EFI_INVALID_PARAMETER  Hii is NULL or String is NULL.
@@ -135,21 +129,21 @@ EFI_STATUS
 /**
   Return the user identifier associated with the currently authenticated user.
 
-  This function returns the user identifier of the user authenticated by this credential provider. This 
-  function is called after the credential-related information has been submitted on a form OR after a 
+  This function returns the user identifier of the user authenticated by this credential provider. This
+  function is called after the credential-related information has been submitted on a form OR after a
   call to Default() has returned that this credential is ready to log on.
 
   @param[in]  This               Points to this instance of the EFI_USER_CREDENTIAL2_PROTOCOL.
-  @param[in]  User               The user profile handle of the user profile currently being considered 
-                                 by the user identity manager. If NULL, then no user profile is currently 
+  @param[in]  User               The user profile handle of the user profile currently being considered
+                                 by the user identity manager. If NULL, then no user profile is currently
                                  under consideration.
-  @param[out] Identifier         On return, points to the user identifier. 
- 
+  @param[out] Identifier         On return, points to the user identifier.
+
   @retval EFI_SUCCESS            User identifier returned successfully.
   @retval EFI_NOT_READY          No user identifier can be returned.
   @retval EFI_ACCESS_DENIED      The user has been locked out of this user credential.
-  @retval EFI_NOT_FOUND          User is not NULL, and the specified user handle can't be found in user 
-                                 profile database 
+  @retval EFI_NOT_FOUND          User is not NULL, and the specified user handle can't be found in user
+                                 profile database
   @retval EFI_INVALID_PARAMETER  Identifier is NULL.
 **/
 typedef
@@ -163,13 +157,13 @@ EFI_STATUS
 /**
   Indicate that user interface interaction has begun for the specified credential.
 
-  This function is called when a credential provider is selected by the user. If AutoLogon returns 
-  FALSE, then the user interface will be constructed by the User Identity Manager. 
+  This function is called when a credential provider is selected by the user. If AutoLogon returns
+  FALSE, then the user interface will be constructed by the User Identity Manager.
 
   @param[in]  This               Points to this instance of the EFI_USER_CREDENTIAL2_PROTOCOL.
-  @param[out] AutoLogon          On return, points to the credential provider's capabilities after 
-                                 the credential provider has been selected by the user. 
- 
+  @param[out] AutoLogon          On return, points to the credential provider's capabilities after
+                                 the credential provider has been selected by the user.
+
   @retval EFI_SUCCESS            Credential provider successfully selected.
   @retval EFI_INVALID_PARAMETER  AutoLogon is NULL.
 **/
@@ -178,7 +172,7 @@ EFI_STATUS
 (EFIAPI *EFI_CREDENTIAL2_SELECT)(
   IN CONST EFI_USER_CREDENTIAL2_PROTOCOL *This,
   OUT      EFI_CREDENTIAL_LOGON_FLAGS    *AutoLogon
-  ); 
+  );
 
 /**
   Indicate that user interface interaction has ended for the specified credential.
@@ -186,7 +180,7 @@ EFI_STATUS
   This function is called when a credential provider is deselected by the user.
 
   @param[in] This        Points to this instance of the EFI_USER_CREDENTIAL2_PROTOCOL.
- 
+
   @retval EFI_SUCCESS    Credential provider successfully deselected.
 **/
 typedef
@@ -198,16 +192,16 @@ EFI_STATUS
 /**
   Return the default logon behavior for this user credential.
 
-  This function reports the default login behavior regarding this credential provider.  
+  This function reports the default login behavior regarding this credential provider.
 
   @param[in]  This               Points to this instance of the EFI_USER_CREDENTIAL2_PROTOCOL.
-  @param[out] AutoLogon          On return, holds whether the credential provider should be 
-                                 used by default to automatically log on the user.  
- 
+  @param[out] AutoLogon          On return, holds whether the credential provider should be
+                                 used by default to automatically log on the user.
+
   @retval EFI_SUCCESS            Default information successfully returned.
   @retval EFI_INVALID_PARAMETER  AutoLogon is NULL.
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_CREDENTIAL2_DEFAULT)(
   IN  CONST EFI_USER_CREDENTIAL2_PROTOCOL       *This,
@@ -217,22 +211,22 @@ EFI_STATUS
 /**
   Return information attached to the credential provider.
 
-  This function returns user information. 
+  This function returns user information.
 
   @param[in]     This           Points to this instance of the EFI_USER_CREDENTIAL2_PROTOCOL.
-  @param[in]     UserInfo       Handle of the user information data record. 
-  @param[out]    Info           On entry, points to a buffer of at least *InfoSize bytes. On exit, holds the user 
-                                information. If the buffer is too small to hold the information, then 
-                                EFI_BUFFER_TOO_SMALL is returned and InfoSize is updated to contain the 
+  @param[in]     UserInfo       Handle of the user information data record.
+  @param[out]    Info           On entry, points to a buffer of at least *InfoSize bytes. On exit, holds the user
+                                information. If the buffer is too small to hold the information, then
+                                EFI_BUFFER_TOO_SMALL is returned and InfoSize is updated to contain the
                                 number of bytes actually required.
-  @param[in,out] InfoSize       On entry, points to the size of Info. On return, points to the size of the user 
-                                information. 
- 
+  @param[in,out] InfoSize       On entry, points to the size of Info. On return, points to the size of the user
+                                information.
+
   @retval EFI_SUCCESS           Information returned successfully.
-  @retval EFI_BUFFER_TOO_SMALL  The size specified by InfoSize is too small to hold all of the user 
+  @retval EFI_BUFFER_TOO_SMALL  The size specified by InfoSize is too small to hold all of the user
                                 information. The size required is returned in *InfoSize.
   @retval EFI_NOT_FOUND         The specified UserInfo does not refer to a valid user info handle.
-  @retval EFI_INVALID_PARAMETER Info is NULL or InfoSize is NULL.                                
+  @retval EFI_INVALID_PARAMETER Info is NULL or InfoSize is NULL.
 **/
 typedef
 EFI_STATUS
@@ -246,15 +240,15 @@ EFI_STATUS
 /**
   Enumerate all of the user information records on the credential provider.
 
-  This function returns the next user information record. To retrieve the first user information record 
-  handle, point UserInfo at a NULL. Each subsequent call will retrieve another user information 
-  record handle until there are no more, at which point UserInfo will point to NULL. 
+  This function returns the next user information record. To retrieve the first user information record
+  handle, point UserInfo at a NULL. Each subsequent call will retrieve another user information
+  record handle until there are no more, at which point UserInfo will point to NULL.
 
   @param[in]     This            Points to this instance of the EFI_USER_CREDENTIAL2_PROTOCOL.
-  @param[in,out] UserInfo        On entry, points to the previous user information handle or NULL to  
-                                 start enumeration. On exit, points to the next user information handle 
+  @param[in,out] UserInfo        On entry, points to the previous user information handle or NULL to
+                                 start enumeration. On exit, points to the next user information handle
                                  or NULL if there is no more user information.
- 
+
   @retval EFI_SUCCESS            User information returned.
   @retval EFI_NOT_FOUND          No more user information found.
   @retval EFI_INVALID_PARAMETER  UserInfo is NULL.
@@ -269,21 +263,21 @@ EFI_STATUS
 /**
   Delete a user on this credential provider.
 
-  This function deletes a user on this credential provider. 
+  This function deletes a user on this credential provider.
 
   @param[in]     This            Points to this instance of the EFI_USER_CREDENTIAL2_PROTOCOL.
   @param[in]     User            The user profile handle to delete.
 
   @retval EFI_SUCCESS            User profile was successfully deleted.
-  @retval EFI_ACCESS_DENIED      Current user profile does not permit deletion on the user profile handle. 
-                                 Either the user profile cannot delete on any user profile or cannot delete 
-                                 on a user profile other than the current user profile. 
+  @retval EFI_ACCESS_DENIED      Current user profile does not permit deletion on the user profile handle.
+                                 Either the user profile cannot delete on any user profile or cannot delete
+                                 on a user profile other than the current user profile.
   @retval EFI_UNSUPPORTED        This credential provider does not support deletion in the pre-OS.
   @retval EFI_DEVICE_ERROR       The new credential could not be deleted because of a device error.
   @retval EFI_INVALID_PARAMETER  User does not refer to a valid user profile handle.
 **/
-typedef 
-EFI_STATUS 
+typedef
+EFI_STATUS
 (EFIAPI *EFI_CREDENTIAL2_DELETE)(
  IN CONST EFI_USER_CREDENTIAL2_PROTOCOL  *This,
  IN       EFI_USER_PROFILE_HANDLE        User
@@ -300,13 +294,13 @@ struct _EFI_USER_CREDENTIAL2_PROTOCOL {
   EFI_CREDENTIAL2_TILE          Tile;
   EFI_CREDENTIAL2_TITLE         Title;
   EFI_CREDENTIAL2_USER          User;
-  EFI_CREDENTIAL2_SELECT        Select;   
+  EFI_CREDENTIAL2_SELECT        Select;
   EFI_CREDENTIAL2_DESELECT      Deselect;
   EFI_CREDENTIAL2_DEFAULT       Default;
   EFI_CREDENTIAL2_GET_INFO      GetInfo;
   EFI_CREDENTIAL2_GET_NEXT_INFO GetNextInfo;
   EFI_CREDENTIAL_CAPABILITIES   Capabilities;
-  EFI_CREDENTIAL2_DELETE        Delete; 
+  EFI_CREDENTIAL2_DELETE        Delete;
 };
 
 extern EFI_GUID gEfiUserCredential2ProtocolGuid;
diff --git a/MdePkg/Include/Protocol/UserManager.h b/MdePkg/Include/Protocol/UserManager.h
index 73fa672a5915..0496af76955d 100644
--- a/MdePkg/Include/Protocol/UserManager.h
+++ b/MdePkg/Include/Protocol/UserManager.h
@@ -3,14 +3,8 @@
 
   This protocol manages user profiles.
 
-  Copyright (c) 2009 - 2011, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -53,7 +47,7 @@ typedef UINT16 EFI_USER_INFO_ATTRIBS;
 ///
 typedef struct {
   ///
-  /// The user credential identifier associated with this user information or else Nil if the 
+  /// The user credential identifier associated with this user information or else Nil if the
   /// information is not associated with any specific credential.
   ///
   EFI_GUID               Credential;
@@ -95,7 +89,7 @@ typedef UINT64   EFI_CREDENTIAL_CAPABILITIES;
 #define EFI_CREDENTIAL_CAPABILITIES_ENROLL  0x0000000000000001
 
 ///
-/// Credential logon flags 
+/// Credential logon flags
 ///
 typedef UINT32 EFI_CREDENTIAL_LOGON_FLAGS;
 #define EFI_CREDENTIAL_LOGON_FLAG_AUTO                0x00000001
@@ -159,7 +153,7 @@ typedef CHAR16 *EFI_USER_INFO_CREDENTIAL_PROVIDER_NAME;
 ///
 #define EFI_USER_INFO_PKCS11_RECORD                   0x0A
 ///
-/// Provides standard biometric information in the format specified by the ISO 19785 (Common 
+/// Provides standard biometric information in the format specified by the ISO 19785 (Common
 /// Biometric Exchange Formats Framework) specification.
 ///
 #define EFI_USER_INFO_CBEFF_RECORD                    0x0B
@@ -170,7 +164,7 @@ typedef VOID *EFI_USER_INFO_CBEFF;
 #define EFI_USER_INFO_FAR_RECORD                      0x0C
 typedef UINT8 EFI_USER_INFO_FAR;
 ///
-/// Indicates how many attempts the user has to with a particular credential before the system prevents 
+/// Indicates how many attempts the user has to with a particular credential before the system prevents
 /// further attempts.
 ///
 #define EFI_USER_INFO_RETRY_RECORD                    0x0D
@@ -192,12 +186,12 @@ typedef EFI_USER_INFO_ACCESS_CONTROL EFI_USER_INFO_ACCESS_POLICY;
 ///
 
 ///
-/// Forbids the user from booting or loading executables from the specified device path or any child 
+/// Forbids the user from booting or loading executables from the specified device path or any child
 /// device paths.
 ///
 #define EFI_USER_INFO_ACCESS_FORBID_LOAD              0x00000001
 ///
-/// Permits the user from booting or loading executables from the specified device path or any child 
+/// Permits the user from booting or loading executables from the specified device path or any child
 /// device paths.
 /// Note: in-consistency between code and the UEFI 2.3 specification here.
 /// The definition EFI_USER_INFO_ACCESS_PERMIT_BOOT in the specification should be typo and wait for
@@ -258,7 +252,7 @@ typedef UINT32 EFI_USER_INFO_ACCESS_BOOT_ORDER_HDR;
 ///
 #define EFI_USER_INFO_ACCESS_BOOT_ORDER_REPLACE       0x00000002
 ///
-/// The Boot Manager will not attempt find a default boot device 
+/// The Boot Manager will not attempt find a default boot device
 /// when the default boot order is does not lead to a bootable device.
 ///
 #define EFI_USER_INFO_ACCESS_BOOT_ORDER_NODEFAULT     0x00000010
@@ -269,7 +263,7 @@ typedef UINT32 EFI_USER_INFO_ACCESS_BOOT_ORDER_HDR;
 #define EFI_USER_INFO_IDENTITY_POLICY_RECORD          0x0F
 
 typedef struct {
-  UINT32  Type;    ///< Specifies either an operator or a data item. 
+  UINT32  Type;    ///< Specifies either an operator or a data item.
   UINT32  Length;  ///< The length of this block, in bytes, including this header.
 } EFI_USER_INFO_IDENTITY_POLICY;
 
@@ -303,13 +297,13 @@ typedef struct _EFI_USER_MANAGER_PROTOCOL  EFI_USER_MANAGER_PROTOCOL;
 /**
   Create a new user profile.
 
-  This function creates a new user profile with only a new user identifier attached and returns its 
+  This function creates a new user profile with only a new user identifier attached and returns its
   handle. The user profile is non-volatile, but the handle User can change across reboots.
 
   @param[in]  This               Points to this instance of the EFI_USER_MANAGER_PROTOCOL.
-  @param[out] User               On return, points to the new user profile handle. 
+  @param[out] User               On return, points to the new user profile handle.
                                  The user profile handle is unique only during this boot.
- 
+
   @retval EFI_SUCCESS            User profile was successfully created.
   @retval EFI_ACCESS_DENIED      Current user does not have sufficient permissions to create a user profile.
   @retval EFI_UNSUPPORTED        Creation of new user profiles is not supported.
@@ -326,7 +320,7 @@ EFI_STATUS
   Delete an existing user profile.
 
   @param[in] This                Points to this instance of the EFI_USER_MANAGER_PROTOCOL.
-  @param[in] User                User profile handle. 
+  @param[in] User                User profile handle.
 
   @retval EFI_SUCCESS            User profile was successfully deleted.
   @retval EFI_ACCESS_DENIED      Current user does not have sufficient permissions to delete a user
@@ -344,16 +338,16 @@ EFI_STATUS
 /**
   Enumerate all of the enrolled users on the platform.
 
-  This function returns the next enrolled user profile. To retrieve the first user profile handle, point 
-  User at a NULL. Each subsequent call will retrieve another user profile handle until there are no 
-  more, at which point User will point to NULL. 
+  This function returns the next enrolled user profile. To retrieve the first user profile handle, point
+  User at a NULL. Each subsequent call will retrieve another user profile handle until there are no
+  more, at which point User will point to NULL.
 
   @param[in]     This            Points to this instance of the EFI_USER_MANAGER_PROTOCOL.
-  @param[in,out] User            On entry, points to the previous user profile handle or NULL to 
+  @param[in,out] User            On entry, points to the previous user profile handle or NULL to
                                  start enumeration. On exit, points to the next user profile handle
                                  or NULL if there are no more user profiles.
 
-  @retval EFI_SUCCESS            Next enrolled user profile successfully returned. 
+  @retval EFI_SUCCESS            Next enrolled user profile successfully returned.
   @retval EFI_ACCESS_DENIED      Next enrolled user profile was not successfully returned.
   @retval EFI_INVALID_PARAMETER  The User parameter is NULL.
 **/
@@ -370,7 +364,7 @@ EFI_STATUS
   @param[in]  This               Points to this instance of the EFI_USER_MANAGER_PROTOCOL.
   @param[out] CurrentUser        On return, points to the current user profile handle.
 
-  @retval EFI_SUCCESS            Current user profile handle returned successfully. 
+  @retval EFI_SUCCESS            Current user profile handle returned successfully.
   @retval EFI_INVALID_PARAMETER  The CurrentUser parameter is NULL.
 **/
 typedef
@@ -384,9 +378,9 @@ EFI_STATUS
   Identify a user.
 
   Identify the user and, if authenticated, returns the user handle and changes the current user profile.
-  All user information marked as private in a previously selected profile is no longer available for 
-  inspection. 
-  Whenever the current user profile is changed then the an event with the GUID 
+  All user information marked as private in a previously selected profile is no longer available for
+  inspection.
+  Whenever the current user profile is changed then the an event with the GUID
   EFI_EVENT_GROUP_USER_PROFILE_CHANGED is signaled.
 
   @param[in]  This               Points to this instance of the EFI_USER_MANAGER_PROTOCOL.
@@ -406,26 +400,26 @@ EFI_STATUS
 /**
   Find a user using a user information record.
 
-  This function searches all user profiles for the specified user information record. The search starts 
-  with the user information record handle following UserInfo and continues until either the 
+  This function searches all user profiles for the specified user information record. The search starts
+  with the user information record handle following UserInfo and continues until either the
   information is found or there are no more user profiles.
-  A match occurs when the Info.InfoType field matches the user information record type and the 
+  A match occurs when the Info.InfoType field matches the user information record type and the
   user information record data matches the portion of Info.
 
   @param[in]     This      Points to this instance of the EFI_USER_MANAGER_PROTOCOL.
-  @param[in,out] User      On entry, points to the previously returned user profile handle or NULL to start 
-                           searching with the first user profile. On return, points to the user profile handle or 
+  @param[in,out] User      On entry, points to the previously returned user profile handle or NULL to start
+                           searching with the first user profile. On return, points to the user profile handle or
                            NULL if not found.
-  @param[in,out] UserInfo  On entry, points to the previously returned user information handle or NULL to start 
-                           searching with the first. On return, points to the user information handle of the user 
-                           information record or NULL if not found. Can be NULL, in which case only one user 
-                           information record per user can be returned. 
-  @param[in]     Info      Points to the buffer containing the user information to be compared to the user 
-                           information record. If the user information record data is empty, then only the user 
-                           information record type is compared. 
+  @param[in,out] UserInfo  On entry, points to the previously returned user information handle or NULL to start
+                           searching with the first. On return, points to the user information handle of the user
+                           information record or NULL if not found. Can be NULL, in which case only one user
+                           information record per user can be returned.
+  @param[in]     Info      Points to the buffer containing the user information to be compared to the user
+                           information record. If the user information record data is empty, then only the user
+                           information record type is compared.
                            If InfoSize is 0, then the user information record must be empty.
 
-  @param[in]     InfoSize  The size of Info, in bytes. 
+  @param[in]     InfoSize  The size of Info, in bytes.
 
   @retval EFI_SUCCESS           User information was found. User points to the user profile handle and UserInfo
                                 points to the user information handle.
@@ -445,15 +439,15 @@ EFI_STATUS
 /**
   Called by credential provider to notify of information change.
 
-  This function allows the credential provider to notify the User Identity Manager when user status  
+  This function allows the credential provider to notify the User Identity Manager when user status
   has changed.
-  If the User Identity Manager doesn't support asynchronous changes in credentials, then this function 
-  should return EFI_UNSUPPORTED. 
-  If current user does not exist, and the credential provider can identify a user, then make the user 
+  If the User Identity Manager doesn't support asynchronous changes in credentials, then this function
+  should return EFI_UNSUPPORTED.
+  If current user does not exist, and the credential provider can identify a user, then make the user
   to be current user and signal the EFI_EVENT_GROUP_USER_PROFILE_CHANGED event.
-  If current user already exists, and the credential provider can identify another user, then switch 
+  If current user already exists, and the credential provider can identify another user, then switch
   current user to the newly identified user, and signal the EFI_EVENT_GROUP_USER_PROFILE_CHANGED event.
-  If current user was identified by this credential provider and now the credential provider cannot identify 
+  If current user was identified by this credential provider and now the credential provider cannot identify
   current user, then logout current user and signal the EFI_EVENT_GROUP_USER_PROFILE_CHANGED event.
 
   @param[in] This          Points to this instance of the EFI_USER_MANAGER_PROTOCOL.
@@ -474,30 +468,30 @@ EFI_STATUS
 /**
   Return information attached to the user.
 
-  This function returns user information. The format of the information is described in User 
-  Information. The function may return EFI_ACCESS_DENIED if the information is marked private 
-  and the handle specified by User is not the current user profile. The function may return 
-  EFI_ACCESS_DENIED if the information is marked protected and the information is associated 
+  This function returns user information. The format of the information is described in User
+  Information. The function may return EFI_ACCESS_DENIED if the information is marked private
+  and the handle specified by User is not the current user profile. The function may return
+  EFI_ACCESS_DENIED if the information is marked protected and the information is associated
   with a credential provider for which the user has not been authenticated.
 
   @param[in]     This           Points to this instance of the EFI_USER_MANAGER_PROTOCOL.
-  @param[in]     User           Handle of the user whose profile will be retrieved. 
-  @param[in]     UserInfo       Handle of the user information data record.   
-  @param[out]    Info           On entry, points to a buffer of at least *InfoSize bytes. On exit, holds the user 
-                                information. If the buffer is too small to hold the information, then 
-                                EFI_BUFFER_TOO_SMALL is returned and InfoSize is updated to contain the 
-                                number of bytes actually required. 
-  @param[in,out] InfoSize       On entry, points to the size of Info. On return, points to the size of the user 
-                                information. 
+  @param[in]     User           Handle of the user whose profile will be retrieved.
+  @param[in]     UserInfo       Handle of the user information data record.
+  @param[out]    Info           On entry, points to a buffer of at least *InfoSize bytes. On exit, holds the user
+                                information. If the buffer is too small to hold the information, then
+                                EFI_BUFFER_TOO_SMALL is returned and InfoSize is updated to contain the
+                                number of bytes actually required.
+  @param[in,out] InfoSize       On entry, points to the size of Info. On return, points to the size of the user
+                                information.
 
   @retval EFI_SUCCESS           Information returned successfully.
   @retval EFI_ACCESS_DENIED     The information about the specified user cannot be accessed by the current user.
-  @retval EFI_BUFFER_TOO_SMALL  The number of bytes specified by *InfoSize is too small to hold 
+  @retval EFI_BUFFER_TOO_SMALL  The number of bytes specified by *InfoSize is too small to hold
                                 the returned data. The actual size required is returned in *InfoSize.
   @retval EFI_NOT_FOUND         User does not refer to a valid user profile or UserInfo does not refer to a valid
                                 user info handle.
   @retval EFI_INVALID_PARAMETER Info is NULL or InfoSize is NULL.
-**/  
+**/
 typedef
 EFI_STATUS
 (EFIAPI *EFI_USER_PROFILE_GET_INFO)(
@@ -511,33 +505,33 @@ EFI_STATUS
 /**
   Add or update user information.
 
-  This function changes user information.  If NULL is pointed to by UserInfo, then a new user 
-  information record is created and its handle is returned in UserInfo. Otherwise, the existing one is 
+  This function changes user information.  If NULL is pointed to by UserInfo, then a new user
+  information record is created and its handle is returned in UserInfo. Otherwise, the existing one is
   replaced.
-  If EFI_USER_INFO_IDENTITY_POLICY_RECORD is changed, it is the caller's responsibility to keep it to 
+  If EFI_USER_INFO_IDENTITY_POLICY_RECORD is changed, it is the caller's responsibility to keep it to
   be synced with the information on credential providers.
-  If EFI_USER_INFO_EXCLUSIVE is specified in Info and a user information record of the same 
-  type already exists in the user profile, then EFI_ACCESS_DENIED will be returned and 
+  If EFI_USER_INFO_EXCLUSIVE is specified in Info and a user information record of the same
+  type already exists in the user profile, then EFI_ACCESS_DENIED will be returned and
   UserInfo will point to the handle of the existing record.
 
   @param[in]     This             Points to this instance of the EFI_USER_MANAGER_PROTOCOL.
-  @param[in]     User             Handle of the user whose profile will be retrieved. 
-  @param[in,out] UserInfo         Handle of the user information data record.   
-  @param[in]     Info             On entry, points to a buffer of at least *InfoSize bytes. On exit, holds the user 
-                                  information. If the buffer is too small to hold the information, then 
-                                  EFI_BUFFER_TOO_SMALL is returned and InfoSize is updated to contain the 
-                                  number of bytes actually required. 
-  @param[in]     InfoSize         On entry, points to the size of Info. On return, points to the size of the user 
-                                  information. 
+  @param[in]     User             Handle of the user whose profile will be retrieved.
+  @param[in,out] UserInfo         Handle of the user information data record.
+  @param[in]     Info             On entry, points to a buffer of at least *InfoSize bytes. On exit, holds the user
+                                  information. If the buffer is too small to hold the information, then
+                                  EFI_BUFFER_TOO_SMALL is returned and InfoSize is updated to contain the
+                                  number of bytes actually required.
+  @param[in]     InfoSize         On entry, points to the size of Info. On return, points to the size of the user
+                                  information.
 
   @retval EFI_SUCCESS             Information returned successfully.
   @retval EFI_ACCESS_DENIED       The record is exclusive.
-  @retval EFI_SECURITY_VIOLATION  The current user does not have permission to change the specified 
+  @retval EFI_SECURITY_VIOLATION  The current user does not have permission to change the specified
                                   user profile or user information record.
   @retval EFI_NOT_FOUND           User does not refer to a valid user profile or UserInfo does not refer to a valid
                                   user info handle.
-  @retval EFI_INVALID_PARAMETER   UserInfo is NULL or Info is NULL. 
-**/  
+  @retval EFI_INVALID_PARAMETER   UserInfo is NULL or Info is NULL.
+**/
 typedef
 EFI_STATUS
 (EFIAPI *EFI_USER_PROFILE_SET_INFO)(
@@ -559,8 +553,8 @@ EFI_STATUS
 
   @retval EFI_SUCCESS        User information deleted successfully.
   @retval EFI_NOT_FOUND      User information record UserInfo does not exist in the user profile.
-  @retval EFI_ACCESS_DENIED  The current user does not have permission to delete this user information. 
-**/ 
+  @retval EFI_ACCESS_DENIED  The current user does not have permission to delete this user information.
+**/
 typedef
 EFI_STATUS
 (EFIAPI *EFI_USER_PROFILE_DELETE_INFO)(
@@ -572,9 +566,9 @@ EFI_STATUS
 /**
   Enumerate user information of all the enrolled users on the platform.
 
-  This function returns the next user information record. To retrieve the first user information record 
-  handle, point UserInfo at a NULL. Each subsequent call will retrieve another user information 
-  record handle until there are no more, at which point UserInfo will point to NULL. 
+  This function returns the next user information record. To retrieve the first user information record
+  handle, point UserInfo at a NULL. Each subsequent call will retrieve another user information
+  record handle until there are no more, at which point UserInfo will point to NULL.
 
   @param[in]     This           Points to this instance of the EFI_USER_MANAGER_PROTOCOL.
   @param[in]     User           Handle of the user whose information will be deleted.
@@ -583,7 +577,7 @@ EFI_STATUS
   @retval EFI_SUCCESS           User information returned.
   @retval EFI_NOT_FOUND         No more user information found.
   @retval EFI_INVALID_PARAMETER UserInfo is NULL.
-**/ 
+**/
 typedef
 EFI_STATUS
 (EFIAPI *EFI_USER_PROFILE_GET_NEXT_INFO)(
diff --git a/MdePkg/Include/Protocol/Variable.h b/MdePkg/Include/Protocol/Variable.h
index c9e86026f7ae..c20934471206 100644
--- a/MdePkg/Include/Protocol/Variable.h
+++ b/MdePkg/Include/Protocol/Variable.h
@@ -1,33 +1,27 @@
 /** @file
   Variable Architectural Protocol as defined in PI Specification VOLUME 2 DXE
 
-  This provides the services required to get and set environment variables. This 
-  protocol must be produced by a runtime DXE driver and may be consumed only by 
-  the DXE Foundation. The DXE driver that produces this protocol must be a runtime 
-  driver. This driver is responsible for initializing the GetVariable(), 
+  This provides the services required to get and set environment variables. This
+  protocol must be produced by a runtime DXE driver and may be consumed only by
+  the DXE Foundation. The DXE driver that produces this protocol must be a runtime
+  driver. This driver is responsible for initializing the GetVariable(),
   GetNextVariableName(), and SetVariable() fields of the UEFI Runtime Services Table.
 
-  After the three fields of the UEFI Runtime Services Table have been initialized, 
-  the driver must install the EFI_VARIABLE_ARCH_PROTOCOL_GUID on a new handle with 
-  a NULL interface pointer. The installation of this protocol informs the DXE Foundation 
-  that the read-only and the volatile environment variable related services are 
-  now available and that the DXE Foundation must update the 32-bit CRC of the UEFI 
-  Runtime Services Table. The full complement of environment variable services are 
-  not available until both this protocol and EFI_VARIABLE_WRITE_ARCH_PROTOCOL are 
-  installed. DXE drivers that require read-only access or read/write access to volatile 
-  environment variables must have this architectural protocol in their dependency 
-  expressions. DXE drivers that require write access to nonvolatile environment 
-  variables must have the EFI_VARIABLE_WRITE_ARCH_PROTOCOL in their dependency 
+  After the three fields of the UEFI Runtime Services Table have been initialized,
+  the driver must install the EFI_VARIABLE_ARCH_PROTOCOL_GUID on a new handle with
+  a NULL interface pointer. The installation of this protocol informs the DXE Foundation
+  that the read-only and the volatile environment variable related services are
+  now available and that the DXE Foundation must update the 32-bit CRC of the UEFI
+  Runtime Services Table. The full complement of environment variable services are
+  not available until both this protocol and EFI_VARIABLE_WRITE_ARCH_PROTOCOL are
+  installed. DXE drivers that require read-only access or read/write access to volatile
+  environment variables must have this architectural protocol in their dependency
+  expressions. DXE drivers that require write access to nonvolatile environment
+  variables must have the EFI_VARIABLE_WRITE_ARCH_PROTOCOL in their dependency
   expressions.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -42,4 +36,4 @@
 
 extern EFI_GUID gEfiVariableArchProtocolGuid;
 
-#endif 
+#endif
diff --git a/MdePkg/Include/Protocol/VariableWrite.h b/MdePkg/Include/Protocol/VariableWrite.h
index 96971d9e8586..9131e1945ec4 100644
--- a/MdePkg/Include/Protocol/VariableWrite.h
+++ b/MdePkg/Include/Protocol/VariableWrite.h
@@ -1,33 +1,27 @@
 /** @file
   Variable Write Architectural Protocol as defined in PI Specification VOLUME 2 DXE
 
-  This provides the services required to set nonvolatile environment variables. 
-  This protocol must be produced by a runtime DXE driver and may be consumed only 
+  This provides the services required to set nonvolatile environment variables.
+  This protocol must be produced by a runtime DXE driver and may be consumed only
   by the DXE Foundation.
 
-  The DXE driver that produces this protocol must be a runtime driver. This driver 
+  The DXE driver that produces this protocol must be a runtime driver. This driver
   may update the SetVariable() field of the UEFI Runtime Services Table.
-  
-  After the UEFI Runtime Services Table has been initialized, the driver must 
-  install the EFI_VARIABLE_WRITE_ARCH_PROTOCOL_GUID on a new handle with a NULL 
-  interface pointer. The installation of this protocol informs the DXE Foundation 
-  that the write services for nonvolatile environment variables are now available 
-  and that the DXE Foundation must update the 32-bit CRC of the UEFI Runtime Services 
-  Table. The full complement of environment variable services are not available 
-  until both this protocol and EFI_VARIABLE_ARCH_PROTOCOL are installed. DXE drivers 
+
+  After the UEFI Runtime Services Table has been initialized, the driver must
+  install the EFI_VARIABLE_WRITE_ARCH_PROTOCOL_GUID on a new handle with a NULL
+  interface pointer. The installation of this protocol informs the DXE Foundation
+  that the write services for nonvolatile environment variables are now available
+  and that the DXE Foundation must update the 32-bit CRC of the UEFI Runtime Services
+  Table. The full complement of environment variable services are not available
+  until both this protocol and EFI_VARIABLE_ARCH_PROTOCOL are installed. DXE drivers
   that require read-only access or read/write access to volatile environment variables
   must have the EFI_VARIABLE_WRITE_ARCH_PROTOCOL in their dependency expressions.
-  DXE drivers that require write access to nonvolatile environment variables must 
-  have this architectural protocol in their dependency expressions.  
-  
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  DXE drivers that require write access to nonvolatile environment variables must
+  have this architectural protocol in their dependency expressions.
+
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -42,4 +36,4 @@
 
 extern EFI_GUID gEfiVariableWriteArchProtocolGuid;
 
-#endif 
+#endif
diff --git a/MdePkg/Include/Protocol/VlanConfig.h b/MdePkg/Include/Protocol/VlanConfig.h
index 5d980a642134..ae53d9aac78a 100644
--- a/MdePkg/Include/Protocol/VlanConfig.h
+++ b/MdePkg/Include/Protocol/VlanConfig.h
@@ -1,16 +1,10 @@
 /** @file
   EFI VLAN Config protocol is to provide manageability interface for VLAN configuration.
 
-  Copyright (c) 2009, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
+  Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-  @par Revision Reference:          
+  @par Revision Reference:
   This Protocol is introduced in UEFI Specification 2.2
 
 **/
@@ -37,28 +31,28 @@ typedef struct {
 
 
 /**
-  Create a VLAN device or modify the configuration parameter of an 
+  Create a VLAN device or modify the configuration parameter of an
   already-configured VLAN.
 
   The Set() function is used to create a new VLAN device or change the VLAN
-  configuration parameters. If the VlanId hasn't been configured in the 
+  configuration parameters. If the VlanId hasn't been configured in the
   physical Ethernet device, a new VLAN device will be created. If a VLAN with
   this VlanId is already configured, then related configuration will be updated
-  as the input parameters. 
- 
+  as the input parameters.
+
   If VlanId is zero, the VLAN device will send and receive untagged frames.
   Otherwise, the VLAN device will send and receive VLAN-tagged frames containing the VlanId.
   If VlanId is out of scope of (0-4094), EFI_INVALID_PARAMETER is returned.
-  If Priority is out of the scope of (0-7), then EFI_INVALID_PARAMETER is returned. 
-  If there is not enough system memory to perform the registration, then 
+  If Priority is out of the scope of (0-7), then EFI_INVALID_PARAMETER is returned.
+  If there is not enough system memory to perform the registration, then
   EFI_OUT_OF_RESOURCES is returned.
 
   @param[in] This                Points to the EFI_VLAN_CONFIG_PROTOCOL.
-  @param[in] VlanId              A unique identifier (1-4094) of the VLAN which is being created 
+  @param[in] VlanId              A unique identifier (1-4094) of the VLAN which is being created
                                  or modified, or zero (0).
-  @param[in] Priority            3 bit priority in VLAN header. Priority 0 is default value. If 
+  @param[in] Priority            3 bit priority in VLAN header. Priority 0 is default value. If
                                  VlanId is zero (0), Priority is ignored.
-                                 
+
   @retval EFI_SUCCESS            The VLAN is successfully configured.
   @retval EFI_INVALID_PARAMETER  One or more of following conditions is TRUE:
                                  - This is NULL.
@@ -79,14 +73,14 @@ EFI_STATUS
   Find configuration information for specified VLAN or all configured VLANs.
 
   The Find() function is used to find the configuration information for matching
-  VLAN and allocate a buffer into which those entries are copied. 
+  VLAN and allocate a buffer into which those entries are copied.
 
   @param[in]  This               Points to the EFI_VLAN_CONFIG_PROTOCOL.
   @param[in]  VlanId             Pointer to VLAN identifier. Set to NULL to find all
                                  configured VLANs.
   @param[out] NumberOfVlan       The number of VLANs which is found by the specified criteria.
   @param[out] Entries            The buffer which receive the VLAN configuration.
-                                 
+
   @retval EFI_SUCCESS            The VLAN is successfully found.
   @retval EFI_INVALID_PARAMETER  One or more of following conditions is TRUE:
                                  - This is NULL.
@@ -106,13 +100,13 @@ EFI_STATUS
 /**
   Remove the configured VLAN device.
 
-  The Remove() function is used to remove the specified VLAN device. 
+  The Remove() function is used to remove the specified VLAN device.
   If the VlanId is out of the scope of (0-4094), EFI_INVALID_PARAMETER is returned.
-  If specified VLAN hasn't been previously configured, EFI_NOT_FOUND is returned.   
+  If specified VLAN hasn't been previously configured, EFI_NOT_FOUND is returned.
 
   @param[in] This                Points to the EFI_VLAN_CONFIG_PROTOCOL.
   @param[in] VlanId              Identifier (0-4094) of the VLAN to be removed.
-                                 
+
   @retval EFI_SUCCESS            The VLAN is successfully removed.
   @retval EFI_INVALID_PARAMETER  One or more of following conditions is TRUE:
                                  - This is NULL.
@@ -129,7 +123,7 @@ EFI_STATUS
 
 ///
 /// EFI_VLAN_CONFIG_PROTOCOL
-/// provide manageability interface for VLAN setting. The intended 
+/// provide manageability interface for VLAN setting. The intended
 /// VLAN tagging implementation is IEEE802.1Q.
 ///
 struct _EFI_VLAN_CONFIG_PROTOCOL {
diff --git a/MdePkg/Include/Protocol/WatchdogTimer.h b/MdePkg/Include/Protocol/WatchdogTimer.h
index b48f943db2d1..94fa0e3ef110 100644
--- a/MdePkg/Include/Protocol/WatchdogTimer.h
+++ b/MdePkg/Include/Protocol/WatchdogTimer.h
@@ -3,14 +3,8 @@
 
   Used to provide system watchdog timer services
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 **/
 
 #ifndef __ARCH_PROTOCOL_WATCHDOG_TIMER_H__
@@ -28,7 +22,7 @@
 typedef struct _EFI_WATCHDOG_TIMER_ARCH_PROTOCOL  EFI_WATCHDOG_TIMER_ARCH_PROTOCOL;
 
 /**
-  A function of this type is called when the watchdog timer fires if a 
+  A function of this type is called when the watchdog timer fires if a
   handler has been registered.
 
   @param  Time             The time in 100 ns units that has passed since the watchdog
@@ -45,15 +39,15 @@ VOID
   );
 
 /**
-  This function registers a handler that is to be invoked when the watchdog 
-  timer fires.  By default, the EFI_WATCHDOG_TIMER protocol will call the 
-  Runtime Service ResetSystem() when the watchdog timer fires.  If a 
-  NotifyFunction is registered, then the NotifyFunction will be called before 
-  the Runtime Service ResetSystem() is called.  If NotifyFunction is NULL, then 
-  the watchdog handler is unregistered.  If a watchdog handler is registered, 
-  then EFI_SUCCESS is returned.  If an attempt is made to register a handler 
-  when a handler is already registered, then EFI_ALREADY_STARTED is returned.  
-  If an attempt is made to uninstall a handler when a handler is not installed, 
+  This function registers a handler that is to be invoked when the watchdog
+  timer fires.  By default, the EFI_WATCHDOG_TIMER protocol will call the
+  Runtime Service ResetSystem() when the watchdog timer fires.  If a
+  NotifyFunction is registered, then the NotifyFunction will be called before
+  the Runtime Service ResetSystem() is called.  If NotifyFunction is NULL, then
+  the watchdog handler is unregistered.  If a watchdog handler is registered,
+  then EFI_SUCCESS is returned.  If an attempt is made to register a handler
+  when a handler is already registered, then EFI_ALREADY_STARTED is returned.
+  If an attempt is made to uninstall a handler when a handler is not installed,
   then return EFI_INVALID_PARAMETER.
 
   @param  This             The EFI_WATCHDOG_TIMER_ARCH_PROTOCOL instance.
@@ -68,7 +62,7 @@ VOID
                                 previously registered.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_WATCHDOG_TIMER_REGISTER_HANDLER)(
   IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL  *This,
@@ -76,8 +70,8 @@ EFI_STATUS
   );
 
 /**
-  This function sets the amount of time to wait before firing the watchdog 
-  timer to TimerPeriod 100 nS units.  If TimerPeriod is 0, then the watchdog 
+  This function sets the amount of time to wait before firing the watchdog
+  timer to TimerPeriod 100 nS units.  If TimerPeriod is 0, then the watchdog
   timer is disabled.
 
   @param  This             The EFI_WATCHDOG_TIMER_ARCH_PROTOCOL instance.
@@ -91,7 +85,7 @@ EFI_STATUS
                                 error.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_WATCHDOG_TIMER_SET_TIMER_PERIOD)(
   IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL  *This,
@@ -99,8 +93,8 @@ EFI_STATUS
   );
 
 /**
-  This function retrieves the amount of time the system will wait before firing 
-  the watchdog timer.  This period is returned in TimerPeriod, and EFI_SUCCESS 
+  This function retrieves the amount of time the system will wait before firing
+  the watchdog timer.  This period is returned in TimerPeriod, and EFI_SUCCESS
   is returned.  If TimerPeriod is NULL, then EFI_INVALID_PARAMETER is returned.
 
   @param  This             The EFI_WATCHDOG_TIMER_ARCH_PROTOCOL instance.
@@ -113,7 +107,7 @@ EFI_STATUS
   @retval EFI_INVALID_PARAMETER TimerPeriod is NULL.
 
 **/
-typedef 
+typedef
 EFI_STATUS
 (EFIAPI *EFI_WATCHDOG_TIMER_GET_TIMER_PERIOD)(
   IN  EFI_WATCHDOG_TIMER_ARCH_PROTOCOL  *This,
@@ -122,14 +116,14 @@ EFI_STATUS
 
 
 ///
-/// This protocol provides the services required to implement the Boot Service 
-/// SetWatchdogTimer().  It provides a service to set the amount of time to wait 
-/// before firing the watchdog timer, and it also provides a service to register 
-/// a handler that is invoked when the watchdog timer fires.  This protocol can 
-/// implement the watchdog timer by using the event and timer Boot Services, or 
-/// it can make use of custom hardware.  When the watchdog timer fires, control 
-/// will be passed to a handler if one has been registered.  If no handler has 
-/// been registered, or the registered handler returns, then the system will be 
+/// This protocol provides the services required to implement the Boot Service
+/// SetWatchdogTimer().  It provides a service to set the amount of time to wait
+/// before firing the watchdog timer, and it also provides a service to register
+/// a handler that is invoked when the watchdog timer fires.  This protocol can
+/// implement the watchdog timer by using the event and timer Boot Services, or
+/// it can make use of custom hardware.  When the watchdog timer fires, control
+/// will be passed to a handler if one has been registered.  If no handler has
+/// been registered, or the registered handler returns, then the system will be
 /// reset by calling the Runtime Service ResetSystem().
 ///
 struct _EFI_WATCHDOG_TIMER_ARCH_PROTOCOL {
diff --git a/MdePkg/Include/Protocol/WiFi.h b/MdePkg/Include/Protocol/WiFi.h
index cbc1a17bc6f6..58c248d1eea7 100644
--- a/MdePkg/Include/Protocol/WiFi.h
+++ b/MdePkg/Include/Protocol/WiFi.h
@@ -4,13 +4,7 @@
   point (AP).
 
   Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution. The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This Protocol is introduced in UEFI Specification 2.5
diff --git a/MdePkg/Include/Protocol/WiFi2.h b/MdePkg/Include/Protocol/WiFi2.h
index c28f9fc492c8..2fb1790f3ad6 100644
--- a/MdePkg/Include/Protocol/WiFi2.h
+++ b/MdePkg/Include/Protocol/WiFi2.h
@@ -1,14 +1,8 @@
 /** @file
   This file defines the EFI Wireless MAC Connection II Protocol.
 
-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution. The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This Protocol is introduced in UEFI Specification 2.6
@@ -202,7 +196,7 @@ typedef struct {
   // The NetworkDesc is a pointer to an array of EFI_80211_NETWORK_DESCRIPTION
   // instances. It is caller's responsibility to free this buffer.
   //
-  EFI_80211_NETWORK_DESCRIPTION             **NetworkDesc;
+  EFI_80211_NETWORK_DESCRIPTION             NetworkDesc[1];
 } EFI_80211_GET_NETWORKS_RESULT;
 
 ///
diff --git a/MdePkg/Include/Register/Amd/Cpuid.h b/MdePkg/Include/Register/Amd/Cpuid.h
new file mode 100644
index 000000000000..09aebd9894cf
--- /dev/null
+++ b/MdePkg/Include/Register/Amd/Cpuid.h
@@ -0,0 +1,737 @@
+/** @file
+  CPUID leaf definitions.
+
+  Provides defines for CPUID leaf indexes.  Data structures are provided for
+  registers returned by a CPUID leaf that contain one or more bit fields.
+  If a register returned is a single 32-bit value, then a data structure is
+  not provided for that register.
+
+  Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  AMD64 Architecture Programming Manual volume 2, March 2017, Sections 15.34
+
+**/
+
+#ifndef __AMD_CPUID_H__
+#define __AMD_CPUID_H__
+
+/**
+CPUID Signature Information
+
+@param   EAX  CPUID_SIGNATURE (0x00)
+
+@retval  EAX  Returns the highest value the CPUID instruction recognizes for
+              returning basic processor information. The value is returned is
+              processor specific.
+@retval  EBX  First 4 characters of a vendor identification string.
+@retval  ECX  Last 4 characters of a vendor identification string.
+@retval  EDX  Middle 4 characters of a vendor identification string.
+
+**/
+
+///
+/// @{ CPUID signature values returned by AMD processors
+///
+#define CPUID_SIGNATURE_AUTHENTIC_AMD_EBX  SIGNATURE_32 ('A', 'u', 't', 'h')
+#define CPUID_SIGNATURE_AUTHENTIC_AMD_EDX  SIGNATURE_32 ('e', 'n', 't', 'i')
+#define CPUID_SIGNATURE_AUTHENTIC_AMD_ECX  SIGNATURE_32 ('c', 'A', 'M', 'D')
+///
+/// @}
+///
+
+
+/**
+  CPUID Extended Processor Signature and Features
+
+  @param   EAX  CPUID_EXTENDED_CPU_SIG (0x80000001)
+
+  @retval  EAX  Extended Family, Model, Stepping Identifiers
+                described by the type CPUID_AMD_EXTENDED_CPU_SIG_EAX.
+  @retval  EBX  Brand Identifier
+                described by the type CPUID_AMD_EXTENDED_CPU_SIG_EBX.
+  @retval  ECX  Extended Feature Identifiers
+                described by the type CPUID_AMD_EXTENDED_CPU_SIG_ECX.
+  @retval  EDX  Extended Feature Identifiers
+                described by the type CPUID_AMD_EXTENDED_CPU_SIG_EDX.
+**/
+
+/**
+  CPUID Extended Processor Signature and Features EAX for CPUID leaf
+  #CPUID_EXTENDED_CPU_SIG.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 3:0] Stepping.
+    ///
+    UINT32  Stepping:4;
+    ///
+    /// [Bits 7:4] Base Model.
+    ///
+    UINT32  BaseModel:4;
+    ///
+    /// [Bits 11:8] Base Family.
+    ///
+    UINT32  BaseFamily:4;
+    ///
+    /// [Bit 15:12] Reserved.
+    ///
+    UINT32  Reserved1:4;
+    ///
+    /// [Bits 19:16] Extended Model.
+    ///
+    UINT32  ExtModel:4;
+    ///
+    /// [Bits 27:20] Extended Family.
+    ///
+    UINT32  ExtFamily:8;
+    ///
+    /// [Bit 31:28] Reserved.
+    ///
+    UINT32  Reserved2:4;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_AMD_EXTENDED_CPU_SIG_EAX;
+
+/**
+  CPUID Extended Processor Signature and Features EBX for CPUID leaf
+  #CPUID_EXTENDED_CPU_SIG.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 27:0] Reserved.
+    ///
+    UINT32  Reserved:28;
+    ///
+    /// [Bit 31:28] Package Type.
+    ///
+    UINT32  PkgType:4;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_AMD_EXTENDED_CPU_SIG_EBX;
+
+/**
+  CPUID Extended Processor Signature and Features ECX for CPUID leaf
+  #CPUID_EXTENDED_CPU_SIG.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] LAHF/SAHF available in 64-bit mode.
+    ///
+    UINT32  LAHF_SAHF:1;
+    ///
+    /// [Bit 1] Core multi-processing legacy mode.
+    ///
+    UINT32  CmpLegacy:1;
+    ///
+    /// [Bit 2] Secure Virtual Mode feature.
+    ///
+    UINT32  SVM:1;
+    ///
+    /// [Bit 3] Extended APIC register space.
+    ///
+    UINT32  ExtApicSpace:1;
+    ///
+    /// [Bit 4] LOCK MOV CR0 means MOV CR8.
+    ///
+    UINT32  AltMovCr8:1;
+    ///
+    /// [Bit 5] LZCNT instruction support.
+    ///
+    UINT32  LZCNT:1;
+    ///
+    /// [Bit 6] SSE4A instruction support.
+    ///
+    UINT32  SSE4A:1;
+    ///
+    /// [Bit 7] Misaligned SSE Mode.
+    ///
+    UINT32  MisAlignSse:1;
+    ///
+    /// [Bit 8] ThreeDNow Prefetch instructions.
+    ///
+    UINT32  PREFETCHW:1;
+    ///
+    /// [Bit 9] OS Visible Work-around support.
+    ///
+    UINT32  OSVW:1;
+    ///
+    /// [Bit 10] Instruction Based Sampling.
+    ///
+    UINT32  IBS:1;
+    ///
+    /// [Bit 11] Extended Operation Support.
+    ///
+    UINT32  XOP:1;
+    ///
+    /// [Bit 12] SKINIT and STGI support.
+    ///
+    UINT32  SKINIT:1;
+    ///
+    /// [Bit 13] Watchdog Timer support.
+    ///
+    UINT32  WDT:1;
+    ///
+    /// [Bit 14] Reserved.
+    ///
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 15] Lightweight Profiling support.
+    ///
+    UINT32  LWP:1;
+    ///
+    /// [Bit 16] 4-Operand FMA instruction support.
+    ///
+    UINT32  FMA4:1;
+    ///
+    /// [Bit 17] Translation Cache Extension.
+    ///
+    UINT32  TCE:1;
+    ///
+    /// [Bit 21:18] Reserved.
+    ///
+    UINT32  Reserved2:4;
+    ///
+    /// [Bit 22] Topology Extensions support.
+    ///
+    UINT32  TopologyExtensions:1;
+    ///
+    /// [Bit 23] Core Performance Counter Extensions.
+    ///
+    UINT32  PerfCtrExtCore:1;
+    ///
+    /// [Bit 25:24] Reserved.
+    ///
+    UINT32  Reserved3:2;
+    ///
+    /// [Bit 26] Data Breakpoint Extension.
+    ///
+    UINT32  DataBreakpointExtension:1;
+    ///
+    /// [Bit 27] Performance Time-Stamp Counter.
+    ///
+    UINT32  PerfTsc:1;
+    ///
+    /// [Bit 28] L3 Performance Counter Extensions.
+    ///
+    UINT32  PerfCtrExtL3:1;
+    ///
+    /// [Bit 29] MWAITX and MONITORX capability.
+    ///
+    UINT32  MwaitExtended:1;
+    ///
+    /// [Bit 31:30] Reserved.
+    ///
+    UINT32  Reserved4:2;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_AMD_EXTENDED_CPU_SIG_ECX;
+
+/**
+  CPUID Extended Processor Signature and Features EDX for CPUID leaf
+  #CPUID_EXTENDED_CPU_SIG.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] x87 floating point unit on-chip.
+    ///
+    UINT32  FPU:1;
+    ///
+    /// [Bit 1] Virtual-mode enhancements.
+    ///
+    UINT32  VME:1;
+    ///
+    /// [Bit 2] Debugging extensions, IO breakpoints, CR4.DE.
+    ///
+    UINT32  DE:1;
+    ///
+    /// [Bit 3] Page-size extensions (4 MB pages).
+    ///
+    UINT32  PSE:1;
+    ///
+    /// [Bit 4] Time stamp counter, RDTSC/RDTSCP instructions, CR4.TSD.
+    ///
+    UINT32  TSC:1;
+    ///
+    /// [Bit 5] MSRs, with RDMSR and WRMSR instructions.
+    ///
+    UINT32  MSR:1;
+    ///
+    /// [Bit 6] Physical-address extensions (PAE).
+    ///
+    UINT32  PAE:1;
+    ///
+    /// [Bit 7] Machine check exception, CR4.MCE.
+    ///
+    UINT32  MCE:1;
+    ///
+    /// [Bit 8] CMPXCHG8B instruction.
+    ///
+    UINT32  CMPXCHG8B:1;
+    ///
+    /// [Bit 9] APIC exists and is enabled.
+    ///
+    UINT32  APIC:1;
+    ///
+    /// [Bit 10] Reserved.
+    ///
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 11] SYSCALL and SYSRET instructions.
+    ///
+    UINT32  SYSCALL_SYSRET:1;
+    ///
+    /// [Bit 12] Memory-type range registers.
+    ///
+    UINT32  MTRR:1;
+    ///
+    /// [Bit 13] Page global extension, CR4.PGE.
+    ///
+    UINT32  PGE:1;
+    ///
+    /// [Bit 14] Machine check architecture, MCG_CAP.
+    ///
+    UINT32  MCA:1;
+    ///
+    /// [Bit 15] Conditional move instructions, CMOV, FCOMI, FCMOV.
+    ///
+    UINT32  CMOV:1;
+    ///
+    /// [Bit 16] Page attribute table.
+    ///
+    UINT32  PAT:1;
+    ///
+    /// [Bit 17] Page-size extensions.
+    ///
+    UINT32  PSE36 : 1;
+    ///
+    /// [Bit 19:18] Reserved.
+    ///
+    UINT32  Reserved2:2;
+    ///
+    /// [Bit 20] No-execute page protection.
+    ///
+    UINT32  NX:1;
+    ///
+    /// [Bit 21] Reserved.
+    ///
+    UINT32  Reserved3:1;
+    ///
+    /// [Bit 22] AMD Extensions to MMX instructions.
+    ///
+    UINT32  MmxExt:1;
+    ///
+    /// [Bit 23] MMX instructions.
+    ///
+    UINT32  MMX:1;
+    ///
+    /// [Bit 24] FXSAVE and FXRSTOR instructions.
+    ///
+    UINT32  FFSR:1;
+    ///
+    /// [Bit 25] FXSAVE and FXRSTOR instruction optimizations.
+    ///
+    UINT32  FFXSR:1;
+    ///
+    /// [Bit 26] 1-GByte large page support.
+    ///
+    UINT32  Page1GB:1;
+    ///
+    /// [Bit 27] RDTSCP instructions.
+    ///
+    UINT32  RDTSCP:1;
+    ///
+    /// [Bit 28] Reserved.
+    ///
+    UINT32  Reserved4:1;
+    ///
+    /// [Bit 29] Long Mode.
+    ///
+    UINT32  LM:1;
+    ///
+    /// [Bit 30] 3DNow! instructions.
+    ///
+    UINT32  ThreeDNow:1;
+    ///
+    /// [Bit 31] AMD Extensions to 3DNow! instructions.
+    ///
+    UINT32  ThreeDNowExt:1;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_AMD_EXTENDED_CPU_SIG_EDX;
+
+
+/**
+CPUID Linear Physical Address Size
+
+@param   EAX  CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008)
+
+@retval  EAX  Linear/Physical Address Size described by the type
+              CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX.
+@retval  EBX  Linear/Physical Address Size described by the type
+              CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX.
+@retval  ECX  Linear/Physical Address Size described by the type
+              CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX.
+@retval  EDX  Reserved.
+**/
+
+/**
+  CPUID Linear Physical Address Size EAX for CPUID leaf
+  #CPUID_VIR_PHY_ADDRESS_SIZE.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Maximum physical byte address size in bits.
+    ///
+    UINT32  PhysicalAddressBits:8;
+    ///
+    /// [Bits 15:8] Maximum linear byte address size in bits.
+    ///
+    UINT32  LinearAddressBits:8;
+    ///
+    /// [Bits 23:16] Maximum guest physical byte address size in bits.
+    ///
+    UINT32  GuestPhysAddrSize:8;
+    ///
+    /// [Bit 31:24] Reserved.
+    ///
+    UINT32  Reserved:8;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX;
+
+/**
+  CPUID Linear Physical Address Size EBX for CPUID leaf
+  #CPUID_VIR_PHY_ADDRESS_SIZE.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 0] Clear Zero Instruction.
+    ///
+    UINT32  CLZERO:1;
+    ///
+    /// [Bits 1] Instructions retired count support.
+    ///
+    UINT32  IRPerf:1;
+    ///
+    /// [Bits 2] Restore error pointers for XSave instructions.
+    ///
+    UINT32  XSaveErPtr:1;
+    ///
+    /// [Bit 31:3] Reserved.
+    ///
+    UINT32  Reserved:29;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX;
+
+/**
+  CPUID Linear Physical Address Size ECX for CPUID leaf
+  #CPUID_VIR_PHY_ADDRESS_SIZE.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Number of threads - 1.
+    ///
+    UINT32  NC:8;
+    ///
+    /// [Bit 11:8] Reserved.
+    ///
+    UINT32  Reserved1:4;
+    ///
+    /// [Bits 15:12] APIC ID size.
+    ///
+    UINT32  ApicIdCoreIdSize:4;
+    ///
+    /// [Bits 17:16] Performance time-stamp counter size.
+    ///
+    UINT32  PerfTscSize:2;
+    ///
+    /// [Bit 31:18] Reserved.
+    ///
+    UINT32  Reserved2:14;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX;
+
+
+/**
+  CPUID AMD Processor Topology
+
+  @param   EAX  CPUID_AMD_PROCESSOR_TOPOLOGY (0x8000001E)
+
+  @retval  EAX  Extended APIC ID described by the type
+                CPUID_AMD_PROCESSOR_TOPOLOGY_EAX.
+  @retval  EBX  Core Identifiers described by the type
+                CPUID_AMD_PROCESSOR_TOPOLOGY_EBX.
+  @retval  ECX  Node Identifiers described by the type
+                CPUID_AMD_PROCESSOR_TOPOLOGY_ECX.
+  @retval  EDX  Reserved.
+**/
+#define CPUID_AMD_PROCESSOR_TOPOLOGY             0x8000001E
+
+/**
+  CPUID AMD Processor Topology EAX for CPUID leaf
+  #CPUID_AMD_PROCESSOR_TOPOLOGY.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 31:0] Extended APIC Id.
+    ///
+    UINT32  ExtendedApicId;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_AMD_PROCESSOR_TOPOLOGY_EAX;
+
+/**
+  CPUID AMD Processor Topology EBX for CPUID leaf
+  #CPUID_AMD_PROCESSOR_TOPOLOGY.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Core Id.
+    ///
+    UINT32  CoreId:8;
+    ///
+    /// [Bits 15:8] Threads per core.
+    ///
+    UINT32  ThreadsPerCore:8;
+    ///
+    /// [Bit 31:16] Reserved.
+    ///
+    UINT32  Reserved:16;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_AMD_PROCESSOR_TOPOLOGY_EBX;
+
+/**
+  CPUID AMD Processor Topology ECX for CPUID leaf
+  #CPUID_AMD_PROCESSOR_TOPOLOGY.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Node Id.
+    ///
+    UINT32  NodeId:8;
+    ///
+    /// [Bits 10:8] Nodes per processor.
+    ///
+    UINT32  NodesPerProcessor:3;
+    ///
+    /// [Bit 31:11] Reserved.
+    ///
+    UINT32  Reserved:21;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_AMD_PROCESSOR_TOPOLOGY_ECX;
+
+
+/**
+  CPUID Memory Encryption Information
+
+  @param   EAX  CPUID_MEMORY_ENCRYPTION_INFO (0x8000001F)
+
+  @retval  EAX  Returns the memory encryption feature support status.
+  @retval  EBX  If memory encryption feature is present then return
+                the page table bit number used to enable memory encryption support
+                and reducing of physical address space in bits.
+  @retval  ECX  Returns number of encrypted guest supported simultaneously.
+  @retval  EDX  Returns minimum SEV enabled and SEV disabled ASID.
+
+  <b>Example usage</b>
+  @code
+  UINT32 Eax;
+  UINT32 Ebx;
+  UINT32 Ecx;
+  UINT32 Edx;
+
+  AsmCpuid (CPUID_MEMORY_ENCRYPTION_INFO, &Eax, &Ebx, &Ecx, &Edx);
+  @endcode
+**/
+
+#define CPUID_MEMORY_ENCRYPTION_INFO             0x8000001F
+
+/**
+  CPUID Memory Encryption support information EAX for CPUID leaf
+  #CPUID_MEMORY_ENCRYPTION_INFO.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Secure Memory Encryption (Sme) Support
+    ///
+    UINT32  SmeBit:1;
+
+    ///
+    /// [Bit 1] Secure Encrypted Virtualization (Sev) Support
+    ///
+    UINT32  SevBit:1;
+
+    ///
+    /// [Bit 2] Page flush MSR support
+    ///
+    UINT32  PageFlushMsrBit:1;
+
+    ///
+    /// [Bit 3] Encrypted state support
+    ///
+    UINT32  SevEsBit:1;
+
+    ///
+    /// [Bit 31:4] Reserved
+    ///
+    UINT32  ReservedBits:28;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_MEMORY_ENCRYPTION_INFO_EAX;
+
+/**
+  CPUID Memory Encryption support information EBX for CPUID leaf
+  #CPUID_MEMORY_ENCRYPTION_INFO.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 5:0] Page table bit number used to enable memory encryption
+    ///
+    UINT32  PtePosBits:6;
+
+    ///
+    /// [Bit 11:6] Reduction of system physical address space bits when
+    ///  memory encryption is enabled
+    ///
+    UINT32  ReducedPhysBits:5;
+
+    ///
+    /// [Bit 31:12] Reserved
+    ///
+    UINT32  ReservedBits:21;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_MEMORY_ENCRYPTION_INFO_EBX;
+
+/**
+  CPUID Memory Encryption support information ECX for CPUID leaf
+  #CPUID_MEMORY_ENCRYPTION_INFO.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 31:0] Number of encrypted guest supported simultaneously
+    ///
+    UINT32  NumGuests;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_MEMORY_ENCRYPTION_INFO_ECX;
+
+/**
+  CPUID Memory Encryption support information EDX for CPUID leaf
+  #CPUID_MEMORY_ENCRYPTION_INFO.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 31:0] Minimum SEV enabled, SEV-ES disabled ASID
+    ///
+    UINT32  MinAsid;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_MEMORY_ENCRYPTION_INFO_EDX;
+
+#endif
diff --git a/MdePkg/Include/Register/Amd/Fam17Msr.h b/MdePkg/Include/Register/Amd/Fam17Msr.h
new file mode 100644
index 000000000000..4325477eef6f
--- /dev/null
+++ b/MdePkg/Include/Register/Amd/Fam17Msr.h
@@ -0,0 +1,56 @@
+/** @file
+  MSR Definitions.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  AMD64 Architecture Programming Manual volume 2, March 2017, Sections 15.34
+
+**/
+
+#ifndef __FAM17_MSR_H__
+#define __FAM17_MSR_H__
+
+/**
+  Secure Encrypted Virtualization (SEV) status register
+
+**/
+#define MSR_SEV_STATUS                     0xc0010131
+
+/**
+  MSR information returned for #MSR_SEV_STATUS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Secure Encrypted Virtualization (Sev) is enabled
+    ///
+    UINT32  SevBit:1;
+
+    ///
+    /// [Bit 1] Secure Encrypted Virtualization Encrypted State (SevEs) is enabled
+    ///
+    UINT32  SevEsBit:1;
+
+    UINT32  Reserved:30;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SEV_STATUS_REGISTER;
+
+#endif
diff --git a/MdePkg/Include/Register/Amd/Msr.h b/MdePkg/Include/Register/Amd/Msr.h
new file mode 100644
index 000000000000..024d5aa6de93
--- /dev/null
+++ b/MdePkg/Include/Register/Amd/Msr.h
@@ -0,0 +1,23 @@
+/** @file
+  MSR Definitions.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2017 - 2019, Advanced Micro Devices. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  AMD64 Architecture Programming Manual volume 2, March 2017, Sections 15.34
+
+**/
+
+#ifndef __AMD_MSR_H__
+#define __AMD_MSR_H__
+
+#include <Register/Intel/ArchitecturalMsr.h>
+#include <Register/Amd/Fam17Msr.h>
+
+#endif
diff --git a/MdePkg/Include/Register/Intel/ArchitecturalMsr.h b/MdePkg/Include/Register/Intel/ArchitecturalMsr.h
new file mode 100644
index 000000000000..22b9ec36f4db
--- /dev/null
+++ b/MdePkg/Include/Register/Intel/ArchitecturalMsr.h
@@ -0,0 +1,6572 @@
+/** @file
+  Intel Architectural MSR Definitions.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+  May 2018, Volume 4: Model-Specific-Registers (MSR)
+
+**/
+
+#ifndef __INTEL_ARCHITECTURAL_MSR_H__
+#define __INTEL_ARCHITECTURAL_MSR_H__
+
+/**
+  See Section 2.22, "MSRs in Pentium Processors.". Pentium Processor (05_01H).
+
+  @param  ECX  MSR_IA32_P5_MC_ADDR (0x00000000)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_P5_MC_ADDR);
+  AsmWriteMsr64 (MSR_IA32_P5_MC_ADDR, Msr);
+  @endcode
+  @note MSR_IA32_P5_MC_ADDR is defined as IA32_P5_MC_ADDR in SDM.
+**/
+#define MSR_IA32_P5_MC_ADDR                      0x00000000
+
+
+/**
+  See Section 2.22, "MSRs in Pentium Processors.". DF_DM = 05_01H.
+
+  @param  ECX  MSR_IA32_P5_MC_TYPE (0x00000001)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_P5_MC_TYPE);
+  AsmWriteMsr64 (MSR_IA32_P5_MC_TYPE, Msr);
+  @endcode
+  @note MSR_IA32_P5_MC_TYPE is defined as IA32_P5_MC_TYPE in SDM.
+**/
+#define MSR_IA32_P5_MC_TYPE                      0x00000001
+
+
+/**
+  See Section 8.10.5, "Monitor/Mwait Address Range Determination.". Introduced
+  at Display Family / Display Model 0F_03H.
+
+  @param  ECX  MSR_IA32_MONITOR_FILTER_SIZE (0x00000006)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_MONITOR_FILTER_SIZE);
+  AsmWriteMsr64 (MSR_IA32_MONITOR_FILTER_SIZE, Msr);
+  @endcode
+  @note MSR_IA32_MONITOR_FILTER_SIZE is defined as IA32_MONITOR_FILTER_SIZE in SDM.
+**/
+#define MSR_IA32_MONITOR_FILTER_SIZE             0x00000006
+
+
+/**
+  See Section 17.17, "Time-Stamp Counter.". Introduced at Display Family /
+  Display Model 05_01H.
+
+  @param  ECX  MSR_IA32_TIME_STAMP_COUNTER (0x00000010)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_TIME_STAMP_COUNTER);
+  AsmWriteMsr64 (MSR_IA32_TIME_STAMP_COUNTER, Msr);
+  @endcode
+  @note MSR_IA32_TIME_STAMP_COUNTER is defined as IA32_TIME_STAMP_COUNTER in SDM.
+**/
+#define MSR_IA32_TIME_STAMP_COUNTER              0x00000010
+
+
+/**
+  Platform ID (RO)  The operating system can use this MSR to determine "slot"
+  information for the processor and the proper microcode update to load.
+  Introduced at Display Family / Display Model 06_01H.
+
+  @param  ECX  MSR_IA32_PLATFORM_ID (0x00000017)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_PLATFORM_ID_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_PLATFORM_ID_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_PLATFORM_ID_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID);
+  @endcode
+  @note MSR_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM.
+**/
+#define MSR_IA32_PLATFORM_ID                     0x00000017
+
+/**
+  MSR information returned for MSR index #MSR_IA32_PLATFORM_ID
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:32;
+    UINT32  Reserved2:18;
+    ///
+    /// [Bits 52:50] Platform Id (RO)  Contains information concerning the
+    /// intended platform for the processor.
+    ///   52 51 50
+    ///   -- -- --
+    ///    0  0  0  Processor Flag 0.
+    ///    0  0  1  Processor Flag 1
+    ///    0  1  0  Processor Flag 2
+    ///    0  1  1  Processor Flag 3
+    ///    1  0  0  Processor Flag 4
+    ///    1  0  1  Processor Flag 5
+    ///    1  1  0  Processor Flag 6
+    ///    1  1  1  Processor Flag 7
+    ///
+    UINT32  PlatformId:3;
+    UINT32  Reserved3:11;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_PLATFORM_ID_REGISTER;
+
+
+/**
+  06_01H.
+
+  @param  ECX  MSR_IA32_APIC_BASE (0x0000001B)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_APIC_BASE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_APIC_BASE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_APIC_BASE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
+  AsmWriteMsr64 (MSR_IA32_APIC_BASE, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_APIC_BASE is defined as IA32_APIC_BASE in SDM.
+**/
+#define MSR_IA32_APIC_BASE                       0x0000001B
+
+/**
+  MSR information returned for MSR index #MSR_IA32_APIC_BASE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:8;
+    ///
+    /// [Bit 8] BSP flag (R/W).
+    ///
+    UINT32  BSP:1;
+    UINT32  Reserved2:1;
+    ///
+    /// [Bit 10] Enable x2APIC mode. Introduced at Display Family / Display
+    /// Model 06_1AH.
+    ///
+    UINT32  EXTD:1;
+    ///
+    /// [Bit 11] APIC Global Enable (R/W).
+    ///
+    UINT32  EN:1;
+    ///
+    /// [Bits 31:12] APIC Base (R/W).
+    ///
+    UINT32  ApicBase:20;
+    ///
+    /// [Bits 63:32] APIC Base (R/W).
+    ///
+    UINT32  ApicBaseHi:32;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_APIC_BASE_REGISTER;
+
+
+/**
+  Control Features in Intel 64 Processor (R/W). If any one enumeration
+  condition for defined bit field holds.
+
+  @param  ECX  MSR_IA32_FEATURE_CONTROL (0x0000003A)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_FEATURE_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FEATURE_CONTROL);
+  AsmWriteMsr64 (MSR_IA32_FEATURE_CONTROL, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.
+**/
+#define MSR_IA32_FEATURE_CONTROL                 0x0000003A
+
+/**
+  MSR information returned for MSR index #MSR_IA32_FEATURE_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Lock bit (R/WO): (1 = locked). When set, locks this MSR from
+    /// being written, writes to this bit will result in GP(0). Note: Once the
+    /// Lock bit is set, the contents of this register cannot be modified.
+    /// Therefore the lock bit must be set after configuring support for Intel
+    /// Virtualization Technology and prior to transferring control to an
+    /// option ROM or the OS. Hence, once the Lock bit is set, the entire
+    /// IA32_FEATURE_CONTROL contents are preserved across RESET when PWRGOOD
+    /// is not deasserted. If any one enumeration condition for defined bit
+    /// field position greater than bit 0 holds.
+    ///
+    UINT32  Lock:1;
+    ///
+    /// [Bit 1] Enable VMX inside SMX operation (R/WL): This bit enables a
+    /// system executive to use VMX in conjunction with SMX to support
+    /// Intel(R) Trusted Execution Technology. BIOS must set this bit only
+    /// when the CPUID function 1 returns VMX feature flag and SMX feature
+    /// flag set (ECX bits 5 and 6 respectively). If CPUID.01H:ECX[5] = 1 &&
+    /// CPUID.01H:ECX[6] = 1.
+    ///
+    UINT32  EnableVmxInsideSmx:1;
+    ///
+    /// [Bit 2] Enable VMX outside SMX operation (R/WL): This bit enables VMX
+    /// for system executive that do not require SMX. BIOS must set this bit
+    /// only when the CPUID function 1 returns VMX feature flag set (ECX bit
+    /// 5). If CPUID.01H:ECX[5] = 1.
+    ///
+    UINT32  EnableVmxOutsideSmx:1;
+    UINT32  Reserved1:5;
+    ///
+    /// [Bits 14:8] SENTER Local Function Enables (R/WL): When set, each bit
+    /// in the field represents an enable control for a corresponding SENTER
+    /// function. This bit is supported only if CPUID.1:ECX.[bit 6] is set. If
+    /// CPUID.01H:ECX[6] = 1.
+    ///
+    UINT32  SenterLocalFunctionEnables:7;
+    ///
+    /// [Bit 15] SENTER Global Enable (R/WL): This bit must be set to enable
+    /// SENTER leaf functions. This bit is supported only if CPUID.1:ECX.[bit
+    /// 6] is set. If CPUID.01H:ECX[6] = 1.
+    ///
+    UINT32  SenterGlobalEnable:1;
+    UINT32  Reserved2:1;
+    ///
+    /// [Bit 17] SGX Launch Control Enable (R/WL): This bit must be set to
+    /// enable runtime reconfiguration of SGX Launch Control via
+    /// IA32_SGXLEPUBKEYHASHn MSR. If CPUID.(EAX=07H, ECX=0H): ECX[30] = 1.
+    ///
+    UINT32  SgxLaunchControlEnable:1;
+    ///
+    /// [Bit 18] SGX Global Enable (R/WL): This bit must be set to enable SGX
+    /// leaf functions. If CPUID.(EAX=07H, ECX=0H): EBX[2] = 1.
+    ///
+    UINT32  SgxEnable:1;
+    UINT32  Reserved3:1;
+    ///
+    /// [Bit 20] LMCE On (R/WL): When set, system software can program the
+    /// MSRs associated with LMCE to configure delivery of some machine check
+    /// exceptions to a single logical processor. If IA32_MCG_CAP[27] = 1.
+    ///
+    UINT32  LmceOn:1;
+    UINT32  Reserved4:11;
+    UINT32  Reserved5:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_FEATURE_CONTROL_REGISTER;
+
+
+/**
+  Per Logical Processor TSC Adjust (R/Write to clear). If CPUID.(EAX=07H,
+  ECX=0H): EBX[1] = 1. THREAD_ADJUST:  Local offset value of the IA32_TSC for
+  a logical processor. Reset value is Zero. A write to IA32_TSC will modify
+  the local offset in IA32_TSC_ADJUST and the content of IA32_TSC, but does
+  not affect the internal invariant TSC hardware.
+
+  @param  ECX  MSR_IA32_TSC_ADJUST (0x0000003B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_TSC_ADJUST);
+  AsmWriteMsr64 (MSR_IA32_TSC_ADJUST, Msr);
+  @endcode
+  @note MSR_IA32_TSC_ADJUST is defined as IA32_TSC_ADJUST in SDM.
+**/
+#define MSR_IA32_TSC_ADJUST                      0x0000003B
+
+
+/**
+  BIOS Update Trigger (W) Executing a WRMSR instruction to this MSR causes a
+  microcode update to be loaded into the processor. See Section 9.11.6,
+  "Microcode Update Loader." A processor may prevent writing to this MSR when
+  loading guest states on VM entries or saving guest states on VM exits.
+  Introduced at Display Family / Display Model 06_01H.
+
+  @param  ECX  MSR_IA32_BIOS_UPDT_TRIG (0x00000079)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = 0;
+  AsmWriteMsr64 (MSR_IA32_BIOS_UPDT_TRIG, Msr);
+  @endcode
+  @note MSR_IA32_BIOS_UPDT_TRIG is defined as IA32_BIOS_UPDT_TRIG in SDM.
+**/
+#define MSR_IA32_BIOS_UPDT_TRIG                  0x00000079
+
+
+/**
+  BIOS Update Signature (RO) Returns the microcode update signature following
+  the execution of CPUID.01H. A processor may prevent writing to this MSR when
+  loading guest states on VM entries or saving guest states on VM exits.
+  Introduced at Display Family / Display Model 06_01H.
+
+  @param  ECX  MSR_IA32_BIOS_SIGN_ID (0x0000008B)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_BIOS_SIGN_ID_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BIOS_SIGN_ID);
+  @endcode
+  @note MSR_IA32_BIOS_SIGN_ID is defined as IA32_BIOS_SIGN_ID in SDM.
+**/
+#define MSR_IA32_BIOS_SIGN_ID                    0x0000008B
+
+/**
+  MSR information returned for MSR index #MSR_IA32_BIOS_SIGN_ID
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved:32;
+    ///
+    /// [Bits 63:32] Microcode update signature. This field contains the
+    /// signature of the currently loaded microcode update when read following
+    /// the execution of the CPUID instruction, function 1. It is required
+    /// that this register field be pre-loaded with zero prior to executing
+    /// the CPUID, function 1. If the field remains equal to zero, then there
+    /// is no microcode update loaded. Another nonzero value will be the
+    /// signature.
+    ///
+    UINT32  MicrocodeUpdateSignature:32;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_BIOS_SIGN_ID_REGISTER;
+
+
+/**
+  IA32_SGXLEPUBKEYHASH[(64*n+63):(64*n)] (R/W) Bits (64*n+63):(64*n) of the
+  SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On reset, the
+  default value is the digest of Intel's signing key. Read permitted If
+  CPUID.(EAX=12H,ECX=0H):EAX[0]=1, Write permitted if CPUID.(EAX=12H,ECX=0H):
+  EAX[0]=1 && IA32_FEATURE_CONTROL[17] = 1 && IA32_FEATURE_CONTROL[0] = 1.
+
+  @param  ECX  MSR_IA32_SGXLEPUBKEYHASHn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_SGXLEPUBKEYHASHn);
+  AsmWriteMsr64 (MSR_IA32_SGXLEPUBKEYHASHn, Msr);
+  @endcode
+  @note MSR_IA32_SGXLEPUBKEYHASH0 is defined as IA32_SGXLEPUBKEYHASH0 in SDM.
+        MSR_IA32_SGXLEPUBKEYHASH1 is defined as IA32_SGXLEPUBKEYHASH1 in SDM.
+        MSR_IA32_SGXLEPUBKEYHASH2 is defined as IA32_SGXLEPUBKEYHASH2 in SDM.
+        MSR_IA32_SGXLEPUBKEYHASH3 is defined as IA32_SGXLEPUBKEYHASH3 in SDM.
+  @{
+**/
+#define MSR_IA32_SGXLEPUBKEYHASH0                0x0000008C
+#define MSR_IA32_SGXLEPUBKEYHASH1                0x0000008D
+#define MSR_IA32_SGXLEPUBKEYHASH2                0x0000008E
+#define MSR_IA32_SGXLEPUBKEYHASH3                0x0000008F
+/// @}
+
+
+/**
+  SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1 or CPUID.01H: ECX[6] =
+  1.
+
+  @param  ECX  MSR_IA32_SMM_MONITOR_CTL (0x0000009B)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_SMM_MONITOR_CTL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMM_MONITOR_CTL);
+  AsmWriteMsr64 (MSR_IA32_SMM_MONITOR_CTL, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_SMM_MONITOR_CTL is defined as IA32_SMM_MONITOR_CTL in SDM.
+**/
+#define MSR_IA32_SMM_MONITOR_CTL                 0x0000009B
+
+/**
+  MSR information returned for MSR index #MSR_IA32_SMM_MONITOR_CTL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Valid (R/W).  The STM may be invoked using VMCALL only if this
+    /// bit is 1. Because VMCALL is used to activate the dual-monitor treatment
+    /// (see Section 34.15.6), the dual-monitor treatment cannot be activated
+    /// if the bit is 0. This bit is cleared when the logical processor is
+    /// reset.
+    ///
+    UINT32  Valid:1;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 2] Controls SMI unblocking by VMXOFF (see Section 34.14.4). If
+    /// IA32_VMX_MISC[28].
+    ///
+    UINT32  BlockSmi:1;
+    UINT32  Reserved2:9;
+    ///
+    /// [Bits 31:12] MSEG Base (R/W).
+    ///
+    UINT32  MsegBase:20;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_SMM_MONITOR_CTL_REGISTER;
+
+/**
+  MSEG header that is located at the physical address specified by the MsegBase
+  field of #MSR_IA32_SMM_MONITOR_CTL_REGISTER.
+**/
+typedef struct {
+  ///
+  /// Different processors may use different MSEG revision identifiers. These
+  /// identifiers enable software to avoid using an MSEG header formatted for
+  /// one processor on a processor that uses a different format. Software can
+  /// discover the MSEG revision identifier that a processor uses by reading
+  /// the VMX capability MSR IA32_VMX_MISC.
+  //
+  UINT32  MsegHeaderRevision;
+  ///
+  /// Bits 31:1 of this field are reserved and must be zero. Bit 0 of the field
+  /// is the IA-32e mode SMM feature bit. It indicates whether the logical
+  /// processor will be in IA-32e mode after the STM is activated.
+  ///
+  UINT32  MonitorFeatures;
+  UINT32  GdtrLimit;
+  UINT32  GdtrBaseOffset;
+  UINT32  CsSelector;
+  UINT32  EipOffset;
+  UINT32  EspOffset;
+  UINT32  Cr3Offset;
+  ///
+  /// Pad header so total size is 2KB
+  ///
+  UINT8   Reserved[SIZE_2KB - 8 * sizeof (UINT32)];
+} MSEG_HEADER;
+
+///
+/// @{ Define values for the MonitorFeatures field of #MSEG_HEADER
+///
+#define STM_FEATURES_IA32E 0x1
+///
+/// @}
+///
+
+/**
+  Base address of the logical processor's SMRAM image (RO, SMM only). If
+  IA32_VMX_MISC[15].
+
+  @param  ECX  MSR_IA32_SMBASE (0x0000009E)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_SMBASE);
+  @endcode
+  @note MSR_IA32_SMBASE is defined as IA32_SMBASE in SDM.
+**/
+#define MSR_IA32_SMBASE                          0x0000009E
+
+
+/**
+  General Performance Counters (R/W).
+  MSR_IA32_PMCn is supported if CPUID.0AH: EAX[15:8] > n.
+
+  @param  ECX  MSR_IA32_PMCn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_PMC0);
+  AsmWriteMsr64 (MSR_IA32_PMC0, Msr);
+  @endcode
+  @note MSR_IA32_PMC0 is defined as IA32_PMC0 in SDM.
+        MSR_IA32_PMC1 is defined as IA32_PMC1 in SDM.
+        MSR_IA32_PMC2 is defined as IA32_PMC2 in SDM.
+        MSR_IA32_PMC3 is defined as IA32_PMC3 in SDM.
+        MSR_IA32_PMC4 is defined as IA32_PMC4 in SDM.
+        MSR_IA32_PMC5 is defined as IA32_PMC5 in SDM.
+        MSR_IA32_PMC6 is defined as IA32_PMC6 in SDM.
+        MSR_IA32_PMC7 is defined as IA32_PMC7 in SDM.
+  @{
+**/
+#define MSR_IA32_PMC0                            0x000000C1
+#define MSR_IA32_PMC1                            0x000000C2
+#define MSR_IA32_PMC2                            0x000000C3
+#define MSR_IA32_PMC3                            0x000000C4
+#define MSR_IA32_PMC4                            0x000000C5
+#define MSR_IA32_PMC5                            0x000000C6
+#define MSR_IA32_PMC6                            0x000000C7
+#define MSR_IA32_PMC7                            0x000000C8
+/// @}
+
+
+/**
+  TSC Frequency Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] = 1.
+  C0_MCNT: C0 TSC Frequency Clock Count Increments at fixed interval (relative
+  to TSC freq.) when the logical processor is in C0. Cleared upon overflow /
+  wrap-around of IA32_APERF.
+
+  @param  ECX  MSR_IA32_MPERF (0x000000E7)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_MPERF);
+  AsmWriteMsr64 (MSR_IA32_MPERF, Msr);
+  @endcode
+  @note MSR_IA32_MPERF is defined as IA32_MPERF in SDM.
+**/
+#define MSR_IA32_MPERF                           0x000000E7
+
+
+/**
+  Actual Performance Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] =
+  1. C0_ACNT: C0 Actual Frequency Clock Count Accumulates core clock counts at
+  the coordinated clock frequency, when the logical processor is in C0.
+  Cleared upon overflow / wrap-around of IA32_MPERF.
+
+  @param  ECX  MSR_IA32_APERF (0x000000E8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_APERF);
+  AsmWriteMsr64 (MSR_IA32_APERF, Msr);
+  @endcode
+  @note MSR_IA32_APERF is defined as IA32_APERF in SDM.
+**/
+#define MSR_IA32_APERF                           0x000000E8
+
+
+/**
+  MTRR Capability (RO) Section 11.11.2.1, "IA32_MTRR_DEF_TYPE MSR.".
+  Introduced at Display Family / Display Model 06_01H.
+
+  @param  ECX  MSR_IA32_MTRRCAP (0x000000FE)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_MTRRCAP_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_MTRRCAP_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_MTRRCAP_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRRCAP);
+  @endcode
+  @note MSR_IA32_MTRRCAP is defined as IA32_MTRRCAP in SDM.
+**/
+#define MSR_IA32_MTRRCAP                         0x000000FE
+
+/**
+  MSR information returned for MSR index #MSR_IA32_MTRRCAP
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] VCNT: The number of variable memory type ranges in the
+    /// processor.
+    ///
+    UINT32  VCNT:8;
+    ///
+    /// [Bit 8] Fixed range MTRRs are supported when set.
+    ///
+    UINT32  FIX:1;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 10] WC Supported when set.
+    ///
+    UINT32  WC:1;
+    ///
+    /// [Bit 11] SMRR Supported when set.
+    ///
+    UINT32  SMRR:1;
+    UINT32  Reserved2:20;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_MTRRCAP_REGISTER;
+
+
+/**
+  SYSENTER_CS_MSR (R/W). Introduced at Display Family / Display Model 06_01H.
+
+  @param  ECX  MSR_IA32_SYSENTER_CS (0x00000174)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_SYSENTER_CS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_SYSENTER_CS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_SYSENTER_CS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SYSENTER_CS);
+  AsmWriteMsr64 (MSR_IA32_SYSENTER_CS, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_SYSENTER_CS is defined as IA32_SYSENTER_CS in SDM.
+**/
+#define MSR_IA32_SYSENTER_CS                     0x00000174
+
+/**
+  MSR information returned for MSR index #MSR_IA32_SYSENTER_CS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 15:0] CS Selector.
+    ///
+    UINT32  CS:16;
+    UINT32  Reserved1:16;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_SYSENTER_CS_REGISTER;
+
+
+/**
+  SYSENTER_ESP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.
+
+  @param  ECX  MSR_IA32_SYSENTER_ESP (0x00000175)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_ESP);
+  AsmWriteMsr64 (MSR_IA32_SYSENTER_ESP, Msr);
+  @endcode
+  @note MSR_IA32_SYSENTER_ESP is defined as IA32_SYSENTER_ESP in SDM.
+**/
+#define MSR_IA32_SYSENTER_ESP                    0x00000175
+
+
+/**
+  SYSENTER_EIP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.
+
+  @param  ECX  MSR_IA32_SYSENTER_EIP (0x00000176)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_EIP);
+  AsmWriteMsr64 (MSR_IA32_SYSENTER_EIP, Msr);
+  @endcode
+  @note MSR_IA32_SYSENTER_EIP is defined as IA32_SYSENTER_EIP in SDM.
+**/
+#define MSR_IA32_SYSENTER_EIP                    0x00000176
+
+
+/**
+  Global Machine Check Capability (RO). Introduced at Display Family / Display
+  Model 06_01H.
+
+  @param  ECX  MSR_IA32_MCG_CAP (0x00000179)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_MCG_CAP_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_MCG_CAP_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_MCG_CAP_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);
+  @endcode
+  @note MSR_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.
+**/
+#define MSR_IA32_MCG_CAP                         0x00000179
+
+/**
+  MSR information returned for MSR index #MSR_IA32_MCG_CAP
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Count: Number of reporting banks.
+    ///
+    UINT32  Count:8;
+    ///
+    /// [Bit 8] MCG_CTL_P: IA32_MCG_CTL is present if this bit is set.
+    ///
+    UINT32  MCG_CTL_P:1;
+    ///
+    /// [Bit 9] MCG_EXT_P: Extended machine check state registers are present
+    /// if this bit is set.
+    ///
+    UINT32  MCG_EXT_P:1;
+    ///
+    /// [Bit 10] MCP_CMCI_P: Support for corrected MC error event is present.
+    /// Introduced at Display Family / Display Model 06_01H.
+    ///
+    UINT32  MCP_CMCI_P:1;
+    ///
+    /// [Bit 11] MCG_TES_P: Threshold-based error status register are present
+    /// if this bit is set.
+    ///
+    UINT32  MCG_TES_P:1;
+    UINT32  Reserved1:4;
+    ///
+    /// [Bits 23:16] MCG_EXT_CNT: Number of extended machine check state
+    /// registers present.
+    ///
+    UINT32  MCG_EXT_CNT:8;
+    ///
+    /// [Bit 24] MCG_SER_P: The processor supports software error recovery if
+    /// this bit is set.
+    ///
+    UINT32  MCG_SER_P:1;
+    UINT32  Reserved2:1;
+    ///
+    /// [Bit 26] MCG_ELOG_P: Indicates that the processor allows platform
+    /// firmware to be invoked when an error is detected so that it may
+    /// provide additional platform specific information in an ACPI format
+    /// "Generic Error Data Entry" that augments the data included in machine
+    /// check bank registers. Introduced at Display Family / Display Model
+    /// 06_3EH.
+    ///
+    UINT32  MCG_ELOG_P:1;
+    ///
+    /// [Bit 27] MCG_LMCE_P: Indicates that the processor support extended
+    /// state in IA32_MCG_STATUS and associated MSR necessary to configure
+    /// Local Machine Check Exception (LMCE). Introduced at Display Family /
+    /// Display Model 06_3EH.
+    ///
+    UINT32  MCG_LMCE_P:1;
+    UINT32  Reserved3:4;
+    UINT32  Reserved4:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_MCG_CAP_REGISTER;
+
+
+/**
+  Global Machine Check Status (R/W0). Introduced at Display Family / Display
+  Model 06_01H.
+
+  @param  ECX  MSR_IA32_MCG_STATUS (0x0000017A)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_MCG_STATUS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_MCG_STATUS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_MCG_STATUS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_STATUS);
+  AsmWriteMsr64 (MSR_IA32_MCG_STATUS, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_MCG_STATUS is defined as IA32_MCG_STATUS in SDM.
+**/
+#define MSR_IA32_MCG_STATUS                      0x0000017A
+
+/**
+  MSR information returned for MSR index #MSR_IA32_MCG_STATUS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] RIPV. Restart IP valid. Introduced at Display Family / Display
+    /// Model 06_01H.
+    ///
+    UINT32  RIPV:1;
+    ///
+    /// [Bit 1] EIPV. Error IP valid. Introduced at Display Family / Display
+    /// Model 06_01H.
+    ///
+    UINT32  EIPV:1;
+    ///
+    /// [Bit 2] MCIP. Machine check in progress. Introduced at Display Family
+    /// / Display Model 06_01H.
+    ///
+    UINT32  MCIP:1;
+    ///
+    /// [Bit 3] LMCE_S. If IA32_MCG_CAP.LMCE_P[2 7] =1.
+    ///
+    UINT32  LMCE_S:1;
+    UINT32  Reserved1:28;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_MCG_STATUS_REGISTER;
+
+
+/**
+  Global Machine Check Control (R/W). If IA32_MCG_CAP.CTL_P[8] =1.
+
+  @param  ECX  MSR_IA32_MCG_CTL (0x0000017B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_MCG_CTL);
+  AsmWriteMsr64 (MSR_IA32_MCG_CTL, Msr);
+  @endcode
+  @note MSR_IA32_MCG_CTL is defined as IA32_MCG_CTL in SDM.
+**/
+#define MSR_IA32_MCG_CTL                         0x0000017B
+
+
+/**
+  Performance Event Select Register n (R/W). If CPUID.0AH: EAX[15:8] > n.
+
+  @param  ECX  MSR_IA32_PERFEVTSELn
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_PERFEVTSEL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_PERFEVTSEL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_PERFEVTSEL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERFEVTSEL0);
+  AsmWriteMsr64 (MSR_IA32_PERFEVTSEL0, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM.
+        MSR_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM.
+        MSR_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM.
+        MSR_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.
+  @{
+**/
+#define MSR_IA32_PERFEVTSEL0                     0x00000186
+#define MSR_IA32_PERFEVTSEL1                     0x00000187
+#define MSR_IA32_PERFEVTSEL2                     0x00000188
+#define MSR_IA32_PERFEVTSEL3                     0x00000189
+/// @}
+
+/**
+  MSR information returned for MSR indexes #MSR_IA32_PERFEVTSEL0 to
+  #MSR_IA32_PERFEVTSEL3
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Event Select: Selects a performance event logic unit.
+    ///
+    UINT32  EventSelect:8;
+    ///
+    /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to
+    /// detect on the selected event logic.
+    ///
+    UINT32  UMASK:8;
+    ///
+    /// [Bit 16] USR: Counts while in privilege level is not ring 0.
+    ///
+    UINT32  USR:1;
+    ///
+    /// [Bit 17] OS: Counts while in privilege level is ring 0.
+    ///
+    UINT32  OS:1;
+    ///
+    /// [Bit 18] Edge: Enables edge detection if set.
+    ///
+    UINT32  E:1;
+    ///
+    /// [Bit 19] PC: enables pin control.
+    ///
+    UINT32  PC:1;
+    ///
+    /// [Bit 20] INT: enables interrupt on counter overflow.
+    ///
+    UINT32  INT:1;
+    ///
+    /// [Bit 21] AnyThread: When set to 1, it enables counting the associated
+    /// event conditions occurring across all logical processors sharing a
+    /// processor core. When set to 0, the counter only increments the
+    /// associated event conditions occurring in the logical processor which
+    /// programmed the MSR.
+    ///
+    UINT32  ANY:1;
+    ///
+    /// [Bit 22] EN: enables the corresponding performance counter to commence
+    /// counting when this bit is set.
+    ///
+    UINT32  EN:1;
+    ///
+    /// [Bit 23] INV: invert the CMASK.
+    ///
+    UINT32  INV:1;
+    ///
+    /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding
+    /// performance counter increments each cycle if the event count is
+    /// greater than or equal to the CMASK.
+    ///
+    UINT32  CMASK:8;
+    UINT32  Reserved:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_PERFEVTSEL_REGISTER;
+
+
+/**
+  Current performance state(P-State) operating point (RO). Introduced at
+  Display Family / Display Model 0F_03H.
+
+  @param  ECX  MSR_IA32_PERF_STATUS (0x00000198)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_PERF_STATUS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_PERF_STATUS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_PERF_STATUS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_STATUS);
+  @endcode
+  @note MSR_IA32_PERF_STATUS is defined as IA32_PERF_STATUS in SDM.
+**/
+#define MSR_IA32_PERF_STATUS                     0x00000198
+
+/**
+  MSR information returned for MSR index #MSR_IA32_PERF_STATUS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 15:0] Current performance State Value.
+    ///
+    UINT32  State:16;
+    UINT32  Reserved1:16;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_PERF_STATUS_REGISTER;
+
+
+/**
+  (R/W). Introduced at Display Family / Display Model 0F_03H.
+
+  @param  ECX  MSR_IA32_PERF_CTL (0x00000199)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_PERF_CTL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_PERF_CTL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_PERF_CTL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CTL);
+  AsmWriteMsr64 (MSR_IA32_PERF_CTL, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_PERF_CTL is defined as IA32_PERF_CTL in SDM.
+**/
+#define MSR_IA32_PERF_CTL                        0x00000199
+
+/**
+  MSR information returned for MSR index #MSR_IA32_PERF_CTL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 15:0] Target performance State Value.
+    ///
+    UINT32  TargetState:16;
+    UINT32  Reserved1:16;
+    ///
+    /// [Bit 32] IDA Engage. (R/W) When set to 1: disengages IDA. 06_0FH
+    /// (Mobile only).
+    ///
+    UINT32  IDA:1;
+    UINT32  Reserved2:31;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_PERF_CTL_REGISTER;
+
+
+/**
+  Clock Modulation Control (R/W) See Section 14.7.3, "Software Controlled
+  Clock Modulation.". If CPUID.01H:EDX[22] = 1.
+
+  @param  ECX  MSR_IA32_CLOCK_MODULATION (0x0000019A)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_CLOCK_MODULATION_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_CLOCK_MODULATION);
+  AsmWriteMsr64 (MSR_IA32_CLOCK_MODULATION, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM.
+**/
+#define MSR_IA32_CLOCK_MODULATION                0x0000019A
+
+/**
+  MSR information returned for MSR index #MSR_IA32_CLOCK_MODULATION
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Extended On-Demand Clock Modulation Duty Cycle:. If
+    /// CPUID.06H:EAX[5] = 1.
+    ///
+    UINT32  ExtendedOnDemandClockModulationDutyCycle:1;
+    ///
+    /// [Bits 3:1] On-Demand Clock Modulation Duty Cycle: Specific encoded
+    /// values for target duty cycle modulation. If CPUID.01H:EDX[22] = 1.
+    ///
+    UINT32  OnDemandClockModulationDutyCycle:3;
+    ///
+    /// [Bit 4] On-Demand Clock Modulation Enable: Set 1 to enable modulation.
+    /// If CPUID.01H:EDX[22] = 1.
+    ///
+    UINT32  OnDemandClockModulationEnable:1;
+    UINT32  Reserved1:27;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_CLOCK_MODULATION_REGISTER;
+
+
+/**
+  Thermal Interrupt Control (R/W) Enables and disables the generation of an
+  interrupt on temperature transitions detected with the processor's thermal
+  sensors and thermal monitor. See Section 14.7.2, "Thermal Monitor.".
+  If CPUID.01H:EDX[22] = 1
+
+  @param  ECX  MSR_IA32_THERM_INTERRUPT (0x0000019B)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_THERM_INTERRUPT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_INTERRUPT);
+  AsmWriteMsr64 (MSR_IA32_THERM_INTERRUPT, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_THERM_INTERRUPT is defined as IA32_THERM_INTERRUPT in SDM.
+**/
+#define MSR_IA32_THERM_INTERRUPT                 0x0000019B
+
+/**
+  MSR information returned for MSR index #MSR_IA32_THERM_INTERRUPT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] High-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.
+    ///
+    UINT32  HighTempEnable:1;
+    ///
+    /// [Bit 1] Low-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.
+    ///
+    UINT32  LowTempEnable:1;
+    ///
+    /// [Bit 2] PROCHOT# Interrupt Enable. If CPUID.01H:EDX[22] = 1.
+    ///
+    UINT32  PROCHOT_Enable:1;
+    ///
+    /// [Bit 3] FORCEPR# Interrupt Enable. If CPUID.01H:EDX[22] = 1.
+    ///
+    UINT32  FORCEPR_Enable:1;
+    ///
+    /// [Bit 4] Critical Temperature Interrupt Enable.
+    /// If CPUID.01H:EDX[22] = 1.
+    ///
+    UINT32  CriticalTempEnable:1;
+    UINT32  Reserved1:3;
+    ///
+    /// [Bits 14:8] Threshold #1 Value. If CPUID.01H:EDX[22] = 1.
+    ///
+    UINT32  Threshold1:7;
+    ///
+    /// [Bit 15] Threshold #1 Interrupt Enable. If CPUID.01H:EDX[22] = 1.
+    ///
+    UINT32  Threshold1Enable:1;
+    ///
+    /// [Bits 22:16] Threshold #2 Value. If CPUID.01H:EDX[22] = 1.
+    ///
+    UINT32  Threshold2:7;
+    ///
+    /// [Bit 23] Threshold #2 Interrupt Enable. If CPUID.01H:EDX[22] = 1.
+    ///
+    UINT32  Threshold2Enable:1;
+    ///
+    /// [Bit 24] Power Limit Notification Enable. If CPUID.06H:EAX[4] = 1.
+    ///
+    UINT32  PowerLimitNotificationEnable:1;
+    UINT32  Reserved2:7;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_THERM_INTERRUPT_REGISTER;
+
+
+/**
+  Thermal Status Information (RO) Contains status information about the
+  processor's thermal sensor and automatic thermal monitoring facilities. See
+  Section 14.7.2, "Thermal Monitor". If CPUID.01H:EDX[22] = 1.
+
+  @param  ECX  MSR_IA32_THERM_STATUS (0x0000019C)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_THERM_STATUS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_THERM_STATUS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_THERM_STATUS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_STATUS);
+  @endcode
+  @note MSR_IA32_THERM_STATUS is defined as IA32_THERM_STATUS in SDM.
+**/
+#define MSR_IA32_THERM_STATUS                    0x0000019C
+
+/**
+  MSR information returned for MSR index #MSR_IA32_THERM_STATUS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Thermal Status (RO):. If CPUID.01H:EDX[22] = 1.
+    ///
+    UINT32  ThermalStatus:1;
+    ///
+    /// [Bit 1] Thermal Status Log (R/W):. If CPUID.01H:EDX[22] = 1.
+    ///
+    UINT32  ThermalStatusLog:1;
+    ///
+    /// [Bit 2] PROCHOT # or FORCEPR# event (RO). If CPUID.01H:EDX[22] = 1.
+    ///
+    UINT32  PROCHOT_FORCEPR_Event:1;
+    ///
+    /// [Bit 3] PROCHOT # or FORCEPR# log (R/WC0). If CPUID.01H:EDX[22] = 1.
+    ///
+    UINT32  PROCHOT_FORCEPR_Log:1;
+    ///
+    /// [Bit 4] Critical Temperature Status (RO). If CPUID.01H:EDX[22] = 1.
+    ///
+    UINT32  CriticalTempStatus:1;
+    ///
+    /// [Bit 5] Critical Temperature Status log (R/WC0).
+    /// If CPUID.01H:EDX[22] = 1.
+    ///
+    UINT32  CriticalTempStatusLog:1;
+    ///
+    /// [Bit 6] Thermal Threshold #1 Status (RO). If CPUID.01H:ECX[8] = 1.
+    ///
+    UINT32  ThermalThreshold1Status:1;
+    ///
+    /// [Bit 7] Thermal Threshold #1 log (R/WC0). If CPUID.01H:ECX[8] = 1.
+    ///
+    UINT32  ThermalThreshold1Log:1;
+    ///
+    /// [Bit 8] Thermal Threshold #2 Status (RO). If CPUID.01H:ECX[8] = 1.
+    ///
+    UINT32  ThermalThreshold2Status:1;
+    ///
+    /// [Bit 9] Thermal Threshold #2 log (R/WC0). If CPUID.01H:ECX[8] = 1.
+    ///
+    UINT32  ThermalThreshold2Log:1;
+    ///
+    /// [Bit 10] Power Limitation Status (RO). If CPUID.06H:EAX[4] = 1.
+    ///
+    UINT32  PowerLimitStatus:1;
+    ///
+    /// [Bit 11] Power Limitation log (R/WC0). If CPUID.06H:EAX[4] = 1.
+    ///
+    UINT32  PowerLimitLog:1;
+    ///
+    /// [Bit 12] Current Limit Status (RO). If CPUID.06H:EAX[7] = 1.
+    ///
+    UINT32  CurrentLimitStatus:1;
+    ///
+    /// [Bit 13] Current Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.
+    ///
+    UINT32  CurrentLimitLog:1;
+    ///
+    /// [Bit 14] Cross Domain Limit Status (RO). If CPUID.06H:EAX[7] = 1.
+    ///
+    UINT32  CrossDomainLimitStatus:1;
+    ///
+    /// [Bit 15] Cross Domain Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.
+    ///
+    UINT32  CrossDomainLimitLog:1;
+    ///
+    /// [Bits 22:16] Digital Readout (RO). If CPUID.06H:EAX[0] = 1.
+    ///
+    UINT32  DigitalReadout:7;
+    UINT32  Reserved1:4;
+    ///
+    /// [Bits 30:27] Resolution in Degrees Celsius (RO). If CPUID.06H:EAX[0] =
+    /// 1.
+    ///
+    UINT32  ResolutionInDegreesCelsius:4;
+    ///
+    /// [Bit 31] Reading Valid (RO). If CPUID.06H:EAX[0] = 1.
+    ///
+    UINT32  ReadingValid:1;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_THERM_STATUS_REGISTER;
+
+
+/**
+  Enable Misc. Processor Features (R/W)  Allows a variety of processor
+  functions to be enabled and disabled.
+
+  @param  ECX  MSR_IA32_MISC_ENABLE (0x000001A0)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_MISC_ENABLE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_MISC_ENABLE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_MISC_ENABLE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE);
+  AsmWriteMsr64 (MSR_IA32_MISC_ENABLE, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
+**/
+#define MSR_IA32_MISC_ENABLE                     0x000001A0
+
+/**
+  MSR information returned for MSR index #MSR_IA32_MISC_ENABLE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Fast-Strings Enable When set, the fast-strings feature (for
+    /// REP MOVS and REP STORS) is enabled (default); when clear, fast-strings
+    /// are disabled. Introduced at Display Family / Display Model 0F_0H.
+    ///
+    UINT32  FastStrings:1;
+    UINT32  Reserved1:2;
+    ///
+    /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W)  1 = Setting
+    /// this bit enables the thermal control circuit (TCC) portion of the
+    /// Intel Thermal Monitor feature. This allows the processor to
+    /// automatically reduce power consumption in response to TCC activation.
+    /// 0 = Disabled. Note: In some products clearing this bit might be
+    /// ignored in critical thermal conditions, and TM1, TM2 and adaptive
+    /// thermal throttling will still be activated. The default value of this
+    /// field varies with product. See respective tables where default value is
+    /// listed. Introduced at Display Family / Display Model 0F_0H.
+    ///
+    UINT32  AutomaticThermalControlCircuit:1;
+    UINT32  Reserved2:3;
+    ///
+    /// [Bit 7] Performance Monitoring Available (R)  1 = Performance
+    /// monitoring enabled 0 = Performance monitoring disabled. Introduced at
+    /// Display Family / Display Model 0F_0H.
+    ///
+    UINT32  PerformanceMonitoring:1;
+    UINT32  Reserved3:3;
+    ///
+    /// [Bit 11] Branch Trace Storage Unavailable (RO) 1 = Processor doesn't
+    /// support branch trace storage (BTS) 0 = BTS is supported. Introduced at
+    /// Display Family / Display Model 0F_0H.
+    ///
+    UINT32  BTS:1;
+    ///
+    /// [Bit 12] Processor Event Based Sampling (PEBS)  Unavailable (RO)  1 =
+    /// PEBS is not supported; 0 = PEBS is supported. Introduced at Display
+    /// Family / Display Model 06_0FH.
+    ///
+    UINT32  PEBS:1;
+    UINT32  Reserved4:3;
+    ///
+    /// [Bit 16] Enhanced Intel SpeedStep Technology  Enable (R/W) 0= Enhanced
+    /// Intel SpeedStep Technology disabled 1 = Enhanced Intel SpeedStep
+    /// Technology enabled. If CPUID.01H: ECX[7] =1.
+    ///
+    UINT32  EIST:1;
+    UINT32  Reserved5:1;
+    ///
+    /// [Bit 18] ENABLE MONITOR FSM (R/W) When this bit is set to 0, the
+    /// MONITOR feature flag is not set (CPUID.01H:ECX[bit 3] = 0). This
+    /// indicates that MONITOR/MWAIT are not supported. Software attempts to
+    /// execute MONITOR/MWAIT will cause #UD when this bit is 0. When this bit
+    /// is set to 1 (default), MONITOR/MWAIT are supported (CPUID.01H:ECX[bit
+    /// 3] = 1). If the SSE3 feature flag ECX[0] is not set (CPUID.01H:ECX[bit
+    /// 0] = 0), the OS must not attempt to alter this bit. BIOS must leave it
+    /// in the default state. Writing this bit when the SSE3 feature flag is
+    /// set to 0 may generate a #GP exception. Introduced at Display Family /
+    /// Display Model 0F_03H.
+    ///
+    UINT32  MONITOR:1;
+    UINT32  Reserved6:3;
+    ///
+    /// [Bit 22] Limit CPUID Maxval (R/W) When this bit is set to 1, CPUID.00H
+    /// returns a maximum value in EAX[7:0] of 2. BIOS should contain a setup
+    /// question that allows users to specify when the installed OS does not
+    /// support CPUID functions greater than 2. Before setting this bit, BIOS
+    /// must execute the CPUID.0H and examine the maximum value returned in
+    /// EAX[7:0]. If the maximum value is greater than 2, this bit is
+    /// supported. Otherwise, this bit is not supported. Setting this bit when
+    /// the maximum value is not greater than 2 may generate a #GP exception.
+    /// Setting this bit may cause unexpected behavior in software that
+    /// depends on the availability of CPUID leaves greater than 2. Introduced
+    /// at Display Family / Display Model 0F_03H.
+    ///
+    UINT32  LimitCpuidMaxval:1;
+    ///
+    /// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are
+    /// disabled. xTPR messages are optional messages that allow the processor
+    /// to inform the chipset of its priority. if CPUID.01H:ECX[14] = 1.
+    ///
+    UINT32  xTPR_Message_Disable:1;
+    UINT32  Reserved7:8;
+    UINT32  Reserved8:2;
+    ///
+    /// [Bit 34] XD Bit Disable (R/W) When set to 1, the Execute Disable Bit
+    /// feature (XD Bit) is disabled and the XD Bit extended feature flag will
+    /// be clear (CPUID.80000001H: EDX[20]=0). When set to a 0 (default), the
+    /// Execute Disable Bit feature (if available) allows the OS to enable PAE
+    /// paging and take advantage of data only pages. BIOS must not alter the
+    /// contents of this bit location, if XD bit is not supported. Writing
+    /// this bit to 1 when the XD Bit extended feature flag is set to 0 may
+    /// generate a #GP exception. if CPUID.80000001H:EDX[2 0] = 1.
+    ///
+    UINT32  XD:1;
+    UINT32  Reserved9:29;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_MISC_ENABLE_REGISTER;
+
+
+/**
+  Performance Energy Bias Hint (R/W). if CPUID.6H:ECX[3] = 1.
+
+  @param  ECX  MSR_IA32_ENERGY_PERF_BIAS (0x000001B0)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_ENERGY_PERF_BIAS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_ENERGY_PERF_BIAS);
+  AsmWriteMsr64 (MSR_IA32_ENERGY_PERF_BIAS, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.
+**/
+#define MSR_IA32_ENERGY_PERF_BIAS                0x000001B0
+
+/**
+  MSR information returned for MSR index #MSR_IA32_ENERGY_PERF_BIAS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 3:0] Power Policy Preference: 0 indicates preference to highest
+    /// performance. 15 indicates preference to maximize energy saving.
+    ///
+    UINT32  PowerPolicyPreference:4;
+    UINT32  Reserved1:28;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_ENERGY_PERF_BIAS_REGISTER;
+
+
+/**
+  Package Thermal Status Information (RO) Contains status information about
+  the package's thermal sensor. See Section 14.8, "Package Level Thermal
+  Management.". If CPUID.06H: EAX[6] = 1.
+
+  @param  ECX  MSR_IA32_PACKAGE_THERM_STATUS (0x000001B1)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_PACKAGE_THERM_STATUS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_STATUS);
+  @endcode
+  @note MSR_IA32_PACKAGE_THERM_STATUS is defined as IA32_PACKAGE_THERM_STATUS in SDM.
+**/
+#define MSR_IA32_PACKAGE_THERM_STATUS            0x000001B1
+
+/**
+  MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_STATUS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Pkg Thermal Status (RO):.
+    ///
+    UINT32  ThermalStatus:1;
+    ///
+    /// [Bit 1] Pkg Thermal Status Log (R/W):.
+    ///
+    UINT32  ThermalStatusLog:1;
+    ///
+    /// [Bit 2] Pkg PROCHOT # event (RO).
+    ///
+    UINT32  PROCHOT_Event:1;
+    ///
+    /// [Bit 3] Pkg PROCHOT # log (R/WC0).
+    ///
+    UINT32  PROCHOT_Log:1;
+    ///
+    /// [Bit 4] Pkg Critical Temperature Status (RO).
+    ///
+    UINT32  CriticalTempStatus:1;
+    ///
+    /// [Bit 5] Pkg Critical Temperature Status log (R/WC0).
+    ///
+    UINT32  CriticalTempStatusLog:1;
+    ///
+    /// [Bit 6] Pkg Thermal Threshold #1 Status (RO).
+    ///
+    UINT32  ThermalThreshold1Status:1;
+    ///
+    /// [Bit 7] Pkg Thermal Threshold #1 log (R/WC0).
+    ///
+    UINT32  ThermalThreshold1Log:1;
+    ///
+    /// [Bit 8] Pkg Thermal Threshold #2 Status (RO).
+    ///
+    UINT32  ThermalThreshold2Status:1;
+    ///
+    /// [Bit 9] Pkg Thermal Threshold #1 log (R/WC0).
+    ///
+    UINT32  ThermalThreshold2Log:1;
+    ///
+    /// [Bit 10] Pkg Power Limitation Status (RO).
+    ///
+    UINT32  PowerLimitStatus:1;
+    ///
+    /// [Bit 11] Pkg Power Limitation log (R/WC0).
+    ///
+    UINT32  PowerLimitLog:1;
+    UINT32  Reserved1:4;
+    ///
+    /// [Bits 22:16] Pkg Digital Readout (RO).
+    ///
+    UINT32  DigitalReadout:7;
+    UINT32  Reserved2:9;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_PACKAGE_THERM_STATUS_REGISTER;
+
+
+/**
+  Pkg Thermal Interrupt Control (R/W) Enables and disables the generation of
+  an interrupt on temperature transitions detected with the package's thermal
+  sensor. See Section 14.8, "Package Level Thermal Management.". If CPUID.06H:
+  EAX[6] = 1.
+
+  @param  ECX  MSR_IA32_PACKAGE_THERM_INTERRUPT (0x000001B2)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT);
+  AsmWriteMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_PACKAGE_THERM_INTERRUPT is defined as IA32_PACKAGE_THERM_INTERRUPT in SDM.
+**/
+#define MSR_IA32_PACKAGE_THERM_INTERRUPT         0x000001B2
+
+/**
+  MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_INTERRUPT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Pkg High-Temperature Interrupt Enable.
+    ///
+    UINT32  HighTempEnable:1;
+    ///
+    /// [Bit 1] Pkg Low-Temperature Interrupt Enable.
+    ///
+    UINT32  LowTempEnable:1;
+    ///
+    /// [Bit 2] Pkg PROCHOT# Interrupt Enable.
+    ///
+    UINT32  PROCHOT_Enable:1;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 4] Pkg Overheat Interrupt Enable.
+    ///
+    UINT32  OverheatEnable:1;
+    UINT32  Reserved2:3;
+    ///
+    /// [Bits 14:8] Pkg Threshold #1 Value.
+    ///
+    UINT32  Threshold1:7;
+    ///
+    /// [Bit 15] Pkg Threshold #1 Interrupt Enable.
+    ///
+    UINT32  Threshold1Enable:1;
+    ///
+    /// [Bits 22:16] Pkg Threshold #2 Value.
+    ///
+    UINT32  Threshold2:7;
+    ///
+    /// [Bit 23] Pkg Threshold #2 Interrupt Enable.
+    ///
+    UINT32  Threshold2Enable:1;
+    ///
+    /// [Bit 24] Pkg Power Limit Notification Enable.
+    ///
+    UINT32  PowerLimitNotificationEnable:1;
+    UINT32  Reserved3:7;
+    UINT32  Reserved4:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER;
+
+
+/**
+  Trace/Profile Resource Control (R/W). Introduced at Display Family / Display
+  Model 06_0EH.
+
+  @param  ECX  MSR_IA32_DEBUGCTL (0x000001D9)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_DEBUGCTL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_DEBUGCTL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_DEBUGCTL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUGCTL);
+  AsmWriteMsr64 (MSR_IA32_DEBUGCTL, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_DEBUGCTL is defined as IA32_DEBUGCTL in SDM.
+**/
+#define MSR_IA32_DEBUGCTL                        0x000001D9
+
+/**
+  MSR information returned for MSR index #MSR_IA32_DEBUGCTL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] LBR: Setting this bit to 1 enables the processor to record a
+    /// running trace of the most recent branches taken by the processor in
+    /// the LBR stack. Introduced at Display Family / Display Model 06_01H.
+    ///
+    UINT32  LBR:1;
+    ///
+    /// [Bit 1] BTF: Setting this bit to 1 enables the processor to treat
+    /// EFLAGS.TF as single-step on branches instead of single-step on
+    /// instructions. Introduced at Display Family / Display Model 06_01H.
+    ///
+    UINT32  BTF:1;
+    UINT32  Reserved1:4;
+    ///
+    /// [Bit 6] TR: Setting this bit to 1 enables branch trace messages to be
+    /// sent. Introduced at Display Family / Display Model 06_0EH.
+    ///
+    UINT32  TR:1;
+    ///
+    /// [Bit 7] BTS: Setting this bit enables branch trace messages (BTMs) to
+    /// be logged in a BTS buffer. Introduced at Display Family / Display
+    /// Model 06_0EH.
+    ///
+    UINT32  BTS:1;
+    ///
+    /// [Bit 8] BTINT: When clear, BTMs are logged in a BTS buffer in circular
+    /// fashion. When this bit is set, an interrupt is generated by the BTS
+    /// facility when the BTS buffer is full. Introduced at Display Family /
+    /// Display Model 06_0EH.
+    ///
+    UINT32  BTINT:1;
+    ///
+    /// [Bit 9] BTS_OFF_OS: When set, BTS or BTM is skipped if CPL = 0.
+    /// Introduced at Display Family / Display Model 06_0FH.
+    ///
+    UINT32  BTS_OFF_OS:1;
+    ///
+    /// [Bit 10] BTS_OFF_USR: When set, BTS or BTM is skipped if CPL > 0.
+    /// Introduced at Display Family / Display Model 06_0FH.
+    ///
+    UINT32  BTS_OFF_USR:1;
+    ///
+    /// [Bit 11] FREEZE_LBRS_ON_PMI: When set, the LBR stack is frozen on a
+    /// PMI request. If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.
+    ///
+    UINT32  FREEZE_LBRS_ON_PMI:1;
+    ///
+    /// [Bit 12] FREEZE_PERFMON_ON_PMI: When set, each ENABLE bit of the
+    /// global counter control MSR are frozen (address 38FH) on a PMI request.
+    /// If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.
+    ///
+    UINT32  FREEZE_PERFMON_ON_PMI:1;
+    ///
+    /// [Bit 13] ENABLE_UNCORE_PMI: When set, enables the logical processor to
+    /// receive and generate PMI on behalf of the uncore. Introduced at
+    /// Display Family / Display Model 06_1AH.
+    ///
+    UINT32  ENABLE_UNCORE_PMI:1;
+    ///
+    /// [Bit 14] FREEZE_WHILE_SMM: When set, freezes perfmon and trace
+    /// messages while in SMM. If IA32_PERF_CAPABILITIES[ 12] = 1.
+    ///
+    UINT32  FREEZE_WHILE_SMM:1;
+    ///
+    /// [Bit 15] RTM_DEBUG: When set, enables DR7 debug bit on XBEGIN. If
+    /// (CPUID.(EAX=07H, ECX=0):EBX[11] = 1).
+    ///
+    UINT32  RTM_DEBUG:1;
+    UINT32  Reserved2:16;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_DEBUGCTL_REGISTER;
+
+
+/**
+  SMRR Base Address (Writeable only in SMM)  Base address of SMM memory range.
+  If IA32_MTRRCAP.SMRR[11] = 1.
+
+  @param  ECX  MSR_IA32_SMRR_PHYSBASE (0x000001F2)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_SMRR_PHYSBASE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSBASE);
+  AsmWriteMsr64 (MSR_IA32_SMRR_PHYSBASE, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_SMRR_PHYSBASE is defined as IA32_SMRR_PHYSBASE in SDM.
+**/
+#define MSR_IA32_SMRR_PHYSBASE                   0x000001F2
+
+/**
+  MSR information returned for MSR index #MSR_IA32_SMRR_PHYSBASE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Type. Specifies memory type of the range.
+    ///
+    UINT32  Type:8;
+    UINT32  Reserved1:4;
+    ///
+    /// [Bits 31:12] PhysBase.  SMRR physical Base Address.
+    ///
+    UINT32  PhysBase:20;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_SMRR_PHYSBASE_REGISTER;
+
+
+/**
+  SMRR Range Mask (Writeable only in SMM) Range Mask of SMM memory range. If
+  IA32_MTRRCAP[SMRR] = 1.
+
+  @param  ECX  MSR_IA32_SMRR_PHYSMASK (0x000001F3)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_SMRR_PHYSMASK_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSMASK);
+  AsmWriteMsr64 (MSR_IA32_SMRR_PHYSMASK, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_SMRR_PHYSMASK is defined as IA32_SMRR_PHYSMASK in SDM.
+**/
+#define MSR_IA32_SMRR_PHYSMASK                   0x000001F3
+
+/**
+  MSR information returned for MSR index #MSR_IA32_SMRR_PHYSMASK
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:11;
+    ///
+    /// [Bit 11] Valid Enable range mask.
+    ///
+    UINT32  Valid:1;
+    ///
+    /// [Bits 31:12] PhysMask SMRR address range mask.
+    ///
+    UINT32  PhysMask:20;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_SMRR_PHYSMASK_REGISTER;
+
+
+/**
+  DCA Capability (R). If CPUID.01H: ECX[18] = 1.
+
+  @param  ECX  MSR_IA32_PLATFORM_DCA_CAP (0x000001F8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_PLATFORM_DCA_CAP);
+  @endcode
+  @note MSR_IA32_PLATFORM_DCA_CAP is defined as IA32_PLATFORM_DCA_CAP in SDM.
+**/
+#define MSR_IA32_PLATFORM_DCA_CAP                0x000001F8
+
+
+/**
+  If set, CPU supports Prefetch-Hint type. If CPUID.01H: ECX[18] = 1.
+
+  @param  ECX  MSR_IA32_CPU_DCA_CAP (0x000001F9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_CPU_DCA_CAP);
+  AsmWriteMsr64 (MSR_IA32_CPU_DCA_CAP, Msr);
+  @endcode
+  @note MSR_IA32_CPU_DCA_CAP is defined as IA32_CPU_DCA_CAP in SDM.
+**/
+#define MSR_IA32_CPU_DCA_CAP                     0x000001F9
+
+
+/**
+  DCA type 0 Status and Control register. If CPUID.01H: ECX[18] = 1.
+
+  @param  ECX  MSR_IA32_DCA_0_CAP (0x000001FA)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_DCA_0_CAP_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_DCA_0_CAP_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_DCA_0_CAP_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DCA_0_CAP);
+  AsmWriteMsr64 (MSR_IA32_DCA_0_CAP, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_DCA_0_CAP is defined as IA32_DCA_0_CAP in SDM.
+**/
+#define MSR_IA32_DCA_0_CAP                       0x000001FA
+
+/**
+  MSR information returned for MSR index #MSR_IA32_DCA_0_CAP
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] DCA_ACTIVE: Set by HW when DCA is fuseenabled and no
+    /// defeatures are set.
+    ///
+    UINT32  DCA_ACTIVE:1;
+    ///
+    /// [Bits 2:1] TRANSACTION.
+    ///
+    UINT32  TRANSACTION:2;
+    ///
+    /// [Bits 6:3] DCA_TYPE.
+    ///
+    UINT32  DCA_TYPE:4;
+    ///
+    /// [Bits 10:7] DCA_QUEUE_SIZE.
+    ///
+    UINT32  DCA_QUEUE_SIZE:4;
+    UINT32  Reserved1:2;
+    ///
+    /// [Bits 16:13] DCA_DELAY: Writes will update the register but have no HW
+    /// side-effect.
+    ///
+    UINT32  DCA_DELAY:4;
+    UINT32  Reserved2:7;
+    ///
+    /// [Bit 24] SW_BLOCK: SW can request DCA block by setting this bit.
+    ///
+    UINT32  SW_BLOCK:1;
+    UINT32  Reserved3:1;
+    ///
+    /// [Bit 26] HW_BLOCK: Set when DCA is blocked by HW (e.g. CR0.CD = 1).
+    ///
+    UINT32  HW_BLOCK:1;
+    UINT32  Reserved4:5;
+    UINT32  Reserved5:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_DCA_0_CAP_REGISTER;
+
+
+/**
+  MTRRphysBasen.  See Section 11.11.2.3, "Variable Range MTRRs".
+  If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.
+
+  @param  ECX  MSR_IA32_MTRR_PHYSBASEn
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_MTRR_PHYSBASE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0);
+  AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_MTRR_PHYSBASE0 is defined as IA32_MTRR_PHYSBASE0 in SDM.
+        MSR_IA32_MTRR_PHYSBASE1 is defined as IA32_MTRR_PHYSBASE1 in SDM.
+        MSR_IA32_MTRR_PHYSBASE2 is defined as IA32_MTRR_PHYSBASE2 in SDM.
+        MSR_IA32_MTRR_PHYSBASE3 is defined as IA32_MTRR_PHYSBASE3 in SDM.
+        MSR_IA32_MTRR_PHYSBASE4 is defined as IA32_MTRR_PHYSBASE4 in SDM.
+        MSR_IA32_MTRR_PHYSBASE5 is defined as IA32_MTRR_PHYSBASE5 in SDM.
+        MSR_IA32_MTRR_PHYSBASE6 is defined as IA32_MTRR_PHYSBASE6 in SDM.
+        MSR_IA32_MTRR_PHYSBASE7 is defined as IA32_MTRR_PHYSBASE7 in SDM.
+        MSR_IA32_MTRR_PHYSBASE8 is defined as IA32_MTRR_PHYSBASE8 in SDM.
+        MSR_IA32_MTRR_PHYSBASE9 is defined as IA32_MTRR_PHYSBASE9 in SDM.
+  @{
+**/
+#define MSR_IA32_MTRR_PHYSBASE0                  0x00000200
+#define MSR_IA32_MTRR_PHYSBASE1                  0x00000202
+#define MSR_IA32_MTRR_PHYSBASE2                  0x00000204
+#define MSR_IA32_MTRR_PHYSBASE3                  0x00000206
+#define MSR_IA32_MTRR_PHYSBASE4                  0x00000208
+#define MSR_IA32_MTRR_PHYSBASE5                  0x0000020A
+#define MSR_IA32_MTRR_PHYSBASE6                  0x0000020C
+#define MSR_IA32_MTRR_PHYSBASE7                  0x0000020E
+#define MSR_IA32_MTRR_PHYSBASE8                  0x00000210
+#define MSR_IA32_MTRR_PHYSBASE9                  0x00000212
+/// @}
+
+/**
+  MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSBASE0 to
+  #MSR_IA32_MTRR_PHYSBASE9
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Type. Specifies memory type of the range.
+    ///
+    UINT32  Type:8;
+    UINT32  Reserved1:4;
+    ///
+    /// [Bits 31:12] PhysBase.  MTRR physical Base Address.
+    ///
+    UINT32  PhysBase:20;
+    ///
+    /// [Bits MAXPHYSADDR:32] PhysBase.  Upper bits of MTRR physical Base Address.
+    /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the
+    /// maximum physical address range supported by the processor. It is
+    /// reported by CPUID leaf function 80000008H. If CPUID does not support
+    /// leaf 80000008H, the processor supports 36-bit physical address size,
+    /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.
+    ///
+    UINT32  PhysBaseHi:32;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_MTRR_PHYSBASE_REGISTER;
+
+
+/**
+  MTRRphysMaskn.  See Section 11.11.2.3, "Variable Range MTRRs".
+  If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.
+
+  @param  ECX  MSR_IA32_MTRR_PHYSMASKn
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_MTRR_PHYSMASK_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0);
+  AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_MTRR_PHYSMASK0 is defined as IA32_MTRR_PHYSMASK0 in SDM.
+        MSR_IA32_MTRR_PHYSMASK1 is defined as IA32_MTRR_PHYSMASK1 in SDM.
+        MSR_IA32_MTRR_PHYSMASK2 is defined as IA32_MTRR_PHYSMASK2 in SDM.
+        MSR_IA32_MTRR_PHYSMASK3 is defined as IA32_MTRR_PHYSMASK3 in SDM.
+        MSR_IA32_MTRR_PHYSMASK4 is defined as IA32_MTRR_PHYSMASK4 in SDM.
+        MSR_IA32_MTRR_PHYSMASK5 is defined as IA32_MTRR_PHYSMASK5 in SDM.
+        MSR_IA32_MTRR_PHYSMASK6 is defined as IA32_MTRR_PHYSMASK6 in SDM.
+        MSR_IA32_MTRR_PHYSMASK7 is defined as IA32_MTRR_PHYSMASK7 in SDM.
+        MSR_IA32_MTRR_PHYSMASK8 is defined as IA32_MTRR_PHYSMASK8 in SDM.
+        MSR_IA32_MTRR_PHYSMASK9 is defined as IA32_MTRR_PHYSMASK9 in SDM.
+  @{
+**/
+#define MSR_IA32_MTRR_PHYSMASK0                  0x00000201
+#define MSR_IA32_MTRR_PHYSMASK1                  0x00000203
+#define MSR_IA32_MTRR_PHYSMASK2                  0x00000205
+#define MSR_IA32_MTRR_PHYSMASK3                  0x00000207
+#define MSR_IA32_MTRR_PHYSMASK4                  0x00000209
+#define MSR_IA32_MTRR_PHYSMASK5                  0x0000020B
+#define MSR_IA32_MTRR_PHYSMASK6                  0x0000020D
+#define MSR_IA32_MTRR_PHYSMASK7                  0x0000020F
+#define MSR_IA32_MTRR_PHYSMASK8                  0x00000211
+#define MSR_IA32_MTRR_PHYSMASK9                  0x00000213
+/// @}
+
+/**
+  MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSMASK0 to
+  #MSR_IA32_MTRR_PHYSMASK9
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:11;
+    ///
+    /// [Bit 11] Valid Enable range mask.
+    ///
+    UINT32  V:1;
+    ///
+    /// [Bits 31:12] PhysMask.  MTRR address range mask.
+    ///
+    UINT32  PhysMask:20;
+    ///
+    /// [Bits MAXPHYSADDR:32] PhysMask.  Upper bits of MTRR address range mask.
+    /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the
+    /// maximum physical address range supported by the processor. It is
+    /// reported by CPUID leaf function 80000008H. If CPUID does not support
+    /// leaf 80000008H, the processor supports 36-bit physical address size,
+    /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.
+    ///
+    UINT32  PhysMaskHi:32;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_MTRR_PHYSMASK_REGISTER;
+
+
+/**
+  MTRRfix64K_00000. If CPUID.01H: EDX.MTRR[12] =1.
+
+  @param  ECX  MSR_IA32_MTRR_FIX64K_00000 (0x00000250)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX64K_00000);
+  AsmWriteMsr64 (MSR_IA32_MTRR_FIX64K_00000, Msr);
+  @endcode
+  @note MSR_IA32_MTRR_FIX64K_00000 is defined as IA32_MTRR_FIX64K_00000 in SDM.
+**/
+#define MSR_IA32_MTRR_FIX64K_00000               0x00000250
+
+
+/**
+  MTRRfix16K_80000. If CPUID.01H: EDX.MTRR[12] =1.
+
+  @param  ECX  MSR_IA32_MTRR_FIX16K_80000 (0x00000258)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_80000);
+  AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_80000, Msr);
+  @endcode
+  @note MSR_IA32_MTRR_FIX16K_80000 is defined as IA32_MTRR_FIX16K_80000 in SDM.
+**/
+#define MSR_IA32_MTRR_FIX16K_80000               0x00000258
+
+
+/**
+  MTRRfix16K_A0000. If CPUID.01H: EDX.MTRR[12] =1.
+
+  @param  ECX  MSR_IA32_MTRR_FIX16K_A0000 (0x00000259)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_A0000);
+  AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_A0000, Msr);
+  @endcode
+  @note MSR_IA32_MTRR_FIX16K_A0000 is defined as IA32_MTRR_FIX16K_A0000 in SDM.
+**/
+#define MSR_IA32_MTRR_FIX16K_A0000               0x00000259
+
+
+/**
+  See Section 11.11.2.2, "Fixed Range MTRRs.". If CPUID.01H: EDX.MTRR[12] =1.
+
+  @param  ECX  MSR_IA32_MTRR_FIX4K_C0000 (0x00000268)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C0000);
+  AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C0000, Msr);
+  @endcode
+  @note MSR_IA32_MTRR_FIX4K_C0000 is defined as IA32_MTRR_FIX4K_C0000 in SDM.
+**/
+#define MSR_IA32_MTRR_FIX4K_C0000                0x00000268
+
+
+/**
+  MTRRfix4K_C8000. If CPUID.01H: EDX.MTRR[12] =1.
+
+  @param  ECX  MSR_IA32_MTRR_FIX4K_C8000 (0x00000269)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C8000);
+  AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C8000, Msr);
+  @endcode
+  @note MSR_IA32_MTRR_FIX4K_C8000 is defined as IA32_MTRR_FIX4K_C8000 in SDM.
+**/
+#define MSR_IA32_MTRR_FIX4K_C8000                0x00000269
+
+
+/**
+  MTRRfix4K_D0000. If CPUID.01H: EDX.MTRR[12] =1.
+
+  @param  ECX  MSR_IA32_MTRR_FIX4K_D0000 (0x0000026A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D0000);
+  AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D0000, Msr);
+  @endcode
+  @note MSR_IA32_MTRR_FIX4K_D0000 is defined as IA32_MTRR_FIX4K_D0000 in SDM.
+**/
+#define MSR_IA32_MTRR_FIX4K_D0000                0x0000026A
+
+
+/**
+  MTRRfix4K_D8000. If CPUID.01H: EDX.MTRR[12] =1.
+
+  @param  ECX  MSR_IA32_MTRR_FIX4K_D8000 (0x0000026B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D8000);
+  AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D8000, Msr);
+  @endcode
+  @note MSR_IA32_MTRR_FIX4K_D8000 is defined as IA32_MTRR_FIX4K_D8000 in SDM.
+**/
+#define MSR_IA32_MTRR_FIX4K_D8000                0x0000026B
+
+
+/**
+  MTRRfix4K_E0000. If CPUID.01H: EDX.MTRR[12] =1.
+
+  @param  ECX  MSR_IA32_MTRR_FIX4K_E0000 (0x0000026C)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E0000);
+  AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E0000, Msr);
+  @endcode
+  @note MSR_IA32_MTRR_FIX4K_E0000 is defined as IA32_MTRR_FIX4K_E0000 in SDM.
+**/
+#define MSR_IA32_MTRR_FIX4K_E0000                0x0000026C
+
+
+/**
+  MTRRfix4K_E8000. If CPUID.01H: EDX.MTRR[12] =1.
+
+  @param  ECX  MSR_IA32_MTRR_FIX4K_E8000 (0x0000026D)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E8000);
+  AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E8000, Msr);
+  @endcode
+  @note MSR_IA32_MTRR_FIX4K_E8000 is defined as IA32_MTRR_FIX4K_E8000 in SDM.
+**/
+#define MSR_IA32_MTRR_FIX4K_E8000                0x0000026D
+
+
+/**
+  MTRRfix4K_F0000. If CPUID.01H: EDX.MTRR[12] =1.
+
+  @param  ECX  MSR_IA32_MTRR_FIX4K_F0000 (0x0000026E)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F0000);
+  AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F0000, Msr);
+  @endcode
+  @note MSR_IA32_MTRR_FIX4K_F0000 is defined as IA32_MTRR_FIX4K_F0000 in SDM.
+**/
+#define MSR_IA32_MTRR_FIX4K_F0000                0x0000026E
+
+
+/**
+  MTRRfix4K_F8000. If CPUID.01H: EDX.MTRR[12] =1.
+
+  @param  ECX  MSR_IA32_MTRR_FIX4K_F8000 (0x0000026F)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F8000);
+  AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F8000, Msr);
+  @endcode
+  @note MSR_IA32_MTRR_FIX4K_F8000 is defined as IA32_MTRR_FIX4K_F8000 in SDM.
+**/
+#define MSR_IA32_MTRR_FIX4K_F8000                0x0000026F
+
+
+/**
+  IA32_PAT (R/W). If CPUID.01H: EDX.MTRR[16] =1.
+
+  @param  ECX  MSR_IA32_PAT (0x00000277)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_PAT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_PAT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_PAT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PAT);
+  AsmWriteMsr64 (MSR_IA32_PAT, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_PAT is defined as IA32_PAT in SDM.
+**/
+#define MSR_IA32_PAT                             0x00000277
+
+/**
+  MSR information returned for MSR index #MSR_IA32_PAT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 2:0] PA0.
+    ///
+    UINT32  PA0:3;
+    UINT32  Reserved1:5;
+    ///
+    /// [Bits 10:8] PA1.
+    ///
+    UINT32  PA1:3;
+    UINT32  Reserved2:5;
+    ///
+    /// [Bits 18:16] PA2.
+    ///
+    UINT32  PA2:3;
+    UINT32  Reserved3:5;
+    ///
+    /// [Bits 26:24] PA3.
+    ///
+    UINT32  PA3:3;
+    UINT32  Reserved4:5;
+    ///
+    /// [Bits 34:32] PA4.
+    ///
+    UINT32  PA4:3;
+    UINT32  Reserved5:5;
+    ///
+    /// [Bits 42:40] PA5.
+    ///
+    UINT32  PA5:3;
+    UINT32  Reserved6:5;
+    ///
+    /// [Bits 50:48] PA6.
+    ///
+    UINT32  PA6:3;
+    UINT32  Reserved7:5;
+    ///
+    /// [Bits 58:56] PA7.
+    ///
+    UINT32  PA7:3;
+    UINT32  Reserved8:5;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_PAT_REGISTER;
+
+
+/**
+  Provides the programming interface to use corrected MC error signaling
+  capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.
+
+  @param  ECX  MSR_IA32_MCn_CTL2
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_MC_CTL2_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_MC_CTL2_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_MC_CTL2_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
+  AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_MC0_CTL2  is defined as IA32_MC0_CTL2  in SDM.
+        MSR_IA32_MC1_CTL2  is defined as IA32_MC1_CTL2  in SDM.
+        MSR_IA32_MC2_CTL2  is defined as IA32_MC2_CTL2  in SDM.
+        MSR_IA32_MC3_CTL2  is defined as IA32_MC3_CTL2  in SDM.
+        MSR_IA32_MC4_CTL2  is defined as IA32_MC4_CTL2  in SDM.
+        MSR_IA32_MC5_CTL2  is defined as IA32_MC5_CTL2  in SDM.
+        MSR_IA32_MC6_CTL2  is defined as IA32_MC6_CTL2  in SDM.
+        MSR_IA32_MC7_CTL2  is defined as IA32_MC7_CTL2  in SDM.
+        MSR_IA32_MC8_CTL2  is defined as IA32_MC8_CTL2  in SDM.
+        MSR_IA32_MC9_CTL2  is defined as IA32_MC9_CTL2  in SDM.
+        MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM.
+        MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM.
+        MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM.
+        MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM.
+        MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM.
+        MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM.
+        MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM.
+        MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM.
+        MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM.
+        MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM.
+        MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM.
+        MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM.
+        MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM.
+        MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM.
+        MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM.
+        MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM.
+        MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM.
+        MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM.
+        MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM.
+        MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM.
+        MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM.
+        MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.
+  @{
+**/
+#define MSR_IA32_MC0_CTL2                        0x00000280
+#define MSR_IA32_MC1_CTL2                        0x00000281
+#define MSR_IA32_MC2_CTL2                        0x00000282
+#define MSR_IA32_MC3_CTL2                        0x00000283
+#define MSR_IA32_MC4_CTL2                        0x00000284
+#define MSR_IA32_MC5_CTL2                        0x00000285
+#define MSR_IA32_MC6_CTL2                        0x00000286
+#define MSR_IA32_MC7_CTL2                        0x00000287
+#define MSR_IA32_MC8_CTL2                        0x00000288
+#define MSR_IA32_MC9_CTL2                        0x00000289
+#define MSR_IA32_MC10_CTL2                       0x0000028A
+#define MSR_IA32_MC11_CTL2                       0x0000028B
+#define MSR_IA32_MC12_CTL2                       0x0000028C
+#define MSR_IA32_MC13_CTL2                       0x0000028D
+#define MSR_IA32_MC14_CTL2                       0x0000028E
+#define MSR_IA32_MC15_CTL2                       0x0000028F
+#define MSR_IA32_MC16_CTL2                       0x00000290
+#define MSR_IA32_MC17_CTL2                       0x00000291
+#define MSR_IA32_MC18_CTL2                       0x00000292
+#define MSR_IA32_MC19_CTL2                       0x00000293
+#define MSR_IA32_MC20_CTL2                       0x00000294
+#define MSR_IA32_MC21_CTL2                       0x00000295
+#define MSR_IA32_MC22_CTL2                       0x00000296
+#define MSR_IA32_MC23_CTL2                       0x00000297
+#define MSR_IA32_MC24_CTL2                       0x00000298
+#define MSR_IA32_MC25_CTL2                       0x00000299
+#define MSR_IA32_MC26_CTL2                       0x0000029A
+#define MSR_IA32_MC27_CTL2                       0x0000029B
+#define MSR_IA32_MC28_CTL2                       0x0000029C
+#define MSR_IA32_MC29_CTL2                       0x0000029D
+#define MSR_IA32_MC30_CTL2                       0x0000029E
+#define MSR_IA32_MC31_CTL2                       0x0000029F
+/// @}
+
+/**
+  MSR information returned for MSR indexes #MSR_IA32_MC0_CTL2
+  to #MSR_IA32_MC31_CTL2
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 14:0] Corrected error count threshold.
+    ///
+    UINT32  CorrectedErrorCountThreshold:15;
+    UINT32  Reserved1:15;
+    ///
+    /// [Bit 30] CMCI_EN.
+    ///
+    UINT32  CMCI_EN:1;
+    UINT32  Reserved2:1;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_MC_CTL2_REGISTER;
+
+
+/**
+  MTRRdefType (R/W). If CPUID.01H: EDX.MTRR[12] =1.
+
+  @param  ECX  MSR_IA32_MTRR_DEF_TYPE (0x000002FF)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_MTRR_DEF_TYPE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);
+  AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_MTRR_DEF_TYPE is defined as IA32_MTRR_DEF_TYPE in SDM.
+**/
+#define MSR_IA32_MTRR_DEF_TYPE                   0x000002FF
+
+/**
+  MSR information returned for MSR index #MSR_IA32_MTRR_DEF_TYPE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 2:0] Default Memory Type.
+    ///
+    UINT32  Type:3;
+    UINT32  Reserved1:7;
+    ///
+    /// [Bit 10] Fixed Range MTRR Enable.
+    ///
+    UINT32  FE:1;
+    ///
+    /// [Bit 11] MTRR Enable.
+    ///
+    UINT32  E:1;
+    UINT32  Reserved2:20;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_MTRR_DEF_TYPE_REGISTER;
+
+
+/**
+  Fixed-Function Performance Counter 0 (R/W): Counts Instr_Retired.Any. If
+  CPUID.0AH: EDX[4:0] > 0.
+
+  @param  ECX  MSR_IA32_FIXED_CTR0 (0x00000309)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR0);
+  AsmWriteMsr64 (MSR_IA32_FIXED_CTR0, Msr);
+  @endcode
+  @note MSR_IA32_FIXED_CTR0 is defined as IA32_FIXED_CTR0 in SDM.
+**/
+#define MSR_IA32_FIXED_CTR0                      0x00000309
+
+
+/**
+  Fixed-Function Performance Counter 1 (R/W): Counts CPU_CLK_Unhalted.Core. If
+  CPUID.0AH: EDX[4:0] > 1.
+
+  @param  ECX  MSR_IA32_FIXED_CTR1 (0x0000030A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR1);
+  AsmWriteMsr64 (MSR_IA32_FIXED_CTR1, Msr);
+  @endcode
+  @note MSR_IA32_FIXED_CTR1 is defined as IA32_FIXED_CTR1 in SDM.
+**/
+#define MSR_IA32_FIXED_CTR1                      0x0000030A
+
+
+/**
+  Fixed-Function Performance Counter 2 (R/W): Counts CPU_CLK_Unhalted.Ref. If
+  CPUID.0AH: EDX[4:0] > 2.
+
+  @param  ECX  MSR_IA32_FIXED_CTR2 (0x0000030B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR2);
+  AsmWriteMsr64 (MSR_IA32_FIXED_CTR2, Msr);
+  @endcode
+  @note MSR_IA32_FIXED_CTR2 is defined as IA32_FIXED_CTR2 in SDM.
+**/
+#define MSR_IA32_FIXED_CTR2                      0x0000030B
+
+
+/**
+  RO. If CPUID.01H: ECX[15] = 1.
+
+  @param  ECX  MSR_IA32_PERF_CAPABILITIES (0x00000345)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_PERF_CAPABILITIES_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CAPABILITIES);
+  AsmWriteMsr64 (MSR_IA32_PERF_CAPABILITIES, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_PERF_CAPABILITIES is defined as IA32_PERF_CAPABILITIES in SDM.
+**/
+#define MSR_IA32_PERF_CAPABILITIES               0x00000345
+
+/**
+  MSR information returned for MSR index #MSR_IA32_PERF_CAPABILITIES
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 5:0] LBR format.
+    ///
+    UINT32  LBR_FMT:6;
+    ///
+    /// [Bit 6] PEBS Trap.
+    ///
+    UINT32  PEBS_TRAP:1;
+    ///
+    /// [Bit 7] PEBSSaveArchRegs.
+    ///
+    UINT32  PEBS_ARCH_REG:1;
+    ///
+    /// [Bits 11:8] PEBS Record Format.
+    ///
+    UINT32  PEBS_REC_FMT:4;
+    ///
+    /// [Bit 12] 1: Freeze while SMM is supported.
+    ///
+    UINT32  SMM_FREEZE:1;
+    ///
+    /// [Bit 13] 1: Full width of counter writable via IA32_A_PMCx.
+    ///
+    UINT32  FW_WRITE:1;
+    UINT32  Reserved1:18;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_PERF_CAPABILITIES_REGISTER;
+
+
+/**
+  Fixed-Function Performance Counter Control (R/W) Counter increments while
+  the results of ANDing respective enable bit in IA32_PERF_GLOBAL_CTRL with
+  the corresponding OS or USR bits in this MSR is true. If CPUID.0AH: EAX[7:0]
+  > 1.
+
+  @param  ECX  MSR_IA32_FIXED_CTR_CTRL (0x0000038D)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_FIXED_CTR_CTRL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FIXED_CTR_CTRL);
+  AsmWriteMsr64 (MSR_IA32_FIXED_CTR_CTRL, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_FIXED_CTR_CTRL is defined as IA32_FIXED_CTR_CTRL in SDM.
+**/
+#define MSR_IA32_FIXED_CTR_CTRL                  0x0000038D
+
+/**
+  MSR information returned for MSR index #MSR_IA32_FIXED_CTR_CTRL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] EN0_OS: Enable Fixed Counter 0 to count while CPL = 0.
+    ///
+    UINT32  EN0_OS:1;
+    ///
+    /// [Bit 1] EN0_Usr: Enable Fixed Counter 0 to count while CPL > 0.
+    ///
+    UINT32  EN0_Usr:1;
+    ///
+    /// [Bit 2] AnyThread: When set to 1, it enables counting the associated
+    /// event conditions occurring across all logical processors sharing a
+    /// processor core. When set to 0, the counter only increments the
+    /// associated event conditions occurring in the logical processor which
+    /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.
+    ///
+    UINT32  AnyThread0:1;
+    ///
+    /// [Bit 3] EN0_PMI: Enable PMI when fixed counter 0 overflows.
+    ///
+    UINT32  EN0_PMI:1;
+    ///
+    /// [Bit 4] EN1_OS: Enable Fixed Counter 1 to count while CPL = 0.
+    ///
+    UINT32  EN1_OS:1;
+    ///
+    /// [Bit 5] EN1_Usr: Enable Fixed Counter 1 to count while CPL > 0.
+    ///
+    UINT32  EN1_Usr:1;
+    ///
+    /// [Bit 6] AnyThread: When set to 1, it enables counting the associated
+    /// event conditions occurring across all logical processors sharing a
+    /// processor core. When set to 0, the counter only increments the
+    /// associated event conditions occurring in the logical processor which
+    /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.
+    ///
+    UINT32  AnyThread1:1;
+    ///
+    /// [Bit 7] EN1_PMI: Enable PMI when fixed counter 1 overflows.
+    ///
+    UINT32  EN1_PMI:1;
+    ///
+    /// [Bit 8] EN2_OS: Enable Fixed Counter 2 to count while CPL = 0.
+    ///
+    UINT32  EN2_OS:1;
+    ///
+    /// [Bit 9] EN2_Usr: Enable Fixed Counter 2 to count while CPL > 0.
+    ///
+    UINT32  EN2_Usr:1;
+    ///
+    /// [Bit 10] AnyThread: When set to 1, it enables counting the associated
+    /// event conditions occurring across all logical processors sharing a
+    /// processor core. When set to 0, the counter only increments the
+    /// associated event conditions occurring in the logical processor which
+    /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.
+    ///
+    UINT32  AnyThread2:1;
+    ///
+    /// [Bit 11] EN2_PMI: Enable PMI when fixed counter 2 overflows.
+    ///
+    UINT32  EN2_PMI:1;
+    UINT32  Reserved1:20;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_FIXED_CTR_CTRL_REGISTER;
+
+
+/**
+  Global Performance Counter Status (RO). If CPUID.0AH: EAX[7:0] > 0.
+
+  @param  ECX  MSR_IA32_PERF_GLOBAL_STATUS (0x0000038E)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_PERF_GLOBAL_STATUS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS);
+  @endcode
+  @note MSR_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.
+**/
+#define MSR_IA32_PERF_GLOBAL_STATUS              0x0000038E
+
+/**
+  MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Ovf_PMC0: Overflow status of IA32_PMC0. If CPUID.0AH:
+    /// EAX[15:8] > 0.
+    ///
+    UINT32  Ovf_PMC0:1;
+    ///
+    /// [Bit 1] Ovf_PMC1: Overflow status of IA32_PMC1. If CPUID.0AH:
+    /// EAX[15:8] > 1.
+    ///
+    UINT32  Ovf_PMC1:1;
+    ///
+    /// [Bit 2] Ovf_PMC2: Overflow status of IA32_PMC2. If CPUID.0AH:
+    /// EAX[15:8] > 2.
+    ///
+    UINT32  Ovf_PMC2:1;
+    ///
+    /// [Bit 3] Ovf_PMC3: Overflow status of IA32_PMC3. If CPUID.0AH:
+    /// EAX[15:8] > 3.
+    ///
+    UINT32  Ovf_PMC3:1;
+    UINT32  Reserved1:28;
+    ///
+    /// [Bit 32] Ovf_FixedCtr0: Overflow status of IA32_FIXED_CTR0. If
+    /// CPUID.0AH: EAX[7:0] > 1.
+    ///
+    UINT32  Ovf_FixedCtr0:1;
+    ///
+    /// [Bit 33] Ovf_FixedCtr1: Overflow status of IA32_FIXED_CTR1. If
+    /// CPUID.0AH: EAX[7:0] > 1.
+    ///
+    UINT32  Ovf_FixedCtr1:1;
+    ///
+    /// [Bit 34] Ovf_FixedCtr2: Overflow status of IA32_FIXED_CTR2. If
+    /// CPUID.0AH: EAX[7:0] > 1.
+    ///
+    UINT32  Ovf_FixedCtr2:1;
+    UINT32  Reserved2:20;
+    ///
+    /// [Bit 55] Trace_ToPA_PMI: A PMI occurred due to a ToPA entry memory
+    /// buffer was completely filled. If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1)
+    /// && IA32_RTIT_CTL.ToPA = 1.
+    ///
+    UINT32  Trace_ToPA_PMI:1;
+    UINT32  Reserved3:2;
+    ///
+    /// [Bit 58] LBR_Frz: LBRs are frozen due to -
+    /// IA32_DEBUGCTL.FREEZE_LBR_ON_PMI=1, -  The LBR stack overflowed. If
+    /// CPUID.0AH: EAX[7:0] > 3.
+    ///
+    UINT32  LBR_Frz:1;
+    ///
+    /// [Bit 59] CTR_Frz: Performance counters in the core PMU are frozen due
+    /// to -  IA32_DEBUGCTL.FREEZE_PERFMON_ON_ PMI=1, -  one or more core PMU
+    /// counters overflowed. If CPUID.0AH: EAX[7:0] > 3.
+    ///
+    UINT32  CTR_Frz:1;
+    ///
+    /// [Bit 60] ASCI: Data in the performance counters in the core PMU may
+    /// include contributions from the direct or indirect operation intel SGX
+    /// to protect an enclave. If CPUID.(EAX=07H, ECX=0):EBX[2] = 1.
+    ///
+    UINT32  ASCI:1;
+    ///
+    /// [Bit 61] Ovf_Uncore: Uncore counter overflow status. If CPUID.0AH:
+    /// EAX[7:0] > 2.
+    ///
+    UINT32  Ovf_Uncore:1;
+    ///
+    /// [Bit 62] OvfBuf: DS SAVE area Buffer overflow status. If CPUID.0AH:
+    /// EAX[7:0] > 0.
+    ///
+    UINT32  OvfBuf:1;
+    ///
+    /// [Bit 63] CondChgd: status bits of this register has changed. If
+    /// CPUID.0AH: EAX[7:0] > 0.
+    ///
+    UINT32  CondChgd:1;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_PERF_GLOBAL_STATUS_REGISTER;
+
+
+/**
+  Global Performance Counter Control (R/W) Counter increments while the result
+  of ANDing respective enable bit in this MSR with the corresponding OS or USR
+  bits in the general-purpose or fixed counter control MSR is true. If
+  CPUID.0AH: EAX[7:0] > 0.
+
+  @param  ECX  MSR_IA32_PERF_GLOBAL_CTRL (0x0000038F)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_PERF_GLOBAL_CTRL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_CTRL);
+  AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_CTRL, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM.
+**/
+#define MSR_IA32_PERF_GLOBAL_CTRL                0x0000038F
+
+/**
+  MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_CTRL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+///
+  struct {
+    ///
+    /// [Bits 31:0] EN_PMCn. If CPUID.0AH: EAX[15:8] > n.
+    /// Enable bitmask.  Only the first n-1 bits are valid.
+    /// Bits n..31 are reserved.
+    ///
+    UINT32  EN_PMCn:32;
+    ///
+    /// [Bits 63:32] EN_FIXED_CTRn. If CPUID.0AH: EDX[4:0] > n.
+    /// Enable bitmask.  Only the first n-1 bits are valid.
+    /// Bits 31:n are reserved.
+    ///
+    UINT32  EN_FIXED_CTRn:32;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_PERF_GLOBAL_CTRL_REGISTER;
+
+
+/**
+  Global Performance Counter Overflow Control (R/W). If CPUID.0AH: EAX[7:0] >
+  0 && CPUID.0AH: EAX[7:0] <= 3.
+
+  @param  ECX  MSR_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL);
+  AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM.
+**/
+#define MSR_IA32_PERF_GLOBAL_OVF_CTRL            0x00000390
+
+/**
+  MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_OVF_CTRL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n.
+    /// Clear bitmask.  Only the first n-1 bits are valid.
+    /// Bits 31:n are reserved.
+    ///
+    UINT32  Ovf_PMCn:32;
+    ///
+    /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.
+    /// If CPUID.0AH: EDX[4:0] > n.
+    /// Clear bitmask.  Only the first n-1 bits are valid.
+    /// Bits 22:n are reserved.
+    ///
+    UINT32  Ovf_FIXED_CTRn:23;
+    ///
+    /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,
+    /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA = 1.
+    ///
+    UINT32  Trace_ToPA_PMI:1;
+    UINT32  Reserved2:5;
+    ///
+    /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /
+    /// Display Model 06_2EH.
+    ///
+    UINT32  Ovf_Uncore:1;
+    ///
+    /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.
+    ///
+    UINT32  OvfBuf:1;
+    ///
+    /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.
+    ///
+    UINT32  CondChgd:1;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER;
+
+
+/**
+  Global Performance Counter Overflow Reset Control (R/W). If CPUID.0AH:
+  EAX[7:0] > 3.
+
+  @param  ECX  MSR_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET);
+  AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.
+**/
+#define MSR_IA32_PERF_GLOBAL_STATUS_RESET        0x00000390
+
+/**
+  MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_RESET
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n.
+    /// Clear bitmask.  Only the first n-1 bits are valid.
+    /// Bits 31:n are reserved.
+    ///
+    UINT32  Ovf_PMCn:32;
+    ///
+    /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.
+    /// If CPUID.0AH: EDX[4:0] > n.
+    /// Clear bitmask.  Only the first n-1 bits are valid.
+    /// Bits 22:n are reserved.
+    ///
+    UINT32  Ovf_FIXED_CTRn:23;
+    ///
+    /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,
+    /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA[8] = 1.
+    ///
+    UINT32  Trace_ToPA_PMI:1;
+    UINT32  Reserved2:2;
+    ///
+    /// [Bit 58] Set 1 to Clear LBR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.
+    ///
+    UINT32  LBR_Frz:1;
+    ///
+    /// [Bit 59] Set 1 to Clear CTR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.
+    ///
+    UINT32  CTR_Frz:1;
+    ///
+    /// [Bit 60] Set 1 to Clear ASCI bit. If CPUID.0AH: EAX[7:0] > 3.
+    ///
+    UINT32  ASCI:1;
+    ///
+    /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /
+    /// Display Model 06_2EH.
+    ///
+    UINT32  Ovf_Uncore:1;
+    ///
+    /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.
+    ///
+    UINT32  OvfBuf:1;
+    ///
+    /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.
+    ///
+    UINT32  CondChgd:1;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER;
+
+
+/**
+  Global Performance Counter Overflow Set Control (R/W). If CPUID.0AH:
+  EAX[7:0] > 3.
+
+  @param  ECX  MSR_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET);
+  AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.
+**/
+#define MSR_IA32_PERF_GLOBAL_STATUS_SET          0x00000391
+
+/**
+  MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_SET
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 31:0] Set 1 to cause Ovf_PMCn = 1. If CPUID.0AH: EAX[7:0] > n.
+    /// Set bitmask.  Only the first n-1 bits are valid.
+    /// Bits 31:n are reserved.
+    ///
+    UINT32  Ovf_PMCn:32;
+    ///
+    /// [Bits 54:32] Set 1 to cause Ovf_FIXED_CTRn = 1.
+    /// If CPUID.0AH: EAX[7:0] > n.
+    /// Set bitmask.  Only the first n-1 bits are valid.
+    /// Bits 22:n are reserved.
+    ///
+    UINT32  Ovf_FIXED_CTRn:23;
+    ///
+    /// [Bit 55] Set 1 to cause Trace_ToPA_PMI = 1. If CPUID.0AH: EAX[7:0] > 3.
+    ///
+    UINT32  Trace_ToPA_PMI:1;
+    UINT32  Reserved2:2;
+    ///
+    /// [Bit 58] Set 1 to cause LBR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.
+    ///
+    UINT32  LBR_Frz:1;
+    ///
+    /// [Bit 59] Set 1 to cause CTR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.
+    ///
+    UINT32  CTR_Frz:1;
+    ///
+    /// [Bit 60] Set 1 to cause ASCI = 1. If CPUID.0AH: EAX[7:0] > 3.
+    ///
+    UINT32  ASCI:1;
+    ///
+    /// [Bit 61] Set 1 to cause Ovf_Uncore = 1. If CPUID.0AH: EAX[7:0] > 3.
+    ///
+    UINT32  Ovf_Uncore:1;
+    ///
+    /// [Bit 62] Set 1 to cause OvfBuf = 1. If CPUID.0AH: EAX[7:0] > 3.
+    ///
+    UINT32  OvfBuf:1;
+    UINT32  Reserved3:1;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER;
+
+
+/**
+  Indicator of core perfmon interface is in use (RO). If CPUID.0AH: EAX[7:0] >
+  3.
+
+  @param  ECX  MSR_IA32_PERF_GLOBAL_INUSE (0x00000392)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_PERF_GLOBAL_INUSE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_INUSE);
+  @endcode
+  @note MSR_IA32_PERF_GLOBAL_INUSE is defined as IA32_PERF_GLOBAL_INUSE in SDM.
+**/
+#define MSR_IA32_PERF_GLOBAL_INUSE               0x00000392
+
+/**
+  MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_INUSE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 31:0] IA32_PERFEVTSELn in use.  If CPUID.0AH: EAX[7:0] > n.
+    /// Status bitmask.  Only the first n-1 bits are valid.
+    /// Bits 31:n are reserved.
+    ///
+    UINT32  IA32_PERFEVTSELn:32;
+    ///
+    /// [Bits 62:32] IA32_FIXED_CTRn in use.
+    /// If CPUID.0AH: EAX[7:0] > n.
+    /// Status bitmask.  Only the first n-1 bits are valid.
+    /// Bits 30:n are reserved.
+    ///
+    UINT32  IA32_FIXED_CTRn:31;
+    ///
+    /// [Bit 63] PMI in use.
+    ///
+    UINT32  PMI:1;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_PERF_GLOBAL_INUSE_REGISTER;
+
+
+/**
+  PEBS Control (R/W).
+
+  @param  ECX  MSR_IA32_PEBS_ENABLE (0x000003F1)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_PEBS_ENABLE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_PEBS_ENABLE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_PEBS_ENABLE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PEBS_ENABLE);
+  AsmWriteMsr64 (MSR_IA32_PEBS_ENABLE, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_PEBS_ENABLE is defined as IA32_PEBS_ENABLE in SDM.
+**/
+#define MSR_IA32_PEBS_ENABLE                     0x000003F1
+
+/**
+  MSR information returned for MSR index #MSR_IA32_PEBS_ENABLE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Enable PEBS on IA32_PMC0. Introduced at Display Family /
+    /// Display Model 06_0FH.
+    ///
+    UINT32  Enable:1;
+    ///
+    /// [Bits 3:1] Reserved or Model specific.
+    ///
+    UINT32  Reserved1:3;
+    UINT32  Reserved2:28;
+    ///
+    /// [Bits 35:32] Reserved or Model specific.
+    ///
+    UINT32  Reserved3:4;
+    UINT32  Reserved4:28;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_PEBS_ENABLE_REGISTER;
+
+
+/**
+  MCn_CTL. If IA32_MCG_CAP.CNT > n.
+
+  @param  ECX  MSR_IA32_MCn_CTL
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);
+  AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);
+  @endcode
+  @note MSR_IA32_MC0_CTL  is defined as IA32_MC0_CTL  in SDM.
+        MSR_IA32_MC1_CTL  is defined as IA32_MC1_CTL  in SDM.
+        MSR_IA32_MC2_CTL  is defined as IA32_MC2_CTL  in SDM.
+        MSR_IA32_MC3_CTL  is defined as IA32_MC3_CTL  in SDM.
+        MSR_IA32_MC4_CTL  is defined as IA32_MC4_CTL  in SDM.
+        MSR_IA32_MC5_CTL  is defined as IA32_MC5_CTL  in SDM.
+        MSR_IA32_MC6_CTL  is defined as IA32_MC6_CTL  in SDM.
+        MSR_IA32_MC7_CTL  is defined as IA32_MC7_CTL  in SDM.
+        MSR_IA32_MC8_CTL  is defined as IA32_MC8_CTL  in SDM.
+        MSR_IA32_MC9_CTL  is defined as IA32_MC9_CTL  in SDM.
+        MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM.
+        MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM.
+        MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM.
+        MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM.
+        MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM.
+        MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM.
+        MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM.
+        MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM.
+        MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM.
+        MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM.
+        MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM.
+        MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM.
+        MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM.
+        MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM.
+        MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM.
+        MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM.
+        MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM.
+        MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM.
+        MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.
+  @{
+**/
+#define MSR_IA32_MC0_CTL                         0x00000400
+#define MSR_IA32_MC1_CTL                         0x00000404
+#define MSR_IA32_MC2_CTL                         0x00000408
+#define MSR_IA32_MC3_CTL                         0x0000040C
+#define MSR_IA32_MC4_CTL                         0x00000410
+#define MSR_IA32_MC5_CTL                         0x00000414
+#define MSR_IA32_MC6_CTL                         0x00000418
+#define MSR_IA32_MC7_CTL                         0x0000041C
+#define MSR_IA32_MC8_CTL                         0x00000420
+#define MSR_IA32_MC9_CTL                         0x00000424
+#define MSR_IA32_MC10_CTL                        0x00000428
+#define MSR_IA32_MC11_CTL                        0x0000042C
+#define MSR_IA32_MC12_CTL                        0x00000430
+#define MSR_IA32_MC13_CTL                        0x00000434
+#define MSR_IA32_MC14_CTL                        0x00000438
+#define MSR_IA32_MC15_CTL                        0x0000043C
+#define MSR_IA32_MC16_CTL                        0x00000440
+#define MSR_IA32_MC17_CTL                        0x00000444
+#define MSR_IA32_MC18_CTL                        0x00000448
+#define MSR_IA32_MC19_CTL                        0x0000044C
+#define MSR_IA32_MC20_CTL                        0x00000450
+#define MSR_IA32_MC21_CTL                        0x00000454
+#define MSR_IA32_MC22_CTL                        0x00000458
+#define MSR_IA32_MC23_CTL                        0x0000045C
+#define MSR_IA32_MC24_CTL                        0x00000460
+#define MSR_IA32_MC25_CTL                        0x00000464
+#define MSR_IA32_MC26_CTL                        0x00000468
+#define MSR_IA32_MC27_CTL                        0x0000046C
+#define MSR_IA32_MC28_CTL                        0x00000470
+/// @}
+
+
+/**
+  MCn_STATUS. If IA32_MCG_CAP.CNT > n.
+
+  @param  ECX  MSR_IA32_MCn_STATUS
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);
+  AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);
+  @endcode
+  @note MSR_IA32_MC0_STATUS  is defined as IA32_MC0_STATUS  in SDM.
+        MSR_IA32_MC1_STATUS  is defined as IA32_MC1_STATUS  in SDM.
+        MSR_IA32_MC2_STATUS  is defined as IA32_MC2_STATUS  in SDM.
+        MSR_IA32_MC3_STATUS  is defined as IA32_MC3_STATUS  in SDM.
+        MSR_IA32_MC4_STATUS  is defined as IA32_MC4_STATUS  in SDM.
+        MSR_IA32_MC5_STATUS  is defined as IA32_MC5_STATUS  in SDM.
+        MSR_IA32_MC6_STATUS  is defined as IA32_MC6_STATUS  in SDM.
+        MSR_IA32_MC7_STATUS  is defined as IA32_MC7_STATUS  in SDM.
+        MSR_IA32_MC8_STATUS  is defined as IA32_MC8_STATUS  in SDM.
+        MSR_IA32_MC9_STATUS  is defined as IA32_MC9_STATUS  in SDM.
+        MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM.
+        MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM.
+        MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM.
+        MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM.
+        MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM.
+        MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM.
+        MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM.
+        MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM.
+        MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM.
+        MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM.
+        MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM.
+        MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM.
+        MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM.
+        MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM.
+        MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM.
+        MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM.
+        MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM.
+        MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM.
+        MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.
+  @{
+**/
+#define MSR_IA32_MC0_STATUS                      0x00000401
+#define MSR_IA32_MC1_STATUS                      0x00000405
+#define MSR_IA32_MC2_STATUS                      0x00000409
+#define MSR_IA32_MC3_STATUS                      0x0000040D
+#define MSR_IA32_MC4_STATUS                      0x00000411
+#define MSR_IA32_MC5_STATUS                      0x00000415
+#define MSR_IA32_MC6_STATUS                      0x00000419
+#define MSR_IA32_MC7_STATUS                      0x0000041D
+#define MSR_IA32_MC8_STATUS                      0x00000421
+#define MSR_IA32_MC9_STATUS                      0x00000425
+#define MSR_IA32_MC10_STATUS                     0x00000429
+#define MSR_IA32_MC11_STATUS                     0x0000042D
+#define MSR_IA32_MC12_STATUS                     0x00000431
+#define MSR_IA32_MC13_STATUS                     0x00000435
+#define MSR_IA32_MC14_STATUS                     0x00000439
+#define MSR_IA32_MC15_STATUS                     0x0000043D
+#define MSR_IA32_MC16_STATUS                     0x00000441
+#define MSR_IA32_MC17_STATUS                     0x00000445
+#define MSR_IA32_MC18_STATUS                     0x00000449
+#define MSR_IA32_MC19_STATUS                     0x0000044D
+#define MSR_IA32_MC20_STATUS                     0x00000451
+#define MSR_IA32_MC21_STATUS                     0x00000455
+#define MSR_IA32_MC22_STATUS                     0x00000459
+#define MSR_IA32_MC23_STATUS                     0x0000045D
+#define MSR_IA32_MC24_STATUS                     0x00000461
+#define MSR_IA32_MC25_STATUS                     0x00000465
+#define MSR_IA32_MC26_STATUS                     0x00000469
+#define MSR_IA32_MC27_STATUS                     0x0000046D
+#define MSR_IA32_MC28_STATUS                     0x00000471
+/// @}
+
+
+/**
+  MCn_ADDR. If IA32_MCG_CAP.CNT > n.
+
+  @param  ECX  MSR_IA32_MCn_ADDR
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);
+  AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);
+  @endcode
+  @note MSR_IA32_MC0_ADDR  is defined as IA32_MC0_ADDR  in SDM.
+        MSR_IA32_MC1_ADDR  is defined as IA32_MC1_ADDR  in SDM.
+        MSR_IA32_MC2_ADDR  is defined as IA32_MC2_ADDR  in SDM.
+        MSR_IA32_MC3_ADDR  is defined as IA32_MC3_ADDR  in SDM.
+        MSR_IA32_MC4_ADDR  is defined as IA32_MC4_ADDR  in SDM.
+        MSR_IA32_MC5_ADDR  is defined as IA32_MC5_ADDR  in SDM.
+        MSR_IA32_MC6_ADDR  is defined as IA32_MC6_ADDR  in SDM.
+        MSR_IA32_MC7_ADDR  is defined as IA32_MC7_ADDR  in SDM.
+        MSR_IA32_MC8_ADDR  is defined as IA32_MC8_ADDR  in SDM.
+        MSR_IA32_MC9_ADDR  is defined as IA32_MC9_ADDR  in SDM.
+        MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM.
+        MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM.
+        MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM.
+        MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM.
+        MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM.
+        MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM.
+        MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM.
+        MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM.
+        MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM.
+        MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM.
+        MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM.
+        MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM.
+        MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM.
+        MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM.
+        MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM.
+        MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM.
+        MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM.
+        MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM.
+        MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.
+  @{
+**/
+#define MSR_IA32_MC0_ADDR                        0x00000402
+#define MSR_IA32_MC1_ADDR                        0x00000406
+#define MSR_IA32_MC2_ADDR                        0x0000040A
+#define MSR_IA32_MC3_ADDR                        0x0000040E
+#define MSR_IA32_MC4_ADDR                        0x00000412
+#define MSR_IA32_MC5_ADDR                        0x00000416
+#define MSR_IA32_MC6_ADDR                        0x0000041A
+#define MSR_IA32_MC7_ADDR                        0x0000041E
+#define MSR_IA32_MC8_ADDR                        0x00000422
+#define MSR_IA32_MC9_ADDR                        0x00000426
+#define MSR_IA32_MC10_ADDR                       0x0000042A
+#define MSR_IA32_MC11_ADDR                       0x0000042E
+#define MSR_IA32_MC12_ADDR                       0x00000432
+#define MSR_IA32_MC13_ADDR                       0x00000436
+#define MSR_IA32_MC14_ADDR                       0x0000043A
+#define MSR_IA32_MC15_ADDR                       0x0000043E
+#define MSR_IA32_MC16_ADDR                       0x00000442
+#define MSR_IA32_MC17_ADDR                       0x00000446
+#define MSR_IA32_MC18_ADDR                       0x0000044A
+#define MSR_IA32_MC19_ADDR                       0x0000044E
+#define MSR_IA32_MC20_ADDR                       0x00000452
+#define MSR_IA32_MC21_ADDR                       0x00000456
+#define MSR_IA32_MC22_ADDR                       0x0000045A
+#define MSR_IA32_MC23_ADDR                       0x0000045E
+#define MSR_IA32_MC24_ADDR                       0x00000462
+#define MSR_IA32_MC25_ADDR                       0x00000466
+#define MSR_IA32_MC26_ADDR                       0x0000046A
+#define MSR_IA32_MC27_ADDR                       0x0000046E
+#define MSR_IA32_MC28_ADDR                       0x00000472
+/// @}
+
+
+/**
+  MCn_MISC. If IA32_MCG_CAP.CNT > n.
+
+  @param  ECX  MSR_IA32_MCn_MISC
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);
+  AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);
+  @endcode
+  @note MSR_IA32_MC0_MISC  is defined as IA32_MC0_MISC  in SDM.
+        MSR_IA32_MC1_MISC  is defined as IA32_MC1_MISC  in SDM.
+        MSR_IA32_MC2_MISC  is defined as IA32_MC2_MISC  in SDM.
+        MSR_IA32_MC3_MISC  is defined as IA32_MC3_MISC  in SDM.
+        MSR_IA32_MC4_MISC  is defined as IA32_MC4_MISC  in SDM.
+        MSR_IA32_MC5_MISC  is defined as IA32_MC5_MISC  in SDM.
+        MSR_IA32_MC6_MISC  is defined as IA32_MC6_MISC  in SDM.
+        MSR_IA32_MC7_MISC  is defined as IA32_MC7_MISC  in SDM.
+        MSR_IA32_MC8_MISC  is defined as IA32_MC8_MISC  in SDM.
+        MSR_IA32_MC9_MISC  is defined as IA32_MC9_MISC  in SDM.
+        MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM.
+        MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM.
+        MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM.
+        MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM.
+        MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM.
+        MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM.
+        MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM.
+        MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM.
+        MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM.
+        MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM.
+        MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM.
+        MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM.
+        MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM.
+        MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM.
+        MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM.
+        MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM.
+        MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM.
+        MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM.
+        MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.
+  @{
+**/
+#define MSR_IA32_MC0_MISC                        0x00000403
+#define MSR_IA32_MC1_MISC                        0x00000407
+#define MSR_IA32_MC2_MISC                        0x0000040B
+#define MSR_IA32_MC3_MISC                        0x0000040F
+#define MSR_IA32_MC4_MISC                        0x00000413
+#define MSR_IA32_MC5_MISC                        0x00000417
+#define MSR_IA32_MC6_MISC                        0x0000041B
+#define MSR_IA32_MC7_MISC                        0x0000041F
+#define MSR_IA32_MC8_MISC                        0x00000423
+#define MSR_IA32_MC9_MISC                        0x00000427
+#define MSR_IA32_MC10_MISC                       0x0000042B
+#define MSR_IA32_MC11_MISC                       0x0000042F
+#define MSR_IA32_MC12_MISC                       0x00000433
+#define MSR_IA32_MC13_MISC                       0x00000437
+#define MSR_IA32_MC14_MISC                       0x0000043B
+#define MSR_IA32_MC15_MISC                       0x0000043F
+#define MSR_IA32_MC16_MISC                       0x00000443
+#define MSR_IA32_MC17_MISC                       0x00000447
+#define MSR_IA32_MC18_MISC                       0x0000044B
+#define MSR_IA32_MC19_MISC                       0x0000044F
+#define MSR_IA32_MC20_MISC                       0x00000453
+#define MSR_IA32_MC21_MISC                       0x00000457
+#define MSR_IA32_MC22_MISC                       0x0000045B
+#define MSR_IA32_MC23_MISC                       0x0000045F
+#define MSR_IA32_MC24_MISC                       0x00000463
+#define MSR_IA32_MC25_MISC                       0x00000467
+#define MSR_IA32_MC26_MISC                       0x0000046B
+#define MSR_IA32_MC27_MISC                       0x0000046F
+#define MSR_IA32_MC28_MISC                       0x00000473
+/// @}
+
+
+/**
+  Reporting Register of Basic VMX  Capabilities (R/O) See Appendix A.1, "Basic
+  VMX Information.". If CPUID.01H:ECX.[5] = 1.
+
+  @param  ECX  MSR_IA32_VMX_BASIC (0x00000480)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_VMX_BASIC_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_BASIC);
+  @endcode
+  @note MSR_IA32_VMX_BASIC is defined as IA32_VMX_BASIC in SDM.
+**/
+#define MSR_IA32_VMX_BASIC                       0x00000480
+
+/**
+  MSR information returned for MSR index #MSR_IA32_VMX_BASIC
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 30:0] VMCS revision identifier used by the processor.  Processors
+    /// that use the same VMCS revision identifier use the same size for VMCS
+    /// regions (see subsequent item on bits 44:32).
+    ///
+    /// @note Earlier versions of this manual specified that the VMCS revision
+    /// identifier was a 32-bit field in bits 31:0 of this MSR. For all
+    /// processors produced prior to this change, bit 31 of this MSR was read
+    /// as 0.
+    ///
+    UINT32  VmcsRevisonId:31;
+    UINT32  MustBeZero:1;
+    ///
+    /// [Bit 44:32] Reports the number of bytes that software should allocate
+    /// for the VMXON region and any VMCS region.  It is a value greater than
+    /// 0 and at most 4096(bit 44 is set if and only if bits 43:32 are clear).
+    ///
+    UINT32  VmcsSize:13;
+    UINT32  Reserved1:3;
+    ///
+    /// [Bit 48] Indicates the width of the physical addresses that may be used
+    /// for the VMXON region, each VMCS, and data structures referenced by
+    /// pointers in a VMCS (I/O bitmaps, virtual-APIC page, MSR areas for VMX
+    /// transitions).  If the bit is 0, these addresses are limited to the
+    /// processor's physical-address width.  If the bit is 1, these addresses
+    /// are limited to 32 bits. This bit is always 0 for processors that
+    /// support Intel 64 architecture.
+    ///
+    /// @note On processors that support Intel 64 architecture, the pointer
+    /// must not set bits beyond the processor's physical address width.
+    ///
+    UINT32  VmcsAddressWidth:1;
+    ///
+    /// [Bit 49] If bit 49 is read as 1, the logical processor supports the
+    /// dual-monitor treatment of system-management interrupts and
+    /// system-management mode. See Section 34.15 for details of this treatment.
+    ///
+    UINT32  DualMonitor:1;
+    ///
+    /// [Bit 53:50] report the memory type that should be used for the VMCS,
+    /// for data structures referenced by pointers in the VMCS (I/O bitmaps,
+    /// virtual-APIC page, MSR areas for VMX transitions), and for the MSEG
+    /// header. If software needs to access these data structures (e.g., to
+    /// modify the contents of the MSR bitmaps), it can configure the paging
+    /// structures to map them into the linear-address space. If it does so,
+    /// it should establish mappings that use the memory type reported bits
+    /// 53:50 in this MSR.
+    ///
+    /// As of this writing, all processors that support VMX operation indicate
+    /// the write-back type.
+    ///
+    /// If software needs to access these data structures (e.g., to modify
+    /// the contents of the MSR bitmaps), it can configure the paging
+    /// structures to map them into the linear-address space. If it does so,
+    /// it should establish mappings that use the memory type reported in this
+    /// MSR.
+    ///
+    /// @note Alternatively, software may map any of these regions or
+    /// structures with the UC memory type. (This may be necessary for the MSEG
+    /// header.) Doing so is discouraged unless necessary as it will cause the
+    /// performance of software accesses to those structures to suffer.
+    ///
+    ///
+    UINT32  MemoryType:4;
+    ///
+    /// [Bit 54] If bit 54 is read as 1, the processor reports information in
+    /// the VM-exit instruction-information field on VM exitsdue to execution
+    /// of the INS and OUTS instructions (see Section 27.2.4). This reporting
+    /// is done only if this bit is read as 1.
+    ///
+    UINT32  InsOutsReporting:1;
+    ///
+    /// [Bit 55] Bit 55 is read as 1 if any VMX controls that default to 1 may
+    /// be cleared to 0. See Appendix A.2 for details. It also reports support
+    /// for the VMX capability MSRs IA32_VMX_TRUE_PINBASED_CTLS,
+    /// IA32_VMX_TRUE_PROCBASED_CTLS, IA32_VMX_TRUE_EXIT_CTLS, and
+    /// IA32_VMX_TRUE_ENTRY_CTLS. See Appendix A.3.1, Appendix A.3.2,
+    /// Appendix A.4, and Appendix A.5 for details.
+    ///
+    UINT32  VmxControls:1;
+    UINT32  Reserved2:8;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_VMX_BASIC_REGISTER;
+
+///
+/// @{ Define value for bit field MSR_IA32_VMX_BASIC_REGISTER.MemoryType
+///
+#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_UNCACHEABLE  0x00
+#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_WRITE_BACK   0x06
+///
+/// @}
+///
+
+
+/**
+  Capability Reporting Register of Pinbased VM-execution Controls (R/O) See
+  Appendix A.3.1, "Pin-Based VMExecution Controls.". If CPUID.01H:ECX.[5] = 1.
+
+  @param  ECX  MSR_IA32_VMX_PINBASED_CTLS (0x00000481)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_VMX_PINBASED_CTLS);
+  @endcode
+  @note MSR_IA32_VMX_PINBASED_CTLS is defined as IA32_VMX_PINBASED_CTLS in SDM.
+**/
+#define MSR_IA32_VMX_PINBASED_CTLS               0x00000481
+
+
+/**
+  Capability Reporting Register of Primary  Processor-based VM-execution
+  Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution
+  Controls.". If CPUID.01H:ECX.[5] = 1.
+
+  @param  ECX  MSR_IA32_VMX_PROCBASED_CTLS (0x00000482)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS);
+  @endcode
+  @note MSR_IA32_VMX_PROCBASED_CTLS is defined as IA32_VMX_PROCBASED_CTLS in SDM.
+**/
+#define MSR_IA32_VMX_PROCBASED_CTLS              0x00000482
+
+
+/**
+  Capability Reporting Register of VM-exit  Controls (R/O) See Appendix A.4,
+  "VM-Exit Controls.". If CPUID.01H:ECX.[5] = 1.
+
+  @param  ECX  MSR_IA32_VMX_EXIT_CTLS (0x00000483)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_VMX_EXIT_CTLS);
+  @endcode
+  @note MSR_IA32_VMX_EXIT_CTLS is defined as IA32_VMX_EXIT_CTLS in SDM.
+**/
+#define MSR_IA32_VMX_EXIT_CTLS                   0x00000483
+
+
+/**
+  Capability Reporting Register of VMentry Controls (R/O) See Appendix A.5,
+  "VM-Entry Controls.". If CPUID.01H:ECX.[5] = 1.
+
+  @param  ECX  MSR_IA32_VMX_ENTRY_CTLS (0x00000484)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_VMX_ENTRY_CTLS);
+  @endcode
+  @note MSR_IA32_VMX_ENTRY_CTLS is defined as IA32_VMX_ENTRY_CTLS in SDM.
+**/
+#define MSR_IA32_VMX_ENTRY_CTLS                  0x00000484
+
+
+/**
+  Reporting Register of Miscellaneous VMX Capabilities (R/O) See Appendix A.6,
+  "Miscellaneous Data.". If CPUID.01H:ECX.[5] = 1.
+
+  @param  ECX  MSR_IA32_VMX_MISC (0x00000485)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  IA32_VMX_MISC_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_MISC);
+  @endcode
+  @note MSR_IA32_VMX_MISC is defined as IA32_VMX_MISC in SDM.
+**/
+#define MSR_IA32_VMX_MISC                        0x00000485
+
+/**
+  MSR information returned for MSR index #IA32_VMX_MISC
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 4:0] Reports a value X that specifies the relationship between the
+    /// rate of the VMX-preemption timer and that of the timestamp counter (TSC).
+    /// Specifically, the VMX-preemption timer (if it is active) counts down by
+    /// 1 every time bit X in the TSC changes due to a TSC increment.
+    ///
+    UINT32  VmxTimerRatio:5;
+    ///
+    /// [Bit 5] If bit 5 is read as 1, VM exits store the value of IA32_EFER.LMA
+    /// into the "IA-32e mode guest" VM-entry control;see Section 27.2 for more
+    /// details. This bit is read as 1 on any logical processor that supports
+    /// the 1-setting of the "unrestricted guest" VM-execution control.
+    ///
+    UINT32  VmExitEferLma:1;
+    ///
+    /// [Bit 6] reports (if set) the support for activity state 1 (HLT).
+    ///
+    UINT32  HltActivityStateSupported:1;
+    ///
+    /// [Bit 7] reports (if set) the support for activity state 2 (shutdown).
+    ///
+    UINT32  ShutdownActivityStateSupported:1;
+    ///
+    /// [Bit 8] reports (if set) the support for activity state 3 (wait-for-SIPI).
+    ///
+    UINT32  WaitForSipiActivityStateSupported:1;
+    UINT32  Reserved1:5;
+    ///
+    /// [Bit 14] If read as 1, Intel(R) Processor Trace (Intel PT) can be used
+    /// in VMX operation. If the processor supports Intel PT but does not allow
+    /// it to be used in VMX operation, execution of VMXON clears
+    /// IA32_RTIT_CTL.TraceEn (see "VMXON-Enter VMX Operation" in Chapter 30);
+    /// any attempt to set that bit while in VMX operation (including VMX root
+    /// operation) using the WRMSR instruction causes a general-protection
+    /// exception.
+    ///
+    UINT32  ProcessorTraceSupported:1;
+    ///
+    /// [Bit 15] If read as 1, the RDMSR instruction can be used in system-
+    /// management mode (SMM) to read the IA32_SMBASE MSR (MSR address 9EH).
+    /// See Section 34.15.6.3.
+    ///
+    UINT32  SmBaseMsrSupported:1;
+    ///
+    /// [Bits 24:16] Indicate the number of CR3-target values supported by the
+    /// processor. This number is a value between 0 and 256, inclusive (bit 24
+    /// is set if and only if bits 23:16 are clear).
+    ///
+    UINT32  NumberOfCr3TargetValues:9;
+    ///
+    /// [Bit 27:25] Bits 27:25 is used to compute the recommended maximum
+    /// number of MSRs that should appear in the VM-exit MSR-store list, the
+    /// VM-exit MSR-load list, or the VM-entry MSR-load list. Specifically, if
+    /// the value bits 27:25 of IA32_VMX_MISC is N, then 512 * (N + 1) is the
+    /// recommended maximum number of MSRs to be included in each list. If the
+    /// limit is exceeded, undefined processor behavior may result (including a
+    /// machine check during the VMX transition).
+    ///
+    UINT32  MsrStoreListMaximum:3;
+    ///
+    /// [Bit 28] If read as 1, bit 2 of the IA32_SMM_MONITOR_CTL can be set
+    /// to 1. VMXOFF unblocks SMIs unless IA32_SMM_MONITOR_CTL[bit 2] is 1
+    /// (see Section 34.14.4).
+    ///
+    UINT32  BlockSmiSupported:1;
+    ///
+    /// [Bit 29] read as 1, software can use VMWRITE to write to any supported
+    /// field in the VMCS; otherwise, VMWRITE cannot be used to modify VM-exit
+    /// information fields.
+    ///
+    UINT32  VmWriteSupported:1;
+    ///
+    /// [Bit 30] If read as 1, VM entry allows injection of a software
+    /// interrupt, software exception, or privileged software exception with an
+    /// instruction length of 0.
+    ///
+    UINT32  VmInjectSupported:1;
+    UINT32  Reserved2:1;
+    ///
+    /// [Bits 63:32] Reports the 32-bit MSEG revision identifier used by the
+    /// processor.
+    ///
+    UINT32  MsegRevisionIdentifier:32;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} IA32_VMX_MISC_REGISTER;
+
+
+/**
+  Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Appendix A.7,
+  "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1.
+
+  @param  ECX  MSR_IA32_VMX_CR0_FIXED0 (0x00000486)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED0);
+  @endcode
+  @note MSR_IA32_VMX_CR0_FIXED0 is defined as IA32_VMX_CR0_FIXED0 in SDM.
+**/
+#define MSR_IA32_VMX_CR0_FIXED0                  0x00000486
+
+
+/**
+  Capability Reporting Register of CR0 Bits Fixed to 1 (R/O) See Appendix A.7,
+  "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1.
+
+  @param  ECX  MSR_IA32_VMX_CR0_FIXED1 (0x00000487)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED1);
+  @endcode
+  @note MSR_IA32_VMX_CR0_FIXED1 is defined as IA32_VMX_CR0_FIXED1 in SDM.
+**/
+#define MSR_IA32_VMX_CR0_FIXED1                  0x00000487
+
+
+/**
+  Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) See Appendix A.8,
+  "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1.
+
+  @param  ECX  MSR_IA32_VMX_CR4_FIXED0 (0x00000488)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED0);
+  @endcode
+  @note MSR_IA32_VMX_CR4_FIXED0 is defined as IA32_VMX_CR4_FIXED0 in SDM.
+**/
+#define MSR_IA32_VMX_CR4_FIXED0                  0x00000488
+
+
+/**
+  Capability Reporting Register of CR4 Bits Fixed to 1 (R/O) See Appendix A.8,
+  "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1.
+
+  @param  ECX  MSR_IA32_VMX_CR4_FIXED1 (0x00000489)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED1);
+  @endcode
+  @note MSR_IA32_VMX_CR4_FIXED1 is defined as IA32_VMX_CR4_FIXED1 in SDM.
+**/
+#define MSR_IA32_VMX_CR4_FIXED1                  0x00000489
+
+
+/**
+  Capability Reporting Register of VMCS Field Enumeration (R/O) See Appendix
+  A.9, "VMCS Enumeration.". If CPUID.01H:ECX.[5] = 1.
+
+  @param  ECX  MSR_IA32_VMX_VMCS_ENUM (0x0000048A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_VMX_VMCS_ENUM);
+  @endcode
+  @note MSR_IA32_VMX_VMCS_ENUM is defined as IA32_VMX_VMCS_ENUM in SDM.
+**/
+#define MSR_IA32_VMX_VMCS_ENUM                   0x0000048A
+
+
+/**
+  Capability Reporting Register of  Secondary Processor-based  VM-execution
+  Controls (R/O) See Appendix A.3.3, "Secondary Processor- Based VM-Execution
+  Controls.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C TLS[63]).
+
+  @param  ECX  MSR_IA32_VMX_PROCBASED_CTLS2 (0x0000048B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS2);
+  @endcode
+  @note MSR_IA32_VMX_PROCBASED_CTLS2 is defined as IA32_VMX_PROCBASED_CTLS2 in SDM.
+**/
+#define MSR_IA32_VMX_PROCBASED_CTLS2             0x0000048B
+
+
+/**
+  Capability Reporting Register of EPT and  VPID (R/O) See Appendix A.10,
+  "VPID and EPT Capabilities.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C
+  TLS[63] && ( IA32_VMX_PROCBASED_C TLS2[33] IA32_VMX_PROCBASED_C TLS2[37]) ).
+
+  @param  ECX  MSR_IA32_VMX_EPT_VPID_CAP (0x0000048C)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_VMX_EPT_VPID_CAP);
+  @endcode
+  @note MSR_IA32_VMX_EPT_VPID_CAP is defined as IA32_VMX_EPT_VPID_CAP in SDM.
+**/
+#define MSR_IA32_VMX_EPT_VPID_CAP                0x0000048C
+
+
+/**
+  Capability Reporting Register of Pinbased VM-execution Flex Controls (R/O)
+  See Appendix A.3.1, "Pin-Based VMExecution Controls.". If (
+  CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
+
+  @param  ECX  MSR_IA32_VMX_TRUE_PINBASED_CTLS (0x0000048D)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PINBASED_CTLS);
+  @endcode
+  @note MSR_IA32_VMX_TRUE_PINBASED_CTLS is defined as IA32_VMX_TRUE_PINBASED_CTLS in SDM.
+**/
+#define MSR_IA32_VMX_TRUE_PINBASED_CTLS          0x0000048D
+
+
+/**
+  Capability Reporting Register of Primary  Processor-based VM-execution Flex
+  Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution
+  Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
+
+  @param  ECX  MSR_IA32_VMX_TRUE_PROCBASED_CTLS (0x0000048E)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PROCBASED_CTLS);
+  @endcode
+  @note MSR_IA32_VMX_TRUE_PROCBASED_CTLS is defined as IA32_VMX_TRUE_PROCBASED_CTLS in SDM.
+**/
+#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS         0x0000048E
+
+
+/**
+  Capability Reporting Register of VM-exit  Flex Controls (R/O) See Appendix
+  A.4, "VM-Exit Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
+
+  @param  ECX  MSR_IA32_VMX_TRUE_EXIT_CTLS (0x0000048F)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_EXIT_CTLS);
+  @endcode
+  @note MSR_IA32_VMX_TRUE_EXIT_CTLS is defined as IA32_VMX_TRUE_EXIT_CTLS in SDM.
+**/
+#define MSR_IA32_VMX_TRUE_EXIT_CTLS              0x0000048F
+
+
+/**
+  Capability Reporting Register of VMentry Flex Controls (R/O) See Appendix
+  A.5, "VM-Entry Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
+
+  @param  ECX  MSR_IA32_VMX_TRUE_ENTRY_CTLS (0x00000490)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_ENTRY_CTLS);
+  @endcode
+  @note MSR_IA32_VMX_TRUE_ENTRY_CTLS is defined as IA32_VMX_TRUE_ENTRY_CTLS in SDM.
+**/
+#define MSR_IA32_VMX_TRUE_ENTRY_CTLS             0x00000490
+
+
+/**
+  Capability Reporting Register of VMfunction Controls (R/O). If(
+  CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
+
+  @param  ECX  MSR_IA32_VMX_VMFUNC (0x00000491)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_VMX_VMFUNC);
+  @endcode
+  @note MSR_IA32_VMX_VMFUNC is defined as IA32_VMX_VMFUNC in SDM.
+**/
+#define MSR_IA32_VMX_VMFUNC                      0x00000491
+
+
+/**
+  Full Width Writable IA32_PMCn Alias (R/W). (If CPUID.0AH: EAX[15:8] > n) &&
+  IA32_PERF_CAPABILITIES[ 13] = 1.
+
+  @param  ECX  MSR_IA32_A_PMCn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_A_PMC0);
+  AsmWriteMsr64 (MSR_IA32_A_PMC0, Msr);
+  @endcode
+  @note MSR_IA32_A_PMC0 is defined as IA32_A_PMC0 in SDM.
+        MSR_IA32_A_PMC1 is defined as IA32_A_PMC1 in SDM.
+        MSR_IA32_A_PMC2 is defined as IA32_A_PMC2 in SDM.
+        MSR_IA32_A_PMC3 is defined as IA32_A_PMC3 in SDM.
+        MSR_IA32_A_PMC4 is defined as IA32_A_PMC4 in SDM.
+        MSR_IA32_A_PMC5 is defined as IA32_A_PMC5 in SDM.
+        MSR_IA32_A_PMC6 is defined as IA32_A_PMC6 in SDM.
+        MSR_IA32_A_PMC7 is defined as IA32_A_PMC7 in SDM.
+  @{
+**/
+#define MSR_IA32_A_PMC0                          0x000004C1
+#define MSR_IA32_A_PMC1                          0x000004C2
+#define MSR_IA32_A_PMC2                          0x000004C3
+#define MSR_IA32_A_PMC3                          0x000004C4
+#define MSR_IA32_A_PMC4                          0x000004C5
+#define MSR_IA32_A_PMC5                          0x000004C6
+#define MSR_IA32_A_PMC6                          0x000004C7
+#define MSR_IA32_A_PMC7                          0x000004C8
+/// @}
+
+
+/**
+  (R/W). If IA32_MCG_CAP.LMCE_P =1.
+
+  @param  ECX  MSR_IA32_MCG_EXT_CTL (0x000004D0)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_MCG_EXT_CTL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_EXT_CTL);
+  AsmWriteMsr64 (MSR_IA32_MCG_EXT_CTL, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_MCG_EXT_CTL is defined as IA32_MCG_EXT_CTL in SDM.
+**/
+#define MSR_IA32_MCG_EXT_CTL                     0x000004D0
+
+/**
+  MSR information returned for MSR index #MSR_IA32_MCG_EXT_CTL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] LMCE_EN.
+    ///
+    UINT32  LMCE_EN:1;
+    UINT32  Reserved1:31;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_MCG_EXT_CTL_REGISTER;
+
+
+/**
+  Status and SVN Threshold of SGX Support for ACM (RO). If CPUID.(EAX=07H,
+  ECX=0H): EBX[2] = 1.
+
+  @param  ECX  MSR_IA32_SGX_SVN_STATUS (0x00000500)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_SGX_SVN_STATUS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SGX_SVN_STATUS);
+  @endcode
+  @note MSR_IA32_SGX_SVN_STATUS is defined as IA32_SGX_SVN_STATUS in SDM.
+**/
+#define MSR_IA32_SGX_SVN_STATUS                  0x00000500
+
+/**
+  MSR information returned for MSR index #MSR_IA32_SGX_SVN_STATUS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Lock. See Section 41.11.3, "Interactions with Authenticated
+    /// Code Modules (ACMs)".
+    ///
+    UINT32  Lock:1;
+    UINT32  Reserved1:15;
+    ///
+    /// [Bits 23:16] SGX_SVN_SINIT. See Section 41.11.3, "Interactions with
+    /// Authenticated Code Modules (ACMs)".
+    ///
+    UINT32  SGX_SVN_SINIT:8;
+    UINT32  Reserved2:8;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_SGX_SVN_STATUS_REGISTER;
+
+
+/**
+  Trace Output Base Register (R/W). If ((CPUID.(EAX=07H, ECX=0):EBX[25] = 1)
+  && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1) (CPUID.(EAX=14H,ECX=0): ECX[2] = 1)
+  ) ).
+
+  @param  ECX  MSR_IA32_RTIT_OUTPUT_BASE (0x00000560)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_RTIT_OUTPUT_BASE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_BASE);
+  AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_BASE, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_RTIT_OUTPUT_BASE is defined as IA32_RTIT_OUTPUT_BASE in SDM.
+**/
+#define MSR_IA32_RTIT_OUTPUT_BASE                0x00000560
+
+/**
+  MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_BASE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved:7;
+    ///
+    /// [Bits 31:7] Base physical address.
+    ///
+    UINT32  Base:25;
+    ///
+    /// [Bits 63:32] Base physical address.
+    ///
+    UINT32  BaseHi:32;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_RTIT_OUTPUT_BASE_REGISTER;
+
+
+/**
+  Trace Output Mask Pointers Register (R/W). If ((CPUID.(EAX=07H,
+  ECX=0):EBX[25] = 1) && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1)
+  (CPUID.(EAX=14H,ECX=0): ECX[2] = 1) ) ).
+
+  @param  ECX  MSR_IA32_RTIT_OUTPUT_MASK_PTRS (0x00000561)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS);
+  AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_RTIT_OUTPUT_MASK_PTRS is defined as IA32_RTIT_OUTPUT_MASK_PTRS in SDM.
+**/
+#define MSR_IA32_RTIT_OUTPUT_MASK_PTRS           0x00000561
+
+/**
+  MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_MASK_PTRS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved:7;
+    ///
+    /// [Bits 31:7] MaskOrTableOffset.
+    ///
+    UINT32  MaskOrTableOffset:25;
+    ///
+    /// [Bits 63:32] Output Offset.
+    ///
+    UINT32  OutputOffset:32;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER;
+
+/**
+  Format of ToPA table entries.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] END. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".
+    ///
+    UINT32  END:1;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 2] INT. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".
+    ///
+    UINT32  INT:1;
+    UINT32  Reserved2:1;
+    ///
+    /// [Bit 4] STOP. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".
+    ///
+    UINT32  STOP:1;
+    UINT32  Reserved3:1;
+    ///
+    /// [Bit 6:9] Indicates the size of the associated output region. See Section
+    /// 35.2.6.2, "Table of Physical Addresses (ToPA)".
+    ///
+    UINT32  Size:4;
+    UINT32  Reserved4:2;
+    ///
+    /// [Bit 12:31] Output Region Base Physical Address low part.
+    /// [Bit 12:31] Output Region Base Physical Address [12:63] value to match.
+    /// ATTENTION: The size of the address field is determined by the processor's
+    /// physical-address width (MAXPHYADDR) in bits, as reported in
+    /// CPUID.80000008H:EAX[7:0]. the above part of address reserved.
+    /// True address field is [12:MAXPHYADDR-1], [MAXPHYADDR:63] is reserved part.
+    /// Detail see Section 35.2.6.2, "Table of Physical Addresses (ToPA)".
+    ///
+    UINT32  Base:20;
+    ///
+    /// [Bit 32:63] Output Region Base Physical Address high part.
+    /// [Bit 32:63] Output Region Base Physical Address [12:63] value to match.
+    /// ATTENTION: The size of the address field is determined by the processor's
+    /// physical-address width (MAXPHYADDR) in bits, as reported in
+    /// CPUID.80000008H:EAX[7:0]. the above part of address reserved.
+    /// True address field is [12:MAXPHYADDR-1], [MAXPHYADDR:63] is reserved part.
+    /// Detail see Section 35.2.6.2, "Table of Physical Addresses (ToPA)".
+    ///
+    UINT32  BaseHi:32;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} RTIT_TOPA_TABLE_ENTRY;
+
+///
+/// The size of the associated output region usd by Topa.
+///
+typedef enum {
+  RtitTopaMemorySize4K = 0,
+  RtitTopaMemorySize8K,
+  RtitTopaMemorySize16K,
+  RtitTopaMemorySize32K,
+  RtitTopaMemorySize64K,
+  RtitTopaMemorySize128K,
+  RtitTopaMemorySize256K,
+  RtitTopaMemorySize512K,
+  RtitTopaMemorySize1M,
+  RtitTopaMemorySize2M,
+  RtitTopaMemorySize4M,
+  RtitTopaMemorySize8M,
+  RtitTopaMemorySize16M,
+  RtitTopaMemorySize32M,
+  RtitTopaMemorySize64M,
+  RtitTopaMemorySize128M
+} RTIT_TOPA_MEMORY_SIZE;
+
+/**
+  Trace Control Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).
+
+  @param  ECX  MSR_IA32_RTIT_CTL (0x00000570)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_RTIT_CTL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_RTIT_CTL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_RTIT_CTL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);
+  AsmWriteMsr64 (MSR_IA32_RTIT_CTL, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_RTIT_CTL is defined as IA32_RTIT_CTL in SDM.
+**/
+#define MSR_IA32_RTIT_CTL                        0x00000570
+
+/**
+  MSR information returned for MSR index #MSR_IA32_RTIT_CTL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] TraceEn.
+    ///
+    UINT32  TraceEn:1;
+    ///
+    /// [Bit 1] CYCEn. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).
+    ///
+    UINT32  CYCEn:1;
+    ///
+    /// [Bit 2] OS.
+    ///
+    UINT32  OS:1;
+    ///
+    /// [Bit 3] User.
+    ///
+    UINT32  User:1;
+    ///
+    /// [Bit 4] PwrEvtEn.
+    ///
+    UINT32  PwrEvtEn:1;
+    ///
+    /// [Bit 5] FUPonPTW.
+    ///
+    UINT32  FUPonPTW:1;
+    ///
+    /// [Bit 6] FabricEn. If (CPUID.(EAX=07H, ECX=0):ECX[3] = 1).
+    ///
+    UINT32  FabricEn:1;
+    ///
+    /// [Bit 7] CR3 filter.
+    ///
+    UINT32  CR3:1;
+    ///
+    /// [Bit 8] ToPA.
+    ///
+    UINT32  ToPA:1;
+    ///
+    /// [Bit 9] MTCEn. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).
+    ///
+    UINT32  MTCEn:1;
+    ///
+    /// [Bit 10] TSCEn.
+    ///
+    UINT32  TSCEn:1;
+    ///
+    /// [Bit 11] DisRETC.
+    ///
+    UINT32  DisRETC:1;
+    ///
+    /// [Bit 12] PTWEn.
+    ///
+    UINT32  PTWEn:1;
+    ///
+    /// [Bit 13] BranchEn.
+    ///
+    UINT32  BranchEn:1;
+    ///
+    /// [Bits 17:14] MTCFreq. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).
+    ///
+    UINT32  MTCFreq:4;
+    UINT32  Reserved3:1;
+    ///
+    /// [Bits 22:19] CYCThresh. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).
+    ///
+    UINT32  CYCThresh:4;
+    UINT32  Reserved4:1;
+    ///
+    /// [Bits 27:24] PSBFreq. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).
+    ///
+    UINT32  PSBFreq:4;
+    UINT32  Reserved5:4;
+    ///
+    /// [Bits 35:32] ADDR0_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 0).
+    ///
+    UINT32  ADDR0_CFG:4;
+    ///
+    /// [Bits 39:36] ADDR1_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 1).
+    ///
+    UINT32  ADDR1_CFG:4;
+    ///
+    /// [Bits 43:40] ADDR2_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 2).
+    ///
+    UINT32  ADDR2_CFG:4;
+    ///
+    /// [Bits 47:44] ADDR3_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 3).
+    ///
+    UINT32  ADDR3_CFG:4;
+    UINT32  Reserved6:16;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_RTIT_CTL_REGISTER;
+
+
+/**
+  Tracing Status Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).
+
+  @param  ECX  MSR_IA32_RTIT_STATUS (0x00000571)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_RTIT_STATUS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_RTIT_STATUS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_RTIT_STATUS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_STATUS);
+  AsmWriteMsr64 (MSR_IA32_RTIT_STATUS, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_RTIT_STATUS is defined as IA32_RTIT_STATUS in SDM.
+**/
+#define MSR_IA32_RTIT_STATUS                     0x00000571
+
+/**
+  MSR information returned for MSR index #MSR_IA32_RTIT_STATUS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] FilterEn, (writes ignored).
+    /// If (CPUID.(EAX=07H, ECX=0):EBX[2] = 1).
+    ///
+    UINT32  FilterEn:1;
+    ///
+    /// [Bit 1] ContexEn, (writes ignored).
+    ///
+    UINT32  ContexEn:1;
+    ///
+    /// [Bit 2] TriggerEn, (writes ignored).
+    ///
+    UINT32  TriggerEn:1;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 4] Error.
+    ///
+    UINT32  Error:1;
+    ///
+    /// [Bit 5] Stopped.
+    ///
+    UINT32  Stopped:1;
+    UINT32  Reserved2:26;
+    ///
+    /// [Bits 48:32] PacketByteCnt. If (CPUID.(EAX=07H, ECX=0):EBX[1] > 3).
+    ///
+    UINT32  PacketByteCnt:17;
+    UINT32  Reserved3:15;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_RTIT_STATUS_REGISTER;
+
+
+/**
+  Trace Filter CR3 Match Register (R/W).
+  If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).
+
+  @param  ECX  MSR_IA32_RTIT_CR3_MATCH (0x00000572)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_RTIT_CR3_MATCH_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CR3_MATCH);
+  AsmWriteMsr64 (MSR_IA32_RTIT_CR3_MATCH, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_RTIT_CR3_MATCH is defined as IA32_RTIT_CR3_MATCH in SDM.
+**/
+#define MSR_IA32_RTIT_CR3_MATCH                  0x00000572
+
+/**
+  MSR information returned for MSR index #MSR_IA32_RTIT_CR3_MATCH
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved:5;
+    ///
+    /// [Bits 31:5] CR3[63:5] value to match.
+    ///
+    UINT32  Cr3:27;
+    ///
+    /// [Bits 63:32] CR3[63:5] value to match.
+    ///
+    UINT32  Cr3Hi:32;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_RTIT_CR3_MATCH_REGISTER;
+
+
+/**
+  Region n Start Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).
+
+  @param  ECX  MSR_IA32_RTIT_ADDRn_A
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_RTIT_ADDR_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_A);
+  AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_A, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_RTIT_ADDR0_A is defined as IA32_RTIT_ADDR0_A in SDM.
+        MSR_IA32_RTIT_ADDR1_A is defined as IA32_RTIT_ADDR1_A in SDM.
+        MSR_IA32_RTIT_ADDR2_A is defined as IA32_RTIT_ADDR2_A in SDM.
+        MSR_IA32_RTIT_ADDR3_A is defined as IA32_RTIT_ADDR3_A in SDM.
+  @{
+**/
+#define MSR_IA32_RTIT_ADDR0_A                    0x00000580
+#define MSR_IA32_RTIT_ADDR1_A                    0x00000582
+#define MSR_IA32_RTIT_ADDR2_A                    0x00000584
+#define MSR_IA32_RTIT_ADDR3_A                    0x00000586
+/// @}
+
+
+/**
+  Region n End Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).
+
+  @param  ECX  MSR_IA32_RTIT_ADDRn_B
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_RTIT_ADDR_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_B);
+  AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_B, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_RTIT_ADDR0_B is defined as IA32_RTIT_ADDR0_B in SDM.
+        MSR_IA32_RTIT_ADDR1_B is defined as IA32_RTIT_ADDR1_B in SDM.
+        MSR_IA32_RTIT_ADDR2_B is defined as IA32_RTIT_ADDR2_B in SDM.
+        MSR_IA32_RTIT_ADDR3_B is defined as IA32_RTIT_ADDR3_B in SDM.
+  @{
+**/
+#define MSR_IA32_RTIT_ADDR0_B                    0x00000581
+#define MSR_IA32_RTIT_ADDR1_B                    0x00000583
+#define MSR_IA32_RTIT_ADDR2_B                    0x00000585
+#define MSR_IA32_RTIT_ADDR3_B                    0x00000587
+/// @}
+
+
+/**
+  MSR information returned for MSR indexes
+  #MSR_IA32_RTIT_ADDR0_A to #MSR_IA32_RTIT_ADDR3_A and
+  #MSR_IA32_RTIT_ADDR0_B to #MSR_IA32_RTIT_ADDR3_B
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 31:0] Virtual Address.
+    ///
+    UINT32  VirtualAddress:32;
+    ///
+    /// [Bits 47:32] Virtual Address.
+    ///
+    UINT32  VirtualAddressHi:16;
+    ///
+    /// [Bits 63:48] SignExt_VA.
+    ///
+    UINT32  SignExt_VA:16;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_RTIT_ADDR_REGISTER;
+
+
+/**
+  DS Save Area (R/W) Points to the linear address of the first byte of the DS
+  buffer management area, which is used to manage the BTS and PEBS buffers.
+  See Section 18.6.3.4, "Debug Store (DS) Mechanism.". If(
+  CPUID.01H:EDX.DS[21] = 1. The linear address of the first byte of the DS
+  buffer management area, if IA-32e mode is active.
+
+  @param  ECX  MSR_IA32_DS_AREA (0x00000600)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_DS_AREA_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_DS_AREA_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_DS_AREA);
+  AsmWriteMsr64 (MSR_IA32_DS_AREA, Msr);
+  @endcode
+  @note MSR_IA32_DS_AREA is defined as IA32_DS_AREA in SDM.
+**/
+#define MSR_IA32_DS_AREA                         0x00000600
+
+
+/**
+  TSC Target of Local APIC's TSC Deadline Mode (R/W). If CPUID.01H:ECX.[24] =
+  1.
+
+  @param  ECX  MSR_IA32_TSC_DEADLINE (0x000006E0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_TSC_DEADLINE);
+  AsmWriteMsr64 (MSR_IA32_TSC_DEADLINE, Msr);
+  @endcode
+  @note MSR_IA32_TSC_DEADLINE is defined as IA32_TSC_DEADLINE in SDM.
+**/
+#define MSR_IA32_TSC_DEADLINE                    0x000006E0
+
+
+/**
+  Enable/disable HWP (R/W). If CPUID.06H:EAX.[7] = 1.
+
+  @param  ECX  MSR_IA32_PM_ENABLE (0x00000770)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_PM_ENABLE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_PM_ENABLE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_PM_ENABLE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_ENABLE);
+  AsmWriteMsr64 (MSR_IA32_PM_ENABLE, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_PM_ENABLE is defined as IA32_PM_ENABLE in SDM.
+**/
+#define MSR_IA32_PM_ENABLE                       0x00000770
+
+/**
+  MSR information returned for MSR index #MSR_IA32_PM_ENABLE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] HWP_ENABLE (R/W1-Once). See Section 14.4.2, "Enabling HWP". If
+    /// CPUID.06H:EAX.[7] = 1.
+    ///
+    UINT32  HWP_ENABLE:1;
+    UINT32  Reserved1:31;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_PM_ENABLE_REGISTER;
+
+
+/**
+  HWP Performance Range Enumeration (RO). If CPUID.06H:EAX.[7] = 1.
+
+  @param  ECX  MSR_IA32_HWP_CAPABILITIES (0x00000771)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_HWP_CAPABILITIES_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_CAPABILITIES);
+  @endcode
+  @note MSR_IA32_HWP_CAPABILITIES is defined as IA32_HWP_CAPABILITIES in SDM.
+**/
+#define MSR_IA32_HWP_CAPABILITIES                0x00000771
+
+/**
+  MSR information returned for MSR index #MSR_IA32_HWP_CAPABILITIES
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Highest_Performance See Section 14.4.3, "HWP Performance
+    /// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
+    ///
+    UINT32  Highest_Performance:8;
+    ///
+    /// [Bits 15:8] Guaranteed_Performance See Section 14.4.3, "HWP
+    /// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
+    ///
+    UINT32  Guaranteed_Performance:8;
+    ///
+    /// [Bits 23:16] Most_Efficient_Performance See Section 14.4.3, "HWP
+    /// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
+    ///
+    UINT32  Most_Efficient_Performance:8;
+    ///
+    /// [Bits 31:24] Lowest_Performance See Section 14.4.3, "HWP Performance
+    /// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
+    ///
+    UINT32  Lowest_Performance:8;
+    UINT32  Reserved:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_HWP_CAPABILITIES_REGISTER;
+
+
+/**
+  Power Management Control Hints for All Logical Processors in a Package
+  (R/W). If CPUID.06H:EAX.[11] = 1.
+
+  @param  ECX  MSR_IA32_HWP_REQUEST_PKG (0x00000772)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_HWP_REQUEST_PKG_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST_PKG);
+  AsmWriteMsr64 (MSR_IA32_HWP_REQUEST_PKG, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_HWP_REQUEST_PKG is defined as IA32_HWP_REQUEST_PKG in SDM.
+**/
+#define MSR_IA32_HWP_REQUEST_PKG                 0x00000772
+
+/**
+  MSR information returned for MSR index #MSR_IA32_HWP_REQUEST_PKG
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If
+    /// CPUID.06H:EAX.[11] = 1.
+    ///
+    UINT32  Minimum_Performance:8;
+    ///
+    /// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If
+    /// CPUID.06H:EAX.[11] = 1.
+    ///
+    UINT32  Maximum_Performance:8;
+    ///
+    /// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP".
+    /// If CPUID.06H:EAX.[11] = 1.
+    ///
+    UINT32  Desired_Performance:8;
+    ///
+    /// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4,
+    /// "Managing HWP". If CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[10] = 1.
+    ///
+    UINT32  Energy_Performance_Preference:8;
+    ///
+    /// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If
+    /// CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[9] = 1.
+    ///
+    UINT32  Activity_Window:10;
+    UINT32  Reserved:22;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_HWP_REQUEST_PKG_REGISTER;
+
+
+/**
+  Control HWP Native Interrupts (R/W). If CPUID.06H:EAX.[8] = 1.
+
+  @param  ECX  MSR_IA32_HWP_INTERRUPT (0x00000773)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_HWP_INTERRUPT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_INTERRUPT);
+  AsmWriteMsr64 (MSR_IA32_HWP_INTERRUPT, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_HWP_INTERRUPT is defined as IA32_HWP_INTERRUPT in SDM.
+**/
+#define MSR_IA32_HWP_INTERRUPT                   0x00000773
+
+/**
+  MSR information returned for MSR index #MSR_IA32_HWP_INTERRUPT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] EN_Guaranteed_Performance_Change. See Section 14.4.6, "HWP
+    /// Notifications". If CPUID.06H:EAX.[8] = 1.
+    ///
+    UINT32  EN_Guaranteed_Performance_Change:1;
+    ///
+    /// [Bit 1] EN_Excursion_Minimum. See Section 14.4.6, "HWP Notifications".
+    /// If CPUID.06H:EAX.[8] = 1.
+    ///
+    UINT32  EN_Excursion_Minimum:1;
+    UINT32  Reserved1:30;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_HWP_INTERRUPT_REGISTER;
+
+
+/**
+  Power Management Control Hints to a Logical Processor (R/W). If
+  CPUID.06H:EAX.[7] = 1.
+
+  @param  ECX  MSR_IA32_HWP_REQUEST (0x00000774)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_HWP_REQUEST_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_HWP_REQUEST_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_HWP_REQUEST_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST);
+  AsmWriteMsr64 (MSR_IA32_HWP_REQUEST, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_HWP_REQUEST is defined as IA32_HWP_REQUEST in SDM.
+**/
+#define MSR_IA32_HWP_REQUEST                     0x00000774
+
+/**
+  MSR information returned for MSR index #MSR_IA32_HWP_REQUEST
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If
+    /// CPUID.06H:EAX.[7] = 1.
+    ///
+    UINT32  Minimum_Performance:8;
+    ///
+    /// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If
+    /// CPUID.06H:EAX.[7] = 1.
+    ///
+    UINT32  Maximum_Performance:8;
+    ///
+    /// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP".
+    /// If CPUID.06H:EAX.[7] = 1.
+    ///
+    UINT32  Desired_Performance:8;
+    ///
+    /// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4,
+    /// "Managing HWP". If CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[10] = 1.
+    ///
+    UINT32  Energy_Performance_Preference:8;
+    ///
+    /// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If
+    /// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[9] = 1.
+    ///
+    UINT32  Activity_Window:10;
+    ///
+    /// [Bit 42] Package_Control See Section 14.4.4, "Managing HWP". If
+    /// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[11] = 1.
+    ///
+    UINT32  Package_Control:1;
+    UINT32  Reserved:21;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_HWP_REQUEST_REGISTER;
+
+
+/**
+  Log bits indicating changes to  Guaranteed & excursions to Minimum (R/W). If
+  CPUID.06H:EAX.[7] = 1.
+
+  @param  ECX  MSR_IA32_HWP_STATUS (0x00000777)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_HWP_STATUS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_HWP_STATUS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_HWP_STATUS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_STATUS);
+  AsmWriteMsr64 (MSR_IA32_HWP_STATUS, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_HWP_STATUS is defined as IA32_HWP_STATUS in SDM.
+**/
+#define MSR_IA32_HWP_STATUS                      0x00000777
+
+/**
+  MSR information returned for MSR index #MSR_IA32_HWP_STATUS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Guaranteed_Performance_Change (R/WC0). See Section 14.4.5,
+    /// "HWP Feedback". If CPUID.06H:EAX.[7] = 1.
+    ///
+    UINT32  Guaranteed_Performance_Change:1;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 2] Excursion_To_Minimum (R/WC0). See Section 14.4.5, "HWP
+    /// Feedback". If CPUID.06H:EAX.[7] = 1.
+    ///
+    UINT32  Excursion_To_Minimum:1;
+    UINT32  Reserved2:29;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_HWP_STATUS_REGISTER;
+
+
+/**
+  x2APIC ID Register (R/O) See x2APIC Specification. If CPUID.01H:ECX[21] = 1
+  && IA32_APIC_BASE.[10] = 1.
+
+  @param  ECX  MSR_IA32_X2APIC_APICID (0x00000802)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_X2APIC_APICID);
+  @endcode
+  @note MSR_IA32_X2APIC_APICID is defined as IA32_X2APIC_APICID in SDM.
+**/
+#define MSR_IA32_X2APIC_APICID                   0x00000802
+
+
+/**
+  x2APIC Version Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
+  IA32_APIC_BASE.[10] = 1.
+
+  @param  ECX  MSR_IA32_X2APIC_VERSION (0x00000803)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_X2APIC_VERSION);
+  @endcode
+  @note MSR_IA32_X2APIC_VERSION is defined as IA32_X2APIC_VERSION in SDM.
+**/
+#define MSR_IA32_X2APIC_VERSION                  0x00000803
+
+
+/**
+  x2APIC Task Priority Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
+  IA32_APIC_BASE.[10] = 1.
+
+  @param  ECX  MSR_IA32_X2APIC_TPR (0x00000808)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TPR);
+  AsmWriteMsr64 (MSR_IA32_X2APIC_TPR, Msr);
+  @endcode
+  @note MSR_IA32_X2APIC_TPR is defined as IA32_X2APIC_TPR in SDM.
+**/
+#define MSR_IA32_X2APIC_TPR                      0x00000808
+
+
+/**
+  x2APIC Processor Priority Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
+  IA32_APIC_BASE.[10] = 1.
+
+  @param  ECX  MSR_IA32_X2APIC_PPR (0x0000080A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_X2APIC_PPR);
+  @endcode
+  @note MSR_IA32_X2APIC_PPR is defined as IA32_X2APIC_PPR in SDM.
+**/
+#define MSR_IA32_X2APIC_PPR                      0x0000080A
+
+
+/**
+  x2APIC EOI Register (W/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10]
+  = 1.
+
+  @param  ECX  MSR_IA32_X2APIC_EOI (0x0000080B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = 0;
+  AsmWriteMsr64 (MSR_IA32_X2APIC_EOI, Msr);
+  @endcode
+  @note MSR_IA32_X2APIC_EOI is defined as IA32_X2APIC_EOI in SDM.
+**/
+#define MSR_IA32_X2APIC_EOI                      0x0000080B
+
+
+/**
+  x2APIC Logical Destination Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
+  IA32_APIC_BASE.[10] = 1.
+
+  @param  ECX  MSR_IA32_X2APIC_LDR (0x0000080D)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LDR);
+  @endcode
+  @note MSR_IA32_X2APIC_LDR is defined as IA32_X2APIC_LDR in SDM.
+**/
+#define MSR_IA32_X2APIC_LDR                      0x0000080D
+
+
+/**
+  x2APIC Spurious Interrupt Vector Register (R/W). If CPUID.01H:ECX.[21] = 1
+  && IA32_APIC_BASE.[10] = 1.
+
+  @param  ECX  MSR_IA32_X2APIC_SIVR (0x0000080F)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_X2APIC_SIVR);
+  AsmWriteMsr64 (MSR_IA32_X2APIC_SIVR, Msr);
+  @endcode
+  @note MSR_IA32_X2APIC_SIVR is defined as IA32_X2APIC_SIVR in SDM.
+**/
+#define MSR_IA32_X2APIC_SIVR                     0x0000080F
+
+
+/**
+  x2APIC In-Service Register Bits (n * 32 + 31):(n * 32) (R/O).
+  If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
+
+  @param  ECX  MSR_IA32_X2APIC_ISRn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ISR0);
+  @endcode
+  @note MSR_IA32_X2APIC_ISR0 is defined as IA32_X2APIC_ISR0 in SDM.
+        MSR_IA32_X2APIC_ISR1 is defined as IA32_X2APIC_ISR1 in SDM.
+        MSR_IA32_X2APIC_ISR2 is defined as IA32_X2APIC_ISR2 in SDM.
+        MSR_IA32_X2APIC_ISR3 is defined as IA32_X2APIC_ISR3 in SDM.
+        MSR_IA32_X2APIC_ISR4 is defined as IA32_X2APIC_ISR4 in SDM.
+        MSR_IA32_X2APIC_ISR5 is defined as IA32_X2APIC_ISR5 in SDM.
+        MSR_IA32_X2APIC_ISR6 is defined as IA32_X2APIC_ISR6 in SDM.
+        MSR_IA32_X2APIC_ISR7 is defined as IA32_X2APIC_ISR7 in SDM.
+  @{
+**/
+#define MSR_IA32_X2APIC_ISR0                     0x00000810
+#define MSR_IA32_X2APIC_ISR1                     0x00000811
+#define MSR_IA32_X2APIC_ISR2                     0x00000812
+#define MSR_IA32_X2APIC_ISR3                     0x00000813
+#define MSR_IA32_X2APIC_ISR4                     0x00000814
+#define MSR_IA32_X2APIC_ISR5                     0x00000815
+#define MSR_IA32_X2APIC_ISR6                     0x00000816
+#define MSR_IA32_X2APIC_ISR7                     0x00000817
+/// @}
+
+
+/**
+  x2APIC Trigger Mode Register Bits (n * 32 + ):(n * 32) (R/O).
+  If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
+
+  @param  ECX  MSR_IA32_X2APIC_TMRn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TMR0);
+  @endcode
+  @note MSR_IA32_X2APIC_TMR0 is defined as IA32_X2APIC_TMR0 in SDM.
+        MSR_IA32_X2APIC_TMR1 is defined as IA32_X2APIC_TMR1 in SDM.
+        MSR_IA32_X2APIC_TMR2 is defined as IA32_X2APIC_TMR2 in SDM.
+        MSR_IA32_X2APIC_TMR3 is defined as IA32_X2APIC_TMR3 in SDM.
+        MSR_IA32_X2APIC_TMR4 is defined as IA32_X2APIC_TMR4 in SDM.
+        MSR_IA32_X2APIC_TMR5 is defined as IA32_X2APIC_TMR5 in SDM.
+        MSR_IA32_X2APIC_TMR6 is defined as IA32_X2APIC_TMR6 in SDM.
+        MSR_IA32_X2APIC_TMR7 is defined as IA32_X2APIC_TMR7 in SDM.
+  @{
+**/
+#define MSR_IA32_X2APIC_TMR0                     0x00000818
+#define MSR_IA32_X2APIC_TMR1                     0x00000819
+#define MSR_IA32_X2APIC_TMR2                     0x0000081A
+#define MSR_IA32_X2APIC_TMR3                     0x0000081B
+#define MSR_IA32_X2APIC_TMR4                     0x0000081C
+#define MSR_IA32_X2APIC_TMR5                     0x0000081D
+#define MSR_IA32_X2APIC_TMR6                     0x0000081E
+#define MSR_IA32_X2APIC_TMR7                     0x0000081F
+/// @}
+
+
+/**
+  x2APIC Interrupt Request Register Bits (n* 32 + 31):(n * 32) (R/O).
+  If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
+
+  @param  ECX  MSR_IA32_X2APIC_IRRn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_X2APIC_IRR0);
+  @endcode
+  @note MSR_IA32_X2APIC_IRR0 is defined as IA32_X2APIC_IRR0 in SDM.
+        MSR_IA32_X2APIC_IRR1 is defined as IA32_X2APIC_IRR1 in SDM.
+        MSR_IA32_X2APIC_IRR2 is defined as IA32_X2APIC_IRR2 in SDM.
+        MSR_IA32_X2APIC_IRR3 is defined as IA32_X2APIC_IRR3 in SDM.
+        MSR_IA32_X2APIC_IRR4 is defined as IA32_X2APIC_IRR4 in SDM.
+        MSR_IA32_X2APIC_IRR5 is defined as IA32_X2APIC_IRR5 in SDM.
+        MSR_IA32_X2APIC_IRR6 is defined as IA32_X2APIC_IRR6 in SDM.
+        MSR_IA32_X2APIC_IRR7 is defined as IA32_X2APIC_IRR7 in SDM.
+  @{
+**/
+#define MSR_IA32_X2APIC_IRR0                     0x00000820
+#define MSR_IA32_X2APIC_IRR1                     0x00000821
+#define MSR_IA32_X2APIC_IRR2                     0x00000822
+#define MSR_IA32_X2APIC_IRR3                     0x00000823
+#define MSR_IA32_X2APIC_IRR4                     0x00000824
+#define MSR_IA32_X2APIC_IRR5                     0x00000825
+#define MSR_IA32_X2APIC_IRR6                     0x00000826
+#define MSR_IA32_X2APIC_IRR7                     0x00000827
+/// @}
+
+
+/**
+  x2APIC Error Status Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
+  IA32_APIC_BASE.[10] = 1.
+
+  @param  ECX  MSR_IA32_X2APIC_ESR (0x00000828)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ESR);
+  AsmWriteMsr64 (MSR_IA32_X2APIC_ESR, Msr);
+  @endcode
+  @note MSR_IA32_X2APIC_ESR is defined as IA32_X2APIC_ESR in SDM.
+**/
+#define MSR_IA32_X2APIC_ESR                      0x00000828
+
+
+/**
+  x2APIC LVT Corrected Machine Check Interrupt Register (R/W). If
+  CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
+
+  @param  ECX  MSR_IA32_X2APIC_LVT_CMCI (0x0000082F)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_CMCI);
+  AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_CMCI, Msr);
+  @endcode
+  @note MSR_IA32_X2APIC_LVT_CMCI is defined as IA32_X2APIC_LVT_CMCI in SDM.
+**/
+#define MSR_IA32_X2APIC_LVT_CMCI                 0x0000082F
+
+
+/**
+  x2APIC Interrupt Command Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
+  IA32_APIC_BASE.[10] = 1.
+
+  @param  ECX  MSR_IA32_X2APIC_ICR (0x00000830)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ICR);
+  AsmWriteMsr64 (MSR_IA32_X2APIC_ICR, Msr);
+  @endcode
+  @note MSR_IA32_X2APIC_ICR is defined as IA32_X2APIC_ICR in SDM.
+**/
+#define MSR_IA32_X2APIC_ICR                      0x00000830
+
+
+/**
+  x2APIC LVT Timer Interrupt Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
+  IA32_APIC_BASE.[10] = 1.
+
+  @param  ECX  MSR_IA32_X2APIC_LVT_TIMER (0x00000832)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_TIMER);
+  AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_TIMER, Msr);
+  @endcode
+  @note MSR_IA32_X2APIC_LVT_TIMER is defined as IA32_X2APIC_LVT_TIMER in SDM.
+**/
+#define MSR_IA32_X2APIC_LVT_TIMER                0x00000832
+
+
+/**
+  x2APIC LVT Thermal Sensor Interrupt Register (R/W). If CPUID.01H:ECX.[21] =
+  1 && IA32_APIC_BASE.[10] = 1.
+
+  @param  ECX  MSR_IA32_X2APIC_LVT_THERMAL (0x00000833)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_THERMAL);
+  AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_THERMAL, Msr);
+  @endcode
+  @note MSR_IA32_X2APIC_LVT_THERMAL is defined as IA32_X2APIC_LVT_THERMAL in SDM.
+**/
+#define MSR_IA32_X2APIC_LVT_THERMAL              0x00000833
+
+
+/**
+  x2APIC LVT Performance Monitor Interrupt Register (R/W). If
+  CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
+
+  @param  ECX  MSR_IA32_X2APIC_LVT_PMI (0x00000834)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_PMI);
+  AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_PMI, Msr);
+  @endcode
+  @note MSR_IA32_X2APIC_LVT_PMI is defined as IA32_X2APIC_LVT_PMI in SDM.
+**/
+#define MSR_IA32_X2APIC_LVT_PMI                  0x00000834
+
+
+/**
+  x2APIC LVT LINT0 Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
+  IA32_APIC_BASE.[10] = 1.
+
+  @param  ECX  MSR_IA32_X2APIC_LVT_LINT0 (0x00000835)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT0);
+  AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT0, Msr);
+  @endcode
+  @note MSR_IA32_X2APIC_LVT_LINT0 is defined as IA32_X2APIC_LVT_LINT0 in SDM.
+**/
+#define MSR_IA32_X2APIC_LVT_LINT0                0x00000835
+
+
+/**
+  x2APIC LVT LINT1 Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
+  IA32_APIC_BASE.[10] = 1.
+
+  @param  ECX  MSR_IA32_X2APIC_LVT_LINT1 (0x00000836)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT1);
+  AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT1, Msr);
+  @endcode
+  @note MSR_IA32_X2APIC_LVT_LINT1 is defined as IA32_X2APIC_LVT_LINT1 in SDM.
+**/
+#define MSR_IA32_X2APIC_LVT_LINT1                0x00000836
+
+
+/**
+  x2APIC LVT Error Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
+  IA32_APIC_BASE.[10] = 1.
+
+  @param  ECX  MSR_IA32_X2APIC_LVT_ERROR (0x00000837)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_ERROR);
+  AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_ERROR, Msr);
+  @endcode
+  @note MSR_IA32_X2APIC_LVT_ERROR is defined as IA32_X2APIC_LVT_ERROR in SDM.
+**/
+#define MSR_IA32_X2APIC_LVT_ERROR                0x00000837
+
+
+/**
+  x2APIC Initial Count Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
+  IA32_APIC_BASE.[10] = 1.
+
+  @param  ECX  MSR_IA32_X2APIC_INIT_COUNT (0x00000838)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_X2APIC_INIT_COUNT);
+  AsmWriteMsr64 (MSR_IA32_X2APIC_INIT_COUNT, Msr);
+  @endcode
+  @note MSR_IA32_X2APIC_INIT_COUNT is defined as IA32_X2APIC_INIT_COUNT in SDM.
+**/
+#define MSR_IA32_X2APIC_INIT_COUNT               0x00000838
+
+
+/**
+  x2APIC Current Count Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
+  IA32_APIC_BASE.[10] = 1.
+
+  @param  ECX  MSR_IA32_X2APIC_CUR_COUNT (0x00000839)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_X2APIC_CUR_COUNT);
+  @endcode
+  @note MSR_IA32_X2APIC_CUR_COUNT is defined as IA32_X2APIC_CUR_COUNT in SDM.
+**/
+#define MSR_IA32_X2APIC_CUR_COUNT                0x00000839
+
+
+/**
+  x2APIC Divide Configuration Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
+  IA32_APIC_BASE.[10] = 1.
+
+  @param  ECX  MSR_IA32_X2APIC_DIV_CONF (0x0000083E)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_X2APIC_DIV_CONF);
+  AsmWriteMsr64 (MSR_IA32_X2APIC_DIV_CONF, Msr);
+  @endcode
+  @note MSR_IA32_X2APIC_DIV_CONF is defined as IA32_X2APIC_DIV_CONF in SDM.
+**/
+#define MSR_IA32_X2APIC_DIV_CONF                 0x0000083E
+
+
+/**
+  x2APIC Self IPI Register (W/O). If CPUID.01H:ECX.[21] = 1 &&
+  IA32_APIC_BASE.[10] = 1.
+
+  @param  ECX  MSR_IA32_X2APIC_SELF_IPI (0x0000083F)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = 0;
+  AsmWriteMsr64 (MSR_IA32_X2APIC_SELF_IPI, Msr);
+  @endcode
+  @note MSR_IA32_X2APIC_SELF_IPI is defined as IA32_X2APIC_SELF_IPI in SDM.
+**/
+#define MSR_IA32_X2APIC_SELF_IPI                 0x0000083F
+
+
+/**
+  Silicon Debug Feature Control (R/W). If CPUID.01H:ECX.[11] = 1.
+
+  @param  ECX  MSR_IA32_DEBUG_INTERFACE (0x00000C80)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_DEBUG_INTERFACE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUG_INTERFACE);
+  AsmWriteMsr64 (MSR_IA32_DEBUG_INTERFACE, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_DEBUG_INTERFACE is defined as IA32_DEBUG_INTERFACE in SDM.
+**/
+#define MSR_IA32_DEBUG_INTERFACE                 0x00000C80
+
+/**
+  MSR information returned for MSR index #MSR_IA32_DEBUG_INTERFACE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Enable (R/W) BIOS set 1 to enable Silicon debug features.
+    /// Default is 0. If CPUID.01H:ECX.[11] = 1.
+    ///
+    UINT32  Enable:1;
+    UINT32  Reserved1:29;
+    ///
+    /// [Bit 30] Lock (R/W): If 1, locks any further change to the MSR. The
+    /// lock bit is set automatically on the first SMI assertion even if not
+    /// explicitly set by BIOS. Default is 0. If CPUID.01H:ECX.[11] = 1.
+    ///
+    UINT32  Lock:1;
+    ///
+    /// [Bit 31] Debug Occurred (R/O): This "sticky bit" is set by hardware to
+    /// indicate the status of bit 0. Default is 0. If CPUID.01H:ECX.[11] = 1.
+    ///
+    UINT32  DebugOccurred:1;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_DEBUG_INTERFACE_REGISTER;
+
+
+/**
+  L3 QOS Configuration (R/W). If ( CPUID.(EAX=10H, ECX=1):ECX.[2] = 1 ).
+
+  @param  ECX  MSR_IA32_L3_QOS_CFG (0x00000C81)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_L3_QOS_CFG_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_L3_QOS_CFG_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_L3_QOS_CFG_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_L3_QOS_CFG);
+  AsmWriteMsr64 (MSR_IA32_L3_QOS_CFG, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_L3_QOS_CFG is defined as IA32_L3_QOS_CFG in SDM.
+**/
+#define MSR_IA32_L3_QOS_CFG                      0x00000C81
+
+/**
+  MSR information returned for MSR index #MSR_IA32_L3_QOS_CFG
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Enable (R/W) Set 1 to enable L3 CAT masks and COS to operate
+    /// in Code and Data Prioritization (CDP) mode.
+    ///
+    UINT32  Enable:1;
+    UINT32  Reserved1:31;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_L3_QOS_CFG_REGISTER;
+
+/**
+  L2 QOS Configuration (R/W). If ( CPUID.(EAX=10H, ECX=2):ECX.[2] = 1 ).
+
+  @param  ECX  MSR_IA32_L2_QOS_CFG (0x00000C82)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_L2_QOS_CFG_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_L2_QOS_CFG_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_L2_QOS_CFG_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_L2_QOS_CFG);
+  AsmWriteMsr64 (MSR_IA32_L2_QOS_CFG, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_L2_QOS_CFG is defined as IA32_L2_QOS_CFG in SDM.
+**/
+#define MSR_IA32_L2_QOS_CFG                      0x00000C82
+
+/**
+  MSR information returned for MSR index #MSR_IA32_L2_QOS_CFG
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Enable (R/W) Set 1 to enable L2 CAT masks and COS to operate
+    /// in Code and Data Prioritization (CDP) mode.
+    ///
+    UINT32  Enable:1;
+    UINT32  Reserved1:31;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_L2_QOS_CFG_REGISTER;
+
+/**
+  Monitoring Event Select Register (R/W). If ( CPUID.(EAX=07H, ECX=0):EBX.[12]
+  = 1 ).
+
+  @param  ECX  MSR_IA32_QM_EVTSEL (0x00000C8D)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_QM_EVTSEL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_QM_EVTSEL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_QM_EVTSEL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_EVTSEL);
+  AsmWriteMsr64 (MSR_IA32_QM_EVTSEL, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.
+**/
+#define MSR_IA32_QM_EVTSEL                       0x00000C8D
+
+/**
+  MSR information returned for MSR index #MSR_IA32_QM_EVTSEL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Event ID: ID of a supported monitoring event to report via
+    /// IA32_QM_CTR.
+    ///
+    UINT32  EventID:8;
+    UINT32  Reserved:24;
+    ///
+    /// [Bits 63:32] Resource Monitoring ID: ID for monitoring hardware to
+    /// report monitored data via IA32_QM_CTR. N = Ceil (Log:sub:`2` (
+    /// CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).
+    ///
+    UINT32  ResourceMonitoringID:32;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_QM_EVTSEL_REGISTER;
+
+
+/**
+  Monitoring Counter Register (R/O). If ( CPUID.(EAX=07H, ECX=0):EBX.[12] = 1
+  ).
+
+  @param  ECX  MSR_IA32_QM_CTR (0x00000C8E)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_QM_CTR_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_QM_CTR_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_QM_CTR_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_CTR);
+  @endcode
+  @note MSR_IA32_QM_CTR is defined as IA32_QM_CTR in SDM.
+**/
+#define MSR_IA32_QM_CTR                          0x00000C8E
+
+/**
+  MSR information returned for MSR index #MSR_IA32_QM_CTR
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 31:0] Resource Monitored Data.
+    ///
+    UINT32  ResourceMonitoredData:32;
+    ///
+    /// [Bits 61:32] Resource Monitored Data.
+    ///
+    UINT32  ResourceMonitoredDataHi:30;
+    ///
+    /// [Bit 62] Unavailable: If 1, indicates data for this RMID is not
+    /// available or not monitored for this resource or RMID.
+    ///
+    UINT32  Unavailable:1;
+    ///
+    /// [Bit 63] Error: If 1, indicates and unsupported RMID or event type was
+    /// written to IA32_PQR_QM_EVTSEL.
+    ///
+    UINT32  Error:1;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_QM_CTR_REGISTER;
+
+
+/**
+  Resource Association Register (R/W). If ( (CPUID.(EAX=07H, ECX=0):EBX[12]
+  =1) or (CPUID.(EAX=07H, ECX=0):EBX[15] =1 ) ).
+
+  @param  ECX  MSR_IA32_PQR_ASSOC (0x00000C8F)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_PQR_ASSOC_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_PQR_ASSOC_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_PQR_ASSOC_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PQR_ASSOC);
+  AsmWriteMsr64 (MSR_IA32_PQR_ASSOC, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.
+**/
+#define MSR_IA32_PQR_ASSOC                       0x00000C8F
+
+/**
+  MSR information returned for MSR index #MSR_IA32_PQR_ASSOC
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 31:0] Resource Monitoring ID (R/W): ID for monitoring hardware
+    /// to track internal operation, e.g. memory access. N = Ceil (Log:sub:`2`
+    /// ( CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).
+    ///
+    UINT32  ResourceMonitoringID:32;
+    ///
+    /// [Bits 63:32] COS (R/W). The class of service (COS) to enforce (on
+    /// writes); returns the current COS when read. If ( CPUID.(EAX=07H,
+    /// ECX=0):EBX.[15] = 1 ).
+    ///
+    UINT32  COS:32;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_PQR_ASSOC_REGISTER;
+
+
+/**
+  Supervisor State of MPX Configuration. (R/W). If (CPUID.(EAX=07H,
+  ECX=0H):EBX[14] = 1).
+
+  @param  ECX  MSR_IA32_BNDCFGS (0x00000D90)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_BNDCFGS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_BNDCFGS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_BNDCFGS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BNDCFGS);
+  AsmWriteMsr64 (MSR_IA32_BNDCFGS, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_BNDCFGS is defined as IA32_BNDCFGS in SDM.
+**/
+#define MSR_IA32_BNDCFGS                         0x00000D90
+
+/**
+  MSR information returned for MSR index #MSR_IA32_BNDCFGS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] EN: Enable Intel MPX in supervisor mode.
+    ///
+    UINT32  EN:1;
+    ///
+    /// [Bit 1] BNDPRESERVE: Preserve the bounds registers for near branch
+    /// instructions in the absence of the BND prefix.
+    ///
+    UINT32  BNDPRESERVE:1;
+    UINT32  Reserved:10;
+    ///
+    /// [Bits 31:12] Base Address of Bound Directory.
+    ///
+    UINT32  Base:20;
+    ///
+    /// [Bits 63:32] Base Address of Bound Directory.
+    ///
+    UINT32  BaseHi:32;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_BNDCFGS_REGISTER;
+
+
+/**
+  Extended Supervisor State Mask (R/W). If( CPUID.(0DH, 1):EAX.[3] = 1.
+
+  @param  ECX  MSR_IA32_XSS (0x00000DA0)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_XSS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_XSS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_XSS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_XSS);
+  AsmWriteMsr64 (MSR_IA32_XSS, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_XSS is defined as IA32_XSS in SDM.
+**/
+#define MSR_IA32_XSS                             0x00000DA0
+
+/**
+  MSR information returned for MSR index #MSR_IA32_XSS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:8;
+    ///
+    /// [Bit 8] Trace Packet Configuration State (R/W).
+    ///
+    UINT32  TracePacketConfigurationState:1;
+    UINT32  Reserved2:23;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_XSS_REGISTER;
+
+
+/**
+  Package Level Enable/disable HDC (R/W). If CPUID.06H:EAX.[13] = 1.
+
+  @param  ECX  MSR_IA32_PKG_HDC_CTL (0x00000DB0)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_PKG_HDC_CTL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PKG_HDC_CTL);
+  AsmWriteMsr64 (MSR_IA32_PKG_HDC_CTL, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_PKG_HDC_CTL is defined as IA32_PKG_HDC_CTL in SDM.
+**/
+#define MSR_IA32_PKG_HDC_CTL                     0x00000DB0
+
+/**
+  MSR information returned for MSR index #MSR_IA32_PKG_HDC_CTL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] HDC_Pkg_Enable (R/W) Force HDC idling or wake up HDC-idled
+    /// logical processors in the package. See Section 14.5.2, "Package level
+    /// Enabling HDC". If CPUID.06H:EAX.[13] = 1.
+    ///
+    UINT32  HDC_Pkg_Enable:1;
+    UINT32  Reserved1:31;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_PKG_HDC_CTL_REGISTER;
+
+
+/**
+  Enable/disable HWP (R/W). If CPUID.06H:EAX.[13] = 1.
+
+  @param  ECX  MSR_IA32_PM_CTL1 (0x00000DB1)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_PM_CTL1_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_PM_CTL1_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_PM_CTL1_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_CTL1);
+  AsmWriteMsr64 (MSR_IA32_PM_CTL1, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_PM_CTL1 is defined as IA32_PM_CTL1 in SDM.
+**/
+#define MSR_IA32_PM_CTL1                         0x00000DB1
+
+/**
+  MSR information returned for MSR index #MSR_IA32_PM_CTL1
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] HDC_Allow_Block (R/W) Allow/Block this logical processor for
+    /// package level HDC control. See Section 14.5.3.
+    /// If CPUID.06H:EAX.[13] = 1.
+    ///
+    UINT32  HDC_Allow_Block:1;
+    UINT32  Reserved1:31;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_PM_CTL1_REGISTER;
+
+
+/**
+  Per-Logical_Processor HDC Idle Residency (R/0). If CPUID.06H:EAX.[13] = 1.
+  Stall_Cycle_Cnt (R/W) Stalled cycles due to HDC forced idle on this logical
+  processor. See Section 14.5.4.1. If CPUID.06H:EAX.[13] = 1.
+
+  @param  ECX  MSR_IA32_THREAD_STALL (0x00000DB2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_THREAD_STALL);
+  @endcode
+  @note MSR_IA32_THREAD_STALL is defined as IA32_THREAD_STALL in SDM.
+**/
+#define MSR_IA32_THREAD_STALL                    0x00000DB2
+
+
+/**
+  Extended Feature Enables. If ( CPUID.80000001H:EDX.[2 0]
+  CPUID.80000001H:EDX.[2 9]).
+
+  @param  ECX  MSR_IA32_EFER (0xC0000080)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_EFER_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_EFER_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_EFER_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_EFER);
+  AsmWriteMsr64 (MSR_IA32_EFER, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_EFER is defined as IA32_EFER in SDM.
+**/
+#define MSR_IA32_EFER                            0xC0000080
+
+/**
+  MSR information returned for MSR index #MSR_IA32_EFER
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] SYSCALL Enable: IA32_EFER.SCE (R/W) Enables SYSCALL/SYSRET
+    /// instructions in 64-bit mode.
+    ///
+    UINT32  SCE:1;
+    UINT32  Reserved1:7;
+    ///
+    /// [Bit 8] IA-32e Mode Enable: IA32_EFER.LME (R/W) Enables IA-32e mode
+    /// operation.
+    ///
+    UINT32  LME:1;
+    UINT32  Reserved2:1;
+    ///
+    /// [Bit 10] IA-32e Mode Active: IA32_EFER.LMA (R) Indicates IA-32e mode
+    /// is active when set.
+    ///
+    UINT32  LMA:1;
+    ///
+    /// [Bit 11] Execute Disable Bit Enable: IA32_EFER.NXE (R/W).
+    ///
+    UINT32  NXE:1;
+    UINT32  Reserved3:20;
+    UINT32  Reserved4:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_EFER_REGISTER;
+
+
+/**
+  System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.
+
+  @param  ECX  MSR_IA32_STAR (0xC0000081)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_STAR);
+  AsmWriteMsr64 (MSR_IA32_STAR, Msr);
+  @endcode
+  @note MSR_IA32_STAR is defined as IA32_STAR in SDM.
+**/
+#define MSR_IA32_STAR                            0xC0000081
+
+
+/**
+  IA-32e Mode System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.
+
+  @param  ECX  MSR_IA32_LSTAR (0xC0000082)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_LSTAR);
+  AsmWriteMsr64 (MSR_IA32_LSTAR, Msr);
+  @endcode
+  @note MSR_IA32_LSTAR is defined as IA32_LSTAR in SDM.
+**/
+#define MSR_IA32_LSTAR                           0xC0000082
+
+/**
+  IA-32e Mode System Call Target Address (R/W) Not used, as the SYSCALL
+  instruction is not recognized in compatibility mode. If
+  CPUID.80000001:EDX.[29] = 1.
+
+  @param  ECX  MSR_IA32_CSTAR (0xC0000083)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_CSTAR);
+  AsmWriteMsr64 (MSR_IA32_CSTAR, Msr);
+  @endcode
+  @note MSR_IA32_CSTAR is defined as IA32_CSTAR in SDM.
+**/
+#define MSR_IA32_CSTAR                           0xC0000083
+
+/**
+  System Call Flag Mask (R/W). If CPUID.80000001:EDX.[29] = 1.
+
+  @param  ECX  MSR_IA32_FMASK (0xC0000084)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_FMASK);
+  AsmWriteMsr64 (MSR_IA32_FMASK, Msr);
+  @endcode
+  @note MSR_IA32_FMASK is defined as IA32_FMASK in SDM.
+**/
+#define MSR_IA32_FMASK                           0xC0000084
+
+
+/**
+  Map of BASE Address of FS (R/W). If CPUID.80000001:EDX.[29] = 1.
+
+  @param  ECX  MSR_IA32_FS_BASE (0xC0000100)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_FS_BASE);
+  AsmWriteMsr64 (MSR_IA32_FS_BASE, Msr);
+  @endcode
+  @note MSR_IA32_FS_BASE is defined as IA32_FS_BASE in SDM.
+**/
+#define MSR_IA32_FS_BASE                         0xC0000100
+
+
+/**
+  Map of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.
+
+  @param  ECX  MSR_IA32_GS_BASE (0xC0000101)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_GS_BASE);
+  AsmWriteMsr64 (MSR_IA32_GS_BASE, Msr);
+  @endcode
+  @note MSR_IA32_GS_BASE is defined as IA32_GS_BASE in SDM.
+**/
+#define MSR_IA32_GS_BASE                         0xC0000101
+
+
+/**
+  Swap Target of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.
+
+  @param  ECX  MSR_IA32_KERNEL_GS_BASE (0xC0000102)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IA32_KERNEL_GS_BASE);
+  AsmWriteMsr64 (MSR_IA32_KERNEL_GS_BASE, Msr);
+  @endcode
+  @note MSR_IA32_KERNEL_GS_BASE is defined as IA32_KERNEL_GS_BASE in SDM.
+**/
+#define MSR_IA32_KERNEL_GS_BASE                  0xC0000102
+
+
+/**
+  Auxiliary TSC (RW). If CPUID.80000001H: EDX[27] = 1.
+
+  @param  ECX  MSR_IA32_TSC_AUX (0xC0000103)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IA32_TSC_AUX_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IA32_TSC_AUX_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IA32_TSC_AUX_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IA32_TSC_AUX);
+  AsmWriteMsr64 (MSR_IA32_TSC_AUX, Msr.Uint64);
+  @endcode
+  @note MSR_IA32_TSC_AUX is defined as IA32_TSC_AUX in SDM.
+**/
+#define MSR_IA32_TSC_AUX                         0xC0000103
+
+/**
+  MSR information returned for MSR index #MSR_IA32_TSC_AUX
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 31:0] AUX: Auxiliary signature of TSC.
+    ///
+    UINT32  AUX:32;
+    UINT32  Reserved:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IA32_TSC_AUX_REGISTER;
+
+#endif
diff --git a/MdePkg/Include/Register/Intel/Cpuid.h b/MdePkg/Include/Register/Intel/Cpuid.h
new file mode 100644
index 000000000000..47a694fdf8b8
--- /dev/null
+++ b/MdePkg/Include/Register/Intel/Cpuid.h
@@ -0,0 +1,3997 @@
+/** @file
+  Intel CPUID leaf definitions.
+
+  Provides defines for CPUID leaf indexes.  Data structures are provided for
+  registers returned by a CPUID leaf that contain one or more bit fields.
+  If a register returned is a single 32-bit value, then a data structure is
+  not provided for that register.
+
+  Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A,
+  November 2018, CPUID instruction.
+
+**/
+
+#ifndef __INTEL_CPUID_H__
+#define __INTEL_CPUID_H__
+
+/**
+  CPUID Signature Information
+
+  @param   EAX  CPUID_SIGNATURE (0x00)
+
+  @retval  EAX  Returns the highest value the CPUID instruction recognizes for
+                returning basic processor information. The value is returned is
+                processor specific.
+  @retval  EBX  First 4 characters of a vendor identification string.
+  @retval  ECX  Last 4 characters of a vendor identification string.
+  @retval  EDX  Middle 4 characters of a vendor identification string.
+
+  <b>Example usage</b>
+  @code
+  UINT32 Eax;
+  UINT32 Ebx;
+  UINT32 Ecx;
+  UINT32 Edx;
+
+  AsmCpuid (CPUID_SIGNATURE, &Eax, &Ebx, &Ecx, &Edx);
+  @endcode
+**/
+#define CPUID_SIGNATURE                         0x00
+
+///
+/// @{ CPUID signature values returned by Intel processors
+///
+#define CPUID_SIGNATURE_GENUINE_INTEL_EBX  SIGNATURE_32 ('G', 'e', 'n', 'u')
+#define CPUID_SIGNATURE_GENUINE_INTEL_EDX  SIGNATURE_32 ('i', 'n', 'e', 'I')
+#define CPUID_SIGNATURE_GENUINE_INTEL_ECX  SIGNATURE_32 ('n', 't', 'e', 'l')
+///
+/// @}
+///
+
+
+/**
+  CPUID Version Information
+
+  @param   EAX  CPUID_VERSION_INFO (0x01)
+
+  @retval  EAX  Returns Model, Family, Stepping Information described by the
+                type CPUID_VERSION_INFO_EAX.
+  @retval  EBX  Returns Brand, Cache Line Size, and Initial APIC ID described by
+                the type CPUID_VERSION_INFO_EBX.
+  @retval  ECX  CPU Feature Information described by the type
+                CPUID_VERSION_INFO_ECX.
+  @retval  EDX  CPU Feature Information described by the type
+                CPUID_VERSION_INFO_EDX.
+
+  <b>Example usage</b>
+  @code
+  CPUID_VERSION_INFO_EAX  Eax;
+  CPUID_VERSION_INFO_EBX  Ebx;
+  CPUID_VERSION_INFO_ECX  Ecx;
+  CPUID_VERSION_INFO_EDX  Edx;
+
+  AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
+  @endcode
+**/
+#define CPUID_VERSION_INFO                      0x01
+
+/**
+  CPUID Version Information returned in EAX for CPUID leaf
+  #CPUID_VERSION_INFO.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  SteppingId:4;        ///< [Bits   3:0] Stepping ID
+    UINT32  Model:4;             ///< [Bits   7:4] Model
+    UINT32  FamilyId:4;          ///< [Bits  11:8] Family
+    UINT32  ProcessorType:2;     ///< [Bits 13:12] Processor Type
+    UINT32  Reserved1:2;         ///< [Bits 15:14] Reserved
+    UINT32  ExtendedModelId:4;   ///< [Bits 19:16] Extended Model ID
+    UINT32  ExtendedFamilyId:8;  ///< [Bits 27:20] Extended Family ID
+    UINT32  Reserved2:4;         ///< Reserved
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32    Uint32;
+} CPUID_VERSION_INFO_EAX;
+
+///
+/// @{ Define value for bit field CPUID_VERSION_INFO_EAX.ProcessorType
+///
+#define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_ORIGINAL_OEM_PROCESSOR     0x00
+#define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_INTEL_OVERDRIVE_PROCESSOR  0x01
+#define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_DUAL_PROCESSOR             0x02
+///
+/// @}
+///
+
+/**
+  CPUID Version Information returned in EBX for CPUID leaf
+  #CPUID_VERSION_INFO.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Provides an entry into a brand string table that contains
+    /// brand strings for IA-32 processors.
+    ///
+    UINT32  BrandIndex:8;
+    ///
+    /// [Bits 15:8] Indicates the size of the cache line flushed by the CLFLUSH
+    /// and CLFLUSHOPT instructions in 8-byte increments. This field was
+    /// introduced in the Pentium 4 processor.
+    ///
+    UINT32  CacheLineSize:8;
+    ///
+    /// [Bits 23:16] Maximum number of addressable IDs for logical processors
+    /// in this physical package.
+    ///
+    /// @note
+    /// The nearest power-of-2 integer that is not smaller than EBX[23:16] is
+    /// the number of unique initial APICIDs reserved for addressing different
+    /// logical processors in a physical package. This field is only valid if
+    /// CPUID.1.EDX.HTT[bit 28]= 1.
+    ///
+    UINT32  MaximumAddressableIdsForLogicalProcessors:8;
+    ///
+    /// [Bits 31:24] The 8-bit ID that is assigned to the local APIC on the
+    /// processor during power up. This field was introduced in the Pentium 4
+    /// processor.
+    ///
+    UINT32  InitialLocalApicId:8;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32    Uint32;
+} CPUID_VERSION_INFO_EBX;
+
+/**
+  CPUID Version Information returned in ECX for CPUID leaf
+  #CPUID_VERSION_INFO.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Streaming SIMD Extensions 3 (SSE3).  A value of 1 indicates the
+    /// processor supports this technology
+    ///
+    UINT32  SSE3:1;
+    ///
+    /// [Bit 1] A value of 1 indicates the processor supports the PCLMULQDQ
+    /// instruction.  Carryless Multiplication
+    ///
+    UINT32  PCLMULQDQ:1;
+    ///
+    /// [Bit 2] 64-bit DS Area.  A value of 1 indicates the processor supports
+    /// DS area using 64-bit layout.
+    ///
+    UINT32  DTES64:1;
+    ///
+    /// [Bit 3] MONITOR/MWAIT.  A value of 1 indicates the processor supports
+    /// this feature.
+    ///
+    UINT32  MONITOR:1;
+    ///
+    /// [Bit 4] CPL Qualified Debug Store.  A value of 1 indicates the processor
+    /// supports the extensions to the Debug Store feature to allow for branch
+    /// message storage qualified by CPL
+    ///
+    UINT32  DS_CPL:1;
+    ///
+    /// [Bit 5] Virtual Machine Extensions.  A value of 1 indicates that the
+    /// processor supports this technology.
+    ///
+    UINT32  VMX:1;
+    ///
+    /// [Bit 6] Safer Mode Extensions. A value of 1 indicates that the processor
+    /// supports this technology
+    ///
+    UINT32  SMX:1;
+    ///
+    /// [Bit 7] Enhanced Intel SpeedStep(R) technology.  A value of 1 indicates
+    /// that the processor supports this technology
+    ///
+    UINT32  EIST:1;
+    ///
+    /// [Bit 8] Thermal Monitor 2.  A value of 1 indicates whether the processor
+    /// supports this technology
+    ///
+    UINT32  TM2:1;
+    ///
+    /// [Bit 9] A value of 1 indicates the presence of the Supplemental Streaming
+    /// SIMD Extensions 3 (SSSE3). A value of 0 indicates the instruction
+    /// extensions are not present in the processor.
+    ///
+    UINT32  SSSE3:1;
+    ///
+    /// [Bit 10] L1 Context ID.  A value of 1 indicates the L1 data cache mode
+    /// can be set to either adaptive mode or shared mode. A value of 0 indicates
+    /// this feature is not supported. See definition of the IA32_MISC_ENABLE MSR
+    /// Bit 24 (L1 Data Cache Context Mode) for details
+    ///
+    UINT32  CNXT_ID:1;
+    ///
+    /// [Bit 11] A value of 1 indicates the processor supports IA32_DEBUG_INTERFACE
+    /// MSR for silicon debug
+    ///
+    UINT32  SDBG:1;
+    ///
+    /// [Bit 12] A value of 1 indicates the processor supports FMA (Fused Multiple
+    ///  Add) extensions using YMM state.
+    ///
+    UINT32  FMA:1;
+    ///
+    /// [Bit 13] CMPXCHG16B Available.  A value of 1 indicates that the feature
+    /// is available.
+    ///
+    UINT32  CMPXCHG16B:1;
+    ///
+    /// [Bit 14] xTPR Update Control.  A value of 1 indicates that the processor
+    /// supports changing IA32_MISC_ENABLE[Bit 23].
+    ///
+    UINT32  xTPR_Update_Control:1;
+    ///
+    /// [Bit 15] Perfmon and Debug Capability:  A value of 1 indicates the
+    /// processor supports the performance and debug feature indication MSR
+    /// IA32_PERF_CAPABILITIES.
+    ///
+    UINT32  PDCM:1;
+    UINT32  Reserved:1;
+    ///
+    /// [Bit 17] Process-context identifiers.  A value of 1 indicates that the
+    /// processor supports PCIDs and that software may set CR4.PCIDE to 1.
+    ///
+    UINT32  PCID:1;
+    ///
+    /// [Bit 18] A value of 1 indicates the processor supports the ability to
+    /// prefetch data from a memory mapped device.  Direct Cache Access.
+    ///
+    UINT32  DCA:1;
+    ///
+    /// [Bit 19] A value of 1 indicates that the processor supports SSE4.1.
+    ///
+    UINT32  SSE4_1:1;
+    ///
+    /// [Bit 20] A value of 1 indicates that the processor supports SSE4.2.
+    ///
+    UINT32  SSE4_2:1;
+    ///
+    /// [Bit 21] A value of 1 indicates that the processor supports x2APIC
+    /// feature.
+    ///
+    UINT32  x2APIC:1;
+    ///
+    /// [Bit 22] A value of 1 indicates that the processor supports MOVBE
+    /// instruction.
+    ///
+    UINT32  MOVBE:1;
+    ///
+    /// [Bit 23] A value of 1 indicates that the processor supports the POPCNT
+    /// instruction.
+    ///
+    UINT32  POPCNT:1;
+    ///
+    /// [Bit 24] A value of 1 indicates that the processor's local APIC timer
+    /// supports one-shot operation using a TSC deadline value.
+    ///
+    UINT32  TSC_Deadline:1;
+    ///
+    /// [Bit 25] A value of 1 indicates that the processor supports the AESNI
+    /// instruction extensions.
+    ///
+    UINT32  AESNI:1;
+    ///
+    /// [Bit 26] A value of 1 indicates that the processor supports the
+    /// XSAVE/XRSTOR processor extended states feature, the XSETBV/XGETBV
+    /// instructions, and XCR0.
+    ///
+    UINT32  XSAVE:1;
+    ///
+    /// [Bit 27] A value of 1 indicates that the OS has set CR4.OSXSAVE[Bit 18]
+    /// to enable XSETBV/XGETBV instructions to access XCR0 and to support
+    /// processor extended state management using XSAVE/XRSTOR.
+    ///
+    UINT32  OSXSAVE:1;
+    ///
+    /// [Bit 28] A value of 1 indicates the processor supports the AVX instruction
+    /// extensions.
+    ///
+    UINT32  AVX:1;
+    ///
+    /// [Bit 29] A value of 1 indicates that processor supports 16-bit
+    /// floating-point conversion instructions.
+    ///
+    UINT32  F16C:1;
+    ///
+    /// [Bit 30] A value of 1 indicates that processor supports RDRAND instruction.
+    ///
+    UINT32  RDRAND:1;
+    ///
+    /// [Bit 31] Always returns 0.
+    ///
+    UINT32  NotUsed:1;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32    Uint32;
+} CPUID_VERSION_INFO_ECX;
+
+/**
+  CPUID Version Information returned in EDX for CPUID leaf
+  #CPUID_VERSION_INFO.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Floating Point Unit On-Chip. The processor contains an x87 FPU.
+    ///
+    UINT32  FPU:1;
+    ///
+    /// [Bit 1] Virtual 8086 Mode Enhancements.  Virtual 8086 mode enhancements,
+    /// including CR4.VME for controlling the feature, CR4.PVI for protected
+    /// mode virtual interrupts, software interrupt indirection, expansion of
+    /// the TSS with the software indirection bitmap, and EFLAGS.VIF and
+    /// EFLAGS.VIP flags.
+    ///
+    UINT32  VME:1;
+    ///
+    /// [Bit 2] Debugging Extensions.  Support for I/O breakpoints, including
+    /// CR4.DE for controlling the feature, and optional trapping of accesses to
+    /// DR4 and DR5.
+    ///
+    UINT32  DE:1;
+    ///
+    /// [Bit 3] Page Size Extension.  Large pages of size 4 MByte are supported,
+    /// including CR4.PSE for controlling the feature, the defined dirty bit in
+    /// PDE (Page Directory Entries), optional reserved bit trapping in CR3,
+    /// PDEs, and PTEs.
+    ///
+    UINT32  PSE:1;
+    ///
+    /// [Bit 4] Time Stamp Counter.  The RDTSC instruction is supported,
+    /// including CR4.TSD for controlling privilege.
+    ///
+    UINT32  TSC:1;
+    ///
+    /// [Bit 5] Model Specific Registers RDMSR and WRMSR Instructions.  The
+    /// RDMSR and WRMSR instructions are supported. Some of the MSRs are
+    /// implementation dependent.
+    ///
+    UINT32  MSR:1;
+    ///
+    /// [Bit 6] Physical Address Extension.  Physical addresses greater than 32
+    /// bits are supported: extended page table entry formats, an extra level in
+    /// the page translation tables is defined, 2-MByte pages are supported
+    /// instead of 4 Mbyte pages if PAE bit is 1.
+    ///
+    UINT32  PAE:1;
+    ///
+    /// [Bit 7] Machine Check Exception.  Exception 18 is defined for Machine
+    /// Checks, including CR4.MCE for controlling the feature. This feature does
+    /// not define the model-specific implementations of machine-check error
+    /// logging, reporting, and processor shutdowns. Machine Check exception
+    /// handlers may have to depend on processor version to do model specific
+    /// processing of the exception, or test for the presence of the Machine
+    /// Check feature.
+    ///
+    UINT32  MCE:1;
+    ///
+    /// [Bit 8] CMPXCHG8B Instruction.  The compare-and-exchange 8 bytes(64 bits)
+    /// instruction is supported (implicitly locked and atomic).
+    ///
+    UINT32  CX8:1;
+    ///
+    /// [Bit 9] APIC On-Chip.  The processor contains an Advanced Programmable
+    /// Interrupt Controller (APIC), responding to memory mapped commands in the
+    /// physical address range FFFE0000H to FFFE0FFFH (by default - some
+    /// processors permit the APIC to be relocated).
+    ///
+    UINT32  APIC:1;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 11] SYSENTER and SYSEXIT Instructions.  The SYSENTER and SYSEXIT
+    /// and associated MSRs are supported.
+    ///
+    UINT32  SEP:1;
+    ///
+    /// [Bit 12] Memory Type Range Registers.  MTRRs are supported. The MTRRcap
+    /// MSR contains feature bits that describe what memory types are supported,
+    /// how many variable MTRRs are supported, and whether fixed MTRRs are
+    /// supported.
+    ///
+    UINT32  MTRR:1;
+    ///
+    /// [Bit 13] Page Global Bit.  The global bit is supported in paging-structure
+    /// entries that map a page, indicating TLB entries that are common to
+    /// different processes and need not be flushed. The CR4.PGE bit controls
+    /// this feature.
+    ///
+    UINT32  PGE:1;
+    ///
+    /// [Bit 14] Machine Check Architecture. A value of 1 indicates the Machine
+    /// Check Architecture of reporting machine errors is supported. The MCG_CAP
+    /// MSR contains feature bits describing how many banks of error reporting
+    /// MSRs are supported.
+    ///
+    UINT32  MCA:1;
+    ///
+    /// [Bit 15] Conditional Move Instructions.  The conditional move instruction
+    /// CMOV is supported. In addition, if x87 FPU is present as indicated by the
+    /// CPUID.FPU feature bit, then the FCOMI and FCMOV instructions are supported.
+    ///
+    UINT32  CMOV:1;
+    ///
+    /// [Bit 16] Page Attribute Table.  Page Attribute Table is supported. This
+    /// feature augments the Memory Type Range Registers (MTRRs), allowing an
+    /// operating system to specify attributes of memory accessed through a
+    /// linear address on a 4KB granularity.
+    ///
+    UINT32  PAT:1;
+    ///
+    /// [Bit 17] 36-Bit Page Size Extension.  4-MByte pages addressing physical
+    /// memory beyond 4 GBytes are supported with 32-bit paging. This feature
+    /// indicates that upper bits of the physical address of a 4-MByte page are
+    /// encoded in bits 20:13 of the page-directory entry. Such physical
+    /// addresses are limited by MAXPHYADDR and may be up to 40 bits in size.
+    ///
+    UINT32  PSE_36:1;
+    ///
+    /// [Bit 18] Processor Serial Number.  The processor supports the 96-bit
+    /// processor identification number feature and the feature is enabled.
+    ///
+    UINT32  PSN:1;
+    ///
+    /// [Bit 19] CLFLUSH Instruction.  CLFLUSH Instruction is supported.
+    ///
+    UINT32  CLFSH:1;
+    UINT32  Reserved2:1;
+    ///
+    /// [Bit 21] Debug Store.  The processor supports the ability to write debug
+    /// information into a memory resident buffer.  This feature is used by the
+    /// branch trace store (BTS) and precise event-based sampling (PEBS)
+    /// facilities.
+    ///
+    UINT32  DS:1;
+    ///
+    /// [Bit 22] Thermal Monitor and Software Controlled Clock Facilities.  The
+    /// processor implements internal MSRs that allow processor temperature to
+    /// be monitored and processor performance to be modulated in predefined
+    /// duty cycles under software control.
+    ///
+    UINT32  ACPI:1;
+    ///
+    /// [Bit 23] Intel MMX Technology.  The processor supports the Intel MMX
+    /// technology.
+    ///
+    UINT32  MMX:1;
+    ///
+    /// [Bit 24] FXSAVE and FXRSTOR Instructions.  The FXSAVE and FXRSTOR
+    /// instructions are supported for fast save and restore of the floating
+    /// point context. Presence of this bit also indicates that CR4.OSFXSR is
+    /// available for an operating system to indicate that it supports the
+    /// FXSAVE and FXRSTOR instructions.
+    ///
+    UINT32  FXSR:1;
+    ///
+    /// [Bit 25] SSE.  The processor supports the SSE extensions.
+    ///
+    UINT32  SSE:1;
+    ///
+    /// [Bit 26] SSE2.  The processor supports the SSE2 extensions.
+    ///
+    UINT32  SSE2:1;
+    ///
+    /// [Bit 27] Self Snoop.  The processor supports the management of
+    /// conflicting memory types by performing a snoop of its own cache
+    /// structure for transactions issued to the bus.
+    ///
+    UINT32  SS:1;
+    ///
+    /// [Bit 28] Max APIC IDs reserved field is Valid.  A value of 0 for HTT
+    /// indicates there is only a single logical processor in the package and
+    /// software should assume only a single APIC ID is reserved. A value of 1
+    /// for HTT indicates the value in CPUID.1.EBX[23:16] (the Maximum number of
+    /// addressable IDs for logical processors in this package) is valid for the
+    /// package.
+    ///
+    UINT32  HTT:1;
+    ///
+    /// [Bit 29] Thermal Monitor.  The processor implements the thermal monitor
+    /// automatic thermal control circuitry (TCC).
+    ///
+    UINT32  TM:1;
+    UINT32  Reserved3:1;
+    ///
+    /// [Bit 31] Pending Break Enable.  The processor supports the use of the
+    /// FERR#/PBE# pin when the processor is in the stop-clock state (STPCLK# is
+    /// asserted) to signal the processor that an interrupt is pending and that
+    /// the processor should return to normal operation to handle the interrupt.
+    /// Bit 10 (PBE enable) in the IA32_MISC_ENABLE MSR enables this capability.
+    ///
+    UINT32  PBE:1;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32    Uint32;
+} CPUID_VERSION_INFO_EDX;
+
+
+/**
+  CPUID Cache and TLB Information
+
+  @param   EAX  CPUID_CACHE_INFO (0x02)
+
+  @retval  EAX  Cache and TLB Information described by the type
+                CPUID_CACHE_INFO_CACHE_TLB.
+                CPUID_CACHE_INFO_CACHE_TLB.CacheDescriptor[0] always returns
+                0x01 and must be ignored.  Only valid if
+                CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
+  @retval  EBX  Cache and TLB Information described by the type
+                CPUID_CACHE_INFO_CACHE_TLB.  Only valid if
+                CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
+  @retval  ECX  Cache and TLB Information described by the type
+                CPUID_CACHE_INFO_CACHE_TLB.  Only valid if
+                CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
+  @retval  EDX  Cache and TLB Information described by the type
+                CPUID_CACHE_INFO_CACHE_TLB.  Only valid if
+                CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.
+
+  <b>Example usage</b>
+  @code
+  CPUID_CACHE_INFO_CACHE_TLB  Eax;
+  CPUID_CACHE_INFO_CACHE_TLB  Ebx;
+  CPUID_CACHE_INFO_CACHE_TLB  Ecx;
+  CPUID_CACHE_INFO_CACHE_TLB  Edx;
+
+  AsmCpuid (CPUID_CACHE_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
+  @endcode
+
+  <b>Cache Descriptor values</b>
+  <table>
+  <tr><th>Value </th><th> Type    </th><th> Description </th></tr>
+  <tr><td> 0x00 </td><td> General </td><td> Null descriptor, this byte contains no information</td></tr>
+  <tr><td> 0x01 </td><td> TLB     </td><td> Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries</td></tr>
+  <tr><td> 0x02 </td><td> TLB     </td><td> Instruction TLB: 4 MByte pages, fully associative, 2 entries</td></tr>
+  <tr><td> 0x03 </td><td> TLB     </td><td> Data TLB: 4 KByte pages, 4-way set associative, 64 entries</td></tr>
+  <tr><td> 0x04 </td><td> TLB     </td><td> Data TLB: 4 MByte pages, 4-way set associative, 8 entries</td></tr>
+  <tr><td> 0x05 </td><td> TLB     </td><td> Data TLB1: 4 MByte pages, 4-way set associative, 32 entries</td></tr>
+  <tr><td> 0x06 </td><td> Cache   </td><td> 1st-level instruction cache: 8 KBytes, 4-way set associative,
+                                            32 byte line size</td></tr>
+  <tr><td> 0x08 </td><td> Cache   </td><td> 1st-level instruction cache: 16 KBytes, 4-way set associative,
+                                            32 byte line size</td></tr>
+  <tr><td> 0x09 </td><td> Cache   </td><td> 1st-level instruction cache: 32KBytes, 4-way set associative,
+                                            64 byte line size</td></tr>
+  <tr><td> 0x0A </td><td> Cache   </td><td> 1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size</td></tr>
+  <tr><td> 0x0B </td><td> TLB     </td><td> Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries</td></tr>
+  <tr><td> 0x0C </td><td> Cache   </td><td> 1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size</td></tr>
+  <tr><td> 0x0D </td><td> Cache   </td><td> 1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size</td></tr>
+  <tr><td> 0x0E </td><td> Cache   </td><td> 1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size</td></tr>
+  <tr><td> 0x1D </td><td> Cache   </td><td> 2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size</td></tr>
+  <tr><td> 0x21 </td><td> Cache   </td><td> 2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size</td></tr>
+  <tr><td> 0x22 </td><td> Cache   </td><td> 3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size,
+                                            2 lines per sector</td></tr>
+  <tr><td> 0x23 </td><td> Cache   </td><td> 3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size,
+                                            2 lines per sector</td></tr>
+  <tr><td> 0x24 </td><td> Cache   </td><td> 2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size</td></tr>
+  <tr><td> 0x25 </td><td> Cache   </td><td> 3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size,
+                                            2 lines per sector</td></tr>
+  <tr><td> 0x29 </td><td> Cache   </td><td> 3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size,
+                                            2 lines per sector</td></tr>
+  <tr><td> 0x2C </td><td> Cache   </td><td> 1st-level data cache: 32 KBytes, 8-way set associative,
+                                            64 byte line size</td></tr>
+  <tr><td> 0x30 </td><td> Cache   </td><td> 1st-level instruction cache: 32 KBytes, 8-way set associative,
+                                            64 byte line size</td></tr>
+  <tr><td> 0x40 </td><td> Cache   </td><td> No 2nd-level cache or, if processor contains a valid 2nd-level cache,
+                                            no 3rd-level cache</td></tr>
+  <tr><td> 0x41 </td><td> Cache   </td><td> 2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size</td></tr>
+  <tr><td> 0x42 </td><td> Cache   </td><td> 2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size</td></tr>
+  <tr><td> 0x43 </td><td> Cache   </td><td> 2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size</td></tr>
+  <tr><td> 0x44 </td><td> Cache   </td><td> 2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size</td></tr>
+  <tr><td> 0x45 </td><td> Cache   </td><td> 2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size</td></tr>
+  <tr><td> 0x46 </td><td> Cache   </td><td> 3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size</td></tr>
+  <tr><td> 0x47 </td><td> Cache   </td><td> 3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size</td></tr>
+  <tr><td> 0x48 </td><td> Cache   </td><td> 2nd-level cache: 3MByte, 12-way set associative, 64 byte line size</td></tr>
+  <tr><td> 0x49 </td><td> Cache   </td><td> 3rd-level cache: 4MB, 16-way set associative, 64-byte line size
+                                            (Intel Xeon processor MP, Family 0FH, Model 06H)<BR>
+                                            2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size</td></tr>
+  <tr><td> 0x4A </td><td> Cache   </td><td> 3rd-level cache: 6MByte, 12-way set associative, 64 byte line size</td></tr>
+  <tr><td> 0x4B </td><td> Cache   </td><td> 3rd-level cache: 8MByte, 16-way set associative, 64 byte line size</td></tr>
+  <tr><td> 0x4C </td><td> Cache   </td><td> 3rd-level cache: 12MByte, 12-way set associative, 64 byte line size</td></tr>
+  <tr><td> 0x4D </td><td> Cache   </td><td> 3rd-level cache: 16MByte, 16-way set associative, 64 byte line size</td></tr>
+  <tr><td> 0x4E </td><td> Cache   </td><td> 2nd-level cache: 6MByte, 24-way set associative, 64 byte line size</td></tr>
+  <tr><td> 0x4F </td><td> TLB     </td><td> Instruction TLB: 4 KByte pages, 32 entries</td></tr>
+  <tr><td> 0x50 </td><td> TLB     </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries</td></tr>
+  <tr><td> 0x51 </td><td> TLB     </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries</td></tr>
+  <tr><td> 0x52 </td><td> TLB     </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries</td></tr>
+  <tr><td> 0x55 </td><td> TLB     </td><td> Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries</td></tr>
+  <tr><td> 0x56 </td><td> TLB     </td><td> Data TLB0: 4 MByte pages, 4-way set associative, 16 entries</td></tr>
+  <tr><td> 0x57 </td><td> TLB     </td><td> Data TLB0: 4 KByte pages, 4-way associative, 16 entries</td></tr>
+  <tr><td> 0x59 </td><td> TLB     </td><td> Data TLB0: 4 KByte pages, fully associative, 16 entries</td></tr>
+  <tr><td> 0x5A </td><td> TLB     </td><td> Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries</td></tr>
+  <tr><td> 0x5B </td><td> TLB     </td><td> Data TLB: 4 KByte and 4 MByte pages, 64 entries</td></tr>
+  <tr><td> 0x5C </td><td> TLB     </td><td> Data TLB: 4 KByte and 4 MByte pages,128 entries</td></tr>
+  <tr><td> 0x5D </td><td> TLB     </td><td> Data TLB: 4 KByte and 4 MByte pages,256 entries</td></tr>
+  <tr><td> 0x60 </td><td> Cache   </td><td> 1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size</td></tr>
+  <tr><td> 0x61 </td><td> TLB     </td><td> Instruction TLB: 4 KByte pages, fully associative, 48 entries</td></tr>
+  <tr><td> 0x63 </td><td> TLB     </td><td> Data TLB: 2 MByte or 4 MByte pages, 4-way set associative,
+                                            32 entries and a separate array with 1 GByte pages, 4-way set associative,
+                                            4 entries</td></tr>
+  <tr><td> 0x64 </td><td> TLB     </td><td> Data TLB: 4 KByte pages, 4-way set associative, 512 entries</td></tr>
+  <tr><td> 0x66 </td><td> Cache   </td><td> 1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size</td></tr>
+  <tr><td> 0x67 </td><td> Cache   </td><td> 1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size</td></tr>
+  <tr><td> 0x68 </td><td> Cache   </td><td> 1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size</td></tr>
+  <tr><td> 0x6A </td><td> Cache   </td><td> uTLB: 4 KByte pages, 8-way set associative, 64 entries</td></tr>
+  <tr><td> 0x6B </td><td> Cache   </td><td> DTLB: 4 KByte pages, 8-way set associative, 256 entries</td></tr>
+  <tr><td> 0x6C </td><td> Cache   </td><td> DTLB: 2M/4M pages, 8-way set associative, 128 entries</td></tr>
+  <tr><td> 0x6D </td><td> Cache   </td><td> DTLB: 1 GByte pages, fully associative, 16 entries</td></tr>
+  <tr><td> 0x70 </td><td> Cache   </td><td> Trace cache: 12 K-uop, 8-way set associative</td></tr>
+  <tr><td> 0x71 </td><td> Cache   </td><td> Trace cache: 16 K-uop, 8-way set associative</td></tr>
+  <tr><td> 0x72 </td><td> Cache   </td><td> Trace cache: 32 K-uop, 8-way set associative</td></tr>
+  <tr><td> 0x76 </td><td> TLB     </td><td> Instruction TLB: 2M/4M pages, fully associative, 8 entries</td></tr>
+  <tr><td> 0x78 </td><td> Cache   </td><td> 2nd-level cache: 1 MByte, 4-way set associative, 64byte line size</td></tr>
+  <tr><td> 0x79 </td><td> Cache   </td><td> 2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size,
+                                            2 lines per sector</td></tr>
+  <tr><td> 0x7A </td><td> Cache   </td><td> 2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size,
+                                            2 lines per sector</td></tr>
+  <tr><td> 0x7B </td><td> Cache   </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size,
+                                            2 lines per sector</td></tr>
+  <tr><td> 0x7C </td><td> Cache   </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size,
+                                            2 lines per sector</td></tr>
+  <tr><td> 0x7D </td><td> Cache   </td><td> 2nd-level cache: 2 MByte, 8-way set associative, 64byte line size</td></tr>
+  <tr><td> 0x7F </td><td> Cache   </td><td> 2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size</td></tr>
+  <tr><td> 0x80 </td><td> Cache   </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size</td></tr>
+  <tr><td> 0x82 </td><td> Cache   </td><td> 2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size</td></tr>
+  <tr><td> 0x83 </td><td> Cache   </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size</td></tr>
+  <tr><td> 0x84 </td><td> Cache   </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size</td></tr>
+  <tr><td> 0x85 </td><td> Cache   </td><td> 2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size</td></tr>
+  <tr><td> 0x86 </td><td> Cache   </td><td> 2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr>
+  <tr><td> 0x87 </td><td> Cache   </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size</td></tr>
+  <tr><td> 0xA0 </td><td> DTLB    </td><td> DTLB: 4k pages, fully associative, 32 entries</td></tr>
+  <tr><td> 0xB0 </td><td> TLB     </td><td> Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries</td></tr>
+  <tr><td> 0xB1 </td><td> TLB     </td><td> Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries</td></tr>
+  <tr><td> 0xB2 </td><td> TLB     </td><td> Instruction TLB: 4KByte pages, 4-way set associative, 64 entries</td></tr>
+  <tr><td> 0xB3 </td><td> TLB     </td><td> Data TLB: 4 KByte pages, 4-way set associative, 128 entries</td></tr>
+  <tr><td> 0xB4 </td><td> TLB     </td><td> Data TLB1: 4 KByte pages, 4-way associative, 256 entries</td></tr>
+  <tr><td> 0xB5 </td><td> TLB     </td><td> Instruction TLB: 4KByte pages, 8-way set associative, 64 entries</td></tr>
+  <tr><td> 0xB6 </td><td> TLB     </td><td> Instruction TLB: 4KByte pages, 8-way set associative,
+                                            128 entries</td></tr>
+  <tr><td> 0xBA </td><td> TLB     </td><td> Data TLB1: 4 KByte pages, 4-way associative, 64 entries</td></tr>
+  <tr><td> 0xC0 </td><td> TLB     </td><td> Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries</td></tr>
+  <tr><td> 0xC1 </td><td> STLB    </td><td> Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative,
+                                            1024 entries</td></tr>
+  <tr><td> 0xC2 </td><td> DTLB    </td><td> DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries</td></tr>
+  <tr><td> 0xC3 </td><td> STLB    </td><td> Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative,
+                                            1536 entries. Also 1GBbyte pages, 4-way, 16 entries.</td></tr>
+  <tr><td> 0xC4 </td><td> DTLB    </td><td> DTLB: 2M/4M Byte pages, 4-way associative, 32 entries</td></tr>
+  <tr><td> 0xCA </td><td> STLB    </td><td> Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries</td></tr>
+  <tr><td> 0xD0 </td><td> Cache   </td><td> 3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr>
+  <tr><td> 0xD1 </td><td> Cache   </td><td> 3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size</td></tr>
+  <tr><td> 0xD2 </td><td> Cache   </td><td> 3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size</td></tr>
+  <tr><td> 0xD6 </td><td> Cache   </td><td> 3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size</td></tr>
+  <tr><td> 0xD7 </td><td> Cache   </td><td> 3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size</td></tr>
+  <tr><td> 0xD8 </td><td> Cache   </td><td> 3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size</td></tr>
+  <tr><td> 0xDC </td><td> Cache   </td><td> 3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size</td></tr>
+  <tr><td> 0xDD </td><td> Cache   </td><td> 3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size</td></tr>
+  <tr><td> 0xDE </td><td> Cache   </td><td> 3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size</td></tr>
+  <tr><td> 0xE2 </td><td> Cache   </td><td> 3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size</td></tr>
+  <tr><td> 0xE3 </td><td> Cache   </td><td> 3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size</td></tr>
+  <tr><td> 0xE4 </td><td> Cache   </td><td> 3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size</td></tr>
+  <tr><td> 0xEA </td><td> Cache   </td><td> 3rd-level cache: 12MByte, 24-way set associative, 64 byte line size</td></tr>
+  <tr><td> 0xEB </td><td> Cache   </td><td> 3rd-level cache: 18MByte, 24-way set associative, 64 byte line size</td></tr>
+  <tr><td> 0xEC </td><td> Cache   </td><td> 3rd-level cache: 24MByte, 24-way set associative, 64 byte line size</td></tr>
+  <tr><td> 0xF0 </td><td> Prefetch</td><td> 64-Byte prefetching</td></tr>
+  <tr><td> 0xF1 </td><td> Prefetch</td><td> 128-Byte prefetching</td></tr>
+  <tr><td> 0xFE </td><td> General </td><td> CPUID leaf 2 does not report TLB descriptor information; use CPUID
+                                            leaf 18H to query TLB and other address translation parameters.</td></tr>
+  <tr><td> 0xFF </td><td> General </td><td> CPUID leaf 2 does not report cache descriptor information,
+                                            use CPUID leaf 4 to query cache parameters</td></tr>
+  </table>
+**/
+#define CPUID_CACHE_INFO                        0x02
+
+/**
+  CPUID Cache and TLB Information returned in EAX, EBX, ECX, and EDX for CPUID
+  leaf #CPUID_CACHE_INFO.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved:31;
+    ///
+    /// [Bit 31] If 0, then the cache descriptor bytes in the register are valid.
+    /// if 1, then none of the cache descriptor bytes in the register are valid.
+    ///
+    UINT32  NotValid:1;
+  } Bits;
+  ///
+  /// Array of Cache and TLB descriptor bytes
+  ///
+  UINT8   CacheDescriptor[4];
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_CACHE_INFO_CACHE_TLB;
+
+
+/**
+  CPUID Processor Serial Number
+
+  Processor serial number (PSN) is not supported in the Pentium 4 processor
+  or later.  On all models, use the PSN flag (returned using CPUID) to check
+  for PSN support before accessing the feature.
+
+  @param   EAX  CPUID_SERIAL_NUMBER (0x03)
+
+  @retval  EAX  Reserved.
+  @retval  EBX  Reserved.
+  @retval  ECX  Bits 31:0 of 96 bit processor serial number. (Available in
+                Pentium III processor only; otherwise, the value in this
+                register is reserved.)
+  @retval  EDX  Bits 63:32 of 96 bit processor serial number. (Available in
+                Pentium III processor only; otherwise, the value in this
+                register is reserved.)
+
+  <b>Example usage</b>
+  @code
+  UINT32  Ecx;
+  UINT32  Edx;
+
+  AsmCpuid (CPUID_SERIAL_NUMBER, NULL, NULL, &Ecx, &Edx);
+  @endcode
+**/
+#define CPUID_SERIAL_NUMBER                     0x03
+
+
+/**
+  CPUID Cache Parameters
+
+  @param   EAX  CPUID_CACHE_PARAMS (0x04)
+  @param   ECX  Cache Level.  Valid values start at 0.  Software can enumerate
+                the deterministic cache parameters for each level of the cache
+                hierarchy starting with an index value of 0, until the
+                parameters report the value associated with the CacheType
+                field in CPUID_CACHE_PARAMS_EAX is 0.
+
+  @retval  EAX  Returns cache type information described by the type
+                CPUID_CACHE_PARAMS_EAX.
+  @retval  EBX  Returns cache line and associativity information described by
+                the type CPUID_CACHE_PARAMS_EBX.
+  @retval  ECX  Returns the number of sets in the cache.
+  @retval  EDX  Returns cache WINVD/INVD behavior described by the type
+                CPUID_CACHE_PARAMS_EDX.
+
+  <b>Example usage</b>
+  @code
+  UINT32                  CacheLevel;
+  CPUID_CACHE_PARAMS_EAX  Eax;
+  CPUID_CACHE_PARAMS_EBX  Ebx;
+  UINT32                  Ecx;
+  CPUID_CACHE_PARAMS_EDX  Edx;
+
+  CacheLevel = 0;
+  do {
+    AsmCpuidEx (
+      CPUID_CACHE_PARAMS, CacheLevel,
+      &Eax.Uint32, &Ebx.Uint32, &Ecx, &Edx.Uint32
+      );
+    CacheLevel++;
+  } while (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL);
+  @endcode
+**/
+#define CPUID_CACHE_PARAMS                      0x04
+
+/**
+  CPUID Cache Parameters Information returned in EAX for CPUID leaf
+  #CPUID_CACHE_PARAMS.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 4:0] Cache type field.  If #CPUID_CACHE_PARAMS_CACHE_TYPE_NULL,
+    /// then there is no information for the requested cache level.
+    ///
+    UINT32  CacheType:5;
+    ///
+    /// [Bits 7:5] Cache level (Starts at 1).
+    ///
+    UINT32  CacheLevel:3;
+    ///
+    /// [Bit 8] Self Initializing cache level (does not need SW initialization).
+    ///
+    UINT32  SelfInitializingCache:1;
+    ///
+    /// [Bit 9] Fully Associative cache.
+    ///
+    UINT32  FullyAssociativeCache:1;
+    ///
+    /// [Bits 13:10] Reserved.
+    ///
+    UINT32  Reserved:4;
+    ///
+    /// [Bits 25:14] Maximum number of addressable IDs for logical processors
+    /// sharing this cache.
+    ///
+    /// Add one to the return value to get the result.
+    /// The nearest power-of-2 integer that is not smaller than (1 + EAX[25:14])
+    /// is the number of unique initial APIC IDs reserved for addressing
+    /// different logical processors sharing this cache.
+    ///
+    UINT32  MaximumAddressableIdsForLogicalProcessors:12;
+    ///
+    /// [Bits 31:26] Maximum number of addressable IDs for processor cores in
+    /// the physical package.
+    ///
+    /// The nearest power-of-2 integer that is not smaller than (1 + EAX[31:26])
+    /// is the number of unique Core_IDs reserved for addressing different
+    /// processor cores in a physical package. Core ID is a subset of bits of
+    /// the initial APIC ID.
+    /// The returned value is constant for valid initial values in ECX. Valid
+    /// ECX values start from 0.
+    ///
+    UINT32  MaximumAddressableIdsForProcessorCores:6;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_CACHE_PARAMS_EAX;
+
+///
+/// @{ Define value for bit field CPUID_CACHE_PARAMS_EAX.CacheType
+///
+#define CPUID_CACHE_PARAMS_CACHE_TYPE_NULL         0x00
+#define CPUID_CACHE_PARAMS_CACHE_TYPE_DATA         0x01
+#define CPUID_CACHE_PARAMS_CACHE_TYPE_INSTRUCTION  0x02
+#define CPUID_CACHE_PARAMS_CACHE_TYPE_UNIFIED      0x03
+///
+/// @}
+///
+
+/**
+  CPUID Cache Parameters Information returned in EBX for CPUID leaf
+  #CPUID_CACHE_PARAMS.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 11:0] System Coherency Line Size.  Add one to the return value to
+    /// get the result.
+    ///
+    UINT32  LineSize:12;
+    ///
+    /// [Bits 21:12] Physical Line Partitions.  Add one to the return value to
+    /// get the result.
+    ///
+    UINT32  LinePartitions:10;
+    ///
+    /// [Bits 31:22] Ways of associativity.  Add one to the return value to get
+    /// the result.
+    ///
+    UINT32  Ways:10;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_CACHE_PARAMS_EBX;
+
+/**
+  CPUID Cache Parameters Information returned in EDX for CPUID leaf
+  #CPUID_CACHE_PARAMS.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Write-Back Invalidate/Invalidate.
+    /// 0 = WBINVD/INVD from threads sharing this cache acts upon lower level
+    /// caches for threads sharing this cache.
+    /// 1 = WBINVD/INVD is not guaranteed to act upon lower level caches of
+    /// non-originating threads sharing this cache.
+    ///
+    UINT32  Invalidate:1;
+    ///
+    /// [Bit 1] Cache Inclusiveness.
+    /// 0 = Cache is not inclusive of lower cache levels.
+    /// 1 = Cache is inclusive of lower cache levels.
+    ///
+    UINT32  CacheInclusiveness:1;
+    ///
+    /// [Bit 2] Complex Cache Indexing.
+    /// 0 = Direct mapped cache.
+    /// 1 = A complex function is used to index the cache, potentially using all
+    /// address bits.
+    ///
+    UINT32  ComplexCacheIndexing:1;
+    UINT32  Reserved:29;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_CACHE_PARAMS_EDX;
+
+
+/**
+  CPUID MONITOR/MWAIT Information
+
+  @param   EAX  CPUID_MONITOR_MWAIT (0x05)
+
+  @retval  EAX  Smallest monitor-line size in bytes described by the type
+                CPUID_MONITOR_MWAIT_EAX.
+  @retval  EBX  Largest monitor-line size in bytes described by the type
+                CPUID_MONITOR_MWAIT_EBX.
+  @retval  ECX  Enumeration of Monitor-Mwait extensions support described by
+                the type CPUID_MONITOR_MWAIT_ECX.
+  @retval  EDX  Sub C-states supported described by the type
+                CPUID_MONITOR_MWAIT_EDX.
+
+  <b>Example usage</b>
+  @code
+  CPUID_MONITOR_MWAIT_EAX  Eax;
+  CPUID_MONITOR_MWAIT_EBX  Ebx;
+  CPUID_MONITOR_MWAIT_ECX  Ecx;
+  CPUID_MONITOR_MWAIT_EDX  Edx;
+
+  AsmCpuid (CPUID_MONITOR_MWAIT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
+  @endcode
+**/
+#define CPUID_MONITOR_MWAIT                     0x05
+
+/**
+  CPUID MONITOR/MWAIT Information returned in EAX for CPUID leaf
+  #CPUID_MONITOR_MWAIT.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 15:0] Smallest monitor-line size in bytes (default is processor's
+    /// monitor granularity).
+    ///
+    UINT32  SmallestMonitorLineSize:16;
+    UINT32  Reserved:16;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_MONITOR_MWAIT_EAX;
+
+/**
+  CPUID MONITOR/MWAIT Information returned in EBX for CPUID leaf
+  #CPUID_MONITOR_MWAIT.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 15:0] Largest monitor-line size in bytes (default is processor's
+    /// monitor granularity).
+    ///
+    UINT32  LargestMonitorLineSize:16;
+    UINT32  Reserved:16;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_MONITOR_MWAIT_EBX;
+
+/**
+  CPUID MONITOR/MWAIT Information returned in ECX for CPUID leaf
+  #CPUID_MONITOR_MWAIT.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] If 0, then only EAX and EBX are valid.  If 1, then EAX, EBX, ECX,
+    /// and EDX are valid.
+    ///
+    UINT32  ExtensionsSupported:1;
+    ///
+    /// [Bit 1] Supports treating interrupts as break-event for MWAIT, even when
+    /// interrupts disabled.
+    ///
+    UINT32  InterruptAsBreak:1;
+    UINT32  Reserved:30;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_MONITOR_MWAIT_ECX;
+
+/**
+  CPUID MONITOR/MWAIT Information returned in EDX for CPUID leaf
+  #CPUID_MONITOR_MWAIT.
+
+  @note
+  The definition of C0 through C7 states for MWAIT extension are
+  processor-specific C-states, not ACPI C-states.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 3:0] Number of C0 sub C-states supported using MWAIT.
+    ///
+    UINT32  C0States:4;
+    ///
+    /// [Bits 7:4] Number of C1 sub C-states supported using MWAIT.
+    ///
+    UINT32  C1States:4;
+    ///
+    /// [Bits 11:8] Number of C2 sub C-states supported using MWAIT.
+    ///
+    UINT32  C2States:4;
+    ///
+    /// [Bits 15:12] Number of C3 sub C-states supported using MWAIT.
+    ///
+    UINT32  C3States:4;
+    ///
+    /// [Bits 19:16] Number of C4 sub C-states supported using MWAIT.
+    ///
+    UINT32  C4States:4;
+    ///
+    /// [Bits 23:20] Number of C5 sub C-states supported using MWAIT.
+    ///
+    UINT32  C5States:4;
+    ///
+    /// [Bits 27:24] Number of C6 sub C-states supported using MWAIT.
+    ///
+    UINT32  C6States:4;
+    ///
+    /// [Bits 31:28] Number of C7 sub C-states supported using MWAIT.
+    ///
+    UINT32  C7States:4;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_MONITOR_MWAIT_EDX;
+
+
+/**
+  CPUID Thermal and Power Management
+
+  @param   EAX  CPUID_THERMAL_POWER_MANAGEMENT (0x06)
+
+  @retval  EAX  Thermal and power management features described by the type
+                CPUID_THERMAL_POWER_MANAGEMENT_EAX.
+  @retval  EBX  Number of Interrupt Thresholds in Digital Thermal Sensor
+                described by the type CPUID_THERMAL_POWER_MANAGEMENT_EBX.
+  @retval  ECX  Performance features described by the type
+                CPUID_THERMAL_POWER_MANAGEMENT_ECX.
+  @retval  EDX  Reserved.
+
+  <b>Example usage</b>
+  @code
+  CPUID_THERMAL_POWER_MANAGEMENT_EAX  Eax;
+  CPUID_THERMAL_POWER_MANAGEMENT_EBX  Ebx;
+  CPUID_THERMAL_POWER_MANAGEMENT_ECX  Ecx;
+
+  AsmCpuid (CPUID_THERMAL_POWER_MANAGEMENT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);
+  @endcode
+**/
+#define CPUID_THERMAL_POWER_MANAGEMENT          0x06
+
+/**
+  CPUID Thermal and Power Management Information returned in EAX for CPUID leaf
+  #CPUID_THERMAL_POWER_MANAGEMENT.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Digital temperature sensor is supported if set.
+    ///
+    UINT32  DigitalTemperatureSensor:1;
+    ///
+    /// [Bit 1] Intel Turbo Boost Technology Available (see IA32_MISC_ENABLE[38]).
+    ///
+    UINT32  TurboBoostTechnology:1;
+    ///
+    /// [Bit 2] APIC-Timer-always-running feature is supported if set.
+    ///
+    UINT32  ARAT:1;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 4] Power limit notification controls are supported if set.
+    ///
+    UINT32  PLN:1;
+    ///
+    /// [Bit 5] Clock modulation duty cycle extension is supported if set.
+    ///
+    UINT32  ECMD:1;
+    ///
+    /// [Bit 6] Package thermal management is supported if set.
+    ///
+    UINT32  PTM:1;
+    ///
+    /// [Bit 7] HWP base registers (IA32_PM_ENABLE[Bit 0], IA32_HWP_CAPABILITIES,
+    /// IA32_HWP_REQUEST, IA32_HWP_STATUS) are supported if set.
+    ///
+    UINT32  HWP:1;
+    ///
+    /// [Bit 8] IA32_HWP_INTERRUPT MSR is supported if set.
+    ///
+    UINT32  HWP_Notification:1;
+    ///
+    /// [Bit 9] IA32_HWP_REQUEST[Bits 41:32] is supported if set.
+    ///
+    UINT32  HWP_Activity_Window:1;
+    ///
+    /// [Bit 10] IA32_HWP_REQUEST[Bits 31:24] is supported if set.
+    ///
+    UINT32  HWP_Energy_Performance_Preference:1;
+    ///
+    /// [Bit 11] IA32_HWP_REQUEST_PKG MSR is supported if set.
+    ///
+    UINT32  HWP_Package_Level_Request:1;
+    UINT32  Reserved2:1;
+    ///
+    /// [Bit 13] HDC base registers IA32_PKG_HDC_CTL, IA32_PM_CTL1,
+    /// IA32_THREAD_STALL MSRs are supported if set.
+    ///
+    UINT32  HDC:1;
+    ///
+    /// [Bit 14] Intel Turbo Boost Max Technology 3.0 available.
+    ///
+    UINT32  TurboBoostMaxTechnology30:1;
+    ///
+    /// [Bit 15] HWP Capabilities.
+    /// Highest Performance change is supported if set.
+    ///
+    UINT32  HWPCapabilities:1;
+    ///
+    /// [Bit 16] HWP PECI override is supported if set.
+    ///
+    UINT32  HWPPECIOverride:1;
+    ///
+    /// [Bit 17] Flexible HWP is supported if set.
+    ///
+    UINT32  FlexibleHWP:1;
+    ///
+    /// [Bit 18] Fast access mode for the IA32_HWP_REQUEST MSR is supported if set.
+    ///
+    UINT32  FastAccessMode:1;
+    UINT32  Reserved4:1;
+    ///
+    /// [Bit 20] Ignoring Idle Logical Processor HWP request is supported if set.
+    ///
+    UINT32  IgnoringIdleLogicalProcessorHWPRequest:1;
+    UINT32  Reserved5:11;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_THERMAL_POWER_MANAGEMENT_EAX;
+
+/**
+  CPUID Thermal and Power Management Information returned in EBX for CPUID leaf
+  #CPUID_THERMAL_POWER_MANAGEMENT.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// {Bits 3:0] Number of Interrupt Thresholds in Digital Thermal Sensor.
+    ///
+    UINT32  InterruptThresholds:4;
+    UINT32  Reserved:28;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_THERMAL_POWER_MANAGEMENT_EBX;
+
+/**
+  CPUID Thermal and Power Management Information returned in ECX for CPUID leaf
+  #CPUID_THERMAL_POWER_MANAGEMENT.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Hardware Coordination Feedback Capability (Presence of IA32_MPERF
+    /// and IA32_APERF). The capability to provide a measure of delivered
+    /// processor performance (since last reset of the counters), as a percentage
+    /// of the expected processor performance when running at the TSC frequency.
+    ///
+    UINT32  HardwareCoordinationFeedback:1;
+    UINT32  Reserved1:2;
+    ///
+    /// [Bit 3] If this bit is set, then the processor supports performance-energy
+    /// bias preference and the architectural MSR called IA32_ENERGY_PERF_BIAS
+    /// (1B0H).
+    ///
+    UINT32  PerformanceEnergyBias:1;
+    UINT32  Reserved2:28;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_THERMAL_POWER_MANAGEMENT_ECX;
+
+
+/**
+  CPUID Structured Extended Feature Flags Enumeration
+
+  @param   EAX  CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (0x07)
+  @param   ECX  CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO (0x00).
+
+  @note
+  If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0.  Sub-leaf
+  index n is invalid if n exceeds the value that sub-leaf 0 returns in EAX.
+
+  @retval  EAX  The maximum input value for ECX to retrieve sub-leaf information.
+  @retval  EBX  Structured Extended Feature Flags described by the type
+                CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX.
+  @retval  EBX  Structured Extended Feature Flags described by the type
+                CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX.
+  @retval  EDX  Reserved.
+
+  <b>Example usage</b>
+  @code
+  UINT32                                       Eax;
+  CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX  Ebx;
+  CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX  Ecx;
+  UINT32                                       SubLeaf;
+
+  AsmCpuidEx (
+    CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
+    CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,
+    &Eax, NULL, NULL, NULL
+    );
+  for (SubLeaf = 0; SubLeaf <= Eax; SubLeaf++) {
+    AsmCpuidEx (
+      CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
+      SubLeaf,
+      NULL, &Ebx.Uint32, &Ecx.Uint32, NULL
+      );
+  }
+  @endcode
+**/
+#define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS                0x07
+
+///
+/// CPUID Structured Extended Feature Flags Enumeration sub-leaf
+///
+#define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO  0x00
+
+/**
+  CPUID Structured Extended Feature Flags Enumeration in EBX for CPUID leaf
+  #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf
+  #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1.
+    ///
+    UINT32  FSGSBASE:1;
+    ///
+    /// [Bit 1] IA32_TSC_ADJUST MSR is supported if 1.
+    ///
+    UINT32  IA32_TSC_ADJUST:1;
+    ///
+    /// [Bit 2] Intel SGX is supported if 1. See section 37.7 "DISCOVERING SUPPORT
+    /// FOR INTEL(R) SGX AND ENABLING ENCLAVE INSTRUCTIONS".
+    ///
+    UINT32  SGX:1;
+    ///
+    /// [Bit 3] If 1 indicates the processor supports the first group of advanced
+    /// bit manipulation extensions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, TZCNT)
+    ///
+    UINT32  BMI1:1;
+    ///
+    /// [Bit 4] Hardware Lock Elision
+    ///
+    UINT32  HLE:1;
+    ///
+    /// [Bit 5] If 1 indicates the processor supports AVX2 instruction extensions.
+    ///
+    UINT32  AVX2:1;
+    ///
+    /// [Bit 6] x87 FPU Data Pointer updated only on x87 exceptions if 1.
+    ///
+    UINT32  FDP_EXCPTN_ONLY:1;
+    ///
+    /// [Bit 7] Supports Supervisor-Mode Execution Prevention if 1.
+    ///
+    UINT32  SMEP:1;
+    ///
+    /// [Bit 8] If 1 indicates the processor supports the second group of
+    /// advanced bit manipulation extensions (BZHI, MULX, PDEP, PEXT, RORX,
+    /// SARX, SHLX, SHRX)
+    ///
+    UINT32  BMI2:1;
+    ///
+    /// [Bit 9] Supports Enhanced REP MOVSB/STOSB if 1.
+    ///
+    UINT32  EnhancedRepMovsbStosb:1;
+    ///
+    /// [Bit 10] If 1, supports INVPCID instruction for system software that
+    /// manages process-context identifiers.
+    ///
+    UINT32  INVPCID:1;
+    ///
+    /// [Bit 11] Restricted Transactional Memory
+    ///
+    UINT32  RTM:1;
+    ///
+    /// [Bit 12] Supports Intel(R) Resource Director Technology (Intel(R) RDT)
+    /// Monitoring capability if 1.
+    ///
+    UINT32  RDT_M:1;
+    ///
+    /// [Bit 13] Deprecates FPU CS and FPU DS values if 1.
+    ///
+    UINT32  DeprecateFpuCsDs:1;
+    ///
+    /// [Bit 14] Supports Intel(R) Memory Protection Extensions if 1.
+    ///
+    UINT32  MPX:1;
+    ///
+    /// [Bit 15] Supports Intel(R) Resource Director Technology (Intel(R) RDT)
+    /// Allocation capability if 1.
+    ///
+    UINT32  RDT_A:1;
+    ///
+    /// [Bit 16] AVX512F.
+    ///
+    UINT32  AVX512F:1;
+    ///
+    /// [Bit 17] AVX512DQ.
+    ///
+    UINT32  AVX512DQ:1;
+    ///
+    /// [Bit 18] If 1 indicates the processor supports the RDSEED instruction.
+    ///
+    UINT32  RDSEED:1;
+    ///
+    /// [Bit 19] If 1 indicates the processor supports the ADCX and ADOX
+    /// instructions.
+    ///
+    UINT32  ADX:1;
+    ///
+    /// [Bit 20] Supports Supervisor-Mode Access Prevention (and the CLAC/STAC
+    /// instructions) if 1.
+    ///
+    UINT32  SMAP:1;
+    ///
+    /// [Bit 21] AVX512_IFMA.
+    ///
+    UINT32  AVX512_IFMA:1;
+    UINT32  Reserved6:1;
+    ///
+    /// [Bit 23] If 1 indicates the processor supports the CLFLUSHOPT instruction.
+    ///
+    UINT32  CLFLUSHOPT:1;
+    ///
+    /// [Bit 24] If 1 indicates the processor supports the CLWB instruction.
+    ///
+    UINT32  CLWB:1;
+    ///
+    /// [Bit 25] If 1 indicates the processor supports the Intel Processor Trace
+    /// extensions.
+    ///
+    UINT32  IntelProcessorTrace:1;
+    ///
+    /// [Bit 26] AVX512PF. (Intel Xeon Phi only.).
+    ///
+    UINT32  AVX512PF:1;
+    ///
+    /// [Bit 27] AVX512ER. (Intel Xeon Phi only.).
+    ///
+    UINT32  AVX512ER:1;
+    ///
+    /// [Bit 28] AVX512CD.
+    ///
+    UINT32  AVX512CD:1;
+    ///
+    /// [Bit 29] Supports Intel(R) Secure Hash Algorithm Extensions (Intel(R)
+    /// SHA Extensions) if 1.
+    ///
+    UINT32  SHA:1;
+    ///
+    /// [Bit 30] AVX512BW.
+    ///
+    UINT32  AVX512BW:1;
+    ///
+    /// [Bit 31] AVX512VL.
+    ///
+    UINT32  AVX512VL:1;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX;
+
+/**
+  CPUID Structured Extended Feature Flags Enumeration in ECX for CPUID leaf
+  #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf
+  #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] If 1 indicates the processor supports the PREFETCHWT1 instruction.
+    /// (Intel Xeon Phi only.)
+    ///
+    UINT32  PREFETCHWT1:1;
+    ///
+    /// [Bit 1] AVX512_VBMI.
+    ///
+    UINT32  AVX512_VBMI:1;
+    ///
+    /// [Bit 2] Supports user-mode instruction prevention if 1.
+    ///
+    UINT32  UMIP:1;
+    ///
+    /// [Bit 3] Supports protection keys for user-mode pages if 1.
+    ///
+    UINT32  PKU:1;
+    ///
+    /// [Bit 4] If 1, OS has set CR4.PKE to enable protection keys (and the
+    /// RDPKRU/WRPKRU instructions).
+    ///
+    UINT32  OSPKE:1;
+    UINT32  Reserved5:9;
+    ///
+    /// [Bits 14] AVX512_VPOPCNTDQ. (Intel Xeon Phi only.).
+    ///
+    UINT32  AVX512_VPOPCNTDQ:1;
+    UINT32  Reserved7:1;
+    ///
+    /// [Bits 16] Supports 5-level paging if 1.
+    ///
+    UINT32  FiveLevelPage:1;
+    ///
+    /// [Bits 21:17] The value of MAWAU used by the BNDLDX and BNDSTX instructions
+    /// in 64-bit mode.
+    ///
+    UINT32  MAWAU:5;
+    ///
+    /// [Bit 22] RDPID and IA32_TSC_AUX are available if 1.
+    ///
+    UINT32  RDPID:1;
+    UINT32  Reserved3:7;
+    ///
+    /// [Bit 30] Supports SGX Launch Configuration if 1.
+    ///
+    UINT32  SGX_LC:1;
+    UINT32  Reserved4:1;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX;
+
+/**
+  CPUID Structured Extended Feature Flags Enumeration in EDX for CPUID leaf
+  #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf
+  #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 1:0] Reserved.
+    ///
+    UINT32  Reserved1:2;
+    ///
+    /// [Bit 2] AVX512_4VNNIW. (Intel Xeon Phi only.)
+    ///
+    UINT32  AVX512_4VNNIW:1;
+    ///
+    /// [Bit 3] AVX512_4FMAPS. (Intel Xeon Phi only.)
+    ///
+    UINT32  AVX512_4FMAPS:1;
+    ///
+    /// [Bit 25:4] Reserved.
+    ///
+    UINT32  Reserved2:22;
+    ///
+    /// [Bit 26] Enumerates support for indirect branch restricted speculation
+    /// (IBRS) and the indirect branch pre-dictor barrier (IBPB). Processors
+    /// that set this bit support the IA32_SPEC_CTRL MSR and the IA32_PRED_CMD
+    /// MSR. They allow software to set IA32_SPEC_CTRL[0] (IBRS) and
+    /// IA32_PRED_CMD[0] (IBPB).
+    ///
+    UINT32  EnumeratesSupportForIBRSAndIBPB:1;
+    ///
+    /// [Bit 27] Enumerates support for single thread indirect branch
+    /// predictors (STIBP). Processors that set this bit support the
+    /// IA32_SPEC_CTRL MSR. They allow software to set IA32_SPEC_CTRL[1]
+    /// (STIBP).
+    ///
+    UINT32  EnumeratesSupportForSTIBP:1;
+    ///
+    /// [Bit 28] Enumerates support for L1D_FLUSH. Processors that set this bit
+    /// support the IA32_FLUSH_CMD MSR. They allow software to set
+    /// IA32_FLUSH_CMD[0] (L1D_FLUSH).
+    ///
+    UINT32  EnumeratesSupportForL1D_FLUSH:1;
+    ///
+    /// [Bit 29] Enumerates support for the IA32_ARCH_CAPABILITIES MSR.
+    ///
+    UINT32  EnumeratesSupportForCapability:1;
+    ///
+    /// [Bit 30] Reserved.
+    ///
+    UINT32  Reserved3:1;
+    ///
+    /// [Bit 31] Enumerates support for Speculative Store Bypass Disable (SSBD).
+    /// Processors that set this bit sup-port the IA32_SPEC_CTRL MSR. They allow
+    /// software to set IA32_SPEC_CTRL[2] (SSBD).
+    ///
+    UINT32  EnumeratesSupportForSSBD:1;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EDX;
+
+/**
+  CPUID Direct Cache Access Information
+
+  @param   EAX  CPUID_DIRECT_CACHE_ACCESS_INFO (0x09)
+
+  @retval  EAX  Value of bits [31:0] of IA32_PLATFORM_DCA_CAP MSR (address 1F8H).
+  @retval  EBX  Reserved.
+  @retval  ECX  Reserved.
+  @retval  EDX  Reserved.
+
+  <b>Example usage</b>
+  @code
+  UINT32  Eax;
+
+  AsmCpuid (CPUID_DIRECT_CACHE_ACCESS_INFO, &Eax, NULL, NULL, NULL);
+  @endcode
+**/
+#define CPUID_DIRECT_CACHE_ACCESS_INFO              0x09
+
+
+/**
+  CPUID Architectural Performance Monitoring
+
+  @param   EAX  CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING (0x0A)
+
+  @retval  EAX  Architectural Performance Monitoring information described by
+                the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX.
+  @retval  EBX  Architectural Performance Monitoring information described by
+                the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX.
+  @retval  ECX  Reserved.
+  @retval  EDX  Architectural Performance Monitoring information described by
+                the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX.
+
+  <b>Example usage</b>
+  @code
+  CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX  Eax;
+  CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX  Ebx;
+  CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX  Edx;
+
+  AsmCpuid (CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING, &Eax.Uint32, &Ebx.Uint32, NULL, &Edx.Uint32);
+  @endcode
+**/
+#define CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING  0x0A
+
+/**
+  CPUID Architectural Performance Monitoring EAX for CPUID leaf
+  #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 7:0] Version ID of architectural performance monitoring.
+    ///
+    UINT32  ArchPerfMonVerID:8;
+    ///
+    /// [Bits 15:8] Number of general-purpose performance monitoring counter
+    /// per logical processor.
+    ///
+    /// IA32_PERFEVTSELx MSRs start at address 186H and occupy a contiguous
+    /// block of MSR address space. Each performance event select register is
+    /// paired with a corresponding performance counter in the 0C1H address
+    /// block.
+    ///
+    UINT32  PerformanceMonitorCounters:8;
+    ///
+    /// [Bits 23:16] Bit width of general-purpose, performance monitoring counter.
+    ///
+    /// The bit width of an IA32_PMCx MSR. This the number of valid bits for
+    /// read operation. On write operations, the lower-order 32 bits of the MSR
+    /// may be written with any value, and the high-order bits are sign-extended
+    /// from the value of bit 31.
+    ///
+    UINT32  PerformanceMonitorCounterWidth:8;
+    ///
+    /// [Bits 31:24] Length of EBX bit vector to enumerate architectural
+    /// performance monitoring events.
+    ///
+    UINT32  EbxBitVectorLength:8;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX;
+
+/**
+  CPUID Architectural Performance Monitoring EBX for CPUID leaf
+  #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Core cycle event not available if 1.
+    ///
+    UINT32  UnhaltedCoreCycles:1;
+    ///
+    /// [Bit 1] Instruction retired event not available if 1.
+    ///
+    UINT32  InstructionsRetired:1;
+    ///
+    /// [Bit 2] Reference cycles event not available if 1.
+    ///
+    UINT32  UnhaltedReferenceCycles:1;
+    ///
+    /// [Bit 3] Last-level cache reference event not available if 1.
+    ///
+    UINT32  LastLevelCacheReferences:1;
+    ///
+    /// [Bit 4] Last-level cache misses event not available if 1.
+    ///
+    UINT32  LastLevelCacheMisses:1;
+    ///
+    /// [Bit 5] Branch instruction retired event not available if 1.
+    ///
+    UINT32  BranchInstructionsRetired:1;
+    ///
+    /// [Bit 6] Branch mispredict retired event not available if 1.
+    ///
+    UINT32  AllBranchMispredictRetired:1;
+    UINT32  Reserved:25;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX;
+
+/**
+  CPUID Architectural Performance Monitoring EDX for CPUID leaf
+  #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 4:0] Number of fixed-function performance counters
+    /// (if Version ID > 1).
+    ///
+    UINT32  FixedFunctionPerformanceCounters:5;
+    ///
+    /// [Bits 12:5] Bit width of fixed-function performance counters
+    /// (if Version ID > 1).
+    ///
+    UINT32  FixedFunctionPerformanceCounterWidth:8;
+    UINT32  Reserved1:2;
+    ///
+    /// [Bits 15] AnyThread deprecation.
+    ///
+    UINT32  AnyThreadDeprecation:1;
+    UINT32  Reserved2:16;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX;
+
+
+/**
+  CPUID Extended Topology Information
+
+  @note
+  CPUID leaf 1FH is a preferred superset to leaf 0BH. Intel recommends first
+  checking for the existence of Leaf 1FH before using leaf 0BH.
+  Most of Leaf 0BH output depends on the initial value in ECX.  The EDX output
+  of leaf 0BH is always valid and does not vary with input value in ECX.  Output
+  value in ECX[7:0] always equals input value in ECX[7:0].
+  Sub-leaf index 0 enumerates SMT level. Each subsequent higher sub-leaf index
+  enumerates a higher-level topological entity in hierarchical order.
+  For sub-leaves that return an invalid level-type of 0 in ECX[15:8]; EAX and
+  EBX will return 0.
+  If an input value n in ECX returns the invalid level-type of 0 in ECX[15:8],
+  other input values with ECX > n also return 0 in ECX[15:8].
+
+  @param   EAX  CPUID_EXTENDED_TOPOLOGY (0x0B)
+  @param   ECX  Level number
+
+  @retval  EAX  Extended topology information described by the type
+                CPUID_EXTENDED_TOPOLOGY_EAX.
+  @retval  EBX  Extended topology information described by the type
+                CPUID_EXTENDED_TOPOLOGY_EBX.
+  @retval  ECX  Extended topology information described by the type
+                CPUID_EXTENDED_TOPOLOGY_ECX.
+  @retval  EDX  x2APIC ID the current logical processor.
+
+  <b>Example usage</b>
+  @code
+  CPUID_EXTENDED_TOPOLOGY_EAX  Eax;
+  CPUID_EXTENDED_TOPOLOGY_EBX  Ebx;
+  CPUID_EXTENDED_TOPOLOGY_ECX  Ecx;
+  UINT32                       Edx;
+  UINT32                       LevelNumber;
+
+  LevelNumber = 0;
+  do {
+    AsmCpuidEx (
+      CPUID_EXTENDED_TOPOLOGY, LevelNumber,
+      &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx
+      );
+    LevelNumber++;
+  } while (Eax.Bits.ApicIdShift != 0);
+  @endcode
+**/
+#define CPUID_EXTENDED_TOPOLOGY                             0x0B
+
+/**
+  CPUID Extended Topology Information EAX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 4:0] Number of bits to shift right on x2APIC ID to get a unique
+    /// topology ID of the next level type.  All logical processors with the
+    /// same next level ID share current level.
+    ///
+    /// @note
+    /// Software should use this field (EAX[4:0]) to enumerate processor
+    /// topology of the system.
+    ///
+    UINT32  ApicIdShift:5;
+    UINT32  Reserved:27;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_EXTENDED_TOPOLOGY_EAX;
+
+/**
+  CPUID Extended Topology Information EBX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 15:0] Number of logical processors at this level type. The number
+    /// reflects configuration as shipped by Intel.
+    ///
+    /// @note
+    /// Software must not use EBX[15:0] to enumerate processor topology of the
+    /// system. This value in this field (EBX[15:0]) is only intended for
+    /// display/diagnostic purposes. The actual number of logical processors
+    /// available to BIOS/OS/Applications may be different from the value of
+    /// EBX[15:0], depending on software and platform hardware configurations.
+    ///
+    UINT32  LogicalProcessors:16;
+    UINT32  Reserved:16;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_EXTENDED_TOPOLOGY_EBX;
+
+/**
+  CPUID Extended Topology Information ECX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Level number. Same value in ECX input.
+    ///
+    UINT32  LevelNumber:8;
+    ///
+    /// [Bits 15:8] Level type.
+    ///
+    /// @note
+    /// The value of the "level type" field is not related to level numbers in
+    /// any way, higher "level type" values do not mean higher levels.
+    ///
+    UINT32  LevelType:8;
+    UINT32  Reserved:16;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_EXTENDED_TOPOLOGY_ECX;
+
+///
+/// @{ Define value for CPUID_EXTENDED_TOPOLOGY_ECX.LevelType
+///
+#define   CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID        0x00
+#define   CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT            0x01
+#define   CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE           0x02
+///
+/// @}
+///
+
+
+/**
+  CPUID Extended State Information
+
+  @param   EAX  CPUID_EXTENDED_STATE (0x0D)
+  @param   ECX  CPUID_EXTENDED_STATE_MAIN_LEAF (0x00).
+                CPUID_EXTENDED_STATE_SUB_LEAF (0x01).
+                CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02).
+                Sub leafs 2..n based on supported bits in XCR0 or IA32_XSS_MSR.
+**/
+#define CPUID_EXTENDED_STATE                                0x0D
+
+/**
+  CPUID Extended State Information Main Leaf
+
+  @param   EAX  CPUID_EXTENDED_STATE (0x0D)
+  @param   ECX  CPUID_EXTENDED_STATE_MAIN_LEAF (0x00)
+
+  @retval  EAX  Reports the supported bits of the lower 32 bits of XCR0. XCR0[n]
+                can be set to 1 only if EAX[n] is 1.  The format of the extended
+                state main leaf is described by the type
+                CPUID_EXTENDED_STATE_MAIN_LEAF_EAX.
+  @retval  EBX  Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save
+                area) required by enabled features in XCR0. May be different than
+                ECX if some features at the end of the XSAVE save area are not
+                enabled.
+  @retval  ECX  Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save
+                area) of the XSAVE/XRSTOR save area required by all supported
+                features in the processor, i.e., all the valid bit fields in XCR0.
+  @retval  EDX  Reports the supported bits of the upper 32 bits of XCR0.
+                XCR0[n+32] can be set to 1 only if EDX[n] is 1.
+
+  <b>Example usage</b>
+  @code
+  CPUID_EXTENDED_STATE_MAIN_LEAF_EAX  Eax;
+  UINT32                              Ebx;
+  UINT32                              Ecx;
+  UINT32                              Edx;
+
+  AsmCpuidEx (
+    CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF,
+    &Eax.Uint32, &Ebx, &Ecx, &Edx
+    );
+  @endcode
+**/
+#define CPUID_EXTENDED_STATE_MAIN_LEAF                      0x00
+
+/**
+  CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE,
+  sub-leaf #CPUID_EXTENDED_STATE_MAIN_LEAF.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] x87 state.
+    ///
+    UINT32  x87:1;
+    ///
+    /// [Bit 1] SSE state.
+    ///
+    UINT32  SSE:1;
+    ///
+    /// [Bit 2] AVX state.
+    ///
+    UINT32  AVX:1;
+    ///
+    /// [Bits 4:3] MPX state.
+    ///
+    UINT32  MPX:2;
+    ///
+    /// [Bits 7:5] AVX-512 state.
+    ///
+    UINT32  AVX_512:3;
+    ///
+    /// [Bit 8] Used for IA32_XSS.
+    ///
+    UINT32  IA32_XSS:1;
+    ///
+    /// [Bit 9] PKRU state.
+    ///
+    UINT32  PKRU:1;
+    UINT32  Reserved1:3;
+    ///
+    /// [Bit 13] Used for IA32_XSS, part 2.
+    ///
+    UINT32  IA32_XSS_2:1;
+    UINT32  Reserved2:18;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_EXTENDED_STATE_MAIN_LEAF_EAX;
+
+/**
+  CPUID Extended State Information Sub Leaf
+
+  @param   EAX  CPUID_EXTENDED_STATE (0x0D)
+  @param   ECX  CPUID_EXTENDED_STATE_SUB_LEAF (0x01)
+
+  @retval  EAX  The format of the extended state sub-leaf is described by the
+                type CPUID_EXTENDED_STATE_SUB_LEAF_EAX.
+  @retval  EBX  The size in bytes of the XSAVE area containing all states
+                enabled by XCRO | IA32_XSS.
+  @retval  ECX  The format of the extended state sub-leaf is described by the
+                type CPUID_EXTENDED_STATE_SUB_LEAF_ECX.
+  @retval  EDX  Reports the supported bits of the upper 32 bits of the
+                IA32_XSS MSR. IA32_XSS[n+32] can be set to 1 only if EDX[n] is 1.
+
+  <b>Example usage</b>
+  @code
+  CPUID_EXTENDED_STATE_SUB_LEAF_EAX  Eax;
+  UINT32                             Ebx;
+  CPUID_EXTENDED_STATE_SUB_LEAF_ECX  Ecx;
+  UINT32                             Edx;
+
+  AsmCpuidEx (
+    CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF,
+    &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx
+    );
+  @endcode
+**/
+#define CPUID_EXTENDED_STATE_SUB_LEAF                       0x01
+
+/**
+  CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE,
+  sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] XSAVEOPT is available.
+    ///
+    UINT32  XSAVEOPT:1;
+    ///
+    /// [Bit 1] Supports XSAVEC and the compacted form of XRSTOR if set.
+    ///
+    UINT32  XSAVEC:1;
+    ///
+    /// [Bit 2] Supports XGETBV with ECX = 1 if set.
+    ///
+    UINT32  XGETBV:1;
+    ///
+    /// [Bit 3] Supports XSAVES/XRSTORS and IA32_XSS if set.
+    ///
+    UINT32  XSAVES:1;
+    UINT32  Reserved:28;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_EXTENDED_STATE_SUB_LEAF_EAX;
+
+/**
+  CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE,
+  sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Used for XCR0.
+    ///
+    UINT32  XCR0:1;
+    ///
+    /// [Bit 8] PT STate.
+    ///
+    UINT32  PT:1;
+    ///
+    /// [Bit 9] Used for XCR0.
+    ///
+    UINT32  XCR0_1:1;
+    UINT32  Reserved1:3;
+    ///
+    /// [Bit 13] HWP state.
+    ///
+    UINT32  HWPState:1;
+    UINT32  Reserved8:18;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_EXTENDED_STATE_SUB_LEAF_ECX;
+
+/**
+  CPUID Extended State Information Size and Offset Sub Leaf
+
+  @note
+  Leaf 0DH output depends on the initial value in ECX.
+  Each sub-leaf index (starting at position 2) is supported if it corresponds to
+  a supported bit in either the XCR0 register or the IA32_XSS MSR.
+  If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf
+  n (0 <= n <= 31) is invalid if sub-leaf 0 returns 0 in EAX[n] and sub-leaf 1
+  returns 0 in ECX[n]. Sub-leaf n (32 <= n <= 63) is invalid if sub-leaf 0
+  returns 0 in EDX[n-32] and sub-leaf 1 returns 0 in EDX[n-32].
+
+  @param   EAX  CPUID_EXTENDED_STATE (0x0D)
+  @param   ECX  CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02).  Sub leafs 2..n based
+                on supported bits in XCR0 or IA32_XSS_MSR.
+
+  @retval  EAX  The size in bytes (from the offset specified in EBX) of the save
+                area for an extended state feature associated with a valid
+                sub-leaf index, n.
+  @retval  EBX  The offset in bytes of this extended state component's save area
+                from the beginning of the XSAVE/XRSTOR area.  This field reports
+                0 if the sub-leaf index, n, does not map to a valid bit in the
+                XCR0 register.
+  @retval  ECX  The format of the extended state components's save area as
+                described by the type CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX.
+                This field reports 0 if the sub-leaf index, n, is invalid.
+  @retval  EDX  This field reports 0 if the sub-leaf index, n, is invalid;
+                otherwise it is reserved.
+
+  <b>Example usage</b>
+  @code
+  UINT32                                Eax;
+  UINT32                                Ebx;
+  CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX  Ecx;
+  UINT32                                Edx;
+  UINTN                                 SubLeaf;
+
+  for (SubLeaf = CPUID_EXTENDED_STATE_SIZE_OFFSET; SubLeaf < 32; SubLeaf++) {
+    AsmCpuidEx (
+      CPUID_EXTENDED_STATE, SubLeaf,
+      &Eax, &Ebx, &Ecx.Uint32, &Edx
+      );
+  }
+  @endcode
+**/
+#define CPUID_EXTENDED_STATE_SIZE_OFFSET                    0x02
+
+/**
+  CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE,
+  sub-leaf #CPUID_EXTENDED_STATE_SIZE_OFFSET.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Is set if the bit n (corresponding to the sub-leaf index) is
+    /// supported in the IA32_XSS MSR; it is clear if bit n is instead supported
+    /// in XCR0.
+    ///
+    UINT32  XSS:1;
+    ///
+    /// [Bit 1] is set if, when the compacted format of an XSAVE area is used,
+    /// this extended state component located on the next 64-byte boundary
+    /// following the preceding state component (otherwise, it is located
+    /// immediately following the preceding state component).
+    ///
+    UINT32  Compacted:1;
+    UINT32  Reserved:30;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX;
+
+
+/**
+  CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information
+
+  @param   EAX  CPUID_INTEL_RDT_MONITORING (0x0F)
+  @param   ECX  CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF (0x00).
+                CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01).
+
+**/
+#define CPUID_INTEL_RDT_MONITORING                          0x0F
+
+/**
+  CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information
+  Enumeration Sub-leaf
+
+  @param   EAX  CPUID_INTEL_RDT_MONITORING (0x0F)
+  @param   ECX  CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF (0x00)
+
+  @retval  EAX  Reserved.
+  @retval  EBX  Maximum range (zero-based) of RMID within this physical
+                processor of all types.
+  @retval  ECX  Reserved.
+  @retval  EDX  L3 Cache Intel RDT Monitoring Information Enumeration described by
+                the type CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX.
+
+  <b>Example usage</b>
+  @code
+  UINT32                                                  Ebx;
+  CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX     Edx;
+
+  AsmCpuidEx (
+    CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF,
+    NULL, &Ebx, NULL, &Edx.Uint32
+    );
+  @endcode
+**/
+#define CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF     0x00
+
+/**
+  CPUID Intel RDT Monitoring Information EDX for CPUID leaf
+  #CPUID_INTEL_RDT_MONITORING, sub-leaf
+  #CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 1] Supports L3 Cache Intel RDT Monitoring if 1.
+    ///
+    UINT32  L3CacheRDT_M:1;
+    UINT32  Reserved2:30;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX;
+
+/**
+  CPUID L3 Cache Intel RDT Monitoring Capability Enumeration Sub-leaf
+
+  @param   EAX  CPUID_INTEL_RDT_MONITORING (0x0F)
+  @param   ECX  CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01)
+
+  @retval  EAX  Reserved.
+  @retval  EBX  Conversion factor from reported IA32_QM_CTR value to occupancy metric (bytes).
+  @retval  ECX  Maximum range (zero-based) of RMID of this resource type.
+  @retval  EDX  L3 Cache Intel RDT Monitoring Capability information described by the
+                type CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX.
+
+  <b>Example usage</b>
+  @code
+  UINT32                                            Ebx;
+  UINT32                                            Ecx;
+  CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX  Edx;
+
+  AsmCpuidEx (
+    CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF,
+    NULL, &Ebx, &Ecx, &Edx.Uint32
+    );
+  @endcode
+**/
+#define CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF        0x01
+
+/**
+  CPUID L3 Cache Intel RDT Monitoring Capability Information EDX for CPUID leaf
+  #CPUID_INTEL_RDT_MONITORING, sub-leaf
+  #CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Supports L3 occupancy monitoring if 1.
+    ///
+    UINT32  L3CacheOccupancyMonitoring:1;
+    ///
+    /// [Bit 1] Supports L3 Total Bandwidth monitoring if 1.
+    ///
+    UINT32  L3CacheTotalBandwidthMonitoring:1;
+    ///
+    /// [Bit 2] Supports L3 Local Bandwidth monitoring if 1.
+    ///
+    UINT32  L3CacheLocalBandwidthMonitoring:1;
+    UINT32  Reserved:29;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX;
+
+
+/**
+  CPUID Intel Resource Director Technology (Intel RDT) Allocation Information
+
+  @param   EAX  CPUID_INTEL_RDT_ALLOCATION (0x10).
+  @param   ECX  CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF (0x00).
+                CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01).
+                CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02).
+**/
+#define CPUID_INTEL_RDT_ALLOCATION                          0x10
+
+/**
+  Intel Resource Director Technology (Intel RDT) Allocation Enumeration Sub-leaf
+
+  @param   EAX  CPUID_INTEL_RDT_ALLOCATION (0x10)
+  @param   ECX  CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF (0x00).
+
+  @retval  EAX  Reserved.
+  @retval  EBX  L3 and L2 Cache Allocation Technology information described by
+                the type CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX.
+  @retval  ECX  Reserved.
+  @retval  EDX  Reserved.
+
+  <b>Example usage</b>
+  @code
+  CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX  Ebx;
+
+  AsmCpuidEx (
+    CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF,
+    NULL, &Ebx.Uint32, NULL, NULL
+    );
+  @endcode
+**/
+#define CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF     0x00
+
+/**
+  CPUID L3 and L2 Cache Allocation Support Information EBX for CPUID leaf
+  #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
+  #CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 1] Supports L3 Cache Allocation Technology if 1.
+    ///
+    UINT32  L3CacheAllocation:1;
+    ///
+    /// [Bit 2] Supports L2 Cache Allocation Technology if 1.
+    ///
+    UINT32  L2CacheAllocation:1;
+    ///
+    /// [Bit 3] Supports Memory Bandwidth Allocation if 1.
+    ///
+    UINT32  MemoryBandwidth:1;
+    UINT32  Reserved3:28;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX;
+
+
+/**
+  L3 Cache Allocation Technology Enumeration Sub-leaf
+
+  @param   EAX  CPUID_INTEL_RDT_ALLOCATION (0x10)
+  @param   ECX  CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01)
+
+  @retval  EAX  RESID L3 Cache Allocation Technology information described by
+                the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX.
+  @retval  EBX  Bit-granular map of isolation/contention of allocation units.
+  @retval  ECX  RESID L3 Cache Allocation Technology information described by
+                the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX.
+  @retval  EDX  RESID L3 Cache Allocation Technology information described by
+                the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX.
+
+  <b>Example usage</b>
+  @code
+  CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX  Eax;
+  UINT32                                            Ebx;
+  CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX  Ecx;
+  CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX  Edx;
+
+  AsmCpuidEx (
+    CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF,
+    &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32
+    );
+  @endcode
+**/
+#define CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF        0x01
+
+/**
+  CPUID L3 Cache Allocation Technology Information EAX for CPUID leaf
+  #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
+  #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID
+    /// using minus-one notation.
+    ///
+    UINT32  CapacityLength:5;
+    UINT32  Reserved:27;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX;
+
+/**
+  CPUID L3 Cache Allocation Technology Information ECX for CPUID leaf
+  #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
+  #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved3:2;
+    ///
+    /// [Bit 2] Code and Data Prioritization Technology supported if 1.
+    ///
+    UINT32  CodeDataPrioritization:1;
+    UINT32  Reserved2:29;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX;
+
+/**
+  CPUID L3 Cache Allocation Technology Information EDX for CPUID leaf
+  #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
+  #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 15:0] Highest COS number supported for this ResID.
+    ///
+    UINT32  HighestCosNumber:16;
+    UINT32  Reserved:16;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX;
+
+/**
+  L2 Cache Allocation Technology Enumeration Sub-leaf
+
+  @param   EAX  CPUID_INTEL_RDT_ALLOCATION (0x10)
+  @param   ECX  CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02)
+
+  @retval  EAX  RESID L2 Cache Allocation Technology information described by
+                the type CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX.
+  @retval  EBX  Bit-granular map of isolation/contention of allocation units.
+  @retval  ECX  Reserved.
+  @retval  EDX  RESID L2 Cache Allocation Technology information described by
+                the type CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX.
+
+  <b>Example usage</b>
+  @code
+  CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX  Eax;
+  UINT32                                            Ebx;
+  CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX  Edx;
+
+  AsmCpuidEx (
+    CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF,
+    &Eax.Uint32, &Ebx, NULL, &Edx.Uint32
+    );
+  @endcode
+**/
+#define CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF        0x02
+
+/**
+  CPUID L2 Cache Allocation Technology Information EAX for CPUID leaf
+  #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
+  #CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID
+    /// using minus-one notation.
+    ///
+    UINT32  CapacityLength:5;
+    UINT32  Reserved:27;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX;
+
+/**
+  CPUID L2 Cache Allocation Technology Information EDX for CPUID leaf
+  #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
+  #CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 15:0] Highest COS number supported for this ResID.
+    ///
+    UINT32  HighestCosNumber:16;
+    UINT32  Reserved:16;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX;
+
+/**
+  Memory Bandwidth Allocation Enumeration Sub-leaf
+
+  @param   EAX  CPUID_INTEL_RDT_ALLOCATION (0x10)
+  @param   ECX  CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF (0x03)
+
+  @retval  EAX  RESID memory bandwidth Allocation Technology information
+                described by the type
+                CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX.
+  @retval  EBX  Reserved.
+  @retval  ECX  RESID memory bandwidth Allocation Technology information
+                described by the type
+                CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX.
+  @retval  EDX  RESID memory bandwidth Allocation Technology information
+                described by the type
+                CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX.
+
+  <b>Example usage</b>
+  @code
+  CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX  Eax;
+  UINT32                                                    Ebx;
+  CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX  Ecx;
+  CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX  Edx;
+
+
+  AsmCpuidEx (
+    CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF,
+    &Eax.Uint32, &Ebx, NULL, &Edx.Uint32
+    );
+  @endcode
+**/
+#define CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF        0x03
+
+/**
+  CPUID memory bandwidth Allocation Technology Information EAX for CPUID leaf
+  #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
+  #CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 11:0] Reports the maximum MBA throttling value supported for
+    /// the corresponding ResID using minus-one notation.
+    ///
+    UINT32  MaximumMBAThrottling:12;
+    UINT32  Reserved:20;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX;
+
+/**
+  CPUID memory bandwidth Allocation Technology Information ECX for CPUID leaf
+  #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
+  #CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 1:0] Reserved.
+    ///
+    UINT32  Reserved1:2;
+    ///
+    /// [Bits 3] Reports whether the response of the delay values is linear.
+    ///
+    UINT32  Liner:1;
+    UINT32  Reserved2:29;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX;
+
+/**
+  CPUID memory bandwidth Allocation Technology Information EDX for CPUID leaf
+  #CPUID_INTEL_RDT_ALLOCATION, sub-leaf
+  #CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 15:0] Highest COS number supported for this ResID.
+    ///
+    UINT32  HighestCosNumber:16;
+    UINT32  Reserved:16;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX;
+
+/**
+  Intel SGX resource capability and configuration.
+  See Section 37.7.2 "Intel(R) SGX Resource Enumeration Leaves".
+
+  If CPUID.(EAX=07H, ECX=0H):EBX.SGX = 1, the processor also supports querying
+  CPUID with EAX=12H on Intel SGX resource capability and configuration.
+
+  @param   EAX  CPUID_INTEL_SGX (0x12)
+  @param   ECX  CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00).
+                CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01).
+                CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02).
+                Sub leafs 2..n based on the sub-leaf-type encoding (returned in EAX[3:0])
+                until the sub-leaf type is invalid.
+
+**/
+#define CPUID_INTEL_SGX                                  0x12
+
+/**
+  Sub-Leaf 0 Enumeration of Intel SGX Capabilities.
+  Enumerates Intel SGX capability, including enclave instruction opcode support.
+
+  @param   EAX  CPUID_INTEL_SGX (0x12)
+  @param   ECX  CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00)
+
+  @retval  EAX  The format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is
+                described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX.
+  @retval  EBX  MISCSELECT: Reports the bit vector of supported extended features
+                that can be written to the MISC region of the SSA.
+  @retval  ECX  Reserved.
+  @retval  EDX  The format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is
+                described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX.
+
+  <b>Example usage</b>
+  @code
+  CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX  Eax;
+  UINT32                                       Ebx;
+  CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX  Edx;
+
+  AsmCpuidEx (
+    CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF,
+    &Eax.Uint32, &Ebx, NULL, &Edx.Uint32
+    );
+  @endcode
+**/
+#define CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF          0x00
+
+/**
+  Sub-Leaf 0 Enumeration of Intel SGX Capabilities EAX for CPUID leaf #CPUID_INTEL_SGX,
+  sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] If 1, indicates leaf functions of SGX1 instruction are supported.
+    ///
+    UINT32  SGX1:1;
+    ///
+    /// [Bit 1] If 1, indicates leaf functions of SGX2 instruction are supported.
+    ///
+    UINT32  SGX2:1;
+    UINT32  Reserved1:3;
+    ///
+    /// [Bit 5] If 1, indicates Intel SGX supports ENCLV instruction leaves
+    /// EINCVIRTCHILD, EDECVIRTCHILD, and ESETCONTEXT.
+    ///
+    UINT32  ENCLV:1;
+    ///
+    /// [Bit 6] If 1, indicates Intel SGX supports ENCLS instruction leaves ETRACKC,
+    /// ERDINFO, ELDBC, and ELDUC.
+    ///
+    UINT32  ENCLS:1;
+    UINT32  Reserved2:25;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX;
+
+/**
+  Sub-Leaf 0 Enumeration of Intel SGX Capabilities EDX for CPUID leaf #CPUID_INTEL_SGX,
+  sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 7:0] The maximum supported enclave size is 2^(EDX[7:0]) bytes
+    /// when not in 64-bit mode.
+    ///
+    UINT32  MaxEnclaveSize_Not64:8;
+    ///
+    /// [Bit 15:8] The maximum supported enclave size is 2^(EDX[15:8]) bytes
+    /// when operating in 64-bit mode.
+    ///
+    UINT32  MaxEnclaveSize_64:8;
+    UINT32  Reserved:16;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX;
+
+
+/**
+  Sub-Leaf 1 Enumeration of Intel SGX Capabilities.
+  Enumerates Intel SGX capability of processor state configuration and enclave
+  configuration in the SECS structure.
+
+  @param   EAX  CPUID_INTEL_SGX (0x12)
+  @param   ECX  CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01)
+
+  @retval  EAX  Report the valid bits of SECS.ATTRIBUTES[31:0] that software can
+                set with ECREATE. SECS.ATTRIBUTES[n] can be set to 1 using ECREATE
+                only if EAX[n] is 1, where n < 32.
+  @retval  EBX  Report the valid bits of SECS.ATTRIBUTES[63:32] that software can
+                set with ECREATE. SECS.ATTRIBUTES[n+32] can be set to 1 using ECREATE
+                only if EBX[n] is 1, where n < 32.
+  @retval  ECX  Report the valid bits of SECS.ATTRIBUTES[95:64] that software can
+                set with ECREATE. SECS.ATTRIBUTES[n+64] can be set to 1 using ECREATE
+                only if ECX[n] is 1, where n < 32.
+  @retval  EDX  Report the valid bits of SECS.ATTRIBUTES[127:96] that software can
+                set with ECREATE. SECS.ATTRIBUTES[n+96] can be set to 1 using ECREATE
+                only if EDX[n] is 1, where n < 32.
+
+  <b>Example usage</b>
+  @code
+  UINT32  Eax;
+  UINT32  Ebx;
+  UINT32  Ecx;
+  UINT32  Edx;
+
+  AsmCpuidEx (
+    CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF,
+    &Eax, &Ebx, &Ecx, &Edx
+    );
+  @endcode
+**/
+#define CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF          0x01
+
+
+/**
+  Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources.
+  Enumerates available EPC resources.
+
+  @param   EAX  CPUID_INTEL_SGX (0x12)
+  @param   ECX  CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02)
+
+  @retval  EAX  The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX
+                Resources is described by the type
+                CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX.
+  @retval  EBX  The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX
+                Resources is described by the type
+                CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX.
+  @retval  EDX  The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX
+                Resources is described by the type
+                CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX.
+  @retval  EDX  The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX
+                Resources is described by the type
+                CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX.
+
+  <b>Example usage</b>
+  @code
+  CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX  Eax;
+  CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX  Ebx;
+  CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX  Ecx;
+  CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX  Edx;
+
+  AsmCpuidEx (
+    CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF,
+    &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
+    );
+  @endcode
+**/
+#define CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF  0x02
+
+/**
+  Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EAX for CPUID
+  leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 3:0] Sub-leaf-type encoding.
+    /// 0000b: This sub-leaf is invalid, EBX:EAX and EDX:ECX report 0.
+    /// 0001b: This sub-leaf provides information on the Enclave Page Cache (EPC)
+    ///        in EBX:EAX and EDX:ECX.
+    /// All other encoding are reserved.
+    ///
+    UINT32  SubLeafType:4;
+    UINT32  Reserved:8;
+    ///
+    /// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the physical address of
+    /// the base of the EPC section.
+    ///
+    UINT32  LowAddressOfEpcSection:20;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX;
+
+/**
+  Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EBX for CPUID
+  leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the physical address of
+    /// the base of the EPC section.
+    ///
+    UINT32  HighAddressOfEpcSection:20;
+    UINT32  Reserved:12;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX;
+
+/**
+  Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources ECX for CPUID
+  leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 3:0] The EPC section encoding.
+    /// 0000b: Not valid.
+    /// 0001b: The EPC section is confidentiality, integrity and replay protected.
+    /// All other encoding are reserved.
+    ///
+    UINT32  EpcSection:4;
+    UINT32  Reserved:8;
+    ///
+    /// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the size of the
+    /// corresponding EPC section within the Processor Reserved Memory.
+    ///
+    UINT32  LowSizeOfEpcSection:20;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX;
+
+/**
+  Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EDX for CPUID
+  leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the size of the
+    /// corresponding EPC section within the Processor Reserved Memory.
+    ///
+    UINT32  HighSizeOfEpcSection:20;
+    UINT32  Reserved:12;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX;
+
+
+/**
+  CPUID Intel Processor Trace Information
+
+  @param   EAX  CPUID_INTEL_PROCESSOR_TRACE (0x14)
+  @param   ECX  CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF (0x00).
+                CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01).
+
+**/
+#define CPUID_INTEL_PROCESSOR_TRACE                         0x14
+
+/**
+  CPUID Intel Processor Trace Information Main Leaf
+
+  @param   EAX  CPUID_INTEL_PROCEDSSOR_TRACE (0x14)
+  @param   ECX  CPUID_INTEL_PROCEDSSOR_TRACE_MAIN_LEAF (0x00)
+
+  @retval  EAX  Reports the maximum sub-leaf supported in leaf 14H.
+  @retval  EBX  Returns Intel processor trace information described by the
+                type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX.
+  @retval  ECX  Returns Intel processor trace information described by the
+                type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX.
+  @retval  EDX  Reserved.
+
+  <b>Example usage</b>
+  @code
+  UINT32                                     Eax;
+  CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX  Ebx;
+  CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX  Ecx;
+
+  AsmCpuidEx (
+    CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,
+    &Eax, &Ebx.Uint32, &Ecx.Uint32, NULL
+    );
+  @endcode
+**/
+#define CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF               0x00
+
+/**
+  CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
+  sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] If 1, indicates that IA32_RTIT_CTL.CR3Filter can be set to 1,
+    /// and that IA32_RTIT_CR3_MATCH MSR can be accessed.
+    ///
+    UINT32  Cr3Filter:1;
+    ///
+    /// [Bit 1] If 1, indicates support of Configurable PSB and Cycle-Accurate
+    /// Mode.
+    ///
+    UINT32  ConfigurablePsb:1;
+    ///
+    /// [Bit 2] If 1, indicates support of IP Filtering, TraceStop filtering,
+    /// and preservation of Intel PT MSRs across warm reset.
+    ///
+    UINT32  IpTraceStopFiltering:1;
+    ///
+    /// [Bit 3] If 1, indicates support of MTC timing packet and suppression of
+    /// COFI-based packets.
+    ///
+    UINT32  Mtc:1;
+    ///
+    /// [Bit 4] If 1, indicates support of PTWRITE. Writes can set
+    /// IA32_RTIT_CTL[12] (PTWEn) and IA32_RTIT_CTL[5] (FUPonPTW), and PTWRITE
+    /// can generate packets.
+    ///
+    UINT32  PTWrite:1;
+    ///
+    /// [Bit 5] If 1, indicates support of Power Event Trace. Writes can set
+    /// IA32_RTIT_CTL[4] (PwrEvtEn), enabling Power Event Trace packet
+    /// generation.
+    ///
+    UINT32  PowerEventTrace:1;
+    UINT32  Reserved:26;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX;
+
+/**
+  CPUID Intel Processor Trace ECX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
+  sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] If 1, Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1, hence
+    /// utilizing the ToPA output scheme; IA32_RTIT_OUTPUT_BASE and
+    /// IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be accessed.
+    ///
+    UINT32  RTIT:1;
+    ///
+    /// [Bit 1] If 1, ToPA tables can hold any number of output entries, up to
+    /// the maximum allowed by the MaskOrTableOffset field of
+    /// IA32_RTIT_OUTPUT_MASK_PTRS.
+    ///
+    UINT32  ToPA:1;
+    ///
+    /// [Bit 2] If 1, indicates support of Single-Range Output scheme.
+    ///
+    UINT32  SingleRangeOutput:1;
+    ///
+    /// [Bit 3] If 1, indicates support of output to Trace Transport subsystem.
+    ///
+    UINT32  TraceTransportSubsystem:1;
+    UINT32  Reserved:27;
+    ///
+    /// [Bit 31] If 1, generated packets which contain IP payloads have LIP
+    /// values, which include the CS base component.
+    ///
+    UINT32  LIP:1;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX;
+
+
+/**
+  CPUID Intel Processor Trace Information Sub-leaf
+
+  @param   EAX  CPUID_INTEL_PROCEDSSOR_TRACE (0x14)
+  @param   ECX  CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01)
+
+  @retval  EAX  Returns Intel processor trace information described by the
+                type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX.
+  @retval  EBX  Returns Intel processor trace information described by the
+                type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX.
+  @retval  ECX  Reserved.
+  @retval  EDX  Reserved.
+
+  <b>Example usage</b>
+  @code
+  UINT32                                    MaximumSubLeaf;
+  UINT32                                    SubLeaf;
+  CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX  Eax;
+  CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX  Ebx;
+
+  AsmCpuidEx (
+    CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,
+    &MaximumSubLeaf, NULL, NULL, NULL
+    );
+
+  for (SubLeaf = CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF; SubLeaf <= MaximumSubLeaf; SubLeaf++) {
+    AsmCpuidEx (
+      CPUID_INTEL_PROCESSOR_TRACE, SubLeaf,
+      &Eax.Uint32, &Ebx.Uint32, NULL, NULL
+      );
+  }
+  @endcode
+**/
+#define CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF                0x01
+
+/**
+  CPUID Intel Processor Trace EAX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
+  sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 2:0] Number of configurable Address Ranges for filtering.
+    ///
+    UINT32  ConfigurableAddressRanges:3;
+    UINT32  Reserved:13;
+    ///
+    /// [Bits 31:16] Bitmap of supported MTC period encodings
+    ///
+    UINT32  MtcPeriodEncodings:16;
+
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX;
+
+/**
+  CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,
+  sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 15:0] Bitmap of supported Cycle Threshold value encodings.
+    ///
+    UINT32  CycleThresholdEncodings:16;
+    ///
+    /// [Bits 31:16] Bitmap of supported Configurable PSB frequency encodings.
+    ///
+    UINT32  PsbFrequencyEncodings:16;
+
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX;
+
+
+/**
+  CPUID Time Stamp Counter and Nominal Core Crystal Clock Information
+
+  @note
+  If EBX[31:0] is 0, the TSC/"core crystal clock" ratio is not enumerated.
+  EBX[31:0]/EAX[31:0] indicates the ratio of the TSC frequency and the core
+  crystal clock frequency.
+  If ECX is 0, the nominal core crystal clock frequency is not enumerated.
+  "TSC frequency" = "core crystal clock frequency" * EBX/EAX.
+  The core crystal clock may differ from the reference clock, bus clock, or core
+  clock frequencies.
+
+  @param   EAX  CPUID_TIME_STAMP_COUNTER (0x15)
+
+  @retval  EAX  An unsigned integer which is the denominator of the
+                TSC/"core crystal clock" ratio
+  @retval  EBX  An unsigned integer which is the numerator of the
+                TSC/"core crystal clock" ratio.
+  @retval  ECX  An unsigned integer which is the nominal frequency
+                of the core crystal clock in Hz.
+  @retval  EDX  Reserved.
+
+  <b>Example usage</b>
+  @code
+  UINT32  Eax;
+  UINT32  Ebx;
+  UINT32  Ecx;
+
+  AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, &Ecx, NULL);
+  @endcode
+**/
+#define CPUID_TIME_STAMP_COUNTER                            0x15
+
+
+/**
+  CPUID Processor Frequency Information
+
+  @note
+  Data is returned from this interface in accordance with the processor's
+  specification and does not reflect actual values. Suitable use of this data
+  includes the display of processor information in like manner to the processor
+  brand string and for determining the appropriate range to use when displaying
+  processor information e.g. frequency history graphs. The returned information
+  should not be used for any other purpose as the returned information does not
+  accurately correlate to information / counters returned by other processor
+  interfaces.  While a processor may support the Processor Frequency Information
+  leaf, fields that return a value of zero are not supported.
+
+  @param   EAX  CPUID_TIME_STAMP_COUNTER (0x16)
+
+  @retval  EAX  Returns processor base frequency information described by the
+                type CPUID_PROCESSOR_FREQUENCY_EAX.
+  @retval  EBX  Returns maximum frequency information described by the type
+                CPUID_PROCESSOR_FREQUENCY_EBX.
+  @retval  ECX  Returns bus frequency information described by the type
+                CPUID_PROCESSOR_FREQUENCY_ECX.
+  @retval  EDX  Reserved.
+
+  <b>Example usage</b>
+  @code
+  CPUID_PROCESSOR_FREQUENCY_EAX  Eax;
+  CPUID_PROCESSOR_FREQUENCY_EBX  Ebx;
+  CPUID_PROCESSOR_FREQUENCY_ECX  Ecx;
+
+  AsmCpuid (CPUID_PROCESSOR_FREQUENCY, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);
+  @endcode
+**/
+#define CPUID_PROCESSOR_FREQUENCY                           0x16
+
+/**
+  CPUID Processor Frequency Information EAX for CPUID leaf
+  #CPUID_PROCESSOR_FREQUENCY.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 15:0] Processor Base Frequency (in MHz).
+    ///
+    UINT32  ProcessorBaseFrequency:16;
+    UINT32  Reserved:16;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_PROCESSOR_FREQUENCY_EAX;
+
+/**
+  CPUID Processor Frequency Information EBX for CPUID leaf
+  #CPUID_PROCESSOR_FREQUENCY.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 15:0] Maximum Frequency (in MHz).
+    ///
+    UINT32  MaximumFrequency:16;
+    UINT32  Reserved:16;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_PROCESSOR_FREQUENCY_EBX;
+
+/**
+  CPUID Processor Frequency Information ECX for CPUID leaf
+  #CPUID_PROCESSOR_FREQUENCY.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 15:0] Bus (Reference) Frequency (in MHz).
+    ///
+    UINT32  BusFrequency:16;
+    UINT32  Reserved:16;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_PROCESSOR_FREQUENCY_ECX;
+
+
+/**
+  CPUID SoC Vendor Information
+
+  @param   EAX  CPUID_SOC_VENDOR (0x17)
+  @param   ECX  CPUID_SOC_VENDOR_MAIN_LEAF (0x00)
+                CPUID_SOC_VENDOR_BRAND_STRING1 (0x01)
+                CPUID_SOC_VENDOR_BRAND_STRING1 (0x02)
+                CPUID_SOC_VENDOR_BRAND_STRING1 (0x03)
+
+  @note
+  Leaf 17H output depends on the initial value in ECX.  SOC Vendor Brand String
+  is a UTF-8 encoded string padded with trailing bytes of 00H.  The complete SOC
+  Vendor Brand String is constructed by concatenating in ascending order of
+  EAX:EBX:ECX:EDX and from the sub-leaf 1 fragment towards sub-leaf 3.
+
+**/
+#define CPUID_SOC_VENDOR                                    0x17
+
+/**
+  CPUID SoC Vendor Information
+
+  @param   EAX  CPUID_SOC_VENDOR (0x17)
+  @param   ECX  CPUID_SOC_VENDOR_MAIN_LEAF (0x00)
+
+  @retval  EAX  MaxSOCID_Index. Reports the maximum input value of supported
+                sub-leaf in leaf 17H.
+  @retval  EBX  Returns SoC Vendor information described by the type
+                CPUID_SOC_VENDOR_MAIN_LEAF_EBX.
+  @retval  ECX  Project ID. A unique number an SOC vendor assigns to its SOC
+                projects.
+  @retval  EDX  Stepping ID. A unique number within an SOC project that an SOC
+                vendor assigns.
+
+  <b>Example usage</b>
+  @code
+  UINT32                          Eax;
+  CPUID_SOC_VENDOR_MAIN_LEAF_EBX  Ebx;
+  UINT32                          Ecx;
+  UINT32                          Edx;
+
+  AsmCpuidEx (
+    CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF,
+    &Eax, &Ebx.Uint32, &Ecx, &Edx
+    );
+  @endcode
+**/
+#define CPUID_SOC_VENDOR_MAIN_LEAF                          0x00
+
+/**
+  CPUID SoC Vendor Information EBX for CPUID leaf #CPUID_SOC_VENDOR sub-leaf
+  #CPUID_SOC_VENDOR_MAIN_LEAF.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 15:0] SOC Vendor ID.
+    ///
+    UINT32  SocVendorId:16;
+    ///
+    /// [Bit 16] If 1, the SOC Vendor ID field is assigned via an industry
+    /// standard enumeration scheme. Otherwise, the SOC Vendor ID field is
+    /// assigned by Intel.
+    ///
+    UINT32  IsVendorScheme:1;
+    UINT32  Reserved:15;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_SOC_VENDOR_MAIN_LEAF_EBX;
+
+/**
+  CPUID SoC Vendor Information
+
+  @param   EAX  CPUID_SOC_VENDOR (0x17)
+  @param   ECX  CPUID_SOC_VENDOR_BRAND_STRING1 (0x01)
+
+  @retval  EAX  SOC Vendor Brand String. UTF-8 encoded string of type
+                CPUID_SOC_VENDOR_BRAND_STRING_DATA.
+  @retval  EBX  SOC Vendor Brand String. UTF-8 encoded string of type
+                CPUID_SOC_VENDOR_BRAND_STRING_DATA.
+  @retval  ECX  SOC Vendor Brand String. UTF-8 encoded string of type
+                CPUID_SOC_VENDOR_BRAND_STRING_DATA.
+  @retval  EDX  SOC Vendor Brand String. UTF-8 encoded string of type
+                CPUID_SOC_VENDOR_BRAND_STRING_DATA.
+
+  <b>Example usage</b>
+  @code
+  CPUID_SOC_VENDOR_BRAND_STRING_DATA  Eax;
+  CPUID_SOC_VENDOR_BRAND_STRING_DATA  Ebx;
+  CPUID_SOC_VENDOR_BRAND_STRING_DATA  Ecx;
+  CPUID_SOC_VENDOR_BRAND_STRING_DATA  Edx;
+
+  AsmCpuidEx (
+    CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1,
+    &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
+    );
+  @endcode
+**/
+#define CPUID_SOC_VENDOR_BRAND_STRING1                      0x01
+
+/**
+  CPUID SoC Vendor Brand String for CPUID leafs #CPUID_SOC_VENDOR_BRAND_STRING1,
+  #CPUID_SOC_VENDOR_BRAND_STRING2, and #CPUID_SOC_VENDOR_BRAND_STRING3.
+**/
+typedef union {
+  ///
+  /// 4 UTF-8 characters of Soc Vendor Brand String
+  ///
+  CHAR8   BrandString[4];
+  ///
+  /// All fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_SOC_VENDOR_BRAND_STRING_DATA;
+
+/**
+  CPUID SoC Vendor Information
+
+  @param   EAX  CPUID_SOC_VENDOR (0x17)
+  @param   ECX  CPUID_SOC_VENDOR_BRAND_STRING2 (0x02)
+
+  @retval  EAX  SOC Vendor Brand String. UTF-8 encoded string of type
+                CPUID_SOC_VENDOR_BRAND_STRING_DATA.
+  @retval  EBX  SOC Vendor Brand String. UTF-8 encoded string of type
+                CPUID_SOC_VENDOR_BRAND_STRING_DATA.
+  @retval  ECX  SOC Vendor Brand String. UTF-8 encoded string of type
+                CPUID_SOC_VENDOR_BRAND_STRING_DATA.
+  @retval  EDX  SOC Vendor Brand String. UTF-8 encoded string of type
+                CPUID_SOC_VENDOR_BRAND_STRING_DATA.
+
+  <b>Example usage</b>
+  @code
+  CPUID_SOC_VENDOR_BRAND_STRING_DATA  Eax;
+  CPUID_SOC_VENDOR_BRAND_STRING_DATA  Ebx;
+  CPUID_SOC_VENDOR_BRAND_STRING_DATA  Ecx;
+  CPUID_SOC_VENDOR_BRAND_STRING_DATA  Edx;
+
+  AsmCpuidEx (
+    CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2,
+    &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
+    );
+  @endcode
+**/
+#define CPUID_SOC_VENDOR_BRAND_STRING2                      0x02
+
+/**
+  CPUID SoC Vendor Information
+
+  @param   EAX  CPUID_SOC_VENDOR (0x17)
+  @param   ECX  CPUID_SOC_VENDOR_BRAND_STRING3 (0x03)
+
+  @retval  EAX  SOC Vendor Brand String. UTF-8 encoded string of type
+                CPUID_SOC_VENDOR_BRAND_STRING_DATA.
+  @retval  EBX  SOC Vendor Brand String. UTF-8 encoded string of type
+                CPUID_SOC_VENDOR_BRAND_STRING_DATA.
+  @retval  ECX  SOC Vendor Brand String. UTF-8 encoded string of type
+                CPUID_SOC_VENDOR_BRAND_STRING_DATA.
+  @retval  EDX  SOC Vendor Brand String. UTF-8 encoded string of type
+                CPUID_SOC_VENDOR_BRAND_STRING_DATA.
+
+  <b>Example usage</b>
+  @code
+  CPUID_SOC_VENDOR_BRAND_STRING_DATA  Eax;
+  CPUID_SOC_VENDOR_BRAND_STRING_DATA  Ebx;
+  CPUID_SOC_VENDOR_BRAND_STRING_DATA  Ecx;
+  CPUID_SOC_VENDOR_BRAND_STRING_DATA  Edx;
+
+  AsmCpuidEx (
+    CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3,
+    &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32
+    );
+  @endcode
+**/
+#define CPUID_SOC_VENDOR_BRAND_STRING3                      0x03
+
+/**
+  CPUID Deterministic Address Translation Parameters
+
+  @note
+  Each sub-leaf enumerates a different address translation structure.
+  If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf
+  index n is invalid if n exceeds the value that sub-leaf 0 returns in EAX. A
+  sub-leaf index is also invalid if EDX[4:0] returns 0.
+  Valid sub-leaves do not need to be contiguous or in any particular order. A
+  valid sub-leaf may be in a higher input ECX value than an invalid sub-leaf or
+  than a valid sub-leaf of a higher or lower-level structure.
+  * Some unified TLBs will allow a single TLB entry to satisfy data read/write
+  and instruction fetches. Others will require separate entries (e.g., one
+  loaded on data read/write and another loaded on an instruction fetch).
+  Please see the Intel 64 and IA-32 Architectures Optimization Reference Manual
+  for details of a particular product.
+  ** Add one to the return value to get the result.
+
+  @param   EAX  CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS (0x18)
+  @param   ECX  CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF (0x00)
+                CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_SUB_LEAF  (0x*)
+
+**/
+#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS             0x18
+
+/**
+  CPUID Deterministic Address Translation Parameters
+
+  @param   EAX  CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS (0x18)
+  @param   ECX  CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF (0x00)
+
+  @retval  EAX  Reports the maximum input value of supported sub-leaf in leaf 18H.
+  @retval  EBX  Returns Deterministic Address Translation Parameters described by
+                the type CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX.
+  @retval  ECX  Number of Sets.
+  @retval  EDX  Returns Deterministic Address Translation Parameters described by
+                the type CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX.
+
+  <b>Example usage</b>
+  @code
+  UINT32                                                  Eax;
+  CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX  Ebx;
+  UINT32                                                  Ecx;
+  CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX  Edx;
+
+  AsmCpuidEx (
+    CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS,
+    CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF,
+    &Eax, &Ebx.Uint32, &Ecx, &Edx.Uint32
+    );
+  @endcode
+**/
+#define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF   0x00
+
+/**
+  CPUID Deterministic Address Translation Parameters EBX for CPUID leafs.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 0] 4K page size entries supported by this structure.
+    ///
+    UINT32  Page4K:1;
+    ///
+    /// [Bits 1] 2MB page size entries supported by this structure.
+    ///
+    UINT32  Page2M:1;
+    ///
+    /// [Bits 2] 4MB page size entries supported by this structure.
+    ///
+    UINT32  Page4M:1;
+    ///
+    /// [Bits 3] 1 GB page size entries supported by this structure.
+    ///
+    UINT32  Page1G:1;
+    ///
+    /// [Bits 7:4] Reserved.
+    ///
+    UINT32  Reserved1:4;
+    ///
+    /// [Bits 10:8] Partitioning (0: Soft partitioning between the logical
+    /// processors sharing this structure)
+    ///
+    UINT32  Partitioning:3;
+    ///
+    /// [Bits 15:11] Reserved.
+    ///
+    UINT32  Reserved2:5;
+    ///
+    /// [Bits 31:16] W = Ways of associativity.
+    ///
+    UINT32  Way:16;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX;
+
+/**
+  CPUID Deterministic Address Translation Parameters EDX for CPUID leafs.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 4:0] Translation cache type field.
+    ///
+    UINT32  TranslationCacheType:5;
+    ///
+    /// [Bits 7:5] Translation cache level (starts at 1).
+    ///
+    UINT32  TranslationCacheLevel:3;
+    ///
+    /// [Bits 8] Fully associative structure.
+    ///
+    UINT32  FullyAssociative:1;
+    ///
+    /// [Bits 13:9] Reserved.
+    ///
+    UINT32  Reserved1:5;
+    ///
+    /// [Bits 25:14] Maximum number of addressable IDs for logical
+    /// processors sharing this translation cache.
+    ///
+    UINT32  MaximumNum:12;
+    ///
+    /// [Bits 31:26] Reserved.
+    ///
+    UINT32  Reserved2:6;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX;
+
+///
+/// @{ Define value for CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX.TranslationCacheType
+///
+#define   CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_INVALID          0x00
+#define   CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_DATA_TLB         0x01
+#define   CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_INSTRUCTION_TLB  0x02
+#define   CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_UNIFIED_TLB      0x03
+///
+/// @}
+///
+
+
+/**
+  CPUID V2 Extended Topology Enumeration Leaf
+
+  @note
+  CPUID leaf 1FH is a preferred superset to leaf 0BH. Intel recommends first checking
+  for the existence of Leaf 1FH and using this if available.
+  Most of Leaf 1FH output depends on the initial value in ECX. The EDX output of leaf
+  1FH is always valid and does not vary with input value in ECX. Output value in ECX[7:0]
+  always equals input value in ECX[7:0]. Sub-leaf index 0 enumerates SMT level. Each
+  subsequent higher sub-leaf index enumerates a higher-level topological entity in
+  hierarchical order. For sub-leaves that return an invalid level-type of 0 in ECX[15:8];
+  EAX and EBX will return 0. If an input value n in ECX returns the invalid level-type of
+  0 in ECX[15:8], other input values with ECX > n also return 0 in ECX[15:8].
+
+  Software should use this field (EAX[4:0]) to enumerate processor topology of the system.
+  Software must not use EBX[15:0] to enumerate processor topology of the system. This value
+  in this field (EBX[15:0]) is only intended for display/diagnostic purposes. The actual
+  number of logical processors available to BIOS/OS/Applications may be different from the
+  value of EBX[15:0], depending on software and platform hardware configurations.
+
+  @param   EAX  CPUID_V2_EXTENDED_TOPOLOGY                        (0x1F)
+  @param   ECX  Level number
+
+**/
+#define CPUID_V2_EXTENDED_TOPOLOGY                                     0x1F
+
+///
+/// @{ Define value for CPUID_EXTENDED_TOPOLOGY_ECX.LevelType
+/// The value of the "level type" field is not related to level numbers in
+/// any way, higher "level type" values do not mean higher levels.
+///
+#define   CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE                  0x03
+#define   CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE                    0x04
+#define   CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE                     0x05
+///
+/// @}
+///
+
+/**
+  CPUID Extended Function
+
+  @param   EAX  CPUID_EXTENDED_FUNCTION (0x80000000)
+
+  @retval  EAX  Maximum Input Value for Extended Function CPUID Information.
+  @retval  EBX  Reserved.
+  @retval  ECX  Reserved.
+  @retval  EDX  Reserved.
+
+  <b>Example usage</b>
+  @code
+  UINT32  Eax;
+
+  AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL);
+  @endcode
+**/
+#define CPUID_EXTENDED_FUNCTION                 0x80000000
+
+
+/**
+  CPUID Extended Processor Signature and Feature Bits
+
+  @param   EAX  CPUID_EXTENDED_CPU_SIG (0x80000001)
+
+  @retval  EAX  CPUID_EXTENDED_CPU_SIG.
+  @retval  EBX  Reserved.
+  @retval  ECX  Extended Processor Signature and Feature Bits information
+                described by the type CPUID_EXTENDED_CPU_SIG_ECX.
+  @retval  EDX  Extended Processor Signature and Feature Bits information
+                described by the type CPUID_EXTENDED_CPU_SIG_EDX.
+
+  <b>Example usage</b>
+  @code
+  UINT32                      Eax;
+  CPUID_EXTENDED_CPU_SIG_ECX  Ecx;
+  CPUID_EXTENDED_CPU_SIG_EDX  Edx;
+
+  AsmCpuid (CPUID_EXTENDED_CPU_SIG, &Eax, NULL, &Ecx.Uint32, &Edx.Uint32);
+  @endcode
+**/
+#define CPUID_EXTENDED_CPU_SIG                  0x80000001
+
+/**
+  CPUID Extended Processor Signature and Feature Bits ECX for CPUID leaf
+  #CPUID_EXTENDED_CPU_SIG.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] LAHF/SAHF available in 64-bit mode.
+    ///
+    UINT32  LAHF_SAHF:1;
+    UINT32  Reserved1:4;
+    ///
+    /// [Bit 5] LZCNT.
+    ///
+    UINT32  LZCNT:1;
+    UINT32  Reserved2:2;
+    ///
+    /// [Bit 8] PREFETCHW.
+    ///
+    UINT32  PREFETCHW:1;
+    UINT32  Reserved3:23;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_EXTENDED_CPU_SIG_ECX;
+
+/**
+  CPUID Extended Processor Signature and Feature Bits EDX for CPUID leaf
+  #CPUID_EXTENDED_CPU_SIG.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:11;
+    ///
+    /// [Bit 11] SYSCALL/SYSRET available in 64-bit mode.
+    ///
+    UINT32  SYSCALL_SYSRET:1;
+    UINT32  Reserved2:8;
+    ///
+    /// [Bit 20] Execute Disable Bit available.
+    ///
+    UINT32  NX:1;
+    UINT32  Reserved3:5;
+    ///
+    /// [Bit 26] 1-GByte pages are available if 1.
+    ///
+    UINT32  Page1GB:1;
+    ///
+    /// [Bit 27] RDTSCP and IA32_TSC_AUX are available if 1.
+    ///
+    UINT32  RDTSCP:1;
+    UINT32  Reserved4:1;
+    ///
+    /// [Bit 29] Intel(R) 64 Architecture available if 1.
+    ///
+    UINT32  LM:1;
+    UINT32  Reserved5:2;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_EXTENDED_CPU_SIG_EDX;
+
+
+/**
+  CPUID Processor Brand String
+
+  @param   EAX  CPUID_BRAND_STRING1 (0x80000002)
+
+  @retval  EAX  Processor Brand String in type CPUID_BRAND_STRING_DATA.
+  @retval  EBX  Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
+  @retval  ECX  Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
+  @retval  EDX  Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
+
+  <b>Example usage</b>
+  @code
+  CPUID_BRAND_STRING_DATA  Eax;
+  CPUID_BRAND_STRING_DATA  Ebx;
+  CPUID_BRAND_STRING_DATA  Ecx;
+  CPUID_BRAND_STRING_DATA  Edx;
+
+  AsmCpuid (CPUID_BRAND_STRING1, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
+  @endcode
+**/
+#define CPUID_BRAND_STRING1                     0x80000002
+
+/**
+  CPUID Processor Brand String for CPUID leafs #CPUID_BRAND_STRING1,
+  #CPUID_BRAND_STRING2, and #CPUID_BRAND_STRING3.
+**/
+typedef union {
+  ///
+  /// 4 ASCII characters of Processor Brand String
+  ///
+  CHAR8   BrandString[4];
+  ///
+  /// All fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_BRAND_STRING_DATA;
+
+/**
+  CPUID Processor Brand String
+
+  @param   EAX  CPUID_BRAND_STRING2 (0x80000003)
+
+  @retval  EAX  Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
+  @retval  EBX  Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
+  @retval  ECX  Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
+  @retval  EDX  Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
+
+  <b>Example usage</b>
+  @code
+  CPUID_BRAND_STRING_DATA  Eax;
+  CPUID_BRAND_STRING_DATA  Ebx;
+  CPUID_BRAND_STRING_DATA  Ecx;
+  CPUID_BRAND_STRING_DATA  Edx;
+
+  AsmCpuid (CPUID_BRAND_STRING2, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
+  @endcode
+**/
+#define CPUID_BRAND_STRING2                     0x80000003
+
+/**
+  CPUID Processor Brand String
+
+  @param   EAX  CPUID_BRAND_STRING3 (0x80000004)
+
+  @retval  EAX  Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
+  @retval  EBX  Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
+  @retval  ECX  Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
+  @retval  EDX  Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.
+
+  <b>Example usage</b>
+  @code
+  CPUID_BRAND_STRING_DATA  Eax;
+  CPUID_BRAND_STRING_DATA  Ebx;
+  CPUID_BRAND_STRING_DATA  Ecx;
+  CPUID_BRAND_STRING_DATA  Edx;
+
+  AsmCpuid (CPUID_BRAND_STRING3, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);
+  @endcode
+**/
+#define CPUID_BRAND_STRING3                     0x80000004
+
+
+/**
+  CPUID Extended Cache information
+
+  @param   EAX  CPUID_EXTENDED_CACHE_INFO (0x80000006)
+
+  @retval  EAX  Reserved.
+  @retval  EBX  Reserved.
+  @retval  ECX  Extended cache information described by the type
+                CPUID_EXTENDED_CACHE_INFO_ECX.
+  @retval  EDX  Reserved.
+
+  <b>Example usage</b>
+  @code
+  CPUID_EXTENDED_CACHE_INFO_ECX  Ecx;
+
+  AsmCpuid (CPUID_EXTENDED_CACHE_INFO, NULL, NULL, &Ecx.Uint32, NULL);
+  @endcode
+**/
+#define CPUID_EXTENDED_CACHE_INFO               0x80000006
+
+/**
+  CPUID Extended Cache information ECX for CPUID leaf #CPUID_EXTENDED_CACHE_INFO.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Cache line size in bytes.
+    ///
+    UINT32  CacheLineSize:8;
+    UINT32  Reserved:4;
+    ///
+    /// [Bits 15:12] L2 Associativity field.  Supported values are in the range
+    /// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED to
+    /// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL
+    ///
+    UINT32  L2Associativity:4;
+    ///
+    /// [Bits 31:16] Cache size in 1K units.
+    ///
+    UINT32  CacheSize:16;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_EXTENDED_CACHE_INFO_ECX;
+
+///
+/// @{ Define value for bit field CPUID_EXTENDED_CACHE_INFO_ECX.L2Associativity
+///
+#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED       0x00
+#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DIRECT_MAPPED  0x01
+#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_2_WAY          0x02
+#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_4_WAY          0x04
+#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_8_WAY          0x06
+#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_16_WAY         0x08
+#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_32_WAY         0x0A
+#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_48_WAY         0x0B
+#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_64_WAY         0x0C
+#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_96_WAY         0x0D
+#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_128_WAY        0x0E
+#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL           0x0F
+///
+/// @}
+///
+
+/**
+  CPUID Extended Time Stamp Counter information
+
+  @param   EAX  CPUID_EXTENDED_TIME_STAMP_COUNTER (0x80000007)
+
+  @retval  EAX  Reserved.
+  @retval  EBX  Reserved.
+  @retval  ECX  Reserved.
+  @retval  EDX  Extended time stamp counter (TSC) information described by the
+                type CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX.
+
+  <b>Example usage</b>
+  @code
+  CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX  Edx;
+
+  AsmCpuid (CPUID_EXTENDED_TIME_STAMP_COUNTER, NULL, NULL, NULL, &Edx.Uint32);
+  @endcode
+**/
+#define CPUID_EXTENDED_TIME_STAMP_COUNTER       0x80000007
+
+/**
+  CPUID Extended Time Stamp Counter information EDX for CPUID leaf
+  #CPUID_EXTENDED_TIME_STAMP_COUNTER.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:8;
+    ///
+    /// [Bit 8] Invariant TSC available if 1.
+    ///
+    UINT32  InvariantTsc:1;
+    UINT32  Reserved2:23;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX;
+
+
+/**
+  CPUID Linear Physical Address Size
+
+  @param   EAX  CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008)
+
+  @retval  EAX  Linear/Physical Address Size described by the type
+                CPUID_VIR_PHY_ADDRESS_SIZE_EAX.
+  @retval  EBX  Reserved.
+  @retval  ECX  Reserved.
+  @retval  EDX  Reserved.
+
+  <b>Example usage</b>
+  @code
+  CPUID_VIR_PHY_ADDRESS_SIZE_EAX  Eax;
+
+  AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &Eax.Uint32, NULL, NULL, NULL);
+  @endcode
+**/
+#define CPUID_VIR_PHY_ADDRESS_SIZE              0x80000008
+
+/**
+  CPUID Linear Physical Address Size EAX for CPUID leaf
+  #CPUID_VIR_PHY_ADDRESS_SIZE.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Number of physical address bits.
+    ///
+    /// @note
+    /// If CPUID.80000008H:EAX[7:0] is supported, the maximum physical address
+    /// number supported should come from this field.
+    ///
+    UINT32  PhysicalAddressBits:8;
+    ///
+    /// [Bits 15:8] Number of linear address bits.
+    ///
+    UINT32  LinearAddressBits:8;
+    UINT32  Reserved:16;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+} CPUID_VIR_PHY_ADDRESS_SIZE_EAX;
+
+#endif
diff --git a/MdePkg/Include/Register/Intel/LocalApic.h b/MdePkg/Include/Register/Intel/LocalApic.h
new file mode 100644
index 000000000000..5bc7f4149ad6
--- /dev/null
+++ b/MdePkg/Include/Register/Intel/LocalApic.h
@@ -0,0 +1,183 @@
+/** @file
+  IA32 Local APIC Definitions.
+
+  Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __INTEL_LOCAL_APIC_H__
+#define __INTEL_LOCAL_APIC_H__
+
+//
+// Definition for Local APIC registers and related values
+//
+#define XAPIC_ID_OFFSET                         0x20
+#define XAPIC_VERSION_OFFSET                    0x30
+#define XAPIC_EOI_OFFSET                        0x0b0
+#define XAPIC_ICR_DFR_OFFSET                    0x0e0
+#define XAPIC_SPURIOUS_VECTOR_OFFSET            0x0f0
+#define XAPIC_ICR_LOW_OFFSET                    0x300
+#define XAPIC_ICR_HIGH_OFFSET                   0x310
+#define XAPIC_LVT_TIMER_OFFSET                  0x320
+#define XAPIC_LVT_LINT0_OFFSET                  0x350
+#define XAPIC_LVT_LINT1_OFFSET                  0x360
+#define XAPIC_TIMER_INIT_COUNT_OFFSET           0x380
+#define XAPIC_TIMER_CURRENT_COUNT_OFFSET        0x390
+#define XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET 0x3E0
+
+#define X2APIC_MSR_BASE_ADDRESS                 0x800
+#define X2APIC_MSR_ICR_ADDRESS                  0x830
+
+#define LOCAL_APIC_DELIVERY_MODE_FIXED           0
+#define LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY 1
+#define LOCAL_APIC_DELIVERY_MODE_SMI             2
+#define LOCAL_APIC_DELIVERY_MODE_NMI             4
+#define LOCAL_APIC_DELIVERY_MODE_INIT            5
+#define LOCAL_APIC_DELIVERY_MODE_STARTUP         6
+#define LOCAL_APIC_DELIVERY_MODE_EXTINT          7
+
+#define LOCAL_APIC_DESTINATION_SHORTHAND_NO_SHORTHAND       0
+#define LOCAL_APIC_DESTINATION_SHORTHAND_SELF               1
+#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_INCLUDING_SELF 2
+#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF 3
+
+//
+// Local APIC Version Register.
+//
+typedef union {
+  struct {
+    UINT32  Version:8;                  ///< The version numbers of the local APIC.
+    UINT32  Reserved0:8;                ///< Reserved.
+    UINT32  MaxLvtEntry:8;              ///< Number of LVT entries minus 1.
+    UINT32  EoiBroadcastSuppression:1;  ///< 1 if EOI-broadcast suppression supported.
+    UINT32  Reserved1:7;                ///< Reserved.
+  } Bits;
+  UINT32    Uint32;
+} LOCAL_APIC_VERSION;
+
+//
+// Low half of Interrupt Command Register (ICR).
+//
+typedef union {
+  struct {
+    UINT32  Vector:8;                ///< The vector number of the interrupt being sent.
+    UINT32  DeliveryMode:3;          ///< Specifies the type of IPI to be sent.
+    UINT32  DestinationMode:1;       ///< 0: physical destination mode, 1: logical destination mode.
+    UINT32  DeliveryStatus:1;        ///< Indicates the IPI delivery status. This field is reserved in x2APIC mode.
+    UINT32  Reserved0:1;             ///< Reserved.
+    UINT32  Level:1;                 ///< 0 for the INIT level de-assert delivery mode. Otherwise 1.
+    UINT32  TriggerMode:1;           ///< 0: edge, 1: level when using the INIT level de-assert delivery mode.
+    UINT32  Reserved1:2;             ///< Reserved.
+    UINT32  DestinationShorthand:2;  ///< A shorthand notation to specify the destination of the interrupt.
+    UINT32  Reserved2:12;            ///< Reserved.
+  } Bits;
+  UINT32    Uint32;
+} LOCAL_APIC_ICR_LOW;
+
+//
+// High half of Interrupt Command Register (ICR)
+//
+typedef union {
+  struct {
+    UINT32  Reserved0:24;   ///< Reserved.
+    UINT32  Destination:8;  ///< Specifies the target processor or processors in xAPIC mode.
+  } Bits;
+  UINT32    Uint32;         ///< Destination field expanded to 32-bit in x2APIC mode.
+} LOCAL_APIC_ICR_HIGH;
+
+//
+// Spurious-Interrupt Vector Register (SVR)
+//
+typedef union {
+  struct {
+    UINT32  SpuriousVector:8;           ///< Spurious Vector.
+    UINT32  SoftwareEnable:1;           ///< APIC Software Enable/Disable.
+    UINT32  FocusProcessorChecking:1;   ///< Focus Processor Checking.
+    UINT32  Reserved0:2;                ///< Reserved.
+    UINT32  EoiBroadcastSuppression:1;  ///< EOI-Broadcast Suppression.
+    UINT32  Reserved1:19;               ///< Reserved.
+  } Bits;
+  UINT32    Uint32;
+} LOCAL_APIC_SVR;
+
+//
+// Divide Configuration Register (DCR)
+//
+typedef union {
+  struct {
+    UINT32  DivideValue1:2;  ///< Low 2 bits of the divide value.
+    UINT32  Reserved0:1;     ///< Always 0.
+    UINT32  DivideValue2:1;  ///< Highest 1 bit of the divide value.
+    UINT32  Reserved1:28;    ///< Reserved.
+  } Bits;
+  UINT32    Uint32;
+} LOCAL_APIC_DCR;
+
+//
+// LVT Timer Register
+//
+typedef union {
+  struct {
+    UINT32  Vector:8;          ///< The vector number of the interrupt being sent.
+    UINT32  Reserved0:4;       ///< Reserved.
+    UINT32  DeliveryStatus:1;  ///< 0: Idle, 1: send pending.
+    UINT32  Reserved1:3;       ///< Reserved.
+    UINT32  Mask:1;            ///< 0: Not masked, 1: Masked.
+    UINT32  TimerMode:1;       ///< 0: One-shot, 1: Periodic.
+    UINT32  Reserved2:14;      ///< Reserved.
+  } Bits;
+  UINT32    Uint32;
+} LOCAL_APIC_LVT_TIMER;
+
+//
+// LVT LINT0/LINT1 Register
+//
+typedef union {
+  struct {
+    UINT32  Vector:8;            ///< The vector number of the interrupt being sent.
+    UINT32  DeliveryMode:3;      ///< Specifies the type of interrupt to be sent.
+    UINT32  Reserved0:1;         ///< Reserved.
+    UINT32  DeliveryStatus:1;    ///< 0: Idle, 1: send pending.
+    UINT32  InputPinPolarity:1;  ///< Interrupt Input Pin Polarity.
+    UINT32  RemoteIrr:1;         ///< RO. Set when the local APIC accepts the interrupt and reset when an EOI is received.
+    UINT32  TriggerMode:1;       ///< 0:edge, 1:level.
+    UINT32  Mask:1;              ///< 0: Not masked, 1: Masked.
+    UINT32  Reserved1:15;        ///< Reserved.
+  } Bits;
+  UINT32    Uint32;
+} LOCAL_APIC_LVT_LINT;
+
+//
+// MSI Address Register
+//
+typedef union {
+  struct {
+    UINT32  Reserved0:2;         ///< Reserved
+    UINT32  DestinationMode:1;   ///< Specifies the Destination Mode.
+    UINT32  RedirectionHint:1;   ///< Specifies the Redirection Hint.
+    UINT32  Reserved1:8;         ///< Reserved.
+    UINT32  DestinationId:8;     ///< Specifies the Destination ID.
+    UINT32  BaseAddress:12;      ///< Must be 0FEEH
+  } Bits;
+  UINT32    Uint32;
+} LOCAL_APIC_MSI_ADDRESS;
+
+//
+// MSI Address Register
+//
+typedef union {
+  struct {
+    UINT32  Vector:8;            ///< Interrupt vector in range 010h..0FEH
+    UINT32  DeliveryMode:3;      ///< Specifies the type of interrupt to be sent.
+    UINT32  Reserved0:3;         ///< Reserved.
+    UINT32  Level:1;             ///< 0:Deassert, 1:Assert.  Ignored for Edge triggered interrupts.
+    UINT32  TriggerMode:1;       ///< 0:Edge,     1:Level.
+    UINT32  Reserved1:16;        ///< Reserved.
+    UINT32  Reserved2:32;        ///< Reserved.
+  } Bits;
+  UINT64    Uint64;
+} LOCAL_APIC_MSI_DATA;
+
+#endif
+
diff --git a/MdePkg/Include/Register/Intel/Microcode.h b/MdePkg/Include/Register/Intel/Microcode.h
new file mode 100644
index 000000000000..3834fe64e860
--- /dev/null
+++ b/MdePkg/Include/Register/Intel/Microcode.h
@@ -0,0 +1,194 @@
+/** @file
+  Microcode Definitions.
+
+  Microcode Definitions based on contents of the
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual
+    Volume 3A, Section 9.11  Microcode Definitions
+
+  Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3A,
+  June 2016, Chapter 9 Processor Management and Initialization, Section 9-11.
+
+**/
+
+#ifndef __INTEL_MICROCODE_H__
+#define __INTEL_MICROCODE_H__
+
+///
+/// CPU Microcode Date in BCD format
+///
+typedef union {
+  struct {
+    UINT32   Year:16;
+    UINT32   Day:8;
+    UINT32   Month:8;
+  } Bits;
+  UINT32     Uint32;
+} CPU_MICROCODE_DATE;
+
+///
+/// CPU Microcode Processor Signature format
+///
+typedef union {
+  struct {
+    UINT32   Stepping:4;
+    UINT32   Model:4;
+    UINT32   Family:4;
+    UINT32   Type:2;
+    UINT32   Reserved1:2;
+    UINT32   ExtendedModel:4;
+    UINT32   ExtendedFamily:8;
+    UINT32   Reserved2:4;
+  } Bits;
+  UINT32     Uint32;
+} CPU_MICROCODE_PROCESSOR_SIGNATURE;
+
+#pragma pack (1)
+
+///
+/// Microcode Update Format definition
+///
+typedef struct {
+  ///
+  /// Version number of the update header
+  ///
+  UINT32                            HeaderVersion;
+  ///
+  /// Unique version number for the update, the basis for the update
+  /// signature provided by the processor to indicate the current update
+  /// functioning within the processor. Used by the BIOS to authenticate
+  /// the update and verify that the processor loads successfully. The
+  /// value in this field cannot be used for processor stepping identification
+  /// alone. This is a signed 32-bit number.
+  ///
+  UINT32                            UpdateRevision;
+  ///
+  /// Date of the update creation in binary format: mmddyyyy (e.g.
+  /// 07/18/98 is 07181998H).
+  ///
+  CPU_MICROCODE_DATE                Date;
+  ///
+  /// Extended family, extended model, type, family, model, and stepping
+  /// of processor that requires this particular update revision (e.g.,
+  /// 00000650H). Each microcode update is designed specifically for a
+  /// given extended family, extended model, type, family, model, and
+  /// stepping of the processor.
+  /// The BIOS uses the processor signature field in conjunction with the
+  /// CPUID instruction to determine whether or not an update is
+  /// appropriate to load on a processor. The information encoded within
+  /// this field exactly corresponds to the bit representations returned by
+  /// the CPUID instruction.
+  ///
+  CPU_MICROCODE_PROCESSOR_SIGNATURE ProcessorSignature;
+  ///
+  /// Checksum of Update Data and Header. Used to verify the integrity of
+  /// the update header and data. Checksum is correct when the
+  /// summation of all the DWORDs (including the extended Processor
+  /// Signature Table) that comprise the microcode update result in
+  /// 00000000H.
+  ///
+  UINT32                            Checksum;
+  ///
+  /// Version number of the loader program needed to correctly load this
+  /// update. The initial version is 00000001H
+  ///
+  UINT32                            LoaderRevision;
+  ///
+  /// Platform type information is encoded in the lower 8 bits of this 4-
+  /// byte field. Each bit represents a particular platform type for a given
+  /// CPUID. The BIOS uses the processor flags field in conjunction with
+  /// the platform Id bits in MSR (17H) to determine whether or not an
+  /// update is appropriate to load on a processor. Multiple bits may be set
+  /// representing support for multiple platform IDs.
+  ///
+  UINT32                            ProcessorFlags;
+  ///
+  /// Specifies the size of the encrypted data in bytes, and must be a
+  /// multiple of DWORDs. If this value is 00000000H, then the microcode
+  /// update encrypted data is 2000 bytes (or 500 DWORDs).
+  ///
+  UINT32                            DataSize;
+  ///
+  /// Specifies the total size of the microcode update in bytes. It is the
+  /// summation of the header size, the encrypted data size and the size of
+  /// the optional extended signature table. This value is always a multiple
+  /// of 1024.
+  ///
+  UINT32                            TotalSize;
+  ///
+  /// Reserved fields for future expansion.
+  ///
+  UINT8                             Reserved[12];
+} CPU_MICROCODE_HEADER;
+
+///
+/// Extended Signature Table Header Field Definitions
+///
+typedef struct {
+  ///
+  /// Specifies the number of extended signature structures (Processor
+  /// Signature[n], processor flags[n] and checksum[n]) that exist in this
+  /// microcode update
+  ///
+  UINT32                            ExtendedSignatureCount;
+  ///
+  /// Checksum of update extended processor signature table. Used to
+  /// verify the integrity of the extended processor signature table.
+  /// Checksum is correct when the summation of the DWORDs that
+  /// comprise the extended processor signature table results in
+  /// 00000000H.
+  ///
+  UINT32                            ExtendedChecksum;
+  ///
+  /// Reserved fields.
+  ///
+  UINT8                             Reserved[12];
+} CPU_MICROCODE_EXTENDED_TABLE_HEADER;
+
+///
+/// Extended Signature Table Field Definitions
+///
+typedef struct {
+  ///
+  /// Extended family, extended model, type, family, model, and stepping
+  /// of processor that requires this particular update revision (e.g.,
+  /// 00000650H). Each microcode update is designed specifically for a
+  /// given extended family, extended model, type, family, model, and
+  /// stepping of the processor.
+  /// The BIOS uses the processor signature field in conjunction with the
+  /// CPUID instruction to determine whether or not an update is
+  /// appropriate to load on a processor. The information encoded within
+  /// this field exactly corresponds to the bit representations returned by
+  /// the CPUID instruction.
+  ///
+  CPU_MICROCODE_PROCESSOR_SIGNATURE ProcessorSignature;
+  ///
+  /// Platform type information is encoded in the lower 8 bits of this 4-
+  /// byte field. Each bit represents a particular platform type for a given
+  /// CPUID. The BIOS uses the processor flags field in conjunction with
+  /// the platform Id bits in MSR (17H) to determine whether or not an
+  /// update is appropriate to load on a processor. Multiple bits may be set
+  /// representing support for multiple platform IDs.
+  ///
+  UINT32                             ProcessorFlag;
+  ///
+  /// Used by utility software to decompose a microcode update into
+  /// multiple microcode updates where each of the new updates is
+  /// constructed without the optional Extended Processor Signature
+  /// Table.
+  /// To calculate the Checksum, substitute the Primary Processor
+  /// Signature entry and the Processor Flags entry with the
+  /// corresponding Extended Patch entry. Delete the Extended Processor
+  /// Signature Table entries. The Checksum is correct when the
+  /// summation of all DWORDs that comprise the created Extended
+  /// Processor Patch results in 00000000H.
+  ///
+  UINT32                             Checksum;
+} CPU_MICROCODE_EXTENDED_TABLE;
+
+#pragma pack ()
+
+#endif
diff --git a/MdePkg/Include/Register/Intel/Msr.h b/MdePkg/Include/Register/Intel/Msr.h
new file mode 100644
index 000000000000..4f6172a16e09
--- /dev/null
+++ b/MdePkg/Include/Register/Intel/Msr.h
@@ -0,0 +1,44 @@
+/** @file
+  MSR Definitions.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016 ~ 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+  May 2018, Volume 4: Model-Specific-Registers (MSR)
+
+**/
+
+#ifndef __INTEL_MSR_H__
+#define __INTEL_MSR_H__
+
+#include <Register/Intel/ArchitecturalMsr.h>
+#include <Register/Intel/Msr/Core2Msr.h>
+#include <Register/Intel/Msr/AtomMsr.h>
+#include <Register/Intel/Msr/SilvermontMsr.h>
+#include <Register/Intel/Msr/GoldmontMsr.h>
+#include <Register/Intel/Msr/GoldmontPlusMsr.h>
+#include <Register/Intel/Msr/NehalemMsr.h>
+#include <Register/Intel/Msr/Xeon5600Msr.h>
+#include <Register/Intel/Msr/XeonE7Msr.h>
+#include <Register/Intel/Msr/SandyBridgeMsr.h>
+#include <Register/Intel/Msr/IvyBridgeMsr.h>
+#include <Register/Intel/Msr/HaswellMsr.h>
+#include <Register/Intel/Msr/HaswellEMsr.h>
+#include <Register/Intel/Msr/BroadwellMsr.h>
+#include <Register/Intel/Msr/XeonDMsr.h>
+#include <Register/Intel/Msr/SkylakeMsr.h>
+#include <Register/Intel/Msr/XeonPhiMsr.h>
+#include <Register/Intel/Msr/Pentium4Msr.h>
+#include <Register/Intel/Msr/CoreMsr.h>
+#include <Register/Intel/Msr/PentiumMMsr.h>
+#include <Register/Intel/Msr/P6Msr.h>
+#include <Register/Intel/Msr/PentiumMsr.h>
+
+#endif
diff --git a/MdePkg/Include/Register/Intel/Msr/AtomMsr.h b/MdePkg/Include/Register/Intel/Msr/AtomMsr.h
new file mode 100644
index 000000000000..20bfd1fe6c74
--- /dev/null
+++ b/MdePkg/Include/Register/Intel/Msr/AtomMsr.h
@@ -0,0 +1,784 @@
+/** @file
+  MSR Definitions for the Intel(R) Atom(TM) Processor Family.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+  May 2018, Volume 4: Model-Specific-Registers (MSR)
+
+**/
+
+#ifndef __ATOM_MSR_H__
+#define __ATOM_MSR_H__
+
+#include <Register/Intel/ArchitecturalMsr.h>
+
+/**
+  Is Intel(R) Atom(TM) Processor Family?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_ATOM_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (                        \
+    DisplayModel == 0x1C || \
+    DisplayModel == 0x26 || \
+    DisplayModel == 0x27 || \
+    DisplayModel == 0x35 || \
+    DisplayModel == 0x36    \
+    )                       \
+   )
+
+/**
+  Shared. Model Specific Platform ID (R).
+
+  @param  ECX  MSR_ATOM_PLATFORM_ID (0x00000017)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_ATOM_PLATFORM_ID_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_ATOM_PLATFORM_ID_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_ATOM_PLATFORM_ID_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PLATFORM_ID);
+  @endcode
+  @note MSR_ATOM_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.
+**/
+#define MSR_ATOM_PLATFORM_ID                     0x00000017
+
+/**
+  MSR information returned for MSR index #MSR_ATOM_PLATFORM_ID
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:8;
+    ///
+    /// [Bits 12:8] Maximum Qualified Ratio (R)  The maximum allowed bus ratio.
+    ///
+    UINT32  MaximumQualifiedRatio:5;
+    UINT32  Reserved2:19;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_ATOM_PLATFORM_ID_REGISTER;
+
+
+/**
+  Shared. Processor Hard Power-On Configuration (R/W) Enables and disables
+  processor features; (R) indicates current processor configuration.
+
+  @param  ECX  MSR_ATOM_EBL_CR_POWERON (0x0000002A)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_ATOM_EBL_CR_POWERON_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_EBL_CR_POWERON);
+  AsmWriteMsr64 (MSR_ATOM_EBL_CR_POWERON, Msr.Uint64);
+  @endcode
+  @note MSR_ATOM_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
+**/
+#define MSR_ATOM_EBL_CR_POWERON                  0x0000002A
+
+/**
+  MSR information returned for MSR index #MSR_ATOM_EBL_CR_POWERON
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
+    /// Always 0.
+    ///
+    UINT32  DataErrorCheckingEnable:1;
+    ///
+    /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
+    /// Always 0.
+    ///
+    UINT32  ResponseErrorCheckingEnable:1;
+    ///
+    /// [Bit 3] AERR# Drive Enable (R/W)  1 = Enabled; 0 = Disabled Always 0.
+    ///
+    UINT32  AERR_DriveEnable:1;
+    ///
+    /// [Bit 4] BERR# Enable for initiator bus requests (R/W) 1 = Enabled; 0 =
+    /// Disabled Always 0.
+    ///
+    UINT32  BERR_Enable:1;
+    UINT32  Reserved2:1;
+    UINT32  Reserved3:1;
+    ///
+    /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.
+    ///
+    UINT32  BINIT_DriverEnable:1;
+    UINT32  Reserved4:1;
+    ///
+    /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
+    ///
+    UINT32  ExecuteBIST:1;
+    ///
+    /// [Bit 10] AERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
+    /// Always 0.
+    ///
+    UINT32  AERR_ObservationEnabled:1;
+    UINT32  Reserved5:1;
+    ///
+    /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
+    /// Always 0.
+    ///
+    UINT32  BINIT_ObservationEnabled:1;
+    UINT32  Reserved6:1;
+    ///
+    /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.
+    ///
+    UINT32  ResetVector:1;
+    UINT32  Reserved7:1;
+    ///
+    /// [Bits 17:16] APIC Cluster ID (R/O) Always 00B.
+    ///
+    UINT32  APICClusterID:2;
+    UINT32  Reserved8:2;
+    ///
+    /// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B.
+    ///
+    UINT32  SymmetricArbitrationID:2;
+    ///
+    /// [Bits 26:22] Integer Bus Frequency Ratio (R/O).
+    ///
+    UINT32  IntegerBusFrequencyRatio:5;
+    UINT32  Reserved9:5;
+    UINT32  Reserved10:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_ATOM_EBL_CR_POWERON_REGISTER;
+
+
+/**
+  Unique. Last Branch Record n From IP (R/W) One of eight pairs of last branch
+  record registers on the last branch record stack. The From_IP part of the
+  stack contains pointers to the source instruction . See also: -  Last Branch
+  Record Stack TOS at 1C9H -  Section 17.5.
+
+  @param  ECX  MSR_ATOM_LASTBRANCH_n_FROM_IP
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP);
+  AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP, Msr);
+  @endcode
+  @note MSR_ATOM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.
+        MSR_ATOM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.
+        MSR_ATOM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.
+        MSR_ATOM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.
+        MSR_ATOM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.
+        MSR_ATOM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.
+        MSR_ATOM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.
+        MSR_ATOM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.
+  @{
+**/
+#define MSR_ATOM_LASTBRANCH_0_FROM_IP            0x00000040
+#define MSR_ATOM_LASTBRANCH_1_FROM_IP            0x00000041
+#define MSR_ATOM_LASTBRANCH_2_FROM_IP            0x00000042
+#define MSR_ATOM_LASTBRANCH_3_FROM_IP            0x00000043
+#define MSR_ATOM_LASTBRANCH_4_FROM_IP            0x00000044
+#define MSR_ATOM_LASTBRANCH_5_FROM_IP            0x00000045
+#define MSR_ATOM_LASTBRANCH_6_FROM_IP            0x00000046
+#define MSR_ATOM_LASTBRANCH_7_FROM_IP            0x00000047
+/// @}
+
+
+/**
+  Unique. Last Branch Record n To IP (R/W) One of eight pairs of last branch
+  record registers on the last branch record stack. The To_IP part of the
+  stack contains pointers to the destination instruction.
+
+  @param  ECX  MSR_ATOM_LASTBRANCH_n_TO_IP
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP);
+  AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP, Msr);
+  @endcode
+  @note MSR_ATOM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.
+        MSR_ATOM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.
+        MSR_ATOM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.
+        MSR_ATOM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.
+        MSR_ATOM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.
+        MSR_ATOM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.
+        MSR_ATOM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.
+        MSR_ATOM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.
+  @{
+**/
+#define MSR_ATOM_LASTBRANCH_0_TO_IP              0x00000060
+#define MSR_ATOM_LASTBRANCH_1_TO_IP              0x00000061
+#define MSR_ATOM_LASTBRANCH_2_TO_IP              0x00000062
+#define MSR_ATOM_LASTBRANCH_3_TO_IP              0x00000063
+#define MSR_ATOM_LASTBRANCH_4_TO_IP              0x00000064
+#define MSR_ATOM_LASTBRANCH_5_TO_IP              0x00000065
+#define MSR_ATOM_LASTBRANCH_6_TO_IP              0x00000066
+#define MSR_ATOM_LASTBRANCH_7_TO_IP              0x00000067
+/// @}
+
+
+/**
+  Shared. Scalable Bus Speed(RO) This field indicates the intended scalable
+  bus clock speed for processors based on Intel Atom microarchitecture:.
+
+  @param  ECX  MSR_ATOM_FSB_FREQ (0x000000CD)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_ATOM_FSB_FREQ_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_ATOM_FSB_FREQ_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_ATOM_FSB_FREQ_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_FSB_FREQ);
+  @endcode
+  @note MSR_ATOM_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.
+**/
+#define MSR_ATOM_FSB_FREQ                        0x000000CD
+
+/**
+  MSR information returned for MSR index #MSR_ATOM_FSB_FREQ
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 2:0] - Scalable Bus Speed
+    ///
+    /// Atom Processor Family
+    /// ---------------------
+    ///   111B: 083 MHz (FSB 333)
+    ///   101B: 100 MHz (FSB 400)
+    ///   001B: 133 MHz (FSB 533)
+    ///   011B: 167 MHz (FSB 667)
+    ///
+    /// 133.33 MHz should be utilized if performing calculation with
+    /// System Bus Speed when encoding is 001B.
+    /// 166.67 MHz should be utilized if performing calculation with
+    /// System Bus Speed when
+    /// encoding is 011B.
+    ///
+    UINT32  ScalableBusSpeed:3;
+    UINT32  Reserved1:29;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_ATOM_FSB_FREQ_REGISTER;
+
+
+/**
+  Shared.
+
+  @param  ECX  MSR_ATOM_BBL_CR_CTL3 (0x0000011E)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_ATOM_BBL_CR_CTL3_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_ATOM_BBL_CR_CTL3_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_ATOM_BBL_CR_CTL3_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_BBL_CR_CTL3);
+  AsmWriteMsr64 (MSR_ATOM_BBL_CR_CTL3, Msr.Uint64);
+  @endcode
+  @note MSR_ATOM_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
+**/
+#define MSR_ATOM_BBL_CR_CTL3                     0x0000011E
+
+/**
+  MSR information returned for MSR index #MSR_ATOM_BBL_CR_CTL3
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
+    /// Indicates if the L2 is hardware-disabled.
+    ///
+    UINT32  L2HardwareEnabled:1;
+    UINT32  Reserved1:7;
+    ///
+    /// [Bit 8] L2 Enabled. (R/W)  1 = L2 cache has been initialized 0 =
+    /// Disabled (default) Until this bit is set the processor will not
+    /// respond to the WBINVD instruction or the assertion of the FLUSH# input.
+    ///
+    UINT32  L2Enabled:1;
+    UINT32  Reserved2:14;
+    ///
+    /// [Bit 23] L2 Not Present (RO)  1. = L2 Present 2. = L2 Not Present.
+    ///
+    UINT32  L2NotPresent:1;
+    UINT32  Reserved3:8;
+    UINT32  Reserved4:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_ATOM_BBL_CR_CTL3_REGISTER;
+
+
+/**
+  Shared.
+
+  @param  ECX  MSR_ATOM_PERF_STATUS (0x00000198)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_ATOM_PERF_STATUS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_ATOM_PERF_STATUS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_ATOM_PERF_STATUS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PERF_STATUS);
+  AsmWriteMsr64 (MSR_ATOM_PERF_STATUS, Msr.Uint64);
+  @endcode
+  @note MSR_ATOM_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.
+**/
+#define MSR_ATOM_PERF_STATUS                     0x00000198
+
+/**
+  MSR information returned for MSR index #MSR_ATOM_PERF_STATUS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 15:0] Current Performance State Value.
+    ///
+    UINT32  CurrentPerformanceStateValue:16;
+    UINT32  Reserved1:16;
+    UINT32  Reserved2:8;
+    ///
+    /// [Bits 44:40] Maximum Bus Ratio (R/O) Indicates maximum bus ratio
+    /// configured for the processor.
+    ///
+    UINT32  MaximumBusRatio:5;
+    UINT32  Reserved3:19;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_ATOM_PERF_STATUS_REGISTER;
+
+
+/**
+  Shared.
+
+  @param  ECX  MSR_ATOM_THERM2_CTL (0x0000019D)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_ATOM_THERM2_CTL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_ATOM_THERM2_CTL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_ATOM_THERM2_CTL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_THERM2_CTL);
+  AsmWriteMsr64 (MSR_ATOM_THERM2_CTL, Msr.Uint64);
+  @endcode
+  @note MSR_ATOM_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
+**/
+#define MSR_ATOM_THERM2_CTL                      0x0000019D
+
+/**
+  MSR information returned for MSR index #MSR_ATOM_THERM2_CTL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:16;
+    ///
+    /// [Bit 16] TM_SELECT (R/W)  Mode of automatic thermal monitor: 1. =
+    /// Thermal Monitor 1 (thermally-initiated on-die modulation of the
+    /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated
+    /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is
+    /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 are enabled.
+    ///
+    UINT32  TM_SELECT:1;
+    UINT32  Reserved2:15;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_ATOM_THERM2_CTL_REGISTER;
+
+
+/**
+  Unique. Enable Misc. Processor Features (R/W)  Allows a variety of processor
+  functions to be enabled and disabled.
+
+  @param  ECX  MSR_ATOM_IA32_MISC_ENABLE (0x000001A0)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_ATOM_IA32_MISC_ENABLE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_ATOM_IA32_MISC_ENABLE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_ATOM_IA32_MISC_ENABLE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_IA32_MISC_ENABLE);
+  AsmWriteMsr64 (MSR_ATOM_IA32_MISC_ENABLE, Msr.Uint64);
+  @endcode
+  @note MSR_ATOM_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
+**/
+#define MSR_ATOM_IA32_MISC_ENABLE                0x000001A0
+
+/**
+  MSR information returned for MSR index #MSR_ATOM_IA32_MISC_ENABLE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Fast-Strings Enable See Table 2-2.
+    ///
+    UINT32  FastStrings:1;
+    UINT32  Reserved1:2;
+    ///
+    /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See
+    /// Table 2-2. Default value is 0.
+    ///
+    UINT32  AutomaticThermalControlCircuit:1;
+    UINT32  Reserved2:3;
+    ///
+    /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2.
+    ///
+    UINT32  PerformanceMonitoring:1;
+    UINT32  Reserved3:1;
+    UINT32  Reserved4:1;
+    ///
+    /// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by
+    /// the processor to indicate a pending break event within the processor 0
+    /// = Indicates compatible FERR# signaling behavior This bit must be set
+    /// to 1 to support XAPIC interrupt model usage.
+    ///
+    UINT32  FERR:1;
+    ///
+    /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2.
+    ///
+    UINT32  BTS:1;
+    ///
+    /// [Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See
+    /// Table 2-2.
+    ///
+    UINT32  PEBS:1;
+    ///
+    /// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the
+    /// thermal sensor indicates that the die temperature is at the
+    /// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.
+    /// TM2 will reduce the bus to core ratio and voltage according to the
+    /// value last written to MSR_THERM2_CTL bits 15:0.
+    ///   When this bit is clear (0, default), the processor does not change
+    ///   the VID signals or the bus to core ratio when the processor enters a
+    ///   thermally managed state. The BIOS must enable this feature if the
+    ///   TM2 feature flag (CPUID.1:ECX[8]) is set; if the TM2 feature flag is
+    ///   not set, this feature is not supported and BIOS must not alter the
+    ///   contents of the TM2 bit location. The processor is operating out of
+    ///   specification if both this bit and the TM1 bit are set to 0.
+    ///
+    UINT32  TM2:1;
+    UINT32  Reserved5:2;
+    ///
+    /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See
+    /// Table 2-2.
+    ///
+    UINT32  EIST:1;
+    UINT32  Reserved6:1;
+    ///
+    /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2.
+    ///
+    UINT32  MONITOR:1;
+    UINT32  Reserved7:1;
+    ///
+    /// [Bit 20] Shared. Enhanced Intel SpeedStep Technology Select Lock
+    /// (R/WO) When set, this bit causes the following bits to become
+    /// read-only: -  Enhanced Intel SpeedStep Technology Select Lock (this
+    /// bit), -  Enhanced Intel SpeedStep Technology Enable bit. The bit must
+    /// be set before an Enhanced Intel SpeedStep Technology transition is
+    /// requested. This bit is cleared on reset.
+    ///
+    UINT32  EISTLock:1;
+    UINT32  Reserved8:1;
+    ///
+    /// [Bit 22] Unique. Limit CPUID Maxval (R/W) See Table 2-2.
+    ///
+    UINT32  LimitCpuidMaxval:1;
+    ///
+    /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2.
+    ///
+    UINT32  xTPR_Message_Disable:1;
+    UINT32  Reserved9:8;
+    UINT32  Reserved10:2;
+    ///
+    /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2.
+    ///
+    UINT32  XD:1;
+    UINT32  Reserved11:29;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_ATOM_IA32_MISC_ENABLE_REGISTER;
+
+
+/**
+  Unique. Last Branch Record Stack TOS (R/W)  Contains an index (bits 0-2)
+  that points to the MSR containing the most recent branch record. See
+  MSR_LASTBRANCH_0_FROM_IP (at 40H).
+
+  @param  ECX  MSR_ATOM_LASTBRANCH_TOS (0x000001C9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_TOS);
+  AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_TOS, Msr);
+  @endcode
+  @note MSR_ATOM_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
+**/
+#define MSR_ATOM_LASTBRANCH_TOS                  0x000001C9
+
+
+/**
+  Unique. Last Exception Record From Linear IP (R)  Contains a pointer to the
+  last branch instruction that the processor executed prior to the last
+  exception that was generated or the last interrupt that was handled.
+
+  @param  ECX  MSR_ATOM_LER_FROM_LIP (0x000001DD)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_ATOM_LER_FROM_LIP);
+  @endcode
+  @note MSR_ATOM_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
+**/
+#define MSR_ATOM_LER_FROM_LIP                    0x000001DD
+
+
+/**
+  Unique. Last Exception Record To Linear IP (R)  This area contains a pointer
+  to the target of the last branch instruction that the processor executed
+  prior to the last exception that was generated or the last interrupt that
+  was handled.
+
+  @param  ECX  MSR_ATOM_LER_TO_LIP (0x000001DE)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_ATOM_LER_TO_LIP);
+  @endcode
+  @note MSR_ATOM_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
+**/
+#define MSR_ATOM_LER_TO_LIP                      0x000001DE
+
+
+/**
+  Unique. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling
+  (PEBS).".
+
+  @param  ECX  MSR_ATOM_PEBS_ENABLE (0x000003F1)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_ATOM_PEBS_ENABLE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_ATOM_PEBS_ENABLE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_ATOM_PEBS_ENABLE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PEBS_ENABLE);
+  AsmWriteMsr64 (MSR_ATOM_PEBS_ENABLE, Msr.Uint64);
+  @endcode
+  @note MSR_ATOM_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
+**/
+#define MSR_ATOM_PEBS_ENABLE                     0x000003F1
+
+/**
+  MSR information returned for MSR index #MSR_ATOM_PEBS_ENABLE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
+    ///
+    UINT32  Enable:1;
+    UINT32  Reserved1:31;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_ATOM_PEBS_ENABLE_REGISTER;
+
+
+/**
+  Package. Package C2 Residency Note: C-state values are processor specific
+  C-state code names, unrelated to MWAIT extension C-state parameters or ACPI
+  C-States. Package. Package C2 Residency Counter. (R/O) Time that this
+  package is in processor-specific C2 states since last reset. Counts at 1 Mhz
+  frequency.
+
+  @param  ECX  MSR_ATOM_PKG_C2_RESIDENCY (0x000003F8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_ATOM_PKG_C2_RESIDENCY);
+  AsmWriteMsr64 (MSR_ATOM_PKG_C2_RESIDENCY, Msr);
+  @endcode
+  @note MSR_ATOM_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.
+**/
+#define MSR_ATOM_PKG_C2_RESIDENCY                0x000003F8
+
+
+/**
+  Package. Package C4 Residency Note: C-state values are processor specific
+  C-state code names, unrelated to MWAIT extension C-state parameters or ACPI
+  C-States. Package. Package C4 Residency Counter. (R/O) Time that this
+  package is in processor-specific C4 states since last reset. Counts at 1 Mhz
+  frequency.
+
+  @param  ECX  MSR_ATOM_PKG_C4_RESIDENCY (0x000003F9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_ATOM_PKG_C4_RESIDENCY);
+  AsmWriteMsr64 (MSR_ATOM_PKG_C4_RESIDENCY, Msr);
+  @endcode
+  @note MSR_ATOM_PKG_C4_RESIDENCY is defined as MSR_PKG_C4_RESIDENCY in SDM.
+**/
+#define MSR_ATOM_PKG_C4_RESIDENCY                0x000003F9
+
+
+/**
+  Package. Package C6 Residency Note: C-state values are processor specific
+  C-state code names, unrelated to MWAIT extension C-state parameters or ACPI
+  C-States. Package. Package C6 Residency Counter. (R/O) Time that this
+  package is in processor-specific C6 states since last reset. Counts at 1 Mhz
+  frequency.
+
+  @param  ECX  MSR_ATOM_PKG_C6_RESIDENCY (0x000003FA)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_ATOM_PKG_C6_RESIDENCY);
+  AsmWriteMsr64 (MSR_ATOM_PKG_C6_RESIDENCY, Msr);
+  @endcode
+  @note MSR_ATOM_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
+**/
+#define MSR_ATOM_PKG_C6_RESIDENCY                0x000003FA
+
+#endif
diff --git a/MdePkg/Include/Register/Intel/Msr/BroadwellMsr.h b/MdePkg/Include/Register/Intel/Msr/BroadwellMsr.h
new file mode 100644
index 000000000000..f4de39c4df08
--- /dev/null
+++ b/MdePkg/Include/Register/Intel/Msr/BroadwellMsr.h
@@ -0,0 +1,354 @@
+/** @file
+  MSR Definitions for Intel processors based on the Broadwell microarchitecture.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+  May 2018, Volume 4: Model-Specific-Registers (MSR)
+
+**/
+
+#ifndef __BROADWELL_MSR_H__
+#define __BROADWELL_MSR_H__
+
+#include <Register/Intel/ArchitecturalMsr.h>
+
+/**
+  Is Intel processors based on the Broadwell microarchitecture?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_BROADWELL_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (                        \
+    DisplayModel == 0x3D || \
+    DisplayModel == 0x47 || \
+    DisplayModel == 0x4F || \
+    DisplayModel == 0x56    \
+    )                       \
+   )
+
+/**
+  Thread. See Table 2-2. See Section 18.6.2.2, "Global Counter Control
+  Facilities.".
+
+  @param  ECX  MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS (0x0000038E)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS);
+  AsmWriteMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);
+  @endcode
+  @note MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.
+**/
+#define MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS    0x0000038E
+
+/**
+  MSR information returned for MSR index #MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Ovf_PMC0.
+    ///
+    UINT32  Ovf_PMC0:1;
+    ///
+    /// [Bit 1] Ovf_PMC1.
+    ///
+    UINT32  Ovf_PMC1:1;
+    ///
+    /// [Bit 2] Ovf_PMC2.
+    ///
+    UINT32  Ovf_PMC2:1;
+    ///
+    /// [Bit 3] Ovf_PMC3.
+    ///
+    UINT32  Ovf_PMC3:1;
+    UINT32  Reserved1:28;
+    ///
+    /// [Bit 32] Ovf_FixedCtr0.
+    ///
+    UINT32  Ovf_FixedCtr0:1;
+    ///
+    /// [Bit 33] Ovf_FixedCtr1.
+    ///
+    UINT32  Ovf_FixedCtr1:1;
+    ///
+    /// [Bit 34] Ovf_FixedCtr2.
+    ///
+    UINT32  Ovf_FixedCtr2:1;
+    UINT32  Reserved2:20;
+    ///
+    /// [Bit 55] Trace_ToPA_PMI. See Section 36.2.6.2, "Table of Physical
+    /// Addresses (ToPA).".
+    ///
+    UINT32  Trace_ToPA_PMI:1;
+    UINT32  Reserved3:5;
+    ///
+    /// [Bit 61] Ovf_Uncore.
+    ///
+    UINT32  Ovf_Uncore:1;
+    ///
+    /// [Bit 62] Ovf_BufDSSAVE.
+    ///
+    UINT32  OvfBuf:1;
+    ///
+    /// [Bit 63] CondChgd.
+    ///
+    UINT32  CondChgd:1;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER;
+
+
+/**
+  Core. C-State Configuration Control (R/W) Note: C-state values are processor
+  specific C-state code names, unrelated to MWAIT extension C-state parameters
+  or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.
+
+  @param  ECX  MSR_BROADWELL_PKG_CST_CONFIG_CONTROL (0x000000E2)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL);
+  AsmWriteMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
+  @endcode
+  @note MSR_BROADWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
+**/
+#define MSR_BROADWELL_PKG_CST_CONFIG_CONTROL     0x000000E2
+
+/**
+  MSR information returned for MSR index #MSR_BROADWELL_PKG_CST_CONFIG_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest
+    /// processor-specific C-state code name (consuming the least power) for
+    /// the package. The default is set as factory-configured package C-state
+    /// limit. The following C-state code name encodings are supported: 0000b:
+    /// C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6
+    /// 0100b: C7 0101b: C7s 0110b: C8 0111b: C9 1000b: C10.
+    ///
+    UINT32  Limit:4;
+    UINT32  Reserved1:6;
+    ///
+    /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
+    ///
+    UINT32  IO_MWAIT:1;
+    UINT32  Reserved2:4;
+    ///
+    /// [Bit 15] CFG Lock (R/WO).
+    ///
+    UINT32  CFGLock:1;
+    UINT32  Reserved3:9;
+    ///
+    /// [Bit 25] C3 State Auto Demotion Enable (R/W).
+    ///
+    UINT32  C3AutoDemotion:1;
+    ///
+    /// [Bit 26] C1 State Auto Demotion Enable (R/W).
+    ///
+    UINT32  C1AutoDemotion:1;
+    ///
+    /// [Bit 27] Enable C3 Undemotion (R/W).
+    ///
+    UINT32  C3Undemotion:1;
+    ///
+    /// [Bit 28] Enable C1 Undemotion (R/W).
+    ///
+    UINT32  C1Undemotion:1;
+    ///
+    /// [Bit 29] Enable Package C-State Auto-demotion (R/W).
+    ///
+    UINT32  CStateAutoDemotion:1;
+    ///
+    /// [Bit 30] Enable Package C-State Undemotion (R/W).
+    ///
+    UINT32  CStateUndemotion:1;
+    UINT32  Reserved4:1;
+    UINT32  Reserved5:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER;
+
+
+/**
+  Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
+  RW if MSR_PLATFORM_INFO.[28] = 1.
+
+  @param  ECX  MSR_BROADWELL_TURBO_RATIO_LIMIT (0x000001AD)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_TURBO_RATIO_LIMIT);
+  @endcode
+  @note MSR_BROADWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
+**/
+#define MSR_BROADWELL_TURBO_RATIO_LIMIT          0x000001AD
+
+/**
+  MSR information returned for MSR index #MSR_BROADWELL_TURBO_RATIO_LIMIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
+    /// limit of 1 core active.
+    ///
+    UINT32  Maximum1C:8;
+    ///
+    /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
+    /// limit of 2 core active.
+    ///
+    UINT32  Maximum2C:8;
+    ///
+    /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
+    /// limit of 3 core active.
+    ///
+    UINT32  Maximum3C:8;
+    ///
+    /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
+    /// limit of 4 core active.
+    ///
+    UINT32  Maximum4C:8;
+    ///
+    /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
+    /// limit of 5core active.
+    ///
+    UINT32  Maximum5C:8;
+    ///
+    /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
+    /// limit of 6core active.
+    ///
+    UINT32  Maximum6C:8;
+    UINT32  Reserved:16;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER;
+
+
+/**
+  Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio
+  fields represent the widest possible range of uncore frequencies. Writing to
+  these fields allows software to control the minimum and the maximum
+  frequency that hardware will select.
+
+  @param  ECX  MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT (0x00000620)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT);
+  AsmWriteMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);
+  @endcode
+**/
+#define MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT      0x00000620
+
+/**
+  MSR information returned for MSR index #MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the
+    /// LLC/Ring.
+    ///
+    UINT32  MAX_RATIO:7;
+    UINT32  Reserved2:1;
+    ///
+    /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum
+    /// possible ratio of the LLC/Ring.
+    ///
+    UINT32  MIN_RATIO:7;
+    UINT32  Reserved3:17;
+    UINT32  Reserved4:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER;
+
+/**
+  Package. PP0 Energy Status (R/O)  See Section 14.9.4, "PP0/PP1 RAPL
+  Domains.".
+
+  @param  ECX  MSR_BROADWELL_PP0_ENERGY_STATUS (0x00000639)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_BROADWELL_PP0_ENERGY_STATUS);
+  @endcode
+  @note MSR_BROADWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
+**/
+#define MSR_BROADWELL_PP0_ENERGY_STATUS          0x00000639
+
+#endif
diff --git a/MdePkg/Include/Register/Intel/Msr/Core2Msr.h b/MdePkg/Include/Register/Intel/Msr/Core2Msr.h
new file mode 100644
index 000000000000..617daaaff848
--- /dev/null
+++ b/MdePkg/Include/Register/Intel/Msr/Core2Msr.h
@@ -0,0 +1,1068 @@
+/** @file
+   MSR Definitions for the Intel(R) Core(TM) 2 Processor Family.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+  May 2018, Volume 4: Model-Specific-Registers (MSR)
+
+**/
+
+#ifndef __CORE2_MSR_H__
+#define __CORE2_MSR_H__
+
+#include <Register/Intel/ArchitecturalMsr.h>
+
+/**
+  Is Intel(R) Core(TM) 2 Processor Family?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_CORE2_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (                        \
+    DisplayModel == 0x0F || \
+    DisplayModel == 0x17    \
+    )                       \
+   )
+
+/**
+  Shared. Model Specific Platform ID (R).
+
+  @param  ECX  MSR_CORE2_PLATFORM_ID (0x00000017)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_CORE2_PLATFORM_ID_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_CORE2_PLATFORM_ID_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_CORE2_PLATFORM_ID_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PLATFORM_ID);
+  @endcode
+  @note MSR_CORE2_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.
+**/
+#define MSR_CORE2_PLATFORM_ID                    0x00000017
+
+/**
+  MSR information returned for MSR index #MSR_CORE2_PLATFORM_ID
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:8;
+    ///
+    /// [Bits 12:8] Maximum Qualified Ratio (R)  The maximum allowed bus ratio.
+    ///
+    UINT32  MaximumQualifiedRatio:5;
+    UINT32  Reserved2:19;
+    UINT32  Reserved3:18;
+    ///
+    /// [Bits 52:50] See Table 2-2.
+    ///
+    UINT32  PlatformId:3;
+    UINT32  Reserved4:11;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_CORE2_PLATFORM_ID_REGISTER;
+
+
+/**
+  Shared. Processor Hard Power-On Configuration (R/W) Enables and disables
+  processor features; (R) indicates current processor configuration.
+
+  @param  ECX  MSR_CORE2_EBL_CR_POWERON (0x0000002A)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_CORE2_EBL_CR_POWERON_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_CORE2_EBL_CR_POWERON_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_CORE2_EBL_CR_POWERON_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_EBL_CR_POWERON);
+  AsmWriteMsr64 (MSR_CORE2_EBL_CR_POWERON, Msr.Uint64);
+  @endcode
+  @note MSR_CORE2_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
+**/
+#define MSR_CORE2_EBL_CR_POWERON                 0x0000002A
+
+/**
+  MSR information returned for MSR index #MSR_CORE2_EBL_CR_POWERON
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
+    /// Note: Not all processor implements R/W.
+    ///
+    UINT32  DataErrorCheckingEnable:1;
+    ///
+    /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
+    /// Note: Not all processor implements R/W.
+    ///
+    UINT32  ResponseErrorCheckingEnable:1;
+    ///
+    /// [Bit 3] MCERR# Drive Enable (R/W)  1 = Enabled; 0 = Disabled Note: Not
+    /// all processor implements R/W.
+    ///
+    UINT32  MCERR_DriveEnable:1;
+    ///
+    /// [Bit 4] Address Parity Enable (R/W) 1 = Enabled; 0 = Disabled Note:
+    /// Not all processor implements R/W.
+    ///
+    UINT32  AddressParityEnable:1;
+    UINT32  Reserved2:1;
+    UINT32  Reserved3:1;
+    ///
+    /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not
+    /// all processor implements R/W.
+    ///
+    UINT32  BINIT_DriverEnable:1;
+    ///
+    /// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.
+    ///
+    UINT32  OutputTriStateEnable:1;
+    ///
+    /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
+    ///
+    UINT32  ExecuteBIST:1;
+    ///
+    /// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.
+    ///
+    UINT32  MCERR_ObservationEnabled:1;
+    ///
+    /// [Bit 11] Intel TXT Capable Chipset. (R/O) 1 = Present; 0 = Not Present.
+    ///
+    UINT32  IntelTXTCapableChipset:1;
+    ///
+    /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.
+    ///
+    UINT32  BINIT_ObservationEnabled:1;
+    UINT32  Reserved4:1;
+    ///
+    /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.
+    ///
+    UINT32  ResetVector:1;
+    UINT32  Reserved5:1;
+    ///
+    /// [Bits 17:16] APIC Cluster ID (R/O).
+    ///
+    UINT32  APICClusterID:2;
+    ///
+    /// [Bit 18] N/2 Non-Integer Bus Ratio (R/O) 0 = Integer ratio; 1 =
+    /// Non-integer ratio.
+    ///
+    UINT32  NonIntegerBusRatio:1;
+    UINT32  Reserved6:1;
+    ///
+    /// [Bits 21:20] Symmetric Arbitration ID (R/O).
+    ///
+    UINT32  SymmetricArbitrationID:2;
+    ///
+    /// [Bits 26:22] Integer Bus Frequency Ratio (R/O).
+    ///
+    UINT32  IntegerBusFrequencyRatio:5;
+    UINT32  Reserved7:5;
+    UINT32  Reserved8:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_CORE2_EBL_CR_POWERON_REGISTER;
+
+
+/**
+  Unique. Control Features in Intel 64 Processor (R/W) See Table 2-2.
+
+  @param  ECX  MSR_CORE2_FEATURE_CONTROL (0x0000003A)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_CORE2_FEATURE_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_CORE2_FEATURE_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_CORE2_FEATURE_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_FEATURE_CONTROL);
+  AsmWriteMsr64 (MSR_CORE2_FEATURE_CONTROL, Msr.Uint64);
+  @endcode
+  @note MSR_CORE2_FEATURE_CONTROL is defined as MSR_FEATURE_CONTROL in SDM.
+**/
+#define MSR_CORE2_FEATURE_CONTROL                0x0000003A
+
+/**
+  MSR information returned for MSR index #MSR_CORE2_FEATURE_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:3;
+    ///
+    /// [Bit 3] Unique. SMRR Enable (R/WL) When this bit is set and the lock
+    /// bit is set makes the SMRR_PHYS_BASE and SMRR_PHYS_MASK registers read
+    /// visible and writeable while in SMM.
+    ///
+    UINT32  SMRREnable:1;
+    UINT32  Reserved2:28;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_CORE2_FEATURE_CONTROL_REGISTER;
+
+
+/**
+  Unique. Last Branch Record n From IP (R/W) One of four pairs of last branch
+  record registers on the last branch record stack. The From_IP part of the
+  stack contains pointers to the source instruction. See also: -  Last Branch
+  Record Stack TOS at 1C9H -  Section 17.5.
+
+  @param  ECX  MSR_CORE2_LASTBRANCH_n_FROM_IP
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_0_FROM_IP);
+  AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_0_FROM_IP, Msr);
+  @endcode
+  @note MSR_CORE2_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.
+        MSR_CORE2_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.
+        MSR_CORE2_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.
+        MSR_CORE2_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.
+  @{
+**/
+#define MSR_CORE2_LASTBRANCH_0_FROM_IP           0x00000040
+#define MSR_CORE2_LASTBRANCH_1_FROM_IP           0x00000041
+#define MSR_CORE2_LASTBRANCH_2_FROM_IP           0x00000042
+#define MSR_CORE2_LASTBRANCH_3_FROM_IP           0x00000043
+/// @}
+
+
+/**
+  Unique. Last Branch Record n To IP (R/W) One of four pairs of last branch
+  record registers on the last branch record stack. This To_IP part of the
+  stack contains pointers to the destination instruction.
+
+  @param  ECX  MSR_CORE2_LASTBRANCH_n_TO_IP
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_0_TO_IP);
+  AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_0_TO_IP, Msr);
+  @endcode
+  @note MSR_CORE2_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.
+        MSR_CORE2_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.
+        MSR_CORE2_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.
+        MSR_CORE2_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.
+  @{
+**/
+#define MSR_CORE2_LASTBRANCH_0_TO_IP             0x00000060
+#define MSR_CORE2_LASTBRANCH_1_TO_IP             0x00000061
+#define MSR_CORE2_LASTBRANCH_2_TO_IP             0x00000062
+#define MSR_CORE2_LASTBRANCH_3_TO_IP             0x00000063
+/// @}
+
+
+/**
+  Unique. System Management Mode Base Address register (WO in SMM)
+  Model-specific implementation of SMRR-like interface, read visible and write
+  only in SMM.
+
+  @param  ECX  MSR_CORE2_SMRR_PHYSBASE (0x000000A0)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_CORE2_SMRR_PHYSBASE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_CORE2_SMRR_PHYSBASE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_CORE2_SMRR_PHYSBASE_REGISTER  Msr;
+
+  Msr.Uint64 = 0;
+  AsmWriteMsr64 (MSR_CORE2_SMRR_PHYSBASE, Msr.Uint64);
+  @endcode
+  @note MSR_CORE2_SMRR_PHYSBASE is defined as MSR_SMRR_PHYSBASE in SDM.
+**/
+#define MSR_CORE2_SMRR_PHYSBASE                  0x000000A0
+
+/**
+  MSR information returned for MSR index #MSR_CORE2_SMRR_PHYSBASE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:12;
+    ///
+    /// [Bits 31:12] PhysBase. SMRR physical Base Address.
+    ///
+    UINT32  PhysBase:20;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_CORE2_SMRR_PHYSBASE_REGISTER;
+
+
+/**
+  Unique. System Management Mode Physical Address Mask register (WO in SMM)
+  Model-specific implementation of SMRR-like interface, read visible and write
+  only in SMM.
+
+  @param  ECX  MSR_CORE2_SMRR_PHYSMASK (0x000000A1)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_CORE2_SMRR_PHYSMASK_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_CORE2_SMRR_PHYSMASK_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_CORE2_SMRR_PHYSMASK_REGISTER  Msr;
+
+  Msr.Uint64 = 0;
+  AsmWriteMsr64 (MSR_CORE2_SMRR_PHYSMASK, Msr.Uint64);
+  @endcode
+  @note MSR_CORE2_SMRR_PHYSMASK is defined as MSR_SMRR_PHYSMASK in SDM.
+**/
+#define MSR_CORE2_SMRR_PHYSMASK                  0x000000A1
+
+/**
+  MSR information returned for MSR index #MSR_CORE2_SMRR_PHYSMASK
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:11;
+    ///
+    /// [Bit 11] Valid. Physical address base and range mask are valid.
+    ///
+    UINT32  Valid:1;
+    ///
+    /// [Bits 31:12] PhysMask. SMRR physical address range mask.
+    ///
+    UINT32  PhysMask:20;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_CORE2_SMRR_PHYSMASK_REGISTER;
+
+
+/**
+  Shared. Scalable Bus Speed(RO) This field indicates the intended scalable
+  bus clock speed for processors based on Intel Core microarchitecture:.
+
+  @param  ECX  MSR_CORE2_FSB_FREQ (0x000000CD)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_CORE2_FSB_FREQ_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_CORE2_FSB_FREQ_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_CORE2_FSB_FREQ_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_FSB_FREQ);
+  @endcode
+  @note MSR_CORE2_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.
+**/
+#define MSR_CORE2_FSB_FREQ                       0x000000CD
+
+/**
+  MSR information returned for MSR index #MSR_CORE2_FSB_FREQ
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 2:0] - Scalable Bus Speed
+    ///   101B: 100 MHz (FSB 400)
+    ///   001B: 133 MHz (FSB 533)
+    ///   011B: 167 MHz (FSB 667)
+    ///   010B: 200 MHz (FSB 800)
+    ///   000B: 267 MHz (FSB 1067)
+    ///   100B: 333 MHz (FSB 1333)
+    ///
+    ///   133.33 MHz should be utilized if performing calculation with System
+    ///   Bus Speed when encoding is 001B. 166.67 MHz should be utilized if
+    ///   performing calculation with System Bus Speed when encoding is 011B.
+    ///   266.67 MHz should be utilized if performing calculation with System
+    ///   Bus Speed when encoding is 000B. 333.33 MHz should be utilized if
+    ///   performing calculation with System Bus Speed when encoding is 100B.
+    ///
+    UINT32  ScalableBusSpeed:3;
+    UINT32  Reserved1:29;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_CORE2_FSB_FREQ_REGISTER;
+
+/**
+  Shared.
+
+  @param  ECX  MSR_CORE2_PERF_STATUS (0x00000198)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_CORE2_PERF_STATUS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_CORE2_PERF_STATUS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_CORE2_PERF_STATUS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PERF_STATUS);
+  AsmWriteMsr64 (MSR_CORE2_PERF_STATUS, Msr.Uint64);
+  @endcode
+  @note MSR_CORE2_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.
+**/
+#define MSR_CORE2_PERF_STATUS                    0x00000198
+
+/**
+  MSR information returned for MSR index #MSR_CORE2_PERF_STATUS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 15:0] Current Performance State Value.
+    ///
+    UINT32  CurrentPerformanceStateValue:16;
+    UINT32  Reserved1:15;
+    ///
+    /// [Bit 31] XE Operation (R/O). If set, XE operation is enabled. Default
+    /// is cleared.
+    ///
+    UINT32  XEOperation:1;
+    UINT32  Reserved2:8;
+    ///
+    /// [Bits 44:40] Maximum Bus Ratio (R/O) Indicates maximum bus ratio
+    /// configured for the processor.
+    ///
+    UINT32  MaximumBusRatio:5;
+    UINT32  Reserved3:1;
+    ///
+    /// [Bit 46] Non-Integer Bus Ratio (R/O) Indicates non-integer bus ratio
+    /// is enabled. Applies processors based on Enhanced Intel Core
+    /// microarchitecture.
+    ///
+    UINT32  NonIntegerBusRatio:1;
+    UINT32  Reserved4:17;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_CORE2_PERF_STATUS_REGISTER;
+
+
+/**
+  Unique.
+
+  @param  ECX  MSR_CORE2_THERM2_CTL (0x0000019D)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_CORE2_THERM2_CTL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_CORE2_THERM2_CTL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_CORE2_THERM2_CTL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_THERM2_CTL);
+  AsmWriteMsr64 (MSR_CORE2_THERM2_CTL, Msr.Uint64);
+  @endcode
+  @note MSR_CORE2_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
+**/
+#define MSR_CORE2_THERM2_CTL                     0x0000019D
+
+/**
+  MSR information returned for MSR index #MSR_CORE2_THERM2_CTL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:16;
+    ///
+    /// [Bit 16] TM_SELECT (R/W)  Mode of automatic thermal monitor: 1. =
+    /// Thermal Monitor 1 (thermally-initiated on-die modulation of the
+    /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated
+    /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is
+    /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 are enabled.
+    ///
+    UINT32  TM_SELECT:1;
+    UINT32  Reserved2:15;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_CORE2_THERM2_CTL_REGISTER;
+
+
+/**
+  Enable Misc. Processor Features (R/W)  Allows a variety of processor
+  functions to be enabled and disabled.
+
+  @param  ECX  MSR_CORE2_IA32_MISC_ENABLE (0x000001A0)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_CORE2_IA32_MISC_ENABLE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_CORE2_IA32_MISC_ENABLE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_CORE2_IA32_MISC_ENABLE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_IA32_MISC_ENABLE);
+  AsmWriteMsr64 (MSR_CORE2_IA32_MISC_ENABLE, Msr.Uint64);
+  @endcode
+  @note MSR_CORE2_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
+**/
+#define MSR_CORE2_IA32_MISC_ENABLE               0x000001A0
+
+/**
+  MSR information returned for MSR index #MSR_CORE2_IA32_MISC_ENABLE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Fast-Strings Enable See Table 2-2.
+    ///
+    UINT32  FastStrings:1;
+    UINT32  Reserved1:2;
+    ///
+    /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See
+    /// Table 2-2.
+    ///
+    UINT32  AutomaticThermalControlCircuit:1;
+    UINT32  Reserved2:3;
+    ///
+    /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2.
+    ///
+    UINT32  PerformanceMonitoring:1;
+    UINT32  Reserved3:1;
+    ///
+    /// [Bit 9] Hardware Prefetcher Disable (R/W) When set, disables the
+    /// hardware prefetcher operation on streams of data. When clear
+    /// (default), enables the prefetch queue. Disabling of the hardware
+    /// prefetcher may impact processor performance.
+    ///
+    UINT32  HardwarePrefetcherDisable:1;
+    ///
+    /// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by
+    /// the processor to indicate a pending break event within the processor 0
+    /// = Indicates compatible FERR# signaling behavior This bit must be set
+    /// to 1 to support XAPIC interrupt model usage.
+    ///
+    UINT32  FERR:1;
+    ///
+    /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2.
+    ///
+    UINT32  BTS:1;
+    ///
+    /// [Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See
+    /// Table 2-2.
+    ///
+    UINT32  PEBS:1;
+    ///
+    /// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the
+    /// thermal sensor indicates that the die temperature is at the
+    /// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.
+    /// TM2 will reduce the bus to core ratio and voltage according to the
+    /// value last written to MSR_THERM2_CTL bits 15:0.
+    ///   When this bit is clear (0, default), the processor does not change
+    ///   the VID signals or the bus to core ratio when the processor enters a
+    ///   thermally managed state. The BIOS must enable this feature if the
+    ///   TM2 feature flag (CPUID.1:ECX[8]) is set; if the TM2 feature flag is
+    ///   not set, this feature is not supported and BIOS must not alter the
+    ///   contents of the TM2 bit location. The processor is operating out of
+    ///   specification if both this bit and the TM1 bit are set to 0.
+    ///
+    UINT32  TM2:1;
+    UINT32  Reserved4:2;
+    ///
+    /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See
+    /// Table 2-2.
+    ///
+    UINT32  EIST:1;
+    UINT32  Reserved5:1;
+    ///
+    /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2.
+    ///
+    UINT32  MONITOR:1;
+    ///
+    /// [Bit 19] Shared. Adjacent Cache Line Prefetch Disable (R/W)  When set
+    /// to 1, the processor fetches the cache line that contains data
+    /// currently required by the processor. When set to 0, the processor
+    /// fetches cache lines that comprise a cache line pair (128 bytes).
+    /// Single processor platforms should not set this bit. Server platforms
+    /// should set or clear this bit based on platform performance observed in
+    /// validation and testing. BIOS may contain a setup option that controls
+    /// the setting of this bit.
+    ///
+    UINT32  AdjacentCacheLinePrefetchDisable:1;
+    ///
+    /// [Bit 20] Shared. Enhanced Intel SpeedStep Technology Select Lock
+    /// (R/WO) When set, this bit causes the following bits to become
+    /// read-only: -  Enhanced Intel SpeedStep Technology Select Lock (this
+    /// bit), -  Enhanced Intel SpeedStep Technology Enable bit. The bit must
+    /// be set before an Enhanced Intel SpeedStep Technology transition is
+    /// requested. This bit is cleared on reset.
+    ///
+    UINT32  EISTLock:1;
+    UINT32  Reserved6:1;
+    ///
+    /// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 2-2.
+    ///
+    UINT32  LimitCpuidMaxval:1;
+    ///
+    /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2.
+    ///
+    UINT32  xTPR_Message_Disable:1;
+    UINT32  Reserved7:8;
+    UINT32  Reserved8:2;
+    ///
+    /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2.
+    ///
+    UINT32  XD:1;
+    UINT32  Reserved9:2;
+    ///
+    /// [Bit 37] Unique. DCU Prefetcher Disable (R/W) When set to 1, The DCU
+    /// L1 data cache prefetcher is disabled. The default value after reset is
+    /// 0. BIOS may write '1' to disable this feature. The DCU prefetcher is
+    /// an L1 data cache prefetcher. When the DCU prefetcher detects multiple
+    /// loads from the same line done within a time limit, the DCU prefetcher
+    /// assumes the next line will be required. The next line is prefetched in
+    /// to the L1 data cache from memory or L2.
+    ///
+    UINT32  DCUPrefetcherDisable:1;
+    ///
+    /// [Bit 38] Shared. IDA Disable (R/W) When set to 1 on processors that
+    /// support IDA, the Intel Dynamic Acceleration feature (IDA) is disabled
+    /// and the IDA_Enable feature flag will be clear (CPUID.06H: EAX[1]=0).
+    /// When set to a 0 on processors that support IDA, CPUID.06H: EAX[1]
+    /// reports the processor's support of IDA is enabled. Note: the power-on
+    /// default value is used by BIOS to detect hardware support of IDA. If
+    /// power-on default value is 1, IDA is available in the processor. If
+    /// power-on default value is 0, IDA is not available.
+    ///
+    UINT32  IDADisable:1;
+    ///
+    /// [Bit 39] Unique. IP Prefetcher Disable (R/W) When set to 1, The IP
+    /// prefetcher is disabled. The default value after reset is 0. BIOS may
+    /// write '1' to disable this feature. The IP prefetcher is an L1 data
+    /// cache prefetcher. The IP prefetcher looks for sequential load history
+    /// to determine whether to prefetch the next expected data into the L1
+    /// cache from memory or L2.
+    ///
+    UINT32  IPPrefetcherDisable:1;
+    UINT32  Reserved10:24;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_CORE2_IA32_MISC_ENABLE_REGISTER;
+
+
+/**
+  Unique. Last Branch Record Stack TOS (R/W)  Contains an index (bits 0-3)
+  that points to the MSR containing the most recent branch record. See
+  MSR_LASTBRANCH_0_FROM_IP (at 40H).
+
+  @param  ECX  MSR_CORE2_LASTBRANCH_TOS (0x000001C9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_TOS);
+  AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_TOS, Msr);
+  @endcode
+  @note MSR_CORE2_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
+**/
+#define MSR_CORE2_LASTBRANCH_TOS                 0x000001C9
+
+
+/**
+  Unique. Last Exception Record From Linear IP (R)  Contains a pointer to the
+  last branch instruction that the processor executed prior to the last
+  exception that was generated or the last interrupt that was handled.
+
+  @param  ECX  MSR_CORE2_LER_FROM_LIP (0x000001DD)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE2_LER_FROM_LIP);
+  @endcode
+  @note MSR_CORE2_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
+**/
+#define MSR_CORE2_LER_FROM_LIP                   0x000001DD
+
+
+/**
+  Unique. Last Exception Record To Linear IP (R)  This area contains a pointer
+  to the target of the last branch instruction that the processor executed
+  prior to the last exception that was generated or the last interrupt that
+  was handled.
+
+  @param  ECX  MSR_CORE2_LER_TO_LIP (0x000001DE)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE2_LER_TO_LIP);
+  @endcode
+  @note MSR_CORE2_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
+**/
+#define MSR_CORE2_LER_TO_LIP                     0x000001DE
+
+
+/**
+  Unique. Fixed-Function Performance Counter Register n (R/W).
+
+  @param  ECX  MSR_CORE2_PERF_FIXED_CTRn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE2_PERF_FIXED_CTR0);
+  AsmWriteMsr64 (MSR_CORE2_PERF_FIXED_CTR0, Msr);
+  @endcode
+  @note MSR_CORE2_PERF_FIXED_CTR0 is defined as MSR_PERF_FIXED_CTR0 in SDM.
+        MSR_CORE2_PERF_FIXED_CTR1 is defined as MSR_PERF_FIXED_CTR1 in SDM.
+        MSR_CORE2_PERF_FIXED_CTR2 is defined as MSR_PERF_FIXED_CTR2 in SDM.
+  @{
+**/
+#define MSR_CORE2_PERF_FIXED_CTR0                0x00000309
+#define MSR_CORE2_PERF_FIXED_CTR1                0x0000030A
+#define MSR_CORE2_PERF_FIXED_CTR2                0x0000030B
+/// @}
+
+
+/**
+  Unique. RO. This applies to processors that do not support architectural
+  perfmon version 2.
+
+  @param  ECX  MSR_CORE2_PERF_CAPABILITIES (0x00000345)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_CORE2_PERF_CAPABILITIES_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_CORE2_PERF_CAPABILITIES_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_CORE2_PERF_CAPABILITIES_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PERF_CAPABILITIES);
+  AsmWriteMsr64 (MSR_CORE2_PERF_CAPABILITIES, Msr.Uint64);
+  @endcode
+  @note MSR_CORE2_PERF_CAPABILITIES is defined as MSR_PERF_CAPABILITIES in SDM.
+**/
+#define MSR_CORE2_PERF_CAPABILITIES              0x00000345
+
+/**
+  MSR information returned for MSR index #MSR_CORE2_PERF_CAPABILITIES
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 5:0] LBR Format. See Table 2-2.
+    ///
+    UINT32  LBR_FMT:6;
+    ///
+    /// [Bit 6] PEBS Record Format.
+    ///
+    UINT32  PEBS_FMT:1;
+    ///
+    /// [Bit 7] PEBSSaveArchRegs. See Table 2-2.
+    ///
+    UINT32  PEBS_ARCH_REG:1;
+    UINT32  Reserved1:24;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_CORE2_PERF_CAPABILITIES_REGISTER;
+
+
+/**
+  Unique. Fixed-Function-Counter Control Register (R/W).
+
+  @param  ECX  MSR_CORE2_PERF_FIXED_CTR_CTRL (0x0000038D)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE2_PERF_FIXED_CTR_CTRL);
+  AsmWriteMsr64 (MSR_CORE2_PERF_FIXED_CTR_CTRL, Msr);
+  @endcode
+  @note MSR_CORE2_PERF_FIXED_CTR_CTRL is defined as MSR_PERF_FIXED_CTR_CTRL in SDM.
+**/
+#define MSR_CORE2_PERF_FIXED_CTR_CTRL            0x0000038D
+
+
+/**
+  Unique. See Section 18.6.2.2, "Global Counter Control Facilities.".
+
+  @param  ECX  MSR_CORE2_PERF_GLOBAL_STATUS (0x0000038E)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_STATUS);
+  AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_STATUS, Msr);
+  @endcode
+  @note MSR_CORE2_PERF_GLOBAL_STATUS is defined as MSR_PERF_GLOBAL_STATUS in SDM.
+**/
+#define MSR_CORE2_PERF_GLOBAL_STATUS             0x0000038E
+
+
+/**
+  Unique. See Section 18.6.2.2, "Global Counter Control Facilities.".
+
+  @param  ECX  MSR_CORE2_PERF_GLOBAL_CTRL (0x0000038F)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_CTRL);
+  AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_CTRL, Msr);
+  @endcode
+  @note MSR_CORE2_PERF_GLOBAL_CTRL is defined as MSR_PERF_GLOBAL_CTRL in SDM.
+**/
+#define MSR_CORE2_PERF_GLOBAL_CTRL               0x0000038F
+
+
+/**
+  Unique. See Section 18.6.2.2, "Global Counter Control Facilities.".
+
+  @param  ECX  MSR_CORE2_PERF_GLOBAL_OVF_CTRL (0x00000390)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_OVF_CTRL);
+  AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_OVF_CTRL, Msr);
+  @endcode
+  @note MSR_CORE2_PERF_GLOBAL_OVF_CTRL is defined as MSR_PERF_GLOBAL_OVF_CTRL in SDM.
+**/
+#define MSR_CORE2_PERF_GLOBAL_OVF_CTRL           0x00000390
+
+
+/**
+  Unique. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling
+  (PEBS).".
+
+  @param  ECX  MSR_CORE2_PEBS_ENABLE (0x000003F1)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_CORE2_PEBS_ENABLE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_CORE2_PEBS_ENABLE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_CORE2_PEBS_ENABLE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PEBS_ENABLE);
+  AsmWriteMsr64 (MSR_CORE2_PEBS_ENABLE, Msr.Uint64);
+  @endcode
+  @note MSR_CORE2_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
+**/
+#define MSR_CORE2_PEBS_ENABLE                    0x000003F1
+
+/**
+  MSR information returned for MSR index #MSR_CORE2_PEBS_ENABLE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
+    ///
+    UINT32  Enable:1;
+    UINT32  Reserved1:31;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_CORE2_PEBS_ENABLE_REGISTER;
+
+
+/**
+  Unique. GBUSQ Event Control/Counter Register (R/W) Apply to Intel Xeon
+  processor 7400 series (processor signature 06_1D) only. See Section 17.2.2.
+
+  @param  ECX  MSR_CORE2_EMON_L3_CTR_CTLn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE2_EMON_L3_CTR_CTL0);
+  AsmWriteMsr64 (MSR_CORE2_EMON_L3_CTR_CTL0, Msr);
+  @endcode
+  @note MSR_CORE2_EMON_L3_CTR_CTL0 is defined as MSR_EMON_L3_CTR_CTL0 in SDM.
+        MSR_CORE2_EMON_L3_CTR_CTL1 is defined as MSR_EMON_L3_CTR_CTL1 in SDM.
+        MSR_CORE2_EMON_L3_CTR_CTL2 is defined as MSR_EMON_L3_CTR_CTL2 in SDM.
+        MSR_CORE2_EMON_L3_CTR_CTL3 is defined as MSR_EMON_L3_CTR_CTL3 in SDM.
+        MSR_CORE2_EMON_L3_CTR_CTL4 is defined as MSR_EMON_L3_CTR_CTL4 in SDM.
+        MSR_CORE2_EMON_L3_CTR_CTL5 is defined as MSR_EMON_L3_CTR_CTL5 in SDM.
+        MSR_CORE2_EMON_L3_CTR_CTL6 is defined as MSR_EMON_L3_CTR_CTL6 in SDM.
+        MSR_CORE2_EMON_L3_CTR_CTL7 is defined as MSR_EMON_L3_CTR_CTL7 in SDM.
+  @{
+**/
+#define MSR_CORE2_EMON_L3_CTR_CTL0               0x000107CC
+#define MSR_CORE2_EMON_L3_CTR_CTL1               0x000107CD
+#define MSR_CORE2_EMON_L3_CTR_CTL2               0x000107CE
+#define MSR_CORE2_EMON_L3_CTR_CTL3               0x000107CF
+#define MSR_CORE2_EMON_L3_CTR_CTL4               0x000107D0
+#define MSR_CORE2_EMON_L3_CTR_CTL5               0x000107D1
+#define MSR_CORE2_EMON_L3_CTR_CTL6               0x000107D2
+#define MSR_CORE2_EMON_L3_CTR_CTL7               0x000107D3
+/// @}
+
+
+/**
+  Unique. L3/FSB Common Control Register (R/W) Apply to Intel Xeon processor
+  7400 series (processor signature 06_1D) only. See Section 17.2.2.
+
+  @param  ECX  MSR_CORE2_EMON_L3_GL_CTL (0x000107D8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE2_EMON_L3_GL_CTL);
+  AsmWriteMsr64 (MSR_CORE2_EMON_L3_GL_CTL, Msr);
+  @endcode
+  @note MSR_CORE2_EMON_L3_GL_CTL is defined as MSR_EMON_L3_GL_CTL in SDM.
+**/
+#define MSR_CORE2_EMON_L3_GL_CTL                 0x000107D8
+
+#endif
diff --git a/MdePkg/Include/Register/Intel/Msr/CoreMsr.h b/MdePkg/Include/Register/Intel/Msr/CoreMsr.h
new file mode 100644
index 000000000000..a000ab718419
--- /dev/null
+++ b/MdePkg/Include/Register/Intel/Msr/CoreMsr.h
@@ -0,0 +1,1056 @@
+/** @file
+  MSR Definitions for Intel Core Solo and Intel Core Duo Processors.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+  May 2018, Volume 4: Model-Specific-Registers (MSR)
+
+**/
+
+#ifndef __CORE_MSR_H__
+#define __CORE_MSR_H__
+
+#include <Register/Intel/ArchitecturalMsr.h>
+
+/**
+  Is Intel Core Solo and Intel Core Duo Processors?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_CORE_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   ( \
+    DisplayModel == 0x0E \
+    ) \
+   )
+
+/**
+  Unique. See Section 2.22, "MSRs in Pentium Processors," and see Table 2-2.
+
+  @param  ECX  MSR_CORE_P5_MC_ADDR (0x00000000)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_P5_MC_ADDR);
+  AsmWriteMsr64 (MSR_CORE_P5_MC_ADDR, Msr);
+  @endcode
+  @note MSR_CORE_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.
+**/
+#define MSR_CORE_P5_MC_ADDR                      0x00000000
+
+
+/**
+  Unique. See Section 2.22, "MSRs in Pentium Processors," and see Table 2-2.
+
+  @param  ECX  MSR_CORE_P5_MC_TYPE (0x00000001)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_P5_MC_TYPE);
+  AsmWriteMsr64 (MSR_CORE_P5_MC_TYPE, Msr);
+  @endcode
+  @note MSR_CORE_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.
+**/
+#define MSR_CORE_P5_MC_TYPE                      0x00000001
+
+
+/**
+  Shared. Processor Hard Power-On Configuration (R/W) Enables and disables
+  processor features; (R) indicates current processor configuration.
+
+  @param  ECX  MSR_CORE_EBL_CR_POWERON (0x0000002A)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_CORE_EBL_CR_POWERON_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_CORE_EBL_CR_POWERON_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_CORE_EBL_CR_POWERON_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_CORE_EBL_CR_POWERON);
+  AsmWriteMsr64 (MSR_CORE_EBL_CR_POWERON, Msr.Uint64);
+  @endcode
+  @note MSR_CORE_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
+**/
+#define MSR_CORE_EBL_CR_POWERON                  0x0000002A
+
+/**
+  MSR information returned for MSR index #MSR_CORE_EBL_CR_POWERON
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
+    /// Note: Not all processor implements R/W.
+    ///
+    UINT32  DataErrorCheckingEnable:1;
+    ///
+    /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
+    /// Note: Not all processor implements R/W.
+    ///
+    UINT32  ResponseErrorCheckingEnable:1;
+    ///
+    /// [Bit 3] MCERR# Drive Enable (R/W)  1 = Enabled; 0 = Disabled Note: Not
+    /// all processor implements R/W.
+    ///
+    UINT32  MCERR_DriveEnable:1;
+    ///
+    /// [Bit 4] Address Parity Enable (R/W) 1 = Enabled; 0 = Disabled Note:
+    /// Not all processor implements R/W.
+    ///
+    UINT32  AddressParityEnable:1;
+    UINT32  Reserved2:2;
+    ///
+    /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not
+    /// all processor implements R/W.
+    ///
+    UINT32  BINIT_DriverEnable:1;
+    ///
+    /// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.
+    ///
+    UINT32  OutputTriStateEnable:1;
+    ///
+    /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
+    ///
+    UINT32  ExecuteBIST:1;
+    ///
+    /// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.
+    ///
+    UINT32  MCERR_ObservationEnabled:1;
+    UINT32  Reserved3:1;
+    ///
+    /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.
+    ///
+    UINT32  BINIT_ObservationEnabled:1;
+    UINT32  Reserved4:1;
+    ///
+    /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.
+    ///
+    UINT32  ResetVector:1;
+    UINT32  Reserved5:1;
+    ///
+    /// [Bits 17:16] APIC Cluster ID (R/O).
+    ///
+    UINT32  APICClusterID:2;
+    ///
+    /// [Bit 18] System Bus Frequency (R/O) 1. = 100 MHz 2. = Reserved.
+    ///
+    UINT32  SystemBusFrequency:1;
+    UINT32  Reserved6:1;
+    ///
+    /// [Bits 21:20] Symmetric Arbitration ID (R/O).
+    ///
+    UINT32  SymmetricArbitrationID:2;
+    ///
+    /// [Bits 26:22] Clock Frequency Ratio (R/O).
+    ///
+    UINT32  ClockFrequencyRatio:5;
+    UINT32  Reserved7:5;
+    UINT32  Reserved8:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_CORE_EBL_CR_POWERON_REGISTER;
+
+
+/**
+  Unique. Last Branch Record n (R/W) One of 8 last branch record registers on
+  the last branch record stack: bits 31-0 hold the 'from' address and bits
+  63-32 hold the 'to' address. See also: -  Last Branch Record Stack TOS at
+  1C9H -  Section 17.15, "Last Branch, Interrupt, and Exception Recording
+  (Pentium M Processors).".
+
+  @param  ECX  MSR_CORE_LASTBRANCH_n
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_0);
+  AsmWriteMsr64 (MSR_CORE_LASTBRANCH_0, Msr);
+  @endcode
+  @note MSR_CORE_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM.
+        MSR_CORE_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM.
+        MSR_CORE_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM.
+        MSR_CORE_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.
+        MSR_CORE_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM.
+        MSR_CORE_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM.
+        MSR_CORE_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM.
+        MSR_CORE_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.
+  @{
+**/
+#define MSR_CORE_LASTBRANCH_0                    0x00000040
+#define MSR_CORE_LASTBRANCH_1                    0x00000041
+#define MSR_CORE_LASTBRANCH_2                    0x00000042
+#define MSR_CORE_LASTBRANCH_3                    0x00000043
+#define MSR_CORE_LASTBRANCH_4                    0x00000044
+#define MSR_CORE_LASTBRANCH_5                    0x00000045
+#define MSR_CORE_LASTBRANCH_6                    0x00000046
+#define MSR_CORE_LASTBRANCH_7                    0x00000047
+/// @}
+
+
+/**
+  Shared. Scalable Bus Speed (RO) This field indicates the scalable bus
+  clock speed:.
+
+  @param  ECX  MSR_CORE_FSB_FREQ (0x000000CD)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_CORE_FSB_FREQ_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_CORE_FSB_FREQ_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_CORE_FSB_FREQ_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_CORE_FSB_FREQ);
+  @endcode
+  @note MSR_CORE_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.
+**/
+#define MSR_CORE_FSB_FREQ                        0x000000CD
+
+/**
+  MSR information returned for MSR index #MSR_CORE_FSB_FREQ
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 2:0] - Scalable Bus Speed
+    ///   101B: 100 MHz (FSB 400)
+    ///   001B: 133 MHz (FSB 533)
+    ///   011B: 167 MHz (FSB 667)
+    ///
+    /// 133.33 MHz should be utilized if performing calculation with System Bus
+    /// Speed when encoding is 101B. 166.67 MHz should be utilized if
+    /// performing calculation with System Bus Speed when encoding is 001B.
+    ///
+    UINT32  ScalableBusSpeed:3;
+    UINT32  Reserved1:29;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_CORE_FSB_FREQ_REGISTER;
+
+
+/**
+  Shared.
+
+  @param  ECX  MSR_CORE_BBL_CR_CTL3 (0x0000011E)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_CORE_BBL_CR_CTL3_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_CORE_BBL_CR_CTL3_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_CORE_BBL_CR_CTL3_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_CORE_BBL_CR_CTL3);
+  AsmWriteMsr64 (MSR_CORE_BBL_CR_CTL3, Msr.Uint64);
+  @endcode
+  @note MSR_CORE_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
+**/
+#define MSR_CORE_BBL_CR_CTL3                     0x0000011E
+
+/**
+  MSR information returned for MSR index #MSR_CORE_BBL_CR_CTL3
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
+    /// Indicates if the L2 is hardware-disabled.
+    ///
+    UINT32  L2HardwareEnabled:1;
+    UINT32  Reserved1:7;
+    ///
+    /// [Bit 8] L2 Enabled (R/W)  1 = L2 cache has been initialized 0 =
+    /// Disabled (default) Until this bit is set the processor will not
+    /// respond to the WBINVD instruction or the assertion of the FLUSH# input.
+    ///
+    UINT32  L2Enabled:1;
+    UINT32  Reserved2:14;
+    ///
+    /// [Bit 23] L2 Not Present (RO)  1. = L2 Present 2. = L2 Not Present.
+    ///
+    UINT32  L2NotPresent:1;
+    UINT32  Reserved3:8;
+    UINT32  Reserved4:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_CORE_BBL_CR_CTL3_REGISTER;
+
+
+/**
+  Unique.
+
+  @param  ECX  MSR_CORE_THERM2_CTL (0x0000019D)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_CORE_THERM2_CTL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_CORE_THERM2_CTL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_CORE_THERM2_CTL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_CORE_THERM2_CTL);
+  AsmWriteMsr64 (MSR_CORE_THERM2_CTL, Msr.Uint64);
+  @endcode
+  @note MSR_CORE_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
+**/
+#define MSR_CORE_THERM2_CTL                      0x0000019D
+
+/**
+  MSR information returned for MSR index #MSR_CORE_THERM2_CTL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:16;
+    ///
+    /// [Bit 16] TM_SELECT (R/W)  Mode of automatic thermal monitor: 1. =
+    /// Thermal Monitor 1 (thermally-initiated on-die modulation of the
+    /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated
+    /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is
+    /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled.
+    ///
+    UINT32  TM_SELECT:1;
+    UINT32  Reserved2:15;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_CORE_THERM2_CTL_REGISTER;
+
+
+/**
+  Enable Miscellaneous Processor Features (R/W) Allows a variety of processor
+  functions to be enabled and disabled.
+
+  @param  ECX  MSR_CORE_IA32_MISC_ENABLE (0x000001A0)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_CORE_IA32_MISC_ENABLE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_CORE_IA32_MISC_ENABLE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_CORE_IA32_MISC_ENABLE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_MISC_ENABLE);
+  AsmWriteMsr64 (MSR_CORE_IA32_MISC_ENABLE, Msr.Uint64);
+  @endcode
+  @note MSR_CORE_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
+**/
+#define MSR_CORE_IA32_MISC_ENABLE                0x000001A0
+
+/**
+  MSR information returned for MSR index #MSR_CORE_IA32_MISC_ENABLE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:3;
+    ///
+    /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See
+    /// Table 2-2.
+    ///
+    UINT32  AutomaticThermalControlCircuit:1;
+    UINT32  Reserved2:3;
+    ///
+    /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2.
+    ///
+    UINT32  PerformanceMonitoring:1;
+    UINT32  Reserved3:2;
+    ///
+    /// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by
+    /// the processor to indicate a pending break event within the processor 0
+    /// = Indicates compatible FERR# signaling behavior This bit must be set
+    /// to 1 to support XAPIC interrupt model usage.
+    ///
+    UINT32  FERR:1;
+    ///
+    /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2.
+    ///
+    UINT32  BTS:1;
+    UINT32  Reserved4:1;
+    ///
+    /// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the
+    /// thermal sensor indicates that the die temperature is at the
+    /// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.
+    /// TM2 will reduce the bus to core ratio and voltage according to the
+    /// value last written to MSR_THERM2_CTL bits 15:0. When this bit is clear
+    /// (0, default), the processor does not change the VID signals or the bus
+    /// to core ratio when the processor enters a thermal managed state. If
+    /// the TM2 feature flag (ECX[8]) is not set to 1 after executing CPUID
+    /// with EAX = 1, then this feature is not supported and BIOS must not
+    /// alter the contents of this bit location. The processor is operating
+    /// out of spec if both this bit and the TM1 bit are set to disabled
+    /// states.
+    ///
+    UINT32  TM2:1;
+    UINT32  Reserved5:2;
+    ///
+    /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) 1 =
+    /// Enhanced Intel SpeedStep Technology enabled.
+    ///
+    UINT32  EIST:1;
+    UINT32  Reserved6:1;
+    ///
+    /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2.
+    ///
+    UINT32  MONITOR:1;
+    UINT32  Reserved7:1;
+    UINT32  Reserved8:2;
+    ///
+    /// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 2-2. Setting this
+    /// bit may cause behavior in software that depends on the availability of
+    /// CPUID leaves greater than 2.
+    ///
+    UINT32  LimitCpuidMaxval:1;
+    UINT32  Reserved9:9;
+    UINT32  Reserved10:2;
+    ///
+    /// [Bit 34] Shared. XD Bit Disable (R/W) See Table 2-2.
+    ///
+    UINT32  XD:1;
+    UINT32  Reserved11:29;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_CORE_IA32_MISC_ENABLE_REGISTER;
+
+
+/**
+  Unique. Last Branch Record Stack TOS (R/W)  Contains an index (bits 0-3)
+  that points to the MSR containing the most recent branch record. See
+  MSR_LASTBRANCH_0_FROM_IP (at 40H).
+
+  @param  ECX  MSR_CORE_LASTBRANCH_TOS (0x000001C9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_LASTBRANCH_TOS);
+  AsmWriteMsr64 (MSR_CORE_LASTBRANCH_TOS, Msr);
+  @endcode
+  @note MSR_CORE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
+**/
+#define MSR_CORE_LASTBRANCH_TOS                  0x000001C9
+
+
+/**
+  Unique. Last Exception Record From Linear IP (R)  Contains a pointer to the
+  last branch instruction that the processor executed prior to the last
+  exception that was generated or the last interrupt that was handled.
+
+  @param  ECX  MSR_CORE_LER_FROM_LIP (0x000001DD)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_LER_FROM_LIP);
+  @endcode
+  @note MSR_CORE_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
+**/
+#define MSR_CORE_LER_FROM_LIP                    0x000001DD
+
+
+/**
+  Unique. Last Exception Record To Linear IP (R)  This area contains a pointer
+  to the target of the last branch instruction that the processor executed
+  prior to the last exception that was generated or the last interrupt that
+  was handled.
+
+  @param  ECX  MSR_CORE_LER_TO_LIP (0x000001DE)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_LER_TO_LIP);
+  @endcode
+  @note MSR_CORE_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
+**/
+#define MSR_CORE_LER_TO_LIP                      0x000001DE
+
+/**
+  Unique.
+
+  @param  ECX  MSR_CORE_MTRRPHYSBASEn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSBASE0);
+  AsmWriteMsr64 (MSR_CORE_MTRRPHYSBASE0, Msr);
+  @endcode
+  @note MSR_CORE_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM.
+        MSR_CORE_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM.
+        MSR_CORE_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM.
+        MSR_CORE_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM.
+        MSR_CORE_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM.
+        MSR_CORE_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM.
+        MSR_CORE_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM.
+        MSR_CORE_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM.
+  @{
+**/
+#define MSR_CORE_MTRRPHYSBASE0                   0x00000200
+#define MSR_CORE_MTRRPHYSBASE1                   0x00000202
+#define MSR_CORE_MTRRPHYSBASE2                   0x00000204
+#define MSR_CORE_MTRRPHYSBASE3                   0x00000206
+#define MSR_CORE_MTRRPHYSBASE4                   0x00000208
+#define MSR_CORE_MTRRPHYSBASE5                   0x0000020A
+#define MSR_CORE_MTRRPHYSMASK6                   0x0000020D
+#define MSR_CORE_MTRRPHYSMASK7                   0x0000020F
+/// @}
+
+
+/**
+  Unique.
+
+  @param  ECX  MSR_CORE_MTRRPHYSMASKn (0x00000201)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MTRRPHYSMASK0);
+  AsmWriteMsr64 (MSR_CORE_MTRRPHYSMASK0, Msr);
+  @endcode
+  @note MSR_CORE_MTRRPHYSMASK0 is defined as MTRRPHYSMASK0 in SDM.
+        MSR_CORE_MTRRPHYSMASK1 is defined as MTRRPHYSMASK1 in SDM.
+        MSR_CORE_MTRRPHYSMASK2 is defined as MTRRPHYSMASK2 in SDM.
+        MSR_CORE_MTRRPHYSMASK3 is defined as MTRRPHYSMASK3 in SDM.
+        MSR_CORE_MTRRPHYSMASK4 is defined as MTRRPHYSMASK4 in SDM.
+        MSR_CORE_MTRRPHYSMASK5 is defined as MTRRPHYSMASK5 in SDM.
+        MSR_CORE_MTRRPHYSBASE6 is defined as MTRRPHYSBASE6 in SDM.
+        MSR_CORE_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM.
+  @{
+**/
+#define MSR_CORE_MTRRPHYSMASK0                   0x00000201
+#define MSR_CORE_MTRRPHYSMASK1                   0x00000203
+#define MSR_CORE_MTRRPHYSMASK2                   0x00000205
+#define MSR_CORE_MTRRPHYSMASK3                   0x00000207
+#define MSR_CORE_MTRRPHYSMASK4                   0x00000209
+#define MSR_CORE_MTRRPHYSMASK5                   0x0000020B
+#define MSR_CORE_MTRRPHYSBASE6                   0x0000020C
+#define MSR_CORE_MTRRPHYSBASE7                   0x0000020E
+/// @}
+
+
+/**
+  Unique.
+
+  @param  ECX  MSR_CORE_MTRRFIX64K_00000 (0x00000250)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX64K_00000);
+  AsmWriteMsr64 (MSR_CORE_MTRRFIX64K_00000, Msr);
+  @endcode
+  @note MSR_CORE_MTRRFIX64K_00000 is defined as MTRRFIX64K_00000 in SDM.
+**/
+#define MSR_CORE_MTRRFIX64K_00000                0x00000250
+
+
+/**
+  Unique.
+
+  @param  ECX  MSR_CORE_MTRRFIX16K_80000 (0x00000258)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX16K_80000);
+  AsmWriteMsr64 (MSR_CORE_MTRRFIX16K_80000, Msr);
+  @endcode
+  @note MSR_CORE_MTRRFIX16K_80000 is defined as MTRRFIX16K_80000 in SDM.
+**/
+#define MSR_CORE_MTRRFIX16K_80000                0x00000258
+
+
+/**
+  Unique.
+
+  @param  ECX  MSR_CORE_MTRRFIX16K_A0000 (0x00000259)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX16K_A0000);
+  AsmWriteMsr64 (MSR_CORE_MTRRFIX16K_A0000, Msr);
+  @endcode
+  @note MSR_CORE_MTRRFIX16K_A0000 is defined as MTRRFIX16K_A0000 in SDM.
+**/
+#define MSR_CORE_MTRRFIX16K_A0000                0x00000259
+
+
+/**
+  Unique.
+
+  @param  ECX  MSR_CORE_MTRRFIX4K_C0000 (0x00000268)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_C0000);
+  AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_C0000, Msr);
+  @endcode
+  @note MSR_CORE_MTRRFIX4K_C0000 is defined as MTRRFIX4K_C0000 in SDM.
+**/
+#define MSR_CORE_MTRRFIX4K_C0000                 0x00000268
+
+
+/**
+  Unique.
+
+  @param  ECX  MSR_CORE_MTRRFIX4K_C8000 (0x00000269)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_C8000);
+  AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_C8000, Msr);
+  @endcode
+  @note MSR_CORE_MTRRFIX4K_C8000 is defined as MTRRFIX4K_C8000 in SDM.
+**/
+#define MSR_CORE_MTRRFIX4K_C8000                 0x00000269
+
+
+/**
+  Unique.
+
+  @param  ECX  MSR_CORE_MTRRFIX4K_D0000 (0x0000026A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_D0000);
+  AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_D0000, Msr);
+  @endcode
+  @note MSR_CORE_MTRRFIX4K_D0000 is defined as MTRRFIX4K_D0000 in SDM.
+**/
+#define MSR_CORE_MTRRFIX4K_D0000                 0x0000026A
+
+
+/**
+  Unique.
+
+  @param  ECX  MSR_CORE_MTRRFIX4K_D8000 (0x0000026B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_D8000);
+  AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_D8000, Msr);
+  @endcode
+  @note MSR_CORE_MTRRFIX4K_D8000 is defined as MTRRFIX4K_D8000 in SDM.
+**/
+#define MSR_CORE_MTRRFIX4K_D8000                 0x0000026B
+
+
+/**
+  Unique.
+
+  @param  ECX  MSR_CORE_MTRRFIX4K_E0000 (0x0000026C)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_E0000);
+  AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_E0000, Msr);
+  @endcode
+  @note MSR_CORE_MTRRFIX4K_E0000 is defined as MTRRFIX4K_E0000 in SDM.
+**/
+#define MSR_CORE_MTRRFIX4K_E0000                 0x0000026C
+
+
+/**
+  Unique.
+
+  @param  ECX  MSR_CORE_MTRRFIX4K_E8000 (0x0000026D)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_E8000);
+  AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_E8000, Msr);
+  @endcode
+  @note MSR_CORE_MTRRFIX4K_E8000 is defined as MTRRFIX4K_E8000 in SDM.
+**/
+#define MSR_CORE_MTRRFIX4K_E8000                 0x0000026D
+
+
+/**
+  Unique.
+
+  @param  ECX  MSR_CORE_MTRRFIX4K_F0000 (0x0000026E)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_F0000);
+  AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_F0000, Msr);
+  @endcode
+  @note MSR_CORE_MTRRFIX4K_F0000 is defined as MTRRFIX4K_F0000 in SDM.
+**/
+#define MSR_CORE_MTRRFIX4K_F0000                 0x0000026E
+
+
+/**
+  Unique.
+
+  @param  ECX  MSR_CORE_MTRRFIX4K_F8000 (0x0000026F)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MTRRFIX4K_F8000);
+  AsmWriteMsr64 (MSR_CORE_MTRRFIX4K_F8000, Msr);
+  @endcode
+  @note MSR_CORE_MTRRFIX4K_F8000 is defined as MTRRFIX4K_F8000 in SDM.
+**/
+#define MSR_CORE_MTRRFIX4K_F8000                 0x0000026F
+
+
+/**
+  Unique. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
+
+  @param  ECX  MSR_CORE_MC4_CTL (0x0000040C)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MC4_CTL);
+  AsmWriteMsr64 (MSR_CORE_MC4_CTL, Msr);
+  @endcode
+  @note MSR_CORE_MC4_CTL is defined as MSR_MC4_CTL in SDM.
+**/
+#define MSR_CORE_MC4_CTL                         0x0000040C
+
+
+/**
+  Unique. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
+
+  @param  ECX  MSR_CORE_MC4_STATUS (0x0000040D)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MC4_STATUS);
+  AsmWriteMsr64 (MSR_CORE_MC4_STATUS, Msr);
+  @endcode
+  @note MSR_CORE_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.
+**/
+#define MSR_CORE_MC4_STATUS                      0x0000040D
+
+
+/**
+  Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR
+  register is either not implemented or contains no address if the ADDRV flag
+  in the MSR_MC4_STATUS register is clear. When not implemented in the
+  processor, all reads and writes to this MSR will cause a general-protection
+  exception.
+
+  @param  ECX  MSR_CORE_MC4_ADDR (0x0000040E)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MC4_ADDR);
+  AsmWriteMsr64 (MSR_CORE_MC4_ADDR, Msr);
+  @endcode
+  @note MSR_CORE_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.
+**/
+#define MSR_CORE_MC4_ADDR                        0x0000040E
+
+
+/**
+  Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR
+  register is either not implemented or contains no address if the ADDRV flag
+  in the MSR_MC3_STATUS register is clear. When not implemented in the
+  processor, all reads and writes to this MSR will cause a general-protection
+  exception.
+
+  @param  ECX  MSR_CORE_MC3_ADDR (0x00000412)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MC3_ADDR);
+  AsmWriteMsr64 (MSR_CORE_MC3_ADDR, Msr);
+  @endcode
+  @note MSR_CORE_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.
+**/
+#define MSR_CORE_MC3_ADDR                        0x00000412
+
+
+/**
+  Unique.
+
+  @param  ECX  MSR_CORE_MC3_MISC (0x00000413)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MC3_MISC);
+  AsmWriteMsr64 (MSR_CORE_MC3_MISC, Msr);
+  @endcode
+  @note MSR_CORE_MC3_MISC is defined as MSR_MC3_MISC in SDM.
+**/
+#define MSR_CORE_MC3_MISC                        0x00000413
+
+
+/**
+  Unique.
+
+  @param  ECX  MSR_CORE_MC5_CTL (0x00000414)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MC5_CTL);
+  AsmWriteMsr64 (MSR_CORE_MC5_CTL, Msr);
+  @endcode
+  @note MSR_CORE_MC5_CTL is defined as MSR_MC5_CTL in SDM.
+**/
+#define MSR_CORE_MC5_CTL                         0x00000414
+
+
+/**
+  Unique.
+
+  @param  ECX  MSR_CORE_MC5_STATUS (0x00000415)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MC5_STATUS);
+  AsmWriteMsr64 (MSR_CORE_MC5_STATUS, Msr);
+  @endcode
+  @note MSR_CORE_MC5_STATUS is defined as MSR_MC5_STATUS in SDM.
+**/
+#define MSR_CORE_MC5_STATUS                      0x00000415
+
+
+/**
+  Unique.
+
+  @param  ECX  MSR_CORE_MC5_ADDR (0x00000416)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MC5_ADDR);
+  AsmWriteMsr64 (MSR_CORE_MC5_ADDR, Msr);
+  @endcode
+  @note MSR_CORE_MC5_ADDR is defined as MSR_MC5_ADDR in SDM.
+**/
+#define MSR_CORE_MC5_ADDR                        0x00000416
+
+
+/**
+  Unique.
+
+  @param  ECX  MSR_CORE_MC5_MISC (0x00000417)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_CORE_MC5_MISC);
+  AsmWriteMsr64 (MSR_CORE_MC5_MISC, Msr);
+  @endcode
+  @note MSR_CORE_MC5_MISC is defined as MSR_MC5_MISC in SDM.
+**/
+#define MSR_CORE_MC5_MISC                        0x00000417
+
+
+/**
+  Unique. See Table 2-2.
+
+  @param  ECX  MSR_CORE_IA32_EFER (0xC0000080)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_CORE_IA32_EFER_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_CORE_IA32_EFER_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_CORE_IA32_EFER_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_EFER);
+  AsmWriteMsr64 (MSR_CORE_IA32_EFER, Msr.Uint64);
+  @endcode
+  @note MSR_CORE_IA32_EFER is defined as IA32_EFER in SDM.
+**/
+#define MSR_CORE_IA32_EFER                       0xC0000080
+
+/**
+  MSR information returned for MSR index #MSR_CORE_IA32_EFER
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:11;
+    ///
+    /// [Bit 11] Execute Disable Bit Enable.
+    ///
+    UINT32  NXE:1;
+    UINT32  Reserved2:20;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_CORE_IA32_EFER_REGISTER;
+
+#endif
diff --git a/MdePkg/Include/Register/Intel/Msr/GoldmontMsr.h b/MdePkg/Include/Register/Intel/Msr/GoldmontMsr.h
new file mode 100644
index 000000000000..a8da54c39459
--- /dev/null
+++ b/MdePkg/Include/Register/Intel/Msr/GoldmontMsr.h
@@ -0,0 +1,2539 @@
+/** @file
+  MSR Definitions for Intel Atom processors based on the Goldmont microarchitecture.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+  May 2018, Volume 4: Model-Specific-Registers (MSR)
+
+**/
+
+#ifndef __GOLDMONT_MSR_H__
+#define __GOLDMONT_MSR_H__
+
+#include <Register/Intel/ArchitecturalMsr.h>
+
+/**
+  Is Intel Atom processors based on the Goldmont microarchitecture?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_GOLDMONT_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (                        \
+    DisplayModel == 0x5C    \
+    )                       \
+   )
+
+/**
+  Core. Control Features in Intel 64Processor (R/W).
+
+  @param  ECX  MSR_GOLDMONT_FEATURE_CONTROL (0x0000003A)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_FEATURE_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_FEATURE_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_FEATURE_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_FEATURE_CONTROL);
+  AsmWriteMsr64 (MSR_GOLDMONT_FEATURE_CONTROL, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.
+**/
+#define MSR_GOLDMONT_FEATURE_CONTROL             0x0000003A
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_FEATURE_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Lock bit (R/WL)
+    ///
+    UINT32  Lock:1;
+    ///
+    /// [Bit 1] Enable VMX inside SMX operation (R/WL)
+    ///
+    UINT32  EnableVmxInsideSmx:1;
+    ///
+    /// [Bit 2] Enable VMX outside SMX operation (R/WL)
+    ///
+    UINT32  EnableVmxOutsideSmx:1;
+    UINT32  Reserved1:5;
+    ///
+    /// [Bits 14:8] SENTER local function enables (R/WL)
+    ///
+    UINT32  SenterLocalFunctionEnables:7;
+    ///
+    /// [Bit 15] SENTER global functions enable (R/WL)
+    ///
+    UINT32  SenterGlobalEnable:1;
+    UINT32  Reserved2:2;
+    ///
+    /// [Bit 18] SGX global functions enable (R/WL)
+    ///
+    UINT32  SgxEnable:1;
+    UINT32  Reserved3:13;
+    UINT32  Reserved4:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_FEATURE_CONTROL_REGISTER;
+
+
+/**
+  Package. See http://biosbits.org.
+
+  @param  ECX  MSR_GOLDMONT_PLATFORM_INFO (0x000000CE)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_PLATFORM_INFO_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_PLATFORM_INFO_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_PLATFORM_INFO_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PLATFORM_INFO);
+  AsmWriteMsr64 (MSR_GOLDMONT_PLATFORM_INFO, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
+**/
+#define MSR_GOLDMONT_PLATFORM_INFO               0x000000CE
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_PLATFORM_INFO
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:8;
+    ///
+    /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O)  The is the ratio
+    /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
+    /// MHz.
+    ///
+    UINT32  MaximumNonTurboRatio:8;
+    UINT32  Reserved2:12;
+    ///
+    /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O)  When
+    /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
+    /// enabled, and when set to 0, indicates Programmable Ratio Limits for
+    /// Turbo mode is disabled.
+    ///
+    UINT32  RatioLimit:1;
+    ///
+    /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O)  When
+    /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
+    /// and when set to 0, indicates TDP Limit for Turbo mode is not
+    /// programmable.
+    ///
+    UINT32  TDPLimit:1;
+    ///
+    /// [Bit 30] Package. Programmable TJ OFFSET (R/O)  When set to 1,
+    /// indicates that MSR_TEMPERATURE_TARGET.[27:24] is valid and writable to
+    /// specify an temperature offset.
+    ///
+    UINT32  TJOFFSET:1;
+    UINT32  Reserved3:1;
+    UINT32  Reserved4:8;
+    ///
+    /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O)  The is the
+    /// minimum ratio (maximum efficiency) that the processor can operates, in
+    /// units of 100MHz.
+    ///
+    UINT32  MaximumEfficiencyRatio:8;
+    UINT32  Reserved5:16;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_PLATFORM_INFO_REGISTER;
+
+
+/**
+  Core. C-State Configuration Control (R/W)  Note: C-state values are
+  processor specific C-state code names, unrelated to MWAIT extension C-state
+  parameters or ACPI CStates. See http://biosbits.org.
+
+  @param  ECX  MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL (0x000000E2)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type
+               MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type
+               MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL);
+  AsmWriteMsr64 (MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
+**/
+#define MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL      0x000000E2
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 3:0] Package C-State Limit (R/W)  Specifies the lowest
+    /// processor-specific C-state code name (consuming the least power). for
+    /// the package. The default is set as factory-configured package C-state
+    /// limit. The following C-state code name encodings are supported: 0000b:
+    /// No limit 0001b: C1 0010b: C3 0011b: C6 0100b: C7 0101b: C7S 0110b: C8
+    /// 0111b: C9 1000b: C10.
+    ///
+    UINT32  Limit:4;
+    UINT32  Reserved1:6;
+    ///
+    /// [Bit 10] I/O MWAIT Redirection Enable (R/W)  When set, will map
+    /// IO_read instructions sent to IO register specified by
+    /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
+    ///
+    UINT32  IO_MWAIT:1;
+    UINT32  Reserved2:4;
+    ///
+    /// [Bit 15] CFG Lock (R/WO)  When set, lock bits 15:0 of this register
+    /// until next reset.
+    ///
+    UINT32  CFGLock:1;
+    UINT32  Reserved3:16;
+    UINT32  Reserved4:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER;
+
+
+/**
+  Core. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability Enhancement.
+  Accessible only while in SMM.
+
+  @param  ECX  MSR_GOLDMONT_SMM_MCA_CAP (0x0000017D)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_SMM_MCA_CAP_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_SMM_MCA_CAP_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_SMM_MCA_CAP_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_MCA_CAP);
+  AsmWriteMsr64 (MSR_GOLDMONT_SMM_MCA_CAP, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.
+**/
+#define MSR_GOLDMONT_SMM_MCA_CAP                 0x0000017D
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_SMM_MCA_CAP
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:32;
+    UINT32  Reserved2:26;
+    ///
+    /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
+    /// SMM code access restriction is supported and the
+    /// MSR_SMM_FEATURE_CONTROL is supported.
+    ///
+    UINT32  SMM_Code_Access_Chk:1;
+    ///
+    /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the
+    /// SMM long flow indicator is supported and the MSR_SMM_DELAYED is
+    /// supported.
+    ///
+    UINT32  Long_Flow_Indication:1;
+    UINT32  Reserved3:4;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_SMM_MCA_CAP_REGISTER;
+
+
+/**
+  Enable Misc. Processor Features (R/W)  Allows a variety of processor
+  functions to be enabled and disabled.
+
+  @param  ECX  MSR_GOLDMONT_IA32_MISC_ENABLE (0x000001A0)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_MISC_ENABLE);
+  AsmWriteMsr64 (MSR_GOLDMONT_IA32_MISC_ENABLE, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
+**/
+#define MSR_GOLDMONT_IA32_MISC_ENABLE            0x000001A0
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_IA32_MISC_ENABLE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Core. Fast-Strings Enable See Table 2-2.
+    ///
+    UINT32  FastStrings:1;
+    UINT32  Reserved1:2;
+    ///
+    /// [Bit 3] Package. Automatic Thermal Control Circuit Enable (R/W) See
+    /// Table 2-2. Default value is 1.
+    ///
+    UINT32  AutomaticThermalControlCircuit:1;
+    UINT32  Reserved2:3;
+    ///
+    /// [Bit 7] Core. Performance Monitoring Available (R) See Table 2-2.
+    ///
+    UINT32  PerformanceMonitoring:1;
+    UINT32  Reserved3:3;
+    ///
+    /// [Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 2-2.
+    ///
+    UINT32  BTS:1;
+    ///
+    /// [Bit 12] Core. Processor Event Based Sampling Unavailable (RO) See
+    /// Table 2-2.
+    ///
+    UINT32  PEBS:1;
+    UINT32  Reserved4:3;
+    ///
+    /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See
+    /// Table 2-2.
+    ///
+    UINT32  EIST:1;
+    UINT32  Reserved5:1;
+    ///
+    /// [Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 2-2.
+    ///
+    UINT32  MONITOR:1;
+    UINT32  Reserved6:3;
+    ///
+    /// [Bit 22] Core. Limit CPUID Maxval (R/W) See Table 2-2.
+    ///
+    UINT32  LimitCpuidMaxval:1;
+    ///
+    /// [Bit 23] Package. xTPR Message Disable (R/W) See Table 2-2.
+    ///
+    UINT32  xTPR_Message_Disable:1;
+    UINT32  Reserved7:8;
+    UINT32  Reserved8:2;
+    ///
+    /// [Bit 34] Core. XD Bit Disable (R/W) See Table 2-2.
+    ///
+    UINT32  XD:1;
+    UINT32  Reserved9:3;
+    ///
+    /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors
+    /// that support Intel Turbo Boost Technology, the turbo mode feature is
+    /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:
+    /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:
+    /// EAX[1] reports the processor's support of turbo mode is enabled. Note:
+    /// the power-on default value is used by BIOS to detect hardware support
+    /// of turbo mode. If power-on default value is 1, turbo mode is available
+    /// in the processor. If power-on default value is 0, turbo mode is not
+    /// available.
+    ///
+    UINT32  TurboModeDisable:1;
+    UINT32  Reserved10:25;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER;
+
+
+/**
+  Miscellaneous Feature Control (R/W).
+
+  @param  ECX  MSR_GOLDMONT_MISC_FEATURE_CONTROL (0x000001A4)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_MISC_FEATURE_CONTROL);
+  AsmWriteMsr64 (MSR_GOLDMONT_MISC_FEATURE_CONTROL, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.
+**/
+#define MSR_GOLDMONT_MISC_FEATURE_CONTROL        0x000001A4
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_MISC_FEATURE_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W)  If 1, disables the
+    /// L2 hardware prefetcher, which fetches additional lines of code or data
+    /// into the L2 cache.
+    ///
+    UINT32  L2HardwarePrefetcherDisable:1;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W)  If 1, disables
+    /// the L1 data cache prefetcher, which fetches the next cache line into
+    /// L1 data cache.
+    ///
+    UINT32  DCUHardwarePrefetcherDisable:1;
+    UINT32  Reserved2:29;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER;
+
+
+/**
+  Package. See http://biosbits.org.
+
+  @param  ECX  MSR_GOLDMONT_MISC_PWR_MGMT (0x000001AA)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_MISC_PWR_MGMT);
+  AsmWriteMsr64 (MSR_GOLDMONT_MISC_PWR_MGMT, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM.
+**/
+#define MSR_GOLDMONT_MISC_PWR_MGMT               0x000001AA
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_MISC_PWR_MGMT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] EIST Hardware Coordination Disable (R/W) When 0, enables
+    /// hardware coordination of Enhanced Intel Speedstep Technology request
+    /// from processor cores; When 1, disables hardware coordination of
+    /// Enhanced Intel Speedstep Technology requests.
+    ///
+    UINT32  EISTHardwareCoordinationDisable:1;
+    UINT32  Reserved1:21;
+    ///
+    /// [Bit 22] Thermal Interrupt Coordination Enable (R/W)  If set, then
+    /// thermal interrupt on one core is routed to all cores.
+    ///
+    UINT32  ThermalInterruptCoordinationEnable:1;
+    UINT32  Reserved2:9;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER;
+
+
+/**
+  Package. Maximum Ratio Limit of Turbo Mode by Core Groups (RW) Specifies
+  Maximum Ratio Limit for each Core Group. Max ratio for groups with more
+  cores must decrease monotonically. For groups with less than 4 cores, the
+  max ratio must be 32 or less. For groups with 4-5 cores, the max ratio must
+  be 22 or less. For groups with more than 5 cores, the max ratio must be 16
+  or less..
+
+  @param  ECX  MSR_GOLDMONT_TURBO_RATIO_LIMIT (0x000001AD)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_TURBO_RATIO_LIMIT);
+  AsmWriteMsr64 (MSR_GOLDMONT_TURBO_RATIO_LIMIT, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
+**/
+#define MSR_GOLDMONT_TURBO_RATIO_LIMIT           0x000001AD
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_TURBO_RATIO_LIMIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Package. Maximum Ratio Limit for Active cores in Group 0
+    /// Maximum turbo ratio limit when number of active cores is less or equal
+    /// to Group 0 threshold.
+    ///
+    UINT32  MaxRatioLimitGroup0:8;
+    ///
+    /// [Bits 15:8] Package. Maximum Ratio Limit for Active cores in Group 1
+    /// Maximum turbo ratio limit when number of active cores is less or equal
+    /// to Group 1 threshold and greater than Group 0 threshold.
+    ///
+    UINT32  MaxRatioLimitGroup1:8;
+    ///
+    /// [Bits 23:16] Package. Maximum Ratio Limit for Active cores in Group 2
+    /// Maximum turbo ratio limit when number of active cores is less or equal
+    /// to Group 2 threshold and greater than Group 1 threshold.
+    ///
+    UINT32  MaxRatioLimitGroup2:8;
+    ///
+    /// [Bits 31:24] Package. Maximum Ratio Limit for Active cores in Group 3
+    /// Maximum turbo ratio limit when number of active cores is less or equal
+    /// to Group 3 threshold and greater than Group 2 threshold.
+    ///
+    UINT32  MaxRatioLimitGroup3:8;
+    ///
+    /// [Bits 39:32] Package. Maximum Ratio Limit for Active cores in Group 4
+    /// Maximum turbo ratio limit when number of active cores is less or equal
+    /// to Group 4 threshold and greater than Group 3 threshold.
+    ///
+    UINT32  MaxRatioLimitGroup4:8;
+    ///
+    /// [Bits 47:40] Package. Maximum Ratio Limit for Active cores in Group 5
+    /// Maximum turbo ratio limit when number of active cores is less or equal
+    /// to Group 5 threshold and greater than Group 4 threshold.
+    ///
+    UINT32  MaxRatioLimitGroup5:8;
+    ///
+    /// [Bits 55:48] Package. Maximum Ratio Limit for Active cores in Group 6
+    /// Maximum turbo ratio limit when number of active cores is less or equal
+    /// to Group 6 threshold and greater than Group 5 threshold.
+    ///
+    UINT32  MaxRatioLimitGroup6:8;
+    ///
+    /// [Bits 63:56] Package. Maximum Ratio Limit for Active cores in Group 7
+    /// Maximum turbo ratio limit when number of active cores is less or equal
+    /// to Group 7 threshold and greater than Group 6 threshold.
+    ///
+    UINT32  MaxRatioLimitGroup7:8;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER;
+
+
+/**
+  Package. Group Size of Active Cores for Turbo Mode Operation (RW) Writes of
+  0 threshold is ignored.
+
+  @param  ECX  MSR_GOLDMONT_TURBO_GROUP_CORECNT (0x000001AE)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_TURBO_GROUP_CORECNT);
+  AsmWriteMsr64 (MSR_GOLDMONT_TURBO_GROUP_CORECNT, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_TURBO_GROUP_CORECNT is defined as MSR_TURBO_GROUP_CORECNT in SDM.
+**/
+#define MSR_GOLDMONT_TURBO_GROUP_CORECNT         0x000001AE
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_TURBO_GROUP_CORECNT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Package. Group 0 Core Count Threshold Maximum number of
+    /// active cores to operate under Group 0 Max Turbo Ratio limit.
+    ///
+    UINT32  CoreCountThresholdGroup0:8;
+    ///
+    /// [Bits 15:8] Package. Group 1 Core Count Threshold Maximum number of
+    /// active cores to operate under Group 1 Max Turbo Ratio limit. Must be
+    /// greater than Group 0 Core Count.
+    ///
+    UINT32  CoreCountThresholdGroup1:8;
+    ///
+    /// [Bits 23:16] Package. Group 2 Core Count Threshold Maximum number of
+    /// active cores to operate under Group 2 Max Turbo Ratio limit. Must be
+    /// greater than Group 1 Core Count.
+    ///
+    UINT32  CoreCountThresholdGroup2:8;
+    ///
+    /// [Bits 31:24] Package. Group 3 Core Count Threshold Maximum number of
+    /// active cores to operate under Group 3 Max Turbo Ratio limit. Must be
+    /// greater than Group 2 Core Count.
+    ///
+    UINT32  CoreCountThresholdGroup3:8;
+    ///
+    /// [Bits 39:32] Package. Group 4 Core Count Threshold Maximum number of
+    /// active cores to operate under Group 4 Max Turbo Ratio limit. Must be
+    /// greater than Group 3 Core Count.
+    ///
+    UINT32  CoreCountThresholdGroup4:8;
+    ///
+    /// [Bits 47:40] Package. Group 5 Core Count Threshold Maximum number of
+    /// active cores to operate under Group 5 Max Turbo Ratio limit. Must be
+    /// greater than Group 4 Core Count.
+    ///
+    UINT32  CoreCountThresholdGroup5:8;
+    ///
+    /// [Bits 55:48] Package. Group 6 Core Count Threshold Maximum number of
+    /// active cores to operate under Group 6 Max Turbo Ratio limit. Must be
+    /// greater than Group 5 Core Count.
+    ///
+    UINT32  CoreCountThresholdGroup6:8;
+    ///
+    /// [Bits 63:56] Package. Group 7 Core Count Threshold Maximum number of
+    /// active cores to operate under Group 7 Max Turbo Ratio limit. Must be
+    /// greater than Group 6 Core Count and not less than the total number of
+    /// processor cores in the package. E.g. specify 255.
+    ///
+    UINT32  CoreCountThresholdGroup7:8;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER;
+
+
+/**
+  Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2,
+  "Filtering of Last Branch Records.".
+
+  @param  ECX  MSR_GOLDMONT_LBR_SELECT (0x000001C8)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_LBR_SELECT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_LBR_SELECT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_LBR_SELECT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_LBR_SELECT);
+  AsmWriteMsr64 (MSR_GOLDMONT_LBR_SELECT, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
+**/
+#define MSR_GOLDMONT_LBR_SELECT                  0x000001C8
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_LBR_SELECT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] CPL_EQ_0.
+    ///
+    UINT32  CPL_EQ_0:1;
+    ///
+    /// [Bit 1] CPL_NEQ_0.
+    ///
+    UINT32  CPL_NEQ_0:1;
+    ///
+    /// [Bit 2] JCC.
+    ///
+    UINT32  JCC:1;
+    ///
+    /// [Bit 3] NEAR_REL_CALL.
+    ///
+    UINT32  NEAR_REL_CALL:1;
+    ///
+    /// [Bit 4] NEAR_IND_CALL.
+    ///
+    UINT32  NEAR_IND_CALL:1;
+    ///
+    /// [Bit 5] NEAR_RET.
+    ///
+    UINT32  NEAR_RET:1;
+    ///
+    /// [Bit 6] NEAR_IND_JMP.
+    ///
+    UINT32  NEAR_IND_JMP:1;
+    ///
+    /// [Bit 7] NEAR_REL_JMP.
+    ///
+    UINT32  NEAR_REL_JMP:1;
+    ///
+    /// [Bit 8] FAR_BRANCH.
+    ///
+    UINT32  FAR_BRANCH:1;
+    ///
+    /// [Bit 9] EN_CALL_STACK.
+    ///
+    UINT32  EN_CALL_STACK:1;
+    UINT32  Reserved1:22;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_LBR_SELECT_REGISTER;
+
+
+/**
+  Core. Last Branch Record Stack TOS (R/W)  Contains an index (bits 0-4) that
+  points to the MSR containing the most recent branch record. See
+  MSR_LASTBRANCH_0_FROM_IP.
+
+  @param  ECX  MSR_GOLDMONT_LASTBRANCH_TOS (0x000001C9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_GOLDMONT_LASTBRANCH_TOS);
+  AsmWriteMsr64 (MSR_GOLDMONT_LASTBRANCH_TOS, Msr);
+  @endcode
+  @note MSR_GOLDMONT_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
+**/
+#define MSR_GOLDMONT_LASTBRANCH_TOS              0x000001C9
+
+
+/**
+  Core. Power Control Register. See http://biosbits.org.
+
+  @param  ECX  MSR_GOLDMONT_POWER_CTL (0x000001FC)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_POWER_CTL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_POWER_CTL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_POWER_CTL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_POWER_CTL);
+  AsmWriteMsr64 (MSR_GOLDMONT_POWER_CTL, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_POWER_CTL is defined as MSR_POWER_CTL in SDM.
+**/
+#define MSR_GOLDMONT_POWER_CTL                   0x000001FC
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_POWER_CTL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 1] Package. C1E Enable (R/W)  When set to '1', will enable the
+    /// CPU to switch to the Minimum Enhanced Intel SpeedStep Technology
+    /// operating point when all execution cores enter MWAIT (C1).
+    ///
+    UINT32  C1EEnable:1;
+    UINT32  Reserved2:30;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_POWER_CTL_REGISTER;
+
+
+/**
+  Package. Lower 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update
+  CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in
+  the package. Lower 64 bits of an 128-bit external entropy value for key
+  derivation of an enclave.
+
+  @param  ECX  MSR_GOLDMONT_SGXOWNEREPOCH0 (0x00000300)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_GOLDMONT_SGXOWNEREPOCH0);
+  @endcode
+  @note MSR_GOLDMONT_SGXOWNEREPOCH0 is defined as MSR_SGXOWNEREPOCH0 in SDM.
+**/
+#define MSR_GOLDMONT_SGXOWNEREPOCH0                   0x00000300
+
+
+//
+// Define MSR_GOLDMONT_SGXOWNER0 for compatibility due to name change in the SDM.
+//
+#define MSR_GOLDMONT_SGXOWNER0                        MSR_GOLDMONT_SGXOWNEREPOCH0
+
+
+/**
+  Package. Upper 64 Bit OwnerEpoch Component of SGX Key (RO). Upper 64 bits of
+  an 128-bit external entropy value for key derivation of an enclave.
+
+  @param  ECX  MSR_GOLDMONT_SGXOWNEREPOCH1 (0x00000301)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_GOLDMONT_SGXOWNEREPOCH1);
+  @endcode
+  @note MSR_GOLDMONT_SGXOWNEREPOCH1 is defined as MSR_SGXOWNEREPOCH1 in SDM.
+**/
+#define MSR_GOLDMONT_SGXOWNEREPOCH1                   0x00000301
+
+
+//
+// Define MSR_GOLDMONT_SGXOWNER1 for compatibility due to name change in the SDM.
+//
+#define MSR_GOLDMONT_SGXOWNER1                        MSR_GOLDMONT_SGXOWNEREPOCH1
+
+
+/**
+  Core. See Table 2-2. See Section 18.2.4, "Architectural Performance
+  Monitoring Version 4.".
+
+  @param  ECX  MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET);
+  AsmWriteMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.
+**/
+#define MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390
+
+/**
+  MSR information returned for MSR index
+  #MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Set 1 to clear Ovf_PMC0.
+    ///
+    UINT32  Ovf_PMC0:1;
+    ///
+    /// [Bit 1] Set 1 to clear Ovf_PMC1.
+    ///
+    UINT32  Ovf_PMC1:1;
+    ///
+    /// [Bit 2] Set 1 to clear Ovf_PMC2.
+    ///
+    UINT32  Ovf_PMC2:1;
+    ///
+    /// [Bit 3] Set 1 to clear Ovf_PMC3.
+    ///
+    UINT32  Ovf_PMC3:1;
+    UINT32  Reserved1:28;
+    ///
+    /// [Bit 32] Set 1 to clear Ovf_FixedCtr0.
+    ///
+    UINT32  Ovf_FixedCtr0:1;
+    ///
+    /// [Bit 33] Set 1 to clear Ovf_FixedCtr1.
+    ///
+    UINT32  Ovf_FixedCtr1:1;
+    ///
+    /// [Bit 34] Set 1 to clear Ovf_FixedCtr2.
+    ///
+    UINT32  Ovf_FixedCtr2:1;
+    UINT32  Reserved2:20;
+    ///
+    /// [Bit 55] Set 1 to clear Trace_ToPA_PMI.
+    ///
+    UINT32  Trace_ToPA_PMI:1;
+    UINT32  Reserved3:2;
+    ///
+    /// [Bit 58] Set 1 to clear LBR_Frz.
+    ///
+    UINT32  LBR_Frz:1;
+    ///
+    /// [Bit 59] Set 1 to clear CTR_Frz.
+    ///
+    UINT32  CTR_Frz:1;
+    ///
+    /// [Bit 60] Set 1 to clear ASCI.
+    ///
+    UINT32  ASCI:1;
+    ///
+    /// [Bit 61] Set 1 to clear Ovf_Uncore.
+    ///
+    UINT32  Ovf_Uncore:1;
+    ///
+    /// [Bit 62] Set 1 to clear Ovf_BufDSSAVE.
+    ///
+    UINT32  Ovf_BufDSSAVE:1;
+    ///
+    /// [Bit 63] Set 1 to clear CondChgd.
+    ///
+    UINT32  CondChgd:1;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER;
+
+
+/**
+  Core. See Table 2-2. See Section 18.2.4, "Architectural Performance
+  Monitoring Version 4.".
+
+  @param  ECX  MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET);
+  AsmWriteMsr64 (MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.
+**/
+#define MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET 0x00000391
+
+/**
+  MSR information returned for MSR index
+  #MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Set 1 to cause Ovf_PMC0 = 1.
+    ///
+    UINT32  Ovf_PMC0:1;
+    ///
+    /// [Bit 1] Set 1 to cause Ovf_PMC1 = 1.
+    ///
+    UINT32  Ovf_PMC1:1;
+    ///
+    /// [Bit 2] Set 1 to cause Ovf_PMC2 = 1.
+    ///
+    UINT32  Ovf_PMC2:1;
+    ///
+    /// [Bit 3] Set 1 to cause Ovf_PMC3 = 1.
+    ///
+    UINT32  Ovf_PMC3:1;
+    UINT32  Reserved1:28;
+    ///
+    /// [Bit 32] Set 1 to cause Ovf_FixedCtr0 = 1.
+    ///
+    UINT32  Ovf_FixedCtr0:1;
+    ///
+    /// [Bit 33] Set 1 to cause Ovf_FixedCtr1 = 1.
+    ///
+    UINT32  Ovf_FixedCtr1:1;
+    ///
+    /// [Bit 34] Set 1 to cause Ovf_FixedCtr2 = 1.
+    ///
+    UINT32  Ovf_FixedCtr2:1;
+    UINT32  Reserved2:20;
+    ///
+    /// [Bit 55] Set 1 to cause Trace_ToPA_PMI = 1.
+    ///
+    UINT32  Trace_ToPA_PMI:1;
+    UINT32  Reserved3:2;
+    ///
+    /// [Bit 58] Set 1 to cause LBR_Frz = 1.
+    ///
+    UINT32  LBR_Frz:1;
+    ///
+    /// [Bit 59] Set 1 to cause CTR_Frz = 1.
+    ///
+    UINT32  CTR_Frz:1;
+    ///
+    /// [Bit 60] Set 1 to cause ASCI = 1.
+    ///
+    UINT32  ASCI:1;
+    ///
+    /// [Bit 61] Set 1 to cause Ovf_Uncore.
+    ///
+    UINT32  Ovf_Uncore:1;
+    ///
+    /// [Bit 62] Set 1 to cause Ovf_BufDSSAVE.
+    ///
+    UINT32  Ovf_BufDSSAVE:1;
+    UINT32  Reserved4:1;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER;
+
+
+/**
+  Core. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling
+  (PEBS).".
+
+  @param  ECX  MSR_GOLDMONT_PEBS_ENABLE (0x000003F1)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_PEBS_ENABLE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_PEBS_ENABLE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_PEBS_ENABLE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PEBS_ENABLE);
+  AsmWriteMsr64 (MSR_GOLDMONT_PEBS_ENABLE, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
+**/
+#define MSR_GOLDMONT_PEBS_ENABLE                 0x000003F1
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_PEBS_ENABLE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Enable PEBS trigger and recording for the programmed event
+    /// (precise or otherwise) on IA32_PMC0. (R/W).
+    ///
+    UINT32  Enable:1;
+    UINT32  Reserved1:31;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_PEBS_ENABLE_REGISTER;
+
+
+/**
+  Package. Note: C-state values are processor specific C-state code names,
+  unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3
+  Residency Counter. (R/O) Value since last reset that this package is in
+  processor-specific C3 states. Count at the same frequency as the TSC.
+
+  @param  ECX  MSR_GOLDMONT_PKG_C3_RESIDENCY (0x000003F8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C3_RESIDENCY);
+  AsmWriteMsr64 (MSR_GOLDMONT_PKG_C3_RESIDENCY, Msr);
+  @endcode
+  @note MSR_GOLDMONT_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.
+**/
+#define MSR_GOLDMONT_PKG_C3_RESIDENCY            0x000003F8
+
+
+/**
+  Package. Note: C-state values are processor specific C-state code names,
+  unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6
+  Residency Counter. (R/O) Value since last reset that this package is in
+  processor-specific C6 states. Count at the same frequency as the TSC.
+
+  @param  ECX  MSR_GOLDMONT_PKG_C6_RESIDENCY (0x000003F9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C6_RESIDENCY);
+  AsmWriteMsr64 (MSR_GOLDMONT_PKG_C6_RESIDENCY, Msr);
+  @endcode
+  @note MSR_GOLDMONT_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
+**/
+#define MSR_GOLDMONT_PKG_C6_RESIDENCY            0x000003F9
+
+
+/**
+  Core. Note: C-state values are processor specific C-state code names,
+  unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3
+  Residency Counter. (R/O) Value since last reset that this core is in
+  processor-specific C3 states. Count at the same frequency as the TSC.
+
+  @param  ECX  MSR_GOLDMONT_CORE_C3_RESIDENCY (0x000003FC)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_GOLDMONT_CORE_C3_RESIDENCY);
+  AsmWriteMsr64 (MSR_GOLDMONT_CORE_C3_RESIDENCY, Msr);
+  @endcode
+  @note MSR_GOLDMONT_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM.
+**/
+#define MSR_GOLDMONT_CORE_C3_RESIDENCY           0x000003FC
+
+
+/**
+  Package. Enhanced SMM Feature Control (SMM-RW) Reports SMM capability
+  Enhancement. Accessible only while in SMM.
+
+  @param  ECX  MSR_GOLDMONT_SMM_FEATURE_CONTROL (0x000004E0)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_FEATURE_CONTROL);
+  AsmWriteMsr64 (MSR_GOLDMONT_SMM_FEATURE_CONTROL, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_SMM_FEATURE_CONTROL is defined as MSR_SMM_FEATURE_CONTROL in SDM.
+**/
+#define MSR_GOLDMONT_SMM_FEATURE_CONTROL         0x000004E0
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_SMM_FEATURE_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Lock (SMM-RWO) When set to '1' locks this register from
+    /// further changes.
+    ///
+    UINT32  Lock:1;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 2] SMM_Code_Chk_En (SMM-RW) This control bit is available only if
+    /// MSR_SMM_MCA_CAP[58] == 1. When set to '0' (default) none of the
+    /// logical processors are prevented from executing SMM code outside the
+    /// ranges defined by the SMRR. When set to '1' any logical processor in
+    /// the package that attempts to execute SMM code not within the ranges
+    /// defined by the SMRR will assert an unrecoverable MCE.
+    ///
+    UINT32  SMM_Code_Chk_En:1;
+    UINT32  Reserved2:29;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER;
+
+
+/**
+  Package. SMM Delayed (SMM-RO) Reports the interruptible state of all logical
+  processors in the package. Available only while in SMM and
+  MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] == 1.
+
+  @param  ECX  MSR_GOLDMONT_SMM_DELAYED (0x000004E2)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_SMM_DELAYED_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_SMM_DELAYED_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_SMM_DELAYED_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_DELAYED);
+  AsmWriteMsr64 (MSR_GOLDMONT_SMM_DELAYED, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_SMM_DELAYED is defined as MSR_SMM_DELAYED in SDM.
+**/
+#define MSR_GOLDMONT_SMM_DELAYED                 0x000004E2
+
+
+/**
+  Package. SMM Blocked (SMM-RO) Reports the blocked state of all logical
+  processors in the package. Available only while in SMM.
+
+  @param  ECX  MSR_GOLDMONT_SMM_BLOCKED (0x000004E3)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_SMM_BLOCKED_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_SMM_BLOCKED_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_SMM_BLOCKED_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_SMM_BLOCKED);
+  AsmWriteMsr64 (MSR_GOLDMONT_SMM_BLOCKED, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_SMM_BLOCKED is defined as MSR_SMM_BLOCKED in SDM.
+**/
+#define MSR_GOLDMONT_SMM_BLOCKED                 0x000004E3
+
+
+/**
+  Core. Trace Control Register (R/W).
+
+  @param  ECX  MSR_GOLDMONT_IA32_RTIT_CTL (0x00000570)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_RTIT_CTL);
+  AsmWriteMsr64 (MSR_GOLDMONT_IA32_RTIT_CTL, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_IA32_RTIT_CTL is defined as IA32_RTIT_CTL in SDM.
+**/
+#define MSR_IA32_RTIT_CTL                        0x00000570
+
+/**
+  MSR information returned for MSR index #MSR_IA32_RTIT_CTL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] TraceEn.
+    ///
+    UINT32  TraceEn:1;
+    ///
+    /// [Bit 1] CYCEn.
+    ///
+    UINT32  CYCEn:1;
+    ///
+    /// [Bit 2] OS.
+    ///
+    UINT32  OS:1;
+    ///
+    /// [Bit 3] User.
+    ///
+    UINT32  User:1;
+    UINT32  Reserved1:3;
+    ///
+    /// [Bit 7] CR3 filter.
+    ///
+    UINT32  CR3:1;
+    ///
+    /// [Bit 8] ToPA. Writing 0 will #GP if also setting TraceEn.
+    ///
+    UINT32  ToPA:1;
+    ///
+    /// [Bit 9] MTCEn.
+    ///
+    UINT32  MTCEn:1;
+    ///
+    /// [Bit 10] TSCEn.
+    ///
+    UINT32  TSCEn:1;
+    ///
+    /// [Bit 11] DisRETC.
+    ///
+    UINT32  DisRETC:1;
+    UINT32  Reserved2:1;
+    ///
+    /// [Bit 13] BranchEn.
+    ///
+    UINT32  BranchEn:1;
+    ///
+    /// [Bits 17:14] MTCFreq.
+    ///
+    UINT32  MTCFreq:4;
+    UINT32  Reserved3:1;
+    ///
+    /// [Bits 22:19] CYCThresh.
+    ///
+    UINT32  CYCThresh:4;
+    UINT32  Reserved4:1;
+    ///
+    /// [Bits 27:24] PSBFreq.
+    ///
+    UINT32  PSBFreq:4;
+    UINT32  Reserved5:4;
+    ///
+    /// [Bits 35:32] ADDR0_CFG.
+    ///
+    UINT32  ADDR0_CFG:4;
+    ///
+    /// [Bits 39:36] ADDR1_CFG.
+    ///
+    UINT32  ADDR1_CFG:4;
+    UINT32  Reserved6:24;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER;
+
+
+/**
+  Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1,
+  "RAPL Interfaces.".
+
+  @param  ECX  MSR_GOLDMONT_RAPL_POWER_UNIT (0x00000606)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_RAPL_POWER_UNIT);
+  @endcode
+  @note MSR_GOLDMONT_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
+**/
+#define MSR_GOLDMONT_RAPL_POWER_UNIT             0x00000606
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_RAPL_POWER_UNIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 3:0] Power Units. Power related information (in Watts) is in
+    /// unit of, 1W/2^PU; where PU is an unsigned integer represented by bits
+    /// 3:0. Default value is 1000b, indicating power unit is in 3.9
+    /// milliWatts increment.
+    ///
+    UINT32  PowerUnits:4;
+    UINT32  Reserved1:4;
+    ///
+    /// [Bits 12:8] Energy Status Units. Energy related information (in
+    /// Joules) is in unit of, 1Joule/ (2^ESU); where ESU is an unsigned
+    /// integer represented by bits 12:8. Default value is 01110b, indicating
+    /// energy unit is in 61 microJoules.
+    ///
+    UINT32  EnergyStatusUnits:5;
+    UINT32  Reserved2:3;
+    ///
+    /// [Bits 19:16] Time Unit. Time related information (in seconds) is in
+    /// unit of, 1S/2^TU; where TU is an unsigned integer represented by bits
+    /// 19:16. Default value is 1010b, indicating power unit is in 0.977
+    /// millisecond.
+    ///
+    UINT32  TimeUnit:4;
+    UINT32  Reserved3:12;
+    UINT32  Reserved4:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER;
+
+
+/**
+  Package. Package C3 Interrupt Response Limit (R/W)  Note: C-state values are
+  processor specific C-state code names, unrelated to MWAIT extension C-state
+  parameters or ACPI CStates.
+
+  @param  ECX  MSR_GOLDMONT_PKGC3_IRTL (0x0000060A)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_PKGC3_IRTL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_PKGC3_IRTL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_PKGC3_IRTL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKGC3_IRTL);
+  AsmWriteMsr64 (MSR_GOLDMONT_PKGC3_IRTL, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_PKGC3_IRTL is defined as MSR_PKGC3_IRTL in SDM.
+**/
+#define MSR_GOLDMONT_PKGC3_IRTL                  0x0000060A
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_PKGC3_IRTL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 9:0] Interrupt response time limit (R/W)  Specifies the limit
+    /// that should be used to decide if the package should be put into a
+    /// package C3 state.
+    ///
+    UINT32  InterruptResponseTimeLimit:10;
+    ///
+    /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit
+    /// of the interrupt response time limit. See Table 2-19 for supported
+    /// time unit encodings.
+    ///
+    UINT32  TimeUnit:3;
+    UINT32  Reserved1:2;
+    ///
+    /// [Bit 15] Valid (R/W)  Indicates whether the values in bits 12:0 are
+    /// valid and can be used by the processor for package C-sate management.
+    ///
+    UINT32  Valid:1;
+    UINT32  Reserved2:16;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_PKGC3_IRTL_REGISTER;
+
+
+/**
+  Package. Package C6/C7S Interrupt Response Limit 1 (R/W)  This MSR defines
+  the interrupt response time limit used by the processor to manage transition
+  to package C6 or C7S state. Note: C-state values are processor specific
+  C-state code names, unrelated to MWAIT extension C-state parameters or ACPI
+  CStates.
+
+  @param  ECX  MSR_GOLDMONT_PKGC_IRTL1 (0x0000060B)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_PKGC_IRTL1_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_PKGC_IRTL1_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_PKGC_IRTL1_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKGC_IRTL1);
+  AsmWriteMsr64 (MSR_GOLDMONT_PKGC_IRTL1, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_PKGC_IRTL1 is defined as MSR_PKGC_IRTL1 in SDM.
+**/
+#define MSR_GOLDMONT_PKGC_IRTL1                  0x0000060B
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_PKGC_IRTL1
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 9:0] Interrupt response time limit (R/W)  Specifies the limit
+    /// that should be used to decide if the package should be put into a
+    /// package C6 or C7S state.
+    ///
+    UINT32  InterruptResponseTimeLimit:10;
+    ///
+    /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit
+    /// of the interrupt response time limit. See Table 2-19 for supported
+    /// time unit encodings.
+    ///
+    UINT32  TimeUnit:3;
+    UINT32  Reserved1:2;
+    ///
+    /// [Bit 15] Valid (R/W)  Indicates whether the values in bits 12:0 are
+    /// valid and can be used by the processor for package C-sate management.
+    ///
+    UINT32  Valid:1;
+    UINT32  Reserved2:16;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_PKGC_IRTL1_REGISTER;
+
+
+/**
+  Package. Package C7 Interrupt Response Limit 2 (R/W)  This MSR defines the
+  interrupt response time limit used by the processor to manage transition to
+  package C7 state. Note: C-state values are processor specific C-state code
+  names, unrelated to MWAIT extension C-state parameters or ACPI CStates.
+
+  @param  ECX  MSR_GOLDMONT_PKGC_IRTL2 (0x0000060C)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_PKGC_IRTL2_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_PKGC_IRTL2_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_PKGC_IRTL2_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKGC_IRTL2);
+  AsmWriteMsr64 (MSR_GOLDMONT_PKGC_IRTL2, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_PKGC_IRTL2 is defined as MSR_PKGC_IRTL2 in SDM.
+**/
+#define MSR_GOLDMONT_PKGC_IRTL2                  0x0000060C
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_PKGC_IRTL2
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 9:0] Interrupt response time limit (R/W)  Specifies the limit
+    /// that should be used to decide if the package should be put into a
+    /// package C7 state.
+    ///
+    UINT32  InterruptResponseTimeLimit:10;
+    ///
+    /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit
+    /// of the interrupt response time limit. See Table 2-19 for supported
+    /// time unit encodings.
+    ///
+    UINT32  TimeUnit:3;
+    UINT32  Reserved1:2;
+    ///
+    /// [Bit 15] Valid (R/W)  Indicates whether the values in bits 12:0 are
+    /// valid and can be used by the processor for package C-sate management.
+    ///
+    UINT32  Valid:1;
+    UINT32  Reserved2:16;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_PKGC_IRTL2_REGISTER;
+
+
+/**
+  Package. Note: C-state values are processor specific C-state code names,
+  unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C2
+  Residency Counter. (R/O) Value since last reset that this package is in
+  processor-specific C2 states. Count at the same frequency as the TSC.
+
+  @param  ECX  MSR_GOLDMONT_PKG_C2_RESIDENCY (0x0000060D)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C2_RESIDENCY);
+  AsmWriteMsr64 (MSR_GOLDMONT_PKG_C2_RESIDENCY, Msr);
+  @endcode
+  @note MSR_GOLDMONT_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.
+**/
+#define MSR_GOLDMONT_PKG_C2_RESIDENCY            0x0000060D
+
+
+/**
+  Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package
+  RAPL Domain.".
+
+  @param  ECX  MSR_GOLDMONT_PKG_POWER_LIMIT (0x00000610)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_POWER_LIMIT);
+  AsmWriteMsr64 (MSR_GOLDMONT_PKG_POWER_LIMIT, Msr);
+  @endcode
+  @note MSR_GOLDMONT_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.
+**/
+#define MSR_GOLDMONT_PKG_POWER_LIMIT             0x00000610
+
+
+/**
+  Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
+
+  @param  ECX  MSR_GOLDMONT_PKG_ENERGY_STATUS (0x00000611)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_ENERGY_STATUS);
+  @endcode
+  @note MSR_GOLDMONT_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.
+**/
+#define MSR_GOLDMONT_PKG_ENERGY_STATUS           0x00000611
+
+
+/**
+  Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
+
+  @param  ECX  MSR_GOLDMONT_PKG_PERF_STATUS (0x00000613)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_PERF_STATUS);
+  @endcode
+  @note MSR_GOLDMONT_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.
+**/
+#define MSR_GOLDMONT_PKG_PERF_STATUS             0x00000613
+
+
+/**
+  Package. PKG RAPL Parameters (R/W).
+
+  @param  ECX  MSR_GOLDMONT_PKG_POWER_INFO (0x00000614)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_PKG_POWER_INFO_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_PKG_POWER_INFO_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_PKG_POWER_INFO_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PKG_POWER_INFO);
+  AsmWriteMsr64 (MSR_GOLDMONT_PKG_POWER_INFO, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.
+**/
+#define MSR_GOLDMONT_PKG_POWER_INFO              0x00000614
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_PKG_POWER_INFO
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 14:0] Thermal Spec Power (R/W)  See Section 14.9.3, "Package
+    /// RAPL Domain.".
+    ///
+    UINT32  ThermalSpecPower:15;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bits 30:16] Minimum Power (R/W)  See Section 14.9.3, "Package RAPL
+    /// Domain.".
+    ///
+    UINT32  MinimumPower:15;
+    UINT32  Reserved2:1;
+    ///
+    /// [Bits 46:32] Maximum Power (R/W)  See Section 14.9.3, "Package RAPL
+    /// Domain.".
+    ///
+    UINT32  MaximumPower:15;
+    UINT32  Reserved3:1;
+    ///
+    /// [Bits 54:48] Maximum Time Window (R/W)  Specified by 2^Y * (1.0 +
+    /// Z/4.0) * Time_Unit, where "Y" is the unsigned integer value
+    /// represented. by bits 52:48, "Z" is an unsigned integer represented by
+    /// bits 54:53. "Time_Unit" is specified by the "Time Units" field of
+    /// MSR_RAPL_POWER_UNIT.
+    ///
+    UINT32  MaximumTimeWindow:7;
+    UINT32  Reserved4:9;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_PKG_POWER_INFO_REGISTER;
+
+
+/**
+  Package. DRAM RAPL Power Limit Control (R/W)  See Section 14.9.5, "DRAM RAPL
+  Domain.".
+
+  @param  ECX  MSR_GOLDMONT_DRAM_POWER_LIMIT (0x00000618)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_POWER_LIMIT);
+  AsmWriteMsr64 (MSR_GOLDMONT_DRAM_POWER_LIMIT, Msr);
+  @endcode
+  @note MSR_GOLDMONT_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
+**/
+#define MSR_GOLDMONT_DRAM_POWER_LIMIT            0x00000618
+
+
+/**
+  Package. DRAM Energy Status (R/O)  See Section 14.9.5, "DRAM RAPL Domain.".
+
+  @param  ECX  MSR_GOLDMONT_DRAM_ENERGY_STATUS (0x00000619)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_ENERGY_STATUS);
+  @endcode
+  @note MSR_GOLDMONT_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
+**/
+#define MSR_GOLDMONT_DRAM_ENERGY_STATUS          0x00000619
+
+
+/**
+  Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
+  RAPL Domain.".
+
+  @param  ECX  MSR_GOLDMONT_DRAM_PERF_STATUS (0x0000061B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_PERF_STATUS);
+  @endcode
+  @note MSR_GOLDMONT_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
+**/
+#define MSR_GOLDMONT_DRAM_PERF_STATUS            0x0000061B
+
+
+/**
+  Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
+
+  @param  ECX  MSR_GOLDMONT_DRAM_POWER_INFO (0x0000061C)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_GOLDMONT_DRAM_POWER_INFO);
+  AsmWriteMsr64 (MSR_GOLDMONT_DRAM_POWER_INFO, Msr);
+  @endcode
+  @note MSR_GOLDMONT_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
+**/
+#define MSR_GOLDMONT_DRAM_POWER_INFO             0x0000061C
+
+
+/**
+  Package. Note: C-state values are processor specific C-state code names,.
+  Package C10 Residency Counter. (R/O) Value since last reset that the entire
+  SOC is in an S0i3 state. Count at the same frequency as the TSC.
+
+  @param  ECX  MSR_GOLDMONT_PKG_C10_RESIDENCY (0x00000632)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_GOLDMONT_PKG_C10_RESIDENCY);
+  AsmWriteMsr64 (MSR_GOLDMONT_PKG_C10_RESIDENCY, Msr);
+  @endcode
+  @note MSR_GOLDMONT_PKG_C10_RESIDENCY is defined as MSR_PKG_C10_RESIDENCY in SDM.
+**/
+#define MSR_GOLDMONT_PKG_C10_RESIDENCY           0x00000632
+
+
+/**
+  Package. PP0 Energy Status (R/O)  See Section 14.9.4, "PP0/PP1 RAPL
+  Domains.".
+
+  @param  ECX  MSR_GOLDMONT_PP0_ENERGY_STATUS (0x00000639)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_GOLDMONT_PP0_ENERGY_STATUS);
+  @endcode
+  @note MSR_GOLDMONT_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
+**/
+#define MSR_GOLDMONT_PP0_ENERGY_STATUS           0x00000639
+
+
+/**
+  Package. PP1 Energy Status (R/O)  See Section 14.9.4, "PP0/PP1 RAPL
+  Domains.".
+
+  @param  ECX  MSR_GOLDMONT_PP1_ENERGY_STATUS (0x00000641)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_GOLDMONT_PP1_ENERGY_STATUS);
+  @endcode
+  @note MSR_GOLDMONT_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM.
+**/
+#define MSR_GOLDMONT_PP1_ENERGY_STATUS           0x00000641
+
+
+/**
+  Package. ConfigTDP Control (R/W).
+
+  @param  ECX  MSR_GOLDMONT_TURBO_ACTIVATION_RATIO (0x0000064C)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_TURBO_ACTIVATION_RATIO);
+  AsmWriteMsr64 (MSR_GOLDMONT_TURBO_ACTIVATION_RATIO, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.
+**/
+#define MSR_GOLDMONT_TURBO_ACTIVATION_RATIO      0x0000064C
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_TURBO_ACTIVATION_RATIO
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this
+    /// field.
+    ///
+    UINT32  MAX_NON_TURBO_RATIO:8;
+    UINT32  Reserved1:23;
+    ///
+    /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the
+    /// content of this register is locked until a reset.
+    ///
+    UINT32  TURBO_ACTIVATION_RATIO_Lock:1;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER;
+
+
+/**
+  Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
+  refers to processor core frequency).
+
+  @param  ECX  MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS (0x0000064F)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS);
+  AsmWriteMsr64 (MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
+**/
+#define MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS     0x0000064F
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is
+    /// reduced below the operating system request due to assertion of
+    /// external PROCHOT.
+    ///
+    UINT32  PROCHOTStatus:1;
+    ///
+    /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
+    /// operating system request due to a thermal event.
+    ///
+    UINT32  ThermalStatus:1;
+    ///
+    /// [Bit 2] Package-Level Power Limiting PL1 Status (R0) When set,
+    /// frequency is reduced below the operating system request due to
+    /// package-level power limiting PL1.
+    ///
+    UINT32  PL1Status:1;
+    ///
+    /// [Bit 3] Package-Level PL2 Power Limiting Status (R0) When set,
+    /// frequency is reduced below the operating system request due to
+    /// package-level power limiting PL2.
+    ///
+    UINT32  PL2Status:1;
+    UINT32  Reserved1:5;
+    ///
+    /// [Bit 9] Core Power Limiting Status (R0) When set, frequency is reduced
+    /// below the operating system request due to domain-level power limiting.
+    ///
+    UINT32  PowerLimitingStatus:1;
+    ///
+    /// [Bit 10] VR Therm Alert Status (R0) When set, frequency is reduced
+    /// below the operating system request due to a thermal alert from the
+    /// Voltage Regulator.
+    ///
+    UINT32  VRThermAlertStatus:1;
+    ///
+    /// [Bit 11] Max Turbo Limit Status (R0) When set, frequency is reduced
+    /// below the operating system request due to multi-core turbo limits.
+    ///
+    UINT32  MaxTurboLimitStatus:1;
+    ///
+    /// [Bit 12] Electrical Design Point Status (R0) When set, frequency is
+    /// reduced below the operating system request due to electrical design
+    /// point constraints (e.g. maximum electrical current consumption).
+    ///
+    UINT32  ElectricalDesignPointStatus:1;
+    ///
+    /// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency
+    /// is reduced below the operating system request due to Turbo transition
+    /// attenuation. This prevents performance degradation due to frequent
+    /// operating ratio changes.
+    ///
+    UINT32  TurboTransitionAttenuationStatus:1;
+    ///
+    /// [Bit 14] Maximum Efficiency Frequency Status (R0) When set, frequency
+    /// is reduced below the maximum efficiency frequency.
+    ///
+    UINT32  MaximumEfficiencyFrequencyStatus:1;
+    UINT32  Reserved2:1;
+    ///
+    /// [Bit 16] PROCHOT Log  When set, indicates that the PROCHOT Status bit
+    /// has asserted since the log bit was last cleared. This log bit will
+    /// remain set until cleared by software writing 0.
+    ///
+    UINT32  PROCHOT:1;
+    ///
+    /// [Bit 17] Thermal Log  When set, indicates that the Thermal Status bit
+    /// has asserted since the log bit was last cleared. This log bit will
+    /// remain set until cleared by software writing 0.
+    ///
+    UINT32  ThermalLog:1;
+    ///
+    /// [Bit 18] Package-Level PL1 Power Limiting Log  When set, indicates
+    /// that the Package Level PL1 Power Limiting Status bit has asserted
+    /// since the log bit was last cleared. This log bit will remain set until
+    /// cleared by software writing 0.
+    ///
+    UINT32  PL1Log:1;
+    ///
+    /// [Bit 19] Package-Level PL2 Power Limiting Log When set, indicates that
+    /// the Package Level PL2 Power Limiting Status bit has asserted since the
+    /// log bit was last cleared. This log bit will remain set until cleared
+    /// by software writing 0.
+    ///
+    UINT32  PL2Log:1;
+    UINT32  Reserved3:5;
+    ///
+    /// [Bit 25] Core Power Limiting Log  When set, indicates that the Core
+    /// Power Limiting Status bit has asserted since the log bit was last
+    /// cleared. This log bit will remain set until cleared by software
+    /// writing 0.
+    ///
+    UINT32  CorePowerLimitingLog:1;
+    ///
+    /// [Bit 26] VR Therm Alert Log  When set, indicates that the VR Therm
+    /// Alert Status bit has asserted since the log bit was last cleared. This
+    /// log bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  VRThermAlertLog:1;
+    ///
+    /// [Bit 27] Max Turbo Limit Log When set, indicates that the Max Turbo
+    /// Limit Status bit has asserted since the log bit was last cleared. This
+    /// log bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  MaxTurboLimitLog:1;
+    ///
+    /// [Bit 28] Electrical Design Point Log  When set, indicates that the EDP
+    /// Status bit has asserted since the log bit was last cleared. This log
+    /// bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  ElectricalDesignPointLog:1;
+    ///
+    /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the
+    /// Turbo Transition Attenuation Status bit has asserted since the log bit
+    /// was last cleared. This log bit will remain set until cleared by
+    /// software writing 0.
+    ///
+    UINT32  TurboTransitionAttenuationLog:1;
+    ///
+    /// [Bit 30] Maximum Efficiency Frequency Log  When set, indicates that
+    /// the Maximum Efficiency Frequency Status bit has asserted since the log
+    /// bit was last cleared. This log bit will remain set until cleared by
+    /// software writing 0.
+    ///
+    UINT32  MaximumEfficiencyFrequencyLog:1;
+    UINT32  Reserved4:1;
+    UINT32  Reserved5:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER;
+
+
+/**
+  Core. Last Branch Record n From IP (R/W) One of 32 pairs of last branch
+  record registers on the last branch record stack. The From_IP part of the
+  stack contains pointers to the source instruction . See also: -  Last Branch
+  Record Stack TOS at 1C9H -  Section 17.6 and record format in Section
+  17.4.8.1.
+
+  @param  ECX  MSR_GOLDMONT_LASTBRANCH_n_FROM_IP
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_LASTBRANCH_n_FROM_IP);
+  AsmWriteMsr64 (MSR_GOLDMONT_LASTBRANCH_n_FROM_IP, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_LASTBRANCH_0_FROM_IP  is defined as MSR_LASTBRANCH_0_FROM_IP  in SDM.
+        MSR_GOLDMONT_LASTBRANCH_1_FROM_IP  is defined as MSR_LASTBRANCH_1_FROM_IP  in SDM.
+        MSR_GOLDMONT_LASTBRANCH_2_FROM_IP  is defined as MSR_LASTBRANCH_2_FROM_IP  in SDM.
+        MSR_GOLDMONT_LASTBRANCH_3_FROM_IP  is defined as MSR_LASTBRANCH_3_FROM_IP  in SDM.
+        MSR_GOLDMONT_LASTBRANCH_4_FROM_IP  is defined as MSR_LASTBRANCH_4_FROM_IP  in SDM.
+        MSR_GOLDMONT_LASTBRANCH_5_FROM_IP  is defined as MSR_LASTBRANCH_5_FROM_IP  in SDM.
+        MSR_GOLDMONT_LASTBRANCH_6_FROM_IP  is defined as MSR_LASTBRANCH_6_FROM_IP  in SDM.
+        MSR_GOLDMONT_LASTBRANCH_7_FROM_IP  is defined as MSR_LASTBRANCH_7_FROM_IP  in SDM.
+        MSR_GOLDMONT_LASTBRANCH_8_FROM_IP  is defined as MSR_LASTBRANCH_8_FROM_IP  in SDM.
+        MSR_GOLDMONT_LASTBRANCH_9_FROM_IP  is defined as MSR_LASTBRANCH_9_FROM_IP  in SDM.
+        MSR_GOLDMONT_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_16_FROM_IP is defined as MSR_LASTBRANCH_16_FROM_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_17_FROM_IP is defined as MSR_LASTBRANCH_17_FROM_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_18_FROM_IP is defined as MSR_LASTBRANCH_18_FROM_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_19_FROM_IP is defined as MSR_LASTBRANCH_19_FROM_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_20_FROM_IP is defined as MSR_LASTBRANCH_20_FROM_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_21_FROM_IP is defined as MSR_LASTBRANCH_21_FROM_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_22_FROM_IP is defined as MSR_LASTBRANCH_22_FROM_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_23_FROM_IP is defined as MSR_LASTBRANCH_23_FROM_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_24_FROM_IP is defined as MSR_LASTBRANCH_24_FROM_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_25_FROM_IP is defined as MSR_LASTBRANCH_25_FROM_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_26_FROM_IP is defined as MSR_LASTBRANCH_26_FROM_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_27_FROM_IP is defined as MSR_LASTBRANCH_27_FROM_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_28_FROM_IP is defined as MSR_LASTBRANCH_28_FROM_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_29_FROM_IP is defined as MSR_LASTBRANCH_29_FROM_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_30_FROM_IP is defined as MSR_LASTBRANCH_30_FROM_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_31_FROM_IP is defined as MSR_LASTBRANCH_31_FROM_IP in SDM.
+  @{
+**/
+#define MSR_GOLDMONT_LASTBRANCH_0_FROM_IP        0x00000680
+#define MSR_GOLDMONT_LASTBRANCH_1_FROM_IP        0x00000681
+#define MSR_GOLDMONT_LASTBRANCH_2_FROM_IP        0x00000682
+#define MSR_GOLDMONT_LASTBRANCH_3_FROM_IP        0x00000683
+#define MSR_GOLDMONT_LASTBRANCH_4_FROM_IP        0x00000684
+#define MSR_GOLDMONT_LASTBRANCH_5_FROM_IP        0x00000685
+#define MSR_GOLDMONT_LASTBRANCH_6_FROM_IP        0x00000686
+#define MSR_GOLDMONT_LASTBRANCH_7_FROM_IP        0x00000687
+#define MSR_GOLDMONT_LASTBRANCH_8_FROM_IP        0x00000688
+#define MSR_GOLDMONT_LASTBRANCH_9_FROM_IP        0x00000689
+#define MSR_GOLDMONT_LASTBRANCH_10_FROM_IP       0x0000068A
+#define MSR_GOLDMONT_LASTBRANCH_11_FROM_IP       0x0000068B
+#define MSR_GOLDMONT_LASTBRANCH_12_FROM_IP       0x0000068C
+#define MSR_GOLDMONT_LASTBRANCH_13_FROM_IP       0x0000068D
+#define MSR_GOLDMONT_LASTBRANCH_14_FROM_IP       0x0000068E
+#define MSR_GOLDMONT_LASTBRANCH_15_FROM_IP       0x0000068F
+#define MSR_GOLDMONT_LASTBRANCH_16_FROM_IP       0x00000690
+#define MSR_GOLDMONT_LASTBRANCH_17_FROM_IP       0x00000691
+#define MSR_GOLDMONT_LASTBRANCH_18_FROM_IP       0x00000692
+#define MSR_GOLDMONT_LASTBRANCH_19_FROM_IP       0x00000693
+#define MSR_GOLDMONT_LASTBRANCH_20_FROM_IP       0x00000694
+#define MSR_GOLDMONT_LASTBRANCH_21_FROM_IP       0x00000695
+#define MSR_GOLDMONT_LASTBRANCH_22_FROM_IP       0x00000696
+#define MSR_GOLDMONT_LASTBRANCH_23_FROM_IP       0x00000697
+#define MSR_GOLDMONT_LASTBRANCH_24_FROM_IP       0x00000698
+#define MSR_GOLDMONT_LASTBRANCH_25_FROM_IP       0x00000699
+#define MSR_GOLDMONT_LASTBRANCH_26_FROM_IP       0x0000069A
+#define MSR_GOLDMONT_LASTBRANCH_27_FROM_IP       0x0000069B
+#define MSR_GOLDMONT_LASTBRANCH_28_FROM_IP       0x0000069C
+#define MSR_GOLDMONT_LASTBRANCH_29_FROM_IP       0x0000069D
+#define MSR_GOLDMONT_LASTBRANCH_30_FROM_IP       0x0000069E
+#define MSR_GOLDMONT_LASTBRANCH_31_FROM_IP       0x0000069F
+/// @}
+
+/**
+  MSR information returned for MSR indexes #MSR_GOLDMONT_LASTBRANCH_0_FROM_IP
+  to #MSR_GOLDMONT_LASTBRANCH_31_FROM_IP.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 31:0] From Linear Address (R/W).
+    ///
+    UINT32  FromLinearAddress:32;
+    ///
+    /// [Bit 47:32] From Linear Address (R/W).
+    ///
+    UINT32  FromLinearAddressHi:16;
+    ///
+    /// [Bits 62:48] Signed extension of bits 47:0.
+    ///
+    UINT32  SignedExtension:15;
+    ///
+    /// [Bit 63] Mispred.
+    ///
+    UINT32  Mispred:1;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER;
+
+
+/**
+  Core. Last Branch Record n To IP (R/W) One of 32 pairs of last branch record
+  registers on the last branch record stack. The To_IP part of the stack
+  contains pointers to the Destination instruction and elapsed cycles from
+  last LBR update. See also: - Section 17.6.
+
+  @param  ECX  MSR_GOLDMONT_LASTBRANCH_n_TO_IP
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_LASTBRANCH_0_TO_IP);
+  AsmWriteMsr64 (MSR_GOLDMONT_LASTBRANCH_0_TO_IP, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_LASTBRANCH_0_TO_IP  is defined as MSR_LASTBRANCH_0_TO_IP  in SDM.
+        MSR_GOLDMONT_LASTBRANCH_1_TO_IP  is defined as MSR_LASTBRANCH_1_TO_IP  in SDM.
+        MSR_GOLDMONT_LASTBRANCH_2_TO_IP  is defined as MSR_LASTBRANCH_2_TO_IP  in SDM.
+        MSR_GOLDMONT_LASTBRANCH_3_TO_IP  is defined as MSR_LASTBRANCH_3_TO_IP  in SDM.
+        MSR_GOLDMONT_LASTBRANCH_4_TO_IP  is defined as MSR_LASTBRANCH_4_TO_IP  in SDM.
+        MSR_GOLDMONT_LASTBRANCH_5_TO_IP  is defined as MSR_LASTBRANCH_5_TO_IP  in SDM.
+        MSR_GOLDMONT_LASTBRANCH_6_TO_IP  is defined as MSR_LASTBRANCH_6_TO_IP  in SDM.
+        MSR_GOLDMONT_LASTBRANCH_7_TO_IP  is defined as MSR_LASTBRANCH_7_TO_IP  in SDM.
+        MSR_GOLDMONT_LASTBRANCH_8_TO_IP  is defined as MSR_LASTBRANCH_8_TO_IP  in SDM.
+        MSR_GOLDMONT_LASTBRANCH_9_TO_IP  is defined as MSR_LASTBRANCH_9_TO_IP  in SDM.
+        MSR_GOLDMONT_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_16_TO_IP is defined as MSR_LASTBRANCH_16_TO_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_17_TO_IP is defined as MSR_LASTBRANCH_17_TO_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_18_TO_IP is defined as MSR_LASTBRANCH_18_TO_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_19_TO_IP is defined as MSR_LASTBRANCH_19_TO_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_20_TO_IP is defined as MSR_LASTBRANCH_20_TO_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_21_TO_IP is defined as MSR_LASTBRANCH_21_TO_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_22_TO_IP is defined as MSR_LASTBRANCH_22_TO_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_23_TO_IP is defined as MSR_LASTBRANCH_23_TO_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_24_TO_IP is defined as MSR_LASTBRANCH_24_TO_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_25_TO_IP is defined as MSR_LASTBRANCH_25_TO_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_26_TO_IP is defined as MSR_LASTBRANCH_26_TO_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_27_TO_IP is defined as MSR_LASTBRANCH_27_TO_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_28_TO_IP is defined as MSR_LASTBRANCH_28_TO_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_29_TO_IP is defined as MSR_LASTBRANCH_29_TO_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_30_TO_IP is defined as MSR_LASTBRANCH_30_TO_IP in SDM.
+        MSR_GOLDMONT_LASTBRANCH_31_TO_IP is defined as MSR_LASTBRANCH_31_TO_IP in SDM.
+  @{
+**/
+#define MSR_GOLDMONT_LASTBRANCH_0_TO_IP          0x000006C0
+#define MSR_GOLDMONT_LASTBRANCH_1_TO_IP          0x000006C1
+#define MSR_GOLDMONT_LASTBRANCH_2_TO_IP          0x000006C2
+#define MSR_GOLDMONT_LASTBRANCH_3_TO_IP          0x000006C3
+#define MSR_GOLDMONT_LASTBRANCH_4_TO_IP          0x000006C4
+#define MSR_GOLDMONT_LASTBRANCH_5_TO_IP          0x000006C5
+#define MSR_GOLDMONT_LASTBRANCH_6_TO_IP          0x000006C6
+#define MSR_GOLDMONT_LASTBRANCH_7_TO_IP          0x000006C7
+#define MSR_GOLDMONT_LASTBRANCH_8_TO_IP          0x000006C8
+#define MSR_GOLDMONT_LASTBRANCH_9_TO_IP          0x000006C9
+#define MSR_GOLDMONT_LASTBRANCH_10_TO_IP         0x000006CA
+#define MSR_GOLDMONT_LASTBRANCH_11_TO_IP         0x000006CB
+#define MSR_GOLDMONT_LASTBRANCH_12_TO_IP         0x000006CC
+#define MSR_GOLDMONT_LASTBRANCH_13_TO_IP         0x000006CD
+#define MSR_GOLDMONT_LASTBRANCH_14_TO_IP         0x000006CE
+#define MSR_GOLDMONT_LASTBRANCH_15_TO_IP         0x000006CF
+#define MSR_GOLDMONT_LASTBRANCH_16_TO_IP         0x000006D0
+#define MSR_GOLDMONT_LASTBRANCH_17_TO_IP         0x000006D1
+#define MSR_GOLDMONT_LASTBRANCH_18_TO_IP         0x000006D2
+#define MSR_GOLDMONT_LASTBRANCH_19_TO_IP         0x000006D3
+#define MSR_GOLDMONT_LASTBRANCH_20_TO_IP         0x000006D4
+#define MSR_GOLDMONT_LASTBRANCH_21_TO_IP         0x000006D5
+#define MSR_GOLDMONT_LASTBRANCH_22_TO_IP         0x000006D6
+#define MSR_GOLDMONT_LASTBRANCH_23_TO_IP         0x000006D7
+#define MSR_GOLDMONT_LASTBRANCH_24_TO_IP         0x000006D8
+#define MSR_GOLDMONT_LASTBRANCH_25_TO_IP         0x000006D9
+#define MSR_GOLDMONT_LASTBRANCH_26_TO_IP         0x000006DA
+#define MSR_GOLDMONT_LASTBRANCH_27_TO_IP         0x000006DB
+#define MSR_GOLDMONT_LASTBRANCH_28_TO_IP         0x000006DC
+#define MSR_GOLDMONT_LASTBRANCH_29_TO_IP         0x000006DD
+#define MSR_GOLDMONT_LASTBRANCH_30_TO_IP         0x000006DE
+#define MSR_GOLDMONT_LASTBRANCH_31_TO_IP         0x000006DF
+/// @}
+
+/**
+  MSR information returned for MSR indexes #MSR_GOLDMONT_LASTBRANCH_0_TO_IP to
+  #MSR_GOLDMONT_LASTBRANCH_31_TO_IP.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 31:0] Target Linear Address (R/W).
+    ///
+    UINT32  TargetLinearAddress:32;
+    ///
+    /// [Bit 47:32] Target Linear Address (R/W).
+    ///
+    UINT32  TargetLinearAddressHi:16;
+    ///
+    /// [Bits 63:48] Elapsed cycles from last update to the LBR.
+    ///
+    UINT32  ElapsedCycles:16;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER;
+
+
+/**
+  Core. Resource Association Register (R/W).
+
+  @param  ECX  MSR_GOLDMONT_IA32_PQR_ASSOC (0x00000C8F)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_PQR_ASSOC);
+  AsmWriteMsr64 (MSR_GOLDMONT_IA32_PQR_ASSOC, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.
+**/
+#define MSR_GOLDMONT_IA32_PQR_ASSOC              0x00000C8F
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_IA32_PQR_ASSOC
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:32;
+    ///
+    /// [Bits 33:32] COS (R/W).
+    ///
+    UINT32  COS:2;
+    UINT32  Reserved2:30;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER;
+
+
+/**
+  Module. L2 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H,
+  ECX=1):EDX.COS_MAX[15:0] >=n.
+
+  @param  ECX  MSR_GOLDMONT_IA32_L2_QOS_MASK_n
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_n);
+  AsmWriteMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_n, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_IA32_L2_QOS_MASK_0 is defined as IA32_L2_QOS_MASK_0 in SDM.
+        MSR_GOLDMONT_IA32_L2_QOS_MASK_1 is defined as IA32_L2_QOS_MASK_1 in SDM.
+        MSR_GOLDMONT_IA32_L2_QOS_MASK_2 is defined as IA32_L2_QOS_MASK_2 in SDM.
+  @{
+**/
+#define MSR_GOLDMONT_IA32_L2_QOS_MASK_0          0x00000D10
+#define MSR_GOLDMONT_IA32_L2_QOS_MASK_1          0x00000D11
+#define MSR_GOLDMONT_IA32_L2_QOS_MASK_2          0x00000D12
+/// @}
+
+/**
+  MSR information returned for MSR indexes #MSR_GOLDMONT_IA32_L2_QOS_MASK_0 to
+  #MSR_GOLDMONT_IA32_L2_QOS_MASK_2.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] CBM: Bit vector of available L2 ways for COS 0 enforcement
+    ///
+    UINT32  CBM:8;
+    UINT32  Reserved1:24;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER;
+
+
+/**
+  Package. L2 Class Of Service Mask - COS 3 (R/W) if CPUID.(EAX=10H,
+  ECX=1):EDX.COS_MAX[15:0] >=3.
+
+  @param  ECX  MSR_GOLDMONT_IA32_L2_QOS_MASK_3
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_3);
+  AsmWriteMsr64 (MSR_GOLDMONT_IA32_L2_QOS_MASK_3, Msr.Uint64);
+  @endcode
+  @note MSR_GOLDMONT_IA32_L2_QOS_MASK_3 is defined as IA32_L2_QOS_MASK_3 in SDM.
+**/
+#define MSR_GOLDMONT_IA32_L2_QOS_MASK_3          0x00000D13
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_IA32_L2_QOS_MASK_3.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 19:0] CBM: Bit vector of available L2 ways for COS 0 enforcement
+    ///
+    UINT32  CBM:20;
+    UINT32  Reserved1:12;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER;
+
+
+#endif
diff --git a/MdePkg/Include/Register/Intel/Msr/GoldmontPlusMsr.h b/MdePkg/Include/Register/Intel/Msr/GoldmontPlusMsr.h
new file mode 100644
index 000000000000..95e7de91dfed
--- /dev/null
+++ b/MdePkg/Include/Register/Intel/Msr/GoldmontPlusMsr.h
@@ -0,0 +1,266 @@
+/** @file
+  MSR Definitions for Intel Atom processors based on the Goldmont Plus microarchitecture.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+  May 2018, Volume 4: Model-Specific-Registers (MSR)
+
+**/
+
+#ifndef __GOLDMONT_PLUS_MSR_H__
+#define __GOLDMONT_PLUS_MSR_H__
+
+#include <Register/Intel/ArchitecturalMsr.h>
+
+/**
+  Is Intel Atom processors based on the Goldmont plus microarchitecture?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_GOLDMONT_PLUS_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (                        \
+    DisplayModel == 0x7A    \
+    )                       \
+   )
+
+/**
+  Core. (R/W) See Table 2-2. See Section 18.6.2.4, "Processor Event Based
+  Sampling (PEBS).".
+
+  @param  ECX  MSR_GOLDMONT_PLUS_PEBS_ENABLE (0x000003F1)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_GOLDMONT_PLUS_PEBS_ENABLE);
+  AsmWriteMsr64 (MSR_GOLDMONT_PLUS_PEBS_ENABLE, Msr.Uint64);
+  @endcode
+**/
+#define MSR_GOLDMONT_PLUS_PEBS_ENABLE            0x000003F1
+
+/**
+  MSR information returned for MSR index #MSR_GOLDMONT_PLUS_PEBS_ENABLE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Enable PEBS trigger and recording for the programmed event
+    /// (precise or otherwise) on IA32_PMC0.
+    ///
+    UINT32  Fix_Me_1:1;
+    ///
+    /// [Bit 1] Enable PEBS trigger and recording for the programmed event
+    /// (precise or otherwise) on IA32_PMC1.
+    ///
+    UINT32  Fix_Me_2:1;
+    ///
+    /// [Bit 2] Enable PEBS trigger and recording for the programmed event
+    /// (precise or otherwise) on IA32_PMC2.
+    ///
+    UINT32  Fix_Me_3:1;
+    ///
+    /// [Bit 3] Enable PEBS trigger and recording for the programmed event
+    /// (precise or otherwise) on IA32_PMC3.
+    ///
+    UINT32  Fix_Me_4:1;
+    UINT32  Reserved1:28;
+    ///
+    /// [Bit 32] Enable PEBS trigger and recording for IA32_FIXED_CTR0.
+    ///
+    UINT32  Fix_Me_5:1;
+    ///
+    /// [Bit 33] Enable PEBS trigger and recording for IA32_FIXED_CTR1.
+    ///
+    UINT32  Fix_Me_6:1;
+    ///
+    /// [Bit 34] Enable PEBS trigger and recording for IA32_FIXED_CTR2.
+    ///
+    UINT32  Fix_Me_7:1;
+    UINT32  Reserved2:29;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER;
+
+
+/**
+  Core. Last Branch Record N From IP (R/W) One of the three MSRs that make up
+  the first entry of the 32-entry LBR stack. The From_IP part of the stack
+  contains pointers to the source instruction. See also: -  Last Branch Record
+  Stack TOS at 1C9H. -  Section 17.7, "Last Branch, Call Stack, Interrupt, and
+  .. Exception Recording for Processors based on Goldmont Plus
+  Microarchitecture.".
+
+  @param  ECX  MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP (0x0000068N)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP);
+  AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_FROM_IP, Msr);
+  @endcode
+**/
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_0_FROM_IP    0x00000680
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_1_FROM_IP    0x00000681
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_2_FROM_IP    0x00000682
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_3_FROM_IP    0x00000683
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_4_FROM_IP    0x00000684
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_5_FROM_IP    0x00000685
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_6_FROM_IP    0x00000686
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_7_FROM_IP    0x00000687
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_8_FROM_IP    0x00000688
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_9_FROM_IP    0x00000689
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_10_FROM_IP   0x0000068A
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_11_FROM_IP   0x0000068B
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_12_FROM_IP   0x0000068C
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_13_FROM_IP   0x0000068D
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_14_FROM_IP   0x0000068E
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_15_FROM_IP   0x0000068F
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_16_FROM_IP   0x00000690
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_17_FROM_IP   0x00000691
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_18_FROM_IP   0x00000692
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_19_FROM_IP   0x00000693
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_20_FROM_IP   0x00000694
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_21_FROM_IP   0x00000695
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_22_FROM_IP   0x00000696
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_23_FROM_IP   0x00000697
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_24_FROM_IP   0x00000698
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_25_FROM_IP   0x00000699
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_26_FROM_IP   0x0000069A
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_27_FROM_IP   0x0000069B
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_28_FROM_IP   0x0000069C
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_29_FROM_IP   0x0000069D
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_30_FROM_IP   0x0000069E
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_31_FROM_IP   0x0000069F
+
+/**
+  Core. Last Branch Record N To IP (R/W) One of the three MSRs that make up
+  the first entry of the 32-entry LBR stack. The To_IP part of the stack
+  contains pointers to the Destination instruction. See also: - Section 17.7,
+  "Last Branch, Call Stack, Interrupt, and Exception Recording for Processors
+  based on Goldmont Plus Microarchitecture.".
+
+  @param  ECX  MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP (0x000006C0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP);
+  AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_N_TO_IP, Msr);
+  @endcode
+**/
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_0_TO_IP      0x000006C0
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_1_TO_IP      0x000006C1
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_2_TO_IP      0x000006C2
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_3_TO_IP      0x000006C3
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_4_TO_IP      0x000006C4
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_5_TO_IP      0x000006C5
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_6_TO_IP      0x000006C6
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_7_TO_IP      0x000006C7
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_8_TO_IP      0x000006C8
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_9_TO_IP      0x000006C9
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_10_TO_IP     0x000006CA
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_11_TO_IP     0x000006CB
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_12_TO_IP     0x000006CC
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_13_TO_IP     0x000006CD
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_14_TO_IP     0x000006CE
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_15_TO_IP     0x000006CF
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_16_TO_IP     0x000006D0
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_17_TO_IP     0x000006D1
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_18_TO_IP     0x000006D2
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_19_TO_IP     0x000006D3
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_20_TO_IP     0x000006D4
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_21_TO_IP     0x000006D5
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_22_TO_IP     0x000006D6
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_23_TO_IP     0x000006D7
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_24_TO_IP     0x000006D8
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_25_TO_IP     0x000006D9
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_26_TO_IP     0x000006DA
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_27_TO_IP     0x000006DB
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_28_TO_IP     0x000006DC
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_29_TO_IP     0x000006DD
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_30_TO_IP     0x000006DE
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_31_TO_IP     0x000006DF
+
+
+/**
+  Core. Last Branch Record N Additional Information (R/W) One of the three
+  MSRs that make up the first entry of the 32-entry LBR stack. This part of
+  the stack contains flag and elapsed cycle information. See also: -  Last
+  Branch Record Stack TOS at 1C9H. -  Section 17.9.1, "LBR Stack.".
+
+  @param  ECX  MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N (0x00000DCN)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N);
+  AsmWriteMsr64 (MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_N, Msr);
+  @endcode
+**/
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_0      0x00000DC0
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_1      0x00000DC1
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_2      0x00000DC2
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_3      0x00000DC3
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_4      0x00000DC4
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_5      0x00000DC5
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_6      0x00000DC6
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_7      0x00000DC7
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_8      0x00000DC8
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_9      0x00000DC9
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_10     0x00000DCA
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_11     0x00000DCB
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_12     0x00000DCC
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_13     0x00000DCD
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_14     0x00000DCE
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_15     0x00000DCF
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_16     0x00000DD0
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_17     0x00000DD1
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_18     0x00000DD2
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_19     0x00000DD3
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_20     0x00000DD4
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_21     0x00000DD5
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_22     0x00000DD6
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_23     0x00000DD7
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_24     0x00000DD8
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_25     0x00000DD9
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_26     0x00000DDA
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_27     0x00000DDB
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_28     0x00000DDC
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_29     0x00000DDD
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_30     0x00000DDE
+#define MSR_GOLDMONT_PLUS_LASTBRANCH_INFO_31     0x00000DDF
+
+#endif
diff --git a/MdePkg/Include/Register/Intel/Msr/HaswellEMsr.h b/MdePkg/Include/Register/Intel/Msr/HaswellEMsr.h
new file mode 100644
index 000000000000..4fa6000f7066
--- /dev/null
+++ b/MdePkg/Include/Register/Intel/Msr/HaswellEMsr.h
@@ -0,0 +1,6400 @@
+/** @file
+  MSR Definitions for Intel processors based on the Haswell-E microarchitecture.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+  May 2018, Volume 4: Model-Specific-Registers (MSR)
+
+**/
+
+#ifndef __HASWELL_E_MSR_H__
+#define __HASWELL_E_MSR_H__
+
+#include <Register/Intel/ArchitecturalMsr.h>
+
+/**
+  Is Intel processors based on the Haswell-E microarchitecture?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_HASWELL_E_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (                        \
+    DisplayModel == 0x3F    \
+    )                       \
+   )
+
+/**
+  Package. Configured State of Enabled Processor Core Count and Logical
+  Processor Count (RO) -  After a Power-On RESET, enumerates factory
+  configuration of the number of processor cores and logical processors in the
+  physical package. -  Following the sequence of (i) BIOS modified a
+  Configuration Mask which selects a subset of processor cores to be active
+  post RESET and (ii) a RESET event after the modification, enumerates the
+  current configuration of enabled processor core count and logical processor
+  count in the physical package.
+
+  @param  ECX  MSR_HASWELL_E_CORE_THREAD_COUNT (0x00000035)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_CORE_THREAD_COUNT);
+  @endcode
+  @note MSR_HASWELL_E_CORE_THREAD_COUNT is defined as MSR_CORE_THREAD_COUNT in SDM.
+**/
+#define MSR_HASWELL_E_CORE_THREAD_COUNT          0x00000035
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_E_CORE_THREAD_COUNT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 15:0] Core_COUNT (RO) The number of processor cores that are
+    /// currently enabled (by either factory configuration or BIOS
+    /// configuration) in the physical package.
+    ///
+    UINT32  Core_Count:16;
+    ///
+    /// [Bits 31:16] THREAD_COUNT (RO) The number of logical processors that
+    /// are currently enabled (by either factory configuration or BIOS
+    /// configuration) in the physical package.
+    ///
+    UINT32  Thread_Count:16;
+    UINT32  Reserved:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER;
+
+
+/**
+  Thread. A Hardware Assigned ID for the Logical Processor (RO).
+
+  @param  ECX  MSR_HASWELL_E_THREAD_ID_INFO (0x00000053)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_THREAD_ID_INFO_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_THREAD_ID_INFO_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_E_THREAD_ID_INFO_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_THREAD_ID_INFO);
+  @endcode
+  @note MSR_HASWELL_E_THREAD_ID_INFO is defined as MSR_THREAD_ID_INFO in SDM.
+**/
+#define MSR_HASWELL_E_THREAD_ID_INFO             0x00000053
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_E_THREAD_ID_INFO
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Logical_Processor_ID (RO) An implementation-specific
+    /// numerical. value physically assigned to each logical processor. This
+    /// ID is not related to Initial APIC ID or x2APIC ID, it is unique within
+    /// a physical package.
+    ///
+    UINT32  Logical_Processor_ID:8;
+    UINT32  Reserved1:24;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_E_THREAD_ID_INFO_REGISTER;
+
+
+/**
+  Core. C-State Configuration Control (R/W) Note: C-state values are processor
+  specific C-state code names, unrelated to MWAIT extension C-state parameters
+  or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.
+
+  @param  ECX  MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL (0x000000E2)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL);
+  AsmWriteMsr64 (MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
+**/
+#define MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL     0x000000E2
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest
+    /// processor-specific C-state code name (consuming the least power) for
+    /// the package. The default is set as factory-configured package C-state
+    /// limit. The following C-state code name encodings are supported: 000b:
+    /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention)
+    /// 011b: C6 (retention) 111b: No Package C state limits. All C states
+    /// supported by the processor are available.
+    ///
+    UINT32  Limit:3;
+    UINT32  Reserved1:7;
+    ///
+    /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
+    ///
+    UINT32  IO_MWAIT:1;
+    UINT32  Reserved2:4;
+    ///
+    /// [Bit 15] CFG Lock (R/WO).
+    ///
+    UINT32  CFGLock:1;
+    UINT32  Reserved3:9;
+    ///
+    /// [Bit 25] C3 State Auto Demotion Enable (R/W).
+    ///
+    UINT32  C3AutoDemotion:1;
+    ///
+    /// [Bit 26] C1 State Auto Demotion Enable (R/W).
+    ///
+    UINT32  C1AutoDemotion:1;
+    ///
+    /// [Bit 27] Enable C3 Undemotion (R/W).
+    ///
+    UINT32  C3Undemotion:1;
+    ///
+    /// [Bit 28] Enable C1 Undemotion (R/W).
+    ///
+    UINT32  C1Undemotion:1;
+    ///
+    /// [Bit 29] Package C State Demotion Enable (R/W).
+    ///
+    UINT32  CStateDemotion:1;
+    ///
+    /// [Bit 30] Package C State UnDemotion Enable (R/W).
+    ///
+    UINT32  CStateUndemotion:1;
+    UINT32  Reserved4:1;
+    UINT32  Reserved5:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER;
+
+
+/**
+  Thread. Global Machine Check Capability (R/O).
+
+  @param  ECX  MSR_HASWELL_E_IA32_MCG_CAP (0x00000179)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_IA32_MCG_CAP_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_IA32_MCG_CAP_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_E_IA32_MCG_CAP_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_MCG_CAP);
+  @endcode
+  @note MSR_HASWELL_E_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.
+**/
+#define MSR_HASWELL_E_IA32_MCG_CAP               0x00000179
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_E_IA32_MCG_CAP
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Count.
+    ///
+    UINT32  Count:8;
+    ///
+    /// [Bit 8] MCG_CTL_P.
+    ///
+    UINT32  MCG_CTL_P:1;
+    ///
+    /// [Bit 9] MCG_EXT_P.
+    ///
+    UINT32  MCG_EXT_P:1;
+    ///
+    /// [Bit 10] MCP_CMCI_P.
+    ///
+    UINT32  MCP_CMCI_P:1;
+    ///
+    /// [Bit 11] MCG_TES_P.
+    ///
+    UINT32  MCG_TES_P:1;
+    UINT32  Reserved1:4;
+    ///
+    /// [Bits 23:16] MCG_EXT_CNT.
+    ///
+    UINT32  MCG_EXT_CNT:8;
+    ///
+    /// [Bit 24] MCG_SER_P.
+    ///
+    UINT32  MCG_SER_P:1;
+    ///
+    /// [Bit 25] MCG_EM_P.
+    ///
+    UINT32  MCG_EM_P:1;
+    ///
+    /// [Bit 26] MCG_ELOG_P.
+    ///
+    UINT32  MCG_ELOG_P:1;
+    UINT32  Reserved2:5;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_E_IA32_MCG_CAP_REGISTER;
+
+
+/**
+  THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability
+  Enhancement. Accessible only while in SMM.
+
+  @param  ECX  MSR_HASWELL_E_SMM_MCA_CAP (0x0000017D)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_SMM_MCA_CAP_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_SMM_MCA_CAP_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_E_SMM_MCA_CAP_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_SMM_MCA_CAP);
+  AsmWriteMsr64 (MSR_HASWELL_E_SMM_MCA_CAP, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_E_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.
+**/
+#define MSR_HASWELL_E_SMM_MCA_CAP                0x0000017D
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_E_SMM_MCA_CAP
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:32;
+    UINT32  Reserved2:26;
+    ///
+    /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
+    /// SMM code access restriction is supported and a host-space interface
+    /// available to SMM handler.
+    ///
+    UINT32  SMM_Code_Access_Chk:1;
+    ///
+    /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the
+    /// SMM long flow indicator is supported and a host-space interface
+    /// available to SMM handler.
+    ///
+    UINT32  Long_Flow_Indication:1;
+    UINT32  Reserved3:4;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_E_SMM_MCA_CAP_REGISTER;
+
+
+/**
+  Package. MC Bank Error Configuration (R/W).
+
+  @param  ECX  MSR_HASWELL_E_ERROR_CONTROL (0x0000017F)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_ERROR_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_ERROR_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_E_ERROR_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_ERROR_CONTROL);
+  AsmWriteMsr64 (MSR_HASWELL_E_ERROR_CONTROL, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_E_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.
+**/
+#define MSR_HASWELL_E_ERROR_CONTROL              0x0000017F
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_E_ERROR_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 1] MemError Log Enable (R/W)  When set, enables IMC status bank
+    /// to log additional info in bits 36:32.
+    ///
+    UINT32  MemErrorLogEnable:1;
+    UINT32  Reserved2:30;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_E_ERROR_CONTROL_REGISTER;
+
+
+/**
+  Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
+  RW if MSR_PLATFORM_INFO.[28] = 1.
+
+  @param  ECX  MSR_HASWELL_E_TURBO_RATIO_LIMIT (0x000001AD)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT);
+  @endcode
+  @note MSR_HASWELL_E_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
+**/
+#define MSR_HASWELL_E_TURBO_RATIO_LIMIT          0x000001AD
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
+    /// limit of 1 core active.
+    ///
+    UINT32  Maximum1C:8;
+    ///
+    /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
+    /// limit of 2 core active.
+    ///
+    UINT32  Maximum2C:8;
+    ///
+    /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
+    /// limit of 3 core active.
+    ///
+    UINT32  Maximum3C:8;
+    ///
+    /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
+    /// limit of 4 core active.
+    ///
+    UINT32  Maximum4C:8;
+    ///
+    /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
+    /// limit of 5 core active.
+    ///
+    UINT32  Maximum5C:8;
+    ///
+    /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
+    /// limit of 6 core active.
+    ///
+    UINT32  Maximum6C:8;
+    ///
+    /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio
+    /// limit of 7 core active.
+    ///
+    UINT32  Maximum7C:8;
+    ///
+    /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio
+    /// limit of 8 core active.
+    ///
+    UINT32  Maximum8C:8;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER;
+
+
+/**
+  Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
+  RW if MSR_PLATFORM_INFO.[28] = 1.
+
+  @param  ECX  MSR_HASWELL_E_TURBO_RATIO_LIMIT1 (0x000001AE)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT1);
+  @endcode
+  @note MSR_HASWELL_E_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.
+**/
+#define MSR_HASWELL_E_TURBO_RATIO_LIMIT1         0x000001AE
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT1
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio
+    /// limit of 9 core active.
+    ///
+    UINT32  Maximum9C:8;
+    ///
+    /// [Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio
+    /// limit of 10 core active.
+    ///
+    UINT32  Maximum10C:8;
+    ///
+    /// [Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio
+    /// limit of 11 core active.
+    ///
+    UINT32  Maximum11C:8;
+    ///
+    /// [Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio
+    /// limit of 12 core active.
+    ///
+    UINT32  Maximum12C:8;
+    ///
+    /// [Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio
+    /// limit of 13 core active.
+    ///
+    UINT32  Maximum13C:8;
+    ///
+    /// [Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio
+    /// limit of 14 core active.
+    ///
+    UINT32  Maximum14C:8;
+    ///
+    /// [Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio
+    /// limit of 15 core active.
+    ///
+    UINT32  Maximum15C:8;
+    ///
+    /// [Bits 63:56] Package. Maximum Ratio Limit for16C Maximum turbo ratio
+    /// limit of 16 core active.
+    ///
+    UINT32  Maximum16C:8;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER;
+
+
+/**
+  Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
+  RW if MSR_PLATFORM_INFO.[28] = 1.
+
+  @param  ECX  MSR_HASWELL_E_TURBO_RATIO_LIMIT2 (0x000001AF)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_TURBO_RATIO_LIMIT2);
+  @endcode
+  @note MSR_HASWELL_E_TURBO_RATIO_LIMIT2 is defined as MSR_TURBO_RATIO_LIMIT2 in SDM.
+**/
+#define MSR_HASWELL_E_TURBO_RATIO_LIMIT2         0x000001AF
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT2
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Package. Maximum Ratio Limit for 17C Maximum turbo ratio
+    /// limit of 17 core active.
+    ///
+    UINT32  Maximum17C:8;
+    ///
+    /// [Bits 15:8] Package. Maximum Ratio Limit for 18C Maximum turbo ratio
+    /// limit of 18 core active.
+    ///
+    UINT32  Maximum18C:8;
+    UINT32  Reserved1:16;
+    UINT32  Reserved2:31;
+    ///
+    /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,
+    /// the processor uses override configuration specified in
+    /// MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1 and
+    /// MSR_TURBO_RATIO_LIMIT2. If 0, the processor uses factory-set
+    /// configuration (Default).
+    ///
+    UINT32  TurboRatioLimitConfigurationSemaphore:1;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER;
+
+
+/**
+  Package. Unit Multipliers used in RAPL Interfaces (R/O).
+
+  @param  ECX  MSR_HASWELL_E_RAPL_POWER_UNIT (0x00000606)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_RAPL_POWER_UNIT);
+  @endcode
+  @note MSR_HASWELL_E_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
+**/
+#define MSR_HASWELL_E_RAPL_POWER_UNIT            0x00000606
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_E_RAPL_POWER_UNIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".
+    ///
+    UINT32  PowerUnits:4;
+    UINT32  Reserved1:4;
+    ///
+    /// [Bits 12:8] Package. Energy Status Units Energy related information
+    /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an
+    /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61
+    /// micro-joules).
+    ///
+    UINT32  EnergyStatusUnits:5;
+    UINT32  Reserved2:3;
+    ///
+    /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL
+    /// Interfaces.".
+    ///
+    UINT32  TimeUnits:4;
+    UINT32  Reserved3:12;
+    UINT32  Reserved4:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER;
+
+
+/**
+  Package. DRAM RAPL Power Limit Control (R/W)  See Section 14.9.5, "DRAM RAPL
+  Domain.".
+
+  @param  ECX  MSR_HASWELL_E_DRAM_POWER_LIMIT (0x00000618)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_POWER_LIMIT);
+  AsmWriteMsr64 (MSR_HASWELL_E_DRAM_POWER_LIMIT, Msr);
+  @endcode
+  @note MSR_HASWELL_E_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
+**/
+#define MSR_HASWELL_E_DRAM_POWER_LIMIT           0x00000618
+
+
+/**
+  Package. DRAM Energy Status (R/O)  Energy Consumed by DRAM devices.
+
+  @param  ECX  MSR_HASWELL_E_DRAM_ENERGY_STATUS (0x00000619)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_DRAM_ENERGY_STATUS);
+  @endcode
+  @note MSR_HASWELL_E_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_DRAM_ENERGY_STATUS         0x00000619
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_E_DRAM_ENERGY_STATUS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration
+    /// to enable DRAM RAPL mode 0 (Direct VR).
+    ///
+    UINT32  Energy:32;
+    UINT32  Reserved:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER;
+
+
+/**
+  Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
+  RAPL Domain.".
+
+  @param  ECX  MSR_HASWELL_E_DRAM_PERF_STATUS (0x0000061B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_PERF_STATUS);
+  @endcode
+  @note MSR_HASWELL_E_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_DRAM_PERF_STATUS           0x0000061B
+
+
+/**
+  Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
+
+  @param  ECX  MSR_HASWELL_E_DRAM_POWER_INFO (0x0000061C)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_DRAM_POWER_INFO);
+  AsmWriteMsr64 (MSR_HASWELL_E_DRAM_POWER_INFO, Msr);
+  @endcode
+  @note MSR_HASWELL_E_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
+**/
+#define MSR_HASWELL_E_DRAM_POWER_INFO            0x0000061C
+
+
+/**
+  Package. Configuration of PCIE PLL Relative to BCLK(R/W).
+
+  @param  ECX  MSR_HASWELL_E_PCIE_PLL_RATIO (0x0000061E)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_PCIE_PLL_RATIO);
+  AsmWriteMsr64 (MSR_HASWELL_E_PCIE_PLL_RATIO, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_E_PCIE_PLL_RATIO is defined as MSR_PCIE_PLL_RATIO in SDM.
+**/
+#define MSR_HASWELL_E_PCIE_PLL_RATIO             0x0000061E
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_E_PCIE_PLL_RATIO
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 1:0] Package. PCIE Ratio (R/W) 00b: Use 5:5 mapping for100MHz
+    /// operation (default) 01b: Use 5:4 mapping for125MHz operation 10b: Use
+    /// 5:3 mapping for166MHz operation 11b: Use 5:2 mapping for250MHz
+    /// operation.
+    ///
+    UINT32  PCIERatio:2;
+    ///
+    /// [Bit 2] Package. LPLL Select (R/W) if 1, use configured setting of
+    /// PCIE Ratio.
+    ///
+    UINT32  LPLLSelect:1;
+    ///
+    /// [Bit 3] Package. LONG RESET (R/W) if 1, wait additional time-out
+    /// before re-locking Gen2/Gen3 PLLs.
+    ///
+    UINT32  LONGRESET:1;
+    UINT32  Reserved1:28;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER;
+
+
+/**
+  Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio
+  fields represent the widest possible range of uncore frequencies. Writing to
+  these fields allows software to control the minimum and the maximum
+  frequency that hardware will select.
+
+  @param  ECX  MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT (0x00000620)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT);
+  AsmWriteMsr64 (MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);
+  @endcode
+**/
+#define MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT      0x00000620
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the
+    /// LLC/Ring.
+    ///
+    UINT32  MAX_RATIO:7;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum
+    /// possible ratio of the LLC/Ring.
+    ///
+    UINT32  MIN_RATIO:7;
+    UINT32  Reserved2:17;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER;
+
+/**
+  Package. Reserved (R/O) Reads return 0.
+
+  @param  ECX  MSR_HASWELL_E_PP0_ENERGY_STATUS (0x00000639)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_PP0_ENERGY_STATUS);
+  @endcode
+  @note MSR_HASWELL_E_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_PP0_ENERGY_STATUS          0x00000639
+
+
+/**
+  Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
+  refers to processor core frequency).
+
+  @param  ECX  MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS (0x00000690)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS);
+  AsmWriteMsr64 (MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
+**/
+#define MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS    0x00000690
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is
+    /// reduced below the operating system request due to assertion of
+    /// external PROCHOT.
+    ///
+    UINT32  PROCHOT_Status:1;
+    ///
+    /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
+    /// operating system request due to a thermal event.
+    ///
+    UINT32  ThermalStatus:1;
+    ///
+    /// [Bit 2] Power Budget Management Status (R0) When set, frequency is
+    /// reduced below the operating system request due to PBM limit.
+    ///
+    UINT32  PowerBudgetManagementStatus:1;
+    ///
+    /// [Bit 3] Platform Configuration Services Status (R0) When set,
+    /// frequency is reduced below the operating system request due to PCS
+    /// limit.
+    ///
+    UINT32  PlatformConfigurationServicesStatus:1;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)
+    /// When set, frequency is reduced below the operating system request
+    /// because the processor has detected that utilization is low.
+    ///
+    UINT32  AutonomousUtilizationBasedFrequencyControlStatus:1;
+    ///
+    /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced
+    /// below the operating system request due to a thermal alert from the
+    /// Voltage Regulator.
+    ///
+    UINT32  VRThermAlertStatus:1;
+    UINT32  Reserved2:1;
+    ///
+    /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is
+    /// reduced below the operating system request due to electrical design
+    /// point constraints (e.g. maximum electrical current consumption).
+    ///
+    UINT32  ElectricalDesignPointStatus:1;
+    UINT32  Reserved3:1;
+    ///
+    /// [Bit 10] Multi-Core Turbo Status (R0) When set, frequency is reduced
+    /// below the operating system request due to Multi-Core Turbo limits.
+    ///
+    UINT32  MultiCoreTurboStatus:1;
+    UINT32  Reserved4:2;
+    ///
+    /// [Bit 13] Core Frequency P1 Status (R0) When set, frequency is reduced
+    /// below max non-turbo P1.
+    ///
+    UINT32  FrequencyP1Status:1;
+    ///
+    /// [Bit 14] Core Max n-core Turbo Frequency Limiting Status (R0) When
+    /// set, frequency is reduced below max n-core turbo frequency.
+    ///
+    UINT32  TurboFrequencyLimitingStatus:1;
+    ///
+    /// [Bit 15] Core Frequency Limiting Status (R0) When set, frequency is
+    /// reduced below the operating system request.
+    ///
+    UINT32  FrequencyLimitingStatus:1;
+    ///
+    /// [Bit 16] PROCHOT Log  When set, indicates that the PROCHOT Status bit
+    /// has asserted since the log bit was last cleared. This log bit will
+    /// remain set until cleared by software writing 0.
+    ///
+    UINT32  PROCHOT_Log:1;
+    ///
+    /// [Bit 17] Thermal Log  When set, indicates that the Thermal Status bit
+    /// has asserted since the log bit was last cleared. This log bit will
+    /// remain set until cleared by software writing 0.
+    ///
+    UINT32  ThermalLog:1;
+    ///
+    /// [Bit 18] Power Budget Management Log  When set, indicates that the PBM
+    /// Status bit has asserted since the log bit was last cleared. This log
+    /// bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  PowerBudgetManagementLog:1;
+    ///
+    /// [Bit 19] Platform Configuration Services Log  When set, indicates that
+    /// the PCS Status bit has asserted since the log bit was last cleared.
+    /// This log bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  PlatformConfigurationServicesLog:1;
+    UINT32  Reserved5:1;
+    ///
+    /// [Bit 21] Autonomous Utilization-Based Frequency Control Log  When set,
+    /// indicates that the AUBFC Status bit has asserted since the log bit was
+    /// last cleared. This log bit will remain set until cleared by software
+    /// writing 0.
+    ///
+    UINT32  AutonomousUtilizationBasedFrequencyControlLog:1;
+    ///
+    /// [Bit 22] VR Therm Alert Log  When set, indicates that the VR Therm
+    /// Alert Status bit has asserted since the log bit was last cleared. This
+    /// log bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  VRThermAlertLog:1;
+    UINT32  Reserved6:1;
+    ///
+    /// [Bit 24] Electrical Design Point Log  When set, indicates that the EDP
+    /// Status bit has asserted since the log bit was last cleared. This log
+    /// bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  ElectricalDesignPointLog:1;
+    UINT32  Reserved7:1;
+    ///
+    /// [Bit 26] Multi-Core Turbo Log  When set, indicates that the Multi-Core
+    /// Turbo Status bit has asserted since the log bit was last cleared. This
+    /// log bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  MultiCoreTurboLog:1;
+    UINT32  Reserved8:2;
+    ///
+    /// [Bit 29] Core Frequency P1 Log When set, indicates that the Core
+    /// Frequency P1 Status bit has asserted since the log bit was last
+    /// cleared. This log bit will remain set until cleared by software
+    /// writing 0.
+    ///
+    UINT32  CoreFrequencyP1Log:1;
+    ///
+    /// [Bit 30] Core Max n-core Turbo Frequency Limiting Log When set,
+    /// indicates that the Core Max n-core Turbo Frequency Limiting Status bit
+    /// has asserted since the log bit was last cleared. This log bit will
+    /// remain set until cleared by software writing 0.
+    ///
+    UINT32  TurboFrequencyLimitingLog:1;
+    ///
+    /// [Bit 31] Core Frequency Limiting Log When set, indicates that the Core
+    /// Frequency Limiting Status bit has asserted since the log bit was last
+    /// cleared. This log bit will remain set until cleared by software
+    /// writing 0.
+    ///
+    UINT32  CoreFrequencyLimitingLog:1;
+    UINT32  Reserved9:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER;
+
+
+/**
+  THREAD. Monitoring Event Select Register (R/W). if CPUID.(EAX=07H,
+  ECX=0):EBX.RDT-M[bit 12] = 1.
+
+  @param  ECX  MSR_HASWELL_E_IA32_QM_EVTSEL (0x00000C8D)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_QM_EVTSEL);
+  AsmWriteMsr64 (MSR_HASWELL_E_IA32_QM_EVTSEL, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_E_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.
+**/
+#define MSR_HASWELL_E_IA32_QM_EVTSEL             0x00000C8D
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_E_IA32_QM_EVTSEL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] EventID (RW) Event encoding: 0x0: no monitoring 0x1: L3
+    /// occupancy monitoring all other encoding reserved..
+    ///
+    UINT32  EventID:8;
+    UINT32  Reserved1:24;
+    ///
+    /// [Bits 41:32] RMID (RW).
+    ///
+    UINT32  RMID:10;
+    UINT32  Reserved2:22;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER;
+
+
+/**
+  THREAD. Resource Association Register (R/W)..
+
+  @param  ECX  MSR_HASWELL_E_IA32_PQR_ASSOC (0x00000C8F)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_E_IA32_PQR_ASSOC);
+  AsmWriteMsr64 (MSR_HASWELL_E_IA32_PQR_ASSOC, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_E_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.
+**/
+#define MSR_HASWELL_E_IA32_PQR_ASSOC             0x00000C8F
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_E_IA32_PQR_ASSOC
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 9:0] RMID.
+    ///
+    UINT32  RMID:10;
+    UINT32  Reserved1:22;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER;
+
+
+/**
+  Package. Uncore perfmon per-socket global control.
+
+  @param  ECX  MSR_HASWELL_E_PMON_GLOBAL_CTL (0x00000700)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_PMON_GLOBAL_CTL is defined as MSR_PMON_GLOBAL_CTL in SDM.
+**/
+#define MSR_HASWELL_E_PMON_GLOBAL_CTL            0x00000700
+
+
+/**
+  Package. Uncore perfmon per-socket global status.
+
+  @param  ECX  MSR_HASWELL_E_PMON_GLOBAL_STATUS (0x00000701)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_STATUS, Msr);
+  @endcode
+  @note MSR_HASWELL_E_PMON_GLOBAL_STATUS is defined as MSR_PMON_GLOBAL_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_PMON_GLOBAL_STATUS         0x00000701
+
+
+/**
+  Package. Uncore perfmon per-socket global configuration.
+
+  @param  ECX  MSR_HASWELL_E_PMON_GLOBAL_CONFIG (0x00000702)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CONFIG);
+  AsmWriteMsr64 (MSR_HASWELL_E_PMON_GLOBAL_CONFIG, Msr);
+  @endcode
+  @note MSR_HASWELL_E_PMON_GLOBAL_CONFIG is defined as MSR_PMON_GLOBAL_CONFIG in SDM.
+**/
+#define MSR_HASWELL_E_PMON_GLOBAL_CONFIG         0x00000702
+
+
+/**
+  Package. Uncore U-box UCLK fixed counter control.
+
+  @param  ECX  MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL (0x00000703)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL is defined as MSR_U_PMON_UCLK_FIXED_CTL in SDM.
+**/
+#define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTL      0x00000703
+
+
+/**
+  Package. Uncore U-box UCLK fixed counter.
+
+  @param  ECX  MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR (0x00000704)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR);
+  AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR, Msr);
+  @endcode
+  @note MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR is defined as MSR_U_PMON_UCLK_FIXED_CTR in SDM.
+**/
+#define MSR_HASWELL_E_U_PMON_UCLK_FIXED_CTR      0x00000704
+
+
+/**
+  Package. Uncore U-box perfmon event select for U-box counter 0.
+
+  @param  ECX  MSR_HASWELL_E_U_PMON_EVNTSEL0 (0x00000705)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_U_PMON_EVNTSEL0 is defined as MSR_U_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_U_PMON_EVNTSEL0            0x00000705
+
+
+/**
+  Package. Uncore U-box perfmon event select for U-box counter 1.
+
+  @param  ECX  MSR_HASWELL_E_U_PMON_EVNTSEL1 (0x00000706)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_U_PMON_EVNTSEL1 is defined as MSR_U_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_U_PMON_EVNTSEL1            0x00000706
+
+
+/**
+  Package. Uncore U-box perfmon U-box wide status.
+
+  @param  ECX  MSR_HASWELL_E_U_PMON_BOX_STATUS (0x00000708)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_HASWELL_E_U_PMON_BOX_STATUS is defined as MSR_U_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_U_PMON_BOX_STATUS          0x00000708
+
+
+/**
+  Package. Uncore U-box perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_U_PMON_CTR0 (0x00000709)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_U_PMON_CTR0 is defined as MSR_U_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_U_PMON_CTR0                0x00000709
+
+
+/**
+  Package. Uncore U-box perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_U_PMON_CTR1 (0x0000070A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_U_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_U_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_U_PMON_CTR1 is defined as MSR_U_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_U_PMON_CTR1                0x0000070A
+
+
+/**
+  Package. Uncore PCU perfmon for PCU-box-wide control.
+
+  @param  ECX  MSR_HASWELL_E_PCU_PMON_BOX_CTL (0x00000710)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_PCU_PMON_BOX_CTL is defined as MSR_PCU_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_PCU_PMON_BOX_CTL           0x00000710
+
+
+/**
+  Package. Uncore PCU perfmon event select for PCU counter 0.
+
+  @param  ECX  MSR_HASWELL_E_PCU_PMON_EVNTSEL0 (0x00000711)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_PCU_PMON_EVNTSEL0 is defined as MSR_PCU_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_PCU_PMON_EVNTSEL0          0x00000711
+
+
+/**
+  Package. Uncore PCU perfmon event select for PCU counter 1.
+
+  @param  ECX  MSR_HASWELL_E_PCU_PMON_EVNTSEL1 (0x00000712)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_PCU_PMON_EVNTSEL1 is defined as MSR_PCU_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_PCU_PMON_EVNTSEL1          0x00000712
+
+
+/**
+  Package. Uncore PCU perfmon event select for PCU counter 2.
+
+  @param  ECX  MSR_HASWELL_E_PCU_PMON_EVNTSEL2 (0x00000713)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_PCU_PMON_EVNTSEL2 is defined as MSR_PCU_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_PCU_PMON_EVNTSEL2          0x00000713
+
+
+/**
+  Package. Uncore PCU perfmon event select for PCU counter 3.
+
+  @param  ECX  MSR_HASWELL_E_PCU_PMON_EVNTSEL3 (0x00000714)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_PCU_PMON_EVNTSEL3 is defined as MSR_PCU_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_PCU_PMON_EVNTSEL3          0x00000714
+
+
+/**
+  Package. Uncore PCU perfmon box-wide filter.
+
+  @param  ECX  MSR_HASWELL_E_PCU_PMON_BOX_FILTER (0x00000715)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_FILTER);
+  AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_FILTER, Msr);
+  @endcode
+  @note MSR_HASWELL_E_PCU_PMON_BOX_FILTER is defined as MSR_PCU_PMON_BOX_FILTER in SDM.
+**/
+#define MSR_HASWELL_E_PCU_PMON_BOX_FILTER        0x00000715
+
+
+/**
+  Package. Uncore PCU perfmon box wide status.
+
+  @param  ECX  MSR_HASWELL_E_PCU_PMON_BOX_STATUS (0x00000716)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_HASWELL_E_PCU_PMON_BOX_STATUS is defined as MSR_PCU_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_PCU_PMON_BOX_STATUS        0x00000716
+
+
+/**
+  Package. Uncore PCU perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_PCU_PMON_CTR0 (0x00000717)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_PCU_PMON_CTR0 is defined as MSR_PCU_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_PCU_PMON_CTR0              0x00000717
+
+
+/**
+  Package. Uncore PCU perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_PCU_PMON_CTR1 (0x00000718)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_PCU_PMON_CTR1 is defined as MSR_PCU_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_PCU_PMON_CTR1              0x00000718
+
+
+/**
+  Package. Uncore PCU perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_PCU_PMON_CTR2 (0x00000719)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_PCU_PMON_CTR2 is defined as MSR_PCU_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_PCU_PMON_CTR2              0x00000719
+
+
+/**
+  Package. Uncore PCU perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_PCU_PMON_CTR3 (0x0000071A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_PCU_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_PCU_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_PCU_PMON_CTR3 is defined as MSR_PCU_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_PCU_PMON_CTR3              0x0000071A
+
+
+/**
+  Package. Uncore SBo 0 perfmon for SBo 0 box-wide control.
+
+  @param  ECX  MSR_HASWELL_E_S0_PMON_BOX_CTL (0x00000720)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S0_PMON_BOX_CTL is defined as MSR_S0_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_S0_PMON_BOX_CTL            0x00000720
+
+
+/**
+  Package. Uncore SBo 0 perfmon event select for SBo 0 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_S0_PMON_EVNTSEL0 (0x00000721)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S0_PMON_EVNTSEL0 is defined as MSR_S0_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_S0_PMON_EVNTSEL0           0x00000721
+
+
+/**
+  Package. Uncore SBo 0 perfmon event select for SBo 0 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_S0_PMON_EVNTSEL1 (0x00000722)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S0_PMON_EVNTSEL1 is defined as MSR_S0_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_S0_PMON_EVNTSEL1           0x00000722
+
+
+/**
+  Package. Uncore SBo 0 perfmon event select for SBo 0 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_S0_PMON_EVNTSEL2 (0x00000723)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S0_PMON_EVNTSEL2 is defined as MSR_S0_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_S0_PMON_EVNTSEL2           0x00000723
+
+
+/**
+  Package. Uncore SBo 0 perfmon event select for SBo 0 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_S0_PMON_EVNTSEL3 (0x00000724)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S0_PMON_EVNTSEL3 is defined as MSR_S0_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_S0_PMON_EVNTSEL3           0x00000724
+
+
+/**
+  Package. Uncore SBo 0 perfmon box-wide filter.
+
+  @param  ECX  MSR_HASWELL_E_S0_PMON_BOX_FILTER (0x00000725)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_BOX_FILTER);
+  AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_BOX_FILTER, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S0_PMON_BOX_FILTER is defined as MSR_S0_PMON_BOX_FILTER in SDM.
+**/
+#define MSR_HASWELL_E_S0_PMON_BOX_FILTER         0x00000725
+
+
+/**
+  Package. Uncore SBo 0 perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_S0_PMON_CTR0 (0x00000726)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S0_PMON_CTR0 is defined as MSR_S0_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_S0_PMON_CTR0               0x00000726
+
+
+/**
+  Package. Uncore SBo 0 perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_S0_PMON_CTR1 (0x00000727)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S0_PMON_CTR1 is defined as MSR_S0_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_S0_PMON_CTR1               0x00000727
+
+
+/**
+  Package. Uncore SBo 0 perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_S0_PMON_CTR2 (0x00000728)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S0_PMON_CTR2 is defined as MSR_S0_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_S0_PMON_CTR2               0x00000728
+
+
+/**
+  Package. Uncore SBo 0 perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_S0_PMON_CTR3 (0x00000729)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S0_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_S0_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S0_PMON_CTR3 is defined as MSR_S0_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_S0_PMON_CTR3               0x00000729
+
+
+/**
+  Package. Uncore SBo 1 perfmon for SBo 1 box-wide control.
+
+  @param  ECX  MSR_HASWELL_E_S1_PMON_BOX_CTL (0x0000072A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S1_PMON_BOX_CTL is defined as MSR_S1_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_S1_PMON_BOX_CTL            0x0000072A
+
+
+/**
+  Package. Uncore SBo 1 perfmon event select for SBo 1 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_S1_PMON_EVNTSEL0 (0x0000072B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S1_PMON_EVNTSEL0 is defined as MSR_S1_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_S1_PMON_EVNTSEL0           0x0000072B
+
+
+/**
+  Package. Uncore SBo 1 perfmon event select for SBo 1 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_S1_PMON_EVNTSEL1 (0x0000072C)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S1_PMON_EVNTSEL1 is defined as MSR_S1_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_S1_PMON_EVNTSEL1           0x0000072C
+
+
+/**
+  Package. Uncore SBo 1 perfmon event select for SBo 1 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_S1_PMON_EVNTSEL2 (0x0000072D)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S1_PMON_EVNTSEL2 is defined as MSR_S1_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_S1_PMON_EVNTSEL2           0x0000072D
+
+
+/**
+  Package. Uncore SBo 1 perfmon event select for SBo 1 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_S1_PMON_EVNTSEL3 (0x0000072E)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S1_PMON_EVNTSEL3 is defined as MSR_S1_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_S1_PMON_EVNTSEL3           0x0000072E
+
+
+/**
+  Package. Uncore SBo 1 perfmon box-wide filter.
+
+  @param  ECX  MSR_HASWELL_E_S1_PMON_BOX_FILTER (0x0000072F)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_BOX_FILTER);
+  AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_BOX_FILTER, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S1_PMON_BOX_FILTER is defined as MSR_S1_PMON_BOX_FILTER in SDM.
+**/
+#define MSR_HASWELL_E_S1_PMON_BOX_FILTER         0x0000072F
+
+
+/**
+  Package. Uncore SBo 1 perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_S1_PMON_CTR0 (0x00000730)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S1_PMON_CTR0 is defined as MSR_S1_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_S1_PMON_CTR0               0x00000730
+
+
+/**
+  Package. Uncore SBo 1 perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_S1_PMON_CTR1 (0x00000731)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S1_PMON_CTR1 is defined as MSR_S1_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_S1_PMON_CTR1               0x00000731
+
+
+/**
+  Package. Uncore SBo 1 perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_S1_PMON_CTR2 (0x00000732)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S1_PMON_CTR2 is defined as MSR_S1_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_S1_PMON_CTR2               0x00000732
+
+
+/**
+  Package. Uncore SBo 1 perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_S1_PMON_CTR3 (0x00000733)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S1_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_S1_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S1_PMON_CTR3 is defined as MSR_S1_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_S1_PMON_CTR3               0x00000733
+
+
+/**
+  Package. Uncore SBo 2 perfmon for SBo 2 box-wide control.
+
+  @param  ECX  MSR_HASWELL_E_S2_PMON_BOX_CTL (0x00000734)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S2_PMON_BOX_CTL is defined as MSR_S2_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_S2_PMON_BOX_CTL            0x00000734
+
+
+/**
+  Package. Uncore SBo 2 perfmon event select for SBo 2 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_S2_PMON_EVNTSEL0 (0x00000735)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S2_PMON_EVNTSEL0 is defined as MSR_S2_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_S2_PMON_EVNTSEL0           0x00000735
+
+
+/**
+  Package. Uncore SBo 2 perfmon event select for SBo 2 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_S2_PMON_EVNTSEL1 (0x00000736)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S2_PMON_EVNTSEL1 is defined as MSR_S2_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_S2_PMON_EVNTSEL1           0x00000736
+
+
+/**
+  Package. Uncore SBo 2 perfmon event select for SBo 2 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_S2_PMON_EVNTSEL2 (0x00000737)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S2_PMON_EVNTSEL2 is defined as MSR_S2_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_S2_PMON_EVNTSEL2           0x00000737
+
+
+/**
+  Package. Uncore SBo 2 perfmon event select for SBo 2 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_S2_PMON_EVNTSEL3 (0x00000738)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S2_PMON_EVNTSEL3 is defined as MSR_S2_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_S2_PMON_EVNTSEL3           0x00000738
+
+
+/**
+  Package. Uncore SBo 2 perfmon box-wide filter.
+
+  @param  ECX  MSR_HASWELL_E_S2_PMON_BOX_FILTER (0x00000739)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_BOX_FILTER);
+  AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_BOX_FILTER, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S2_PMON_BOX_FILTER is defined as MSR_S2_PMON_BOX_FILTER in SDM.
+**/
+#define MSR_HASWELL_E_S2_PMON_BOX_FILTER         0x00000739
+
+
+/**
+  Package. Uncore SBo 2 perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_S2_PMON_CTR0 (0x0000073A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S2_PMON_CTR0 is defined as MSR_S2_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_S2_PMON_CTR0               0x0000073A
+
+
+/**
+  Package. Uncore SBo 2 perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_S2_PMON_CTR1 (0x0000073B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S2_PMON_CTR1 is defined as MSR_S2_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_S2_PMON_CTR1               0x0000073B
+
+
+/**
+  Package. Uncore SBo 2 perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_S2_PMON_CTR2 (0x0000073C)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S2_PMON_CTR2 is defined as MSR_S2_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_S2_PMON_CTR2               0x0000073C
+
+
+/**
+  Package. Uncore SBo 2 perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_S2_PMON_CTR3 (0x0000073D)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S2_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_S2_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S2_PMON_CTR3 is defined as MSR_S2_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_S2_PMON_CTR3               0x0000073D
+
+
+/**
+  Package. Uncore SBo 3 perfmon for SBo 3 box-wide control.
+
+  @param  ECX  MSR_HASWELL_E_S3_PMON_BOX_CTL (0x0000073E)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S3_PMON_BOX_CTL is defined as MSR_S3_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_S3_PMON_BOX_CTL            0x0000073E
+
+
+/**
+  Package. Uncore SBo 3 perfmon event select for SBo 3 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_S3_PMON_EVNTSEL0 (0x0000073F)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S3_PMON_EVNTSEL0 is defined as MSR_S3_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_S3_PMON_EVNTSEL0           0x0000073F
+
+
+/**
+  Package. Uncore SBo 3 perfmon event select for SBo 3 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_S3_PMON_EVNTSEL1 (0x00000740)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S3_PMON_EVNTSEL1 is defined as MSR_S3_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_S3_PMON_EVNTSEL1           0x00000740
+
+
+/**
+  Package. Uncore SBo 3 perfmon event select for SBo 3 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_S3_PMON_EVNTSEL2 (0x00000741)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S3_PMON_EVNTSEL2 is defined as MSR_S3_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_S3_PMON_EVNTSEL2           0x00000741
+
+
+/**
+  Package. Uncore SBo 3 perfmon event select for SBo 3 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_S3_PMON_EVNTSEL3 (0x00000742)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S3_PMON_EVNTSEL3 is defined as MSR_S3_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_S3_PMON_EVNTSEL3           0x00000742
+
+
+/**
+  Package. Uncore SBo 3 perfmon box-wide filter.
+
+  @param  ECX  MSR_HASWELL_E_S3_PMON_BOX_FILTER (0x00000743)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_BOX_FILTER);
+  AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_BOX_FILTER, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S3_PMON_BOX_FILTER is defined as MSR_S3_PMON_BOX_FILTER in SDM.
+**/
+#define MSR_HASWELL_E_S3_PMON_BOX_FILTER         0x00000743
+
+
+/**
+  Package. Uncore SBo 3 perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_S3_PMON_CTR0 (0x00000744)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S3_PMON_CTR0 is defined as MSR_S3_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_S3_PMON_CTR0               0x00000744
+
+
+/**
+  Package. Uncore SBo 3 perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_S3_PMON_CTR1 (0x00000745)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S3_PMON_CTR1 is defined as MSR_S3_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_S3_PMON_CTR1               0x00000745
+
+
+/**
+  Package. Uncore SBo 3 perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_S3_PMON_CTR2 (0x00000746)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S3_PMON_CTR2 is defined as MSR_S3_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_S3_PMON_CTR2               0x00000746
+
+
+/**
+  Package. Uncore SBo 3 perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_S3_PMON_CTR3 (0x00000747)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_S3_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_S3_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_S3_PMON_CTR3 is defined as MSR_S3_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_S3_PMON_CTR3               0x00000747
+
+
+/**
+  Package. Uncore C-box 0 perfmon for box-wide control.
+
+  @param  ECX  MSR_HASWELL_E_C0_PMON_BOX_CTL (0x00000E00)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C0_PMON_BOX_CTL is defined as MSR_C0_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_C0_PMON_BOX_CTL            0x00000E00
+
+
+/**
+  Package. Uncore C-box 0 perfmon event select for C-box 0 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C0_PMON_EVNTSEL0 (0x00000E01)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C0_PMON_EVNTSEL0 is defined as MSR_C0_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_C0_PMON_EVNTSEL0           0x00000E01
+
+
+/**
+  Package. Uncore C-box 0 perfmon event select for C-box 0 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C0_PMON_EVNTSEL1 (0x00000E02)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C0_PMON_EVNTSEL1 is defined as MSR_C0_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_C0_PMON_EVNTSEL1           0x00000E02
+
+
+/**
+  Package. Uncore C-box 0 perfmon event select for C-box 0 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C0_PMON_EVNTSEL2 (0x00000E03)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C0_PMON_EVNTSEL2 is defined as MSR_C0_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_C0_PMON_EVNTSEL2           0x00000E03
+
+
+/**
+  Package. Uncore C-box 0 perfmon event select for C-box 0 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C0_PMON_EVNTSEL3 (0x00000E04)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C0_PMON_EVNTSEL3 is defined as MSR_C0_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_C0_PMON_EVNTSEL3           0x00000E04
+
+
+/**
+  Package. Uncore C-box 0 perfmon box wide filter 0.
+
+  @param  ECX  MSR_HASWELL_E_C0_PMON_BOX_FILTER0 (0x00000E05)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C0_PMON_BOX_FILTER0 is defined as MSR_C0_PMON_BOX_FILTER0 in SDM.
+**/
+#define MSR_HASWELL_E_C0_PMON_BOX_FILTER0        0x00000E05
+
+
+/**
+  Package. Uncore C-box 0 perfmon box wide filter 1.
+
+  @param  ECX  MSR_HASWELL_E_C0_PMON_BOX_FILTER1 (0x00000E06)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C0_PMON_BOX_FILTER1 is defined as MSR_C0_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_HASWELL_E_C0_PMON_BOX_FILTER1        0x00000E06
+
+
+/**
+  Package. Uncore C-box 0 perfmon box wide status.
+
+  @param  ECX  MSR_HASWELL_E_C0_PMON_BOX_STATUS (0x00000E07)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C0_PMON_BOX_STATUS is defined as MSR_C0_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_C0_PMON_BOX_STATUS         0x00000E07
+
+
+/**
+  Package. Uncore C-box 0 perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C0_PMON_CTR0 (0x00000E08)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_C0_PMON_CTR0               0x00000E08
+
+
+/**
+  Package. Uncore C-box 0 perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C0_PMON_CTR1 (0x00000E09)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_C0_PMON_CTR1               0x00000E09
+
+
+/**
+  Package. Uncore C-box 0 perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C0_PMON_CTR2 (0x00000E0A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_C0_PMON_CTR2               0x00000E0A
+
+
+/**
+  Package. Uncore C-box 0 perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C0_PMON_CTR3 (0x00000E0B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C0_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C0_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_C0_PMON_CTR3               0x00000E0B
+
+
+/**
+  Package. Uncore C-box 1 perfmon for box-wide control.
+
+  @param  ECX  MSR_HASWELL_E_C1_PMON_BOX_CTL (0x00000E10)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C1_PMON_BOX_CTL is defined as MSR_C1_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_C1_PMON_BOX_CTL            0x00000E10
+
+
+/**
+  Package. Uncore C-box 1 perfmon event select for C-box 1 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C1_PMON_EVNTSEL0 (0x00000E11)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C1_PMON_EVNTSEL0 is defined as MSR_C1_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_C1_PMON_EVNTSEL0           0x00000E11
+
+
+/**
+  Package. Uncore C-box 1 perfmon event select for C-box 1 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C1_PMON_EVNTSEL1 (0x00000E12)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C1_PMON_EVNTSEL1 is defined as MSR_C1_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_C1_PMON_EVNTSEL1           0x00000E12
+
+
+/**
+  Package. Uncore C-box 1 perfmon event select for C-box 1 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C1_PMON_EVNTSEL2 (0x00000E13)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C1_PMON_EVNTSEL2 is defined as MSR_C1_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_C1_PMON_EVNTSEL2           0x00000E13
+
+
+/**
+  Package. Uncore C-box 1 perfmon event select for C-box 1 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C1_PMON_EVNTSEL3 (0x00000E14)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C1_PMON_EVNTSEL3 is defined as MSR_C1_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_C1_PMON_EVNTSEL3           0x00000E14
+
+
+/**
+  Package. Uncore C-box 1 perfmon box wide filter 0.
+
+  @param  ECX  MSR_HASWELL_E_C1_PMON_BOX_FILTER0 (0x00000E15)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C1_PMON_BOX_FILTER0 is defined as MSR_C1_PMON_BOX_FILTER0 in SDM.
+**/
+#define MSR_HASWELL_E_C1_PMON_BOX_FILTER0        0x00000E15
+
+
+/**
+  Package. Uncore C-box 1 perfmon box wide filter1.
+
+  @param  ECX  MSR_HASWELL_E_C1_PMON_BOX_FILTER1 (0x00000E16)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C1_PMON_BOX_FILTER1 is defined as MSR_C1_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_HASWELL_E_C1_PMON_BOX_FILTER1        0x00000E16
+
+
+/**
+  Package. Uncore C-box 1 perfmon box wide status.
+
+  @param  ECX  MSR_HASWELL_E_C1_PMON_BOX_STATUS (0x00000E17)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C1_PMON_BOX_STATUS is defined as MSR_C1_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_C1_PMON_BOX_STATUS         0x00000E17
+
+
+/**
+  Package. Uncore C-box 1 perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C1_PMON_CTR0 (0x00000E18)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_C1_PMON_CTR0               0x00000E18
+
+
+/**
+  Package. Uncore C-box 1 perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C1_PMON_CTR1 (0x00000E19)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_C1_PMON_CTR1               0x00000E19
+
+
+/**
+  Package. Uncore C-box 1 perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C1_PMON_CTR2 (0x00000E1A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_C1_PMON_CTR2               0x00000E1A
+
+
+/**
+  Package. Uncore C-box 1 perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C1_PMON_CTR3 (0x00000E1B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C1_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C1_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_C1_PMON_CTR3               0x00000E1B
+
+
+/**
+  Package. Uncore C-box 2 perfmon for box-wide control.
+
+  @param  ECX  MSR_HASWELL_E_C2_PMON_BOX_CTL (0x00000E20)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C2_PMON_BOX_CTL is defined as MSR_C2_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_C2_PMON_BOX_CTL            0x00000E20
+
+
+/**
+  Package. Uncore C-box 2 perfmon event select for C-box 2 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C2_PMON_EVNTSEL0 (0x00000E21)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C2_PMON_EVNTSEL0 is defined as MSR_C2_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_C2_PMON_EVNTSEL0           0x00000E21
+
+
+/**
+  Package. Uncore C-box 2 perfmon event select for C-box 2 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C2_PMON_EVNTSEL1 (0x00000E22)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C2_PMON_EVNTSEL1 is defined as MSR_C2_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_C2_PMON_EVNTSEL1           0x00000E22
+
+
+/**
+  Package. Uncore C-box 2 perfmon event select for C-box 2 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C2_PMON_EVNTSEL2 (0x00000E23)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C2_PMON_EVNTSEL2 is defined as MSR_C2_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_C2_PMON_EVNTSEL2           0x00000E23
+
+
+/**
+  Package. Uncore C-box 2 perfmon event select for C-box 2 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C2_PMON_EVNTSEL3 (0x00000E24)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C2_PMON_EVNTSEL3 is defined as MSR_C2_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_C2_PMON_EVNTSEL3           0x00000E24
+
+
+/**
+  Package. Uncore C-box 2 perfmon box wide filter 0.
+
+  @param  ECX  MSR_HASWELL_E_C2_PMON_BOX_FILTER0 (0x00000E25)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C2_PMON_BOX_FILTER0 is defined as MSR_C2_PMON_BOX_FILTER0 in SDM.
+**/
+#define MSR_HASWELL_E_C2_PMON_BOX_FILTER0        0x00000E25
+
+
+/**
+  Package. Uncore C-box 2 perfmon box wide filter1.
+
+  @param  ECX  MSR_HASWELL_E_C2_PMON_BOX_FILTER1 (0x00000E26)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C2_PMON_BOX_FILTER1 is defined as MSR_C2_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_HASWELL_E_C2_PMON_BOX_FILTER1        0x00000E26
+
+
+/**
+  Package. Uncore C-box 2 perfmon box wide status.
+
+  @param  ECX  MSR_HASWELL_E_C2_PMON_BOX_STATUS (0x00000E27)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C2_PMON_BOX_STATUS is defined as MSR_C2_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_C2_PMON_BOX_STATUS         0x00000E27
+
+
+/**
+  Package. Uncore C-box 2 perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C2_PMON_CTR0 (0x00000E28)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_C2_PMON_CTR0               0x00000E28
+
+
+/**
+  Package. Uncore C-box 2 perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C2_PMON_CTR1 (0x00000E29)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_C2_PMON_CTR1               0x00000E29
+
+
+/**
+  Package. Uncore C-box 2 perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C2_PMON_CTR2 (0x00000E2A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_C2_PMON_CTR2               0x00000E2A
+
+
+/**
+  Package. Uncore C-box 2 perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C2_PMON_CTR3 (0x00000E2B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C2_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C2_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_C2_PMON_CTR3               0x00000E2B
+
+
+/**
+  Package. Uncore C-box 3 perfmon for box-wide control.
+
+  @param  ECX  MSR_HASWELL_E_C3_PMON_BOX_CTL (0x00000E30)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C3_PMON_BOX_CTL is defined as MSR_C3_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_C3_PMON_BOX_CTL            0x00000E30
+
+
+/**
+  Package. Uncore C-box 3 perfmon event select for C-box 3 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C3_PMON_EVNTSEL0 (0x00000E31)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C3_PMON_EVNTSEL0 is defined as MSR_C3_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_C3_PMON_EVNTSEL0           0x00000E31
+
+
+/**
+  Package. Uncore C-box 3 perfmon event select for C-box 3 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C3_PMON_EVNTSEL1 (0x00000E32)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C3_PMON_EVNTSEL1 is defined as MSR_C3_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_C3_PMON_EVNTSEL1           0x00000E32
+
+
+/**
+  Package. Uncore C-box 3 perfmon event select for C-box 3 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C3_PMON_EVNTSEL2 (0x00000E33)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C3_PMON_EVNTSEL2 is defined as MSR_C3_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_C3_PMON_EVNTSEL2           0x00000E33
+
+
+/**
+  Package. Uncore C-box 3 perfmon event select for C-box 3 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C3_PMON_EVNTSEL3 (0x00000E34)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C3_PMON_EVNTSEL3 is defined as MSR_C3_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_C3_PMON_EVNTSEL3           0x00000E34
+
+
+/**
+  Package. Uncore C-box 3 perfmon box wide filter 0.
+
+  @param  ECX  MSR_HASWELL_E_C3_PMON_BOX_FILTER0 (0x00000E35)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C3_PMON_BOX_FILTER0 is defined as MSR_C3_PMON_BOX_FILTER0 in SDM.
+**/
+#define MSR_HASWELL_E_C3_PMON_BOX_FILTER0        0x00000E35
+
+
+/**
+  Package. Uncore C-box 3 perfmon box wide filter1.
+
+  @param  ECX  MSR_HASWELL_E_C3_PMON_BOX_FILTER1 (0x00000E36)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C3_PMON_BOX_FILTER1 is defined as MSR_C3_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_HASWELL_E_C3_PMON_BOX_FILTER1        0x00000E36
+
+
+/**
+  Package. Uncore C-box 3 perfmon box wide status.
+
+  @param  ECX  MSR_HASWELL_E_C3_PMON_BOX_STATUS (0x00000E37)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C3_PMON_BOX_STATUS is defined as MSR_C3_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_C3_PMON_BOX_STATUS         0x00000E37
+
+
+/**
+  Package. Uncore C-box 3 perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C3_PMON_CTR0 (0x00000E38)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_C3_PMON_CTR0               0x00000E38
+
+
+/**
+  Package. Uncore C-box 3 perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C3_PMON_CTR1 (0x00000E39)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_C3_PMON_CTR1               0x00000E39
+
+
+/**
+  Package. Uncore C-box 3 perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C3_PMON_CTR2 (0x00000E3A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_C3_PMON_CTR2               0x00000E3A
+
+
+/**
+  Package. Uncore C-box 3 perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C3_PMON_CTR3 (0x00000E3B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C3_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C3_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_C3_PMON_CTR3               0x00000E3B
+
+
+/**
+  Package. Uncore C-box 4 perfmon for box-wide control.
+
+  @param  ECX  MSR_HASWELL_E_C4_PMON_BOX_CTL (0x00000E40)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C4_PMON_BOX_CTL is defined as MSR_C4_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_C4_PMON_BOX_CTL            0x00000E40
+
+
+/**
+  Package. Uncore C-box 4 perfmon event select for C-box 4 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C4_PMON_EVNTSEL0 (0x00000E41)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C4_PMON_EVNTSEL0 is defined as MSR_C4_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_C4_PMON_EVNTSEL0           0x00000E41
+
+
+/**
+  Package. Uncore C-box 4 perfmon event select for C-box 4 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C4_PMON_EVNTSEL1 (0x00000E42)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C4_PMON_EVNTSEL1 is defined as MSR_C4_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_C4_PMON_EVNTSEL1           0x00000E42
+
+
+/**
+  Package. Uncore C-box 4 perfmon event select for C-box 4 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C4_PMON_EVNTSEL2 (0x00000E43)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C4_PMON_EVNTSEL2 is defined as MSR_C4_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_C4_PMON_EVNTSEL2           0x00000E43
+
+
+/**
+  Package. Uncore C-box 4 perfmon event select for C-box 4 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C4_PMON_EVNTSEL3 (0x00000E44)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C4_PMON_EVNTSEL3 is defined as MSR_C4_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_C4_PMON_EVNTSEL3           0x00000E44
+
+
+/**
+  Package. Uncore C-box 4 perfmon box wide filter 0.
+
+  @param  ECX  MSR_HASWELL_E_C4_PMON_BOX_FILTER0 (0x00000E45)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C4_PMON_BOX_FILTER0 is defined as MSR_C4_PMON_BOX_FILTER0 in SDM.
+**/
+#define MSR_HASWELL_E_C4_PMON_BOX_FILTER0        0x00000E45
+
+
+/**
+  Package. Uncore C-box 4 perfmon box wide filter1.
+
+  @param  ECX  MSR_HASWELL_E_C4_PMON_BOX_FILTER1 (0x00000E46)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C4_PMON_BOX_FILTER1 is defined as MSR_C4_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_HASWELL_E_C4_PMON_BOX_FILTER1        0x00000E46
+
+
+/**
+  Package. Uncore C-box 4 perfmon box wide status.
+
+  @param  ECX  MSR_HASWELL_E_C4_PMON_BOX_STATUS (0x00000E47)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C4_PMON_BOX_STATUS is defined as MSR_C4_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_C4_PMON_BOX_STATUS         0x00000E47
+
+
+/**
+  Package. Uncore C-box 4 perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C4_PMON_CTR0 (0x00000E48)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_C4_PMON_CTR0               0x00000E48
+
+
+/**
+  Package. Uncore C-box 4 perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C4_PMON_CTR1 (0x00000E49)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_C4_PMON_CTR1               0x00000E49
+
+
+/**
+  Package. Uncore C-box 4 perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C4_PMON_CTR2 (0x00000E4A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_C4_PMON_CTR2               0x00000E4A
+
+
+/**
+  Package. Uncore C-box 4 perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C4_PMON_CTR3 (0x00000E4B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C4_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C4_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_C4_PMON_CTR3               0x00000E4B
+
+
+/**
+  Package. Uncore C-box 5 perfmon for box-wide control.
+
+  @param  ECX  MSR_HASWELL_E_C5_PMON_BOX_CTL (0x00000E50)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C5_PMON_BOX_CTL is defined as MSR_C5_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_C5_PMON_BOX_CTL            0x00000E50
+
+
+/**
+  Package. Uncore C-box 5 perfmon event select for C-box 5 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C5_PMON_EVNTSEL0 (0x00000E51)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C5_PMON_EVNTSEL0 is defined as MSR_C5_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_C5_PMON_EVNTSEL0           0x00000E51
+
+
+/**
+  Package. Uncore C-box 5 perfmon event select for C-box 5 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C5_PMON_EVNTSEL1 (0x00000E52)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C5_PMON_EVNTSEL1 is defined as MSR_C5_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_C5_PMON_EVNTSEL1           0x00000E52
+
+
+/**
+  Package. Uncore C-box 5 perfmon event select for C-box 5 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C5_PMON_EVNTSEL2 (0x00000E53)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C5_PMON_EVNTSEL2 is defined as MSR_C5_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_C5_PMON_EVNTSEL2           0x00000E53
+
+
+/**
+  Package. Uncore C-box 5 perfmon event select for C-box 5 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C5_PMON_EVNTSEL3 (0x00000E54)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C5_PMON_EVNTSEL3 is defined as MSR_C5_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_C5_PMON_EVNTSEL3           0x00000E54
+
+
+/**
+  Package. Uncore C-box 5 perfmon box wide filter 0.
+
+  @param  ECX  MSR_HASWELL_E_C5_PMON_BOX_FILTER0 (0x00000E55)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C5_PMON_BOX_FILTER0 is defined as MSR_C5_PMON_BOX_FILTER0 in SDM.
+**/
+#define MSR_HASWELL_E_C5_PMON_BOX_FILTER0        0x00000E55
+
+
+/**
+  Package. Uncore C-box 5 perfmon box wide filter1.
+
+  @param  ECX  MSR_HASWELL_E_C5_PMON_BOX_FILTER1 (0x00000E56)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C5_PMON_BOX_FILTER1 is defined as MSR_C5_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_HASWELL_E_C5_PMON_BOX_FILTER1        0x00000E56
+
+
+/**
+  Package. Uncore C-box 5 perfmon box wide status.
+
+  @param  ECX  MSR_HASWELL_E_C5_PMON_BOX_STATUS (0x00000E57)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C5_PMON_BOX_STATUS is defined as MSR_C5_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_C5_PMON_BOX_STATUS         0x00000E57
+
+
+/**
+  Package. Uncore C-box 5 perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C5_PMON_CTR0 (0x00000E58)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_C5_PMON_CTR0               0x00000E58
+
+
+/**
+  Package. Uncore C-box 5 perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C5_PMON_CTR1 (0x00000E59)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_C5_PMON_CTR1               0x00000E59
+
+
+/**
+  Package. Uncore C-box 5 perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C5_PMON_CTR2 (0x00000E5A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_C5_PMON_CTR2               0x00000E5A
+
+
+/**
+  Package. Uncore C-box 5 perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C5_PMON_CTR3 (0x00000E5B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C5_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C5_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_C5_PMON_CTR3               0x00000E5B
+
+
+/**
+  Package. Uncore C-box 6 perfmon for box-wide control.
+
+  @param  ECX  MSR_HASWELL_E_C6_PMON_BOX_CTL (0x00000E60)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C6_PMON_BOX_CTL is defined as MSR_C6_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_C6_PMON_BOX_CTL            0x00000E60
+
+
+/**
+  Package. Uncore C-box 6 perfmon event select for C-box 6 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C6_PMON_EVNTSEL0 (0x00000E61)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C6_PMON_EVNTSEL0 is defined as MSR_C6_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_C6_PMON_EVNTSEL0           0x00000E61
+
+
+/**
+  Package. Uncore C-box 6 perfmon event select for C-box 6 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C6_PMON_EVNTSEL1 (0x00000E62)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C6_PMON_EVNTSEL1 is defined as MSR_C6_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_C6_PMON_EVNTSEL1           0x00000E62
+
+
+/**
+  Package. Uncore C-box 6 perfmon event select for C-box 6 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C6_PMON_EVNTSEL2 (0x00000E63)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C6_PMON_EVNTSEL2 is defined as MSR_C6_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_C6_PMON_EVNTSEL2           0x00000E63
+
+
+/**
+  Package. Uncore C-box 6 perfmon event select for C-box 6 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C6_PMON_EVNTSEL3 (0x00000E64)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C6_PMON_EVNTSEL3 is defined as MSR_C6_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_C6_PMON_EVNTSEL3           0x00000E64
+
+
+/**
+  Package. Uncore C-box 6 perfmon box wide filter 0.
+
+  @param  ECX  MSR_HASWELL_E_C6_PMON_BOX_FILTER0 (0x00000E65)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C6_PMON_BOX_FILTER0 is defined as MSR_C6_PMON_BOX_FILTER0 in SDM.
+**/
+#define MSR_HASWELL_E_C6_PMON_BOX_FILTER0        0x00000E65
+
+
+/**
+  Package. Uncore C-box 6 perfmon box wide filter1.
+
+  @param  ECX  MSR_HASWELL_E_C6_PMON_BOX_FILTER1 (0x00000E66)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C6_PMON_BOX_FILTER1 is defined as MSR_C6_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_HASWELL_E_C6_PMON_BOX_FILTER1        0x00000E66
+
+
+/**
+  Package. Uncore C-box 6 perfmon box wide status.
+
+  @param  ECX  MSR_HASWELL_E_C6_PMON_BOX_STATUS (0x00000E67)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C6_PMON_BOX_STATUS is defined as MSR_C6_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_C6_PMON_BOX_STATUS         0x00000E67
+
+
+/**
+  Package. Uncore C-box 6 perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C6_PMON_CTR0 (0x00000E68)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_C6_PMON_CTR0               0x00000E68
+
+
+/**
+  Package. Uncore C-box 6 perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C6_PMON_CTR1 (0x00000E69)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_C6_PMON_CTR1               0x00000E69
+
+
+/**
+  Package. Uncore C-box 6 perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C6_PMON_CTR2 (0x00000E6A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_C6_PMON_CTR2               0x00000E6A
+
+
+/**
+  Package. Uncore C-box 6 perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C6_PMON_CTR3 (0x00000E6B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C6_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C6_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_C6_PMON_CTR3               0x00000E6B
+
+
+/**
+  Package. Uncore C-box 7 perfmon for box-wide control.
+
+  @param  ECX  MSR_HASWELL_E_C7_PMON_BOX_CTL (0x00000E70)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C7_PMON_BOX_CTL is defined as MSR_C7_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_C7_PMON_BOX_CTL            0x00000E70
+
+
+/**
+  Package. Uncore C-box 7 perfmon event select for C-box 7 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C7_PMON_EVNTSEL0 (0x00000E71)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C7_PMON_EVNTSEL0 is defined as MSR_C7_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_C7_PMON_EVNTSEL0           0x00000E71
+
+
+/**
+  Package. Uncore C-box 7 perfmon event select for C-box 7 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C7_PMON_EVNTSEL1 (0x00000E72)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C7_PMON_EVNTSEL1 is defined as MSR_C7_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_C7_PMON_EVNTSEL1           0x00000E72
+
+
+/**
+  Package. Uncore C-box 7 perfmon event select for C-box 7 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C7_PMON_EVNTSEL2 (0x00000E73)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C7_PMON_EVNTSEL2 is defined as MSR_C7_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_C7_PMON_EVNTSEL2           0x00000E73
+
+
+/**
+  Package. Uncore C-box 7 perfmon event select for C-box 7 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C7_PMON_EVNTSEL3 (0x00000E74)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C7_PMON_EVNTSEL3 is defined as MSR_C7_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_C7_PMON_EVNTSEL3           0x00000E74
+
+
+/**
+  Package. Uncore C-box 7 perfmon box wide filter 0.
+
+  @param  ECX  MSR_HASWELL_E_C7_PMON_BOX_FILTER0 (0x00000E75)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C7_PMON_BOX_FILTER0 is defined as MSR_C7_PMON_BOX_FILTER0 in SDM.
+**/
+#define MSR_HASWELL_E_C7_PMON_BOX_FILTER0        0x00000E75
+
+
+/**
+  Package. Uncore C-box 7 perfmon box wide filter1.
+
+  @param  ECX  MSR_HASWELL_E_C7_PMON_BOX_FILTER1 (0x00000E76)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C7_PMON_BOX_FILTER1 is defined as MSR_C7_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_HASWELL_E_C7_PMON_BOX_FILTER1        0x00000E76
+
+
+/**
+  Package. Uncore C-box 7 perfmon box wide status.
+
+  @param  ECX  MSR_HASWELL_E_C7_PMON_BOX_STATUS (0x00000E77)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C7_PMON_BOX_STATUS is defined as MSR_C7_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_C7_PMON_BOX_STATUS         0x00000E77
+
+
+/**
+  Package. Uncore C-box 7 perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C7_PMON_CTR0 (0x00000E78)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_C7_PMON_CTR0               0x00000E78
+
+
+/**
+  Package. Uncore C-box 7 perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C7_PMON_CTR1 (0x00000E79)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_C7_PMON_CTR1               0x00000E79
+
+
+/**
+  Package. Uncore C-box 7 perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C7_PMON_CTR2 (0x00000E7A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_C7_PMON_CTR2               0x00000E7A
+
+
+/**
+  Package. Uncore C-box 7 perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C7_PMON_CTR3 (0x00000E7B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C7_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C7_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_C7_PMON_CTR3               0x00000E7B
+
+
+/**
+  Package. Uncore C-box 8 perfmon local box wide control.
+
+  @param  ECX  MSR_HASWELL_E_C8_PMON_BOX_CTL (0x00000E80)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C8_PMON_BOX_CTL is defined as MSR_C8_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_C8_PMON_BOX_CTL            0x00000E80
+
+
+/**
+  Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C8_PMON_EVNTSEL0 (0x00000E81)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C8_PMON_EVNTSEL0 is defined as MSR_C8_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_C8_PMON_EVNTSEL0           0x00000E81
+
+
+/**
+  Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C8_PMON_EVNTSEL1 (0x00000E82)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C8_PMON_EVNTSEL1 is defined as MSR_C8_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_C8_PMON_EVNTSEL1           0x00000E82
+
+
+/**
+  Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C8_PMON_EVNTSEL2 (0x00000E83)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C8_PMON_EVNTSEL2 is defined as MSR_C8_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_C8_PMON_EVNTSEL2           0x00000E83
+
+
+/**
+  Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C8_PMON_EVNTSEL3 (0x00000E84)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C8_PMON_EVNTSEL3 is defined as MSR_C8_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_C8_PMON_EVNTSEL3           0x00000E84
+
+
+/**
+  Package. Uncore C-box 8 perfmon box wide filter0.
+
+  @param  ECX  MSR_HASWELL_E_C8_PMON_BOX_FILTER0 (0x00000E85)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C8_PMON_BOX_FILTER0 is defined as MSR_C8_PMON_BOX_FILTER0 in SDM.
+**/
+#define MSR_HASWELL_E_C8_PMON_BOX_FILTER0        0x00000E85
+
+
+/**
+  Package. Uncore C-box 8 perfmon box wide filter1.
+
+  @param  ECX  MSR_HASWELL_E_C8_PMON_BOX_FILTER1 (0x00000E86)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C8_PMON_BOX_FILTER1 is defined as MSR_C8_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_HASWELL_E_C8_PMON_BOX_FILTER1        0x00000E86
+
+
+/**
+  Package. Uncore C-box 8 perfmon box wide status.
+
+  @param  ECX  MSR_HASWELL_E_C8_PMON_BOX_STATUS (0x00000E87)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_C8_PMON_BOX_STATUS         0x00000E87
+
+
+/**
+  Package. Uncore C-box 8 perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C8_PMON_CTR0 (0x00000E88)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_C8_PMON_CTR0               0x00000E88
+
+
+/**
+  Package. Uncore C-box 8 perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C8_PMON_CTR1 (0x00000E89)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_C8_PMON_CTR1               0x00000E89
+
+
+/**
+  Package. Uncore C-box 8 perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C8_PMON_CTR2 (0x00000E8A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_C8_PMON_CTR2               0x00000E8A
+
+
+/**
+  Package. Uncore C-box 8 perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C8_PMON_CTR3 (0x00000E8B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C8_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C8_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_C8_PMON_CTR3               0x00000E8B
+
+
+/**
+  Package. Uncore C-box 9 perfmon local box wide control.
+
+  @param  ECX  MSR_HASWELL_E_C9_PMON_BOX_CTL (0x00000E90)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C9_PMON_BOX_CTL is defined as MSR_C9_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_C9_PMON_BOX_CTL            0x00000E90
+
+
+/**
+  Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C9_PMON_EVNTSEL0 (0x00000E91)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C9_PMON_EVNTSEL0 is defined as MSR_C9_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_C9_PMON_EVNTSEL0           0x00000E91
+
+
+/**
+  Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C9_PMON_EVNTSEL1 (0x00000E92)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C9_PMON_EVNTSEL1 is defined as MSR_C9_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_C9_PMON_EVNTSEL1           0x00000E92
+
+
+/**
+  Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C9_PMON_EVNTSEL2 (0x00000E93)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C9_PMON_EVNTSEL2 is defined as MSR_C9_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_C9_PMON_EVNTSEL2           0x00000E93
+
+
+/**
+  Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C9_PMON_EVNTSEL3 (0x00000E94)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C9_PMON_EVNTSEL3 is defined as MSR_C9_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_C9_PMON_EVNTSEL3           0x00000E94
+
+
+/**
+  Package. Uncore C-box 9 perfmon box wide filter0.
+
+  @param  ECX  MSR_HASWELL_E_C9_PMON_BOX_FILTER0 (0x00000E95)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C9_PMON_BOX_FILTER0 is defined as MSR_C9_PMON_BOX_FILTER0 in SDM.
+**/
+#define MSR_HASWELL_E_C9_PMON_BOX_FILTER0        0x00000E95
+
+
+/**
+  Package. Uncore C-box 9 perfmon box wide filter1.
+
+  @param  ECX  MSR_HASWELL_E_C9_PMON_BOX_FILTER1 (0x00000E96)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C9_PMON_BOX_FILTER1 is defined as MSR_C9_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_HASWELL_E_C9_PMON_BOX_FILTER1        0x00000E96
+
+
+/**
+  Package. Uncore C-box 9 perfmon box wide status.
+
+  @param  ECX  MSR_HASWELL_E_C9_PMON_BOX_STATUS (0x00000E97)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_C9_PMON_BOX_STATUS         0x00000E97
+
+
+/**
+  Package. Uncore C-box 9 perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C9_PMON_CTR0 (0x00000E98)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_C9_PMON_CTR0               0x00000E98
+
+
+/**
+  Package. Uncore C-box 9 perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C9_PMON_CTR1 (0x00000E99)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_C9_PMON_CTR1               0x00000E99
+
+
+/**
+  Package. Uncore C-box 9 perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C9_PMON_CTR2 (0x00000E9A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_C9_PMON_CTR2               0x00000E9A
+
+
+/**
+  Package. Uncore C-box 9 perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C9_PMON_CTR3 (0x00000E9B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C9_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C9_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_C9_PMON_CTR3               0x00000E9B
+
+
+/**
+  Package. Uncore C-box 10 perfmon local box wide control.
+
+  @param  ECX  MSR_HASWELL_E_C10_PMON_BOX_CTL (0x00000EA0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C10_PMON_BOX_CTL is defined as MSR_C10_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_C10_PMON_BOX_CTL           0x00000EA0
+
+
+/**
+  Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C10_PMON_EVNTSEL0 (0x00000EA1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C10_PMON_EVNTSEL0 is defined as MSR_C10_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_C10_PMON_EVNTSEL0          0x00000EA1
+
+
+/**
+  Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C10_PMON_EVNTSEL1 (0x00000EA2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C10_PMON_EVNTSEL1 is defined as MSR_C10_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_C10_PMON_EVNTSEL1          0x00000EA2
+
+
+/**
+  Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C10_PMON_EVNTSEL2 (0x00000EA3)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C10_PMON_EVNTSEL2 is defined as MSR_C10_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_C10_PMON_EVNTSEL2          0x00000EA3
+
+
+/**
+  Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C10_PMON_EVNTSEL3 (0x00000EA4)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C10_PMON_EVNTSEL3 is defined as MSR_C10_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_C10_PMON_EVNTSEL3          0x00000EA4
+
+
+/**
+  Package. Uncore C-box 10 perfmon box wide filter0.
+
+  @param  ECX  MSR_HASWELL_E_C10_PMON_BOX_FILTER0 (0x00000EA5)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C10_PMON_BOX_FILTER0 is defined as MSR_C10_PMON_BOX_FILTER0 in SDM.
+**/
+#define MSR_HASWELL_E_C10_PMON_BOX_FILTER0       0x00000EA5
+
+
+/**
+  Package. Uncore C-box 10 perfmon box wide filter1.
+
+  @param  ECX  MSR_HASWELL_E_C10_PMON_BOX_FILTER1 (0x00000EA6)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C10_PMON_BOX_FILTER1 is defined as MSR_C10_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_HASWELL_E_C10_PMON_BOX_FILTER1       0x00000EA6
+
+
+/**
+  Package. Uncore C-box 10 perfmon box wide status.
+
+  @param  ECX  MSR_HASWELL_E_C10_PMON_BOX_STATUS (0x00000EA7)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C10_PMON_BOX_STATUS is defined as MSR_C10_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_C10_PMON_BOX_STATUS        0x00000EA7
+
+
+/**
+  Package. Uncore C-box 10 perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C10_PMON_CTR0 (0x00000EA8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C10_PMON_CTR0 is defined as MSR_C10_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_C10_PMON_CTR0              0x00000EA8
+
+
+/**
+  Package. Uncore C-box 10 perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C10_PMON_CTR1 (0x00000EA9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C10_PMON_CTR1 is defined as MSR_C10_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_C10_PMON_CTR1              0x00000EA9
+
+
+/**
+  Package. Uncore C-box 10 perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C10_PMON_CTR2 (0x00000EAA)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C10_PMON_CTR2 is defined as MSR_C10_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_C10_PMON_CTR2              0x00000EAA
+
+
+/**
+  Package. Uncore C-box 10 perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C10_PMON_CTR3 (0x00000EAB)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C10_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C10_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C10_PMON_CTR3 is defined as MSR_C10_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_C10_PMON_CTR3              0x00000EAB
+
+
+/**
+  Package. Uncore C-box 11 perfmon local box wide control.
+
+  @param  ECX  MSR_HASWELL_E_C11_PMON_BOX_CTL (0x00000EB0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C11_PMON_BOX_CTL is defined as MSR_C11_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_C11_PMON_BOX_CTL           0x00000EB0
+
+
+/**
+  Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C11_PMON_EVNTSEL0 (0x00000EB1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C11_PMON_EVNTSEL0 is defined as MSR_C11_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_C11_PMON_EVNTSEL0          0x00000EB1
+
+
+/**
+  Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C11_PMON_EVNTSEL1 (0x00000EB2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C11_PMON_EVNTSEL1 is defined as MSR_C11_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_C11_PMON_EVNTSEL1          0x00000EB2
+
+
+/**
+  Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C11_PMON_EVNTSEL2 (0x00000EB3)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C11_PMON_EVNTSEL2 is defined as MSR_C11_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_C11_PMON_EVNTSEL2          0x00000EB3
+
+
+/**
+  Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C11_PMON_EVNTSEL3 (0x00000EB4)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C11_PMON_EVNTSEL3 is defined as MSR_C11_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_C11_PMON_EVNTSEL3          0x00000EB4
+
+
+/**
+  Package. Uncore C-box 11 perfmon box wide filter0.
+
+  @param  ECX  MSR_HASWELL_E_C11_PMON_BOX_FILTER0 (0x00000EB5)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C11_PMON_BOX_FILTER0 is defined as MSR_C11_PMON_BOX_FILTER0 in SDM.
+**/
+#define MSR_HASWELL_E_C11_PMON_BOX_FILTER0       0x00000EB5
+
+
+/**
+  Package. Uncore C-box 11 perfmon box wide filter1.
+
+  @param  ECX  MSR_HASWELL_E_C11_PMON_BOX_FILTER1 (0x00000EB6)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C11_PMON_BOX_FILTER1 is defined as MSR_C11_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_HASWELL_E_C11_PMON_BOX_FILTER1       0x00000EB6
+
+
+/**
+  Package. Uncore C-box 11 perfmon box wide status.
+
+  @param  ECX  MSR_HASWELL_E_C11_PMON_BOX_STATUS (0x00000EB7)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C11_PMON_BOX_STATUS is defined as MSR_C11_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_C11_PMON_BOX_STATUS        0x00000EB7
+
+
+/**
+  Package. Uncore C-box 11 perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C11_PMON_CTR0 (0x00000EB8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C11_PMON_CTR0 is defined as MSR_C11_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_C11_PMON_CTR0              0x00000EB8
+
+
+/**
+  Package. Uncore C-box 11 perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C11_PMON_CTR1 (0x00000EB9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C11_PMON_CTR1 is defined as MSR_C11_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_C11_PMON_CTR1              0x00000EB9
+
+
+/**
+  Package. Uncore C-box 11 perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C11_PMON_CTR2 (0x00000EBA)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C11_PMON_CTR2 is defined as MSR_C11_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_C11_PMON_CTR2              0x00000EBA
+
+
+/**
+  Package. Uncore C-box 11 perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C11_PMON_CTR3 (0x00000EBB)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C11_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C11_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C11_PMON_CTR3 is defined as MSR_C11_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_C11_PMON_CTR3              0x00000EBB
+
+
+/**
+  Package. Uncore C-box 12 perfmon local box wide control.
+
+  @param  ECX  MSR_HASWELL_E_C12_PMON_BOX_CTL (0x00000EC0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C12_PMON_BOX_CTL is defined as MSR_C12_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_C12_PMON_BOX_CTL           0x00000EC0
+
+
+/**
+  Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C12_PMON_EVNTSEL0 (0x00000EC1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C12_PMON_EVNTSEL0 is defined as MSR_C12_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_C12_PMON_EVNTSEL0          0x00000EC1
+
+
+/**
+  Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C12_PMON_EVNTSEL1 (0x00000EC2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C12_PMON_EVNTSEL1 is defined as MSR_C12_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_C12_PMON_EVNTSEL1          0x00000EC2
+
+
+/**
+  Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C12_PMON_EVNTSEL2 (0x00000EC3)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C12_PMON_EVNTSEL2 is defined as MSR_C12_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_C12_PMON_EVNTSEL2          0x00000EC3
+
+
+/**
+  Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C12_PMON_EVNTSEL3 (0x00000EC4)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C12_PMON_EVNTSEL3 is defined as MSR_C12_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_C12_PMON_EVNTSEL3          0x00000EC4
+
+
+/**
+  Package. Uncore C-box 12 perfmon box wide filter0.
+
+  @param  ECX  MSR_HASWELL_E_C12_PMON_BOX_FILTER0 (0x00000EC5)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C12_PMON_BOX_FILTER0 is defined as MSR_C12_PMON_BOX_FILTER0 in SDM.
+**/
+#define MSR_HASWELL_E_C12_PMON_BOX_FILTER0       0x00000EC5
+
+
+/**
+  Package. Uncore C-box 12 perfmon box wide filter1.
+
+  @param  ECX  MSR_HASWELL_E_C12_PMON_BOX_FILTER1 (0x00000EC6)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C12_PMON_BOX_FILTER1 is defined as MSR_C12_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_HASWELL_E_C12_PMON_BOX_FILTER1       0x00000EC6
+
+
+/**
+  Package. Uncore C-box 12 perfmon box wide status.
+
+  @param  ECX  MSR_HASWELL_E_C12_PMON_BOX_STATUS (0x00000EC7)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C12_PMON_BOX_STATUS is defined as MSR_C12_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_C12_PMON_BOX_STATUS        0x00000EC7
+
+
+/**
+  Package. Uncore C-box 12 perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C12_PMON_CTR0 (0x00000EC8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C12_PMON_CTR0 is defined as MSR_C12_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_C12_PMON_CTR0              0x00000EC8
+
+
+/**
+  Package. Uncore C-box 12 perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C12_PMON_CTR1 (0x00000EC9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C12_PMON_CTR1 is defined as MSR_C12_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_C12_PMON_CTR1              0x00000EC9
+
+
+/**
+  Package. Uncore C-box 12 perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C12_PMON_CTR2 (0x00000ECA)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C12_PMON_CTR2 is defined as MSR_C12_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_C12_PMON_CTR2              0x00000ECA
+
+
+/**
+  Package. Uncore C-box 12 perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C12_PMON_CTR3 (0x00000ECB)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C12_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C12_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C12_PMON_CTR3 is defined as MSR_C12_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_C12_PMON_CTR3              0x00000ECB
+
+
+/**
+  Package. Uncore C-box 13 perfmon local box wide control.
+
+  @param  ECX  MSR_HASWELL_E_C13_PMON_BOX_CTL (0x00000ED0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C13_PMON_BOX_CTL is defined as MSR_C13_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_C13_PMON_BOX_CTL           0x00000ED0
+
+
+/**
+  Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C13_PMON_EVNTSEL0 (0x00000ED1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C13_PMON_EVNTSEL0 is defined as MSR_C13_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_C13_PMON_EVNTSEL0          0x00000ED1
+
+
+/**
+  Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C13_PMON_EVNTSEL1 (0x00000ED2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C13_PMON_EVNTSEL1 is defined as MSR_C13_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_C13_PMON_EVNTSEL1          0x00000ED2
+
+
+/**
+  Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C13_PMON_EVNTSEL2 (0x00000ED3)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C13_PMON_EVNTSEL2 is defined as MSR_C13_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_C13_PMON_EVNTSEL2          0x00000ED3
+
+
+/**
+  Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C13_PMON_EVNTSEL3 (0x00000ED4)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C13_PMON_EVNTSEL3 is defined as MSR_C13_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_C13_PMON_EVNTSEL3          0x00000ED4
+
+
+/**
+  Package. Uncore C-box 13 perfmon box wide filter0.
+
+  @param  ECX  MSR_HASWELL_E_C13_PMON_BOX_FILTER0 (0x00000ED5)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C13_PMON_BOX_FILTER0 is defined as MSR_C13_PMON_BOX_FILTER0 in SDM.
+**/
+#define MSR_HASWELL_E_C13_PMON_BOX_FILTER0       0x00000ED5
+
+
+/**
+  Package. Uncore C-box 13 perfmon box wide filter1.
+
+  @param  ECX  MSR_HASWELL_E_C13_PMON_BOX_FILTER1 (0x00000ED6)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C13_PMON_BOX_FILTER1 is defined as MSR_C13_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_HASWELL_E_C13_PMON_BOX_FILTER1       0x00000ED6
+
+
+/**
+  Package. Uncore C-box 13 perfmon box wide status.
+
+  @param  ECX  MSR_HASWELL_E_C13_PMON_BOX_STATUS (0x00000ED7)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C13_PMON_BOX_STATUS is defined as MSR_C13_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_C13_PMON_BOX_STATUS        0x00000ED7
+
+
+/**
+  Package. Uncore C-box 13 perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C13_PMON_CTR0 (0x00000ED8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C13_PMON_CTR0 is defined as MSR_C13_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_C13_PMON_CTR0              0x00000ED8
+
+
+/**
+  Package. Uncore C-box 13 perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C13_PMON_CTR1 (0x00000ED9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C13_PMON_CTR1 is defined as MSR_C13_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_C13_PMON_CTR1              0x00000ED9
+
+
+/**
+  Package. Uncore C-box 13 perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C13_PMON_CTR2 (0x00000EDA)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C13_PMON_CTR2 is defined as MSR_C13_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_C13_PMON_CTR2              0x00000EDA
+
+
+/**
+  Package. Uncore C-box 13 perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C13_PMON_CTR3 (0x00000EDB)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C13_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C13_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C13_PMON_CTR3 is defined as MSR_C13_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_C13_PMON_CTR3              0x00000EDB
+
+
+/**
+  Package. Uncore C-box 14 perfmon local box wide control.
+
+  @param  ECX  MSR_HASWELL_E_C14_PMON_BOX_CTL (0x00000EE0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C14_PMON_BOX_CTL is defined as MSR_C14_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_C14_PMON_BOX_CTL           0x00000EE0
+
+
+/**
+  Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C14_PMON_EVNTSEL0 (0x00000EE1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C14_PMON_EVNTSEL0 is defined as MSR_C14_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_C14_PMON_EVNTSEL0          0x00000EE1
+
+
+/**
+  Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C14_PMON_EVNTSEL1 (0x00000EE2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C14_PMON_EVNTSEL1 is defined as MSR_C14_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_C14_PMON_EVNTSEL1          0x00000EE2
+
+
+/**
+  Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C14_PMON_EVNTSEL2 (0x00000EE3)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C14_PMON_EVNTSEL2 is defined as MSR_C14_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_C14_PMON_EVNTSEL2          0x00000EE3
+
+
+/**
+  Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C14_PMON_EVNTSEL3 (0x00000EE4)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C14_PMON_EVNTSEL3 is defined as MSR_C14_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_C14_PMON_EVNTSEL3          0x00000EE4
+
+
+/**
+  Package. Uncore C-box 14 perfmon box wide filter0.
+
+  @param  ECX  MSR_HASWELL_E_C14_PMON_BOX_FILTER (0x00000EE5)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER);
+  AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C14_PMON_BOX_FILTER is defined as MSR_C14_PMON_BOX_FILTER in SDM.
+**/
+#define MSR_HASWELL_E_C14_PMON_BOX_FILTER        0x00000EE5
+
+
+/**
+  Package. Uncore C-box 14 perfmon box wide filter1.
+
+  @param  ECX  MSR_HASWELL_E_C14_PMON_BOX_FILTER1 (0x00000EE6)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C14_PMON_BOX_FILTER1 is defined as MSR_C14_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_HASWELL_E_C14_PMON_BOX_FILTER1       0x00000EE6
+
+
+/**
+  Package. Uncore C-box 14 perfmon box wide status.
+
+  @param  ECX  MSR_HASWELL_E_C14_PMON_BOX_STATUS (0x00000EE7)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C14_PMON_BOX_STATUS is defined as MSR_C14_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_C14_PMON_BOX_STATUS        0x00000EE7
+
+
+/**
+  Package. Uncore C-box 14 perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C14_PMON_CTR0 (0x00000EE8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C14_PMON_CTR0 is defined as MSR_C14_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_C14_PMON_CTR0              0x00000EE8
+
+
+/**
+  Package. Uncore C-box 14 perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C14_PMON_CTR1 (0x00000EE9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C14_PMON_CTR1 is defined as MSR_C14_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_C14_PMON_CTR1              0x00000EE9
+
+
+/**
+  Package. Uncore C-box 14 perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C14_PMON_CTR2 (0x00000EEA)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C14_PMON_CTR2 is defined as MSR_C14_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_C14_PMON_CTR2              0x00000EEA
+
+
+/**
+  Package. Uncore C-box 14 perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C14_PMON_CTR3 (0x00000EEB)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C14_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C14_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C14_PMON_CTR3 is defined as MSR_C14_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_C14_PMON_CTR3              0x00000EEB
+
+
+/**
+  Package. Uncore C-box 15 perfmon local box wide control.
+
+  @param  ECX  MSR_HASWELL_E_C15_PMON_BOX_CTL (0x00000EF0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C15_PMON_BOX_CTL is defined as MSR_C15_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_C15_PMON_BOX_CTL           0x00000EF0
+
+
+/**
+  Package. Uncore C-box 15 perfmon event select for C-box 15 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C15_PMON_EVNTSEL0 (0x00000EF1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C15_PMON_EVNTSEL0 is defined as MSR_C15_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_C15_PMON_EVNTSEL0          0x00000EF1
+
+
+/**
+  Package. Uncore C-box 15 perfmon event select for C-box 15 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C15_PMON_EVNTSEL1 (0x00000EF2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C15_PMON_EVNTSEL1 is defined as MSR_C15_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_C15_PMON_EVNTSEL1          0x00000EF2
+
+
+/**
+  Package. Uncore C-box 15 perfmon event select for C-box 15 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C15_PMON_EVNTSEL2 (0x00000EF3)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C15_PMON_EVNTSEL2 is defined as MSR_C15_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_C15_PMON_EVNTSEL2          0x00000EF3
+
+
+/**
+  Package. Uncore C-box 15 perfmon event select for C-box 15 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C15_PMON_EVNTSEL3 (0x00000EF4)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C15_PMON_EVNTSEL3 is defined as MSR_C15_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_C15_PMON_EVNTSEL3          0x00000EF4
+
+
+/**
+  Package. Uncore C-box 15 perfmon box wide filter0.
+
+  @param  ECX  MSR_HASWELL_E_C15_PMON_BOX_FILTER0 (0x00000EF5)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C15_PMON_BOX_FILTER0 is defined as MSR_C15_PMON_BOX_FILTER0 in SDM.
+**/
+#define MSR_HASWELL_E_C15_PMON_BOX_FILTER0       0x00000EF5
+
+
+/**
+  Package. Uncore C-box 15 perfmon box wide filter1.
+
+  @param  ECX  MSR_HASWELL_E_C15_PMON_BOX_FILTER1 (0x00000EF6)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C15_PMON_BOX_FILTER1 is defined as MSR_C15_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_HASWELL_E_C15_PMON_BOX_FILTER1       0x00000EF6
+
+
+/**
+  Package. Uncore C-box 15 perfmon box wide status.
+
+  @param  ECX  MSR_HASWELL_E_C15_PMON_BOX_STATUS (0x00000EF7)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C15_PMON_BOX_STATUS is defined as MSR_C15_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_C15_PMON_BOX_STATUS        0x00000EF7
+
+
+/**
+  Package. Uncore C-box 15 perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C15_PMON_CTR0 (0x00000EF8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C15_PMON_CTR0 is defined as MSR_C15_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_C15_PMON_CTR0              0x00000EF8
+
+
+/**
+  Package. Uncore C-box 15 perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C15_PMON_CTR1 (0x00000EF9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C15_PMON_CTR1 is defined as MSR_C15_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_C15_PMON_CTR1              0x00000EF9
+
+
+/**
+  Package. Uncore C-box 15 perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C15_PMON_CTR2 (0x00000EFA)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C15_PMON_CTR2 is defined as MSR_C15_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_C15_PMON_CTR2              0x00000EFA
+
+
+/**
+  Package. Uncore C-box 15 perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C15_PMON_CTR3 (0x00000EFB)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C15_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C15_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C15_PMON_CTR3 is defined as MSR_C15_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_C15_PMON_CTR3              0x00000EFB
+
+
+/**
+  Package. Uncore C-box 16 perfmon for box-wide control.
+
+  @param  ECX  MSR_HASWELL_E_C16_PMON_BOX_CTL (0x00000F00)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C16_PMON_BOX_CTL is defined as MSR_C16_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_C16_PMON_BOX_CTL           0x00000F00
+
+
+/**
+  Package. Uncore C-box 16 perfmon event select for C-box 16 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C16_PMON_EVNTSEL0 (0x00000F01)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C16_PMON_EVNTSEL0 is defined as MSR_C16_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_C16_PMON_EVNTSEL0          0x00000F01
+
+
+/**
+  Package. Uncore C-box 16 perfmon event select for C-box 16 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C16_PMON_EVNTSEL1 (0x00000F02)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C16_PMON_EVNTSEL1 is defined as MSR_C16_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_C16_PMON_EVNTSEL1          0x00000F02
+
+
+/**
+  Package. Uncore C-box 16 perfmon event select for C-box 16 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C16_PMON_EVNTSEL2 (0x00000F03)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C16_PMON_EVNTSEL2 is defined as MSR_C16_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_C16_PMON_EVNTSEL2          0x00000F03
+
+
+/**
+  Package. Uncore C-box 16 perfmon event select for C-box 16 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C16_PMON_EVNTSEL3 (0x00000F04)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C16_PMON_EVNTSEL3 is defined as MSR_C16_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_C16_PMON_EVNTSEL3          0x00000F04
+
+
+/**
+  Package. Uncore C-box 16 perfmon box wide filter 0.
+
+  @param  ECX  MSR_HASWELL_E_C16_PMON_BOX_FILTER0 (0x00000F05)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C16_PMON_BOX_FILTER0 is defined as MSR_C16_PMON_BOX_FILTER0 in SDM.
+**/
+#define MSR_HASWELL_E_C16_PMON_BOX_FILTER0       0x00000F05
+
+
+/**
+  Package. Uncore C-box 16 perfmon box wide filter 1.
+
+  @param  ECX  MSR_HASWELL_E_C16_PMON_BOX_FILTER1 (0x00000F06)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C16_PMON_BOX_FILTER1 is defined as MSR_C16_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_HASWELL_E_C16_PMON_BOX_FILTER1       0x00000F06
+
+
+/**
+  Package. Uncore C-box 16 perfmon box wide status.
+
+  @param  ECX  MSR_HASWELL_E_C16_PMON_BOX_STATUS (0x00000F07)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C16_PMON_BOX_STATUS is defined as MSR_C16_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_C16_PMON_BOX_STATUS        0x00000F07
+
+
+/**
+  Package. Uncore C-box 16 perfmon counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C16_PMON_CTR0 (0x00000F08)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C16_PMON_CTR0 is defined as MSR_C16_PMON_CTR0 in SDM.
+**/
+#define MSR_HASWELL_E_C16_PMON_CTR0              0x00000F08
+
+
+/**
+  Package. Uncore C-box 16 perfmon counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C16_PMON_CTR1 (0x00000F09)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C16_PMON_CTR1 is defined as MSR_C16_PMON_CTR1 in SDM.
+**/
+#define MSR_HASWELL_E_C16_PMON_CTR1              0x00000F09
+
+
+/**
+  Package. Uncore C-box 16 perfmon counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C16_PMON_CTR2 (0x00000F0A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C16_PMON_CTR2 is defined as MSR_C16_PMON_CTR2 in SDM.
+**/
+#define MSR_HASWELL_E_C16_PMON_CTR2              0x00000F0A
+
+
+/**
+  Package. Uncore C-box 16 perfmon counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C16_PMON_CTR3 (0x00000E0B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C16_PMON_CTR3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C16_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C16_PMON_CTR3 is defined as MSR_C16_PMON_CTR3 in SDM.
+**/
+#define MSR_HASWELL_E_C16_PMON_CTR3              0x00000E0B
+
+
+/**
+  Package. Uncore C-box 17 perfmon for box-wide control.
+
+  @param  ECX  MSR_HASWELL_E_C17_PMON_BOX_CTL (0x00000F10)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C17_PMON_BOX_CTL is defined as MSR_C17_PMON_BOX_CTL in SDM.
+**/
+#define MSR_HASWELL_E_C17_PMON_BOX_CTL           0x00000F10
+
+
+/**
+  Package. Uncore C-box 17 perfmon event select for C-box 17 counter 0.
+
+  @param  ECX  MSR_HASWELL_E_C17_PMON_EVNTSEL0 (0x00000F11)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C17_PMON_EVNTSEL0 is defined as MSR_C17_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_HASWELL_E_C17_PMON_EVNTSEL0          0x00000F11
+
+
+/**
+  Package. Uncore C-box 17 perfmon event select for C-box 17 counter 1.
+
+  @param  ECX  MSR_HASWELL_E_C17_PMON_EVNTSEL1 (0x00000F12)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C17_PMON_EVNTSEL1 is defined as MSR_C17_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_HASWELL_E_C17_PMON_EVNTSEL1          0x00000F12
+
+
+/**
+  Package. Uncore C-box 17 perfmon event select for C-box 17 counter 2.
+
+  @param  ECX  MSR_HASWELL_E_C17_PMON_EVNTSEL2 (0x00000F13)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C17_PMON_EVNTSEL2 is defined as MSR_C17_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_HASWELL_E_C17_PMON_EVNTSEL2          0x00000F13
+
+
+/**
+  Package. Uncore C-box 17 perfmon event select for C-box 17 counter 3.
+
+  @param  ECX  MSR_HASWELL_E_C17_PMON_EVNTSEL3 (0x00000F14)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C17_PMON_EVNTSEL3 is defined as MSR_C17_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_HASWELL_E_C17_PMON_EVNTSEL3          0x00000F14
+
+
+/**
+  Package. Uncore C-box 17 perfmon box wide filter 0.
+
+  @param  ECX  MSR_HASWELL_E_C17_PMON_BOX_FILTER0 (0x00000F15)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C17_PMON_BOX_FILTER0 is defined as MSR_C17_PMON_BOX_FILTER0 in SDM.
+**/
+#define MSR_HASWELL_E_C17_PMON_BOX_FILTER0       0x00000F15
+
+
+/**
+  Package. Uncore C-box 17 perfmon box wide filter1.
+
+  @param  ECX  MSR_HASWELL_E_C17_PMON_BOX_FILTER1 (0x00000F16)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C17_PMON_BOX_FILTER1 is defined as MSR_C17_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_HASWELL_E_C17_PMON_BOX_FILTER1       0x00000F16
+
+/**
+  Package. Uncore C-box 17 perfmon box wide status.
+
+  @param  ECX  MSR_HASWELL_E_C17_PMON_BOX_STATUS (0x00000F17)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C17_PMON_BOX_STATUS is defined as MSR_C17_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_HASWELL_E_C17_PMON_BOX_STATUS        0x00000F17
+
+
+/**
+  Package. Uncore C-box 17 perfmon counter n.
+
+  @param  ECX  MSR_HASWELL_E_C17_PMON_CTRn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_E_C17_PMON_CTR0);
+  AsmWriteMsr64 (MSR_HASWELL_E_C17_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_E_C17_PMON_CTR0 is defined as MSR_C17_PMON_CTR0 in SDM.
+        MSR_HASWELL_E_C17_PMON_CTR1 is defined as MSR_C17_PMON_CTR1 in SDM.
+        MSR_HASWELL_E_C17_PMON_CTR2 is defined as MSR_C17_PMON_CTR2 in SDM.
+        MSR_HASWELL_E_C17_PMON_CTR3 is defined as MSR_C17_PMON_CTR3 in SDM.
+  @{
+**/
+#define MSR_HASWELL_E_C17_PMON_CTR0              0x00000F18
+#define MSR_HASWELL_E_C17_PMON_CTR1              0x00000F19
+#define MSR_HASWELL_E_C17_PMON_CTR2              0x00000F1A
+#define MSR_HASWELL_E_C17_PMON_CTR3              0x00000F1B
+/// @}
+
+#endif
diff --git a/MdePkg/Include/Register/Intel/Msr/HaswellMsr.h b/MdePkg/Include/Register/Intel/Msr/HaswellMsr.h
new file mode 100644
index 000000000000..da5c2e497c3d
--- /dev/null
+++ b/MdePkg/Include/Register/Intel/Msr/HaswellMsr.h
@@ -0,0 +1,2631 @@
+/** @file
+  MSR Definitions for Intel processors based on the Haswell microarchitecture.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+  May 2018, Volume 4: Model-Specific-Registers (MSR)
+
+**/
+
+#ifndef __HASWELL_MSR_H__
+#define __HASWELL_MSR_H__
+
+#include <Register/Intel/ArchitecturalMsr.h>
+
+/**
+  Is Intel processors based on the Haswell microarchitecture?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_HASWELL_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (                        \
+    DisplayModel == 0x3C || \
+    DisplayModel == 0x45 || \
+    DisplayModel == 0x46    \
+    )                       \
+   )
+
+/**
+  Package.
+
+  @param  ECX  MSR_HASWELL_PLATFORM_INFO (0x000000CE)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_PLATFORM_INFO_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_PLATFORM_INFO_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_PLATFORM_INFO_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PLATFORM_INFO);
+  AsmWriteMsr64 (MSR_HASWELL_PLATFORM_INFO, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
+**/
+#define MSR_HASWELL_PLATFORM_INFO                0x000000CE
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_PLATFORM_INFO
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:8;
+    ///
+    /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O)  The is the ratio
+    /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
+    /// MHz.
+    ///
+    UINT32  MaximumNonTurboRatio:8;
+    UINT32  Reserved2:12;
+    ///
+    /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O)  When
+    /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
+    /// enabled, and when set to 0, indicates Programmable Ratio Limits for
+    /// Turbo mode is disabled.
+    ///
+    UINT32  RatioLimit:1;
+    ///
+    /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O)  When
+    /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
+    /// and when set to 0, indicates TDP Limit for Turbo mode is not
+    /// programmable.
+    ///
+    UINT32  TDPLimit:1;
+    UINT32  Reserved3:2;
+    ///
+    /// [Bit 32] Package. Low Power Mode Support (LPM) (R/O)  When set to 1,
+    /// indicates that LPM is supported, and when set to 0, indicates LPM is
+    /// not supported.
+    ///
+    UINT32  LowPowerModeSupport:1;
+    ///
+    /// [Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base
+    /// TDP level available. 01: One additional TDP level available. 02: Two
+    /// additional TDP level available. 11: Reserved.
+    ///
+    UINT32  ConfigTDPLevels:2;
+    UINT32  Reserved4:5;
+    ///
+    /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O)  The is the
+    /// minimum ratio (maximum efficiency) that the processor can operates, in
+    /// units of 100MHz.
+    ///
+    UINT32  MaximumEfficiencyRatio:8;
+    ///
+    /// [Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the
+    /// minimum supported operating ratio in units of 100 MHz.
+    ///
+    UINT32  MinimumOperatingRatio:8;
+    UINT32  Reserved5:8;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_PLATFORM_INFO_REGISTER;
+
+
+/**
+  Thread. Performance Event Select for Counter n (R/W) Supports all fields
+  described inTable 2-2 and the fields below.
+
+  @param  ECX  MSR_HASWELL_IA32_PERFEVTSELn
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_IA32_PERFEVTSEL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_IA32_PERFEVTSEL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_IA32_PERFEVTSEL0, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM.
+        MSR_HASWELL_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM.
+        MSR_HASWELL_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.
+  @{
+**/
+#define MSR_HASWELL_IA32_PERFEVTSEL0             0x00000186
+#define MSR_HASWELL_IA32_PERFEVTSEL1             0x00000187
+#define MSR_HASWELL_IA32_PERFEVTSEL3             0x00000189
+/// @}
+
+/**
+  MSR information returned for MSR indexes #MSR_HASWELL_IA32_PERFEVTSEL0,
+  #MSR_HASWELL_IA32_PERFEVTSEL1, and #MSR_HASWELL_IA32_PERFEVTSEL3.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Event Select: Selects a performance event logic unit.
+    ///
+    UINT32  EventSelect:8;
+    ///
+    /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to
+    /// detect on the selected event logic.
+    ///
+    UINT32  UMASK:8;
+    ///
+    /// [Bit 16] USR: Counts while in privilege level is not ring 0.
+    ///
+    UINT32  USR:1;
+    ///
+    /// [Bit 17] OS: Counts while in privilege level is ring 0.
+    ///
+    UINT32  OS:1;
+    ///
+    /// [Bit 18] Edge: Enables edge detection if set.
+    ///
+    UINT32  E:1;
+    ///
+    /// [Bit 19] PC: enables pin control.
+    ///
+    UINT32  PC:1;
+    ///
+    /// [Bit 20] INT: enables interrupt on counter overflow.
+    ///
+    UINT32  INT:1;
+    ///
+    /// [Bit 21] AnyThread: When set to 1, it enables counting the associated
+    /// event conditions occurring across all logical processors sharing a
+    /// processor core. When set to 0, the counter only increments the
+    /// associated event conditions occurring in the logical processor which
+    /// programmed the MSR.
+    ///
+    UINT32  ANY:1;
+    ///
+    /// [Bit 22] EN: enables the corresponding performance counter to commence
+    /// counting when this bit is set.
+    ///
+    UINT32  EN:1;
+    ///
+    /// [Bit 23] INV: invert the CMASK.
+    ///
+    UINT32  INV:1;
+    ///
+    /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding
+    /// performance counter increments each cycle if the event count is
+    /// greater than or equal to the CMASK.
+    ///
+    UINT32  CMASK:8;
+    UINT32  Reserved:32;
+    ///
+    /// [Bit 32] IN_TX: see Section 18.3.6.5.1 When IN_TX (bit 32) is set,
+    /// AnyThread (bit 21) should be cleared to prevent incorrect results.
+    ///
+    UINT32  IN_TX:1;
+    UINT32  Reserved2:31;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_IA32_PERFEVTSEL_REGISTER;
+
+
+/**
+  Thread. Performance Event Select for Counter 2 (R/W) Supports all fields
+  described inTable 2-2 and the fields below.
+
+  @param  ECX  MSR_HASWELL_IA32_PERFEVTSEL2 (0x00000188)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_IA32_PERFEVTSEL2);
+  AsmWriteMsr64 (MSR_HASWELL_IA32_PERFEVTSEL2, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM.
+**/
+#define MSR_HASWELL_IA32_PERFEVTSEL2             0x00000188
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_IA32_PERFEVTSEL2
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Event Select: Selects a performance event logic unit.
+    ///
+    UINT32  EventSelect:8;
+    ///
+    /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to
+    /// detect on the selected event logic.
+    ///
+    UINT32  UMASK:8;
+    ///
+    /// [Bit 16] USR: Counts while in privilege level is not ring 0.
+    ///
+    UINT32  USR:1;
+    ///
+    /// [Bit 17] OS: Counts while in privilege level is ring 0.
+    ///
+    UINT32  OS:1;
+    ///
+    /// [Bit 18] Edge: Enables edge detection if set.
+    ///
+    UINT32  E:1;
+    ///
+    /// [Bit 19] PC: enables pin control.
+    ///
+    UINT32  PC:1;
+    ///
+    /// [Bit 20] INT: enables interrupt on counter overflow.
+    ///
+    UINT32  INT:1;
+    ///
+    /// [Bit 21] AnyThread: When set to 1, it enables counting the associated
+    /// event conditions occurring across all logical processors sharing a
+    /// processor core. When set to 0, the counter only increments the
+    /// associated event conditions occurring in the logical processor which
+    /// programmed the MSR.
+    ///
+    UINT32  ANY:1;
+    ///
+    /// [Bit 22] EN: enables the corresponding performance counter to commence
+    /// counting when this bit is set.
+    ///
+    UINT32  EN:1;
+    ///
+    /// [Bit 23] INV: invert the CMASK.
+    ///
+    UINT32  INV:1;
+    ///
+    /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding
+    /// performance counter increments each cycle if the event count is
+    /// greater than or equal to the CMASK.
+    ///
+    UINT32  CMASK:8;
+    UINT32  Reserved:32;
+    ///
+    /// [Bit 32] IN_TX: see Section 18.3.6.5.1 When IN_TX (bit 32) is set,
+    /// AnyThread (bit 21) should be cleared to prevent incorrect results.
+    ///
+    UINT32  IN_TX:1;
+    ///
+    /// [Bit 33] IN_TXCP: see Section 18.3.6.5.1 When IN_TXCP=1 & IN_TX=1 and
+    /// in sampling, spurious PMI may occur and transactions may continuously
+    /// abort near overflow conditions. Software should favor using IN_TXCP
+    /// for counting over sampling. If sampling, software should use large
+    /// "sample-after" value after clearing the counter configured to use
+    /// IN_TXCP and also always reset the counter even when no overflow
+    /// condition was reported.
+    ///
+    UINT32  IN_TXCP:1;
+    UINT32  Reserved2:30;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER;
+
+
+/**
+  Thread. Last Branch Record Filtering Select Register (R/W).
+
+  @param  ECX  MSR_HASWELL_LBR_SELECT (0x000001C8)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_LBR_SELECT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_LBR_SELECT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_LBR_SELECT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_LBR_SELECT);
+  AsmWriteMsr64 (MSR_HASWELL_LBR_SELECT, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
+**/
+#define MSR_HASWELL_LBR_SELECT                   0x000001C8
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_LBR_SELECT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] CPL_EQ_0.
+    ///
+    UINT32  CPL_EQ_0:1;
+    ///
+    /// [Bit 1] CPL_NEQ_0.
+    ///
+    UINT32  CPL_NEQ_0:1;
+    ///
+    /// [Bit 2] JCC.
+    ///
+    UINT32  JCC:1;
+    ///
+    /// [Bit 3] NEAR_REL_CALL.
+    ///
+    UINT32  NEAR_REL_CALL:1;
+    ///
+    /// [Bit 4] NEAR_IND_CALL.
+    ///
+    UINT32  NEAR_IND_CALL:1;
+    ///
+    /// [Bit 5] NEAR_RET.
+    ///
+    UINT32  NEAR_RET:1;
+    ///
+    /// [Bit 6] NEAR_IND_JMP.
+    ///
+    UINT32  NEAR_IND_JMP:1;
+    ///
+    /// [Bit 7] NEAR_REL_JMP.
+    ///
+    UINT32  NEAR_REL_JMP:1;
+    ///
+    /// [Bit 8] FAR_BRANCH.
+    ///
+    UINT32  FAR_BRANCH:1;
+    ///
+    /// [Bit 9] EN_CALL_STACK.
+    ///
+    UINT32  EN_CALL_STACK:1;
+    UINT32  Reserved1:22;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_LBR_SELECT_REGISTER;
+
+
+/**
+  Package. Package C6/C7 Interrupt Response Limit 1 (R/W)  This MSR defines
+  the interrupt response time limit used by the processor to manage transition
+  to package C6 or C7 state. The latency programmed in this register is for
+  the shorter-latency sub C-states used by an MWAIT hint to C6 or C7 state.
+  Note: C-state values are processor specific C-state code names, unrelated to
+  MWAIT extension C-state parameters or ACPI C-States.
+
+  @param  ECX  MSR_HASWELL_PKGC_IRTL1 (0x0000060B)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_PKGC_IRTL1_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_PKGC_IRTL1_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_PKGC_IRTL1_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKGC_IRTL1);
+  AsmWriteMsr64 (MSR_HASWELL_PKGC_IRTL1, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_PKGC_IRTL1 is defined as MSR_PKGC_IRTL1 in SDM.
+**/
+#define MSR_HASWELL_PKGC_IRTL1                   0x0000060B
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_PKGC_IRTL1
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 9:0] Interrupt response time limit (R/W)  Specifies the limit
+    /// that should be used to decide if the package should be put into a
+    /// package C6 or C7 state.
+    ///
+    UINT32  InterruptResponseTimeLimit:10;
+    ///
+    /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit
+    /// of the interrupt response time limit. See Table 2-19 for supported
+    /// time unit encodings.
+    ///
+    UINT32  TimeUnit:3;
+    UINT32  Reserved1:2;
+    ///
+    /// [Bit 15] Valid (R/W)  Indicates whether the values in bits 12:0 are
+    /// valid and can be used by the processor for package C-sate management.
+    ///
+    UINT32  Valid:1;
+    UINT32  Reserved2:16;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_PKGC_IRTL1_REGISTER;
+
+
+/**
+  Package. Package C6/C7 Interrupt Response Limit 2 (R/W)  This MSR defines
+  the interrupt response time limit used by the processor to manage transition
+  to package C6 or C7 state. The latency programmed in this register is for
+  the longer-latency sub Cstates used by an MWAIT hint to C6 or C7 state.
+  Note: C-state values are processor specific C-state code names, unrelated to
+  MWAIT extension C-state parameters or ACPI C-States.
+
+  @param  ECX  MSR_HASWELL_PKGC_IRTL2 (0x0000060C)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_PKGC_IRTL2_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_PKGC_IRTL2_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_PKGC_IRTL2_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKGC_IRTL2);
+  AsmWriteMsr64 (MSR_HASWELL_PKGC_IRTL2, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_PKGC_IRTL2 is defined as MSR_PKGC_IRTL2 in SDM.
+**/
+#define MSR_HASWELL_PKGC_IRTL2                   0x0000060C
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_PKGC_IRTL2
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit
+    /// that should be used to decide if the package should be put into a
+    /// package C6 or C7 state.
+    ///
+    UINT32  InterruptResponseTimeLimit:10;
+    ///
+    /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit
+    /// of the interrupt response time limit. See Table 2-19 for supported
+    /// time unit encodings.
+    ///
+    UINT32  TimeUnit:3;
+    UINT32  Reserved1:2;
+    ///
+    /// [Bit 15] Valid (R/W)  Indicates whether the values in bits 12:0 are
+    /// valid and can be used by the processor for package C-sate management.
+    ///
+    UINT32  Valid:1;
+    UINT32  Reserved2:16;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_PKGC_IRTL2_REGISTER;
+
+
+/**
+  Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
+
+  @param  ECX  MSR_HASWELL_PKG_PERF_STATUS (0x00000613)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_PKG_PERF_STATUS);
+  @endcode
+  @note MSR_HASWELL_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.
+**/
+#define MSR_HASWELL_PKG_PERF_STATUS              0x00000613
+
+
+/**
+  Package. DRAM Energy Status (R/O)  See Section 14.9.5, "DRAM RAPL Domain.".
+
+  @param  ECX  MSR_HASWELL_DRAM_ENERGY_STATUS (0x00000619)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_DRAM_ENERGY_STATUS);
+  @endcode
+  @note MSR_HASWELL_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
+**/
+#define MSR_HASWELL_DRAM_ENERGY_STATUS           0x00000619
+
+
+/**
+  Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
+  RAPL Domain.".
+
+  @param  ECX  MSR_HASWELL_DRAM_PERF_STATUS (0x0000061B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_DRAM_PERF_STATUS);
+  @endcode
+  @note MSR_HASWELL_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
+**/
+#define MSR_HASWELL_DRAM_PERF_STATUS             0x0000061B
+
+
+/**
+  Package. Base TDP Ratio (R/O).
+
+  @param  ECX  MSR_HASWELL_CONFIG_TDP_NOMINAL (0x00000648)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_NOMINAL);
+  @endcode
+  @note MSR_HASWELL_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.
+**/
+#define MSR_HASWELL_CONFIG_TDP_NOMINAL           0x00000648
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_NOMINAL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Config_TDP_Base Base TDP level ratio to be used for this
+    /// specific processor (in units of 100 MHz).
+    ///
+    UINT32  Config_TDP_Base:8;
+    UINT32  Reserved1:24;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER;
+
+
+/**
+  Package. ConfigTDP Level 1 ratio and power level (R/O).
+
+  @param  ECX  MSR_HASWELL_CONFIG_TDP_LEVEL1 (0x00000649)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_LEVEL1);
+  @endcode
+  @note MSR_HASWELL_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.
+**/
+#define MSR_HASWELL_CONFIG_TDP_LEVEL1            0x00000649
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_LEVEL1
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 14:0] PKG_TDP_LVL1. Power setting for ConfigTDP Level 1.
+    ///
+    UINT32  PKG_TDP_LVL1:15;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bits 23:16] Config_TDP_LVL1_Ratio. ConfigTDP level 1 ratio to be used
+    /// for this specific processor.
+    ///
+    UINT32  Config_TDP_LVL1_Ratio:8;
+    UINT32  Reserved2:8;
+    ///
+    /// [Bits 46:32] PKG_MAX_PWR_LVL1. Max Power setting allowed for ConfigTDP
+    /// Level 1.
+    ///
+    UINT32  PKG_MAX_PWR_LVL1:15;
+    ///
+    /// [Bits 62:47] PKG_MIN_PWR_LVL1. MIN Power setting allowed for ConfigTDP
+    /// Level 1.
+    ///
+    UINT32  PKG_MIN_PWR_LVL1:16;
+    UINT32  Reserved3:1;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER;
+
+
+/**
+  Package. ConfigTDP Level 2 ratio and power level (R/O).
+
+  @param  ECX  MSR_HASWELL_CONFIG_TDP_LEVEL2 (0x0000064A)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_LEVEL2);
+  @endcode
+  @note MSR_HASWELL_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.
+**/
+#define MSR_HASWELL_CONFIG_TDP_LEVEL2            0x0000064A
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_LEVEL2
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 14:0] PKG_TDP_LVL2. Power setting for ConfigTDP Level 2.
+    ///
+    UINT32  PKG_TDP_LVL2:15;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bits 23:16] Config_TDP_LVL2_Ratio. ConfigTDP level 2 ratio to be used
+    /// for this specific processor.
+    ///
+    UINT32  Config_TDP_LVL2_Ratio:8;
+    UINT32  Reserved2:8;
+    ///
+    /// [Bits 46:32] PKG_MAX_PWR_LVL2. Max Power setting allowed for ConfigTDP
+    /// Level 2.
+    ///
+    UINT32  PKG_MAX_PWR_LVL2:15;
+    ///
+    /// [Bits 62:47] PKG_MIN_PWR_LVL2. MIN Power setting allowed for ConfigTDP
+    /// Level 2.
+    ///
+    UINT32  PKG_MIN_PWR_LVL2:16;
+    UINT32  Reserved3:1;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER;
+
+
+/**
+  Package. ConfigTDP Control (R/W).
+
+  @param  ECX  MSR_HASWELL_CONFIG_TDP_CONTROL (0x0000064B)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CONFIG_TDP_CONTROL);
+  AsmWriteMsr64 (MSR_HASWELL_CONFIG_TDP_CONTROL, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.
+**/
+#define MSR_HASWELL_CONFIG_TDP_CONTROL           0x0000064B
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 1:0] TDP_LEVEL (RW/L) System BIOS can program this field.
+    ///
+    UINT32  TDP_LEVEL:2;
+    UINT32  Reserved1:29;
+    ///
+    /// [Bit 31] Config_TDP_Lock (RW/L) When this bit is set, the content of
+    /// this register is locked until a reset.
+    ///
+    UINT32  Config_TDP_Lock:1;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER;
+
+
+/**
+  Package. ConfigTDP Control (R/W).
+
+  @param  ECX  MSR_HASWELL_TURBO_ACTIVATION_RATIO (0x0000064C)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_TURBO_ACTIVATION_RATIO);
+  AsmWriteMsr64 (MSR_HASWELL_TURBO_ACTIVATION_RATIO, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.
+**/
+#define MSR_HASWELL_TURBO_ACTIVATION_RATIO       0x0000064C
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_TURBO_ACTIVATION_RATIO
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this
+    /// field.
+    ///
+    UINT32  MAX_NON_TURBO_RATIO:8;
+    UINT32  Reserved1:23;
+    ///
+    /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the
+    /// content of this register is locked until a reset.
+    ///
+    UINT32  TURBO_ACTIVATION_RATIO_Lock:1;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER;
+
+
+/**
+  Core. C-State Configuration Control (R/W) Note: C-state values are processor
+  specific C-state code names, unrelated to MWAIT extension C-state parameters
+  or ACPI Cstates. `See http://biosbits.org. <http://biosbits.org>`__.
+
+  @param  ECX  MSR_HASWELL_PKG_CST_CONFIG_CONTROL (0x000000E2)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_CST_CONFIG_CONTROL);
+  AsmWriteMsr64 (MSR_HASWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
+**/
+#define MSR_HASWELL_PKG_CST_CONFIG_CONTROL       0x000000E2
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_PKG_CST_CONFIG_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest
+    /// processor-specific C-state code name (consuming the least power) for
+    /// the package. The default is set as factory-configured package C-state
+    /// limit. The following C-state code name encodings are supported: 0000b:
+    /// C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6
+    /// 0100b: C7 0101b: C7s Package C states C7 are not available to
+    /// processor with signature 06_3CH.
+    ///
+    UINT32  Limit:4;
+    UINT32  Reserved1:6;
+    ///
+    /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
+    ///
+    UINT32  IO_MWAIT:1;
+    UINT32  Reserved2:4;
+    ///
+    /// [Bit 15] CFG Lock (R/WO).
+    ///
+    UINT32  CFGLock:1;
+    UINT32  Reserved3:9;
+    ///
+    /// [Bit 25] C3 State Auto Demotion Enable (R/W).
+    ///
+    UINT32  C3AutoDemotion:1;
+    ///
+    /// [Bit 26] C1 State Auto Demotion Enable (R/W).
+    ///
+    UINT32  C1AutoDemotion:1;
+    ///
+    /// [Bit 27] Enable C3 Undemotion (R/W).
+    ///
+    UINT32  C3Undemotion:1;
+    ///
+    /// [Bit 28] Enable C1 Undemotion (R/W).
+    ///
+    UINT32  C1Undemotion:1;
+    UINT32  Reserved4:3;
+    UINT32  Reserved5:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER;
+
+
+/**
+  THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability
+  Enhancement. Accessible only while in SMM.
+
+  @param  ECX  MSR_HASWELL_SMM_MCA_CAP (0x0000017D)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_SMM_MCA_CAP_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_SMM_MCA_CAP_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_SMM_MCA_CAP_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_SMM_MCA_CAP);
+  AsmWriteMsr64 (MSR_HASWELL_SMM_MCA_CAP, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.
+**/
+#define MSR_HASWELL_SMM_MCA_CAP                  0x0000017D
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_SMM_MCA_CAP
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:32;
+    UINT32  Reserved2:26;
+    ///
+    /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
+    /// SMM code access restriction is supported and the
+    /// MSR_SMM_FEATURE_CONTROL is supported.
+    ///
+    UINT32  SMM_Code_Access_Chk:1;
+    ///
+    /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the
+    /// SMM long flow indicator is supported and the MSR_SMM_DELAYED is
+    /// supported.
+    ///
+    UINT32  Long_Flow_Indication:1;
+    UINT32  Reserved3:4;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_SMM_MCA_CAP_REGISTER;
+
+
+/**
+  Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
+  RW if MSR_PLATFORM_INFO.[28] = 1.
+
+  @param  ECX  MSR_HASWELL_TURBO_RATIO_LIMIT (0x000001AD)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_TURBO_RATIO_LIMIT);
+  @endcode
+  @note MSR_HASWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
+**/
+#define MSR_HASWELL_TURBO_RATIO_LIMIT            0x000001AD
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_TURBO_RATIO_LIMIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
+    /// limit of 1 core active.
+    ///
+    UINT32  Maximum1C:8;
+    ///
+    /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
+    /// limit of 2 core active.
+    ///
+    UINT32  Maximum2C:8;
+    ///
+    /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
+    /// limit of 3 core active.
+    ///
+    UINT32  Maximum3C:8;
+    ///
+    /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
+    /// limit of 4 core active.
+    ///
+    UINT32  Maximum4C:8;
+    UINT32  Reserved:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER;
+
+
+/**
+  Package. Uncore PMU global control.
+
+  @param  ECX  MSR_HASWELL_UNC_PERF_GLOBAL_CTRL (0x00000391)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_CTRL);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_CTRL, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.
+**/
+#define MSR_HASWELL_UNC_PERF_GLOBAL_CTRL         0x00000391
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_GLOBAL_CTRL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Core 0 select.
+    ///
+    UINT32  PMI_Sel_Core0:1;
+    ///
+    /// [Bit 1] Core 1 select.
+    ///
+    UINT32  PMI_Sel_Core1:1;
+    ///
+    /// [Bit 2] Core 2 select.
+    ///
+    UINT32  PMI_Sel_Core2:1;
+    ///
+    /// [Bit 3] Core 3 select.
+    ///
+    UINT32  PMI_Sel_Core3:1;
+    UINT32  Reserved1:15;
+    UINT32  Reserved2:10;
+    ///
+    /// [Bit 29] Enable all uncore counters.
+    ///
+    UINT32  EN:1;
+    ///
+    /// [Bit 30] Enable wake on PMI.
+    ///
+    UINT32  WakePMI:1;
+    ///
+    /// [Bit 31] Enable Freezing counter when overflow.
+    ///
+    UINT32  FREEZE:1;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER;
+
+
+/**
+  Package. Uncore PMU main status.
+
+  @param  ECX  MSR_HASWELL_UNC_PERF_GLOBAL_STATUS (0x00000392)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_STATUS);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_GLOBAL_STATUS, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM.
+**/
+#define MSR_HASWELL_UNC_PERF_GLOBAL_STATUS       0x00000392
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_GLOBAL_STATUS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Fixed counter overflowed.
+    ///
+    UINT32  Fixed:1;
+    ///
+    /// [Bit 1] An ARB counter overflowed.
+    ///
+    UINT32  ARB:1;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 3] A CBox counter overflowed (on any slice).
+    ///
+    UINT32  CBox:1;
+    UINT32  Reserved2:28;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER;
+
+
+/**
+  Package. Uncore fixed counter control (R/W).
+
+  @param  ECX  MSR_HASWELL_UNC_PERF_FIXED_CTRL (0x00000394)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTRL);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTRL, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.
+**/
+#define MSR_HASWELL_UNC_PERF_FIXED_CTRL          0x00000394
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_FIXED_CTRL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:20;
+    ///
+    /// [Bit 20] Enable overflow propagation.
+    ///
+    UINT32  EnableOverflow:1;
+    UINT32  Reserved2:1;
+    ///
+    /// [Bit 22] Enable counting.
+    ///
+    UINT32  EnableCounting:1;
+    UINT32  Reserved3:9;
+    UINT32  Reserved4:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER;
+
+
+/**
+  Package. Uncore fixed counter.
+
+  @param  ECX  MSR_HASWELL_UNC_PERF_FIXED_CTR (0x00000395)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTR);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_PERF_FIXED_CTR, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.
+**/
+#define MSR_HASWELL_UNC_PERF_FIXED_CTR           0x00000395
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_FIXED_CTR
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 31:0] Current count.
+    ///
+    UINT32  CurrentCount:32;
+    ///
+    /// [Bits 47:32] Current count.
+    ///
+    UINT32  CurrentCountHi:16;
+    UINT32  Reserved:16;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER;
+
+
+/**
+  Package. Uncore C-Box configuration information (R/O).
+
+  @param  ECX  MSR_HASWELL_UNC_CBO_CONFIG (0x00000396)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_UNC_CBO_CONFIG_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_UNC_CBO_CONFIG_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_UNC_CBO_CONFIG_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_CONFIG);
+  @endcode
+  @note MSR_HASWELL_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.
+**/
+#define MSR_HASWELL_UNC_CBO_CONFIG               0x00000396
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_UNC_CBO_CONFIG
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 3:0] Encoded number of C-Box, derive value by "-1".
+    ///
+    UINT32  CBox:4;
+    UINT32  Reserved1:28;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_UNC_CBO_CONFIG_REGISTER;
+
+
+/**
+  Package. Uncore Arb unit, performance counter 0.
+
+  @param  ECX  MSR_HASWELL_UNC_ARB_PERFCTR0 (0x000003B0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR0);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.
+**/
+#define MSR_HASWELL_UNC_ARB_PERFCTR0             0x000003B0
+
+
+/**
+  Package. Uncore Arb unit, performance counter 1.
+
+  @param  ECX  MSR_HASWELL_UNC_ARB_PERFCTR1 (0x000003B1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR1);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFCTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.
+**/
+#define MSR_HASWELL_UNC_ARB_PERFCTR1             0x000003B1
+
+
+/**
+  Package. Uncore Arb unit, counter 0 event select MSR.
+
+  @param  ECX  MSR_HASWELL_UNC_ARB_PERFEVTSEL0 (0x000003B2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.
+**/
+#define MSR_HASWELL_UNC_ARB_PERFEVTSEL0          0x000003B2
+
+
+/**
+  Package. Uncore Arb unit, counter 1 event select MSR.
+
+  @param  ECX  MSR_HASWELL_UNC_ARB_PERFEVTSEL1 (0x000003B3)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_ARB_PERFEVTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_UNC_ARB_PERFEVTSEL1 is defined as MSR_UNC_ARB_PERFEVTSEL1 in SDM.
+**/
+#define MSR_HASWELL_UNC_ARB_PERFEVTSEL1          0x000003B3
+
+
+/**
+  Package. Enhanced SMM Feature Control (SMM-RW) Reports SMM capability
+  Enhancement. Accessible only while in SMM.
+
+  @param  ECX  MSR_HASWELL_SMM_FEATURE_CONTROL (0x000004E0)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_SMM_FEATURE_CONTROL);
+  AsmWriteMsr64 (MSR_HASWELL_SMM_FEATURE_CONTROL, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_SMM_FEATURE_CONTROL is defined as MSR_SMM_FEATURE_CONTROL in SDM.
+**/
+#define MSR_HASWELL_SMM_FEATURE_CONTROL          0x000004E0
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_SMM_FEATURE_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Lock (SMM-RWO) When set to '1' locks this register from
+    /// further changes.
+    ///
+    UINT32  Lock:1;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 2] SMM_Code_Chk_En (SMM-RW) This control bit is available only if
+    /// MSR_SMM_MCA_CAP[58] == 1. When set to '0' (default) none of the
+    /// logical processors are prevented from executing SMM code outside the
+    /// ranges defined by the SMRR. When set to '1' any logical processor in
+    /// the package that attempts to execute SMM code not within the ranges
+    /// defined by the SMRR will assert an unrecoverable MCE.
+    ///
+    UINT32  SMM_Code_Chk_En:1;
+    UINT32  Reserved2:29;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER;
+
+
+/**
+  Package. SMM Delayed (SMM-RO) Reports the interruptible state of all logical
+  processors in the package. Available only while in SMM and
+  MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] == 1.
+
+  [Bits 31:0] LOG_PROC_STATE (SMM-RO) Each bit represents a logical
+  processor of its state in a long flow of internal operation which
+  delays servicing an interrupt. The corresponding bit will be set at
+  the start of long events such as: Microcode Update Load, C6, WBINVD,
+  Ratio Change, Throttle. The bit is automatically cleared at the end of
+  each long event. The reset value of this field is 0. Only bit
+  positions below N = CPUID.(EAX=0BH, ECX=PKG_LVL):EBX[15:0] can be
+  updated.
+
+  [Bits 63:32] LOG_PROC_STATE (SMM-RO) Each bit represents a logical
+  processor of its state in a long flow of internal operation which
+  delays servicing an interrupt. The corresponding bit will be set at
+  the start of long events such as: Microcode Update Load, C6, WBINVD,
+  Ratio Change, Throttle. The bit is automatically cleared at the end of
+  each long event. The reset value of this field is 0. Only bit
+  positions below N = CPUID.(EAX=0BH, ECX=PKG_LVL):EBX[15:0] can be
+  updated.
+
+  @param  ECX  MSR_HASWELL_SMM_DELAYED (0x000004E2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_SMM_DELAYED);
+  @endcode
+  @note MSR_HASWELL_SMM_DELAYED is defined as MSR_SMM_DELAYED in SDM.
+**/
+#define MSR_HASWELL_SMM_DELAYED                  0x000004E2
+
+
+/**
+  Package. SMM Blocked (SMM-RO) Reports the blocked state of all logical
+  processors in the package. Available only while in SMM.
+
+  [Bits 31:0] LOG_PROC_STATE (SMM-RO) Each bit represents a logical
+  processor of its blocked state to service an SMI. The corresponding
+  bit will be set if the logical processor is in one of the following
+  states: Wait For SIPI or SENTER Sleep. The reset value of this field
+  is 0FFFH. Only bit positions below N = CPUID.(EAX=0BH,
+  ECX=PKG_LVL):EBX[15:0] can be updated.
+
+
+  [Bits 63:32] LOG_PROC_STATE (SMM-RO) Each bit represents a logical
+  processor of its blocked state to service an SMI. The corresponding
+  bit will be set if the logical processor is in one of the following
+  states: Wait For SIPI or SENTER Sleep. The reset value of this field
+  is 0FFFH. Only bit positions below N = CPUID.(EAX=0BH,
+  ECX=PKG_LVL):EBX[15:0] can be updated.
+
+  @param  ECX  MSR_HASWELL_SMM_BLOCKED (0x000004E3)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_SMM_BLOCKED);
+  @endcode
+  @note MSR_HASWELL_SMM_BLOCKED is defined as MSR_SMM_BLOCKED in SDM.
+**/
+#define MSR_HASWELL_SMM_BLOCKED                  0x000004E3
+
+
+/**
+  Package. Unit Multipliers used in RAPL Interfaces (R/O).
+
+  @param  ECX  MSR_HASWELL_RAPL_POWER_UNIT (0x00000606)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_RAPL_POWER_UNIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_RAPL_POWER_UNIT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_RAPL_POWER_UNIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_RAPL_POWER_UNIT);
+  @endcode
+  @note MSR_HASWELL_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
+**/
+#define MSR_HASWELL_RAPL_POWER_UNIT              0x00000606
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_RAPL_POWER_UNIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".
+    ///
+    UINT32  PowerUnits:4;
+    UINT32  Reserved1:4;
+    ///
+    /// [Bits 12:8] Package. Energy Status Units Energy related information
+    /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an
+    /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61
+    /// micro-joules).
+    ///
+    UINT32  EnergyStatusUnits:5;
+    UINT32  Reserved2:3;
+    ///
+    /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL
+    /// Interfaces.".
+    ///
+    UINT32  TimeUnits:4;
+    UINT32  Reserved3:12;
+    UINT32  Reserved4:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_RAPL_POWER_UNIT_REGISTER;
+
+
+/**
+  Package. PP0 Energy Status (R/O)  See Section 14.9.4, "PP0/PP1 RAPL
+  Domains.".
+
+  @param  ECX  MSR_HASWELL_PP0_ENERGY_STATUS (0x00000639)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_PP0_ENERGY_STATUS);
+  @endcode
+  @note MSR_HASWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
+**/
+#define MSR_HASWELL_PP0_ENERGY_STATUS            0x00000639
+
+
+/**
+  Package. PP1 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1
+  RAPL Domains.".
+
+  @param  ECX  MSR_HASWELL_PP1_POWER_LIMIT (0x00000640)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_PP1_POWER_LIMIT);
+  AsmWriteMsr64 (MSR_HASWELL_PP1_POWER_LIMIT, Msr);
+  @endcode
+  @note MSR_HASWELL_PP1_POWER_LIMIT is defined as MSR_PP1_POWER_LIMIT in SDM.
+**/
+#define MSR_HASWELL_PP1_POWER_LIMIT              0x00000640
+
+
+/**
+  Package. PP1 Energy Status (R/O)  See Section 14.9.4, "PP0/PP1 RAPL
+  Domains.".
+
+  @param  ECX  MSR_HASWELL_PP1_ENERGY_STATUS (0x00000641)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_PP1_ENERGY_STATUS);
+  @endcode
+  @note MSR_HASWELL_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM.
+**/
+#define MSR_HASWELL_PP1_ENERGY_STATUS            0x00000641
+
+
+/**
+  Package. PP1 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL
+  Domains.".
+
+  @param  ECX  MSR_HASWELL_PP1_POLICY (0x00000642)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_PP1_POLICY);
+  AsmWriteMsr64 (MSR_HASWELL_PP1_POLICY, Msr);
+  @endcode
+  @note MSR_HASWELL_PP1_POLICY is defined as MSR_PP1_POLICY in SDM.
+**/
+#define MSR_HASWELL_PP1_POLICY                   0x00000642
+
+
+/**
+  Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
+  refers to processor core frequency).
+
+  @param  ECX  MSR_HASWELL_CORE_PERF_LIMIT_REASONS (0x00000690)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_CORE_PERF_LIMIT_REASONS);
+  AsmWriteMsr64 (MSR_HASWELL_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
+**/
+#define MSR_HASWELL_CORE_PERF_LIMIT_REASONS      0x00000690
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_CORE_PERF_LIMIT_REASONS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is
+    /// reduced below the operating system request due to assertion of
+    /// external PROCHOT.
+    ///
+    UINT32  PROCHOT_Status:1;
+    ///
+    /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
+    /// operating system request due to a thermal event.
+    ///
+    UINT32  ThermalStatus:1;
+    UINT32  Reserved1:2;
+    ///
+    /// [Bit 4] Graphics Driver Status (R0) When set, frequency is reduced
+    /// below the operating system request due to Processor Graphics driver
+    /// override.
+    ///
+    UINT32  GraphicsDriverStatus:1;
+    ///
+    /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)
+    /// When set, frequency is reduced below the operating system request
+    /// because the processor has detected that utilization is low.
+    ///
+    UINT32  AutonomousUtilizationBasedFrequencyControlStatus:1;
+    ///
+    /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced
+    /// below the operating system request due to a thermal alert from the
+    /// Voltage Regulator.
+    ///
+    UINT32  VRThermAlertStatus:1;
+    UINT32  Reserved2:1;
+    ///
+    /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is
+    /// reduced below the operating system request due to electrical design
+    /// point constraints (e.g. maximum electrical current consumption).
+    ///
+    UINT32  ElectricalDesignPointStatus:1;
+    ///
+    /// [Bit 9] Core Power Limiting Status (R0) When set, frequency is reduced
+    /// below the operating system request due to domain-level power limiting.
+    ///
+    UINT32  PLStatus:1;
+    ///
+    /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set,
+    /// frequency is reduced below the operating system request due to
+    /// package-level power limiting PL1.
+    ///
+    UINT32  PL1Status:1;
+    ///
+    /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set,
+    /// frequency is reduced below the operating system request due to
+    /// package-level power limiting PL2.
+    ///
+    UINT32  PL2Status:1;
+    ///
+    /// [Bit 12] Max Turbo Limit Status (R0) When set, frequency is reduced
+    /// below the operating system request due to multi-core turbo limits.
+    ///
+    UINT32  MaxTurboLimitStatus:1;
+    ///
+    /// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency
+    /// is reduced below the operating system request due to Turbo transition
+    /// attenuation. This prevents performance degradation due to frequent
+    /// operating ratio changes.
+    ///
+    UINT32  TurboTransitionAttenuationStatus:1;
+    UINT32  Reserved3:2;
+    ///
+    /// [Bit 16] PROCHOT Log  When set, indicates that the PROCHOT Status bit
+    /// has asserted since the log bit was last cleared. This log bit will
+    /// remain set until cleared by software writing 0.
+    ///
+    UINT32  PROCHOT_Log:1;
+    ///
+    /// [Bit 17] Thermal Log  When set, indicates that the Thermal Status bit
+    /// has asserted since the log bit was last cleared. This log bit will
+    /// remain set until cleared by software writing 0.
+    ///
+    UINT32  ThermalLog:1;
+    UINT32  Reserved4:2;
+    ///
+    /// [Bit 20] Graphics Driver Log  When set, indicates that the Graphics
+    /// Driver Status bit has asserted since the log bit was last cleared.
+    /// This log bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  GraphicsDriverLog:1;
+    ///
+    /// [Bit 21] Autonomous Utilization-Based Frequency Control Log  When set,
+    /// indicates that the Autonomous Utilization-Based Frequency Control
+    /// Status bit has asserted since the log bit was last cleared. This log
+    /// bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  AutonomousUtilizationBasedFrequencyControlLog:1;
+    ///
+    /// [Bit 22] VR Therm Alert Log  When set, indicates that the VR Therm
+    /// Alert Status bit has asserted since the log bit was last cleared. This
+    /// log bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  VRThermAlertLog:1;
+    UINT32  Reserved5:1;
+    ///
+    /// [Bit 24] Electrical Design Point Log  When set, indicates that the EDP
+    /// Status bit has asserted since the log bit was last cleared. This log
+    /// bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  ElectricalDesignPointLog:1;
+    ///
+    /// [Bit 25] Core Power Limiting Log  When set, indicates that the Core
+    /// Power Limiting Status bit has asserted since the log bit was last
+    /// cleared. This log bit will remain set until cleared by software
+    /// writing 0.
+    ///
+    UINT32  PLLog:1;
+    ///
+    /// [Bit 26] Package-Level PL1 Power Limiting Log  When set, indicates
+    /// that the Package Level PL1 Power Limiting Status bit has asserted
+    /// since the log bit was last cleared. This log bit will remain set until
+    /// cleared by software writing 0.
+    ///
+    UINT32  PL1Log:1;
+    ///
+    /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that
+    /// the Package Level PL2 Power Limiting Status bit has asserted since the
+    /// log bit was last cleared. This log bit will remain set until cleared
+    /// by software writing 0.
+    ///
+    UINT32  PL2Log:1;
+    ///
+    /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo
+    /// Limit Status bit has asserted since the log bit was last cleared. This
+    /// log bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  MaxTurboLimitLog:1;
+    ///
+    /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the
+    /// Turbo Transition Attenuation Status bit has asserted since the log bit
+    /// was last cleared. This log bit will remain set until cleared by
+    /// software writing 0.
+    ///
+    UINT32  TurboTransitionAttenuationLog:1;
+    UINT32  Reserved6:2;
+    UINT32  Reserved7:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER;
+
+
+/**
+  Package. Indicator of Frequency Clipping in the Processor Graphics (R/W)
+  (frequency refers to processor graphics frequency).
+
+  @param  ECX  MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS (0x000006B0)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS);
+  AsmWriteMsr64 (MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS is defined as MSR_GRAPHICS_PERF_LIMIT_REASONS in SDM.
+**/
+#define MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS  0x000006B0
+
+/**
+  MSR information returned for MSR index
+  #MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the
+    /// operating system request due to assertion of external PROCHOT.
+    ///
+    UINT32  PROCHOT_Status:1;
+    ///
+    /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
+    /// operating system request due to a thermal event.
+    ///
+    UINT32  ThermalStatus:1;
+    UINT32  Reserved1:2;
+    ///
+    /// [Bit 4] Graphics Driver Status (R0) When set, frequency is reduced
+    /// below the operating system request due to Processor Graphics driver
+    /// override.
+    ///
+    UINT32  GraphicsDriverStatus:1;
+    ///
+    /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)
+    /// When set, frequency is reduced below the operating system request
+    /// because the processor has detected that utilization is low.
+    ///
+    UINT32  AutonomousUtilizationBasedFrequencyControlStatus:1;
+    ///
+    /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced
+    /// below the operating system request due to a thermal alert from the
+    /// Voltage Regulator.
+    ///
+    UINT32  VRThermAlertStatus:1;
+    UINT32  Reserved2:1;
+    ///
+    /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is
+    /// reduced below the operating system request due to electrical design
+    /// point constraints (e.g. maximum electrical current consumption).
+    ///
+    UINT32  ElectricalDesignPointStatus:1;
+    ///
+    /// [Bit 9] Graphics Power Limiting Status (R0) When set, frequency is
+    /// reduced below the operating system request due to domain-level power
+    /// limiting.
+    ///
+    UINT32  GraphicsPowerLimitingStatus:1;
+    ///
+    /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set,
+    /// frequency is reduced below the operating system request due to
+    /// package-level power limiting PL1.
+    ///
+    UINT32  PL1STatus:1;
+    ///
+    /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set,
+    /// frequency is reduced below the operating system request due to
+    /// package-level power limiting PL2.
+    ///
+    UINT32  PL2Status:1;
+    UINT32  Reserved3:4;
+    ///
+    /// [Bit 16] PROCHOT Log  When set, indicates that the PROCHOT Status bit
+    /// has asserted since the log bit was last cleared. This log bit will
+    /// remain set until cleared by software writing 0.
+    ///
+    UINT32  PROCHOT_Log:1;
+    ///
+    /// [Bit 17] Thermal Log  When set, indicates that the Thermal Status bit
+    /// has asserted since the log bit was last cleared. This log bit will
+    /// remain set until cleared by software writing 0.
+    ///
+    UINT32  ThermalLog:1;
+    UINT32  Reserved4:2;
+    ///
+    /// [Bit 20] Graphics Driver Log  When set, indicates that the Graphics
+    /// Driver Status bit has asserted since the log bit was last cleared.
+    /// This log bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  GraphicsDriverLog:1;
+    ///
+    /// [Bit 21] Autonomous Utilization-Based Frequency Control Log  When set,
+    /// indicates that the Autonomous Utilization-Based Frequency Control
+    /// Status bit has asserted since the log bit was last cleared. This log
+    /// bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  AutonomousUtilizationBasedFrequencyControlLog:1;
+    ///
+    /// [Bit 22] VR Therm Alert Log  When set, indicates that the VR Therm
+    /// Alert Status bit has asserted since the log bit was last cleared. This
+    /// log bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  VRThermAlertLog:1;
+    UINT32  Reserved5:1;
+    ///
+    /// [Bit 24] Electrical Design Point Log  When set, indicates that the EDP
+    /// Status bit has asserted since the log bit was last cleared. This log
+    /// bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  ElectricalDesignPointLog:1;
+    ///
+    /// [Bit 25] Core Power Limiting Log  When set, indicates that the Core
+    /// Power Limiting Status bit has asserted since the log bit was last
+    /// cleared. This log bit will remain set until cleared by software
+    /// writing 0.
+    ///
+    UINT32  CorePowerLimitingLog:1;
+    ///
+    /// [Bit 26] Package-Level PL1 Power Limiting Log  When set, indicates
+    /// that the Package Level PL1 Power Limiting Status bit has asserted
+    /// since the log bit was last cleared. This log bit will remain set until
+    /// cleared by software writing 0.
+    ///
+    UINT32  PL1Log:1;
+    ///
+    /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that
+    /// the Package Level PL2 Power Limiting Status bit has asserted since the
+    /// log bit was last cleared. This log bit will remain set until cleared
+    /// by software writing 0.
+    ///
+    UINT32  PL2Log:1;
+    ///
+    /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo
+    /// Limit Status bit has asserted since the log bit was last cleared. This
+    /// log bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  MaxTurboLimitLog:1;
+    ///
+    /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the
+    /// Turbo Transition Attenuation Status bit has asserted since the log bit
+    /// was last cleared. This log bit will remain set until cleared by
+    /// software writing 0.
+    ///
+    UINT32  TurboTransitionAttenuationLog:1;
+    UINT32  Reserved6:2;
+    UINT32  Reserved7:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER;
+
+
+/**
+  Package. Indicator of Frequency Clipping in the Ring Interconnect (R/W)
+  (frequency refers to ring interconnect in the uncore).
+
+  @param  ECX  MSR_HASWELL_RING_PERF_LIMIT_REASONS (0x000006B1)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_RING_PERF_LIMIT_REASONS);
+  AsmWriteMsr64 (MSR_HASWELL_RING_PERF_LIMIT_REASONS, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_RING_PERF_LIMIT_REASONS is defined as MSR_RING_PERF_LIMIT_REASONS in SDM.
+**/
+#define MSR_HASWELL_RING_PERF_LIMIT_REASONS      0x000006B1
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_RING_PERF_LIMIT_REASONS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the
+    /// operating system request due to assertion of external PROCHOT.
+    ///
+    UINT32  PROCHOT_Status:1;
+    ///
+    /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
+    /// operating system request due to a thermal event.
+    ///
+    UINT32  ThermalStatus:1;
+    UINT32  Reserved1:4;
+    ///
+    /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced
+    /// below the operating system request due to a thermal alert from the
+    /// Voltage Regulator.
+    ///
+    UINT32  VRThermAlertStatus:1;
+    UINT32  Reserved2:1;
+    ///
+    /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is
+    /// reduced below the operating system request due to electrical design
+    /// point constraints (e.g. maximum electrical current consumption).
+    ///
+    UINT32  ElectricalDesignPointStatus:1;
+    UINT32  Reserved3:1;
+    ///
+    /// [Bit 10] Package-Level Power Limiting PL1 Status (R0) When set,
+    /// frequency is reduced below the operating system request due to
+    /// package-level power limiting PL1.
+    ///
+    UINT32  PL1STatus:1;
+    ///
+    /// [Bit 11] Package-Level PL2 Power Limiting Status (R0) When set,
+    /// frequency is reduced below the operating system request due to
+    /// package-level power limiting PL2.
+    ///
+    UINT32  PL2Status:1;
+    UINT32  Reserved4:4;
+    ///
+    /// [Bit 16] PROCHOT Log  When set, indicates that the PROCHOT Status bit
+    /// has asserted since the log bit was last cleared. This log bit will
+    /// remain set until cleared by software writing 0.
+    ///
+    UINT32  PROCHOT_Log:1;
+    ///
+    /// [Bit 17] Thermal Log  When set, indicates that the Thermal Status bit
+    /// has asserted since the log bit was last cleared. This log bit will
+    /// remain set until cleared by software writing 0.
+    ///
+    UINT32  ThermalLog:1;
+    UINT32  Reserved5:2;
+    ///
+    /// [Bit 20] Graphics Driver Log  When set, indicates that the Graphics
+    /// Driver Status bit has asserted since the log bit was last cleared.
+    /// This log bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  GraphicsDriverLog:1;
+    ///
+    /// [Bit 21] Autonomous Utilization-Based Frequency Control Log  When set,
+    /// indicates that the Autonomous Utilization-Based Frequency Control
+    /// Status bit has asserted since the log bit was last cleared. This log
+    /// bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  AutonomousUtilizationBasedFrequencyControlLog:1;
+    ///
+    /// [Bit 22] VR Therm Alert Log  When set, indicates that the VR Therm
+    /// Alert Status bit has asserted since the log bit was last cleared. This
+    /// log bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  VRThermAlertLog:1;
+    UINT32  Reserved6:1;
+    ///
+    /// [Bit 24] Electrical Design Point Log  When set, indicates that the EDP
+    /// Status bit has asserted since the log bit was last cleared. This log
+    /// bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  ElectricalDesignPointLog:1;
+    ///
+    /// [Bit 25] Core Power Limiting Log  When set, indicates that the Core
+    /// Power Limiting Status bit has asserted since the log bit was last
+    /// cleared. This log bit will remain set until cleared by software
+    /// writing 0.
+    ///
+    UINT32  CorePowerLimitingLog:1;
+    ///
+    /// [Bit 26] Package-Level PL1 Power Limiting Log  When set, indicates
+    /// that the Package Level PL1 Power Limiting Status bit has asserted
+    /// since the log bit was last cleared. This log bit will remain set until
+    /// cleared by software writing 0.
+    ///
+    UINT32  PL1Log:1;
+    ///
+    /// [Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that
+    /// the Package Level PL2 Power Limiting Status bit has asserted since the
+    /// log bit was last cleared. This log bit will remain set until cleared
+    /// by software writing 0.
+    ///
+    UINT32  PL2Log:1;
+    ///
+    /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo
+    /// Limit Status bit has asserted since the log bit was last cleared. This
+    /// log bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  MaxTurboLimitLog:1;
+    ///
+    /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the
+    /// Turbo Transition Attenuation Status bit has asserted since the log bit
+    /// was last cleared. This log bit will remain set until cleared by
+    /// software writing 0.
+    ///
+    UINT32  TurboTransitionAttenuationLog:1;
+    UINT32  Reserved7:2;
+    UINT32  Reserved8:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER;
+
+
+/**
+  Package. Uncore C-Box 0, counter 0 event select MSR.
+
+  @param  ECX  MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 (0x00000700)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.
+**/
+#define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL0        0x00000700
+
+
+/**
+  Package. Uncore C-Box 0, counter 1 event select MSR.
+
+  @param  ECX  MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 (0x00000701)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.
+**/
+#define MSR_HASWELL_UNC_CBO_0_PERFEVTSEL1        0x00000701
+
+
+/**
+  Package. Uncore C-Box 0, performance counter 0.
+
+  @param  ECX  MSR_HASWELL_UNC_CBO_0_PERFCTR0 (0x00000706)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR0);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.
+**/
+#define MSR_HASWELL_UNC_CBO_0_PERFCTR0           0x00000706
+
+
+/**
+  Package. Uncore C-Box 0, performance counter 1.
+
+  @param  ECX  MSR_HASWELL_UNC_CBO_0_PERFCTR1 (0x00000707)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR1);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_0_PERFCTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.
+**/
+#define MSR_HASWELL_UNC_CBO_0_PERFCTR1           0x00000707
+
+
+/**
+  Package. Uncore C-Box 1, counter 0 event select MSR.
+
+  @param  ECX  MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 (0x00000710)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.
+**/
+#define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL0        0x00000710
+
+
+/**
+  Package. Uncore C-Box 1, counter 1 event select MSR.
+
+  @param  ECX  MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 (0x00000711)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.
+**/
+#define MSR_HASWELL_UNC_CBO_1_PERFEVTSEL1        0x00000711
+
+
+/**
+  Package. Uncore C-Box 1, performance counter 0.
+
+  @param  ECX  MSR_HASWELL_UNC_CBO_1_PERFCTR0 (0x00000716)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR0);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.
+**/
+#define MSR_HASWELL_UNC_CBO_1_PERFCTR0           0x00000716
+
+
+/**
+  Package. Uncore C-Box 1, performance counter 1.
+
+  @param  ECX  MSR_HASWELL_UNC_CBO_1_PERFCTR1 (0x00000717)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR1);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_1_PERFCTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.
+**/
+#define MSR_HASWELL_UNC_CBO_1_PERFCTR1           0x00000717
+
+
+/**
+  Package. Uncore C-Box 2, counter 0 event select MSR.
+
+  @param  ECX  MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 (0x00000720)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.
+**/
+#define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL0        0x00000720
+
+
+/**
+  Package. Uncore C-Box 2, counter 1 event select MSR.
+
+  @param  ECX  MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 (0x00000721)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.
+**/
+#define MSR_HASWELL_UNC_CBO_2_PERFEVTSEL1        0x00000721
+
+
+/**
+  Package. Uncore C-Box 2, performance counter 0.
+
+  @param  ECX  MSR_HASWELL_UNC_CBO_2_PERFCTR0 (0x00000726)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR0);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.
+**/
+#define MSR_HASWELL_UNC_CBO_2_PERFCTR0           0x00000726
+
+
+/**
+  Package. Uncore C-Box 2, performance counter 1.
+
+  @param  ECX  MSR_HASWELL_UNC_CBO_2_PERFCTR1 (0x00000727)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR1);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_2_PERFCTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.
+**/
+#define MSR_HASWELL_UNC_CBO_2_PERFCTR1           0x00000727
+
+
+/**
+  Package. Uncore C-Box 3, counter 0 event select MSR.
+
+  @param  ECX  MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 (0x00000730)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0, Msr);
+  @endcode
+  @note MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.
+**/
+#define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL0        0x00000730
+
+
+/**
+  Package. Uncore C-Box 3, counter 1 event select MSR.
+
+  @param  ECX  MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 (0x00000731)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1, Msr);
+  @endcode
+  @note MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.
+**/
+#define MSR_HASWELL_UNC_CBO_3_PERFEVTSEL1        0x00000731
+
+
+/**
+  Package. Uncore C-Box 3, performance counter 0.
+
+  @param  ECX  MSR_HASWELL_UNC_CBO_3_PERFCTR0 (0x00000736)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR0);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR0, Msr);
+  @endcode
+  @note MSR_HASWELL_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.
+**/
+#define MSR_HASWELL_UNC_CBO_3_PERFCTR0           0x00000736
+
+
+/**
+  Package. Uncore C-Box 3, performance counter 1.
+
+  @param  ECX  MSR_HASWELL_UNC_CBO_3_PERFCTR1 (0x00000737)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR1);
+  AsmWriteMsr64 (MSR_HASWELL_UNC_CBO_3_PERFCTR1, Msr);
+  @endcode
+  @note MSR_HASWELL_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.
+**/
+#define MSR_HASWELL_UNC_CBO_3_PERFCTR1           0x00000737
+
+
+/**
+  Package. Note: C-state values are processor specific C-state code names,
+  unrelated to MWAIT extension C-state parameters or ACPI C-States.
+
+  @param  ECX  MSR_HASWELL_PKG_C8_RESIDENCY (0x00000630)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C8_RESIDENCY);
+  AsmWriteMsr64 (MSR_HASWELL_PKG_C8_RESIDENCY, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_PKG_C8_RESIDENCY is defined as MSR_PKG_C8_RESIDENCY in SDM.
+**/
+#define MSR_HASWELL_PKG_C8_RESIDENCY             0x00000630
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_PKG_C8_RESIDENCY
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 31:0] Package C8 Residency Counter. (R/O) Value since last reset
+    /// that this package is in processor-specific C8 states. Count at the
+    /// same frequency as the TSC.
+    ///
+    UINT32  C8ResidencyCounter:32;
+    ///
+    /// [Bits 59:32] Package C8 Residency Counter. (R/O) Value since last
+    /// reset that this package is in processor-specific C8 states. Count at
+    /// the same frequency as the TSC.
+    ///
+    UINT32  C8ResidencyCounterHi:28;
+    UINT32  Reserved:4;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER;
+
+
+/**
+  Package. Note: C-state values are processor specific C-state code names,
+  unrelated to MWAIT extension C-state parameters or ACPI C-States.
+
+  @param  ECX  MSR_HASWELL_PKG_C9_RESIDENCY (0x00000631)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C9_RESIDENCY);
+  AsmWriteMsr64 (MSR_HASWELL_PKG_C9_RESIDENCY, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_PKG_C9_RESIDENCY is defined as MSR_PKG_C9_RESIDENCY in SDM.
+**/
+#define MSR_HASWELL_PKG_C9_RESIDENCY             0x00000631
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_PKG_C9_RESIDENCY
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 31:0] Package C9 Residency Counter. (R/O) Value since last reset
+    /// that this package is in processor-specific C9 states. Count at the
+    /// same frequency as the TSC.
+    ///
+    UINT32  C9ResidencyCounter:32;
+    ///
+    /// [Bits 59:32] Package C9 Residency Counter. (R/O) Value since last
+    /// reset that this package is in processor-specific C9 states. Count at
+    /// the same frequency as the TSC.
+    ///
+    UINT32  C9ResidencyCounterHi:28;
+    UINT32  Reserved:4;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER;
+
+
+/**
+  Package. Note: C-state values are processor specific C-state code names,
+  unrelated to MWAIT extension C-state parameters or ACPI C-States.
+
+  @param  ECX  MSR_HASWELL_PKG_C10_RESIDENCY (0x00000632)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_HASWELL_PKG_C10_RESIDENCY);
+  AsmWriteMsr64 (MSR_HASWELL_PKG_C10_RESIDENCY, Msr.Uint64);
+  @endcode
+  @note MSR_HASWELL_PKG_C10_RESIDENCY is defined as MSR_PKG_C10_RESIDENCY in SDM.
+**/
+#define MSR_HASWELL_PKG_C10_RESIDENCY            0x00000632
+
+/**
+  MSR information returned for MSR index #MSR_HASWELL_PKG_C10_RESIDENCY
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 31:0] Package C10 Residency Counter. (R/O) Value since last
+    /// reset that this package is in processor-specific C10 states. Count at
+    /// the same frequency as the TSC.
+    ///
+    UINT32  C10ResidencyCounter:32;
+    ///
+    /// [Bits 59:32] Package C10 Residency Counter. (R/O) Value since last
+    /// reset that this package is in processor-specific C10 states. Count at
+    /// the same frequency as the TSC.
+    ///
+    UINT32  C10ResidencyCounterHi:28;
+    UINT32  Reserved:4;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER;
+
+#endif
diff --git a/MdePkg/Include/Register/Intel/Msr/IvyBridgeMsr.h b/MdePkg/Include/Register/Intel/Msr/IvyBridgeMsr.h
new file mode 100644
index 000000000000..57fde2c677f0
--- /dev/null
+++ b/MdePkg/Include/Register/Intel/Msr/IvyBridgeMsr.h
@@ -0,0 +1,2887 @@
+/** @file
+  MSR Definitions for Intel processors based on the Ivy Bridge microarchitecture.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+  May 2018, Volume 4: Model-Specific-Registers (MSR)
+
+**/
+
+#ifndef __IVY_BRIDGE_MSR_H__
+#define __IVY_BRIDGE_MSR_H__
+
+#include <Register/Intel/ArchitecturalMsr.h>
+
+/**
+  Is Intel processors based on the Ivy Bridge microarchitecture?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_IVY_BRIDGE_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (                        \
+    DisplayModel == 0x3A || \
+    DisplayModel == 0x3E    \
+    )                       \
+   )
+
+/**
+  Package. See http://biosbits.org.
+
+  @param  ECX  MSR_IVY_BRIDGE_PLATFORM_INFO (0x000000CE)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO, Msr.Uint64);
+  @endcode
+  @note MSR_IVY_BRIDGE_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
+**/
+#define MSR_IVY_BRIDGE_PLATFORM_INFO             0x000000CE
+
+/**
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:8;
+    ///
+    /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O)  The is the ratio
+    /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
+    /// MHz.
+    ///
+    UINT32  MaximumNonTurboRatio:8;
+    UINT32  Reserved2:12;
+    ///
+    /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O)  When
+    /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
+    /// enabled, and when set to 0, indicates Programmable Ratio Limits for
+    /// Turbo mode is disabled.
+    ///
+    UINT32  RatioLimit:1;
+    ///
+    /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O)  When
+    /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
+    /// and when set to 0, indicates TDP Limit for Turbo mode is not
+    /// programmable.
+    ///
+    UINT32  TDPLimit:1;
+    UINT32  Reserved3:2;
+    ///
+    /// [Bit 32] Package. Low Power Mode Support (LPM) (R/O)  When set to 1,
+    /// indicates that LPM is supported, and when set to 0, indicates LPM is
+    /// not supported.
+    ///
+    UINT32  LowPowerModeSupport:1;
+    ///
+    /// [Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base
+    /// TDP level available. 01: One additional TDP level available. 02: Two
+    /// additional TDP level available. 11: Reserved.
+    ///
+    UINT32  ConfigTDPLevels:2;
+    UINT32  Reserved4:5;
+    ///
+    /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O)  The is the
+    /// minimum ratio (maximum efficiency) that the processor can operates, in
+    /// units of 100MHz.
+    ///
+    UINT32  MaximumEfficiencyRatio:8;
+    ///
+    /// [Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the
+    /// minimum supported operating ratio in units of 100 MHz.
+    ///
+    UINT32  MinimumOperatingRatio:8;
+    UINT32  Reserved5:8;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER;
+
+
+/**
+  Core. C-State Configuration Control (R/W)  Note: C-state values are
+  processor specific C-state code names, unrelated to MWAIT extension C-state
+  parameters or ACPI C-States. See http://biosbits.org.
+
+  @param  ECX  MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL (0x000000E2)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
+  @endcode
+  @note MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
+**/
+#define MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL    0x000000E2
+
+/**
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 2:0] Package C-State Limit (R/W)  Specifies the lowest
+    /// processor-specific C-state code name (consuming the least power). for
+    /// the package. The default is set as factory-configured package C-state
+    /// limit. The following C-state code name encodings are supported: 000b:
+    /// C0/C1 (no package C-sate support) 001b: C2 010b: C6 no retention 011b:
+    /// C6 retention 100b: C7 101b: C7s 111: No package C-state limit. Note:
+    /// This field cannot be used to limit package C-state to C3.
+    ///
+    UINT32  Limit:3;
+    UINT32  Reserved1:7;
+    ///
+    /// [Bit 10] I/O MWAIT Redirection Enable (R/W)  When set, will map
+    /// IO_read instructions sent to IO register specified by
+    /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
+    ///
+    UINT32  IO_MWAIT:1;
+    UINT32  Reserved2:4;
+    ///
+    /// [Bit 15] CFG Lock (R/WO)  When set, lock bits 15:0 of this register
+    /// until next reset.
+    ///
+    UINT32  CFGLock:1;
+    UINT32  Reserved3:9;
+    ///
+    /// [Bit 25] C3 state auto demotion enable (R/W)  When set, the processor
+    /// will conditionally demote C6/C7 requests to C3 based on uncore
+    /// auto-demote information.
+    ///
+    UINT32  C3AutoDemotion:1;
+    ///
+    /// [Bit 26] C1 state auto demotion enable (R/W)  When set, the processor
+    /// will conditionally demote C3/C6/C7 requests to C1 based on uncore
+    /// auto-demote information.
+    ///
+    UINT32  C1AutoDemotion:1;
+    ///
+    /// [Bit 27] Enable C3 undemotion (R/W)  When set, enables undemotion from
+    /// demoted C3.
+    ///
+    UINT32  C3Undemotion:1;
+    ///
+    /// [Bit 28] Enable C1 undemotion (R/W)  When set, enables undemotion from
+    /// demoted C1.
+    ///
+    UINT32  C1Undemotion:1;
+    UINT32  Reserved4:3;
+    UINT32  Reserved5:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER;
+
+
+/**
+  Package. PP0 Energy Status (R/O)  See Section 14.9.4, "PP0/PP1 RAPL
+  Domains.".
+
+  @param  ECX  MSR_IVY_BRIDGE_PP0_ENERGY_STATUS (0x00000639)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PP0_ENERGY_STATUS);
+  @endcode
+  @note MSR_IVY_BRIDGE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
+**/
+#define MSR_IVY_BRIDGE_PP0_ENERGY_STATUS         0x00000639
+
+
+/**
+  Package. Base TDP Ratio (R/O).
+
+  @param  ECX  MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL (0x00000648)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL);
+  @endcode
+  @note MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.
+**/
+#define MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL        0x00000648
+
+/**
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Config_TDP_Base Base TDP level ratio to be used for this
+    /// specific processor (in units of 100 MHz).
+    ///
+    UINT32  Config_TDP_Base:8;
+    UINT32  Reserved1:24;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER;
+
+
+/**
+  Package. ConfigTDP Level 1 ratio and power level (R/O).
+
+  @param  ECX  MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 (0x00000649)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1);
+  @endcode
+  @note MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1         0x00000649
+
+/**
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 14:0] PKG_TDP_LVL1. Power setting for ConfigTDP Level 1.
+    ///
+    UINT32  PKG_TDP_LVL1:15;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bits 23:16] Config_TDP_LVL1_Ratio. ConfigTDP level 1 ratio to be used
+    /// for this specific processor.
+    ///
+    UINT32  Config_TDP_LVL1_Ratio:8;
+    UINT32  Reserved2:8;
+    ///
+    /// [Bits 46:32] PKG_MAX_PWR_LVL1. Max Power setting allowed for ConfigTDP
+    /// Level 1.
+    ///
+    UINT32  PKG_MAX_PWR_LVL1:15;
+    UINT32  Reserved3:1;
+    ///
+    /// [Bits 62:48] PKG_MIN_PWR_LVL1. MIN Power setting allowed for ConfigTDP
+    /// Level 1.
+    ///
+    UINT32  PKG_MIN_PWR_LVL1:15;
+    UINT32  Reserved4:1;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER;
+
+
+/**
+  Package. ConfigTDP Level 2 ratio and power level (R/O).
+
+  @param  ECX  MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 (0x0000064A)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2);
+  @endcode
+  @note MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.
+**/
+#define MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2         0x0000064A
+
+/**
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 14:0] PKG_TDP_LVL2. Power setting for ConfigTDP Level 2.
+    ///
+    UINT32  PKG_TDP_LVL2:15;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bits 23:16] Config_TDP_LVL2_Ratio. ConfigTDP level 2 ratio to be used
+    /// for this specific processor.
+    ///
+    UINT32  Config_TDP_LVL2_Ratio:8;
+    UINT32  Reserved2:8;
+    ///
+    /// [Bits 46:32] PKG_MAX_PWR_LVL2. Max Power setting allowed for ConfigTDP
+    /// Level 2.
+    ///
+    UINT32  PKG_MAX_PWR_LVL2:15;
+    UINT32  Reserved3:1;
+    ///
+    /// [Bits 62:48] PKG_MIN_PWR_LVL2. MIN Power setting allowed for ConfigTDP
+    /// Level 2.
+    ///
+    UINT32  PKG_MIN_PWR_LVL2:15;
+    UINT32  Reserved4:1;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER;
+
+
+/**
+  Package. ConfigTDP Control (R/W).
+
+  @param  ECX  MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL (0x0000064B)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL, Msr.Uint64);
+  @endcode
+  @note MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.
+**/
+#define MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL        0x0000064B
+
+/**
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 1:0] TDP_LEVEL (RW/L) System BIOS can program this field.
+    ///
+    UINT32  TDP_LEVEL:2;
+    UINT32  Reserved1:29;
+    ///
+    /// [Bit 31] Config_TDP_Lock (RW/L) When this bit is set, the content of
+    /// this register is locked until a reset.
+    ///
+    UINT32  Config_TDP_Lock:1;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER;
+
+
+/**
+  Package. ConfigTDP Control (R/W).
+
+  @param  ECX  MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO (0x0000064C)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO, Msr.Uint64);
+  @endcode
+  @note MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.
+**/
+#define MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO    0x0000064C
+
+/**
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this
+    /// field.
+    ///
+    UINT32  MAX_NON_TURBO_RATIO:8;
+    UINT32  Reserved1:23;
+    ///
+    /// [Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the
+    /// content of this register is locked until a reset.
+    ///
+    UINT32  TURBO_ACTIVATION_RATIO_Lock:1;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER;
+
+
+/**
+  Package. Protected Processor Inventory Number Enable Control (R/W).
+
+  @param  ECX  MSR_IVY_BRIDGE_PPIN_CTL (0x0000004E)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_PPIN_CTL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_PPIN_CTL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IVY_BRIDGE_PPIN_CTL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_PPIN_CTL, Msr.Uint64);
+  @endcode
+  @note MSR_IVY_BRIDGE_PPIN_CTL is defined as MSR_PPIN_CTL in SDM.
+**/
+#define MSR_IVY_BRIDGE_PPIN_CTL                  0x0000004E
+
+/**
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_PPIN_CTL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] LockOut (R/WO) Set 1to prevent further writes to MSR_PPIN_CTL.
+    /// Writing 1 to MSR_PPINCTL[bit 0] is permitted only if MSR_PPIN_CTL[bit
+    /// 1] is clear, Default is 0. BIOS should provide an opt-in menu to
+    /// enable the user to turn on MSR_PPIN_CTL[bit 1] for privileged
+    /// inventory initialization agent to access MSR_PPIN. After reading
+    /// MSR_PPIN, the privileged inventory initialization agent should write
+    /// '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and
+    /// prevent unauthorized modification to MSR_PPIN_CTL.
+    ///
+    UINT32  LockOut:1;
+    ///
+    /// [Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible
+    /// using RDMSR. Once set, attempt to write 1 to MSR_PPIN_CTL[bit 0] will
+    /// cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP. Default
+    /// is 0.
+    ///
+    UINT32  Enable_PPIN:1;
+    UINT32  Reserved1:30;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IVY_BRIDGE_PPIN_CTL_REGISTER;
+
+
+/**
+  Package. Protected Processor Inventory Number (R/O). Protected Processor
+  Inventory Number (R/O) A unique value within a given CPUID
+  family/model/stepping signature that a privileged inventory initialization
+  agent can access to identify each physical processor, when access to
+  MSR_PPIN is enabled. Access to MSR_PPIN is permitted only if
+  MSR_PPIN_CTL[bits 1:0] = '10b'.
+
+  @param  ECX  MSR_IVY_BRIDGE_PPIN (0x0000004F)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN);
+  @endcode
+  @note MSR_IVY_BRIDGE_PPIN is defined as MSR_PPIN in SDM.
+**/
+#define MSR_IVY_BRIDGE_PPIN                      0x0000004F
+
+
+/**
+  Package. See http://biosbits.org.
+
+  @param  ECX  MSR_IVY_BRIDGE_PLATFORM_INFO_1 (0x000000CE)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1, Msr.Uint64);
+  @endcode
+  @note MSR_IVY_BRIDGE_PLATFORM_INFO_1 is defined as MSR_PLATFORM_INFO_1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_PLATFORM_INFO_1           0x000000CE
+
+/**
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO_1
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:8;
+    ///
+    /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O)  The is the ratio
+    /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
+    /// MHz.
+    ///
+    UINT32  MaximumNonTurboRatio:8;
+    UINT32  Reserved2:7;
+    ///
+    /// [Bit 23] Package. PPIN_CAP (R/O) When set to 1, indicates that
+    /// Protected Processor Inventory Number (PPIN) capability can be enabled
+    /// for privileged system inventory agent to read PPIN from MSR_PPIN. When
+    /// set to 0, PPIN capability is not supported. An attempt to access
+    /// MSR_PPIN_CTL or MSR_PPIN will cause #GP.
+    ///
+    UINT32  PPIN_CAP:1;
+    UINT32  Reserved3:4;
+    ///
+    /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O)  When
+    /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
+    /// enabled, and when set to 0, indicates Programmable Ratio Limits for
+    /// Turbo mode is disabled.
+    ///
+    UINT32  RatioLimit:1;
+    ///
+    /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O)  When
+    /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
+    /// and when set to 0, indicates TDP Limit for Turbo mode is not
+    /// programmable.
+    ///
+    UINT32  TDPLimit:1;
+    ///
+    /// [Bit 30] Package. Programmable TJ OFFSET (R/O)  When set to 1,
+    /// indicates that MSR_TEMPERATURE_TARGET.[27:24] is valid and writable to
+    /// specify an temperature offset.
+    ///
+    UINT32  TJOFFSET:1;
+    UINT32  Reserved4:1;
+    UINT32  Reserved5:8;
+    ///
+    /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O)  The is the
+    /// minimum ratio (maximum efficiency) that the processor can operates, in
+    /// units of 100MHz.
+    ///
+    UINT32  MaximumEfficiencyRatio:8;
+    UINT32  Reserved6:16;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER;
+
+
+/**
+  Package. MC Bank Error Configuration (R/W).
+
+  @param  ECX  MSR_IVY_BRIDGE_ERROR_CONTROL (0x0000017F)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_ERROR_CONTROL);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_ERROR_CONTROL, Msr.Uint64);
+  @endcode
+  @note MSR_IVY_BRIDGE_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.
+**/
+#define MSR_IVY_BRIDGE_ERROR_CONTROL             0x0000017F
+
+/**
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_ERROR_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 1] MemError Log Enable (R/W)  When set, enables IMC status bank
+    /// to log additional info in bits 36:32.
+    ///
+    UINT32  MemErrorLogEnable:1;
+    UINT32  Reserved2:30;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER;
+
+
+/**
+  Package.
+
+  @param  ECX  MSR_IVY_BRIDGE_TEMPERATURE_TARGET (0x000001A2)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TEMPERATURE_TARGET);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_TEMPERATURE_TARGET, Msr.Uint64);
+  @endcode
+  @note MSR_IVY_BRIDGE_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
+**/
+#define MSR_IVY_BRIDGE_TEMPERATURE_TARGET        0x000001A2
+
+/**
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_TEMPERATURE_TARGET
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:16;
+    ///
+    /// [Bits 23:16] Temperature Target (RO)  The minimum temperature at which
+    /// PROCHOT# will be asserted. The value is degree C.
+    ///
+    UINT32  TemperatureTarget:8;
+    ///
+    /// [Bits 27:24] TCC Activation Offset (R/W)  Specifies a temperature
+    /// offset in degrees C from the temperature target (bits 23:16). PROCHOT#
+    /// will assert at the offset target temperature. Write is permitted only
+    /// MSR_PLATFORM_INFO.[30] is set.
+    ///
+    UINT32  TCCActivationOffset:4;
+    UINT32  Reserved2:4;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER;
+
+
+/**
+  Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
+  RW if MSR_PLATFORM_INFO.[28] = 1.
+
+  @param  ECX  MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 (0x000001AE)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1);
+  @endcode
+  @note MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1        0x000001AE
+
+/**
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio
+    /// limit of 9 core active.
+    ///
+    UINT32  Maximum9C:8;
+    ///
+    /// [Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio
+    /// limit of 10core active.
+    ///
+    UINT32  Maximum10C:8;
+    ///
+    /// [Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio
+    /// limit of 11 core active.
+    ///
+    UINT32  Maximum11C:8;
+    ///
+    /// [Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio
+    /// limit of 12 core active.
+    ///
+    UINT32  Maximum12C:8;
+    ///
+    /// [Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio
+    /// limit of 13 core active.
+    ///
+    UINT32  Maximum13C:8;
+    ///
+    /// [Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio
+    /// limit of 14 core active.
+    ///
+    UINT32  Maximum14C:8;
+    ///
+    /// [Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio
+    /// limit of 15 core active.
+    ///
+    UINT32  Maximum15C:8;
+    UINT32  Reserved:7;
+    ///
+    /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,
+    /// the processor uses override configuration specified in
+    /// MSR_TURBO_RATIO_LIMIT and MSR_TURBO_RATIO_LIMIT1. If 0, the processor
+    /// uses factory-set configuration (Default).
+    ///
+    UINT32  TurboRatioLimitConfigurationSemaphore:1;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER;
+
+
+/**
+  Package. Misc MAC information of Integrated I/O. (R/O) see Section 15.3.2.4.
+
+  @param  ECX  MSR_IVY_BRIDGE_IA32_MC6_MISC (0x0000041B)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC6_MISC);
+  @endcode
+  @note MSR_IVY_BRIDGE_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM.
+**/
+#define MSR_IVY_BRIDGE_IA32_MC6_MISC             0x0000041B
+
+/**
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_IA32_MC6_MISC
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 5:0] Recoverable Address LSB.
+    ///
+    UINT32  RecoverableAddressLSB:6;
+    ///
+    /// [Bits 8:6] Address Mode.
+    ///
+    UINT32  AddressMode:3;
+    UINT32  Reserved1:7;
+    ///
+    /// [Bits 31:16] PCI Express Requestor ID.
+    ///
+    UINT32  PCIExpressRequestorID:16;
+    ///
+    /// [Bits 39:32] PCI Express Segment Number.
+    ///
+    UINT32  PCIExpressSegmentNumber:8;
+    UINT32  Reserved2:24;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER;
+
+
+/**
+  Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
+  15.3.2.4, "IA32_MCi_MISC MSRs.".
+
+  Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)
+  and its corresponding slice of L3.
+
+  @param  ECX  MSR_IVY_BRIDGE_IA32_MCi_CTL
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_CTL);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_CTL, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_IA32_MC29_CTL is defined as IA32_MC29_CTL in SDM.
+        MSR_IVY_BRIDGE_IA32_MC30_CTL is defined as IA32_MC30_CTL in SDM.
+        MSR_IVY_BRIDGE_IA32_MC31_CTL is defined as IA32_MC31_CTL in SDM.
+  @{
+**/
+#define MSR_IVY_BRIDGE_IA32_MC29_CTL             0x00000474
+#define MSR_IVY_BRIDGE_IA32_MC30_CTL             0x00000478
+#define MSR_IVY_BRIDGE_IA32_MC31_CTL             0x0000047C
+/// @}
+
+
+/**
+  Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
+  15.3.2.4, "IA32_MCi_MISC MSRs.".
+
+  Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)
+  and its corresponding slice of L3.
+
+  @param  ECX  MSR_IVY_BRIDGE_IA32_MCi_STATUS
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_STATUS);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_STATUS, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_IA32_MC29_STATUS is defined as IA32_MC29_STATUS in SDM.
+        MSR_IVY_BRIDGE_IA32_MC30_STATUS is defined as IA32_MC30_STATUS in SDM.
+        MSR_IVY_BRIDGE_IA32_MC31_STATUS is defined as IA32_MC31_STATUS in SDM.
+  @{
+**/
+#define MSR_IVY_BRIDGE_IA32_MC29_STATUS          0x00000475
+#define MSR_IVY_BRIDGE_IA32_MC30_STATUS          0x00000479
+#define MSR_IVY_BRIDGE_IA32_MC31_STATUS          0x0000047D
+/// @}
+
+
+/**
+  Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
+  15.3.2.4, "IA32_MCi_MISC MSRs.".
+
+  Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)
+  and its corresponding slice of L3.
+
+  @param  ECX  MSR_IVY_BRIDGE_IA32_MCi_ADDR
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_ADDR);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_ADDR, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_IA32_MC29_ADDR is defined as IA32_MC29_ADDR in SDM.
+        MSR_IVY_BRIDGE_IA32_MC30_ADDR is defined as IA32_MC30_ADDR in SDM.
+        MSR_IVY_BRIDGE_IA32_MC31_ADDR is defined as IA32_MC31_ADDR in SDM.
+  @{
+**/
+#define MSR_IVY_BRIDGE_IA32_MC29_ADDR            0x00000476
+#define MSR_IVY_BRIDGE_IA32_MC30_ADDR            0x0000047A
+#define MSR_IVY_BRIDGE_IA32_MC31_ADDR            0x0000047E
+/// @}
+
+
+/**
+  Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section
+  15.3.2.4, "IA32_MCi_MISC MSRs.".
+
+  Bank MC29 through MC31 reports MC error from a specific CBo (core broadcast)
+  and its corresponding slice of L3.
+
+  @param  ECX  MSR_IVY_BRIDGE_IA32_MCi_MISC
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_IA32_MC29_MISC);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_IA32_MC29_MISC, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_IA32_MC29_MISC is defined as IA32_MC29_MISC in SDM.
+        MSR_IVY_BRIDGE_IA32_MC30_MISC is defined as IA32_MC30_MISC in SDM.
+        MSR_IVY_BRIDGE_IA32_MC31_MISC is defined as IA32_MC31_MISC in SDM.
+  @{
+**/
+#define MSR_IVY_BRIDGE_IA32_MC29_MISC            0x00000477
+#define MSR_IVY_BRIDGE_IA32_MC30_MISC            0x0000047B
+#define MSR_IVY_BRIDGE_IA32_MC31_MISC            0x0000047F
+/// @}
+
+
+/**
+  Package. Package RAPL Perf Status (R/O).
+
+  @param  ECX  MSR_IVY_BRIDGE_PKG_PERF_STATUS (0x00000613)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PKG_PERF_STATUS);
+  @endcode
+  @note MSR_IVY_BRIDGE_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.
+**/
+#define MSR_IVY_BRIDGE_PKG_PERF_STATUS           0x00000613
+
+
+/**
+  Package. DRAM RAPL Power Limit Control (R/W)  See Section 14.9.5, "DRAM RAPL
+  Domain.".
+
+  @param  ECX  MSR_IVY_BRIDGE_DRAM_POWER_LIMIT (0x00000618)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_LIMIT);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_LIMIT, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
+**/
+#define MSR_IVY_BRIDGE_DRAM_POWER_LIMIT          0x00000618
+
+
+/**
+  Package. DRAM Energy Status (R/O)  See Section 14.9.5, "DRAM RAPL Domain.".
+
+  @param  ECX  MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS (0x00000619)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS);
+  @endcode
+  @note MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
+**/
+#define MSR_IVY_BRIDGE_DRAM_ENERGY_STATUS        0x00000619
+
+
+/**
+  Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
+  RAPL Domain.".
+
+  @param  ECX  MSR_IVY_BRIDGE_DRAM_PERF_STATUS (0x0000061B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_PERF_STATUS);
+  @endcode
+  @note MSR_IVY_BRIDGE_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
+**/
+#define MSR_IVY_BRIDGE_DRAM_PERF_STATUS          0x0000061B
+
+
+/**
+  Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
+
+  @param  ECX  MSR_IVY_BRIDGE_DRAM_POWER_INFO (0x0000061C)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_INFO);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_DRAM_POWER_INFO, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
+**/
+#define MSR_IVY_BRIDGE_DRAM_POWER_INFO           0x0000061C
+
+
+/**
+  Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).".
+
+  @param  ECX  MSR_IVY_BRIDGE_PEBS_ENABLE (0x000003F1)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PEBS_ENABLE);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_PEBS_ENABLE, Msr.Uint64);
+  @endcode
+  @note MSR_IVY_BRIDGE_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
+**/
+#define MSR_IVY_BRIDGE_PEBS_ENABLE               0x000003F1
+
+/**
+  MSR information returned for MSR index #MSR_IVY_BRIDGE_PEBS_ENABLE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
+    ///
+    UINT32  PEBS_EN_PMC0:1;
+    ///
+    /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).
+    ///
+    UINT32  PEBS_EN_PMC1:1;
+    ///
+    /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).
+    ///
+    UINT32  PEBS_EN_PMC2:1;
+    ///
+    /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).
+    ///
+    UINT32  PEBS_EN_PMC3:1;
+    UINT32  Reserved1:28;
+    ///
+    /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).
+    ///
+    UINT32  LL_EN_PMC0:1;
+    ///
+    /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).
+    ///
+    UINT32  LL_EN_PMC1:1;
+    ///
+    /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).
+    ///
+    UINT32  LL_EN_PMC2:1;
+    ///
+    /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).
+    ///
+    UINT32  LL_EN_PMC3:1;
+    UINT32  Reserved2:28;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER;
+
+
+/**
+  Package. Uncore perfmon per-socket global control.
+
+  @param  ECX  MSR_IVY_BRIDGE_PMON_GLOBAL_CTL (0x00000C00)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CTL);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CTL, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_PMON_GLOBAL_CTL is defined as MSR_PMON_GLOBAL_CTL in SDM.
+**/
+#define MSR_IVY_BRIDGE_PMON_GLOBAL_CTL           0x00000C00
+
+
+/**
+  Package. Uncore perfmon per-socket global status.
+
+  @param  ECX  MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS (0x00000C01)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS is defined as MSR_PMON_GLOBAL_STATUS in SDM.
+**/
+#define MSR_IVY_BRIDGE_PMON_GLOBAL_STATUS        0x00000C01
+
+
+/**
+  Package. Uncore perfmon per-socket global configuration.
+
+  @param  ECX  MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG (0x00000C06)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG is defined as MSR_PMON_GLOBAL_CONFIG in SDM.
+**/
+#define MSR_IVY_BRIDGE_PMON_GLOBAL_CONFIG        0x00000C06
+
+
+/**
+  Package. Uncore U-box perfmon U-box wide status.
+
+  @param  ECX  MSR_IVY_BRIDGE_U_PMON_BOX_STATUS (0x00000C15)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_U_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_U_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_U_PMON_BOX_STATUS is defined as MSR_U_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_IVY_BRIDGE_U_PMON_BOX_STATUS         0x00000C15
+
+
+/**
+  Package. Uncore PCU perfmon box wide status.
+
+  @param  ECX  MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS (0x00000C35)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS is defined as MSR_PCU_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_IVY_BRIDGE_PCU_PMON_BOX_STATUS       0x00000C35
+
+
+/**
+  Package. Uncore C-box 0 perfmon box wide filter1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 (0x00000D1A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1 is defined as MSR_C0_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C0_PMON_BOX_FILTER1       0x00000D1A
+
+
+/**
+  Package. Uncore C-box 1 perfmon box wide filter1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 (0x00000D3A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1 is defined as MSR_C1_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C1_PMON_BOX_FILTER1       0x00000D3A
+
+
+/**
+  Package. Uncore C-box 2 perfmon box wide filter1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 (0x00000D5A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1 is defined as MSR_C2_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C2_PMON_BOX_FILTER1       0x00000D5A
+
+
+/**
+  Package. Uncore C-box 3 perfmon box wide filter1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 (0x00000D7A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1 is defined as MSR_C3_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C3_PMON_BOX_FILTER1       0x00000D7A
+
+
+/**
+  Package. Uncore C-box 4 perfmon box wide filter1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 (0x00000D9A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1 is defined as MSR_C4_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C4_PMON_BOX_FILTER1       0x00000D9A
+
+
+/**
+  Package. Uncore C-box 5 perfmon box wide filter1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 (0x00000DBA)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1 is defined as MSR_C5_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C5_PMON_BOX_FILTER1       0x00000DBA
+
+
+/**
+  Package. Uncore C-box 6 perfmon box wide filter1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 (0x00000DDA)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1 is defined as MSR_C6_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C6_PMON_BOX_FILTER1       0x00000DDA
+
+
+/**
+  Package. Uncore C-box 7 perfmon box wide filter1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 (0x00000DFA)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1 is defined as MSR_C7_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C7_PMON_BOX_FILTER1       0x00000DFA
+
+
+/**
+  Package. Uncore C-box 8 perfmon local box wide control.
+
+  @param  ECX  MSR_IVY_BRIDGE_C8_PMON_BOX_CTL (0x00000E04)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C8_PMON_BOX_CTL is defined as MSR_C8_PMON_BOX_CTL in SDM.
+**/
+#define MSR_IVY_BRIDGE_C8_PMON_BOX_CTL           0x00000E04
+
+
+/**
+  Package. Uncore C-box 8 perfmon event select for C-box 8 counter 0.
+
+  @param  ECX  MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 (0x00000E10)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0 is defined as MSR_C8_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL0          0x00000E10
+
+
+/**
+  Package. Uncore C-box 8 perfmon event select for C-box 8 counter 1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 (0x00000E11)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1 is defined as MSR_C8_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL1          0x00000E11
+
+
+/**
+  Package. Uncore C-box 8 perfmon event select for C-box 8 counter 2.
+
+  @param  ECX  MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 (0x00000E12)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2 is defined as MSR_C8_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL2          0x00000E12
+
+
+/**
+  Package. Uncore C-box 8 perfmon event select for C-box 8 counter 3.
+
+  @param  ECX  MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 (0x00000E13)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3 is defined as MSR_C8_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C8_PMON_EVNTSEL3          0x00000E13
+
+
+/**
+  Package. Uncore C-box 8 perfmon box wide filter.
+
+  @param  ECX  MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER (0x00000E14)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER is defined as MSR_C8_PMON_BOX_FILTER in SDM.
+**/
+#define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER        0x00000E14
+
+
+/**
+  Package. Uncore C-box 8 perfmon counter 0.
+
+  @param  ECX  MSR_IVY_BRIDGE_C8_PMON_CTR0 (0x00000E16)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR0);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C8_PMON_CTR0              0x00000E16
+
+
+/**
+  Package. Uncore C-box 8 perfmon counter 1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C8_PMON_CTR1 (0x00000E17)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C8_PMON_CTR1              0x00000E17
+
+
+/**
+  Package. Uncore C-box 8 perfmon counter 2.
+
+  @param  ECX  MSR_IVY_BRIDGE_C8_PMON_CTR2 (0x00000E18)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR2);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C8_PMON_CTR2              0x00000E18
+
+
+/**
+  Package. Uncore C-box 8 perfmon counter 3.
+
+  @param  ECX  MSR_IVY_BRIDGE_C8_PMON_CTR3 (0x00000E19)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR3);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C8_PMON_CTR3              0x00000E19
+
+
+/**
+  Package. Uncore C-box 8 perfmon box wide filter1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 (0x00000E1A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1 is defined as MSR_C8_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C8_PMON_BOX_FILTER1       0x00000E1A
+
+
+/**
+  Package. Uncore C-box 9 perfmon local box wide control.
+
+  @param  ECX  MSR_IVY_BRIDGE_C9_PMON_BOX_CTL (0x00000E24)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C9_PMON_BOX_CTL is defined as MSR_C9_PMON_BOX_CTL in SDM.
+**/
+#define MSR_IVY_BRIDGE_C9_PMON_BOX_CTL           0x00000E24
+
+
+/**
+  Package. Uncore C-box 9 perfmon event select for C-box 9 counter 0.
+
+  @param  ECX  MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 (0x00000E30)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0 is defined as MSR_C9_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL0          0x00000E30
+
+
+/**
+  Package. Uncore C-box 9 perfmon event select for C-box 9 counter 1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 (0x00000E31)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1 is defined as MSR_C9_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL1          0x00000E31
+
+
+/**
+  Package. Uncore C-box 9 perfmon event select for C-box 9 counter 2.
+
+  @param  ECX  MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 (0x00000E32)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2 is defined as MSR_C9_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL2          0x00000E32
+
+
+/**
+  Package. Uncore C-box 9 perfmon event select for C-box 9 counter 3.
+
+  @param  ECX  MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 (0x00000E33)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3 is defined as MSR_C9_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C9_PMON_EVNTSEL3          0x00000E33
+
+
+/**
+  Package. Uncore C-box 9 perfmon box wide filter.
+
+  @param  ECX  MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER (0x00000E34)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER is defined as MSR_C9_PMON_BOX_FILTER in SDM.
+**/
+#define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER        0x00000E34
+
+
+/**
+  Package. Uncore C-box 9 perfmon counter 0.
+
+  @param  ECX  MSR_IVY_BRIDGE_C9_PMON_CTR0 (0x00000E36)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR0);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C9_PMON_CTR0              0x00000E36
+
+
+/**
+  Package. Uncore C-box 9 perfmon counter 1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C9_PMON_CTR1 (0x00000E37)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C9_PMON_CTR1              0x00000E37
+
+
+/**
+  Package. Uncore C-box 9 perfmon counter 2.
+
+  @param  ECX  MSR_IVY_BRIDGE_C9_PMON_CTR2 (0x00000E38)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR2);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C9_PMON_CTR2              0x00000E38
+
+
+/**
+  Package. Uncore C-box 9 perfmon counter 3.
+
+  @param  ECX  MSR_IVY_BRIDGE_C9_PMON_CTR3 (0x00000E39)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR3);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C9_PMON_CTR3              0x00000E39
+
+
+/**
+  Package. Uncore C-box 9 perfmon box wide filter1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 (0x00000E3A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1 is defined as MSR_C9_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C9_PMON_BOX_FILTER1       0x00000E3A
+
+
+/**
+  Package. Uncore C-box 10 perfmon local box wide control.
+
+  @param  ECX  MSR_IVY_BRIDGE_C10_PMON_BOX_CTL (0x00000E44)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C10_PMON_BOX_CTL is defined as MSR_C10_PMON_BOX_CTL in SDM.
+**/
+#define MSR_IVY_BRIDGE_C10_PMON_BOX_CTL          0x00000E44
+
+
+/**
+  Package. Uncore C-box 10 perfmon event select for C-box 10 counter 0.
+
+  @param  ECX  MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 (0x00000E50)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0 is defined as MSR_C10_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL0         0x00000E50
+
+
+/**
+  Package. Uncore C-box 10 perfmon event select for C-box 10 counter 1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 (0x00000E51)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1 is defined as MSR_C10_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL1         0x00000E51
+
+
+/**
+  Package. Uncore C-box 10 perfmon event select for C-box 10 counter 2.
+
+  @param  ECX  MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 (0x00000E52)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2 is defined as MSR_C10_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL2         0x00000E52
+
+
+/**
+  Package. Uncore C-box 10 perfmon event select for C-box 10 counter 3.
+
+  @param  ECX  MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 (0x00000E53)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3 is defined as MSR_C10_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C10_PMON_EVNTSEL3         0x00000E53
+
+
+/**
+  Package. Uncore C-box 10 perfmon box wide filter.
+
+  @param  ECX  MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER (0x00000E54)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER is defined as MSR_C10_PMON_BOX_FILTER in SDM.
+**/
+#define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER       0x00000E54
+
+
+/**
+  Package. Uncore C-box 10 perfmon counter 0.
+
+  @param  ECX  MSR_IVY_BRIDGE_C10_PMON_CTR0 (0x00000E56)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR0);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C10_PMON_CTR0 is defined as MSR_C10_PMON_CTR0 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C10_PMON_CTR0             0x00000E56
+
+
+/**
+  Package. Uncore C-box 10 perfmon counter 1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C10_PMON_CTR1 (0x00000E57)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C10_PMON_CTR1 is defined as MSR_C10_PMON_CTR1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C10_PMON_CTR1             0x00000E57
+
+
+/**
+  Package. Uncore C-box 10 perfmon counter 2.
+
+  @param  ECX  MSR_IVY_BRIDGE_C10_PMON_CTR2 (0x00000E58)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR2);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C10_PMON_CTR2 is defined as MSR_C10_PMON_CTR2 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C10_PMON_CTR2             0x00000E58
+
+
+/**
+  Package. Uncore C-box 10 perfmon counter 3.
+
+  @param  ECX  MSR_IVY_BRIDGE_C10_PMON_CTR3 (0x00000E59)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR3);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C10_PMON_CTR3 is defined as MSR_C10_PMON_CTR3 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C10_PMON_CTR3             0x00000E59
+
+
+/**
+  Package. Uncore C-box 10 perfmon box wide filter1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 (0x00000E5A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1 is defined as MSR_C10_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C10_PMON_BOX_FILTER1      0x00000E5A
+
+
+/**
+  Package. Uncore C-box 11 perfmon local box wide control.
+
+  @param  ECX  MSR_IVY_BRIDGE_C11_PMON_BOX_CTL (0x00000E64)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C11_PMON_BOX_CTL is defined as MSR_C11_PMON_BOX_CTL in SDM.
+**/
+#define MSR_IVY_BRIDGE_C11_PMON_BOX_CTL          0x00000E64
+
+
+/**
+  Package. Uncore C-box 11 perfmon event select for C-box 11 counter 0.
+
+  @param  ECX  MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 (0x00000E70)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0 is defined as MSR_C11_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL0         0x00000E70
+
+
+/**
+  Package. Uncore C-box 11 perfmon event select for C-box 11 counter 1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 (0x00000E71)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1 is defined as MSR_C11_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL1         0x00000E71
+
+
+/**
+  Package. Uncore C-box 11 perfmon event select for C-box 11 counter 2.
+
+  @param  ECX  MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 (0x00000E72)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2 is defined as MSR_C11_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL2         0x00000E72
+
+
+/**
+  Package. Uncore C-box 11 perfmon event select for C-box 11 counter 3.
+
+  @param  ECX  MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 (0x00000E73)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3 is defined as MSR_C11_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C11_PMON_EVNTSEL3         0x00000E73
+
+
+/**
+  Package. Uncore C-box 11 perfmon box wide filter.
+
+  @param  ECX  MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER (0x00000E74)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER is defined as MSR_C11_PMON_BOX_FILTER in SDM.
+**/
+#define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER       0x00000E74
+
+
+/**
+  Package. Uncore C-box 11 perfmon counter 0.
+
+  @param  ECX  MSR_IVY_BRIDGE_C11_PMON_CTR0 (0x00000E76)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR0);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C11_PMON_CTR0 is defined as MSR_C11_PMON_CTR0 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C11_PMON_CTR0             0x00000E76
+
+
+/**
+  Package. Uncore C-box 11 perfmon counter 1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C11_PMON_CTR1 (0x00000E77)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C11_PMON_CTR1 is defined as MSR_C11_PMON_CTR1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C11_PMON_CTR1             0x00000E77
+
+
+/**
+  Package. Uncore C-box 11 perfmon counter 2.
+
+  @param  ECX  MSR_IVY_BRIDGE_C11_PMON_CTR2 (0x00000E78)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR2);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C11_PMON_CTR2 is defined as MSR_C11_PMON_CTR2 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C11_PMON_CTR2             0x00000E78
+
+
+/**
+  Package. Uncore C-box 11 perfmon counter 3.
+
+  @param  ECX  MSR_IVY_BRIDGE_C11_PMON_CTR3 (0x00000E79)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR3);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C11_PMON_CTR3 is defined as MSR_C11_PMON_CTR3 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C11_PMON_CTR3             0x00000E79
+
+
+/**
+  Package. Uncore C-box 11 perfmon box wide filter1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 (0x00000E7A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1 is defined as MSR_C11_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C11_PMON_BOX_FILTER1      0x00000E7A
+
+
+/**
+  Package. Uncore C-box 12 perfmon local box wide control.
+
+  @param  ECX  MSR_IVY_BRIDGE_C12_PMON_BOX_CTL (0x00000E84)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C12_PMON_BOX_CTL is defined as MSR_C12_PMON_BOX_CTL in SDM.
+**/
+#define MSR_IVY_BRIDGE_C12_PMON_BOX_CTL          0x00000E84
+
+
+/**
+  Package. Uncore C-box 12 perfmon event select for C-box 12 counter 0.
+
+  @param  ECX  MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 (0x00000E90)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0 is defined as MSR_C12_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL0         0x00000E90
+
+
+/**
+  Package. Uncore C-box 12 perfmon event select for C-box 12 counter 1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 (0x00000E91)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1 is defined as MSR_C12_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL1         0x00000E91
+
+
+/**
+  Package. Uncore C-box 12 perfmon event select for C-box 12 counter 2.
+
+  @param  ECX  MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 (0x00000E92)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2 is defined as MSR_C12_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL2         0x00000E92
+
+
+/**
+  Package. Uncore C-box 12 perfmon event select for C-box 12 counter 3.
+
+  @param  ECX  MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 (0x00000E93)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3 is defined as MSR_C12_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C12_PMON_EVNTSEL3         0x00000E93
+
+
+/**
+  Package. Uncore C-box 12 perfmon box wide filter.
+
+  @param  ECX  MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER (0x00000E94)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER is defined as MSR_C12_PMON_BOX_FILTER in SDM.
+**/
+#define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER       0x00000E94
+
+
+/**
+  Package. Uncore C-box 12 perfmon counter 0.
+
+  @param  ECX  MSR_IVY_BRIDGE_C12_PMON_CTR0 (0x00000E96)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR0);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C12_PMON_CTR0 is defined as MSR_C12_PMON_CTR0 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C12_PMON_CTR0             0x00000E96
+
+
+/**
+  Package. Uncore C-box 12 perfmon counter 1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C12_PMON_CTR1 (0x00000E97)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C12_PMON_CTR1 is defined as MSR_C12_PMON_CTR1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C12_PMON_CTR1             0x00000E97
+
+
+/**
+  Package. Uncore C-box 12 perfmon counter 2.
+
+  @param  ECX  MSR_IVY_BRIDGE_C12_PMON_CTR2 (0x00000E98)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR2);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C12_PMON_CTR2 is defined as MSR_C12_PMON_CTR2 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C12_PMON_CTR2             0x00000E98
+
+
+/**
+  Package. Uncore C-box 12 perfmon counter 3.
+
+  @param  ECX  MSR_IVY_BRIDGE_C12_PMON_CTR3 (0x00000E99)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR3);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C12_PMON_CTR3 is defined as MSR_C12_PMON_CTR3 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C12_PMON_CTR3             0x00000E99
+
+
+/**
+  Package. Uncore C-box 12 perfmon box wide filter1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 (0x00000E9A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1 is defined as MSR_C12_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C12_PMON_BOX_FILTER1      0x00000E9A
+
+
+/**
+  Package. Uncore C-box 13 perfmon local box wide control.
+
+  @param  ECX  MSR_IVY_BRIDGE_C13_PMON_BOX_CTL (0x00000EA4)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C13_PMON_BOX_CTL is defined as MSR_C13_PMON_BOX_CTL in SDM.
+**/
+#define MSR_IVY_BRIDGE_C13_PMON_BOX_CTL          0x00000EA4
+
+
+/**
+  Package. Uncore C-box 13 perfmon event select for C-box 13 counter 0.
+
+  @param  ECX  MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 (0x00000EB0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0 is defined as MSR_C13_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL0         0x00000EB0
+
+
+/**
+  Package. Uncore C-box 13 perfmon event select for C-box 13 counter 1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 (0x00000EB1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1 is defined as MSR_C13_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL1         0x00000EB1
+
+
+/**
+  Package. Uncore C-box 13 perfmon event select for C-box 13 counter 2.
+
+  @param  ECX  MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 (0x00000EB2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2 is defined as MSR_C13_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL2         0x00000EB2
+
+
+/**
+  Package. Uncore C-box 13 perfmon event select for C-box 13 counter 3.
+
+  @param  ECX  MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 (0x00000EB3)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3 is defined as MSR_C13_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C13_PMON_EVNTSEL3         0x00000EB3
+
+
+/**
+  Package. Uncore C-box 13 perfmon box wide filter.
+
+  @param  ECX  MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER (0x00000EB4)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER is defined as MSR_C13_PMON_BOX_FILTER in SDM.
+**/
+#define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER       0x00000EB4
+
+
+/**
+  Package. Uncore C-box 13 perfmon counter 0.
+
+  @param  ECX  MSR_IVY_BRIDGE_C13_PMON_CTR0 (0x00000EB6)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR0);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C13_PMON_CTR0 is defined as MSR_C13_PMON_CTR0 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C13_PMON_CTR0             0x00000EB6
+
+
+/**
+  Package. Uncore C-box 13 perfmon counter 1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C13_PMON_CTR1 (0x00000EB7)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C13_PMON_CTR1 is defined as MSR_C13_PMON_CTR1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C13_PMON_CTR1             0x00000EB7
+
+
+/**
+  Package. Uncore C-box 13 perfmon counter 2.
+
+  @param  ECX  MSR_IVY_BRIDGE_C13_PMON_CTR2 (0x00000EB8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR2);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C13_PMON_CTR2 is defined as MSR_C13_PMON_CTR2 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C13_PMON_CTR2             0x00000EB8
+
+
+/**
+  Package. Uncore C-box 13 perfmon counter 3.
+
+  @param  ECX  MSR_IVY_BRIDGE_C13_PMON_CTR3 (0x00000EB9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR3);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C13_PMON_CTR3 is defined as MSR_C13_PMON_CTR3 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C13_PMON_CTR3             0x00000EB9
+
+
+/**
+  Package. Uncore C-box 13 perfmon box wide filter1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 (0x00000EBA)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1 is defined as MSR_C13_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C13_PMON_BOX_FILTER1      0x00000EBA
+
+
+/**
+  Package. Uncore C-box 14 perfmon local box wide control.
+
+  @param  ECX  MSR_IVY_BRIDGE_C14_PMON_BOX_CTL (0x00000EC4)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C14_PMON_BOX_CTL is defined as MSR_C14_PMON_BOX_CTL in SDM.
+**/
+#define MSR_IVY_BRIDGE_C14_PMON_BOX_CTL          0x00000EC4
+
+
+/**
+  Package. Uncore C-box 14 perfmon event select for C-box 14 counter 0.
+
+  @param  ECX  MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 (0x00000ED0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0 is defined as MSR_C14_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL0         0x00000ED0
+
+
+/**
+  Package. Uncore C-box 14 perfmon event select for C-box 14 counter 1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 (0x00000ED1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1 is defined as MSR_C14_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL1         0x00000ED1
+
+
+/**
+  Package. Uncore C-box 14 perfmon event select for C-box 14 counter 2.
+
+  @param  ECX  MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 (0x00000ED2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2 is defined as MSR_C14_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL2         0x00000ED2
+
+
+/**
+  Package. Uncore C-box 14 perfmon event select for C-box 14 counter 3.
+
+  @param  ECX  MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 (0x00000ED3)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3 is defined as MSR_C14_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C14_PMON_EVNTSEL3         0x00000ED3
+
+
+/**
+  Package. Uncore C-box 14 perfmon box wide filter.
+
+  @param  ECX  MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER (0x00000ED4)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER is defined as MSR_C14_PMON_BOX_FILTER in SDM.
+**/
+#define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER       0x00000ED4
+
+
+/**
+  Package. Uncore C-box 14 perfmon counter 0.
+
+  @param  ECX  MSR_IVY_BRIDGE_C14_PMON_CTR0 (0x00000ED6)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR0);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C14_PMON_CTR0 is defined as MSR_C14_PMON_CTR0 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C14_PMON_CTR0             0x00000ED6
+
+
+/**
+  Package. Uncore C-box 14 perfmon counter 1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C14_PMON_CTR1 (0x00000ED7)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C14_PMON_CTR1 is defined as MSR_C14_PMON_CTR1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C14_PMON_CTR1             0x00000ED7
+
+
+/**
+  Package. Uncore C-box 14 perfmon counter 2.
+
+  @param  ECX  MSR_IVY_BRIDGE_C14_PMON_CTR2 (0x00000ED8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR2);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C14_PMON_CTR2 is defined as MSR_C14_PMON_CTR2 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C14_PMON_CTR2             0x00000ED8
+
+
+/**
+  Package. Uncore C-box 14 perfmon counter 3.
+
+  @param  ECX  MSR_IVY_BRIDGE_C14_PMON_CTR3 (0x00000ED9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR3);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C14_PMON_CTR3 is defined as MSR_C14_PMON_CTR3 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C14_PMON_CTR3             0x00000ED9
+
+
+/**
+  Package. Uncore C-box 14 perfmon box wide filter1.
+
+  @param  ECX  MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 (0x00000EDA)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1);
+  AsmWriteMsr64 (MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1, Msr);
+  @endcode
+  @note MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1 is defined as MSR_C14_PMON_BOX_FILTER1 in SDM.
+**/
+#define MSR_IVY_BRIDGE_C14_PMON_BOX_FILTER1      0x00000EDA
+
+#endif
diff --git a/MdePkg/Include/Register/Intel/Msr/NehalemMsr.h b/MdePkg/Include/Register/Intel/Msr/NehalemMsr.h
new file mode 100644
index 000000000000..74eef33449b6
--- /dev/null
+++ b/MdePkg/Include/Register/Intel/Msr/NehalemMsr.h
@@ -0,0 +1,7424 @@
+/** @file
+  MSR Definitions for Intel processors based on the Nehalem microarchitecture.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+  May 2018, Volume 4: Model-Specific-Registers (MSR)
+
+**/
+
+#ifndef __NEHALEM_MSR_H__
+#define __NEHALEM_MSR_H__
+
+#include <Register/Intel/ArchitecturalMsr.h>
+
+/**
+  Is Intel processors based on the Nehalem microarchitecture?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_NEHALEM_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (                        \
+    DisplayModel == 0x1A || \
+    DisplayModel == 0x1E || \
+    DisplayModel == 0x1F || \
+    DisplayModel == 0x2E    \
+    )                       \
+   )
+
+/**
+  Package. Model Specific Platform ID (R).
+
+  @param  ECX  MSR_NEHALEM_PLATFORM_ID (0x00000017)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_PLATFORM_ID_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_PLATFORM_ID_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_NEHALEM_PLATFORM_ID_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PLATFORM_ID);
+  @endcode
+  @note MSR_NEHALEM_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.
+**/
+#define MSR_NEHALEM_PLATFORM_ID                  0x00000017
+
+/**
+  MSR information returned for MSR index #MSR_NEHALEM_PLATFORM_ID
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:32;
+    UINT32  Reserved2:18;
+    ///
+    /// [Bits 52:50] See Table 2-2.
+    ///
+    UINT32  PlatformId:3;
+    UINT32  Reserved3:11;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_NEHALEM_PLATFORM_ID_REGISTER;
+
+
+/**
+  Thread. SMI Counter (R/O).
+
+  @param  ECX  MSR_NEHALEM_SMI_COUNT (0x00000034)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_SMI_COUNT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_SMI_COUNT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_NEHALEM_SMI_COUNT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_SMI_COUNT);
+  @endcode
+  @note MSR_NEHALEM_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.
+**/
+#define MSR_NEHALEM_SMI_COUNT                    0x00000034
+
+/**
+  MSR information returned for MSR index #MSR_NEHALEM_SMI_COUNT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 31:0] SMI Count (R/O)  Running count of SMI events since last
+    /// RESET.
+    ///
+    UINT32  SMICount:32;
+    UINT32  Reserved:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_NEHALEM_SMI_COUNT_REGISTER;
+
+
+/**
+  Package. see http://biosbits.org.
+
+  @param  ECX  MSR_NEHALEM_PLATFORM_INFO (0x000000CE)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_PLATFORM_INFO_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_PLATFORM_INFO_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_NEHALEM_PLATFORM_INFO_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PLATFORM_INFO);
+  AsmWriteMsr64 (MSR_NEHALEM_PLATFORM_INFO, Msr.Uint64);
+  @endcode
+  @note MSR_NEHALEM_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
+**/
+#define MSR_NEHALEM_PLATFORM_INFO                0x000000CE
+
+/**
+  MSR information returned for MSR index #MSR_NEHALEM_PLATFORM_INFO
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:8;
+    ///
+    /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O)  The is the ratio
+    /// of the frequency that invariant TSC runs at. The invariant TSC
+    /// frequency can be computed by multiplying this ratio by 133.33 MHz.
+    ///
+    UINT32  MaximumNonTurboRatio:8;
+    UINT32  Reserved2:12;
+    ///
+    /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O)  When
+    /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
+    /// enabled, and when set to 0, indicates Programmable Ratio Limits for
+    /// Turbo mode is disabled.
+    ///
+    UINT32  RatioLimit:1;
+    ///
+    /// [Bit 29] Package. Programmable TDC-TDP Limit for Turbo Mode (R/O)
+    /// When set to 1, indicates that TDC/TDP Limits for Turbo mode are
+    /// programmable, and when set to 0, indicates TDC and TDP Limits for
+    /// Turbo mode are not programmable.
+    ///
+    UINT32  TDC_TDPLimit:1;
+    UINT32  Reserved3:2;
+    UINT32  Reserved4:8;
+    ///
+    /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O)  The is the
+    /// minimum ratio (maximum efficiency) that the processor can operates, in
+    /// units of 133.33MHz.
+    ///
+    UINT32  MaximumEfficiencyRatio:8;
+    UINT32  Reserved5:16;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_NEHALEM_PLATFORM_INFO_REGISTER;
+
+
+/**
+  Core. C-State Configuration Control (R/W)  Note: C-state values are
+  processor specific C-state code names, unrelated to MWAIT extension C-state
+  parameters or ACPI CStates. See http://biosbits.org.
+
+  @param  ECX  MSR_NEHALEM_PKG_CST_CONFIG_CONTROL (0x000000E2)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PKG_CST_CONFIG_CONTROL);
+  AsmWriteMsr64 (MSR_NEHALEM_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
+  @endcode
+  @note MSR_NEHALEM_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
+**/
+#define MSR_NEHALEM_PKG_CST_CONFIG_CONTROL       0x000000E2
+
+/**
+  MSR information returned for MSR index #MSR_NEHALEM_PKG_CST_CONFIG_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 2:0] Package C-State Limit (R/W)  Specifies the lowest
+    /// processor-specific C-state code name (consuming the least power). for
+    /// the package. The default is set as factory-configured package C-state
+    /// limit. The following C-state code name encodings are supported: 000b:
+    /// C0 (no package C-sate support) 001b: C1 (Behavior is the same as 000b)
+    /// 010b: C3 011b: C6 100b: C7 101b and 110b: Reserved 111: No package
+    /// C-state limit. Note: This field cannot be used to limit package
+    /// C-state to C3.
+    ///
+    UINT32  Limit:3;
+    UINT32  Reserved1:7;
+    ///
+    /// [Bit 10] I/O MWAIT Redirection Enable (R/W)  When set, will map
+    /// IO_read instructions sent to IO register specified by
+    /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
+    ///
+    UINT32  IO_MWAIT:1;
+    UINT32  Reserved2:4;
+    ///
+    /// [Bit 15] CFG Lock (R/WO)  When set, lock bits 15:0 of this register
+    /// until next reset.
+    ///
+    UINT32  CFGLock:1;
+    UINT32  Reserved3:8;
+    ///
+    /// [Bit 24] Interrupt filtering enable (R/W)  When set, processor cores
+    /// in a deep C-State will wake only when the event message is destined
+    /// for that core. When 0, all processor cores in a deep C-State will wake
+    /// for an event message.
+    ///
+    UINT32  InterruptFiltering:1;
+    ///
+    /// [Bit 25] C3 state auto demotion enable (R/W)  When set, the processor
+    /// will conditionally demote C6/C7 requests to C3 based on uncore
+    /// auto-demote information.
+    ///
+    UINT32  C3AutoDemotion:1;
+    ///
+    /// [Bit 26] C1 state auto demotion enable (R/W)  When set, the processor
+    /// will conditionally demote C3/C6/C7 requests to C1 based on uncore
+    /// auto-demote information.
+    ///
+    UINT32  C1AutoDemotion:1;
+    ///
+    /// [Bit 27] Enable C3 Undemotion (R/W).
+    ///
+    UINT32  C3Undemotion:1;
+    ///
+    /// [Bit 28] Enable C1 Undemotion (R/W).
+    ///
+    UINT32  C1Undemotion:1;
+    ///
+    /// [Bit 29] Package C State Demotion Enable (R/W).
+    ///
+    UINT32  CStateDemotion:1;
+    ///
+    /// [Bit 30] Package C State UnDemotion Enable (R/W).
+    ///
+    UINT32  CStateUndemotion:1;
+    UINT32  Reserved4:1;
+    UINT32  Reserved5:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER;
+
+
+/**
+  Core. Power Management IO Redirection in C-state (R/W) See
+  http://biosbits.org.
+
+  @param  ECX  MSR_NEHALEM_PMG_IO_CAPTURE_BASE (0x000000E4)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PMG_IO_CAPTURE_BASE);
+  AsmWriteMsr64 (MSR_NEHALEM_PMG_IO_CAPTURE_BASE, Msr.Uint64);
+  @endcode
+  @note MSR_NEHALEM_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.
+**/
+#define MSR_NEHALEM_PMG_IO_CAPTURE_BASE          0x000000E4
+
+/**
+  MSR information returned for MSR index #MSR_NEHALEM_PMG_IO_CAPTURE_BASE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 15:0] LVL_2 Base Address (R/W)  Specifies the base address
+    /// visible to software for IO redirection. If IO MWAIT Redirection is
+    /// enabled, reads to this address will be consumed by the power
+    /// management logic and decoded to MWAIT instructions. When IO port
+    /// address redirection is enabled, this is the IO port address reported
+    /// to the OS/software.
+    ///
+    UINT32  Lvl2Base:16;
+    ///
+    /// [Bits 18:16] C-state Range (R/W)  Specifies the encoding value of the
+    /// maximum C-State code name to be included when IO read to MWAIT
+    /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 000b - C3
+    /// is the max C-State to include 001b - C6 is the max C-State to include
+    /// 010b - C7 is the max C-State to include.
+    ///
+    UINT32  CStateRange:3;
+    UINT32  Reserved1:13;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER;
+
+
+/**
+  Enable Misc. Processor Features (R/W)  Allows a variety of processor
+  functions to be enabled and disabled.
+
+  @param  ECX  MSR_NEHALEM_IA32_MISC_ENABLE (0x000001A0)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_IA32_MISC_ENABLE);
+  AsmWriteMsr64 (MSR_NEHALEM_IA32_MISC_ENABLE, Msr.Uint64);
+  @endcode
+  @note MSR_NEHALEM_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
+**/
+#define MSR_NEHALEM_IA32_MISC_ENABLE             0x000001A0
+
+/**
+  MSR information returned for MSR index #MSR_NEHALEM_IA32_MISC_ENABLE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Thread. Fast-Strings Enable See Table 2-2.
+    ///
+    UINT32  FastStrings:1;
+    UINT32  Reserved1:2;
+    ///
+    /// [Bit 3] Thread. Automatic Thermal Control Circuit Enable (R/W) See
+    /// Table 2-2. Default value is 1.
+    ///
+    UINT32  AutomaticThermalControlCircuit:1;
+    UINT32  Reserved2:3;
+    ///
+    /// [Bit 7] Thread. Performance Monitoring Available (R) See Table 2-2.
+    ///
+    UINT32  PerformanceMonitoring:1;
+    UINT32  Reserved3:3;
+    ///
+    /// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 2-2.
+    ///
+    UINT32  BTS:1;
+    ///
+    /// [Bit 12] Thread. Processor Event Based Sampling Unavailable (RO) See
+    /// Table 2-2.
+    ///
+    UINT32  PEBS:1;
+    UINT32  Reserved4:3;
+    ///
+    /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See
+    /// Table 2-2.
+    ///
+    UINT32  EIST:1;
+    UINT32  Reserved5:1;
+    ///
+    /// [Bit 18] Thread. ENABLE MONITOR FSM. (R/W) See Table 2-2.
+    ///
+    UINT32  MONITOR:1;
+    UINT32  Reserved6:3;
+    ///
+    /// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 2-2.
+    ///
+    UINT32  LimitCpuidMaxval:1;
+    ///
+    /// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 2-2.
+    ///
+    UINT32  xTPR_Message_Disable:1;
+    UINT32  Reserved7:8;
+    UINT32  Reserved8:2;
+    ///
+    /// [Bit 34] Thread. XD Bit Disable (R/W) See Table 2-2.
+    ///
+    UINT32  XD:1;
+    UINT32  Reserved9:3;
+    ///
+    /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors
+    /// that support Intel Turbo Boost Technology, the turbo mode feature is
+    /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:
+    /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:
+    /// EAX[1] reports the processor's support of turbo mode is enabled. Note:
+    /// the power-on default value is used by BIOS to detect hardware support
+    /// of turbo mode. If power-on default value is 1, turbo mode is available
+    /// in the processor. If power-on default value is 0, turbo mode is not
+    /// available.
+    ///
+    UINT32  TurboModeDisable:1;
+    UINT32  Reserved10:25;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER;
+
+
+/**
+  Thread.
+
+  @param  ECX  MSR_NEHALEM_TEMPERATURE_TARGET (0x000001A2)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TEMPERATURE_TARGET);
+  AsmWriteMsr64 (MSR_NEHALEM_TEMPERATURE_TARGET, Msr.Uint64);
+  @endcode
+  @note MSR_NEHALEM_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
+**/
+#define MSR_NEHALEM_TEMPERATURE_TARGET           0x000001A2
+
+/**
+  MSR information returned for MSR index #MSR_NEHALEM_TEMPERATURE_TARGET
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:16;
+    ///
+    /// [Bits 23:16] Temperature Target (R)  The minimum temperature at which
+    /// PROCHOT# will be asserted. The value is degree C.
+    ///
+    UINT32  TemperatureTarget:8;
+    UINT32  Reserved2:8;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER;
+
+
+/**
+  Miscellaneous Feature Control (R/W).
+
+  @param  ECX  MSR_NEHALEM_MISC_FEATURE_CONTROL (0x000001A4)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_MISC_FEATURE_CONTROL);
+  AsmWriteMsr64 (MSR_NEHALEM_MISC_FEATURE_CONTROL, Msr.Uint64);
+  @endcode
+  @note MSR_NEHALEM_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.
+**/
+#define MSR_NEHALEM_MISC_FEATURE_CONTROL         0x000001A4
+
+/**
+  MSR information returned for MSR index #MSR_NEHALEM_MISC_FEATURE_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W)  If 1, disables the
+    /// L2 hardware prefetcher, which fetches additional lines of code or data
+    /// into the L2 cache.
+    ///
+    UINT32  L2HardwarePrefetcherDisable:1;
+    ///
+    /// [Bit 1] Core. L2 Adjacent Cache Line Prefetcher Disable (R/W)  If 1,
+    /// disables the adjacent cache line prefetcher, which fetches the cache
+    /// line that comprises a cache line pair (128 bytes).
+    ///
+    UINT32  L2AdjacentCacheLinePrefetcherDisable:1;
+    ///
+    /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W)  If 1, disables
+    /// the L1 data cache prefetcher, which fetches the next cache line into
+    /// L1 data cache.
+    ///
+    UINT32  DCUHardwarePrefetcherDisable:1;
+    ///
+    /// [Bit 3] Core. DCU IP Prefetcher Disable (R/W)  If 1, disables the L1
+    /// data cache IP prefetcher, which uses sequential load history (based on
+    /// instruction Pointer of previous loads) to determine whether to
+    /// prefetch additional lines.
+    ///
+    UINT32  DCUIPPrefetcherDisable:1;
+    UINT32  Reserved1:28;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER;
+
+
+/**
+  Thread. Offcore Response Event Select Register (R/W).
+
+  @param  ECX  MSR_NEHALEM_OFFCORE_RSP_0 (0x000001A6)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_OFFCORE_RSP_0);
+  AsmWriteMsr64 (MSR_NEHALEM_OFFCORE_RSP_0, Msr);
+  @endcode
+  @note MSR_NEHALEM_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.
+**/
+#define MSR_NEHALEM_OFFCORE_RSP_0                0x000001A6
+
+
+/**
+  See http://biosbits.org.
+
+  @param  ECX  MSR_NEHALEM_MISC_PWR_MGMT (0x000001AA)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_MISC_PWR_MGMT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_MISC_PWR_MGMT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_NEHALEM_MISC_PWR_MGMT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_MISC_PWR_MGMT);
+  AsmWriteMsr64 (MSR_NEHALEM_MISC_PWR_MGMT, Msr.Uint64);
+  @endcode
+  @note MSR_NEHALEM_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM.
+**/
+#define MSR_NEHALEM_MISC_PWR_MGMT                0x000001AA
+
+/**
+  MSR information returned for MSR index #MSR_NEHALEM_MISC_PWR_MGMT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Package. EIST Hardware Coordination Disable (R/W) When 0,
+    /// enables hardware coordination of Enhanced Intel Speedstep Technology
+    /// request from processor cores; When 1, disables hardware coordination
+    /// of Enhanced Intel Speedstep Technology requests.
+    ///
+    UINT32  EISTHardwareCoordinationDisable:1;
+    ///
+    /// [Bit 1] Thread. Energy/Performance Bias Enable (R/W)  This bit makes
+    /// the IA32_ENERGY_PERF_BIAS register (MSR 1B0h) visible to software with
+    /// Ring 0 privileges. This bit's status (1 or 0) is also reflected by
+    /// CPUID.(EAX=06h):ECX[3].
+    ///
+    UINT32  EnergyPerformanceBiasEnable:1;
+    UINT32  Reserved1:30;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_NEHALEM_MISC_PWR_MGMT_REGISTER;
+
+
+/**
+  See http://biosbits.org.
+
+  @param  ECX  MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT (0x000001AC)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT);
+  AsmWriteMsr64 (MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT, Msr.Uint64);
+  @endcode
+  @note MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT is defined as MSR_TURBO_POWER_CURRENT_LIMIT in SDM.
+**/
+#define MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT    0x000001AC
+
+/**
+  MSR information returned for MSR index #MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 14:0] Package. TDP Limit (R/W)  TDP limit in 1/8 Watt
+    /// granularity.
+    ///
+    UINT32  TDPLimit:15;
+    ///
+    /// [Bit 15] Package. TDP Limit Override Enable (R/W)  A value = 0
+    /// indicates override is not active, and a value = 1 indicates active.
+    ///
+    UINT32  TDPLimitOverrideEnable:1;
+    ///
+    /// [Bits 30:16] Package. TDC Limit (R/W)  TDC limit in 1/8 Amp
+    /// granularity.
+    ///
+    UINT32  TDCLimit:15;
+    ///
+    /// [Bit 31] Package. TDC Limit Override Enable (R/W)  A value = 0
+    /// indicates override is not active, and a value = 1 indicates active.
+    ///
+    UINT32  TDCLimitOverrideEnable:1;
+    UINT32  Reserved:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER;
+
+
+/**
+  Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
+  RW if MSR_PLATFORM_INFO.[28] = 1.
+
+  @param  ECX  MSR_NEHALEM_TURBO_RATIO_LIMIT (0x000001AD)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TURBO_RATIO_LIMIT);
+  @endcode
+  @note MSR_NEHALEM_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
+**/
+#define MSR_NEHALEM_TURBO_RATIO_LIMIT            0x000001AD
+
+/**
+  MSR information returned for MSR index #MSR_NEHALEM_TURBO_RATIO_LIMIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
+    /// limit of 1 core active.
+    ///
+    UINT32  Maximum1C:8;
+    ///
+    /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
+    /// limit of 2 core active.
+    ///
+    UINT32  Maximum2C:8;
+    ///
+    /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
+    /// limit of 3 core active.
+    ///
+    UINT32  Maximum3C:8;
+    ///
+    /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
+    /// limit of 4 core active.
+    ///
+    UINT32  Maximum4C:8;
+    UINT32  Reserved:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER;
+
+
+/**
+  Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2,
+  "Filtering of Last Branch Records.".
+
+  @param  ECX  MSR_NEHALEM_LBR_SELECT (0x000001C8)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_LBR_SELECT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_LBR_SELECT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_NEHALEM_LBR_SELECT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_LBR_SELECT);
+  AsmWriteMsr64 (MSR_NEHALEM_LBR_SELECT, Msr.Uint64);
+  @endcode
+  @note MSR_NEHALEM_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
+**/
+#define MSR_NEHALEM_LBR_SELECT                   0x000001C8
+
+/**
+  MSR information returned for MSR index #MSR_NEHALEM_LBR_SELECT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] CPL_EQ_0.
+    ///
+    UINT32  CPL_EQ_0:1;
+    ///
+    /// [Bit 1] CPL_NEQ_0.
+    ///
+    UINT32  CPL_NEQ_0:1;
+    ///
+    /// [Bit 2] JCC.
+    ///
+    UINT32  JCC:1;
+    ///
+    /// [Bit 3] NEAR_REL_CALL.
+    ///
+    UINT32  NEAR_REL_CALL:1;
+    ///
+    /// [Bit 4] NEAR_IND_CALL.
+    ///
+    UINT32  NEAR_IND_CALL:1;
+    ///
+    /// [Bit 5] NEAR_RET.
+    ///
+    UINT32  NEAR_RET:1;
+    ///
+    /// [Bit 6] NEAR_IND_JMP.
+    ///
+    UINT32  NEAR_IND_JMP:1;
+    ///
+    /// [Bit 7] NEAR_REL_JMP.
+    ///
+    UINT32  NEAR_REL_JMP:1;
+    ///
+    /// [Bit 8] FAR_BRANCH.
+    ///
+    UINT32  FAR_BRANCH:1;
+    UINT32  Reserved1:23;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_NEHALEM_LBR_SELECT_REGISTER;
+
+
+/**
+  Thread. Last Branch Record Stack TOS (R/W)  Contains an index (bits 0-3)
+  that points to the MSR containing the most recent branch record. See
+  MSR_LASTBRANCH_0_FROM_IP (at 680H).
+
+  @param  ECX  MSR_NEHALEM_LASTBRANCH_TOS (0x000001C9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_TOS);
+  AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_TOS, Msr);
+  @endcode
+  @note MSR_NEHALEM_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
+**/
+#define MSR_NEHALEM_LASTBRANCH_TOS               0x000001C9
+
+
+/**
+  Thread. Last Exception Record From Linear IP (R)  Contains a pointer to the
+  last branch instruction that the processor executed prior to the last
+  exception that was generated or the last interrupt that was handled.
+
+  @param  ECX  MSR_NEHALEM_LER_FROM_LIP (0x000001DD)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_LER_FROM_LIP);
+  @endcode
+  @note MSR_NEHALEM_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
+**/
+#define MSR_NEHALEM_LER_FROM_LIP                 0x000001DD
+
+
+/**
+  Thread. Last Exception Record To Linear IP (R)  This area contains a pointer
+  to the target of the last branch instruction that the processor executed
+  prior to the last exception that was generated or the last interrupt that
+  was handled.
+
+  @param  ECX  MSR_NEHALEM_LER_TO_LIP (0x000001DE)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_LER_TO_LIP);
+  @endcode
+  @note MSR_NEHALEM_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
+**/
+#define MSR_NEHALEM_LER_TO_LIP                   0x000001DE
+
+
+/**
+  Core. Power Control Register. See http://biosbits.org.
+
+  @param  ECX  MSR_NEHALEM_POWER_CTL (0x000001FC)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_POWER_CTL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_POWER_CTL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_NEHALEM_POWER_CTL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_POWER_CTL);
+  AsmWriteMsr64 (MSR_NEHALEM_POWER_CTL, Msr.Uint64);
+  @endcode
+  @note MSR_NEHALEM_POWER_CTL is defined as MSR_POWER_CTL in SDM.
+**/
+#define MSR_NEHALEM_POWER_CTL                    0x000001FC
+
+/**
+  MSR information returned for MSR index #MSR_NEHALEM_POWER_CTL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 1] Package. C1E Enable (R/W)  When set to '1', will enable the
+    /// CPU to switch to the Minimum Enhanced Intel SpeedStep Technology
+    /// operating point when all execution cores enter MWAIT (C1).
+    ///
+    UINT32  C1EEnable:1;
+    UINT32  Reserved2:30;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_NEHALEM_POWER_CTL_REGISTER;
+
+
+/**
+  Thread. (RO).
+
+  @param  ECX  MSR_NEHALEM_PERF_GLOBAL_STATUS (0x0000038E)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PERF_GLOBAL_STATUS);
+  @endcode
+  @note MSR_NEHALEM_PERF_GLOBAL_STATUS is defined as MSR_PERF_GLOBAL_STATUS in SDM.
+**/
+#define MSR_NEHALEM_PERF_GLOBAL_STATUS           0x0000038E
+
+/**
+  MSR information returned for MSR index #MSR_NEHALEM_PERF_GLOBAL_STATUS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:32;
+    UINT32  Reserved2:29;
+    ///
+    /// [Bit 61] UNC_Ovf Uncore overflowed if 1.
+    ///
+    UINT32  Ovf_Uncore:1;
+    UINT32  Reserved3:2;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER;
+
+
+/**
+  Thread. (R/W).
+
+  @param  ECX  MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL (0x00000390)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL);
+  AsmWriteMsr64 (MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);
+  @endcode
+  @note MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL is defined as MSR_PERF_GLOBAL_OVF_CTRL in SDM.
+**/
+#define MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL         0x00000390
+
+/**
+  MSR information returned for MSR index #MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:32;
+    UINT32  Reserved2:29;
+    ///
+    /// [Bit 61] CLR_UNC_Ovf Set 1 to clear UNC_Ovf.
+    ///
+    UINT32  Ovf_Uncore:1;
+    UINT32  Reserved3:2;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER;
+
+
+/**
+  Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).".
+
+  @param  ECX  MSR_NEHALEM_PEBS_ENABLE (0x000003F1)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_PEBS_ENABLE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_PEBS_ENABLE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_NEHALEM_PEBS_ENABLE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PEBS_ENABLE);
+  AsmWriteMsr64 (MSR_NEHALEM_PEBS_ENABLE, Msr.Uint64);
+  @endcode
+  @note MSR_NEHALEM_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
+**/
+#define MSR_NEHALEM_PEBS_ENABLE                  0x000003F1
+
+/**
+  MSR information returned for MSR index #MSR_NEHALEM_PEBS_ENABLE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
+    ///
+    UINT32  PEBS_EN_PMC0:1;
+    ///
+    /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).
+    ///
+    UINT32  PEBS_EN_PMC1:1;
+    ///
+    /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).
+    ///
+    UINT32  PEBS_EN_PMC2:1;
+    ///
+    /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).
+    ///
+    UINT32  PEBS_EN_PMC3:1;
+    UINT32  Reserved1:28;
+    ///
+    /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).
+    ///
+    UINT32  LL_EN_PMC0:1;
+    ///
+    /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).
+    ///
+    UINT32  LL_EN_PMC1:1;
+    ///
+    /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).
+    ///
+    UINT32  LL_EN_PMC2:1;
+    ///
+    /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).
+    ///
+    UINT32  LL_EN_PMC3:1;
+    UINT32  Reserved2:28;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_NEHALEM_PEBS_ENABLE_REGISTER;
+
+
+/**
+  Thread. See Section 18.3.1.1.2, "Load Latency Performance Monitoring
+  Facility.".
+
+  @param  ECX  MSR_NEHALEM_PEBS_LD_LAT (0x000003F6)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_PEBS_LD_LAT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_PEBS_LD_LAT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_NEHALEM_PEBS_LD_LAT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PEBS_LD_LAT);
+  AsmWriteMsr64 (MSR_NEHALEM_PEBS_LD_LAT, Msr.Uint64);
+  @endcode
+  @note MSR_NEHALEM_PEBS_LD_LAT is defined as MSR_PEBS_LD_LAT in SDM.
+**/
+#define MSR_NEHALEM_PEBS_LD_LAT                  0x000003F6
+
+/**
+  MSR information returned for MSR index #MSR_NEHALEM_PEBS_LD_LAT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 15:0] Minimum threshold latency value of tagged load operation
+    /// that will be counted. (R/W).
+    ///
+    UINT32  MinimumThreshold:16;
+    UINT32  Reserved1:16;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_NEHALEM_PEBS_LD_LAT_REGISTER;
+
+
+/**
+  Package. Note: C-state values are processor specific C-state code names,
+  unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3
+  Residency Counter. (R/O) Value since last reset that this package is in
+  processor-specific C3 states. Count at the same frequency as the TSC.
+
+  @param  ECX  MSR_NEHALEM_PKG_C3_RESIDENCY (0x000003F8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C3_RESIDENCY);
+  AsmWriteMsr64 (MSR_NEHALEM_PKG_C3_RESIDENCY, Msr);
+  @endcode
+  @note MSR_NEHALEM_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.
+**/
+#define MSR_NEHALEM_PKG_C3_RESIDENCY             0x000003F8
+
+
+/**
+  Package. Note: C-state values are processor specific C-state code names,
+  unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6
+  Residency Counter. (R/O) Value since last reset that this package is in
+  processor-specific C6 states. Count at the same frequency as the TSC.
+
+  @param  ECX  MSR_NEHALEM_PKG_C6_RESIDENCY (0x000003F9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C6_RESIDENCY);
+  AsmWriteMsr64 (MSR_NEHALEM_PKG_C6_RESIDENCY, Msr);
+  @endcode
+  @note MSR_NEHALEM_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
+**/
+#define MSR_NEHALEM_PKG_C6_RESIDENCY             0x000003F9
+
+
+/**
+  Package. Note: C-state values are processor specific C-state code names,
+  unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C7
+  Residency Counter. (R/O) Value since last reset that this package is in
+  processor-specific C7 states. Count at the same frequency as the TSC.
+
+  @param  ECX  MSR_NEHALEM_PKG_C7_RESIDENCY (0x000003FA)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C7_RESIDENCY);
+  AsmWriteMsr64 (MSR_NEHALEM_PKG_C7_RESIDENCY, Msr);
+  @endcode
+  @note MSR_NEHALEM_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.
+**/
+#define MSR_NEHALEM_PKG_C7_RESIDENCY             0x000003FA
+
+
+/**
+  Core. Note: C-state values are processor specific C-state code names,
+  unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3
+  Residency Counter. (R/O) Value since last reset that this core is in
+  processor-specific C3 states. Count at the same frequency as the TSC.
+
+  @param  ECX  MSR_NEHALEM_CORE_C3_RESIDENCY (0x000003FC)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_CORE_C3_RESIDENCY);
+  AsmWriteMsr64 (MSR_NEHALEM_CORE_C3_RESIDENCY, Msr);
+  @endcode
+  @note MSR_NEHALEM_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM.
+**/
+#define MSR_NEHALEM_CORE_C3_RESIDENCY            0x000003FC
+
+
+/**
+  Core. Note: C-state values are processor specific C-state code names,
+  unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6
+  Residency Counter. (R/O) Value since last reset that this core is in
+  processor-specific C6 states. Count at the same frequency as the TSC.
+
+  @param  ECX  MSR_NEHALEM_CORE_C6_RESIDENCY (0x000003FD)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_CORE_C6_RESIDENCY);
+  AsmWriteMsr64 (MSR_NEHALEM_CORE_C6_RESIDENCY, Msr);
+  @endcode
+  @note MSR_NEHALEM_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.
+**/
+#define MSR_NEHALEM_CORE_C6_RESIDENCY            0x000003FD
+
+
+/**
+  Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last
+  branch record registers on the last branch record stack. The From_IP part of
+  the stack contains pointers to the source instruction. See also: -  Last
+  Branch Record Stack TOS at 1C9H -  Section 17.7.1 and record format in
+  Section 17.4.8.1.
+
+  @param  ECX  MSR_NEHALEM_LASTBRANCH_n_FROM_IP
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP);
+  AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP, Msr);
+  @endcode
+  @note MSR_NEHALEM_LASTBRANCH_0_FROM_IP  is defined as MSR_LASTBRANCH_0_FROM_IP  in SDM.
+        MSR_NEHALEM_LASTBRANCH_1_FROM_IP  is defined as MSR_LASTBRANCH_1_FROM_IP  in SDM.
+        MSR_NEHALEM_LASTBRANCH_2_FROM_IP  is defined as MSR_LASTBRANCH_2_FROM_IP  in SDM.
+        MSR_NEHALEM_LASTBRANCH_3_FROM_IP  is defined as MSR_LASTBRANCH_3_FROM_IP  in SDM.
+        MSR_NEHALEM_LASTBRANCH_4_FROM_IP  is defined as MSR_LASTBRANCH_4_FROM_IP  in SDM.
+        MSR_NEHALEM_LASTBRANCH_5_FROM_IP  is defined as MSR_LASTBRANCH_5_FROM_IP  in SDM.
+        MSR_NEHALEM_LASTBRANCH_6_FROM_IP  is defined as MSR_LASTBRANCH_6_FROM_IP  in SDM.
+        MSR_NEHALEM_LASTBRANCH_7_FROM_IP  is defined as MSR_LASTBRANCH_7_FROM_IP  in SDM.
+        MSR_NEHALEM_LASTBRANCH_8_FROM_IP  is defined as MSR_LASTBRANCH_8_FROM_IP  in SDM.
+        MSR_NEHALEM_LASTBRANCH_9_FROM_IP  is defined as MSR_LASTBRANCH_9_FROM_IP  in SDM.
+        MSR_NEHALEM_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM.
+        MSR_NEHALEM_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM.
+        MSR_NEHALEM_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM.
+        MSR_NEHALEM_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM.
+        MSR_NEHALEM_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM.
+        MSR_NEHALEM_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.
+  @{
+**/
+#define MSR_NEHALEM_LASTBRANCH_0_FROM_IP         0x00000680
+#define MSR_NEHALEM_LASTBRANCH_1_FROM_IP         0x00000681
+#define MSR_NEHALEM_LASTBRANCH_2_FROM_IP         0x00000682
+#define MSR_NEHALEM_LASTBRANCH_3_FROM_IP         0x00000683
+#define MSR_NEHALEM_LASTBRANCH_4_FROM_IP         0x00000684
+#define MSR_NEHALEM_LASTBRANCH_5_FROM_IP         0x00000685
+#define MSR_NEHALEM_LASTBRANCH_6_FROM_IP         0x00000686
+#define MSR_NEHALEM_LASTBRANCH_7_FROM_IP         0x00000687
+#define MSR_NEHALEM_LASTBRANCH_8_FROM_IP         0x00000688
+#define MSR_NEHALEM_LASTBRANCH_9_FROM_IP         0x00000689
+#define MSR_NEHALEM_LASTBRANCH_10_FROM_IP        0x0000068A
+#define MSR_NEHALEM_LASTBRANCH_11_FROM_IP        0x0000068B
+#define MSR_NEHALEM_LASTBRANCH_12_FROM_IP        0x0000068C
+#define MSR_NEHALEM_LASTBRANCH_13_FROM_IP        0x0000068D
+#define MSR_NEHALEM_LASTBRANCH_14_FROM_IP        0x0000068E
+#define MSR_NEHALEM_LASTBRANCH_15_FROM_IP        0x0000068F
+/// @}
+
+
+/**
+  Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch
+  record registers on the last branch record stack. This part of the stack
+  contains pointers to the destination instruction.
+
+  @param  ECX  MSR_NEHALEM_LASTBRANCH_n_TO_IP
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP);
+  AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP, Msr);
+  @endcode
+  @note MSR_NEHALEM_LASTBRANCH_0_TO_IP  is defined as MSR_LASTBRANCH_0_TO_IP  in SDM.
+        MSR_NEHALEM_LASTBRANCH_1_TO_IP  is defined as MSR_LASTBRANCH_1_TO_IP  in SDM.
+        MSR_NEHALEM_LASTBRANCH_2_TO_IP  is defined as MSR_LASTBRANCH_2_TO_IP  in SDM.
+        MSR_NEHALEM_LASTBRANCH_3_TO_IP  is defined as MSR_LASTBRANCH_3_TO_IP  in SDM.
+        MSR_NEHALEM_LASTBRANCH_4_TO_IP  is defined as MSR_LASTBRANCH_4_TO_IP  in SDM.
+        MSR_NEHALEM_LASTBRANCH_5_TO_IP  is defined as MSR_LASTBRANCH_5_TO_IP  in SDM.
+        MSR_NEHALEM_LASTBRANCH_6_TO_IP  is defined as MSR_LASTBRANCH_6_TO_IP  in SDM.
+        MSR_NEHALEM_LASTBRANCH_7_TO_IP  is defined as MSR_LASTBRANCH_7_TO_IP  in SDM.
+        MSR_NEHALEM_LASTBRANCH_8_TO_IP  is defined as MSR_LASTBRANCH_8_TO_IP  in SDM.
+        MSR_NEHALEM_LASTBRANCH_9_TO_IP  is defined as MSR_LASTBRANCH_9_TO_IP  in SDM.
+        MSR_NEHALEM_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM.
+        MSR_NEHALEM_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM.
+        MSR_NEHALEM_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM.
+        MSR_NEHALEM_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM.
+        MSR_NEHALEM_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM.
+        MSR_NEHALEM_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.
+  @{
+**/
+#define MSR_NEHALEM_LASTBRANCH_0_TO_IP           0x000006C0
+#define MSR_NEHALEM_LASTBRANCH_1_TO_IP           0x000006C1
+#define MSR_NEHALEM_LASTBRANCH_2_TO_IP           0x000006C2
+#define MSR_NEHALEM_LASTBRANCH_3_TO_IP           0x000006C3
+#define MSR_NEHALEM_LASTBRANCH_4_TO_IP           0x000006C4
+#define MSR_NEHALEM_LASTBRANCH_5_TO_IP           0x000006C5
+#define MSR_NEHALEM_LASTBRANCH_6_TO_IP           0x000006C6
+#define MSR_NEHALEM_LASTBRANCH_7_TO_IP           0x000006C7
+#define MSR_NEHALEM_LASTBRANCH_8_TO_IP           0x000006C8
+#define MSR_NEHALEM_LASTBRANCH_9_TO_IP           0x000006C9
+#define MSR_NEHALEM_LASTBRANCH_10_TO_IP          0x000006CA
+#define MSR_NEHALEM_LASTBRANCH_11_TO_IP          0x000006CB
+#define MSR_NEHALEM_LASTBRANCH_12_TO_IP          0x000006CC
+#define MSR_NEHALEM_LASTBRANCH_13_TO_IP          0x000006CD
+#define MSR_NEHALEM_LASTBRANCH_14_TO_IP          0x000006CE
+#define MSR_NEHALEM_LASTBRANCH_15_TO_IP          0x000006CF
+/// @}
+
+
+/**
+  Package.
+
+  @param  ECX  MSR_NEHALEM_GQ_SNOOP_MESF (0x00000301)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_GQ_SNOOP_MESF);
+  AsmWriteMsr64 (MSR_NEHALEM_GQ_SNOOP_MESF, Msr.Uint64);
+  @endcode
+  @note MSR_NEHALEM_GQ_SNOOP_MESF is defined as MSR_GQ_SNOOP_MESF in SDM.
+**/
+#define MSR_NEHALEM_GQ_SNOOP_MESF                0x00000301
+
+/**
+  MSR information returned for MSR index #MSR_NEHALEM_GQ_SNOOP_MESF
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] From M to S (R/W).
+    ///
+    UINT32  FromMtoS:1;
+    ///
+    /// [Bit 1] From E to S (R/W).
+    ///
+    UINT32  FromEtoS:1;
+    ///
+    /// [Bit 2] From S to S (R/W).
+    ///
+    UINT32  FromStoS:1;
+    ///
+    /// [Bit 3] From F to S (R/W).
+    ///
+    UINT32  FromFtoS:1;
+    ///
+    /// [Bit 4] From M to I (R/W).
+    ///
+    UINT32  FromMtoI:1;
+    ///
+    /// [Bit 5] From E to I (R/W).
+    ///
+    UINT32  FromEtoI:1;
+    ///
+    /// [Bit 6] From S to I (R/W).
+    ///
+    UINT32  FromStoI:1;
+    ///
+    /// [Bit 7] From F to I (R/W).
+    ///
+    UINT32  FromFtoI:1;
+    UINT32  Reserved1:24;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER;
+
+
+/**
+  Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management
+  Facility.".
+
+  @param  ECX  MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL (0x00000391)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL);
+  AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL, Msr);
+  @endcode
+  @note MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL is defined as MSR_UNCORE_PERF_GLOBAL_CTRL in SDM.
+**/
+#define MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL      0x00000391
+
+
+/**
+  Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management
+  Facility.".
+
+  @param  ECX  MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS (0x00000392)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS);
+  AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS, Msr);
+  @endcode
+  @note MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS is defined as MSR_UNCORE_PERF_GLOBAL_STATUS in SDM.
+**/
+#define MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS    0x00000392
+
+
+/**
+  Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management
+  Facility.".
+
+  @param  ECX  MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL (0x00000393)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL);
+  AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL, Msr);
+  @endcode
+  @note MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL is defined as MSR_UNCORE_PERF_GLOBAL_OVF_CTRL in SDM.
+**/
+#define MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL  0x00000393
+
+
+/**
+  Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management
+  Facility.".
+
+  @param  ECX  MSR_NEHALEM_UNCORE_FIXED_CTR0 (0x00000394)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR0);
+  AsmWriteMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR0, Msr);
+  @endcode
+  @note MSR_NEHALEM_UNCORE_FIXED_CTR0 is defined as MSR_UNCORE_FIXED_CTR0 in SDM.
+**/
+#define MSR_NEHALEM_UNCORE_FIXED_CTR0            0x00000394
+
+
+/**
+  Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management
+  Facility.".
+
+  @param  ECX  MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL (0x00000395)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL);
+  AsmWriteMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL, Msr);
+  @endcode
+  @note MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL is defined as MSR_UNCORE_FIXED_CTR_CTRL in SDM.
+**/
+#define MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL        0x00000395
+
+
+/**
+  Package. See Section 18.3.1.2.3, "Uncore Address/Opcode Match MSR.".
+
+  @param  ECX  MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH (0x00000396)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH);
+  AsmWriteMsr64 (MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH, Msr);
+  @endcode
+  @note MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH is defined as MSR_UNCORE_ADDR_OPCODE_MATCH in SDM.
+**/
+#define MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH     0x00000396
+
+
+/**
+  Package. See Section 18.3.1.2.2, "Uncore Performance Event Configuration
+  Facility.".
+
+  @param  ECX  MSR_NEHALEM_UNCORE_PMCi
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PMC0);
+  AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PMC0, Msr);
+  @endcode
+  @note MSR_NEHALEM_UNCORE_PMC0 is defined as MSR_UNCORE_PMC0 in SDM.
+        MSR_NEHALEM_UNCORE_PMC1 is defined as MSR_UNCORE_PMC1 in SDM.
+        MSR_NEHALEM_UNCORE_PMC2 is defined as MSR_UNCORE_PMC2 in SDM.
+        MSR_NEHALEM_UNCORE_PMC3 is defined as MSR_UNCORE_PMC3 in SDM.
+        MSR_NEHALEM_UNCORE_PMC4 is defined as MSR_UNCORE_PMC4 in SDM.
+        MSR_NEHALEM_UNCORE_PMC5 is defined as MSR_UNCORE_PMC5 in SDM.
+        MSR_NEHALEM_UNCORE_PMC6 is defined as MSR_UNCORE_PMC6 in SDM.
+        MSR_NEHALEM_UNCORE_PMC7 is defined as MSR_UNCORE_PMC7 in SDM.
+  @{
+**/
+#define MSR_NEHALEM_UNCORE_PMC0                  0x000003B0
+#define MSR_NEHALEM_UNCORE_PMC1                  0x000003B1
+#define MSR_NEHALEM_UNCORE_PMC2                  0x000003B2
+#define MSR_NEHALEM_UNCORE_PMC3                  0x000003B3
+#define MSR_NEHALEM_UNCORE_PMC4                  0x000003B4
+#define MSR_NEHALEM_UNCORE_PMC5                  0x000003B5
+#define MSR_NEHALEM_UNCORE_PMC6                  0x000003B6
+#define MSR_NEHALEM_UNCORE_PMC7                  0x000003B7
+/// @}
+
+/**
+  Package. See Section 18.3.1.2.2, "Uncore Performance Event Configuration
+  Facility.".
+
+  @param  ECX  MSR_NEHALEM_UNCORE_PERFEVTSELi
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0);
+  AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0, Msr);
+  @endcode
+  @note MSR_NEHALEM_UNCORE_PERFEVTSEL0 is defined as MSR_UNCORE_PERFEVTSEL0 in SDM.
+        MSR_NEHALEM_UNCORE_PERFEVTSEL1 is defined as MSR_UNCORE_PERFEVTSEL1 in SDM.
+        MSR_NEHALEM_UNCORE_PERFEVTSEL2 is defined as MSR_UNCORE_PERFEVTSEL2 in SDM.
+        MSR_NEHALEM_UNCORE_PERFEVTSEL3 is defined as MSR_UNCORE_PERFEVTSEL3 in SDM.
+        MSR_NEHALEM_UNCORE_PERFEVTSEL4 is defined as MSR_UNCORE_PERFEVTSEL4 in SDM.
+        MSR_NEHALEM_UNCORE_PERFEVTSEL5 is defined as MSR_UNCORE_PERFEVTSEL5 in SDM.
+        MSR_NEHALEM_UNCORE_PERFEVTSEL6 is defined as MSR_UNCORE_PERFEVTSEL6 in SDM.
+        MSR_NEHALEM_UNCORE_PERFEVTSEL7 is defined as MSR_UNCORE_PERFEVTSEL7 in SDM.
+  @{
+**/
+#define MSR_NEHALEM_UNCORE_PERFEVTSEL0           0x000003C0
+#define MSR_NEHALEM_UNCORE_PERFEVTSEL1           0x000003C1
+#define MSR_NEHALEM_UNCORE_PERFEVTSEL2           0x000003C2
+#define MSR_NEHALEM_UNCORE_PERFEVTSEL3           0x000003C3
+#define MSR_NEHALEM_UNCORE_PERFEVTSEL4           0x000003C4
+#define MSR_NEHALEM_UNCORE_PERFEVTSEL5           0x000003C5
+#define MSR_NEHALEM_UNCORE_PERFEVTSEL6           0x000003C6
+#define MSR_NEHALEM_UNCORE_PERFEVTSEL7           0x000003C7
+/// @}
+
+
+/**
+  Package. Uncore W-box perfmon fixed counter.
+
+  @param  ECX  MSR_NEHALEM_W_PMON_FIXED_CTR (0x00000394)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR);
+  AsmWriteMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR, Msr);
+  @endcode
+  @note MSR_NEHALEM_W_PMON_FIXED_CTR is defined as MSR_W_PMON_FIXED_CTR in SDM.
+**/
+#define MSR_NEHALEM_W_PMON_FIXED_CTR             0x00000394
+
+
+/**
+  Package. Uncore U-box perfmon fixed counter control MSR.
+
+  @param  ECX  MSR_NEHALEM_W_PMON_FIXED_CTR_CTL (0x00000395)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR_CTL);
+  AsmWriteMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR_CTL, Msr);
+  @endcode
+  @note MSR_NEHALEM_W_PMON_FIXED_CTR_CTL is defined as MSR_W_PMON_FIXED_CTR_CTL in SDM.
+**/
+#define MSR_NEHALEM_W_PMON_FIXED_CTR_CTL         0x00000395
+
+
+/**
+  Package. Uncore U-box perfmon global control MSR.
+
+  @param  ECX  MSR_NEHALEM_U_PMON_GLOBAL_CTRL (0x00000C00)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_CTRL);
+  AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_CTRL, Msr);
+  @endcode
+  @note MSR_NEHALEM_U_PMON_GLOBAL_CTRL is defined as MSR_U_PMON_GLOBAL_CTRL in SDM.
+**/
+#define MSR_NEHALEM_U_PMON_GLOBAL_CTRL           0x00000C00
+
+
+/**
+  Package. Uncore U-box perfmon global status MSR.
+
+  @param  ECX  MSR_NEHALEM_U_PMON_GLOBAL_STATUS (0x00000C01)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_STATUS);
+  AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_STATUS, Msr);
+  @endcode
+  @note MSR_NEHALEM_U_PMON_GLOBAL_STATUS is defined as MSR_U_PMON_GLOBAL_STATUS in SDM.
+**/
+#define MSR_NEHALEM_U_PMON_GLOBAL_STATUS         0x00000C01
+
+
+/**
+  Package. Uncore U-box perfmon global overflow control MSR.
+
+  @param  ECX  MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL (0x00000C02)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL);
+  AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL, Msr);
+  @endcode
+  @note MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL is defined as MSR_U_PMON_GLOBAL_OVF_CTRL in SDM.
+**/
+#define MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL       0x00000C02
+
+
+/**
+  Package. Uncore U-box perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_U_PMON_EVNT_SEL (0x00000C10)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_EVNT_SEL);
+  AsmWriteMsr64 (MSR_NEHALEM_U_PMON_EVNT_SEL, Msr);
+  @endcode
+  @note MSR_NEHALEM_U_PMON_EVNT_SEL is defined as MSR_U_PMON_EVNT_SEL in SDM.
+**/
+#define MSR_NEHALEM_U_PMON_EVNT_SEL              0x00000C10
+
+
+/**
+  Package. Uncore U-box perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_U_PMON_CTR (0x00000C11)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_CTR);
+  AsmWriteMsr64 (MSR_NEHALEM_U_PMON_CTR, Msr);
+  @endcode
+  @note MSR_NEHALEM_U_PMON_CTR is defined as MSR_U_PMON_CTR in SDM.
+**/
+#define MSR_NEHALEM_U_PMON_CTR                   0x00000C11
+
+
+/**
+  Package. Uncore B-box 0 perfmon local box control MSR.
+
+  @param  ECX  MSR_NEHALEM_B0_PMON_BOX_CTRL (0x00000C20)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_CTRL);
+  AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_CTRL, Msr);
+  @endcode
+  @note MSR_NEHALEM_B0_PMON_BOX_CTRL is defined as MSR_B0_PMON_BOX_CTRL in SDM.
+**/
+#define MSR_NEHALEM_B0_PMON_BOX_CTRL             0x00000C20
+
+
+/**
+  Package. Uncore B-box 0 perfmon local box status MSR.
+
+  @param  ECX  MSR_NEHALEM_B0_PMON_BOX_STATUS (0x00000C21)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_NEHALEM_B0_PMON_BOX_STATUS is defined as MSR_B0_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_NEHALEM_B0_PMON_BOX_STATUS           0x00000C21
+
+
+/**
+  Package. Uncore B-box 0 perfmon local box overflow control MSR.
+
+  @param  ECX  MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL (0x00000C22)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL);
+  AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL, Msr);
+  @endcode
+  @note MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL is defined as MSR_B0_PMON_BOX_OVF_CTRL in SDM.
+**/
+#define MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL         0x00000C22
+
+
+/**
+  Package. Uncore B-box 0 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_B0_PMON_EVNT_SEL0 (0x00000C30)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL0);
+  AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL0, Msr);
+  @endcode
+  @note MSR_NEHALEM_B0_PMON_EVNT_SEL0 is defined as MSR_B0_PMON_EVNT_SEL0 in SDM.
+**/
+#define MSR_NEHALEM_B0_PMON_EVNT_SEL0            0x00000C30
+
+
+/**
+  Package. Uncore B-box 0 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_B0_PMON_CTR0 (0x00000C31)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR0);
+  AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_NEHALEM_B0_PMON_CTR0 is defined as MSR_B0_PMON_CTR0 in SDM.
+**/
+#define MSR_NEHALEM_B0_PMON_CTR0                 0x00000C31
+
+
+/**
+  Package. Uncore B-box 0 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_B0_PMON_EVNT_SEL1 (0x00000C32)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL1);
+  AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL1, Msr);
+  @endcode
+  @note MSR_NEHALEM_B0_PMON_EVNT_SEL1 is defined as MSR_B0_PMON_EVNT_SEL1 in SDM.
+**/
+#define MSR_NEHALEM_B0_PMON_EVNT_SEL1            0x00000C32
+
+
+/**
+  Package. Uncore B-box 0 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_B0_PMON_CTR1 (0x00000C33)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR1);
+  AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_NEHALEM_B0_PMON_CTR1 is defined as MSR_B0_PMON_CTR1 in SDM.
+**/
+#define MSR_NEHALEM_B0_PMON_CTR1                 0x00000C33
+
+
+/**
+  Package. Uncore B-box 0 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_B0_PMON_EVNT_SEL2 (0x00000C34)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL2);
+  AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL2, Msr);
+  @endcode
+  @note MSR_NEHALEM_B0_PMON_EVNT_SEL2 is defined as MSR_B0_PMON_EVNT_SEL2 in SDM.
+**/
+#define MSR_NEHALEM_B0_PMON_EVNT_SEL2            0x00000C34
+
+
+/**
+  Package. Uncore B-box 0 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_B0_PMON_CTR2 (0x00000C35)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR2);
+  AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_NEHALEM_B0_PMON_CTR2 is defined as MSR_B0_PMON_CTR2 in SDM.
+**/
+#define MSR_NEHALEM_B0_PMON_CTR2                 0x00000C35
+
+
+/**
+  Package. Uncore B-box 0 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_B0_PMON_EVNT_SEL3 (0x00000C36)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL3);
+  AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL3, Msr);
+  @endcode
+  @note MSR_NEHALEM_B0_PMON_EVNT_SEL3 is defined as MSR_B0_PMON_EVNT_SEL3 in SDM.
+**/
+#define MSR_NEHALEM_B0_PMON_EVNT_SEL3            0x00000C36
+
+
+/**
+  Package. Uncore B-box 0 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_B0_PMON_CTR3 (0x00000C37)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR3);
+  AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_NEHALEM_B0_PMON_CTR3 is defined as MSR_B0_PMON_CTR3 in SDM.
+**/
+#define MSR_NEHALEM_B0_PMON_CTR3                 0x00000C37
+
+
+/**
+  Package. Uncore S-box 0 perfmon local box control MSR.
+
+  @param  ECX  MSR_NEHALEM_S0_PMON_BOX_CTRL (0x00000C40)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_CTRL);
+  AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_CTRL, Msr);
+  @endcode
+  @note MSR_NEHALEM_S0_PMON_BOX_CTRL is defined as MSR_S0_PMON_BOX_CTRL in SDM.
+**/
+#define MSR_NEHALEM_S0_PMON_BOX_CTRL             0x00000C40
+
+
+/**
+  Package. Uncore S-box 0 perfmon local box status MSR.
+
+  @param  ECX  MSR_NEHALEM_S0_PMON_BOX_STATUS (0x00000C41)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_NEHALEM_S0_PMON_BOX_STATUS is defined as MSR_S0_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_NEHALEM_S0_PMON_BOX_STATUS           0x00000C41
+
+
+/**
+  Package. Uncore S-box 0 perfmon local box overflow control MSR.
+
+  @param  ECX  MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL (0x00000C42)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL);
+  AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL, Msr);
+  @endcode
+  @note MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL is defined as MSR_S0_PMON_BOX_OVF_CTRL in SDM.
+**/
+#define MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL         0x00000C42
+
+
+/**
+  Package. Uncore S-box 0 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_S0_PMON_EVNT_SEL0 (0x00000C50)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL0);
+  AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL0, Msr);
+  @endcode
+  @note MSR_NEHALEM_S0_PMON_EVNT_SEL0 is defined as MSR_S0_PMON_EVNT_SEL0 in SDM.
+**/
+#define MSR_NEHALEM_S0_PMON_EVNT_SEL0            0x00000C50
+
+
+/**
+  Package. Uncore S-box 0 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_S0_PMON_CTR0 (0x00000C51)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR0);
+  AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_NEHALEM_S0_PMON_CTR0 is defined as MSR_S0_PMON_CTR0 in SDM.
+**/
+#define MSR_NEHALEM_S0_PMON_CTR0                 0x00000C51
+
+
+/**
+  Package. Uncore S-box 0 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_S0_PMON_EVNT_SEL1 (0x00000C52)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL1);
+  AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL1, Msr);
+  @endcode
+  @note MSR_NEHALEM_S0_PMON_EVNT_SEL1 is defined as MSR_S0_PMON_EVNT_SEL1 in SDM.
+**/
+#define MSR_NEHALEM_S0_PMON_EVNT_SEL1            0x00000C52
+
+
+/**
+  Package. Uncore S-box 0 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_S0_PMON_CTR1 (0x00000C53)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR1);
+  AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_NEHALEM_S0_PMON_CTR1 is defined as MSR_S0_PMON_CTR1 in SDM.
+**/
+#define MSR_NEHALEM_S0_PMON_CTR1                 0x00000C53
+
+
+/**
+  Package. Uncore S-box 0 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_S0_PMON_EVNT_SEL2 (0x00000C54)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL2);
+  AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL2, Msr);
+  @endcode
+  @note MSR_NEHALEM_S0_PMON_EVNT_SEL2 is defined as MSR_S0_PMON_EVNT_SEL2 in SDM.
+**/
+#define MSR_NEHALEM_S0_PMON_EVNT_SEL2            0x00000C54
+
+
+/**
+  Package. Uncore S-box 0 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_S0_PMON_CTR2 (0x00000C55)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR2);
+  AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_NEHALEM_S0_PMON_CTR2 is defined as MSR_S0_PMON_CTR2 in SDM.
+**/
+#define MSR_NEHALEM_S0_PMON_CTR2                 0x00000C55
+
+
+/**
+  Package. Uncore S-box 0 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_S0_PMON_EVNT_SEL3 (0x00000C56)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL3);
+  AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL3, Msr);
+  @endcode
+  @note MSR_NEHALEM_S0_PMON_EVNT_SEL3 is defined as MSR_S0_PMON_EVNT_SEL3 in SDM.
+**/
+#define MSR_NEHALEM_S0_PMON_EVNT_SEL3            0x00000C56
+
+
+/**
+  Package. Uncore S-box 0 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_S0_PMON_CTR3 (0x00000C57)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR3);
+  AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_NEHALEM_S0_PMON_CTR3 is defined as MSR_S0_PMON_CTR3 in SDM.
+**/
+#define MSR_NEHALEM_S0_PMON_CTR3                 0x00000C57
+
+
+/**
+  Package. Uncore B-box 1 perfmon local box control MSR.
+
+  @param  ECX  MSR_NEHALEM_B1_PMON_BOX_CTRL (0x00000C60)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_CTRL);
+  AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_CTRL, Msr);
+  @endcode
+  @note MSR_NEHALEM_B1_PMON_BOX_CTRL is defined as MSR_B1_PMON_BOX_CTRL in SDM.
+**/
+#define MSR_NEHALEM_B1_PMON_BOX_CTRL             0x00000C60
+
+
+/**
+  Package. Uncore B-box 1 perfmon local box status MSR.
+
+  @param  ECX  MSR_NEHALEM_B1_PMON_BOX_STATUS (0x00000C61)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_NEHALEM_B1_PMON_BOX_STATUS is defined as MSR_B1_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_NEHALEM_B1_PMON_BOX_STATUS           0x00000C61
+
+
+/**
+  Package. Uncore B-box 1 perfmon local box overflow control MSR.
+
+  @param  ECX  MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL (0x00000C62)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL);
+  AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL, Msr);
+  @endcode
+  @note MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL is defined as MSR_B1_PMON_BOX_OVF_CTRL in SDM.
+**/
+#define MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL         0x00000C62
+
+
+/**
+  Package. Uncore B-box 1 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_B1_PMON_EVNT_SEL0 (0x00000C70)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL0);
+  AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL0, Msr);
+  @endcode
+  @note MSR_NEHALEM_B1_PMON_EVNT_SEL0 is defined as MSR_B1_PMON_EVNT_SEL0 in SDM.
+**/
+#define MSR_NEHALEM_B1_PMON_EVNT_SEL0            0x00000C70
+
+
+/**
+  Package. Uncore B-box 1 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_B1_PMON_CTR0 (0x00000C71)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR0);
+  AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_NEHALEM_B1_PMON_CTR0 is defined as MSR_B1_PMON_CTR0 in SDM.
+**/
+#define MSR_NEHALEM_B1_PMON_CTR0                 0x00000C71
+
+
+/**
+  Package. Uncore B-box 1 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_B1_PMON_EVNT_SEL1 (0x00000C72)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL1);
+  AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL1, Msr);
+  @endcode
+  @note MSR_NEHALEM_B1_PMON_EVNT_SEL1 is defined as MSR_B1_PMON_EVNT_SEL1 in SDM.
+**/
+#define MSR_NEHALEM_B1_PMON_EVNT_SEL1            0x00000C72
+
+
+/**
+  Package. Uncore B-box 1 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_B1_PMON_CTR1 (0x00000C73)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR1);
+  AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_NEHALEM_B1_PMON_CTR1 is defined as MSR_B1_PMON_CTR1 in SDM.
+**/
+#define MSR_NEHALEM_B1_PMON_CTR1                 0x00000C73
+
+
+/**
+  Package. Uncore B-box 1 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_B1_PMON_EVNT_SEL2 (0x00000C74)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL2);
+  AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL2, Msr);
+  @endcode
+  @note MSR_NEHALEM_B1_PMON_EVNT_SEL2 is defined as MSR_B1_PMON_EVNT_SEL2 in SDM.
+**/
+#define MSR_NEHALEM_B1_PMON_EVNT_SEL2            0x00000C74
+
+
+/**
+  Package. Uncore B-box 1 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_B1_PMON_CTR2 (0x00000C75)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR2);
+  AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_NEHALEM_B1_PMON_CTR2 is defined as MSR_B1_PMON_CTR2 in SDM.
+**/
+#define MSR_NEHALEM_B1_PMON_CTR2                 0x00000C75
+
+
+/**
+  Package. Uncore B-box 1vperfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_B1_PMON_EVNT_SEL3 (0x00000C76)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL3);
+  AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL3, Msr);
+  @endcode
+  @note MSR_NEHALEM_B1_PMON_EVNT_SEL3 is defined as MSR_B1_PMON_EVNT_SEL3 in SDM.
+**/
+#define MSR_NEHALEM_B1_PMON_EVNT_SEL3            0x00000C76
+
+
+/**
+  Package. Uncore B-box 1 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_B1_PMON_CTR3 (0x00000C77)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR3);
+  AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_NEHALEM_B1_PMON_CTR3 is defined as MSR_B1_PMON_CTR3 in SDM.
+**/
+#define MSR_NEHALEM_B1_PMON_CTR3                 0x00000C77
+
+
+/**
+  Package. Uncore W-box perfmon local box control MSR.
+
+  @param  ECX  MSR_NEHALEM_W_PMON_BOX_CTRL (0x00000C80)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_CTRL);
+  AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_CTRL, Msr);
+  @endcode
+  @note MSR_NEHALEM_W_PMON_BOX_CTRL is defined as MSR_W_PMON_BOX_CTRL in SDM.
+**/
+#define MSR_NEHALEM_W_PMON_BOX_CTRL              0x00000C80
+
+
+/**
+  Package. Uncore W-box perfmon local box status MSR.
+
+  @param  ECX  MSR_NEHALEM_W_PMON_BOX_STATUS (0x00000C81)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_NEHALEM_W_PMON_BOX_STATUS is defined as MSR_W_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_NEHALEM_W_PMON_BOX_STATUS            0x00000C81
+
+
+/**
+  Package. Uncore W-box perfmon local box overflow control MSR.
+
+  @param  ECX  MSR_NEHALEM_W_PMON_BOX_OVF_CTRL (0x00000C82)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_OVF_CTRL);
+  AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_OVF_CTRL, Msr);
+  @endcode
+  @note MSR_NEHALEM_W_PMON_BOX_OVF_CTRL is defined as MSR_W_PMON_BOX_OVF_CTRL in SDM.
+**/
+#define MSR_NEHALEM_W_PMON_BOX_OVF_CTRL          0x00000C82
+
+
+/**
+  Package. Uncore W-box perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_W_PMON_EVNT_SEL0 (0x00000C90)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL0);
+  AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL0, Msr);
+  @endcode
+  @note MSR_NEHALEM_W_PMON_EVNT_SEL0 is defined as MSR_W_PMON_EVNT_SEL0 in SDM.
+**/
+#define MSR_NEHALEM_W_PMON_EVNT_SEL0             0x00000C90
+
+
+/**
+  Package. Uncore W-box perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_W_PMON_CTR0 (0x00000C91)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR0);
+  AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_NEHALEM_W_PMON_CTR0 is defined as MSR_W_PMON_CTR0 in SDM.
+**/
+#define MSR_NEHALEM_W_PMON_CTR0                  0x00000C91
+
+
+/**
+  Package. Uncore W-box perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_W_PMON_EVNT_SEL1 (0x00000C92)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL1);
+  AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL1, Msr);
+  @endcode
+  @note MSR_NEHALEM_W_PMON_EVNT_SEL1 is defined as MSR_W_PMON_EVNT_SEL1 in SDM.
+**/
+#define MSR_NEHALEM_W_PMON_EVNT_SEL1             0x00000C92
+
+
+/**
+  Package. Uncore W-box perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_W_PMON_CTR1 (0x00000C93)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR1);
+  AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_NEHALEM_W_PMON_CTR1 is defined as MSR_W_PMON_CTR1 in SDM.
+**/
+#define MSR_NEHALEM_W_PMON_CTR1                  0x00000C93
+
+
+/**
+  Package. Uncore W-box perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_W_PMON_EVNT_SEL2 (0x00000C94)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL2);
+  AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL2, Msr);
+  @endcode
+  @note MSR_NEHALEM_W_PMON_EVNT_SEL2 is defined as MSR_W_PMON_EVNT_SEL2 in SDM.
+**/
+#define MSR_NEHALEM_W_PMON_EVNT_SEL2             0x00000C94
+
+
+/**
+  Package. Uncore W-box perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_W_PMON_CTR2 (0x00000C95)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR2);
+  AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_NEHALEM_W_PMON_CTR2 is defined as MSR_W_PMON_CTR2 in SDM.
+**/
+#define MSR_NEHALEM_W_PMON_CTR2                  0x00000C95
+
+
+/**
+  Package. Uncore W-box perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_W_PMON_EVNT_SEL3 (0x00000C96)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL3);
+  AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL3, Msr);
+  @endcode
+  @note MSR_NEHALEM_W_PMON_EVNT_SEL3 is defined as MSR_W_PMON_EVNT_SEL3 in SDM.
+**/
+#define MSR_NEHALEM_W_PMON_EVNT_SEL3             0x00000C96
+
+
+/**
+  Package. Uncore W-box perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_W_PMON_CTR3 (0x00000C97)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR3);
+  AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_NEHALEM_W_PMON_CTR3 is defined as MSR_W_PMON_CTR3 in SDM.
+**/
+#define MSR_NEHALEM_W_PMON_CTR3                  0x00000C97
+
+
+/**
+  Package. Uncore M-box 0 perfmon local box control MSR.
+
+  @param  ECX  MSR_NEHALEM_M0_PMON_BOX_CTRL (0x00000CA0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_CTRL);
+  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_CTRL, Msr);
+  @endcode
+  @note MSR_NEHALEM_M0_PMON_BOX_CTRL is defined as MSR_M0_PMON_BOX_CTRL in SDM.
+**/
+#define MSR_NEHALEM_M0_PMON_BOX_CTRL             0x00000CA0
+
+
+/**
+  Package. Uncore M-box 0 perfmon local box status MSR.
+
+  @param  ECX  MSR_NEHALEM_M0_PMON_BOX_STATUS (0x00000CA1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_NEHALEM_M0_PMON_BOX_STATUS is defined as MSR_M0_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_NEHALEM_M0_PMON_BOX_STATUS           0x00000CA1
+
+
+/**
+  Package. Uncore M-box 0 perfmon local box overflow control MSR.
+
+  @param  ECX  MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL (0x00000CA2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL);
+  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL, Msr);
+  @endcode
+  @note MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL is defined as MSR_M0_PMON_BOX_OVF_CTRL in SDM.
+**/
+#define MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL         0x00000CA2
+
+
+/**
+  Package. Uncore M-box 0 perfmon time stamp unit select MSR.
+
+  @param  ECX  MSR_NEHALEM_M0_PMON_TIMESTAMP (0x00000CA4)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_TIMESTAMP);
+  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_TIMESTAMP, Msr);
+  @endcode
+  @note MSR_NEHALEM_M0_PMON_TIMESTAMP is defined as MSR_M0_PMON_TIMESTAMP in SDM.
+**/
+#define MSR_NEHALEM_M0_PMON_TIMESTAMP            0x00000CA4
+
+
+/**
+  Package. Uncore M-box 0 perfmon DSP unit select MSR.
+
+  @param  ECX  MSR_NEHALEM_M0_PMON_DSP (0x00000CA5)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_DSP);
+  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_DSP, Msr);
+  @endcode
+  @note MSR_NEHALEM_M0_PMON_DSP is defined as MSR_M0_PMON_DSP in SDM.
+**/
+#define MSR_NEHALEM_M0_PMON_DSP                  0x00000CA5
+
+
+/**
+  Package. Uncore M-box 0 perfmon ISS unit select MSR.
+
+  @param  ECX  MSR_NEHALEM_M0_PMON_ISS (0x00000CA6)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ISS);
+  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ISS, Msr);
+  @endcode
+  @note MSR_NEHALEM_M0_PMON_ISS is defined as MSR_M0_PMON_ISS in SDM.
+**/
+#define MSR_NEHALEM_M0_PMON_ISS                  0x00000CA6
+
+
+/**
+  Package. Uncore M-box 0 perfmon MAP unit select MSR.
+
+  @param  ECX  MSR_NEHALEM_M0_PMON_MAP (0x00000CA7)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MAP);
+  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MAP, Msr);
+  @endcode
+  @note MSR_NEHALEM_M0_PMON_MAP is defined as MSR_M0_PMON_MAP in SDM.
+**/
+#define MSR_NEHALEM_M0_PMON_MAP                  0x00000CA7
+
+
+/**
+  Package. Uncore M-box 0 perfmon MIC THR select MSR.
+
+  @param  ECX  MSR_NEHALEM_M0_PMON_MSC_THR (0x00000CA8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MSC_THR);
+  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MSC_THR, Msr);
+  @endcode
+  @note MSR_NEHALEM_M0_PMON_MSC_THR is defined as MSR_M0_PMON_MSC_THR in SDM.
+**/
+#define MSR_NEHALEM_M0_PMON_MSC_THR              0x00000CA8
+
+
+/**
+  Package. Uncore M-box 0 perfmon PGT unit select MSR.
+
+  @param  ECX  MSR_NEHALEM_M0_PMON_PGT (0x00000CA9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_PGT);
+  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_PGT, Msr);
+  @endcode
+  @note MSR_NEHALEM_M0_PMON_PGT is defined as MSR_M0_PMON_PGT in SDM.
+**/
+#define MSR_NEHALEM_M0_PMON_PGT                  0x00000CA9
+
+
+/**
+  Package. Uncore M-box 0 perfmon PLD unit select MSR.
+
+  @param  ECX  MSR_NEHALEM_M0_PMON_PLD (0x00000CAA)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_PLD);
+  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_PLD, Msr);
+  @endcode
+  @note MSR_NEHALEM_M0_PMON_PLD is defined as MSR_M0_PMON_PLD in SDM.
+**/
+#define MSR_NEHALEM_M0_PMON_PLD                  0x00000CAA
+
+
+/**
+  Package. Uncore M-box 0 perfmon ZDP unit select MSR.
+
+  @param  ECX  MSR_NEHALEM_M0_PMON_ZDP (0x00000CAB)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ZDP);
+  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ZDP, Msr);
+  @endcode
+  @note MSR_NEHALEM_M0_PMON_ZDP is defined as MSR_M0_PMON_ZDP in SDM.
+**/
+#define MSR_NEHALEM_M0_PMON_ZDP                  0x00000CAB
+
+
+/**
+  Package. Uncore M-box 0 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_M0_PMON_EVNT_SEL0 (0x00000CB0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL0);
+  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL0, Msr);
+  @endcode
+  @note MSR_NEHALEM_M0_PMON_EVNT_SEL0 is defined as MSR_M0_PMON_EVNT_SEL0 in SDM.
+**/
+#define MSR_NEHALEM_M0_PMON_EVNT_SEL0            0x00000CB0
+
+
+/**
+  Package. Uncore M-box 0 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_M0_PMON_CTR0 (0x00000CB1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR0);
+  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_NEHALEM_M0_PMON_CTR0 is defined as MSR_M0_PMON_CTR0 in SDM.
+**/
+#define MSR_NEHALEM_M0_PMON_CTR0                 0x00000CB1
+
+
+/**
+  Package. Uncore M-box 0 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_M0_PMON_EVNT_SEL1 (0x00000CB2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL1);
+  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL1, Msr);
+  @endcode
+  @note MSR_NEHALEM_M0_PMON_EVNT_SEL1 is defined as MSR_M0_PMON_EVNT_SEL1 in SDM.
+**/
+#define MSR_NEHALEM_M0_PMON_EVNT_SEL1            0x00000CB2
+
+
+/**
+  Package. Uncore M-box 0 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_M0_PMON_CTR1 (0x00000CB3)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR1);
+  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_NEHALEM_M0_PMON_CTR1 is defined as MSR_M0_PMON_CTR1 in SDM.
+**/
+#define MSR_NEHALEM_M0_PMON_CTR1                 0x00000CB3
+
+
+/**
+  Package. Uncore M-box 0 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_M0_PMON_EVNT_SEL2 (0x00000CB4)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL2);
+  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL2, Msr);
+  @endcode
+  @note MSR_NEHALEM_M0_PMON_EVNT_SEL2 is defined as MSR_M0_PMON_EVNT_SEL2 in SDM.
+**/
+#define MSR_NEHALEM_M0_PMON_EVNT_SEL2            0x00000CB4
+
+
+/**
+  Package. Uncore M-box 0 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_M0_PMON_CTR2 (0x00000CB5)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR2);
+  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_NEHALEM_M0_PMON_CTR2 is defined as MSR_M0_PMON_CTR2 in SDM.
+**/
+#define MSR_NEHALEM_M0_PMON_CTR2                 0x00000CB5
+
+
+/**
+  Package. Uncore M-box 0 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_M0_PMON_EVNT_SEL3 (0x00000CB6)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL3);
+  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL3, Msr);
+  @endcode
+  @note MSR_NEHALEM_M0_PMON_EVNT_SEL3 is defined as MSR_M0_PMON_EVNT_SEL3 in SDM.
+**/
+#define MSR_NEHALEM_M0_PMON_EVNT_SEL3            0x00000CB6
+
+
+/**
+  Package. Uncore M-box 0 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_M0_PMON_CTR3 (0x00000CB7)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR3);
+  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_NEHALEM_M0_PMON_CTR3 is defined as MSR_M0_PMON_CTR3 in SDM.
+**/
+#define MSR_NEHALEM_M0_PMON_CTR3                 0x00000CB7
+
+
+/**
+  Package. Uncore M-box 0 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_M0_PMON_EVNT_SEL4 (0x00000CB8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL4);
+  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL4, Msr);
+  @endcode
+  @note MSR_NEHALEM_M0_PMON_EVNT_SEL4 is defined as MSR_M0_PMON_EVNT_SEL4 in SDM.
+**/
+#define MSR_NEHALEM_M0_PMON_EVNT_SEL4            0x00000CB8
+
+
+/**
+  Package. Uncore M-box 0 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_M0_PMON_CTR4 (0x00000CB9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR4);
+  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR4, Msr);
+  @endcode
+  @note MSR_NEHALEM_M0_PMON_CTR4 is defined as MSR_M0_PMON_CTR4 in SDM.
+**/
+#define MSR_NEHALEM_M0_PMON_CTR4                 0x00000CB9
+
+
+/**
+  Package. Uncore M-box 0 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_M0_PMON_EVNT_SEL5 (0x00000CBA)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL5);
+  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL5, Msr);
+  @endcode
+  @note MSR_NEHALEM_M0_PMON_EVNT_SEL5 is defined as MSR_M0_PMON_EVNT_SEL5 in SDM.
+**/
+#define MSR_NEHALEM_M0_PMON_EVNT_SEL5            0x00000CBA
+
+
+/**
+  Package. Uncore M-box 0 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_M0_PMON_CTR5 (0x00000CBB)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR5);
+  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR5, Msr);
+  @endcode
+  @note MSR_NEHALEM_M0_PMON_CTR5 is defined as MSR_M0_PMON_CTR5 in SDM.
+**/
+#define MSR_NEHALEM_M0_PMON_CTR5                 0x00000CBB
+
+
+/**
+  Package. Uncore S-box 1 perfmon local box control MSR.
+
+  @param  ECX  MSR_NEHALEM_S1_PMON_BOX_CTRL (0x00000CC0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_CTRL);
+  AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_CTRL, Msr);
+  @endcode
+  @note MSR_NEHALEM_S1_PMON_BOX_CTRL is defined as MSR_S1_PMON_BOX_CTRL in SDM.
+**/
+#define MSR_NEHALEM_S1_PMON_BOX_CTRL             0x00000CC0
+
+
+/**
+  Package. Uncore S-box 1 perfmon local box status MSR.
+
+  @param  ECX  MSR_NEHALEM_S1_PMON_BOX_STATUS (0x00000CC1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_NEHALEM_S1_PMON_BOX_STATUS is defined as MSR_S1_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_NEHALEM_S1_PMON_BOX_STATUS           0x00000CC1
+
+
+/**
+  Package. Uncore S-box 1 perfmon local box overflow control MSR.
+
+  @param  ECX  MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL (0x00000CC2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL);
+  AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL, Msr);
+  @endcode
+  @note MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL is defined as MSR_S1_PMON_BOX_OVF_CTRL in SDM.
+**/
+#define MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL         0x00000CC2
+
+
+/**
+  Package. Uncore S-box 1 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_S1_PMON_EVNT_SEL0 (0x00000CD0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL0);
+  AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL0, Msr);
+  @endcode
+  @note MSR_NEHALEM_S1_PMON_EVNT_SEL0 is defined as MSR_S1_PMON_EVNT_SEL0 in SDM.
+**/
+#define MSR_NEHALEM_S1_PMON_EVNT_SEL0            0x00000CD0
+
+
+/**
+  Package. Uncore S-box 1 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_S1_PMON_CTR0 (0x00000CD1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR0);
+  AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_NEHALEM_S1_PMON_CTR0 is defined as MSR_S1_PMON_CTR0 in SDM.
+**/
+#define MSR_NEHALEM_S1_PMON_CTR0                 0x00000CD1
+
+
+/**
+  Package. Uncore S-box 1 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_S1_PMON_EVNT_SEL1 (0x00000CD2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL1);
+  AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL1, Msr);
+  @endcode
+  @note MSR_NEHALEM_S1_PMON_EVNT_SEL1 is defined as MSR_S1_PMON_EVNT_SEL1 in SDM.
+**/
+#define MSR_NEHALEM_S1_PMON_EVNT_SEL1            0x00000CD2
+
+
+/**
+  Package. Uncore S-box 1 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_S1_PMON_CTR1 (0x00000CD3)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR1);
+  AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_NEHALEM_S1_PMON_CTR1 is defined as MSR_S1_PMON_CTR1 in SDM.
+**/
+#define MSR_NEHALEM_S1_PMON_CTR1                 0x00000CD3
+
+
+/**
+  Package. Uncore S-box 1 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_S1_PMON_EVNT_SEL2 (0x00000CD4)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL2);
+  AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL2, Msr);
+  @endcode
+  @note MSR_NEHALEM_S1_PMON_EVNT_SEL2 is defined as MSR_S1_PMON_EVNT_SEL2 in SDM.
+**/
+#define MSR_NEHALEM_S1_PMON_EVNT_SEL2            0x00000CD4
+
+
+/**
+  Package. Uncore S-box 1 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_S1_PMON_CTR2 (0x00000CD5)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR2);
+  AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_NEHALEM_S1_PMON_CTR2 is defined as MSR_S1_PMON_CTR2 in SDM.
+**/
+#define MSR_NEHALEM_S1_PMON_CTR2                 0x00000CD5
+
+
+/**
+  Package. Uncore S-box 1 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_S1_PMON_EVNT_SEL3 (0x00000CD6)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL3);
+  AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL3, Msr);
+  @endcode
+  @note MSR_NEHALEM_S1_PMON_EVNT_SEL3 is defined as MSR_S1_PMON_EVNT_SEL3 in SDM.
+**/
+#define MSR_NEHALEM_S1_PMON_EVNT_SEL3            0x00000CD6
+
+
+/**
+  Package. Uncore S-box 1 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_S1_PMON_CTR3 (0x00000CD7)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR3);
+  AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_NEHALEM_S1_PMON_CTR3 is defined as MSR_S1_PMON_CTR3 in SDM.
+**/
+#define MSR_NEHALEM_S1_PMON_CTR3                 0x00000CD7
+
+
+/**
+  Package. Uncore M-box 1 perfmon local box control MSR.
+
+  @param  ECX  MSR_NEHALEM_M1_PMON_BOX_CTRL (0x00000CE0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_CTRL);
+  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_CTRL, Msr);
+  @endcode
+  @note MSR_NEHALEM_M1_PMON_BOX_CTRL is defined as MSR_M1_PMON_BOX_CTRL in SDM.
+**/
+#define MSR_NEHALEM_M1_PMON_BOX_CTRL             0x00000CE0
+
+
+/**
+  Package. Uncore M-box 1 perfmon local box status MSR.
+
+  @param  ECX  MSR_NEHALEM_M1_PMON_BOX_STATUS (0x00000CE1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_NEHALEM_M1_PMON_BOX_STATUS is defined as MSR_M1_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_NEHALEM_M1_PMON_BOX_STATUS           0x00000CE1
+
+
+/**
+  Package. Uncore M-box 1 perfmon local box overflow control MSR.
+
+  @param  ECX  MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL (0x00000CE2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL);
+  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL, Msr);
+  @endcode
+  @note MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL is defined as MSR_M1_PMON_BOX_OVF_CTRL in SDM.
+**/
+#define MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL         0x00000CE2
+
+
+/**
+  Package. Uncore M-box 1 perfmon time stamp unit select MSR.
+
+  @param  ECX  MSR_NEHALEM_M1_PMON_TIMESTAMP (0x00000CE4)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_TIMESTAMP);
+  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_TIMESTAMP, Msr);
+  @endcode
+  @note MSR_NEHALEM_M1_PMON_TIMESTAMP is defined as MSR_M1_PMON_TIMESTAMP in SDM.
+**/
+#define MSR_NEHALEM_M1_PMON_TIMESTAMP            0x00000CE4
+
+
+/**
+  Package. Uncore M-box 1 perfmon DSP unit select MSR.
+
+  @param  ECX  MSR_NEHALEM_M1_PMON_DSP (0x00000CE5)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_DSP);
+  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_DSP, Msr);
+  @endcode
+  @note MSR_NEHALEM_M1_PMON_DSP is defined as MSR_M1_PMON_DSP in SDM.
+**/
+#define MSR_NEHALEM_M1_PMON_DSP                  0x00000CE5
+
+
+/**
+  Package. Uncore M-box 1 perfmon ISS unit select MSR.
+
+  @param  ECX  MSR_NEHALEM_M1_PMON_ISS (0x00000CE6)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ISS);
+  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ISS, Msr);
+  @endcode
+  @note MSR_NEHALEM_M1_PMON_ISS is defined as MSR_M1_PMON_ISS in SDM.
+**/
+#define MSR_NEHALEM_M1_PMON_ISS                  0x00000CE6
+
+
+/**
+  Package. Uncore M-box 1 perfmon MAP unit select MSR.
+
+  @param  ECX  MSR_NEHALEM_M1_PMON_MAP (0x00000CE7)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MAP);
+  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MAP, Msr);
+  @endcode
+  @note MSR_NEHALEM_M1_PMON_MAP is defined as MSR_M1_PMON_MAP in SDM.
+**/
+#define MSR_NEHALEM_M1_PMON_MAP                  0x00000CE7
+
+
+/**
+  Package. Uncore M-box 1 perfmon MIC THR select MSR.
+
+  @param  ECX  MSR_NEHALEM_M1_PMON_MSC_THR (0x00000CE8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MSC_THR);
+  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MSC_THR, Msr);
+  @endcode
+  @note MSR_NEHALEM_M1_PMON_MSC_THR is defined as MSR_M1_PMON_MSC_THR in SDM.
+**/
+#define MSR_NEHALEM_M1_PMON_MSC_THR              0x00000CE8
+
+
+/**
+  Package. Uncore M-box 1 perfmon PGT unit select MSR.
+
+  @param  ECX  MSR_NEHALEM_M1_PMON_PGT (0x00000CE9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_PGT);
+  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_PGT, Msr);
+  @endcode
+  @note MSR_NEHALEM_M1_PMON_PGT is defined as MSR_M1_PMON_PGT in SDM.
+**/
+#define MSR_NEHALEM_M1_PMON_PGT                  0x00000CE9
+
+
+/**
+  Package. Uncore M-box 1 perfmon PLD unit select MSR.
+
+  @param  ECX  MSR_NEHALEM_M1_PMON_PLD (0x00000CEA)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_PLD);
+  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_PLD, Msr);
+  @endcode
+  @note MSR_NEHALEM_M1_PMON_PLD is defined as MSR_M1_PMON_PLD in SDM.
+**/
+#define MSR_NEHALEM_M1_PMON_PLD                  0x00000CEA
+
+
+/**
+  Package. Uncore M-box 1 perfmon ZDP unit select MSR.
+
+  @param  ECX  MSR_NEHALEM_M1_PMON_ZDP (0x00000CEB)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ZDP);
+  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ZDP, Msr);
+  @endcode
+  @note MSR_NEHALEM_M1_PMON_ZDP is defined as MSR_M1_PMON_ZDP in SDM.
+**/
+#define MSR_NEHALEM_M1_PMON_ZDP                  0x00000CEB
+
+
+/**
+  Package. Uncore M-box 1 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_M1_PMON_EVNT_SEL0 (0x00000CF0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL0);
+  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL0, Msr);
+  @endcode
+  @note MSR_NEHALEM_M1_PMON_EVNT_SEL0 is defined as MSR_M1_PMON_EVNT_SEL0 in SDM.
+**/
+#define MSR_NEHALEM_M1_PMON_EVNT_SEL0            0x00000CF0
+
+
+/**
+  Package. Uncore M-box 1 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_M1_PMON_CTR0 (0x00000CF1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR0);
+  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_NEHALEM_M1_PMON_CTR0 is defined as MSR_M1_PMON_CTR0 in SDM.
+**/
+#define MSR_NEHALEM_M1_PMON_CTR0                 0x00000CF1
+
+
+/**
+  Package. Uncore M-box 1 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_M1_PMON_EVNT_SEL1 (0x00000CF2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL1);
+  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL1, Msr);
+  @endcode
+  @note MSR_NEHALEM_M1_PMON_EVNT_SEL1 is defined as MSR_M1_PMON_EVNT_SEL1 in SDM.
+**/
+#define MSR_NEHALEM_M1_PMON_EVNT_SEL1            0x00000CF2
+
+
+/**
+  Package. Uncore M-box 1 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_M1_PMON_CTR1 (0x00000CF3)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR1);
+  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_NEHALEM_M1_PMON_CTR1 is defined as MSR_M1_PMON_CTR1 in SDM.
+**/
+#define MSR_NEHALEM_M1_PMON_CTR1                 0x00000CF3
+
+
+/**
+  Package. Uncore M-box 1 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_M1_PMON_EVNT_SEL2 (0x00000CF4)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL2);
+  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL2, Msr);
+  @endcode
+  @note MSR_NEHALEM_M1_PMON_EVNT_SEL2 is defined as MSR_M1_PMON_EVNT_SEL2 in SDM.
+**/
+#define MSR_NEHALEM_M1_PMON_EVNT_SEL2            0x00000CF4
+
+
+/**
+  Package. Uncore M-box 1 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_M1_PMON_CTR2 (0x00000CF5)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR2);
+  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_NEHALEM_M1_PMON_CTR2 is defined as MSR_M1_PMON_CTR2 in SDM.
+**/
+#define MSR_NEHALEM_M1_PMON_CTR2                 0x00000CF5
+
+
+/**
+  Package. Uncore M-box 1 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_M1_PMON_EVNT_SEL3 (0x00000CF6)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL3);
+  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL3, Msr);
+  @endcode
+  @note MSR_NEHALEM_M1_PMON_EVNT_SEL3 is defined as MSR_M1_PMON_EVNT_SEL3 in SDM.
+**/
+#define MSR_NEHALEM_M1_PMON_EVNT_SEL3            0x00000CF6
+
+
+/**
+  Package. Uncore M-box 1 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_M1_PMON_CTR3 (0x00000CF7)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR3);
+  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_NEHALEM_M1_PMON_CTR3 is defined as MSR_M1_PMON_CTR3 in SDM.
+**/
+#define MSR_NEHALEM_M1_PMON_CTR3                 0x00000CF7
+
+
+/**
+  Package. Uncore M-box 1 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_M1_PMON_EVNT_SEL4 (0x00000CF8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL4);
+  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL4, Msr);
+  @endcode
+  @note MSR_NEHALEM_M1_PMON_EVNT_SEL4 is defined as MSR_M1_PMON_EVNT_SEL4 in SDM.
+**/
+#define MSR_NEHALEM_M1_PMON_EVNT_SEL4            0x00000CF8
+
+
+/**
+  Package. Uncore M-box 1 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_M1_PMON_CTR4 (0x00000CF9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR4);
+  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR4, Msr);
+  @endcode
+  @note MSR_NEHALEM_M1_PMON_CTR4 is defined as MSR_M1_PMON_CTR4 in SDM.
+**/
+#define MSR_NEHALEM_M1_PMON_CTR4                 0x00000CF9
+
+
+/**
+  Package. Uncore M-box 1 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_M1_PMON_EVNT_SEL5 (0x00000CFA)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL5);
+  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL5, Msr);
+  @endcode
+  @note MSR_NEHALEM_M1_PMON_EVNT_SEL5 is defined as MSR_M1_PMON_EVNT_SEL5 in SDM.
+**/
+#define MSR_NEHALEM_M1_PMON_EVNT_SEL5            0x00000CFA
+
+
+/**
+  Package. Uncore M-box 1 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_M1_PMON_CTR5 (0x00000CFB)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR5);
+  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR5, Msr);
+  @endcode
+  @note MSR_NEHALEM_M1_PMON_CTR5 is defined as MSR_M1_PMON_CTR5 in SDM.
+**/
+#define MSR_NEHALEM_M1_PMON_CTR5                 0x00000CFB
+
+
+/**
+  Package. Uncore C-box 0 perfmon local box control MSR.
+
+  @param  ECX  MSR_NEHALEM_C0_PMON_BOX_CTRL (0x00000D00)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_CTRL);
+  AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_CTRL, Msr);
+  @endcode
+  @note MSR_NEHALEM_C0_PMON_BOX_CTRL is defined as MSR_C0_PMON_BOX_CTRL in SDM.
+**/
+#define MSR_NEHALEM_C0_PMON_BOX_CTRL             0x00000D00
+
+
+/**
+  Package. Uncore C-box 0 perfmon local box status MSR.
+
+  @param  ECX  MSR_NEHALEM_C0_PMON_BOX_STATUS (0x00000D01)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_NEHALEM_C0_PMON_BOX_STATUS is defined as MSR_C0_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_NEHALEM_C0_PMON_BOX_STATUS           0x00000D01
+
+
+/**
+  Package. Uncore C-box 0 perfmon local box overflow control MSR.
+
+  @param  ECX  MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL (0x00000D02)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL);
+  AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL, Msr);
+  @endcode
+  @note MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL is defined as MSR_C0_PMON_BOX_OVF_CTRL in SDM.
+**/
+#define MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL         0x00000D02
+
+
+/**
+  Package. Uncore C-box 0 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C0_PMON_EVNT_SEL0 (0x00000D10)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL0);
+  AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL0, Msr);
+  @endcode
+  @note MSR_NEHALEM_C0_PMON_EVNT_SEL0 is defined as MSR_C0_PMON_EVNT_SEL0 in SDM.
+**/
+#define MSR_NEHALEM_C0_PMON_EVNT_SEL0            0x00000D10
+
+
+/**
+  Package. Uncore C-box 0 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C0_PMON_CTR0 (0x00000D11)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR0);
+  AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_NEHALEM_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.
+**/
+#define MSR_NEHALEM_C0_PMON_CTR0                 0x00000D11
+
+
+/**
+  Package. Uncore C-box 0 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C0_PMON_EVNT_SEL1 (0x00000D12)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL1);
+  AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL1, Msr);
+  @endcode
+  @note MSR_NEHALEM_C0_PMON_EVNT_SEL1 is defined as MSR_C0_PMON_EVNT_SEL1 in SDM.
+**/
+#define MSR_NEHALEM_C0_PMON_EVNT_SEL1            0x00000D12
+
+
+/**
+  Package. Uncore C-box 0 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C0_PMON_CTR1 (0x00000D13)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR1);
+  AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_NEHALEM_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.
+**/
+#define MSR_NEHALEM_C0_PMON_CTR1                 0x00000D13
+
+
+/**
+  Package. Uncore C-box 0 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C0_PMON_EVNT_SEL2 (0x00000D14)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL2);
+  AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL2, Msr);
+  @endcode
+  @note MSR_NEHALEM_C0_PMON_EVNT_SEL2 is defined as MSR_C0_PMON_EVNT_SEL2 in SDM.
+**/
+#define MSR_NEHALEM_C0_PMON_EVNT_SEL2            0x00000D14
+
+
+/**
+  Package. Uncore C-box 0 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C0_PMON_CTR2 (0x00000D15)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR2);
+  AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_NEHALEM_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.
+**/
+#define MSR_NEHALEM_C0_PMON_CTR2                 0x00000D15
+
+
+/**
+  Package. Uncore C-box 0 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C0_PMON_EVNT_SEL3 (0x00000D16)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL3);
+  AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL3, Msr);
+  @endcode
+  @note MSR_NEHALEM_C0_PMON_EVNT_SEL3 is defined as MSR_C0_PMON_EVNT_SEL3 in SDM.
+**/
+#define MSR_NEHALEM_C0_PMON_EVNT_SEL3            0x00000D16
+
+
+/**
+  Package. Uncore C-box 0 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C0_PMON_CTR3 (0x00000D17)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR3);
+  AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_NEHALEM_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.
+**/
+#define MSR_NEHALEM_C0_PMON_CTR3                 0x00000D17
+
+
+/**
+  Package. Uncore C-box 0 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C0_PMON_EVNT_SEL4 (0x00000D18)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL4);
+  AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL4, Msr);
+  @endcode
+  @note MSR_NEHALEM_C0_PMON_EVNT_SEL4 is defined as MSR_C0_PMON_EVNT_SEL4 in SDM.
+**/
+#define MSR_NEHALEM_C0_PMON_EVNT_SEL4            0x00000D18
+
+
+/**
+  Package. Uncore C-box 0 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C0_PMON_CTR4 (0x00000D19)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR4);
+  AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR4, Msr);
+  @endcode
+  @note MSR_NEHALEM_C0_PMON_CTR4 is defined as MSR_C0_PMON_CTR4 in SDM.
+**/
+#define MSR_NEHALEM_C0_PMON_CTR4                 0x00000D19
+
+
+/**
+  Package. Uncore C-box 0 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C0_PMON_EVNT_SEL5 (0x00000D1A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL5);
+  AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL5, Msr);
+  @endcode
+  @note MSR_NEHALEM_C0_PMON_EVNT_SEL5 is defined as MSR_C0_PMON_EVNT_SEL5 in SDM.
+**/
+#define MSR_NEHALEM_C0_PMON_EVNT_SEL5            0x00000D1A
+
+
+/**
+  Package. Uncore C-box 0 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C0_PMON_CTR5 (0x00000D1B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR5);
+  AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR5, Msr);
+  @endcode
+  @note MSR_NEHALEM_C0_PMON_CTR5 is defined as MSR_C0_PMON_CTR5 in SDM.
+**/
+#define MSR_NEHALEM_C0_PMON_CTR5                 0x00000D1B
+
+
+/**
+  Package. Uncore C-box 4 perfmon local box control MSR.
+
+  @param  ECX  MSR_NEHALEM_C4_PMON_BOX_CTRL (0x00000D20)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_CTRL);
+  AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_CTRL, Msr);
+  @endcode
+  @note MSR_NEHALEM_C4_PMON_BOX_CTRL is defined as MSR_C4_PMON_BOX_CTRL in SDM.
+**/
+#define MSR_NEHALEM_C4_PMON_BOX_CTRL             0x00000D20
+
+
+/**
+  Package. Uncore C-box 4 perfmon local box status MSR.
+
+  @param  ECX  MSR_NEHALEM_C4_PMON_BOX_STATUS (0x00000D21)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_NEHALEM_C4_PMON_BOX_STATUS is defined as MSR_C4_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_NEHALEM_C4_PMON_BOX_STATUS           0x00000D21
+
+
+/**
+  Package. Uncore C-box 4 perfmon local box overflow control MSR.
+
+  @param  ECX  MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL (0x00000D22)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL);
+  AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL, Msr);
+  @endcode
+  @note MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL is defined as MSR_C4_PMON_BOX_OVF_CTRL in SDM.
+**/
+#define MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL         0x00000D22
+
+
+/**
+  Package. Uncore C-box 4 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C4_PMON_EVNT_SEL0 (0x00000D30)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL0);
+  AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL0, Msr);
+  @endcode
+  @note MSR_NEHALEM_C4_PMON_EVNT_SEL0 is defined as MSR_C4_PMON_EVNT_SEL0 in SDM.
+**/
+#define MSR_NEHALEM_C4_PMON_EVNT_SEL0            0x00000D30
+
+
+/**
+  Package. Uncore C-box 4 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C4_PMON_CTR0 (0x00000D31)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR0);
+  AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_NEHALEM_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.
+**/
+#define MSR_NEHALEM_C4_PMON_CTR0                 0x00000D31
+
+
+/**
+  Package. Uncore C-box 4 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C4_PMON_EVNT_SEL1 (0x00000D32)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL1);
+  AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL1, Msr);
+  @endcode
+  @note MSR_NEHALEM_C4_PMON_EVNT_SEL1 is defined as MSR_C4_PMON_EVNT_SEL1 in SDM.
+**/
+#define MSR_NEHALEM_C4_PMON_EVNT_SEL1            0x00000D32
+
+
+/**
+  Package. Uncore C-box 4 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C4_PMON_CTR1 (0x00000D33)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR1);
+  AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_NEHALEM_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.
+**/
+#define MSR_NEHALEM_C4_PMON_CTR1                 0x00000D33
+
+
+/**
+  Package. Uncore C-box 4 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C4_PMON_EVNT_SEL2 (0x00000D34)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL2);
+  AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL2, Msr);
+  @endcode
+  @note MSR_NEHALEM_C4_PMON_EVNT_SEL2 is defined as MSR_C4_PMON_EVNT_SEL2 in SDM.
+**/
+#define MSR_NEHALEM_C4_PMON_EVNT_SEL2            0x00000D34
+
+
+/**
+  Package. Uncore C-box 4 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C4_PMON_CTR2 (0x00000D35)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR2);
+  AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_NEHALEM_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.
+**/
+#define MSR_NEHALEM_C4_PMON_CTR2                 0x00000D35
+
+
+/**
+  Package. Uncore C-box 4 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C4_PMON_EVNT_SEL3 (0x00000D36)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL3);
+  AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL3, Msr);
+  @endcode
+  @note MSR_NEHALEM_C4_PMON_EVNT_SEL3 is defined as MSR_C4_PMON_EVNT_SEL3 in SDM.
+**/
+#define MSR_NEHALEM_C4_PMON_EVNT_SEL3            0x00000D36
+
+
+/**
+  Package. Uncore C-box 4 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C4_PMON_CTR3 (0x00000D37)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR3);
+  AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_NEHALEM_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.
+**/
+#define MSR_NEHALEM_C4_PMON_CTR3                 0x00000D37
+
+
+/**
+  Package. Uncore C-box 4 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C4_PMON_EVNT_SEL4 (0x00000D38)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL4);
+  AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL4, Msr);
+  @endcode
+  @note MSR_NEHALEM_C4_PMON_EVNT_SEL4 is defined as MSR_C4_PMON_EVNT_SEL4 in SDM.
+**/
+#define MSR_NEHALEM_C4_PMON_EVNT_SEL4            0x00000D38
+
+
+/**
+  Package. Uncore C-box 4 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C4_PMON_CTR4 (0x00000D39)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR4);
+  AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR4, Msr);
+  @endcode
+  @note MSR_NEHALEM_C4_PMON_CTR4 is defined as MSR_C4_PMON_CTR4 in SDM.
+**/
+#define MSR_NEHALEM_C4_PMON_CTR4                 0x00000D39
+
+
+/**
+  Package. Uncore C-box 4 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C4_PMON_EVNT_SEL5 (0x00000D3A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL5);
+  AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL5, Msr);
+  @endcode
+  @note MSR_NEHALEM_C4_PMON_EVNT_SEL5 is defined as MSR_C4_PMON_EVNT_SEL5 in SDM.
+**/
+#define MSR_NEHALEM_C4_PMON_EVNT_SEL5            0x00000D3A
+
+
+/**
+  Package. Uncore C-box 4 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C4_PMON_CTR5 (0x00000D3B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR5);
+  AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR5, Msr);
+  @endcode
+  @note MSR_NEHALEM_C4_PMON_CTR5 is defined as MSR_C4_PMON_CTR5 in SDM.
+**/
+#define MSR_NEHALEM_C4_PMON_CTR5                 0x00000D3B
+
+
+/**
+  Package. Uncore C-box 2 perfmon local box control MSR.
+
+  @param  ECX  MSR_NEHALEM_C2_PMON_BOX_CTRL (0x00000D40)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_CTRL);
+  AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_CTRL, Msr);
+  @endcode
+  @note MSR_NEHALEM_C2_PMON_BOX_CTRL is defined as MSR_C2_PMON_BOX_CTRL in SDM.
+**/
+#define MSR_NEHALEM_C2_PMON_BOX_CTRL             0x00000D40
+
+
+/**
+  Package. Uncore C-box 2 perfmon local box status MSR.
+
+  @param  ECX  MSR_NEHALEM_C2_PMON_BOX_STATUS (0x00000D41)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_NEHALEM_C2_PMON_BOX_STATUS is defined as MSR_C2_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_NEHALEM_C2_PMON_BOX_STATUS           0x00000D41
+
+
+/**
+  Package. Uncore C-box 2 perfmon local box overflow control MSR.
+
+  @param  ECX  MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL (0x00000D42)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL);
+  AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL, Msr);
+  @endcode
+  @note MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL is defined as MSR_C2_PMON_BOX_OVF_CTRL in SDM.
+**/
+#define MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL         0x00000D42
+
+
+/**
+  Package. Uncore C-box 2 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C2_PMON_EVNT_SEL0 (0x00000D50)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL0);
+  AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL0, Msr);
+  @endcode
+  @note MSR_NEHALEM_C2_PMON_EVNT_SEL0 is defined as MSR_C2_PMON_EVNT_SEL0 in SDM.
+**/
+#define MSR_NEHALEM_C2_PMON_EVNT_SEL0            0x00000D50
+
+
+/**
+  Package. Uncore C-box 2 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C2_PMON_CTR0 (0x00000D51)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR0);
+  AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_NEHALEM_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.
+**/
+#define MSR_NEHALEM_C2_PMON_CTR0                 0x00000D51
+
+
+/**
+  Package. Uncore C-box 2 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C2_PMON_EVNT_SEL1 (0x00000D52)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL1);
+  AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL1, Msr);
+  @endcode
+  @note MSR_NEHALEM_C2_PMON_EVNT_SEL1 is defined as MSR_C2_PMON_EVNT_SEL1 in SDM.
+**/
+#define MSR_NEHALEM_C2_PMON_EVNT_SEL1            0x00000D52
+
+
+/**
+  Package. Uncore C-box 2 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C2_PMON_CTR1 (0x00000D53)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR1);
+  AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_NEHALEM_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.
+**/
+#define MSR_NEHALEM_C2_PMON_CTR1                 0x00000D53
+
+
+/**
+  Package. Uncore C-box 2 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C2_PMON_EVNT_SEL2 (0x00000D54)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL2);
+  AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL2, Msr);
+  @endcode
+  @note MSR_NEHALEM_C2_PMON_EVNT_SEL2 is defined as MSR_C2_PMON_EVNT_SEL2 in SDM.
+**/
+#define MSR_NEHALEM_C2_PMON_EVNT_SEL2            0x00000D54
+
+
+/**
+  Package. Uncore C-box 2 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C2_PMON_CTR2 (0x00000D55)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR2);
+  AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_NEHALEM_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.
+**/
+#define MSR_NEHALEM_C2_PMON_CTR2                 0x00000D55
+
+
+/**
+  Package. Uncore C-box 2 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C2_PMON_EVNT_SEL3 (0x00000D56)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL3);
+  AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL3, Msr);
+  @endcode
+  @note MSR_NEHALEM_C2_PMON_EVNT_SEL3 is defined as MSR_C2_PMON_EVNT_SEL3 in SDM.
+**/
+#define MSR_NEHALEM_C2_PMON_EVNT_SEL3            0x00000D56
+
+
+/**
+  Package. Uncore C-box 2 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C2_PMON_CTR3 (0x00000D57)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR3);
+  AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_NEHALEM_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.
+**/
+#define MSR_NEHALEM_C2_PMON_CTR3                 0x00000D57
+
+
+/**
+  Package. Uncore C-box 2 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C2_PMON_EVNT_SEL4 (0x00000D58)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL4);
+  AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL4, Msr);
+  @endcode
+  @note MSR_NEHALEM_C2_PMON_EVNT_SEL4 is defined as MSR_C2_PMON_EVNT_SEL4 in SDM.
+**/
+#define MSR_NEHALEM_C2_PMON_EVNT_SEL4            0x00000D58
+
+
+/**
+  Package. Uncore C-box 2 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C2_PMON_CTR4 (0x00000D59)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR4);
+  AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR4, Msr);
+  @endcode
+  @note MSR_NEHALEM_C2_PMON_CTR4 is defined as MSR_C2_PMON_CTR4 in SDM.
+**/
+#define MSR_NEHALEM_C2_PMON_CTR4                 0x00000D59
+
+
+/**
+  Package. Uncore C-box 2 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C2_PMON_EVNT_SEL5 (0x00000D5A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL5);
+  AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL5, Msr);
+  @endcode
+  @note MSR_NEHALEM_C2_PMON_EVNT_SEL5 is defined as MSR_C2_PMON_EVNT_SEL5 in SDM.
+**/
+#define MSR_NEHALEM_C2_PMON_EVNT_SEL5            0x00000D5A
+
+
+/**
+  Package. Uncore C-box 2 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C2_PMON_CTR5 (0x00000D5B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR5);
+  AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR5, Msr);
+  @endcode
+  @note MSR_NEHALEM_C2_PMON_CTR5 is defined as MSR_C2_PMON_CTR5 in SDM.
+**/
+#define MSR_NEHALEM_C2_PMON_CTR5                 0x00000D5B
+
+
+/**
+  Package. Uncore C-box 6 perfmon local box control MSR.
+
+  @param  ECX  MSR_NEHALEM_C6_PMON_BOX_CTRL (0x00000D60)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_CTRL);
+  AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_CTRL, Msr);
+  @endcode
+  @note MSR_NEHALEM_C6_PMON_BOX_CTRL is defined as MSR_C6_PMON_BOX_CTRL in SDM.
+**/
+#define MSR_NEHALEM_C6_PMON_BOX_CTRL             0x00000D60
+
+
+/**
+  Package. Uncore C-box 6 perfmon local box status MSR.
+
+  @param  ECX  MSR_NEHALEM_C6_PMON_BOX_STATUS (0x00000D61)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_NEHALEM_C6_PMON_BOX_STATUS is defined as MSR_C6_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_NEHALEM_C6_PMON_BOX_STATUS           0x00000D61
+
+
+/**
+  Package. Uncore C-box 6 perfmon local box overflow control MSR.
+
+  @param  ECX  MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL (0x00000D62)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL);
+  AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL, Msr);
+  @endcode
+  @note MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL is defined as MSR_C6_PMON_BOX_OVF_CTRL in SDM.
+**/
+#define MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL         0x00000D62
+
+
+/**
+  Package. Uncore C-box 6 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C6_PMON_EVNT_SEL0 (0x00000D70)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL0);
+  AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL0, Msr);
+  @endcode
+  @note MSR_NEHALEM_C6_PMON_EVNT_SEL0 is defined as MSR_C6_PMON_EVNT_SEL0 in SDM.
+**/
+#define MSR_NEHALEM_C6_PMON_EVNT_SEL0            0x00000D70
+
+
+/**
+  Package. Uncore C-box 6 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C6_PMON_CTR0 (0x00000D71)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR0);
+  AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_NEHALEM_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.
+**/
+#define MSR_NEHALEM_C6_PMON_CTR0                 0x00000D71
+
+
+/**
+  Package. Uncore C-box 6 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C6_PMON_EVNT_SEL1 (0x00000D72)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL1);
+  AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL1, Msr);
+  @endcode
+  @note MSR_NEHALEM_C6_PMON_EVNT_SEL1 is defined as MSR_C6_PMON_EVNT_SEL1 in SDM.
+**/
+#define MSR_NEHALEM_C6_PMON_EVNT_SEL1            0x00000D72
+
+
+/**
+  Package. Uncore C-box 6 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C6_PMON_CTR1 (0x00000D73)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR1);
+  AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_NEHALEM_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.
+**/
+#define MSR_NEHALEM_C6_PMON_CTR1                 0x00000D73
+
+
+/**
+  Package. Uncore C-box 6 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C6_PMON_EVNT_SEL2 (0x00000D74)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL2);
+  AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL2, Msr);
+  @endcode
+  @note MSR_NEHALEM_C6_PMON_EVNT_SEL2 is defined as MSR_C6_PMON_EVNT_SEL2 in SDM.
+**/
+#define MSR_NEHALEM_C6_PMON_EVNT_SEL2            0x00000D74
+
+
+/**
+  Package. Uncore C-box 6 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C6_PMON_CTR2 (0x00000D75)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR2);
+  AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_NEHALEM_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.
+**/
+#define MSR_NEHALEM_C6_PMON_CTR2                 0x00000D75
+
+
+/**
+  Package. Uncore C-box 6 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C6_PMON_EVNT_SEL3 (0x00000D76)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL3);
+  AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL3, Msr);
+  @endcode
+  @note MSR_NEHALEM_C6_PMON_EVNT_SEL3 is defined as MSR_C6_PMON_EVNT_SEL3 in SDM.
+**/
+#define MSR_NEHALEM_C6_PMON_EVNT_SEL3            0x00000D76
+
+
+/**
+  Package. Uncore C-box 6 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C6_PMON_CTR3 (0x00000D77)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR3);
+  AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_NEHALEM_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.
+**/
+#define MSR_NEHALEM_C6_PMON_CTR3                 0x00000D77
+
+
+/**
+  Package. Uncore C-box 6 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C6_PMON_EVNT_SEL4 (0x00000D78)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL4);
+  AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL4, Msr);
+  @endcode
+  @note MSR_NEHALEM_C6_PMON_EVNT_SEL4 is defined as MSR_C6_PMON_EVNT_SEL4 in SDM.
+**/
+#define MSR_NEHALEM_C6_PMON_EVNT_SEL4            0x00000D78
+
+
+/**
+  Package. Uncore C-box 6 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C6_PMON_CTR4 (0x00000D79)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR4);
+  AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR4, Msr);
+  @endcode
+  @note MSR_NEHALEM_C6_PMON_CTR4 is defined as MSR_C6_PMON_CTR4 in SDM.
+**/
+#define MSR_NEHALEM_C6_PMON_CTR4                 0x00000D79
+
+
+/**
+  Package. Uncore C-box 6 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C6_PMON_EVNT_SEL5 (0x00000D7A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL5);
+  AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL5, Msr);
+  @endcode
+  @note MSR_NEHALEM_C6_PMON_EVNT_SEL5 is defined as MSR_C6_PMON_EVNT_SEL5 in SDM.
+**/
+#define MSR_NEHALEM_C6_PMON_EVNT_SEL5            0x00000D7A
+
+
+/**
+  Package. Uncore C-box 6 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C6_PMON_CTR5 (0x00000D7B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR5);
+  AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR5, Msr);
+  @endcode
+  @note MSR_NEHALEM_C6_PMON_CTR5 is defined as MSR_C6_PMON_CTR5 in SDM.
+**/
+#define MSR_NEHALEM_C6_PMON_CTR5                 0x00000D7B
+
+
+/**
+  Package. Uncore C-box 1 perfmon local box control MSR.
+
+  @param  ECX  MSR_NEHALEM_C1_PMON_BOX_CTRL (0x00000D80)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_CTRL);
+  AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_CTRL, Msr);
+  @endcode
+  @note MSR_NEHALEM_C1_PMON_BOX_CTRL is defined as MSR_C1_PMON_BOX_CTRL in SDM.
+**/
+#define MSR_NEHALEM_C1_PMON_BOX_CTRL             0x00000D80
+
+
+/**
+  Package. Uncore C-box 1 perfmon local box status MSR.
+
+  @param  ECX  MSR_NEHALEM_C1_PMON_BOX_STATUS (0x00000D81)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_NEHALEM_C1_PMON_BOX_STATUS is defined as MSR_C1_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_NEHALEM_C1_PMON_BOX_STATUS           0x00000D81
+
+
+/**
+  Package. Uncore C-box 1 perfmon local box overflow control MSR.
+
+  @param  ECX  MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL (0x00000D82)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL);
+  AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL, Msr);
+  @endcode
+  @note MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL is defined as MSR_C1_PMON_BOX_OVF_CTRL in SDM.
+**/
+#define MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL         0x00000D82
+
+
+/**
+  Package. Uncore C-box 1 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C1_PMON_EVNT_SEL0 (0x00000D90)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL0);
+  AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL0, Msr);
+  @endcode
+  @note MSR_NEHALEM_C1_PMON_EVNT_SEL0 is defined as MSR_C1_PMON_EVNT_SEL0 in SDM.
+**/
+#define MSR_NEHALEM_C1_PMON_EVNT_SEL0            0x00000D90
+
+
+/**
+  Package. Uncore C-box 1 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C1_PMON_CTR0 (0x00000D91)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR0);
+  AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_NEHALEM_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.
+**/
+#define MSR_NEHALEM_C1_PMON_CTR0                 0x00000D91
+
+
+/**
+  Package. Uncore C-box 1 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C1_PMON_EVNT_SEL1 (0x00000D92)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL1);
+  AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL1, Msr);
+  @endcode
+  @note MSR_NEHALEM_C1_PMON_EVNT_SEL1 is defined as MSR_C1_PMON_EVNT_SEL1 in SDM.
+**/
+#define MSR_NEHALEM_C1_PMON_EVNT_SEL1            0x00000D92
+
+
+/**
+  Package. Uncore C-box 1 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C1_PMON_CTR1 (0x00000D93)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR1);
+  AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_NEHALEM_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.
+**/
+#define MSR_NEHALEM_C1_PMON_CTR1                 0x00000D93
+
+
+/**
+  Package. Uncore C-box 1 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C1_PMON_EVNT_SEL2 (0x00000D94)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL2);
+  AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL2, Msr);
+  @endcode
+  @note MSR_NEHALEM_C1_PMON_EVNT_SEL2 is defined as MSR_C1_PMON_EVNT_SEL2 in SDM.
+**/
+#define MSR_NEHALEM_C1_PMON_EVNT_SEL2            0x00000D94
+
+
+/**
+  Package. Uncore C-box 1 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C1_PMON_CTR2 (0x00000D95)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR2);
+  AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_NEHALEM_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.
+**/
+#define MSR_NEHALEM_C1_PMON_CTR2                 0x00000D95
+
+
+/**
+  Package. Uncore C-box 1 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C1_PMON_EVNT_SEL3 (0x00000D96)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL3);
+  AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL3, Msr);
+  @endcode
+  @note MSR_NEHALEM_C1_PMON_EVNT_SEL3 is defined as MSR_C1_PMON_EVNT_SEL3 in SDM.
+**/
+#define MSR_NEHALEM_C1_PMON_EVNT_SEL3            0x00000D96
+
+
+/**
+  Package. Uncore C-box 1 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C1_PMON_CTR3 (0x00000D97)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR3);
+  AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_NEHALEM_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.
+**/
+#define MSR_NEHALEM_C1_PMON_CTR3                 0x00000D97
+
+
+/**
+  Package. Uncore C-box 1 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C1_PMON_EVNT_SEL4 (0x00000D98)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL4);
+  AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL4, Msr);
+  @endcode
+  @note MSR_NEHALEM_C1_PMON_EVNT_SEL4 is defined as MSR_C1_PMON_EVNT_SEL4 in SDM.
+**/
+#define MSR_NEHALEM_C1_PMON_EVNT_SEL4            0x00000D98
+
+
+/**
+  Package. Uncore C-box 1 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C1_PMON_CTR4 (0x00000D99)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR4);
+  AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR4, Msr);
+  @endcode
+  @note MSR_NEHALEM_C1_PMON_CTR4 is defined as MSR_C1_PMON_CTR4 in SDM.
+**/
+#define MSR_NEHALEM_C1_PMON_CTR4                 0x00000D99
+
+
+/**
+  Package. Uncore C-box 1 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C1_PMON_EVNT_SEL5 (0x00000D9A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL5);
+  AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL5, Msr);
+  @endcode
+  @note MSR_NEHALEM_C1_PMON_EVNT_SEL5 is defined as MSR_C1_PMON_EVNT_SEL5 in SDM.
+**/
+#define MSR_NEHALEM_C1_PMON_EVNT_SEL5            0x00000D9A
+
+
+/**
+  Package. Uncore C-box 1 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C1_PMON_CTR5 (0x00000D9B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR5);
+  AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR5, Msr);
+  @endcode
+  @note MSR_NEHALEM_C1_PMON_CTR5 is defined as MSR_C1_PMON_CTR5 in SDM.
+**/
+#define MSR_NEHALEM_C1_PMON_CTR5                 0x00000D9B
+
+
+/**
+  Package. Uncore C-box 5 perfmon local box control MSR.
+
+  @param  ECX  MSR_NEHALEM_C5_PMON_BOX_CTRL (0x00000DA0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_CTRL);
+  AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_CTRL, Msr);
+  @endcode
+  @note MSR_NEHALEM_C5_PMON_BOX_CTRL is defined as MSR_C5_PMON_BOX_CTRL in SDM.
+**/
+#define MSR_NEHALEM_C5_PMON_BOX_CTRL             0x00000DA0
+
+
+/**
+  Package. Uncore C-box 5 perfmon local box status MSR.
+
+  @param  ECX  MSR_NEHALEM_C5_PMON_BOX_STATUS (0x00000DA1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_NEHALEM_C5_PMON_BOX_STATUS is defined as MSR_C5_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_NEHALEM_C5_PMON_BOX_STATUS           0x00000DA1
+
+
+/**
+  Package. Uncore C-box 5 perfmon local box overflow control MSR.
+
+  @param  ECX  MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL (0x00000DA2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL);
+  AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL, Msr);
+  @endcode
+  @note MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL is defined as MSR_C5_PMON_BOX_OVF_CTRL in SDM.
+**/
+#define MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL         0x00000DA2
+
+
+/**
+  Package. Uncore C-box 5 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C5_PMON_EVNT_SEL0 (0x00000DB0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL0);
+  AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL0, Msr);
+  @endcode
+  @note MSR_NEHALEM_C5_PMON_EVNT_SEL0 is defined as MSR_C5_PMON_EVNT_SEL0 in SDM.
+**/
+#define MSR_NEHALEM_C5_PMON_EVNT_SEL0            0x00000DB0
+
+
+/**
+  Package. Uncore C-box 5 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C5_PMON_CTR0 (0x00000DB1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR0);
+  AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_NEHALEM_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.
+**/
+#define MSR_NEHALEM_C5_PMON_CTR0                 0x00000DB1
+
+
+/**
+  Package. Uncore C-box 5 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C5_PMON_EVNT_SEL1 (0x00000DB2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL1);
+  AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL1, Msr);
+  @endcode
+  @note MSR_NEHALEM_C5_PMON_EVNT_SEL1 is defined as MSR_C5_PMON_EVNT_SEL1 in SDM.
+**/
+#define MSR_NEHALEM_C5_PMON_EVNT_SEL1            0x00000DB2
+
+
+/**
+  Package. Uncore C-box 5 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C5_PMON_CTR1 (0x00000DB3)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR1);
+  AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_NEHALEM_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.
+**/
+#define MSR_NEHALEM_C5_PMON_CTR1                 0x00000DB3
+
+
+/**
+  Package. Uncore C-box 5 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C5_PMON_EVNT_SEL2 (0x00000DB4)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL2);
+  AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL2, Msr);
+  @endcode
+  @note MSR_NEHALEM_C5_PMON_EVNT_SEL2 is defined as MSR_C5_PMON_EVNT_SEL2 in SDM.
+**/
+#define MSR_NEHALEM_C5_PMON_EVNT_SEL2            0x00000DB4
+
+
+/**
+  Package. Uncore C-box 5 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C5_PMON_CTR2 (0x00000DB5)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR2);
+  AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_NEHALEM_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.
+**/
+#define MSR_NEHALEM_C5_PMON_CTR2                 0x00000DB5
+
+
+/**
+  Package. Uncore C-box 5 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C5_PMON_EVNT_SEL3 (0x00000DB6)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL3);
+  AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL3, Msr);
+  @endcode
+  @note MSR_NEHALEM_C5_PMON_EVNT_SEL3 is defined as MSR_C5_PMON_EVNT_SEL3 in SDM.
+**/
+#define MSR_NEHALEM_C5_PMON_EVNT_SEL3            0x00000DB6
+
+
+/**
+  Package. Uncore C-box 5 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C5_PMON_CTR3 (0x00000DB7)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR3);
+  AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_NEHALEM_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.
+**/
+#define MSR_NEHALEM_C5_PMON_CTR3                 0x00000DB7
+
+
+/**
+  Package. Uncore C-box 5 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C5_PMON_EVNT_SEL4 (0x00000DB8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL4);
+  AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL4, Msr);
+  @endcode
+  @note MSR_NEHALEM_C5_PMON_EVNT_SEL4 is defined as MSR_C5_PMON_EVNT_SEL4 in SDM.
+**/
+#define MSR_NEHALEM_C5_PMON_EVNT_SEL4            0x00000DB8
+
+
+/**
+  Package. Uncore C-box 5 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C5_PMON_CTR4 (0x00000DB9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR4);
+  AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR4, Msr);
+  @endcode
+  @note MSR_NEHALEM_C5_PMON_CTR4 is defined as MSR_C5_PMON_CTR4 in SDM.
+**/
+#define MSR_NEHALEM_C5_PMON_CTR4                 0x00000DB9
+
+
+/**
+  Package. Uncore C-box 5 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C5_PMON_EVNT_SEL5 (0x00000DBA)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL5);
+  AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL5, Msr);
+  @endcode
+  @note MSR_NEHALEM_C5_PMON_EVNT_SEL5 is defined as MSR_C5_PMON_EVNT_SEL5 in SDM.
+**/
+#define MSR_NEHALEM_C5_PMON_EVNT_SEL5            0x00000DBA
+
+
+/**
+  Package. Uncore C-box 5 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C5_PMON_CTR5 (0x00000DBB)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR5);
+  AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR5, Msr);
+  @endcode
+  @note MSR_NEHALEM_C5_PMON_CTR5 is defined as MSR_C5_PMON_CTR5 in SDM.
+**/
+#define MSR_NEHALEM_C5_PMON_CTR5                 0x00000DBB
+
+
+/**
+  Package. Uncore C-box 3 perfmon local box control MSR.
+
+  @param  ECX  MSR_NEHALEM_C3_PMON_BOX_CTRL (0x00000DC0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_CTRL);
+  AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_CTRL, Msr);
+  @endcode
+  @note MSR_NEHALEM_C3_PMON_BOX_CTRL is defined as MSR_C3_PMON_BOX_CTRL in SDM.
+**/
+#define MSR_NEHALEM_C3_PMON_BOX_CTRL             0x00000DC0
+
+
+/**
+  Package. Uncore C-box 3 perfmon local box status MSR.
+
+  @param  ECX  MSR_NEHALEM_C3_PMON_BOX_STATUS (0x00000DC1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_NEHALEM_C3_PMON_BOX_STATUS is defined as MSR_C3_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_NEHALEM_C3_PMON_BOX_STATUS           0x00000DC1
+
+
+/**
+  Package. Uncore C-box 3 perfmon local box overflow control MSR.
+
+  @param  ECX  MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL (0x00000DC2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL);
+  AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL, Msr);
+  @endcode
+  @note MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL is defined as MSR_C3_PMON_BOX_OVF_CTRL in SDM.
+**/
+#define MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL         0x00000DC2
+
+
+/**
+  Package. Uncore C-box 3 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C3_PMON_EVNT_SEL0 (0x00000DD0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL0);
+  AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL0, Msr);
+  @endcode
+  @note MSR_NEHALEM_C3_PMON_EVNT_SEL0 is defined as MSR_C3_PMON_EVNT_SEL0 in SDM.
+**/
+#define MSR_NEHALEM_C3_PMON_EVNT_SEL0            0x00000DD0
+
+
+/**
+  Package. Uncore C-box 3 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C3_PMON_CTR0 (0x00000DD1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR0);
+  AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_NEHALEM_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.
+**/
+#define MSR_NEHALEM_C3_PMON_CTR0                 0x00000DD1
+
+
+/**
+  Package. Uncore C-box 3 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C3_PMON_EVNT_SEL1 (0x00000DD2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL1);
+  AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL1, Msr);
+  @endcode
+  @note MSR_NEHALEM_C3_PMON_EVNT_SEL1 is defined as MSR_C3_PMON_EVNT_SEL1 in SDM.
+**/
+#define MSR_NEHALEM_C3_PMON_EVNT_SEL1            0x00000DD2
+
+
+/**
+  Package. Uncore C-box 3 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C3_PMON_CTR1 (0x00000DD3)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR1);
+  AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_NEHALEM_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.
+**/
+#define MSR_NEHALEM_C3_PMON_CTR1                 0x00000DD3
+
+
+/**
+  Package. Uncore C-box 3 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C3_PMON_EVNT_SEL2 (0x00000DD4)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL2);
+  AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL2, Msr);
+  @endcode
+  @note MSR_NEHALEM_C3_PMON_EVNT_SEL2 is defined as MSR_C3_PMON_EVNT_SEL2 in SDM.
+**/
+#define MSR_NEHALEM_C3_PMON_EVNT_SEL2            0x00000DD4
+
+
+/**
+  Package. Uncore C-box 3 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C3_PMON_CTR2 (0x00000DD5)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR2);
+  AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_NEHALEM_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.
+**/
+#define MSR_NEHALEM_C3_PMON_CTR2                 0x00000DD5
+
+
+/**
+  Package. Uncore C-box 3 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C3_PMON_EVNT_SEL3 (0x00000DD6)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL3);
+  AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL3, Msr);
+  @endcode
+  @note MSR_NEHALEM_C3_PMON_EVNT_SEL3 is defined as MSR_C3_PMON_EVNT_SEL3 in SDM.
+**/
+#define MSR_NEHALEM_C3_PMON_EVNT_SEL3            0x00000DD6
+
+
+/**
+  Package. Uncore C-box 3 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C3_PMON_CTR3 (0x00000DD7)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR3);
+  AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_NEHALEM_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.
+**/
+#define MSR_NEHALEM_C3_PMON_CTR3                 0x00000DD7
+
+
+/**
+  Package. Uncore C-box 3 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C3_PMON_EVNT_SEL4 (0x00000DD8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL4);
+  AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL4, Msr);
+  @endcode
+  @note MSR_NEHALEM_C3_PMON_EVNT_SEL4 is defined as MSR_C3_PMON_EVNT_SEL4 in SDM.
+**/
+#define MSR_NEHALEM_C3_PMON_EVNT_SEL4            0x00000DD8
+
+
+/**
+  Package. Uncore C-box 3 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C3_PMON_CTR4 (0x00000DD9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR4);
+  AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR4, Msr);
+  @endcode
+  @note MSR_NEHALEM_C3_PMON_CTR4 is defined as MSR_C3_PMON_CTR4 in SDM.
+**/
+#define MSR_NEHALEM_C3_PMON_CTR4                 0x00000DD9
+
+
+/**
+  Package. Uncore C-box 3 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C3_PMON_EVNT_SEL5 (0x00000DDA)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL5);
+  AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL5, Msr);
+  @endcode
+  @note MSR_NEHALEM_C3_PMON_EVNT_SEL5 is defined as MSR_C3_PMON_EVNT_SEL5 in SDM.
+**/
+#define MSR_NEHALEM_C3_PMON_EVNT_SEL5            0x00000DDA
+
+
+/**
+  Package. Uncore C-box 3 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C3_PMON_CTR5 (0x00000DDB)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR5);
+  AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR5, Msr);
+  @endcode
+  @note MSR_NEHALEM_C3_PMON_CTR5 is defined as MSR_C3_PMON_CTR5 in SDM.
+**/
+#define MSR_NEHALEM_C3_PMON_CTR5                 0x00000DDB
+
+
+/**
+  Package. Uncore C-box 7 perfmon local box control MSR.
+
+  @param  ECX  MSR_NEHALEM_C7_PMON_BOX_CTRL (0x00000DE0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_CTRL);
+  AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_CTRL, Msr);
+  @endcode
+  @note MSR_NEHALEM_C7_PMON_BOX_CTRL is defined as MSR_C7_PMON_BOX_CTRL in SDM.
+**/
+#define MSR_NEHALEM_C7_PMON_BOX_CTRL             0x00000DE0
+
+
+/**
+  Package. Uncore C-box 7 perfmon local box status MSR.
+
+  @param  ECX  MSR_NEHALEM_C7_PMON_BOX_STATUS (0x00000DE1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_NEHALEM_C7_PMON_BOX_STATUS is defined as MSR_C7_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_NEHALEM_C7_PMON_BOX_STATUS           0x00000DE1
+
+
+/**
+  Package. Uncore C-box 7 perfmon local box overflow control MSR.
+
+  @param  ECX  MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL (0x00000DE2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL);
+  AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL, Msr);
+  @endcode
+  @note MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL is defined as MSR_C7_PMON_BOX_OVF_CTRL in SDM.
+**/
+#define MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL         0x00000DE2
+
+
+/**
+  Package. Uncore C-box 7 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C7_PMON_EVNT_SEL0 (0x00000DF0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL0);
+  AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL0, Msr);
+  @endcode
+  @note MSR_NEHALEM_C7_PMON_EVNT_SEL0 is defined as MSR_C7_PMON_EVNT_SEL0 in SDM.
+**/
+#define MSR_NEHALEM_C7_PMON_EVNT_SEL0            0x00000DF0
+
+
+/**
+  Package. Uncore C-box 7 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C7_PMON_CTR0 (0x00000DF1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR0);
+  AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_NEHALEM_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.
+**/
+#define MSR_NEHALEM_C7_PMON_CTR0                 0x00000DF1
+
+
+/**
+  Package. Uncore C-box 7 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C7_PMON_EVNT_SEL1 (0x00000DF2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL1);
+  AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL1, Msr);
+  @endcode
+  @note MSR_NEHALEM_C7_PMON_EVNT_SEL1 is defined as MSR_C7_PMON_EVNT_SEL1 in SDM.
+**/
+#define MSR_NEHALEM_C7_PMON_EVNT_SEL1            0x00000DF2
+
+
+/**
+  Package. Uncore C-box 7 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C7_PMON_CTR1 (0x00000DF3)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR1);
+  AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_NEHALEM_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.
+**/
+#define MSR_NEHALEM_C7_PMON_CTR1                 0x00000DF3
+
+
+/**
+  Package. Uncore C-box 7 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C7_PMON_EVNT_SEL2 (0x00000DF4)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL2);
+  AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL2, Msr);
+  @endcode
+  @note MSR_NEHALEM_C7_PMON_EVNT_SEL2 is defined as MSR_C7_PMON_EVNT_SEL2 in SDM.
+**/
+#define MSR_NEHALEM_C7_PMON_EVNT_SEL2            0x00000DF4
+
+
+/**
+  Package. Uncore C-box 7 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C7_PMON_CTR2 (0x00000DF5)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR2);
+  AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_NEHALEM_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.
+**/
+#define MSR_NEHALEM_C7_PMON_CTR2                 0x00000DF5
+
+
+/**
+  Package. Uncore C-box 7 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C7_PMON_EVNT_SEL3 (0x00000DF6)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL3);
+  AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL3, Msr);
+  @endcode
+  @note MSR_NEHALEM_C7_PMON_EVNT_SEL3 is defined as MSR_C7_PMON_EVNT_SEL3 in SDM.
+**/
+#define MSR_NEHALEM_C7_PMON_EVNT_SEL3            0x00000DF6
+
+
+/**
+  Package. Uncore C-box 7 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C7_PMON_CTR3 (0x00000DF7)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR3);
+  AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_NEHALEM_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.
+**/
+#define MSR_NEHALEM_C7_PMON_CTR3                 0x00000DF7
+
+
+/**
+  Package. Uncore C-box 7 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C7_PMON_EVNT_SEL4 (0x00000DF8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL4);
+  AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL4, Msr);
+  @endcode
+  @note MSR_NEHALEM_C7_PMON_EVNT_SEL4 is defined as MSR_C7_PMON_EVNT_SEL4 in SDM.
+**/
+#define MSR_NEHALEM_C7_PMON_EVNT_SEL4            0x00000DF8
+
+
+/**
+  Package. Uncore C-box 7 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C7_PMON_CTR4 (0x00000DF9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR4);
+  AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR4, Msr);
+  @endcode
+  @note MSR_NEHALEM_C7_PMON_CTR4 is defined as MSR_C7_PMON_CTR4 in SDM.
+**/
+#define MSR_NEHALEM_C7_PMON_CTR4                 0x00000DF9
+
+
+/**
+  Package. Uncore C-box 7 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_C7_PMON_EVNT_SEL5 (0x00000DFA)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL5);
+  AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL5, Msr);
+  @endcode
+  @note MSR_NEHALEM_C7_PMON_EVNT_SEL5 is defined as MSR_C7_PMON_EVNT_SEL5 in SDM.
+**/
+#define MSR_NEHALEM_C7_PMON_EVNT_SEL5            0x00000DFA
+
+
+/**
+  Package. Uncore C-box 7 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_C7_PMON_CTR5 (0x00000DFB)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR5);
+  AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR5, Msr);
+  @endcode
+  @note MSR_NEHALEM_C7_PMON_CTR5 is defined as MSR_C7_PMON_CTR5 in SDM.
+**/
+#define MSR_NEHALEM_C7_PMON_CTR5                 0x00000DFB
+
+
+/**
+  Package. Uncore R-box 0 perfmon local box control MSR.
+
+  @param  ECX  MSR_NEHALEM_R0_PMON_BOX_CTRL (0x00000E00)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_CTRL);
+  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_CTRL, Msr);
+  @endcode
+  @note MSR_NEHALEM_R0_PMON_BOX_CTRL is defined as MSR_R0_PMON_BOX_CTRL in SDM.
+**/
+#define MSR_NEHALEM_R0_PMON_BOX_CTRL             0x00000E00
+
+
+/**
+  Package. Uncore R-box 0 perfmon local box status MSR.
+
+  @param  ECX  MSR_NEHALEM_R0_PMON_BOX_STATUS (0x00000E01)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_NEHALEM_R0_PMON_BOX_STATUS is defined as MSR_R0_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_NEHALEM_R0_PMON_BOX_STATUS           0x00000E01
+
+
+/**
+  Package. Uncore R-box 0 perfmon local box overflow control MSR.
+
+  @param  ECX  MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL (0x00000E02)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL);
+  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL, Msr);
+  @endcode
+  @note MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL is defined as MSR_R0_PMON_BOX_OVF_CTRL in SDM.
+**/
+#define MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL         0x00000E02
+
+
+/**
+  Package. Uncore R-box 0 perfmon IPERF0 unit Port 0 select MSR.
+
+  @param  ECX  MSR_NEHALEM_R0_PMON_IPERF0_P0 (0x00000E04)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P0);
+  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P0, Msr);
+  @endcode
+  @note MSR_NEHALEM_R0_PMON_IPERF0_P0 is defined as MSR_R0_PMON_IPERF0_P0 in SDM.
+**/
+#define MSR_NEHALEM_R0_PMON_IPERF0_P0            0x00000E04
+
+
+/**
+  Package. Uncore R-box 0 perfmon IPERF0 unit Port 1 select MSR.
+
+  @param  ECX  MSR_NEHALEM_R0_PMON_IPERF0_P1 (0x00000E05)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P1);
+  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P1, Msr);
+  @endcode
+  @note MSR_NEHALEM_R0_PMON_IPERF0_P1 is defined as MSR_R0_PMON_IPERF0_P1 in SDM.
+**/
+#define MSR_NEHALEM_R0_PMON_IPERF0_P1            0x00000E05
+
+
+/**
+  Package. Uncore R-box 0 perfmon IPERF0 unit Port 2 select MSR.
+
+  @param  ECX  MSR_NEHALEM_R0_PMON_IPERF0_P2 (0x00000E06)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P2);
+  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P2, Msr);
+  @endcode
+  @note MSR_NEHALEM_R0_PMON_IPERF0_P2 is defined as MSR_R0_PMON_IPERF0_P2 in SDM.
+**/
+#define MSR_NEHALEM_R0_PMON_IPERF0_P2            0x00000E06
+
+
+/**
+  Package. Uncore R-box 0 perfmon IPERF0 unit Port 3 select MSR.
+
+  @param  ECX  MSR_NEHALEM_R0_PMON_IPERF0_P3 (0x00000E07)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P3);
+  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P3, Msr);
+  @endcode
+  @note MSR_NEHALEM_R0_PMON_IPERF0_P3 is defined as MSR_R0_PMON_IPERF0_P3 in SDM.
+**/
+#define MSR_NEHALEM_R0_PMON_IPERF0_P3            0x00000E07
+
+
+/**
+  Package. Uncore R-box 0 perfmon IPERF0 unit Port 4 select MSR.
+
+  @param  ECX  MSR_NEHALEM_R0_PMON_IPERF0_P4 (0x00000E08)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P4);
+  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P4, Msr);
+  @endcode
+  @note MSR_NEHALEM_R0_PMON_IPERF0_P4 is defined as MSR_R0_PMON_IPERF0_P4 in SDM.
+**/
+#define MSR_NEHALEM_R0_PMON_IPERF0_P4            0x00000E08
+
+
+/**
+  Package. Uncore R-box 0 perfmon IPERF0 unit Port 5 select MSR.
+
+  @param  ECX  MSR_NEHALEM_R0_PMON_IPERF0_P5 (0x00000E09)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P5);
+  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P5, Msr);
+  @endcode
+  @note MSR_NEHALEM_R0_PMON_IPERF0_P5 is defined as MSR_R0_PMON_IPERF0_P5 in SDM.
+**/
+#define MSR_NEHALEM_R0_PMON_IPERF0_P5            0x00000E09
+
+
+/**
+  Package. Uncore R-box 0 perfmon IPERF0 unit Port 6 select MSR.
+
+  @param  ECX  MSR_NEHALEM_R0_PMON_IPERF0_P6 (0x00000E0A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P6);
+  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P6, Msr);
+  @endcode
+  @note MSR_NEHALEM_R0_PMON_IPERF0_P6 is defined as MSR_R0_PMON_IPERF0_P6 in SDM.
+**/
+#define MSR_NEHALEM_R0_PMON_IPERF0_P6            0x00000E0A
+
+
+/**
+  Package. Uncore R-box 0 perfmon IPERF0 unit Port 7 select MSR.
+
+  @param  ECX  MSR_NEHALEM_R0_PMON_IPERF0_P7 (0x00000E0B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P7);
+  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P7, Msr);
+  @endcode
+  @note MSR_NEHALEM_R0_PMON_IPERF0_P7 is defined as MSR_R0_PMON_IPERF0_P7 in SDM.
+**/
+#define MSR_NEHALEM_R0_PMON_IPERF0_P7            0x00000E0B
+
+
+/**
+  Package. Uncore R-box 0 perfmon QLX unit Port 0 select MSR.
+
+  @param  ECX  MSR_NEHALEM_R0_PMON_QLX_P0 (0x00000E0C)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P0);
+  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P0, Msr);
+  @endcode
+  @note MSR_NEHALEM_R0_PMON_QLX_P0 is defined as MSR_R0_PMON_QLX_P0 in SDM.
+**/
+#define MSR_NEHALEM_R0_PMON_QLX_P0               0x00000E0C
+
+
+/**
+  Package. Uncore R-box 0 perfmon QLX unit Port 1 select MSR.
+
+  @param  ECX  MSR_NEHALEM_R0_PMON_QLX_P1 (0x00000E0D)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P1);
+  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P1, Msr);
+  @endcode
+  @note MSR_NEHALEM_R0_PMON_QLX_P1 is defined as MSR_R0_PMON_QLX_P1 in SDM.
+**/
+#define MSR_NEHALEM_R0_PMON_QLX_P1               0x00000E0D
+
+
+/**
+  Package. Uncore R-box 0 perfmon QLX unit Port 2 select MSR.
+
+  @param  ECX  MSR_NEHALEM_R0_PMON_QLX_P2 (0x00000E0E)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P2);
+  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P2, Msr);
+  @endcode
+  @note MSR_NEHALEM_R0_PMON_QLX_P2 is defined as MSR_R0_PMON_QLX_P2 in SDM.
+**/
+#define MSR_NEHALEM_R0_PMON_QLX_P2               0x00000E0E
+
+
+/**
+  Package. Uncore R-box 0 perfmon QLX unit Port 3 select MSR.
+
+  @param  ECX  MSR_NEHALEM_R0_PMON_QLX_P3 (0x00000E0F)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P3);
+  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P3, Msr);
+  @endcode
+  @note MSR_NEHALEM_R0_PMON_QLX_P3 is defined as MSR_R0_PMON_QLX_P3 in SDM.
+**/
+#define MSR_NEHALEM_R0_PMON_QLX_P3               0x00000E0F
+
+
+/**
+  Package. Uncore R-box 0 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_R0_PMON_EVNT_SEL0 (0x00000E10)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL0);
+  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL0, Msr);
+  @endcode
+  @note MSR_NEHALEM_R0_PMON_EVNT_SEL0 is defined as MSR_R0_PMON_EVNT_SEL0 in SDM.
+**/
+#define MSR_NEHALEM_R0_PMON_EVNT_SEL0            0x00000E10
+
+
+/**
+  Package. Uncore R-box 0 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_R0_PMON_CTR0 (0x00000E11)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR0);
+  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_NEHALEM_R0_PMON_CTR0 is defined as MSR_R0_PMON_CTR0 in SDM.
+**/
+#define MSR_NEHALEM_R0_PMON_CTR0                 0x00000E11
+
+
+/**
+  Package. Uncore R-box 0 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_R0_PMON_EVNT_SEL1 (0x00000E12)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL1);
+  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL1, Msr);
+  @endcode
+  @note MSR_NEHALEM_R0_PMON_EVNT_SEL1 is defined as MSR_R0_PMON_EVNT_SEL1 in SDM.
+**/
+#define MSR_NEHALEM_R0_PMON_EVNT_SEL1            0x00000E12
+
+
+/**
+  Package. Uncore R-box 0 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_R0_PMON_CTR1 (0x00000E13)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR1);
+  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_NEHALEM_R0_PMON_CTR1 is defined as MSR_R0_PMON_CTR1 in SDM.
+**/
+#define MSR_NEHALEM_R0_PMON_CTR1                 0x00000E13
+
+
+/**
+  Package. Uncore R-box 0 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_R0_PMON_EVNT_SEL2 (0x00000E14)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL2);
+  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL2, Msr);
+  @endcode
+  @note MSR_NEHALEM_R0_PMON_EVNT_SEL2 is defined as MSR_R0_PMON_EVNT_SEL2 in SDM.
+**/
+#define MSR_NEHALEM_R0_PMON_EVNT_SEL2            0x00000E14
+
+
+/**
+  Package. Uncore R-box 0 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_R0_PMON_CTR2 (0x00000E15)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR2);
+  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_NEHALEM_R0_PMON_CTR2 is defined as MSR_R0_PMON_CTR2 in SDM.
+**/
+#define MSR_NEHALEM_R0_PMON_CTR2                 0x00000E15
+
+
+/**
+  Package. Uncore R-box 0 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_R0_PMON_EVNT_SEL3 (0x00000E16)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL3);
+  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL3, Msr);
+  @endcode
+  @note MSR_NEHALEM_R0_PMON_EVNT_SEL3 is defined as MSR_R0_PMON_EVNT_SEL3 in SDM.
+**/
+#define MSR_NEHALEM_R0_PMON_EVNT_SEL3            0x00000E16
+
+
+/**
+  Package. Uncore R-box 0 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_R0_PMON_CTR3 (0x00000E17)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR3);
+  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_NEHALEM_R0_PMON_CTR3 is defined as MSR_R0_PMON_CTR3 in SDM.
+**/
+#define MSR_NEHALEM_R0_PMON_CTR3                 0x00000E17
+
+
+/**
+  Package. Uncore R-box 0 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_R0_PMON_EVNT_SEL4 (0x00000E18)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL4);
+  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL4, Msr);
+  @endcode
+  @note MSR_NEHALEM_R0_PMON_EVNT_SEL4 is defined as MSR_R0_PMON_EVNT_SEL4 in SDM.
+**/
+#define MSR_NEHALEM_R0_PMON_EVNT_SEL4            0x00000E18
+
+
+/**
+  Package. Uncore R-box 0 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_R0_PMON_CTR4 (0x00000E19)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR4);
+  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR4, Msr);
+  @endcode
+  @note MSR_NEHALEM_R0_PMON_CTR4 is defined as MSR_R0_PMON_CTR4 in SDM.
+**/
+#define MSR_NEHALEM_R0_PMON_CTR4                 0x00000E19
+
+
+/**
+  Package. Uncore R-box 0 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_R0_PMON_EVNT_SEL5 (0x00000E1A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL5);
+  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL5, Msr);
+  @endcode
+  @note MSR_NEHALEM_R0_PMON_EVNT_SEL5 is defined as MSR_R0_PMON_EVNT_SEL5 in SDM.
+**/
+#define MSR_NEHALEM_R0_PMON_EVNT_SEL5            0x00000E1A
+
+
+/**
+  Package. Uncore R-box 0 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_R0_PMON_CTR5 (0x00000E1B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR5);
+  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR5, Msr);
+  @endcode
+  @note MSR_NEHALEM_R0_PMON_CTR5 is defined as MSR_R0_PMON_CTR5 in SDM.
+**/
+#define MSR_NEHALEM_R0_PMON_CTR5                 0x00000E1B
+
+
+/**
+  Package. Uncore R-box 0 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_R0_PMON_EVNT_SEL6 (0x00000E1C)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL6);
+  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL6, Msr);
+  @endcode
+  @note MSR_NEHALEM_R0_PMON_EVNT_SEL6 is defined as MSR_R0_PMON_EVNT_SEL6 in SDM.
+**/
+#define MSR_NEHALEM_R0_PMON_EVNT_SEL6            0x00000E1C
+
+
+/**
+  Package. Uncore R-box 0 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_R0_PMON_CTR6 (0x00000E1D)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR6);
+  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR6, Msr);
+  @endcode
+  @note MSR_NEHALEM_R0_PMON_CTR6 is defined as MSR_R0_PMON_CTR6 in SDM.
+**/
+#define MSR_NEHALEM_R0_PMON_CTR6                 0x00000E1D
+
+
+/**
+  Package. Uncore R-box 0 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_R0_PMON_EVNT_SEL7 (0x00000E1E)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL7);
+  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL7, Msr);
+  @endcode
+  @note MSR_NEHALEM_R0_PMON_EVNT_SEL7 is defined as MSR_R0_PMON_EVNT_SEL7 in SDM.
+**/
+#define MSR_NEHALEM_R0_PMON_EVNT_SEL7            0x00000E1E
+
+
+/**
+  Package. Uncore R-box 0 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_R0_PMON_CTR7 (0x00000E1F)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR7);
+  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR7, Msr);
+  @endcode
+  @note MSR_NEHALEM_R0_PMON_CTR7 is defined as MSR_R0_PMON_CTR7 in SDM.
+**/
+#define MSR_NEHALEM_R0_PMON_CTR7                 0x00000E1F
+
+
+/**
+  Package. Uncore R-box 1 perfmon local box control MSR.
+
+  @param  ECX  MSR_NEHALEM_R1_PMON_BOX_CTRL (0x00000E20)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_CTRL);
+  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_CTRL, Msr);
+  @endcode
+  @note MSR_NEHALEM_R1_PMON_BOX_CTRL is defined as MSR_R1_PMON_BOX_CTRL in SDM.
+**/
+#define MSR_NEHALEM_R1_PMON_BOX_CTRL             0x00000E20
+
+
+/**
+  Package. Uncore R-box 1 perfmon local box status MSR.
+
+  @param  ECX  MSR_NEHALEM_R1_PMON_BOX_STATUS (0x00000E21)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_NEHALEM_R1_PMON_BOX_STATUS is defined as MSR_R1_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_NEHALEM_R1_PMON_BOX_STATUS           0x00000E21
+
+
+/**
+  Package. Uncore R-box 1 perfmon local box overflow control MSR.
+
+  @param  ECX  MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL (0x00000E22)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL);
+  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL, Msr);
+  @endcode
+  @note MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL is defined as MSR_R1_PMON_BOX_OVF_CTRL in SDM.
+**/
+#define MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL         0x00000E22
+
+
+/**
+  Package. Uncore R-box 1 perfmon IPERF1 unit Port 8 select MSR.
+
+  @param  ECX  MSR_NEHALEM_R1_PMON_IPERF1_P8 (0x00000E24)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P8);
+  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P8, Msr);
+  @endcode
+  @note MSR_NEHALEM_R1_PMON_IPERF1_P8 is defined as MSR_R1_PMON_IPERF1_P8 in SDM.
+**/
+#define MSR_NEHALEM_R1_PMON_IPERF1_P8            0x00000E24
+
+
+/**
+  Package. Uncore R-box 1 perfmon IPERF1 unit Port 9 select MSR.
+
+  @param  ECX  MSR_NEHALEM_R1_PMON_IPERF1_P9 (0x00000E25)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P9);
+  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P9, Msr);
+  @endcode
+  @note MSR_NEHALEM_R1_PMON_IPERF1_P9 is defined as MSR_R1_PMON_IPERF1_P9 in SDM.
+**/
+#define MSR_NEHALEM_R1_PMON_IPERF1_P9            0x00000E25
+
+
+/**
+  Package. Uncore R-box 1 perfmon IPERF1 unit Port 10 select MSR.
+
+  @param  ECX  MSR_NEHALEM_R1_PMON_IPERF1_P10 (0x00000E26)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P10);
+  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P10, Msr);
+  @endcode
+  @note MSR_NEHALEM_R1_PMON_IPERF1_P10 is defined as MSR_R1_PMON_IPERF1_P10 in SDM.
+**/
+#define MSR_NEHALEM_R1_PMON_IPERF1_P10           0x00000E26
+
+
+/**
+  Package. Uncore R-box 1 perfmon IPERF1 unit Port 11 select MSR.
+
+  @param  ECX  MSR_NEHALEM_R1_PMON_IPERF1_P11 (0x00000E27)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P11);
+  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P11, Msr);
+  @endcode
+  @note MSR_NEHALEM_R1_PMON_IPERF1_P11 is defined as MSR_R1_PMON_IPERF1_P11 in SDM.
+**/
+#define MSR_NEHALEM_R1_PMON_IPERF1_P11           0x00000E27
+
+
+/**
+  Package. Uncore R-box 1 perfmon IPERF1 unit Port 12 select MSR.
+
+  @param  ECX  MSR_NEHALEM_R1_PMON_IPERF1_P12 (0x00000E28)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P12);
+  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P12, Msr);
+  @endcode
+  @note MSR_NEHALEM_R1_PMON_IPERF1_P12 is defined as MSR_R1_PMON_IPERF1_P12 in SDM.
+**/
+#define MSR_NEHALEM_R1_PMON_IPERF1_P12           0x00000E28
+
+
+/**
+  Package. Uncore R-box 1 perfmon IPERF1 unit Port 13 select MSR.
+
+  @param  ECX  MSR_NEHALEM_R1_PMON_IPERF1_P13 (0x00000E29)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P13);
+  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P13, Msr);
+  @endcode
+  @note MSR_NEHALEM_R1_PMON_IPERF1_P13 is defined as MSR_R1_PMON_IPERF1_P13 in SDM.
+**/
+#define MSR_NEHALEM_R1_PMON_IPERF1_P13           0x00000E29
+
+
+/**
+  Package. Uncore R-box 1 perfmon IPERF1 unit Port 14 select MSR.
+
+  @param  ECX  MSR_NEHALEM_R1_PMON_IPERF1_P14 (0x00000E2A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P14);
+  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P14, Msr);
+  @endcode
+  @note MSR_NEHALEM_R1_PMON_IPERF1_P14 is defined as MSR_R1_PMON_IPERF1_P14 in SDM.
+**/
+#define MSR_NEHALEM_R1_PMON_IPERF1_P14           0x00000E2A
+
+
+/**
+  Package. Uncore R-box 1 perfmon IPERF1 unit Port 15 select MSR.
+
+  @param  ECX  MSR_NEHALEM_R1_PMON_IPERF1_P15 (0x00000E2B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P15);
+  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P15, Msr);
+  @endcode
+  @note MSR_NEHALEM_R1_PMON_IPERF1_P15 is defined as MSR_R1_PMON_IPERF1_P15 in SDM.
+**/
+#define MSR_NEHALEM_R1_PMON_IPERF1_P15           0x00000E2B
+
+
+/**
+  Package. Uncore R-box 1 perfmon QLX unit Port 4 select MSR.
+
+  @param  ECX  MSR_NEHALEM_R1_PMON_QLX_P4 (0x00000E2C)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P4);
+  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P4, Msr);
+  @endcode
+  @note MSR_NEHALEM_R1_PMON_QLX_P4 is defined as MSR_R1_PMON_QLX_P4 in SDM.
+**/
+#define MSR_NEHALEM_R1_PMON_QLX_P4               0x00000E2C
+
+
+/**
+  Package. Uncore R-box 1 perfmon QLX unit Port 5 select MSR.
+
+  @param  ECX  MSR_NEHALEM_R1_PMON_QLX_P5 (0x00000E2D)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P5);
+  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P5, Msr);
+  @endcode
+  @note MSR_NEHALEM_R1_PMON_QLX_P5 is defined as MSR_R1_PMON_QLX_P5 in SDM.
+**/
+#define MSR_NEHALEM_R1_PMON_QLX_P5               0x00000E2D
+
+
+/**
+  Package. Uncore R-box 1 perfmon QLX unit Port 6 select MSR.
+
+  @param  ECX  MSR_NEHALEM_R1_PMON_QLX_P6 (0x00000E2E)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P6);
+  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P6, Msr);
+  @endcode
+  @note MSR_NEHALEM_R1_PMON_QLX_P6 is defined as MSR_R1_PMON_QLX_P6 in SDM.
+**/
+#define MSR_NEHALEM_R1_PMON_QLX_P6               0x00000E2E
+
+
+/**
+  Package. Uncore R-box 1 perfmon QLX unit Port 7 select MSR.
+
+  @param  ECX  MSR_NEHALEM_R1_PMON_QLX_P7 (0x00000E2F)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P7);
+  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P7, Msr);
+  @endcode
+  @note MSR_NEHALEM_R1_PMON_QLX_P7 is defined as MSR_R1_PMON_QLX_P7 in SDM.
+**/
+#define MSR_NEHALEM_R1_PMON_QLX_P7               0x00000E2F
+
+
+/**
+  Package. Uncore R-box 1 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_R1_PMON_EVNT_SEL8 (0x00000E30)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL8);
+  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL8, Msr);
+  @endcode
+  @note MSR_NEHALEM_R1_PMON_EVNT_SEL8 is defined as MSR_R1_PMON_EVNT_SEL8 in SDM.
+**/
+#define MSR_NEHALEM_R1_PMON_EVNT_SEL8            0x00000E30
+
+
+/**
+  Package. Uncore R-box 1 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_R1_PMON_CTR8 (0x00000E31)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR8);
+  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR8, Msr);
+  @endcode
+  @note MSR_NEHALEM_R1_PMON_CTR8 is defined as MSR_R1_PMON_CTR8 in SDM.
+**/
+#define MSR_NEHALEM_R1_PMON_CTR8                 0x00000E31
+
+
+/**
+  Package. Uncore R-box 1 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_R1_PMON_EVNT_SEL9 (0x00000E32)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL9);
+  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL9, Msr);
+  @endcode
+  @note MSR_NEHALEM_R1_PMON_EVNT_SEL9 is defined as MSR_R1_PMON_EVNT_SEL9 in SDM.
+**/
+#define MSR_NEHALEM_R1_PMON_EVNT_SEL9            0x00000E32
+
+
+/**
+  Package. Uncore R-box 1 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_R1_PMON_CTR9 (0x00000E33)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR9);
+  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR9, Msr);
+  @endcode
+  @note MSR_NEHALEM_R1_PMON_CTR9 is defined as MSR_R1_PMON_CTR9 in SDM.
+**/
+#define MSR_NEHALEM_R1_PMON_CTR9                 0x00000E33
+
+
+/**
+  Package. Uncore R-box 1 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_R1_PMON_EVNT_SEL10 (0x00000E34)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL10);
+  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL10, Msr);
+  @endcode
+  @note MSR_NEHALEM_R1_PMON_EVNT_SEL10 is defined as MSR_R1_PMON_EVNT_SEL10 in SDM.
+**/
+#define MSR_NEHALEM_R1_PMON_EVNT_SEL10           0x00000E34
+
+
+/**
+  Package. Uncore R-box 1 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_R1_PMON_CTR10 (0x00000E35)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR10);
+  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR10, Msr);
+  @endcode
+  @note MSR_NEHALEM_R1_PMON_CTR10 is defined as MSR_R1_PMON_CTR10 in SDM.
+**/
+#define MSR_NEHALEM_R1_PMON_CTR10                0x00000E35
+
+
+/**
+  Package. Uncore R-box 1 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_R1_PMON_EVNT_SEL11 (0x00000E36)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL11);
+  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL11, Msr);
+  @endcode
+  @note MSR_NEHALEM_R1_PMON_EVNT_SEL11 is defined as MSR_R1_PMON_EVNT_SEL11 in SDM.
+**/
+#define MSR_NEHALEM_R1_PMON_EVNT_SEL11           0x00000E36
+
+
+/**
+  Package. Uncore R-box 1 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_R1_PMON_CTR11 (0x00000E37)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR11);
+  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR11, Msr);
+  @endcode
+  @note MSR_NEHALEM_R1_PMON_CTR11 is defined as MSR_R1_PMON_CTR11 in SDM.
+**/
+#define MSR_NEHALEM_R1_PMON_CTR11                0x00000E37
+
+
+/**
+  Package. Uncore R-box 1 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_R1_PMON_EVNT_SEL12 (0x00000E38)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL12);
+  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL12, Msr);
+  @endcode
+  @note MSR_NEHALEM_R1_PMON_EVNT_SEL12 is defined as MSR_R1_PMON_EVNT_SEL12 in SDM.
+**/
+#define MSR_NEHALEM_R1_PMON_EVNT_SEL12           0x00000E38
+
+
+/**
+  Package. Uncore R-box 1 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_R1_PMON_CTR12 (0x00000E39)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR12);
+  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR12, Msr);
+  @endcode
+  @note MSR_NEHALEM_R1_PMON_CTR12 is defined as MSR_R1_PMON_CTR12 in SDM.
+**/
+#define MSR_NEHALEM_R1_PMON_CTR12                0x00000E39
+
+
+/**
+  Package. Uncore R-box 1 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_R1_PMON_EVNT_SEL13 (0x00000E3A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL13);
+  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL13, Msr);
+  @endcode
+  @note MSR_NEHALEM_R1_PMON_EVNT_SEL13 is defined as MSR_R1_PMON_EVNT_SEL13 in SDM.
+**/
+#define MSR_NEHALEM_R1_PMON_EVNT_SEL13           0x00000E3A
+
+
+/**
+  Package. Uncore R-box 1perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_R1_PMON_CTR13 (0x00000E3B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR13);
+  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR13, Msr);
+  @endcode
+  @note MSR_NEHALEM_R1_PMON_CTR13 is defined as MSR_R1_PMON_CTR13 in SDM.
+**/
+#define MSR_NEHALEM_R1_PMON_CTR13                0x00000E3B
+
+
+/**
+  Package. Uncore R-box 1 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_R1_PMON_EVNT_SEL14 (0x00000E3C)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL14);
+  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL14, Msr);
+  @endcode
+  @note MSR_NEHALEM_R1_PMON_EVNT_SEL14 is defined as MSR_R1_PMON_EVNT_SEL14 in SDM.
+**/
+#define MSR_NEHALEM_R1_PMON_EVNT_SEL14           0x00000E3C
+
+
+/**
+  Package. Uncore R-box 1 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_R1_PMON_CTR14 (0x00000E3D)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR14);
+  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR14, Msr);
+  @endcode
+  @note MSR_NEHALEM_R1_PMON_CTR14 is defined as MSR_R1_PMON_CTR14 in SDM.
+**/
+#define MSR_NEHALEM_R1_PMON_CTR14                0x00000E3D
+
+
+/**
+  Package. Uncore R-box 1 perfmon event select MSR.
+
+  @param  ECX  MSR_NEHALEM_R1_PMON_EVNT_SEL15 (0x00000E3E)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL15);
+  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL15, Msr);
+  @endcode
+  @note MSR_NEHALEM_R1_PMON_EVNT_SEL15 is defined as MSR_R1_PMON_EVNT_SEL15 in SDM.
+**/
+#define MSR_NEHALEM_R1_PMON_EVNT_SEL15           0x00000E3E
+
+
+/**
+  Package. Uncore R-box 1 perfmon counter MSR.
+
+  @param  ECX  MSR_NEHALEM_R1_PMON_CTR15 (0x00000E3F)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR15);
+  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR15, Msr);
+  @endcode
+  @note MSR_NEHALEM_R1_PMON_CTR15 is defined as MSR_R1_PMON_CTR15 in SDM.
+**/
+#define MSR_NEHALEM_R1_PMON_CTR15                0x00000E3F
+
+
+/**
+  Package. Uncore B-box 0 perfmon local box match MSR.
+
+  @param  ECX  MSR_NEHALEM_B0_PMON_MATCH (0x00000E45)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_MATCH);
+  AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_MATCH, Msr);
+  @endcode
+  @note MSR_NEHALEM_B0_PMON_MATCH is defined as MSR_B0_PMON_MATCH in SDM.
+**/
+#define MSR_NEHALEM_B0_PMON_MATCH                0x00000E45
+
+
+/**
+  Package. Uncore B-box 0 perfmon local box mask MSR.
+
+  @param  ECX  MSR_NEHALEM_B0_PMON_MASK (0x00000E46)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_MASK);
+  AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_MASK, Msr);
+  @endcode
+  @note MSR_NEHALEM_B0_PMON_MASK is defined as MSR_B0_PMON_MASK in SDM.
+**/
+#define MSR_NEHALEM_B0_PMON_MASK                 0x00000E46
+
+
+/**
+  Package. Uncore S-box 0 perfmon local box match MSR.
+
+  @param  ECX  MSR_NEHALEM_S0_PMON_MATCH (0x00000E49)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_MATCH);
+  AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_MATCH, Msr);
+  @endcode
+  @note MSR_NEHALEM_S0_PMON_MATCH is defined as MSR_S0_PMON_MATCH in SDM.
+**/
+#define MSR_NEHALEM_S0_PMON_MATCH                0x00000E49
+
+
+/**
+  Package. Uncore S-box 0 perfmon local box mask MSR.
+
+  @param  ECX  MSR_NEHALEM_S0_PMON_MASK (0x00000E4A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_MASK);
+  AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_MASK, Msr);
+  @endcode
+  @note MSR_NEHALEM_S0_PMON_MASK is defined as MSR_S0_PMON_MASK in SDM.
+**/
+#define MSR_NEHALEM_S0_PMON_MASK                 0x00000E4A
+
+
+/**
+  Package. Uncore B-box 1 perfmon local box match MSR.
+
+  @param  ECX  MSR_NEHALEM_B1_PMON_MATCH (0x00000E4D)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_MATCH);
+  AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_MATCH, Msr);
+  @endcode
+  @note MSR_NEHALEM_B1_PMON_MATCH is defined as MSR_B1_PMON_MATCH in SDM.
+**/
+#define MSR_NEHALEM_B1_PMON_MATCH                0x00000E4D
+
+
+/**
+  Package. Uncore B-box 1 perfmon local box mask MSR.
+
+  @param  ECX  MSR_NEHALEM_B1_PMON_MASK (0x00000E4E)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_MASK);
+  AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_MASK, Msr);
+  @endcode
+  @note MSR_NEHALEM_B1_PMON_MASK is defined as MSR_B1_PMON_MASK in SDM.
+**/
+#define MSR_NEHALEM_B1_PMON_MASK                 0x00000E4E
+
+
+/**
+  Package. Uncore M-box 0 perfmon local box address match/mask config MSR.
+
+  @param  ECX  MSR_NEHALEM_M0_PMON_MM_CONFIG (0x00000E54)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MM_CONFIG);
+  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MM_CONFIG, Msr);
+  @endcode
+  @note MSR_NEHALEM_M0_PMON_MM_CONFIG is defined as MSR_M0_PMON_MM_CONFIG in SDM.
+**/
+#define MSR_NEHALEM_M0_PMON_MM_CONFIG            0x00000E54
+
+
+/**
+  Package. Uncore M-box 0 perfmon local box address match MSR.
+
+  @param  ECX  MSR_NEHALEM_M0_PMON_ADDR_MATCH (0x00000E55)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MATCH);
+  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MATCH, Msr);
+  @endcode
+  @note MSR_NEHALEM_M0_PMON_ADDR_MATCH is defined as MSR_M0_PMON_ADDR_MATCH in SDM.
+**/
+#define MSR_NEHALEM_M0_PMON_ADDR_MATCH           0x00000E55
+
+
+/**
+  Package. Uncore M-box 0 perfmon local box address mask MSR.
+
+  @param  ECX  MSR_NEHALEM_M0_PMON_ADDR_MASK (0x00000E56)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MASK);
+  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MASK, Msr);
+  @endcode
+  @note MSR_NEHALEM_M0_PMON_ADDR_MASK is defined as MSR_M0_PMON_ADDR_MASK in SDM.
+**/
+#define MSR_NEHALEM_M0_PMON_ADDR_MASK            0x00000E56
+
+
+/**
+  Package. Uncore S-box 1 perfmon local box match MSR.
+
+  @param  ECX  MSR_NEHALEM_S1_PMON_MATCH (0x00000E59)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_MATCH);
+  AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_MATCH, Msr);
+  @endcode
+  @note MSR_NEHALEM_S1_PMON_MATCH is defined as MSR_S1_PMON_MATCH in SDM.
+**/
+#define MSR_NEHALEM_S1_PMON_MATCH                0x00000E59
+
+
+/**
+  Package. Uncore S-box 1 perfmon local box mask MSR.
+
+  @param  ECX  MSR_NEHALEM_S1_PMON_MASK (0x00000E5A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_MASK);
+  AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_MASK, Msr);
+  @endcode
+  @note MSR_NEHALEM_S1_PMON_MASK is defined as MSR_S1_PMON_MASK in SDM.
+**/
+#define MSR_NEHALEM_S1_PMON_MASK                 0x00000E5A
+
+
+/**
+  Package. Uncore M-box 1 perfmon local box address match/mask config MSR.
+
+  @param  ECX  MSR_NEHALEM_M1_PMON_MM_CONFIG (0x00000E5C)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MM_CONFIG);
+  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MM_CONFIG, Msr);
+  @endcode
+  @note MSR_NEHALEM_M1_PMON_MM_CONFIG is defined as MSR_M1_PMON_MM_CONFIG in SDM.
+**/
+#define MSR_NEHALEM_M1_PMON_MM_CONFIG            0x00000E5C
+
+
+/**
+  Package. Uncore M-box 1 perfmon local box address match MSR.
+
+  @param  ECX  MSR_NEHALEM_M1_PMON_ADDR_MATCH (0x00000E5D)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MATCH);
+  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MATCH, Msr);
+  @endcode
+  @note MSR_NEHALEM_M1_PMON_ADDR_MATCH is defined as MSR_M1_PMON_ADDR_MATCH in SDM.
+**/
+#define MSR_NEHALEM_M1_PMON_ADDR_MATCH           0x00000E5D
+
+
+/**
+  Package. Uncore M-box 1 perfmon local box address mask MSR.
+
+  @param  ECX  MSR_NEHALEM_M1_PMON_ADDR_MASK (0x00000E5E)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MASK);
+  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MASK, Msr);
+  @endcode
+  @note MSR_NEHALEM_M1_PMON_ADDR_MASK is defined as MSR_M1_PMON_ADDR_MASK in SDM.
+**/
+#define MSR_NEHALEM_M1_PMON_ADDR_MASK            0x00000E5E
+
+#endif
diff --git a/MdePkg/Include/Register/Intel/Msr/P6Msr.h b/MdePkg/Include/Register/Intel/Msr/P6Msr.h
new file mode 100644
index 000000000000..db5396f74c24
--- /dev/null
+++ b/MdePkg/Include/Register/Intel/Msr/P6Msr.h
@@ -0,0 +1,1658 @@
+/** @file
+  MSR Definitions for P6 Family Processors.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+  May 2018, Volume 4: Model-Specific-Registers (MSR)
+
+**/
+
+#ifndef __P6_MSR_H__
+#define __P6_MSR_H__
+
+#include <Register/Intel/ArchitecturalMsr.h>
+
+/**
+  Is P6 Family Processors?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_P6_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (                        \
+    DisplayModel == 0x03 || \
+    DisplayModel == 0x05 || \
+    DisplayModel == 0x07 || \
+    DisplayModel == 0x08 || \
+    DisplayModel == 0x0A || \
+    DisplayModel == 0x0B \
+    ) \
+   )
+
+/**
+  See Section 2.22, "MSRs in Pentium Processors.".
+
+  @param  ECX  MSR_P6_P5_MC_ADDR (0x00000000)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_P5_MC_ADDR);
+  AsmWriteMsr64 (MSR_P6_P5_MC_ADDR, Msr);
+  @endcode
+  @note MSR_P6_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.
+**/
+#define MSR_P6_P5_MC_ADDR                        0x00000000
+
+
+/**
+  See Section 2.22, "MSRs in Pentium Processors.".
+
+  @param  ECX  MSR_P6_P5_MC_TYPE (0x00000001)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_P5_MC_TYPE);
+  AsmWriteMsr64 (MSR_P6_P5_MC_TYPE, Msr);
+  @endcode
+  @note MSR_P6_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.
+**/
+#define MSR_P6_P5_MC_TYPE                        0x00000001
+
+
+/**
+  See Section 17.17, "Time-Stamp Counter.".
+
+  @param  ECX  MSR_P6_TSC (0x00000010)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_TSC);
+  AsmWriteMsr64 (MSR_P6_TSC, Msr);
+  @endcode
+  @note MSR_P6_TSC is defined as TSC in SDM.
+**/
+#define MSR_P6_TSC                               0x00000010
+
+
+/**
+  Platform ID (R)  The operating system can use this MSR to determine "slot"
+  information for the processor and the proper microcode update to load.
+
+  @param  ECX  MSR_P6_IA32_PLATFORM_ID (0x00000017)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_P6_IA32_PLATFORM_ID_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_P6_IA32_PLATFORM_ID_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_P6_IA32_PLATFORM_ID_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_P6_IA32_PLATFORM_ID);
+  @endcode
+  @note MSR_P6_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM.
+**/
+#define MSR_P6_IA32_PLATFORM_ID                  0x00000017
+
+/**
+  MSR information returned for MSR index #MSR_P6_IA32_PLATFORM_ID
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:32;
+    UINT32  Reserved2:18;
+    ///
+    /// [Bits 52:50] Platform Id (R) Contains information concerning the
+    /// intended platform for the processor.
+    ///
+    ///  52 51 50
+    ///   0  0  0  Processor Flag 0.
+    ///   0  0  1  Processor Flag 1
+    ///   0  1  0  Processor Flag 2
+    ///   0  1  1  Processor Flag 3
+    ///   1  0  0  Processor Flag 4
+    ///   1  0  1  Processor Flag 5
+    ///   1  1  0  Processor Flag 6
+    ///   1  1  1  Processor Flag 7
+    ///
+    UINT32  PlatformId:3;
+    ///
+    /// [Bits 56:53] L2 Cache Latency Read.
+    ///
+    UINT32  L2CacheLatencyRead:4;
+    UINT32  Reserved3:3;
+    ///
+    /// [Bit 60] Clock Frequency Ratio Read.
+    ///
+    UINT32  ClockFrequencyRatioRead:1;
+    UINT32  Reserved4:3;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_P6_IA32_PLATFORM_ID_REGISTER;
+
+
+/**
+  Section 10.4.4, "Local APIC Status and Location.".
+
+  @param  ECX  MSR_P6_APIC_BASE (0x0000001B)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_P6_APIC_BASE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_P6_APIC_BASE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_P6_APIC_BASE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_P6_APIC_BASE);
+  AsmWriteMsr64 (MSR_P6_APIC_BASE, Msr.Uint64);
+  @endcode
+  @note MSR_P6_APIC_BASE is defined as APIC_BASE in SDM.
+**/
+#define MSR_P6_APIC_BASE                         0x0000001B
+
+/**
+  MSR information returned for MSR index #MSR_P6_APIC_BASE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:8;
+    ///
+    /// [Bit 8] Boot Strap Processor indicator Bit 1 = BSP.
+    ///
+    UINT32  BSP:1;
+    UINT32  Reserved2:2;
+    ///
+    /// [Bit 11] APIC Global Enable Bit - Permanent till reset 1 = Enabled 0 =
+    /// Disabled.
+    ///
+    UINT32  EN:1;
+    ///
+    /// [Bits 31:12] APIC Base Address.
+    ///
+    UINT32  ApicBase:20;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_P6_APIC_BASE_REGISTER;
+
+
+/**
+  Processor Hard Power-On Configuration (R/W) Enables and disables processor
+  features; (R) indicates current processor configuration.
+
+  @param  ECX  MSR_P6_EBL_CR_POWERON (0x0000002A)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_P6_EBL_CR_POWERON_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_P6_EBL_CR_POWERON_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_P6_EBL_CR_POWERON_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_P6_EBL_CR_POWERON);
+  AsmWriteMsr64 (MSR_P6_EBL_CR_POWERON, Msr.Uint64);
+  @endcode
+  @note MSR_P6_EBL_CR_POWERON is defined as EBL_CR_POWERON in SDM.
+**/
+#define MSR_P6_EBL_CR_POWERON                    0x0000002A
+
+/**
+  MSR information returned for MSR index #MSR_P6_EBL_CR_POWERON
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled 0 = Disabled.
+    ///
+    UINT32  DataErrorCheckingEnable:1;
+    ///
+    /// [Bit 2] Response Error Checking Enable FRCERR Observation Enable (R/W)
+    /// 1 = Enabled 0 = Disabled.
+    ///
+    UINT32  ResponseErrorCheckingEnable:1;
+    ///
+    /// [Bit 3] AERR# Drive Enable (R/W) 1 = Enabled 0 = Disabled.
+    ///
+    UINT32  AERR_DriveEnable:1;
+    ///
+    /// [Bit 4] BERR# Enable for Initiator Bus Requests (R/W) 1 = Enabled 0 =
+    /// Disabled.
+    ///
+    UINT32  BERR_Enable:1;
+    UINT32  Reserved2:1;
+    ///
+    /// [Bit 6] BERR# Driver Enable for Initiator Internal Errors (R/W) 1 =
+    /// Enabled 0 = Disabled.
+    ///
+    UINT32  BERR_DriverEnable:1;
+    ///
+    /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled 0 = Disabled.
+    ///
+    UINT32  BINIT_DriverEnable:1;
+    ///
+    /// [Bit 8] Output Tri-state Enabled (R) 1 = Enabled 0 = Disabled.
+    ///
+    UINT32  OutputTriStateEnable:1;
+    ///
+    /// [Bit 9] Execute BIST (R) 1 = Enabled 0 = Disabled.
+    ///
+    UINT32  ExecuteBIST:1;
+    ///
+    /// [Bit 10] AERR# Observation Enabled (R) 1 = Enabled 0 = Disabled.
+    ///
+    UINT32  AERR_ObservationEnabled:1;
+    UINT32  Reserved3:1;
+    ///
+    /// [Bit 12] BINIT# Observation Enabled (R) 1 = Enabled 0 = Disabled.
+    ///
+    UINT32  BINIT_ObservationEnabled:1;
+    ///
+    /// [Bit 13] In Order Queue Depth (R) 1 = 1 0 = 8.
+    ///
+    UINT32  InOrderQueueDepth:1;
+    ///
+    /// [Bit 14] 1-MByte Power on Reset Vector (R) 1 = 1MByte 0 = 4GBytes.
+    ///
+    UINT32  ResetVector:1;
+    ///
+    /// [Bit 15] FRC Mode Enable (R) 1 = Enabled 0 = Disabled.
+    ///
+    UINT32  FRCModeEnable:1;
+    ///
+    /// [Bits 17:16] APIC Cluster ID (R).
+    ///
+    UINT32  APICClusterID:2;
+    ///
+    /// [Bits 19:18] System Bus Frequency (R) 00 = 66MHz 10 = 100Mhz 01 =
+    /// 133MHz 11 = Reserved.
+    ///
+    UINT32  SystemBusFrequency:2;
+    ///
+    /// [Bits 21:20] Symmetric Arbitration ID (R).
+    ///
+    UINT32  SymmetricArbitrationID:2;
+    ///
+    /// [Bits 25:22] Clock Frequency Ratio (R).
+    ///
+    UINT32  ClockFrequencyRatio:4;
+    ///
+    /// [Bit 26] Low Power Mode Enable (R/W).
+    ///
+    UINT32  LowPowerModeEnable:1;
+    ///
+    /// [Bit 27] Clock Frequency Ratio.
+    ///
+    UINT32  ClockFrequencyRatio1:1;
+    UINT32  Reserved4:4;
+    UINT32  Reserved5:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_P6_EBL_CR_POWERON_REGISTER;
+
+
+/**
+  Test Control Register.
+
+  @param  ECX  MSR_P6_TEST_CTL (0x00000033)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_P6_TEST_CTL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_P6_TEST_CTL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_P6_TEST_CTL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_P6_TEST_CTL);
+  AsmWriteMsr64 (MSR_P6_TEST_CTL, Msr.Uint64);
+  @endcode
+  @note MSR_P6_TEST_CTL is defined as TEST_CTL in SDM.
+**/
+#define MSR_P6_TEST_CTL                          0x00000033
+
+/**
+  MSR information returned for MSR index #MSR_P6_TEST_CTL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:30;
+    ///
+    /// [Bit 30] Streaming Buffer Disable.
+    ///
+    UINT32  StreamingBufferDisable:1;
+    ///
+    /// [Bit 31] Disable LOCK# Assertion for split locked access.
+    ///
+    UINT32  Disable_LOCK:1;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_P6_TEST_CTL_REGISTER;
+
+
+/**
+  BIOS Update Trigger Register.
+
+  @param  ECX  MSR_P6_BIOS_UPDT_TRIG (0x00000079)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_BIOS_UPDT_TRIG);
+  AsmWriteMsr64 (MSR_P6_BIOS_UPDT_TRIG, Msr);
+  @endcode
+  @note MSR_P6_BIOS_UPDT_TRIG is defined as BIOS_UPDT_TRIG in SDM.
+**/
+#define MSR_P6_BIOS_UPDT_TRIG                    0x00000079
+
+
+/**
+  Chunk n data register D[63:0]: used to write to and read from the L2.
+
+  @param  ECX  MSR_P6_BBL_CR_Dn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_BBL_CR_D0);
+  AsmWriteMsr64 (MSR_P6_BBL_CR_D0, Msr);
+  @endcode
+  @note MSR_P6_BBL_CR_D0 is defined as BBL_CR_D0 in SDM.
+        MSR_P6_BBL_CR_D1 is defined as BBL_CR_D1 in SDM.
+        MSR_P6_BBL_CR_D2 is defined as BBL_CR_D2 in SDM.
+  @{
+**/
+#define MSR_P6_BBL_CR_D0                         0x00000088
+#define MSR_P6_BBL_CR_D1                         0x00000089
+#define MSR_P6_BBL_CR_D2                         0x0000008A
+/// @}
+
+
+/**
+  BIOS Update Signature Register or Chunk 3 data register D[63:0] Used to
+  write to and read from the L2 depending on the usage model.
+
+  @param  ECX  MSR_P6_BIOS_SIGN (0x0000008B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_BIOS_SIGN);
+  AsmWriteMsr64 (MSR_P6_BIOS_SIGN, Msr);
+  @endcode
+  @note MSR_P6_BIOS_SIGN is defined as BIOS_SIGN in SDM.
+**/
+#define MSR_P6_BIOS_SIGN                         0x0000008B
+
+
+/**
+
+
+  @param  ECX  MSR_P6_PERFCTR0 (0x000000C1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_PERFCTR0);
+  AsmWriteMsr64 (MSR_P6_PERFCTR0, Msr);
+  @endcode
+  @note MSR_P6_PERFCTR0 is defined as PERFCTR0 in SDM.
+        MSR_P6_PERFCTR1 is defined as PERFCTR1 in SDM.
+  @{
+**/
+#define MSR_P6_PERFCTR0                          0x000000C1
+#define MSR_P6_PERFCTR1                          0x000000C2
+/// @}
+
+
+/**
+
+
+  @param  ECX  MSR_P6_MTRRCAP (0x000000FE)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_MTRRCAP);
+  AsmWriteMsr64 (MSR_P6_MTRRCAP, Msr);
+  @endcode
+  @note MSR_P6_MTRRCAP is defined as MTRRCAP in SDM.
+**/
+#define MSR_P6_MTRRCAP                           0x000000FE
+
+
+/**
+  Address register: used to send specified address (A31-A3) to L2 during cache
+  initialization accesses.
+
+  @param  ECX  MSR_P6_BBL_CR_ADDR (0x00000116)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_P6_BBL_CR_ADDR_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_P6_BBL_CR_ADDR_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_P6_BBL_CR_ADDR_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_ADDR);
+  AsmWriteMsr64 (MSR_P6_BBL_CR_ADDR, Msr.Uint64);
+  @endcode
+  @note MSR_P6_BBL_CR_ADDR is defined as BBL_CR_ADDR in SDM.
+**/
+#define MSR_P6_BBL_CR_ADDR                       0x00000116
+
+/**
+  MSR information returned for MSR index #MSR_P6_BBL_CR_ADDR
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:3;
+    ///
+    /// [Bits 31:3] Address bits
+    ///
+    UINT32  Address:29;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_P6_BBL_CR_ADDR_REGISTER;
+
+
+/**
+  Data ECC register D[7:0]: used to write ECC and read ECC to/from L2.
+
+  @param  ECX  MSR_P6_BBL_CR_DECC (0x00000118)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_BBL_CR_DECC);
+  AsmWriteMsr64 (MSR_P6_BBL_CR_DECC, Msr);
+  @endcode
+  @note MSR_P6_BBL_CR_DECC is defined as BBL_CR_DECC in SDM.
+**/
+#define MSR_P6_BBL_CR_DECC                       0x00000118
+
+
+/**
+  Control register: used to program L2 commands to be issued via cache
+  configuration accesses mechanism. Also receives L2 lookup response.
+
+  @param  ECX  MSR_P6_BBL_CR_CTL (0x00000119)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_P6_BBL_CR_CTL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_P6_BBL_CR_CTL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_P6_BBL_CR_CTL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_CTL);
+  AsmWriteMsr64 (MSR_P6_BBL_CR_CTL, Msr.Uint64);
+  @endcode
+  @note MSR_P6_BBL_CR_CTL is defined as BBL_CR_CTL in SDM.
+**/
+#define MSR_P6_BBL_CR_CTL                        0x00000119
+
+/**
+  MSR information returned for MSR index #MSR_P6_BBL_CR_CTL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 4:0] L2 Command
+    ///   Data Read w/ LRU update (RLU)
+    ///   Tag Read w/ Data Read (TRR)
+    ///   Tag Inquire (TI)
+    ///   L2 Control Register Read (CR)
+    ///   L2 Control Register Write (CW)
+    ///   Tag Write w/ Data Read (TWR)
+    ///   Tag Write w/ Data Write (TWW)
+    ///   Tag Write (TW).
+    ///
+    UINT32  L2Command:5;
+    ///
+    /// [Bits 6:5] State to L2
+    ///
+    UINT32  StateToL2:2;
+    UINT32  Reserved:1;
+    ///
+    /// [Bits 9:8] Way to L2.
+    ///
+    UINT32  WayToL2:2;
+    ///
+    /// [Bits 11:10] Way 0 - 00, Way 1 - 01, Way 2 - 10, Way 3 - 11.
+    ///
+    UINT32  Way:2;
+    ///
+    /// [Bits 13:12] Modified - 11,Exclusive - 10, Shared - 01, Invalid - 00.
+    ///
+    UINT32  MESI:2;
+    ///
+    /// [Bits 15:14] State from L2.
+    ///
+    UINT32  StateFromL2:2;
+    UINT32  Reserved2:1;
+    ///
+    /// [Bit 17] L2 Hit.
+    ///
+    UINT32  L2Hit:1;
+    UINT32  Reserved3:1;
+    ///
+    /// [Bits 20:19] User supplied ECC.
+    ///
+    UINT32  UserEcc:2;
+    ///
+    /// [Bit 21] Processor number Disable = 1 Enable = 0 Reserved.
+    ///
+    UINT32  ProcessorNumber:1;
+    UINT32  Reserved4:10;
+    UINT32  Reserved5:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_P6_BBL_CR_CTL_REGISTER;
+
+
+/**
+  Trigger register: used to initiate a cache configuration accesses access,
+  Write only with Data = 0.
+
+  @param  ECX  MSR_P6_BBL_CR_TRIG (0x0000011A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_BBL_CR_TRIG);
+  AsmWriteMsr64 (MSR_P6_BBL_CR_TRIG, Msr);
+  @endcode
+  @note MSR_P6_BBL_CR_TRIG is defined as BBL_CR_TRIG in SDM.
+**/
+#define MSR_P6_BBL_CR_TRIG                       0x0000011A
+
+
+/**
+  Busy register: indicates when a cache configuration accesses L2 command is
+  in progress. D[0] = 1 = BUSY.
+
+  @param  ECX  MSR_P6_BBL_CR_BUSY (0x0000011B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_BBL_CR_BUSY);
+  AsmWriteMsr64 (MSR_P6_BBL_CR_BUSY, Msr);
+  @endcode
+  @note MSR_P6_BBL_CR_BUSY is defined as BBL_CR_BUSY in SDM.
+**/
+#define MSR_P6_BBL_CR_BUSY                       0x0000011B
+
+
+/**
+  Control register 3: used to configure the L2 Cache.
+
+  @param  ECX  MSR_P6_BBL_CR_CTL3 (0x0000011E)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_P6_BBL_CR_CTL3_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_P6_BBL_CR_CTL3_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_P6_BBL_CR_CTL3_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_P6_BBL_CR_CTL3);
+  AsmWriteMsr64 (MSR_P6_BBL_CR_CTL3, Msr.Uint64);
+  @endcode
+  @note MSR_P6_BBL_CR_CTL3 is defined as BBL_CR_CTL3 in SDM.
+**/
+#define MSR_P6_BBL_CR_CTL3                       0x0000011E
+
+/**
+  MSR information returned for MSR index #MSR_P6_BBL_CR_CTL3
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] L2 Configured (read/write ).
+    ///
+    UINT32  L2Configured:1;
+    ///
+    /// [Bits 4:1] L2 Cache Latency (read/write).
+    ///
+    UINT32  L2CacheLatency:4;
+    ///
+    /// [Bit 5] ECC Check Enable (read/write).
+    ///
+    UINT32  ECCCheckEnable:1;
+    ///
+    /// [Bit 6] Address Parity Check Enable (read/write).
+    ///
+    UINT32  AddressParityCheckEnable:1;
+    ///
+    /// [Bit 7] CRTN Parity Check Enable (read/write).
+    ///
+    UINT32  CRTNParityCheckEnable:1;
+    ///
+    /// [Bit 8] L2 Enabled (read/write).
+    ///
+    UINT32  L2Enabled:1;
+    ///
+    /// [Bits 10:9] L2 Associativity (read only) Direct Mapped 2 Way 4 Way
+    /// Reserved.
+    ///
+    UINT32  L2Associativity:2;
+    ///
+    /// [Bits 12:11] Number of L2 banks (read only).
+    ///
+    UINT32  L2Banks:2;
+    ///
+    /// [Bits 17:13] Cache size per bank (read/write) 256KBytes 512KBytes
+    /// 1MByte 2MByte 4MBytes.
+    ///
+    UINT32  CacheSizePerBank:5;
+    ///
+    /// [Bit 18] Cache State error checking enable (read/write).
+    ///
+    UINT32  CacheStateErrorEnable:1;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bits 22:20] L2 Physical Address Range support 64GBytes 32GBytes
+    /// 16GBytes 8GBytes 4GBytes 2GBytes 1GBytes 512MBytes.
+    ///
+    UINT32  L2AddressRange:3;
+    ///
+    /// [Bit 23] L2 Hardware Disable (read only).
+    ///
+    UINT32  L2HardwareDisable:1;
+    UINT32  Reserved2:1;
+    ///
+    /// [Bit 25] Cache bus fraction (read only).
+    ///
+    UINT32  CacheBusFraction:1;
+    UINT32  Reserved3:6;
+    UINT32  Reserved4:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_P6_BBL_CR_CTL3_REGISTER;
+
+
+/**
+  CS register target for CPL 0 code.
+
+  @param  ECX  MSR_P6_SYSENTER_CS_MSR (0x00000174)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_SYSENTER_CS_MSR);
+  AsmWriteMsr64 (MSR_P6_SYSENTER_CS_MSR, Msr);
+  @endcode
+  @note MSR_P6_SYSENTER_CS_MSR is defined as SYSENTER_CS_MSR in SDM.
+**/
+#define MSR_P6_SYSENTER_CS_MSR                   0x00000174
+
+
+/**
+  Stack pointer for CPL 0 stack.
+
+  @param  ECX  MSR_P6_SYSENTER_ESP_MSR (0x00000175)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_SYSENTER_ESP_MSR);
+  AsmWriteMsr64 (MSR_P6_SYSENTER_ESP_MSR, Msr);
+  @endcode
+  @note MSR_P6_SYSENTER_ESP_MSR is defined as SYSENTER_ESP_MSR in SDM.
+**/
+#define MSR_P6_SYSENTER_ESP_MSR                  0x00000175
+
+
+/**
+  CPL 0 code entry point.
+
+  @param  ECX  MSR_P6_SYSENTER_EIP_MSR (0x00000176)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_SYSENTER_EIP_MSR);
+  AsmWriteMsr64 (MSR_P6_SYSENTER_EIP_MSR, Msr);
+  @endcode
+  @note MSR_P6_SYSENTER_EIP_MSR is defined as SYSENTER_EIP_MSR in SDM.
+**/
+#define MSR_P6_SYSENTER_EIP_MSR                  0x00000176
+
+
+/**
+
+
+  @param  ECX  MSR_P6_MCG_CAP (0x00000179)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_MCG_CAP);
+  AsmWriteMsr64 (MSR_P6_MCG_CAP, Msr);
+  @endcode
+  @note MSR_P6_MCG_CAP is defined as MCG_CAP in SDM.
+**/
+#define MSR_P6_MCG_CAP                           0x00000179
+
+
+/**
+
+
+  @param  ECX  MSR_P6_MCG_STATUS (0x0000017A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_MCG_STATUS);
+  AsmWriteMsr64 (MSR_P6_MCG_STATUS, Msr);
+  @endcode
+  @note MSR_P6_MCG_STATUS is defined as MCG_STATUS in SDM.
+**/
+#define MSR_P6_MCG_STATUS                        0x0000017A
+
+
+/**
+
+
+  @param  ECX  MSR_P6_MCG_CTL (0x0000017B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_MCG_CTL);
+  AsmWriteMsr64 (MSR_P6_MCG_CTL, Msr);
+  @endcode
+  @note MSR_P6_MCG_CTL is defined as MCG_CTL in SDM.
+**/
+#define MSR_P6_MCG_CTL                           0x0000017B
+
+
+/**
+
+
+  @param  ECX  MSR_P6_PERFEVTSELn
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_P6_PERFEVTSEL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_P6_PERFEVTSEL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_P6_PERFEVTSEL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_P6_PERFEVTSEL0);
+  AsmWriteMsr64 (MSR_P6_PERFEVTSEL0, Msr.Uint64);
+  @endcode
+  @note MSR_P6_PERFEVTSEL0 is defined as PERFEVTSEL0 in SDM.
+        MSR_P6_PERFEVTSEL1 is defined as PERFEVTSEL1 in SDM.
+  @{
+**/
+#define MSR_P6_PERFEVTSEL0                       0x00000186
+#define MSR_P6_PERFEVTSEL1                       0x00000187
+/// @}
+
+/**
+  MSR information returned for MSR indexes #MSR_P6_PERFEVTSEL0 and
+  #MSR_P6_PERFEVTSEL1.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Event Select Refer to Performance Counter section for a
+    /// list of event encodings.
+    ///
+    UINT32  EventSelect:8;
+    ///
+    /// [Bits 15:8] UMASK (Unit Mask) Unit mask register set to 0 to enable
+    /// all count options.
+    ///
+    UINT32  UMASK:8;
+    ///
+    /// [Bit 16] USER Controls the counting of events at Privilege levels of
+    /// 1, 2, and 3.
+    ///
+    UINT32  USR:1;
+    ///
+    /// [Bit 17] OS Controls the counting of events at Privilege level of 0.
+    ///
+    UINT32  OS:1;
+    ///
+    /// [Bit 18] E Occurrence/Duration Mode Select 1 = Occurrence 0 = Duration.
+    ///
+    UINT32  E:1;
+    ///
+    /// [Bit 19] PC Enabled the signaling of performance counter overflow via
+    /// BP0 pin.
+    ///
+    UINT32  PC:1;
+    ///
+    /// [Bit 20] INT Enables the signaling of counter overflow via input to
+    /// APIC 1 = Enable 0 = Disable.
+    ///
+    UINT32  INT:1;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 22] ENABLE Enables the counting of performance events in both
+    /// counters 1 = Enable 0 = Disable.
+    ///
+    UINT32  EN:1;
+    ///
+    /// [Bit 23] INV Inverts the result of the CMASK condition 1 = Inverted 0
+    /// = Non-Inverted.
+    ///
+    UINT32  INV:1;
+    ///
+    /// [Bits 31:24] CMASK (Counter Mask).
+    ///
+    UINT32  CMASK:8;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_P6_PERFEVTSEL_REGISTER;
+
+
+/**
+
+
+  @param  ECX  MSR_P6_DEBUGCTLMSR (0x000001D9)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_P6_DEBUGCTLMSR_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_P6_DEBUGCTLMSR_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_P6_DEBUGCTLMSR_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_P6_DEBUGCTLMSR);
+  AsmWriteMsr64 (MSR_P6_DEBUGCTLMSR, Msr.Uint64);
+  @endcode
+  @note MSR_P6_DEBUGCTLMSR is defined as DEBUGCTLMSR in SDM.
+**/
+#define MSR_P6_DEBUGCTLMSR                       0x000001D9
+
+/**
+  MSR information returned for MSR index #MSR_P6_DEBUGCTLMSR
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Enable/Disable Last Branch Records.
+    ///
+    UINT32  LBR:1;
+    ///
+    /// [Bit 1] Branch Trap Flag.
+    ///
+    UINT32  BTF:1;
+    ///
+    /// [Bit 2] Performance Monitoring/Break Point Pins.
+    ///
+    UINT32  PB0:1;
+    ///
+    /// [Bit 3] Performance Monitoring/Break Point Pins.
+    ///
+    UINT32  PB1:1;
+    ///
+    /// [Bit 4] Performance Monitoring/Break Point Pins.
+    ///
+    UINT32  PB2:1;
+    ///
+    /// [Bit 5] Performance Monitoring/Break Point Pins.
+    ///
+    UINT32  PB3:1;
+    ///
+    /// [Bit 6] Enable/Disable Execution Trace Messages.
+    ///
+    UINT32  TR:1;
+    UINT32  Reserved1:25;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_P6_DEBUGCTLMSR_REGISTER;
+
+
+/**
+
+
+  @param  ECX  MSR_P6_LASTBRANCHFROMIP (0x000001DB)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_LASTBRANCHFROMIP);
+  AsmWriteMsr64 (MSR_P6_LASTBRANCHFROMIP, Msr);
+  @endcode
+  @note MSR_P6_LASTBRANCHFROMIP is defined as LASTBRANCHFROMIP in SDM.
+**/
+#define MSR_P6_LASTBRANCHFROMIP                  0x000001DB
+
+
+/**
+
+
+  @param  ECX  MSR_P6_LASTBRANCHTOIP (0x000001DC)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_LASTBRANCHTOIP);
+  AsmWriteMsr64 (MSR_P6_LASTBRANCHTOIP, Msr);
+  @endcode
+  @note MSR_P6_LASTBRANCHTOIP is defined as LASTBRANCHTOIP in SDM.
+**/
+#define MSR_P6_LASTBRANCHTOIP                    0x000001DC
+
+
+/**
+
+
+  @param  ECX  MSR_P6_LASTINTFROMIP (0x000001DD)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_LASTINTFROMIP);
+  AsmWriteMsr64 (MSR_P6_LASTINTFROMIP, Msr);
+  @endcode
+  @note MSR_P6_LASTINTFROMIP is defined as LASTINTFROMIP in SDM.
+**/
+#define MSR_P6_LASTINTFROMIP                     0x000001DD
+
+
+/**
+
+
+  @param  ECX  MSR_P6_LASTINTTOIP (0x000001DE)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_LASTINTTOIP);
+  AsmWriteMsr64 (MSR_P6_LASTINTTOIP, Msr);
+  @endcode
+  @note MSR_P6_LASTINTTOIP is defined as LASTINTTOIP in SDM.
+**/
+#define MSR_P6_LASTINTTOIP                       0x000001DE
+
+/**
+
+
+  @param  ECX  MSR_P6_MTRRPHYSBASEn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSBASE0);
+  AsmWriteMsr64 (MSR_P6_MTRRPHYSBASE0, Msr);
+  @endcode
+  @note MSR_P6_MTRRPHYSBASE0 is defined as MTRRPHYSBASE0 in SDM.
+        MSR_P6_MTRRPHYSBASE1 is defined as MTRRPHYSBASE1 in SDM.
+        MSR_P6_MTRRPHYSBASE2 is defined as MTRRPHYSBASE2 in SDM.
+        MSR_P6_MTRRPHYSBASE3 is defined as MTRRPHYSBASE3 in SDM.
+        MSR_P6_MTRRPHYSBASE4 is defined as MTRRPHYSBASE4 in SDM.
+        MSR_P6_MTRRPHYSBASE5 is defined as MTRRPHYSBASE5 in SDM.
+        MSR_P6_MTRRPHYSBASE6 is defined as MTRRPHYSBASE6 in SDM.
+        MSR_P6_MTRRPHYSBASE7 is defined as MTRRPHYSBASE7 in SDM.
+  @{
+**/
+#define MSR_P6_MTRRPHYSBASE0                     0x00000200
+#define MSR_P6_MTRRPHYSBASE1                     0x00000202
+#define MSR_P6_MTRRPHYSBASE2                     0x00000204
+#define MSR_P6_MTRRPHYSBASE3                     0x00000206
+#define MSR_P6_MTRRPHYSBASE4                     0x00000208
+#define MSR_P6_MTRRPHYSBASE5                     0x0000020A
+#define MSR_P6_MTRRPHYSBASE6                     0x0000020C
+#define MSR_P6_MTRRPHYSBASE7                     0x0000020E
+/// @}
+
+
+/**
+
+
+  @param  ECX  MSR_P6_MTRRPHYSMASKn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_MTRRPHYSMASK0);
+  AsmWriteMsr64 (MSR_P6_MTRRPHYSMASK0, Msr);
+  @endcode
+  @note MSR_P6_MTRRPHYSMASK0 is defined as MTRRPHYSMASK0 in SDM.
+        MSR_P6_MTRRPHYSMASK1 is defined as MTRRPHYSMASK1 in SDM.
+        MSR_P6_MTRRPHYSMASK2 is defined as MTRRPHYSMASK2 in SDM.
+        MSR_P6_MTRRPHYSMASK3 is defined as MTRRPHYSMASK3 in SDM.
+        MSR_P6_MTRRPHYSMASK4 is defined as MTRRPHYSMASK4 in SDM.
+        MSR_P6_MTRRPHYSMASK5 is defined as MTRRPHYSMASK5 in SDM.
+        MSR_P6_MTRRPHYSMASK6 is defined as MTRRPHYSMASK6 in SDM.
+        MSR_P6_MTRRPHYSMASK7 is defined as MTRRPHYSMASK7 in SDM.
+  @{
+**/
+#define MSR_P6_MTRRPHYSMASK0                     0x00000201
+#define MSR_P6_MTRRPHYSMASK1                     0x00000203
+#define MSR_P6_MTRRPHYSMASK2                     0x00000205
+#define MSR_P6_MTRRPHYSMASK3                     0x00000207
+#define MSR_P6_MTRRPHYSMASK4                     0x00000209
+#define MSR_P6_MTRRPHYSMASK5                     0x0000020B
+#define MSR_P6_MTRRPHYSMASK6                     0x0000020D
+#define MSR_P6_MTRRPHYSMASK7                     0x0000020F
+/// @}
+
+
+/**
+
+
+  @param  ECX  MSR_P6_MTRRFIX64K_00000 (0x00000250)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_MTRRFIX64K_00000);
+  AsmWriteMsr64 (MSR_P6_MTRRFIX64K_00000, Msr);
+  @endcode
+  @note MSR_P6_MTRRFIX64K_00000 is defined as MTRRFIX64K_00000 in SDM.
+**/
+#define MSR_P6_MTRRFIX64K_00000                  0x00000250
+
+
+/**
+
+
+  @param  ECX  MSR_P6_MTRRFIX16K_80000 (0x00000258)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_MTRRFIX16K_80000);
+  AsmWriteMsr64 (MSR_P6_MTRRFIX16K_80000, Msr);
+  @endcode
+  @note MSR_P6_MTRRFIX16K_80000 is defined as MTRRFIX16K_80000 in SDM.
+**/
+#define MSR_P6_MTRRFIX16K_80000                  0x00000258
+
+
+/**
+
+
+  @param  ECX  MSR_P6_MTRRFIX16K_A0000 (0x00000259)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_MTRRFIX16K_A0000);
+  AsmWriteMsr64 (MSR_P6_MTRRFIX16K_A0000, Msr);
+  @endcode
+  @note MSR_P6_MTRRFIX16K_A0000 is defined as MTRRFIX16K_A0000 in SDM.
+**/
+#define MSR_P6_MTRRFIX16K_A0000                  0x00000259
+
+
+/**
+
+
+  @param  ECX  MSR_P6_MTRRFIX4K_C0000 (0x00000268)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_C0000);
+  AsmWriteMsr64 (MSR_P6_MTRRFIX4K_C0000, Msr);
+  @endcode
+  @note MSR_P6_MTRRFIX4K_C0000 is defined as MTRRFIX4K_C0000 in SDM.
+**/
+#define MSR_P6_MTRRFIX4K_C0000                   0x00000268
+
+
+/**
+
+
+  @param  ECX  MSR_P6_MTRRFIX4K_C8000 (0x00000269)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_C8000);
+  AsmWriteMsr64 (MSR_P6_MTRRFIX4K_C8000, Msr);
+  @endcode
+  @note MSR_P6_MTRRFIX4K_C8000 is defined as MTRRFIX4K_C8000 in SDM.
+**/
+#define MSR_P6_MTRRFIX4K_C8000                   0x00000269
+
+
+/**
+
+
+  @param  ECX  MSR_P6_MTRRFIX4K_D0000 (0x0000026A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_D0000);
+  AsmWriteMsr64 (MSR_P6_MTRRFIX4K_D0000, Msr);
+  @endcode
+  @note MSR_P6_MTRRFIX4K_D0000 is defined as MTRRFIX4K_D0000 in SDM.
+**/
+#define MSR_P6_MTRRFIX4K_D0000                   0x0000026A
+
+
+/**
+
+
+  @param  ECX  MSR_P6_MTRRFIX4K_D8000 (0x0000026B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_D8000);
+  AsmWriteMsr64 (MSR_P6_MTRRFIX4K_D8000, Msr);
+  @endcode
+  @note MSR_P6_MTRRFIX4K_D8000 is defined as MTRRFIX4K_D8000 in SDM.
+**/
+#define MSR_P6_MTRRFIX4K_D8000                   0x0000026B
+
+
+/**
+
+
+  @param  ECX  MSR_P6_MTRRFIX4K_E0000 (0x0000026C)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_E0000);
+  AsmWriteMsr64 (MSR_P6_MTRRFIX4K_E0000, Msr);
+  @endcode
+  @note MSR_P6_MTRRFIX4K_E0000 is defined as MTRRFIX4K_E0000 in SDM.
+**/
+#define MSR_P6_MTRRFIX4K_E0000                   0x0000026C
+
+
+/**
+
+
+  @param  ECX  MSR_P6_MTRRFIX4K_E8000 (0x0000026D)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_E8000);
+  AsmWriteMsr64 (MSR_P6_MTRRFIX4K_E8000, Msr);
+  @endcode
+  @note MSR_P6_MTRRFIX4K_E8000 is defined as MTRRFIX4K_E8000 in SDM.
+**/
+#define MSR_P6_MTRRFIX4K_E8000                   0x0000026D
+
+
+/**
+
+
+  @param  ECX  MSR_P6_MTRRFIX4K_F0000 (0x0000026E)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_F0000);
+  AsmWriteMsr64 (MSR_P6_MTRRFIX4K_F0000, Msr);
+  @endcode
+  @note MSR_P6_MTRRFIX4K_F0000 is defined as MTRRFIX4K_F0000 in SDM.
+**/
+#define MSR_P6_MTRRFIX4K_F0000                   0x0000026E
+
+
+/**
+
+
+  @param  ECX  MSR_P6_MTRRFIX4K_F8000 (0x0000026F)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_MTRRFIX4K_F8000);
+  AsmWriteMsr64 (MSR_P6_MTRRFIX4K_F8000, Msr);
+  @endcode
+  @note MSR_P6_MTRRFIX4K_F8000 is defined as MTRRFIX4K_F8000 in SDM.
+**/
+#define MSR_P6_MTRRFIX4K_F8000                   0x0000026F
+
+
+/**
+
+
+  @param  ECX  MSR_P6_MTRRDEFTYPE (0x000002FF)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_P6_MTRRDEFTYPE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_P6_MTRRDEFTYPE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_P6_MTRRDEFTYPE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_P6_MTRRDEFTYPE);
+  AsmWriteMsr64 (MSR_P6_MTRRDEFTYPE, Msr.Uint64);
+  @endcode
+  @note MSR_P6_MTRRDEFTYPE is defined as MTRRDEFTYPE in SDM.
+**/
+#define MSR_P6_MTRRDEFTYPE                       0x000002FF
+
+/**
+  MSR information returned for MSR index #MSR_P6_MTRRDEFTYPE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 2:0] Default memory type.
+    ///
+    UINT32  Type:3;
+    UINT32  Reserved1:7;
+    ///
+    /// [Bit 10] Fixed MTRR enable.
+    ///
+    UINT32  FE:1;
+    ///
+    /// [Bit 11] MTRR Enable.
+    ///
+    UINT32  E:1;
+    UINT32  Reserved2:20;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_P6_MTRRDEFTYPE_REGISTER;
+
+
+/**
+
+
+  @param  ECX  MSR_P6_MC0_CTL (0x00000400)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_MC0_CTL);
+  AsmWriteMsr64 (MSR_P6_MC0_CTL, Msr);
+  @endcode
+  @note MSR_P6_MC0_CTL is defined as MC0_CTL in SDM.
+        MSR_P6_MC1_CTL is defined as MC1_CTL in SDM.
+        MSR_P6_MC2_CTL is defined as MC2_CTL in SDM.
+        MSR_P6_MC3_CTL is defined as MC3_CTL in SDM.
+        MSR_P6_MC4_CTL is defined as MC4_CTL in SDM.
+  @{
+**/
+#define MSR_P6_MC0_CTL                           0x00000400
+#define MSR_P6_MC1_CTL                           0x00000404
+#define MSR_P6_MC2_CTL                           0x00000408
+#define MSR_P6_MC3_CTL                           0x00000410
+#define MSR_P6_MC4_CTL                           0x0000040C
+/// @}
+
+
+/**
+
+  Bit definitions for MSR_P6_MC4_STATUS are the same as MSR_P6_MC0_STATUS,
+  except bits 0, 4, 57, and 61 are hardcoded to 1.
+
+  @param  ECX  MSR_P6_MCn_STATUS
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_P6_MC_STATUS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_P6_MC_STATUS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_P6_MC_STATUS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_P6_MC0_STATUS);
+  AsmWriteMsr64 (MSR_P6_MC0_STATUS, Msr.Uint64);
+  @endcode
+  @note MSR_P6_MC0_STATUS is defined as MC0_STATUS in SDM.
+        MSR_P6_MC1_STATUS is defined as MC1_STATUS in SDM.
+        MSR_P6_MC2_STATUS is defined as MC2_STATUS in SDM.
+        MSR_P6_MC3_STATUS is defined as MC3_STATUS in SDM.
+        MSR_P6_MC4_STATUS is defined as MC4_STATUS in SDM.
+  @{
+**/
+#define MSR_P6_MC0_STATUS                        0x00000401
+#define MSR_P6_MC1_STATUS                        0x00000405
+#define MSR_P6_MC2_STATUS                        0x00000409
+#define MSR_P6_MC3_STATUS                        0x00000411
+#define MSR_P6_MC4_STATUS                        0x0000040D
+/// @}
+
+/**
+  MSR information returned for MSR index #MSR_P6_MC0_STATUS to
+  #MSR_P6_MC4_STATUS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 15:0] MC_STATUS_MCACOD.
+    ///
+    UINT32  MC_STATUS_MCACOD:16;
+    ///
+    /// [Bits 31:16] MC_STATUS_MSCOD.
+    ///
+    UINT32  MC_STATUS_MSCOD:16;
+    UINT32  Reserved:25;
+    ///
+    /// [Bit 57] MC_STATUS_DAM.
+    ///
+    UINT32  MC_STATUS_DAM:1;
+    ///
+    /// [Bit 58] MC_STATUS_ADDRV.
+    ///
+    UINT32  MC_STATUS_ADDRV:1;
+    ///
+    /// [Bit 59] MC_STATUS_MISCV.
+    ///
+    UINT32  MC_STATUS_MISCV:1;
+    ///
+    /// [Bit 60] MC_STATUS_EN. (Note: For MC0_STATUS only, this bit is
+    /// hardcoded to 1.).
+    ///
+    UINT32  MC_STATUS_EN:1;
+    ///
+    /// [Bit 61] MC_STATUS_UC.
+    ///
+    UINT32  MC_STATUS_UC:1;
+    ///
+    /// [Bit 62] MC_STATUS_O.
+    ///
+    UINT32  MC_STATUS_O:1;
+    ///
+    /// [Bit 63] MC_STATUS_V.
+    ///
+    UINT32  MC_STATUS_V:1;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_P6_MC_STATUS_REGISTER;
+
+
+/**
+
+  MSR_P6_MC4_ADDR is defined in MCA architecture but not implemented in P6 Family processors.
+
+  @param  ECX  MSR_P6_MC0_ADDR (0x00000402)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_MC0_ADDR);
+  AsmWriteMsr64 (MSR_P6_MC0_ADDR, Msr);
+  @endcode
+  @note MSR_P6_MC0_ADDR is defined as MC0_ADDR in SDM.
+        MSR_P6_MC1_ADDR is defined as MC1_ADDR in SDM.
+        MSR_P6_MC2_ADDR is defined as MC2_ADDR in SDM.
+        MSR_P6_MC3_ADDR is defined as MC3_ADDR in SDM.
+        MSR_P6_MC4_ADDR is defined as MC4_ADDR in SDM.
+  @{
+**/
+#define MSR_P6_MC0_ADDR                          0x00000402
+#define MSR_P6_MC1_ADDR                          0x00000406
+#define MSR_P6_MC2_ADDR                          0x0000040A
+#define MSR_P6_MC3_ADDR                          0x00000412
+#define MSR_P6_MC4_ADDR                          0x0000040E
+/// @}
+
+
+/**
+  Defined in MCA architecture but not implemented in the P6 family processors.
+
+  @param  ECX  MSR_P6_MC0_MISC (0x00000403)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_P6_MC0_MISC);
+  AsmWriteMsr64 (MSR_P6_MC0_MISC, Msr);
+  @endcode
+  @note MSR_P6_MC0_MISC is defined as MC0_MISC in SDM.
+        MSR_P6_MC1_MISC is defined as MC1_MISC in SDM.
+        MSR_P6_MC2_MISC is defined as MC2_MISC in SDM.
+        MSR_P6_MC3_MISC is defined as MC3_MISC in SDM.
+        MSR_P6_MC4_MISC is defined as MC4_MISC in SDM.
+  @{
+**/
+#define MSR_P6_MC0_MISC                          0x00000403
+#define MSR_P6_MC1_MISC                          0x00000407
+#define MSR_P6_MC2_MISC                          0x0000040B
+#define MSR_P6_MC3_MISC                          0x00000413
+#define MSR_P6_MC4_MISC                          0x0000040F
+/// @}
+
+#endif
diff --git a/MdePkg/Include/Register/Intel/Msr/Pentium4Msr.h b/MdePkg/Include/Register/Intel/Msr/Pentium4Msr.h
new file mode 100644
index 000000000000..0fb4bff64b4b
--- /dev/null
+++ b/MdePkg/Include/Register/Intel/Msr/Pentium4Msr.h
@@ -0,0 +1,2724 @@
+/** @file
+  MSR Definitions for Pentium(R) 4 Processors.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+  May 2018, Volume 4: Model-Specific-Registers (MSR)
+
+**/
+
+#ifndef __PENTIUM_4_MSR_H__
+#define __PENTIUM_4_MSR_H__
+
+#include <Register/Intel/ArchitecturalMsr.h>
+
+/**
+  Is Pentium(R) 4 Processors?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_PENTIUM_4_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x0F \
+   )
+
+/**
+  3, 4, 6. Shared. See Section 8.10.5, "Monitor/Mwait Address Range
+  Determination.".
+
+  @param  ECX  MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE (0x00000006)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE);
+  AsmWriteMsr64 (MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE is defined as IA32_MONITOR_FILTER_LINE_SIZE in SDM.
+**/
+#define MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE 0x00000006
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. Processor Hard Power-On Configuration (R/W)
+  Enables and disables processor features; (R) indicates current processor
+  configuration.
+
+  @param  ECX  MSR_PENTIUM_4_EBC_HARD_POWERON (0x0000002A)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_HARD_POWERON);
+  AsmWriteMsr64 (MSR_PENTIUM_4_EBC_HARD_POWERON, Msr.Uint64);
+  @endcode
+  @note MSR_PENTIUM_4_EBC_HARD_POWERON is defined as MSR_EBC_HARD_POWERON in SDM.
+**/
+#define MSR_PENTIUM_4_EBC_HARD_POWERON           0x0000002A
+
+/**
+  MSR information returned for MSR index #MSR_PENTIUM_4_EBC_HARD_POWERON
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Output Tri-state Enabled (R) Indicates whether tri-state
+    /// output is enabled (1) or disabled (0) as set by the strapping of SMI#.
+    /// The value in this bit is written on the deassertion of RESET#; the bit
+    /// is set to 1 when the address bus signal is asserted.
+    ///
+    UINT32  OutputTriStateEnabled:1;
+    ///
+    /// [Bit 1] Execute BIST (R)  Indicates whether the execution of the BIST
+    /// is enabled (1) or disabled (0) as set by the strapping of INIT#. The
+    /// value in this bit is written on the deassertion of RESET#; the bit is
+    /// set to 1 when the address bus signal is asserted.
+    ///
+    UINT32  ExecuteBIST:1;
+    ///
+    /// [Bit 2] In Order Queue Depth (R) Indicates whether the in order queue
+    /// depth for the system bus is 1 (1) or up to 12 (0) as set by the
+    /// strapping of A7#. The value in this bit is written on the deassertion
+    /// of RESET#; the bit is set to 1 when the address bus signal is asserted.
+    ///
+    UINT32  InOrderQueueDepth:1;
+    ///
+    /// [Bit 3] MCERR# Observation Disabled (R) Indicates whether MCERR#
+    /// observation is enabled (0) or disabled (1) as determined by the
+    /// strapping of A9#. The value in this bit is written on the deassertion
+    /// of RESET#; the bit is set to 1 when the address bus signal is asserted.
+    ///
+    UINT32  MCERR_ObservationDisabled:1;
+    ///
+    /// [Bit 4] BINIT# Observation Enabled (R) Indicates whether BINIT#
+    /// observation is enabled (0) or disabled (1) as determined by the
+    /// strapping of A10#. The value in this bit is written on the deassertion
+    /// of RESET#; the bit is set to 1 when the address bus signal is asserted.
+    ///
+    UINT32  BINIT_ObservationEnabled:1;
+    ///
+    /// [Bits 6:5] APIC Cluster ID (R)  Contains the logical APIC cluster ID
+    /// value as set by the strapping of A12# and A11#. The logical cluster ID
+    /// value is written into the field on the deassertion of RESET#; the
+    /// field is set to 1 when the address bus signal is asserted.
+    ///
+    UINT32  APICClusterID:2;
+    ///
+    /// [Bit 7] Bus Park Disable (R)  Indicates whether bus park is enabled
+    /// (0) or disabled (1) as set by the strapping of A15#. The value in this
+    /// bit is written on the deassertion of RESET#; the bit is set to 1 when
+    /// the address bus signal is asserted.
+    ///
+    UINT32  BusParkDisable:1;
+    UINT32  Reserved1:4;
+    ///
+    /// [Bits 13:12] Agent ID (R)  Contains the logical agent ID value as set
+    /// by the strapping of BR[3:0]. The logical ID value is written into the
+    /// field on the deassertion of RESET#; the field is set to 1 when the
+    /// address bus signal is asserted.
+    ///
+    UINT32  AgentID:2;
+    UINT32  Reserved2:18;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER;
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. Processor Soft Power-On Configuration (R/W)
+  Enables and disables processor features.
+
+  @param  ECX  MSR_PENTIUM_4_EBC_SOFT_POWERON (0x0000002B)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_SOFT_POWERON);
+  AsmWriteMsr64 (MSR_PENTIUM_4_EBC_SOFT_POWERON, Msr.Uint64);
+  @endcode
+  @note MSR_PENTIUM_4_EBC_SOFT_POWERON is defined as MSR_EBC_SOFT_POWERON in SDM.
+**/
+#define MSR_PENTIUM_4_EBC_SOFT_POWERON           0x0000002B
+
+/**
+  MSR information returned for MSR index #MSR_PENTIUM_4_EBC_SOFT_POWERON
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] RCNT/SCNT On Request Encoding Enable (R/W)  Controls the
+    /// driving of RCNT/SCNT on the request encoding. Set to enable (1); clear
+    /// to disabled (0, default).
+    ///
+    UINT32  RCNT_SCNT:1;
+    ///
+    /// [Bit 1] Data Error Checking Disable (R/W)  Set to disable system data
+    /// bus parity checking; clear to enable parity checking.
+    ///
+    UINT32  DataErrorCheckingDisable:1;
+    ///
+    /// [Bit 2] Response Error Checking Disable (R/W) Set to disable
+    /// (default); clear to enable.
+    ///
+    UINT32  ResponseErrorCheckingDisable:1;
+    ///
+    /// [Bit 3] Address/Request Error Checking Disable (R/W) Set to disable
+    /// (default); clear to enable.
+    ///
+    UINT32  AddressRequestErrorCheckingDisable:1;
+    ///
+    /// [Bit 4] Initiator MCERR# Disable (R/W) Set to disable MCERR# driving
+    /// for initiator bus requests (default); clear to enable.
+    ///
+    UINT32  InitiatorMCERR_Disable:1;
+    ///
+    /// [Bit 5] Internal MCERR# Disable (R/W) Set to disable MCERR# driving
+    /// for initiator internal errors (default); clear to enable.
+    ///
+    UINT32  InternalMCERR_Disable:1;
+    ///
+    /// [Bit 6] BINIT# Driver Disable (R/W)  Set to disable BINIT# driver
+    /// (default); clear to enable driver.
+    ///
+    UINT32  BINIT_DriverDisable:1;
+    UINT32  Reserved1:25;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER;
+
+
+/**
+  2,3, 4, 6. Shared. Processor Frequency Configuration The bit field layout of
+  this MSR varies according to the MODEL value in the CPUID version
+  information. The following bit field layout applies to Pentium 4 and Xeon
+  Processors with MODEL encoding equal or greater than 2. (R) The field
+  Indicates the current processor frequency configuration.
+
+  @param  ECX  MSR_PENTIUM_4_EBC_FREQUENCY_ID (0x0000002C)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_FREQUENCY_ID);
+  @endcode
+  @note MSR_PENTIUM_4_EBC_FREQUENCY_ID is defined as MSR_EBC_FREQUENCY_ID in SDM.
+**/
+#define MSR_PENTIUM_4_EBC_FREQUENCY_ID           0x0000002C
+
+/**
+  MSR information returned for MSR index #MSR_PENTIUM_4_EBC_FREQUENCY_ID
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:16;
+    ///
+    /// [Bits 18:16] Scalable Bus Speed (R/W) Indicates the intended scalable
+    /// bus speed: *EncodingScalable Bus Speed*
+    ///
+    ///   000B 100 MHz (Model 2).
+    ///   000B 266 MHz (Model 3 or 4)
+    ///   001B 133 MHz
+    ///   010B 200 MHz
+    ///   011B 166 MHz
+    ///   100B 333 MHz (Model 6)
+    ///
+    ///   133.33 MHz should be utilized if performing calculation with System
+    ///   Bus Speed when encoding is 001B. 166.67 MHz should be utilized if
+    ///   performing calculation with System Bus Speed when encoding is 011B.
+    ///   266.67 MHz should be utilized if performing calculation with System
+    ///   Bus Speed when encoding is 000B and model encoding = 3 or 4. 333.33
+    ///   MHz should be utilized if performing calculation with System Bus
+    ///   Speed when encoding is 100B and model encoding = 6. All other values
+    ///   are reserved.
+    ///
+    UINT32  ScalableBusSpeed:3;
+    UINT32  Reserved2:5;
+    ///
+    /// [Bits 31:24] Core Clock Frequency to System Bus  Frequency Ratio (R)
+    /// The processor core clock frequency to system bus frequency ratio
+    /// observed at the de-assertion of the reset pin.
+    ///
+    UINT32  ClockRatio:8;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER;
+
+
+/**
+  0, 1. Shared. Processor Frequency Configuration (R)  The bit field layout of
+  this MSR varies according to the MODEL value of the CPUID version
+  information. This bit field layout applies to Pentium 4 and Xeon Processors
+  with MODEL encoding less than 2. Indicates current processor frequency
+  configuration.
+
+  @param  ECX  MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 (0x0000002C)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_FREQUENCY_ID_1);
+  @endcode
+  @note MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 is defined as MSR_EBC_FREQUENCY_ID_1 in SDM.
+**/
+#define MSR_PENTIUM_4_EBC_FREQUENCY_ID_1         0x0000002C
+
+/**
+  MSR information returned for MSR index #MSR_PENTIUM_4_EBC_FREQUENCY_ID_1
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:21;
+    ///
+    /// [Bits 23:21] Scalable Bus Speed (R/W) Indicates the intended scalable
+    /// bus speed: *Encoding* *Scalable Bus Speed*
+    ///
+    ///   000B 100 MHz All others values reserved.
+    ///
+    UINT32  ScalableBusSpeed:3;
+    UINT32  Reserved2:8;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER;
+
+
+/**
+  0, 1, 2, 3, 4, 6. Unique. Machine Check EAX/RAX Save State See Section
+  15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
+  state at time of machine check error. When in non-64-bit modes at the time
+  of the error, bits 63-32 do not contain valid data.
+
+  @param  ECX  MSR_PENTIUM_4_MCG_RAX (0x00000180)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RAX);
+  AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RAX, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_MCG_RAX is defined as MSR_MCG_RAX in SDM.
+**/
+#define MSR_PENTIUM_4_MCG_RAX                    0x00000180
+
+
+/**
+  0, 1, 2, 3, 4, 6. Unique. Machine Check EBX/RBX Save State See Section
+  15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
+  state at time of machine check error. When in non-64-bit modes at the time
+  of the error, bits 63-32 do not contain valid data.
+
+  @param  ECX  MSR_PENTIUM_4_MCG_RBX (0x00000181)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RBX);
+  AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RBX, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_MCG_RBX is defined as MSR_MCG_RBX in SDM.
+**/
+#define MSR_PENTIUM_4_MCG_RBX                    0x00000181
+
+
+/**
+  0, 1, 2, 3, 4, 6. Unique. Machine Check ECX/RCX Save State See Section
+  15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
+  state at time of machine check error. When in non-64-bit modes at the time
+  of the error, bits 63-32 do not contain valid data.
+
+  @param  ECX  MSR_PENTIUM_4_MCG_RCX (0x00000182)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RCX);
+  AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RCX, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_MCG_RCX is defined as MSR_MCG_RCX in SDM.
+**/
+#define MSR_PENTIUM_4_MCG_RCX                    0x00000182
+
+
+/**
+  0, 1, 2, 3, 4, 6. Unique. Machine Check EDX/RDX Save State See Section
+  15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
+  state at time of machine check error. When in non-64-bit modes at the time
+  of the error, bits 63-32 do not contain valid data.
+
+  @param  ECX  MSR_PENTIUM_4_MCG_RDX (0x00000183)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RDX);
+  AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RDX, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_MCG_RDX is defined as MSR_MCG_RDX in SDM.
+**/
+#define MSR_PENTIUM_4_MCG_RDX                    0x00000183
+
+
+/**
+  0, 1, 2, 3, 4, 6. Unique. Machine Check ESI/RSI Save State See Section
+  15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
+  state at time of machine check error. When in non-64-bit modes at the time
+  of the error, bits 63-32 do not contain valid data.
+
+  @param  ECX  MSR_PENTIUM_4_MCG_RSI (0x00000184)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RSI);
+  AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RSI, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_MCG_RSI is defined as MSR_MCG_RSI in SDM.
+**/
+#define MSR_PENTIUM_4_MCG_RSI                    0x00000184
+
+
+/**
+  0, 1, 2, 3, 4, 6. Unique. Machine Check EDI/RDI Save State See Section
+  15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
+  state at time of machine check error. When in non-64-bit modes at the time
+  of the error, bits 63-32 do not contain valid data.
+
+  @param  ECX  MSR_PENTIUM_4_MCG_RDI (0x00000185)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RDI);
+  AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RDI, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_MCG_RDI is defined as MSR_MCG_RDI in SDM.
+**/
+#define MSR_PENTIUM_4_MCG_RDI                    0x00000185
+
+
+/**
+  0, 1, 2, 3, 4, 6. Unique. Machine Check EBP/RBP Save State See Section
+  15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
+  state at time of machine check error. When in non-64-bit modes at the time
+  of the error, bits 63-32 do not contain valid data.
+
+  @param  ECX  MSR_PENTIUM_4_MCG_RBP (0x00000186)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RBP);
+  AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RBP, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_MCG_RBP is defined as MSR_MCG_RBP in SDM.
+**/
+#define MSR_PENTIUM_4_MCG_RBP                    0x00000186
+
+
+/**
+  0, 1, 2, 3, 4, 6. Unique. Machine Check ESP/RSP Save State See Section
+  15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
+  state at time of machine check error. When in non-64-bit modes at the time
+  of the error, bits 63-32 do not contain valid data.
+
+  @param  ECX  MSR_PENTIUM_4_MCG_RSP (0x00000187)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RSP);
+  AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RSP, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_MCG_RSP is defined as MSR_MCG_RSP in SDM.
+**/
+#define MSR_PENTIUM_4_MCG_RSP                    0x00000187
+
+
+/**
+  0, 1, 2, 3, 4, 6. Unique. Machine Check EFLAGS/RFLAG Save State See Section
+  15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
+  state at time of machine check error. When in non-64-bit modes at the time
+  of the error, bits 63-32 do not contain valid data.
+
+  @param  ECX  MSR_PENTIUM_4_MCG_RFLAGS (0x00000188)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RFLAGS);
+  AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RFLAGS, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_MCG_RFLAGS is defined as MSR_MCG_RFLAGS in SDM.
+**/
+#define MSR_PENTIUM_4_MCG_RFLAGS                 0x00000188
+
+
+/**
+  0, 1, 2, 3, 4, 6. Unique. Machine Check EIP/RIP Save State See Section
+  15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register
+  state at time of machine check error. When in non-64-bit modes at the time
+  of the error, bits 63-32 do not contain valid data.
+
+  @param  ECX  MSR_PENTIUM_4_MCG_RIP (0x00000189)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RIP);
+  AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RIP, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_MCG_RIP is defined as MSR_MCG_RIP in SDM.
+**/
+#define MSR_PENTIUM_4_MCG_RIP                    0x00000189
+
+
+/**
+  0, 1, 2, 3, 4, 6. Unique. Machine Check Miscellaneous See Section 15.3.2.6,
+  "IA32_MCG Extended Machine Check State MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_MCG_MISC (0x0000018A)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_PENTIUM_4_MCG_MISC_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_PENTIUM_4_MCG_MISC_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_PENTIUM_4_MCG_MISC_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_MCG_MISC);
+  AsmWriteMsr64 (MSR_PENTIUM_4_MCG_MISC, Msr.Uint64);
+  @endcode
+  @note MSR_PENTIUM_4_MCG_MISC is defined as MSR_MCG_MISC in SDM.
+**/
+#define MSR_PENTIUM_4_MCG_MISC                   0x0000018A
+
+/**
+  MSR information returned for MSR index #MSR_PENTIUM_4_MCG_MISC
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] DS When set, the bit indicates that a page assist or page
+    /// fault occurred during DS normal operation. The processors response is
+    /// to shut down. The bit is used as an aid for debugging DS handling
+    /// code. It is the responsibility of the user (BIOS or operating system)
+    /// to clear this bit for normal operation.
+    ///
+    UINT32  DS:1;
+    UINT32  Reserved1:31;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_PENTIUM_4_MCG_MISC_REGISTER;
+
+
+/**
+  0, 1, 2, 3, 4, 6. Unique. Machine Check R8 See Section 15.3.2.6, "IA32_MCG
+  Extended Machine Check State MSRs.". Registers R8-15 (and the associated
+  state-save MSRs) exist only in Intel 64 processors. These registers contain
+  valid information only when the processor is operating in 64-bit mode at the
+  time of the error.
+
+  @param  ECX  MSR_PENTIUM_4_MCG_R8 (0x00000190)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R8);
+  AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R8, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_MCG_R8 is defined as MSR_MCG_R8 in SDM.
+**/
+#define MSR_PENTIUM_4_MCG_R8                     0x00000190
+
+
+/**
+  0, 1, 2, 3, 4, 6. Unique. Machine Check R9D/R9 See Section 15.3.2.6,
+  "IA32_MCG Extended Machine Check State MSRs.". Registers R8-15 (and the
+  associated state-save MSRs) exist only in Intel 64 processors. These
+  registers contain valid information only when the processor is operating in
+  64-bit mode at the time of the error.
+
+  @param  ECX  MSR_PENTIUM_4_MCG_R9 (0x00000191)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R9);
+  AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R9, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_MCG_R9 is defined as MSR_MCG_R9 in SDM.
+**/
+#define MSR_PENTIUM_4_MCG_R9                     0x00000191
+
+
+/**
+  0, 1, 2, 3, 4, 6. Unique. Machine Check R10 See Section 15.3.2.6, "IA32_MCG
+  Extended Machine Check State MSRs.". Registers R8-15 (and the associated
+  state-save MSRs) exist only in Intel 64 processors. These registers contain
+  valid information only when the processor is operating in 64-bit mode at the
+  time of the error.
+
+  @param  ECX  MSR_PENTIUM_4_MCG_R10 (0x00000192)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R10);
+  AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R10, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_MCG_R10 is defined as MSR_MCG_R10 in SDM.
+**/
+#define MSR_PENTIUM_4_MCG_R10                    0x00000192
+
+
+/**
+  0, 1, 2, 3, 4, 6. Unique. Machine Check R11 See Section 15.3.2.6, "IA32_MCG
+  Extended Machine Check State MSRs.". Registers R8-15 (and the associated
+  state-save MSRs) exist only in Intel 64 processors. These registers contain
+  valid information only when the processor is operating in 64-bit mode at the
+  time of the error.
+
+  @param  ECX  MSR_PENTIUM_4_MCG_R11 (0x00000193)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R11);
+  AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R11, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_MCG_R11 is defined as MSR_MCG_R11 in SDM.
+**/
+#define MSR_PENTIUM_4_MCG_R11                    0x00000193
+
+
+/**
+  0, 1, 2, 3, 4, 6. Unique. Machine Check R12 See Section 15.3.2.6, "IA32_MCG
+  Extended Machine Check State MSRs.". Registers R8-15 (and the associated
+  state-save MSRs) exist only in Intel 64 processors. These registers contain
+  valid information only when the processor is operating in 64-bit mode at the
+  time of the error.
+
+  @param  ECX  MSR_PENTIUM_4_MCG_R12 (0x00000194)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R12);
+  AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R12, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_MCG_R12 is defined as MSR_MCG_R12 in SDM.
+**/
+#define MSR_PENTIUM_4_MCG_R12                    0x00000194
+
+
+/**
+  0, 1, 2, 3, 4, 6. Unique. Machine Check R13 See Section 15.3.2.6, "IA32_MCG
+  Extended Machine Check State MSRs.". Registers R8-15 (and the associated
+  state-save MSRs) exist only in Intel 64 processors. These registers contain
+  valid information only when the processor is operating in 64-bit mode at the
+  time of the error.
+
+  @param  ECX  MSR_PENTIUM_4_MCG_R13 (0x00000195)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R13);
+  AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R13, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_MCG_R13 is defined as MSR_MCG_R13 in SDM.
+**/
+#define MSR_PENTIUM_4_MCG_R13                    0x00000195
+
+
+/**
+  0, 1, 2, 3, 4, 6. Unique. Machine Check R14 See Section 15.3.2.6, "IA32_MCG
+  Extended Machine Check State MSRs.". Registers R8-15 (and the associated
+  state-save MSRs) exist only in Intel 64 processors. These registers contain
+  valid information only when the processor is operating in 64-bit mode at the
+  time of the error.
+
+  @param  ECX  MSR_PENTIUM_4_MCG_R14 (0x00000196)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R14);
+  AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R14, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_MCG_R14 is defined as MSR_MCG_R14 in SDM.
+**/
+#define MSR_PENTIUM_4_MCG_R14                    0x00000196
+
+
+/**
+  0, 1, 2, 3, 4, 6. Unique. Machine Check R15 See Section 15.3.2.6, "IA32_MCG
+  Extended Machine Check State MSRs.". Registers R8-15 (and the associated
+  state-save MSRs) exist only in Intel 64 processors. These registers contain
+  valid information only when the processor is operating in 64-bit mode at the
+  time of the error.
+
+  @param  ECX  MSR_PENTIUM_4_MCG_R15 (0x00000197)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R15);
+  AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R15, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_MCG_R15 is defined as MSR_MCG_R15 in SDM.
+**/
+#define MSR_PENTIUM_4_MCG_R15                    0x00000197
+
+
+/**
+  Thermal Monitor 2 Control. 3,. Shared. For Family F, Model 3 processors:
+  When read, specifies the value of the target TM2 transition last written.
+  When set, it sets the next target value for TM2 transition. 4, 6. Shared.
+  For Family F, Model 4 and Model 6 processors: When read, specifies the value
+  of the target TM2 transition last written. Writes may cause #GP exceptions.
+
+  @param  ECX  MSR_PENTIUM_4_THERM2_CTL (0x0000019D)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_THERM2_CTL);
+  AsmWriteMsr64 (MSR_PENTIUM_4_THERM2_CTL, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
+**/
+#define MSR_PENTIUM_4_THERM2_CTL                 0x0000019D
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. Enable Miscellaneous Processor Features (R/W).
+
+  @param  ECX  MSR_PENTIUM_4_IA32_MISC_ENABLE (0x000001A0)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_IA32_MISC_ENABLE);
+  AsmWriteMsr64 (MSR_PENTIUM_4_IA32_MISC_ENABLE, Msr.Uint64);
+  @endcode
+  @note MSR_PENTIUM_4_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
+**/
+#define MSR_PENTIUM_4_IA32_MISC_ENABLE           0x000001A0
+
+/**
+  MSR information returned for MSR index #MSR_PENTIUM_4_IA32_MISC_ENABLE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Fast-Strings Enable. See Table 2-2.
+    ///
+    UINT32  FastStrings:1;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 2] x87 FPU Fopcode Compatibility Mode Enable.
+    ///
+    UINT32  FPU:1;
+    ///
+    /// [Bit 3] Thermal Monitor 1 Enable See Section 14.7.2, "Thermal
+    /// Monitor," and see Table 2-2.
+    ///
+    UINT32  TM1:1;
+    ///
+    /// [Bit 4] Split-Lock Disable When set, the bit causes an #AC exception
+    /// to be issued instead of a split-lock cycle. Operating systems that set
+    /// this bit must align system structures to avoid split-lock scenarios.
+    /// When the bit is clear (default), normal split-locks are issued to the
+    /// bus.
+    ///   This debug feature is specific to the Pentium 4 processor.
+    ///
+    UINT32  SplitLockDisable:1;
+    UINT32  Reserved2:1;
+    ///
+    /// [Bit 6] Third-Level Cache Disable (R/W) When set, the third-level
+    /// cache is disabled; when clear (default) the third-level cache is
+    /// enabled. This flag is reserved for processors that do not have a
+    /// third-level cache. Note that the bit controls only the third-level
+    /// cache; and only if overall caching is enabled through the CD flag of
+    /// control register CR0, the page-level cache controls, and/or the MTRRs.
+    /// See Section 11.5.4, "Disabling and Enabling the L3 Cache.".
+    ///
+    UINT32  ThirdLevelCacheDisable:1;
+    ///
+    /// [Bit 7] Performance Monitoring Available (R) See Table 2-2.
+    ///
+    UINT32  PerformanceMonitoring:1;
+    ///
+    /// [Bit 8] Suppress Lock Enable When set, assertion of LOCK on the bus is
+    /// suppressed during a Split Lock access. When clear (default), LOCK is
+    /// not suppressed.
+    ///
+    UINT32  SuppressLockEnable:1;
+    ///
+    /// [Bit 9] Prefetch Queue Disable When set, disables the prefetch queue.
+    /// When clear (default), enables the prefetch queue.
+    ///
+    UINT32  PrefetchQueueDisable:1;
+    ///
+    /// [Bit 10] FERR# Interrupt Reporting Enable (R/W)  When set, interrupt
+    /// reporting through the FERR# pin is enabled; when clear, this interrupt
+    /// reporting function is disabled.
+    ///   When this flag is set and the processor is in the stop-clock state
+    ///   (STPCLK# is asserted), asserting the FERR# pin signals to the
+    ///   processor that an interrupt (such as, INIT#, BINIT#, INTR, NMI,
+    ///   SMI#, or RESET#) is pending and that the processor should return to
+    ///   normal operation to handle the interrupt. This flag does not affect
+    ///   the normal operation of the FERR# pin (to indicate an unmasked
+    ///   floatingpoint error) when the STPCLK# pin is not asserted.
+    ///
+    UINT32  FERR:1;
+    ///
+    /// [Bit 11] Branch Trace Storage Unavailable (BTS_UNAVILABLE) (R) See
+    /// Table 2-2. When set, the processor does not support branch trace
+    /// storage (BTS); when clear, BTS is supported.
+    ///
+    UINT32  BTS:1;
+    ///
+    /// [Bit 12] PEBS_UNAVILABLE: Processor Event Based Sampling Unavailable
+    /// (R) See Table 2-2. When set, the processor does not support processor
+    /// event-based sampling (PEBS); when clear, PEBS is supported.
+    ///
+    UINT32  PEBS:1;
+    ///
+    /// [Bit 13] 3. TM2 Enable (R/W) When this bit is set (1) and the thermal
+    /// sensor indicates that the die temperature is at the predetermined
+    /// threshold, the Thermal Monitor 2 mechanism is engaged. TM2 will reduce
+    /// the bus to core ratio and voltage according to the value last written
+    /// to MSR_THERM2_CTL bits 15:0. When this bit is clear (0, default), the
+    /// processor does not change the VID signals or the bus to core ratio
+    /// when the processor enters a thermal managed state. If the TM2 feature
+    /// flag (ECX[8]) is not set to 1 after executing CPUID with EAX = 1, then
+    /// this feature is not supported and BIOS must not alter the contents of
+    /// this bit location. The processor is operating out of spec if both this
+    /// bit and the TM1 bit are set to disabled states.
+    ///
+    UINT32  TM2:1;
+    UINT32  Reserved3:4;
+    ///
+    /// [Bit 18] 3, 4, 6. ENABLE MONITOR FSM (R/W) See Table 2-2.
+    ///
+    UINT32  MONITOR:1;
+    ///
+    /// [Bit 19] Adjacent Cache Line Prefetch Disable (R/W)  When set to 1,
+    /// the processor fetches the cache line of the 128-byte sector containing
+    /// currently required data. When set to 0, the processor fetches both
+    /// cache lines in the sector.
+    ///   Single processor platforms should not set this bit. Server platforms
+    ///   should set or clear this bit based on platform performance observed
+    ///   in validation and testing. BIOS may contain a setup option that
+    ///   controls the setting of this bit.
+    ///
+    UINT32  AdjacentCacheLinePrefetchDisable:1;
+    UINT32  Reserved4:2;
+    ///
+    /// [Bit 22] 3, 4, 6. Limit CPUID MAXVAL (R/W) See Table 2-2. Setting this
+    /// can cause unexpected behavior to software that depends on the
+    /// availability of CPUID leaves greater than 3.
+    ///
+    UINT32  LimitCpuidMaxval:1;
+    ///
+    /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2.
+    ///
+    UINT32  xTPR_Message_Disable:1;
+    ///
+    /// [Bit 24] L1 Data Cache Context Mode (R/W)  When set, the L1 data cache
+    /// is placed in shared mode; when clear (default), the cache is placed in
+    /// adaptive mode. This bit is only enabled for IA-32 processors that
+    /// support Intel Hyper-Threading Technology. See Section 11.5.6, "L1 Data
+    /// Cache Context Mode." When L1 is running in adaptive mode and CR3s are
+    /// identical, data in L1 is shared across logical processors. Otherwise,
+    /// L1 is not shared and cache use is competitive. If the Context ID
+    /// feature flag (ECX[10]) is set to 0 after executing CPUID with EAX = 1,
+    /// the ability to switch modes is not supported. BIOS must not alter the
+    /// contents of IA32_MISC_ENABLE[24].
+    ///
+    UINT32  L1DataCacheContextMode:1;
+    UINT32  Reserved5:7;
+    UINT32  Reserved6:2;
+    ///
+    /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2.
+    ///
+    UINT32  XD:1;
+    UINT32  Reserved7:29;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER;
+
+
+/**
+  3, 4, 6. Shared. Platform Feature Requirements (R).
+
+  @param  ECX  MSR_PENTIUM_4_PLATFORM_BRV (0x000001A1)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_PENTIUM_4_PLATFORM_BRV_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_PENTIUM_4_PLATFORM_BRV_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_PENTIUM_4_PLATFORM_BRV_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_PLATFORM_BRV);
+  @endcode
+  @note MSR_PENTIUM_4_PLATFORM_BRV is defined as MSR_PLATFORM_BRV in SDM.
+**/
+#define MSR_PENTIUM_4_PLATFORM_BRV               0x000001A1
+
+/**
+  MSR information returned for MSR index #MSR_PENTIUM_4_PLATFORM_BRV
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:18;
+    ///
+    /// [Bit 18] PLATFORM Requirements When set to 1, indicates the processor
+    /// has specific platform requirements. The details of the platform
+    /// requirements are listed in the respective data sheets of the processor.
+    ///
+    UINT32  PLATFORM:1;
+    UINT32  Reserved2:13;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_PENTIUM_4_PLATFORM_BRV_REGISTER;
+
+
+/**
+  0, 1, 2, 3, 4, 6. Unique. Last Exception Record From Linear IP (R)  Contains
+  a pointer to the last branch instruction that the processor executed prior
+  to the last exception that was generated or the last interrupt that was
+  handled. See Section 17.13.3, "Last Exception Records.". Unique. From Linear
+  IP Linear address of the last branch instruction (If IA-32e mode is active).
+  From Linear IP Linear address of the last branch instruction. Reserved.
+
+  @param  ECX  MSR_PENTIUM_4_LER_FROM_LIP (0x000001D7)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_LER_FROM_LIP);
+  @endcode
+  @note MSR_PENTIUM_4_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
+**/
+#define MSR_PENTIUM_4_LER_FROM_LIP               0x000001D7
+
+
+/**
+  0, 1, 2, 3, 4, 6. Unique. Last Exception Record To Linear IP (R)  This area
+  contains a pointer to the target of the last branch instruction that the
+  processor executed prior to the last exception that was generated or the
+  last interrupt that was handled. See Section 17.13.3, "Last Exception
+  Records.". Unique. From Linear IP Linear address of the target of the last
+  branch instruction (If IA-32e mode is active). From Linear IP Linear address
+  of the target of the last branch instruction. Reserved.
+
+  @param  ECX  MSR_PENTIUM_4_LER_TO_LIP (0x000001D8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_LER_TO_LIP);
+  @endcode
+  @note MSR_PENTIUM_4_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
+**/
+#define MSR_PENTIUM_4_LER_TO_LIP                 0x000001D8
+
+
+/**
+  0, 1, 2, 3, 4, 6. Unique. Debug Control (R/W)  Controls how several debug
+  features are used. Bit definitions are discussed in the referenced section.
+  See Section 17.13.1, "MSR_DEBUGCTLA MSR.".
+
+  @param  ECX  MSR_PENTIUM_4_DEBUGCTLA (0x000001D9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_DEBUGCTLA);
+  AsmWriteMsr64 (MSR_PENTIUM_4_DEBUGCTLA, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_DEBUGCTLA is defined as MSR_DEBUGCTLA in SDM.
+**/
+#define MSR_PENTIUM_4_DEBUGCTLA                  0x000001D9
+
+
+/**
+  0, 1, 2, 3, 4, 6. Unique. Last Branch Record Stack TOS (R/W)  Contains an
+  index (0-3 or 0-15) that points to the top of the last branch record stack
+  (that is, that points the index of the MSR containing the most recent branch
+  record). See Section 17.13.2, "LBR Stack for Processors Based on Intel
+  NetBurst(R) Microarchitecture"; and addresses 1DBH-1DEH and 680H-68FH.
+
+  @param  ECX  MSR_PENTIUM_4_LASTBRANCH_TOS (0x000001DA)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_TOS);
+  AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_TOS, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
+**/
+#define MSR_PENTIUM_4_LASTBRANCH_TOS             0x000001DA
+
+
+/**
+  0, 1, 2. Unique. Last Branch Record n (R/W)  One of four last branch record
+  registers on the last branch record stack. It contains pointers to the
+  source and destination instruction for one of the last four branches,
+  exceptions, or interrupts that the processor took. MSR_LASTBRANCH_0 through
+  MSR_LASTBRANCH_3 at 1DBH-1DEH are available only on family 0FH, models
+  0H-02H. They have been replaced by the MSRs at 680H68FH and 6C0H-6CFH. See
+  Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording
+  for Processors based on Skylake Microarchitecture.".
+
+  @param  ECX  MSR_PENTIUM_4_LASTBRANCH_n
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0);
+  AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.
+  @{
+**/
+#define MSR_PENTIUM_4_LASTBRANCH_0               0x000001DB
+#define MSR_PENTIUM_4_LASTBRANCH_1               0x000001DC
+#define MSR_PENTIUM_4_LASTBRANCH_2               0x000001DD
+#define MSR_PENTIUM_4_LASTBRANCH_3               0x000001DE
+/// @}
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".
+
+  @param  ECX  MSR_PENTIUM_4_BPU_COUNTERn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_COUNTER0);
+  AsmWriteMsr64 (MSR_PENTIUM_4_BPU_COUNTER0, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_BPU_COUNTER0 is defined as MSR_BPU_COUNTER0 in SDM.
+        MSR_PENTIUM_4_BPU_COUNTER1 is defined as MSR_BPU_COUNTER1 in SDM.
+        MSR_PENTIUM_4_BPU_COUNTER2 is defined as MSR_BPU_COUNTER2 in SDM.
+        MSR_PENTIUM_4_BPU_COUNTER3 is defined as MSR_BPU_COUNTER3 in SDM.
+  @{
+**/
+#define MSR_PENTIUM_4_BPU_COUNTER0               0x00000300
+#define MSR_PENTIUM_4_BPU_COUNTER1               0x00000301
+#define MSR_PENTIUM_4_BPU_COUNTER2               0x00000302
+#define MSR_PENTIUM_4_BPU_COUNTER3               0x00000303
+/// @}
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".
+
+  @param  ECX  MSR_PENTIUM_4_MS_COUNTERn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_COUNTER0);
+  AsmWriteMsr64 (MSR_PENTIUM_4_MS_COUNTER0, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_MS_COUNTER0 is defined as MSR_MS_COUNTER0 in SDM.
+        MSR_PENTIUM_4_MS_COUNTER1 is defined as MSR_MS_COUNTER1 in SDM.
+        MSR_PENTIUM_4_MS_COUNTER2 is defined as MSR_MS_COUNTER2 in SDM.
+        MSR_PENTIUM_4_MS_COUNTER3 is defined as MSR_MS_COUNTER3 in SDM.
+  @{
+**/
+#define MSR_PENTIUM_4_MS_COUNTER0                0x00000304
+#define MSR_PENTIUM_4_MS_COUNTER1                0x00000305
+#define MSR_PENTIUM_4_MS_COUNTER2                0x00000306
+#define MSR_PENTIUM_4_MS_COUNTER3                0x00000307
+/// @}
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".
+
+  @param  ECX  MSR_PENTIUM_4_FLAME_COUNTERn (0x00000308)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_COUNTER0);
+  AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_COUNTER0, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_FLAME_COUNTER0 is defined as MSR_FLAME_COUNTER0 in SDM.
+        MSR_PENTIUM_4_FLAME_COUNTER1 is defined as MSR_FLAME_COUNTER1 in SDM.
+        MSR_PENTIUM_4_FLAME_COUNTER2 is defined as MSR_FLAME_COUNTER2 in SDM.
+        MSR_PENTIUM_4_FLAME_COUNTER3 is defined as MSR_FLAME_COUNTER3 in SDM.
+  @{
+**/
+#define MSR_PENTIUM_4_FLAME_COUNTER0             0x00000308
+#define MSR_PENTIUM_4_FLAME_COUNTER1             0x00000309
+#define MSR_PENTIUM_4_FLAME_COUNTER2             0x0000030A
+#define MSR_PENTIUM_4_FLAME_COUNTER3             0x0000030B
+/// @}
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".
+
+  @param  ECX  MSR_PENTIUM_4_IQ_COUNTERn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_COUNTER0);
+  AsmWriteMsr64 (MSR_PENTIUM_4_IQ_COUNTER0, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_IQ_COUNTER0 is defined as MSR_IQ_COUNTER0 in SDM.
+        MSR_PENTIUM_4_IQ_COUNTER1 is defined as MSR_IQ_COUNTER1 in SDM.
+        MSR_PENTIUM_4_IQ_COUNTER2 is defined as MSR_IQ_COUNTER2 in SDM.
+        MSR_PENTIUM_4_IQ_COUNTER3 is defined as MSR_IQ_COUNTER3 in SDM.
+        MSR_PENTIUM_4_IQ_COUNTER4 is defined as MSR_IQ_COUNTER4 in SDM.
+        MSR_PENTIUM_4_IQ_COUNTER5 is defined as MSR_IQ_COUNTER5 in SDM.
+  @{
+**/
+#define MSR_PENTIUM_4_IQ_COUNTER0                0x0000030C
+#define MSR_PENTIUM_4_IQ_COUNTER1                0x0000030D
+#define MSR_PENTIUM_4_IQ_COUNTER2                0x0000030E
+#define MSR_PENTIUM_4_IQ_COUNTER3                0x0000030F
+#define MSR_PENTIUM_4_IQ_COUNTER4                0x00000310
+#define MSR_PENTIUM_4_IQ_COUNTER5                0x00000311
+/// @}
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_BPU_CCCRn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_CCCR0);
+  AsmWriteMsr64 (MSR_PENTIUM_4_BPU_CCCR0, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_BPU_CCCR0 is defined as MSR_BPU_CCCR0 in SDM.
+        MSR_PENTIUM_4_BPU_CCCR1 is defined as MSR_BPU_CCCR1 in SDM.
+        MSR_PENTIUM_4_BPU_CCCR2 is defined as MSR_BPU_CCCR2 in SDM.
+        MSR_PENTIUM_4_BPU_CCCR3 is defined as MSR_BPU_CCCR3 in SDM.
+  @{
+**/
+#define MSR_PENTIUM_4_BPU_CCCR0                  0x00000360
+#define MSR_PENTIUM_4_BPU_CCCR1                  0x00000361
+#define MSR_PENTIUM_4_BPU_CCCR2                  0x00000362
+#define MSR_PENTIUM_4_BPU_CCCR3                  0x00000363
+/// @}
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_MS_CCCRn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_CCCR0);
+  AsmWriteMsr64 (MSR_PENTIUM_4_MS_CCCR0, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_MS_CCCR0 is defined as MSR_MS_CCCR0 in SDM.
+        MSR_PENTIUM_4_MS_CCCR1 is defined as MSR_MS_CCCR1 in SDM.
+        MSR_PENTIUM_4_MS_CCCR2 is defined as MSR_MS_CCCR2 in SDM.
+        MSR_PENTIUM_4_MS_CCCR3 is defined as MSR_MS_CCCR3 in SDM.
+  @{
+**/
+#define MSR_PENTIUM_4_MS_CCCR0                   0x00000364
+#define MSR_PENTIUM_4_MS_CCCR1                   0x00000365
+#define MSR_PENTIUM_4_MS_CCCR2                   0x00000366
+#define MSR_PENTIUM_4_MS_CCCR3                   0x00000367
+/// @}
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_FLAME_CCCRn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_CCCR0);
+  AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_CCCR0, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_FLAME_CCCR0 is defined as MSR_FLAME_CCCR0 in SDM.
+        MSR_PENTIUM_4_FLAME_CCCR1 is defined as MSR_FLAME_CCCR1 in SDM.
+        MSR_PENTIUM_4_FLAME_CCCR2 is defined as MSR_FLAME_CCCR2 in SDM.
+        MSR_PENTIUM_4_FLAME_CCCR3 is defined as MSR_FLAME_CCCR3 in SDM.
+  @{
+**/
+#define MSR_PENTIUM_4_FLAME_CCCR0                0x00000368
+#define MSR_PENTIUM_4_FLAME_CCCR1                0x00000369
+#define MSR_PENTIUM_4_FLAME_CCCR2                0x0000036A
+#define MSR_PENTIUM_4_FLAME_CCCR3                0x0000036B
+/// @}
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_IQ_CCCRn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_CCCR0);
+  AsmWriteMsr64 (MSR_PENTIUM_4_IQ_CCCR0, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_IQ_CCCR0 is defined as MSR_IQ_CCCR0 in SDM.
+        MSR_PENTIUM_4_IQ_CCCR1 is defined as MSR_IQ_CCCR1 in SDM.
+        MSR_PENTIUM_4_IQ_CCCR2 is defined as MSR_IQ_CCCR2 in SDM.
+        MSR_PENTIUM_4_IQ_CCCR3 is defined as MSR_IQ_CCCR3 in SDM.
+        MSR_PENTIUM_4_IQ_CCCR4 is defined as MSR_IQ_CCCR4 in SDM.
+        MSR_PENTIUM_4_IQ_CCCR5 is defined as MSR_IQ_CCCR5 in SDM.
+  @{
+**/
+#define MSR_PENTIUM_4_IQ_CCCR0                   0x0000036C
+#define MSR_PENTIUM_4_IQ_CCCR1                   0x0000036D
+#define MSR_PENTIUM_4_IQ_CCCR2                   0x0000036E
+#define MSR_PENTIUM_4_IQ_CCCR3                   0x0000036F
+#define MSR_PENTIUM_4_IQ_CCCR4                   0x00000370
+#define MSR_PENTIUM_4_IQ_CCCR5                   0x00000371
+/// @}
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_BSU_ESCR0 (0x000003A0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_BSU_ESCR0);
+  AsmWriteMsr64 (MSR_PENTIUM_4_BSU_ESCR0, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_BSU_ESCR0 is defined as MSR_BSU_ESCR0 in SDM.
+**/
+#define MSR_PENTIUM_4_BSU_ESCR0                  0x000003A0
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_BSU_ESCR1 (0x000003A1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_BSU_ESCR1);
+  AsmWriteMsr64 (MSR_PENTIUM_4_BSU_ESCR1, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_BSU_ESCR1 is defined as MSR_BSU_ESCR1 in SDM.
+**/
+#define MSR_PENTIUM_4_BSU_ESCR1                  0x000003A1
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_FSB_ESCR0 (0x000003A2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_FSB_ESCR0);
+  AsmWriteMsr64 (MSR_PENTIUM_4_FSB_ESCR0, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_FSB_ESCR0 is defined as MSR_FSB_ESCR0 in SDM.
+**/
+#define MSR_PENTIUM_4_FSB_ESCR0                  0x000003A2
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_FSB_ESCR1 (0x000003A3)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_FSB_ESCR1);
+  AsmWriteMsr64 (MSR_PENTIUM_4_FSB_ESCR1, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_FSB_ESCR1 is defined as MSR_FSB_ESCR1 in SDM.
+**/
+#define MSR_PENTIUM_4_FSB_ESCR1                  0x000003A3
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_FIRM_ESCR0 (0x000003A4)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_FIRM_ESCR0);
+  AsmWriteMsr64 (MSR_PENTIUM_4_FIRM_ESCR0, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_FIRM_ESCR0 is defined as MSR_FIRM_ESCR0 in SDM.
+**/
+#define MSR_PENTIUM_4_FIRM_ESCR0                 0x000003A4
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_FIRM_ESCR1 (0x000003A5)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_FIRM_ESCR1);
+  AsmWriteMsr64 (MSR_PENTIUM_4_FIRM_ESCR1, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_FIRM_ESCR1 is defined as MSR_FIRM_ESCR1 in SDM.
+**/
+#define MSR_PENTIUM_4_FIRM_ESCR1                 0x000003A5
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_FLAME_ESCR0 (0x000003A6)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_ESCR0);
+  AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_ESCR0, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_FLAME_ESCR0 is defined as MSR_FLAME_ESCR0 in SDM.
+**/
+#define MSR_PENTIUM_4_FLAME_ESCR0                0x000003A6
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_FLAME_ESCR1 (0x000003A7)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_ESCR1);
+  AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_ESCR1, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_FLAME_ESCR1 is defined as MSR_FLAME_ESCR1 in SDM.
+**/
+#define MSR_PENTIUM_4_FLAME_ESCR1                0x000003A7
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_DAC_ESCR0 (0x000003A8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_DAC_ESCR0);
+  AsmWriteMsr64 (MSR_PENTIUM_4_DAC_ESCR0, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_DAC_ESCR0 is defined as MSR_DAC_ESCR0 in SDM.
+**/
+#define MSR_PENTIUM_4_DAC_ESCR0                  0x000003A8
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_DAC_ESCR1 (0x000003A9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_DAC_ESCR1);
+  AsmWriteMsr64 (MSR_PENTIUM_4_DAC_ESCR1, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_DAC_ESCR1 is defined as MSR_DAC_ESCR1 in SDM.
+**/
+#define MSR_PENTIUM_4_DAC_ESCR1                  0x000003A9
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_MOB_ESCR0 (0x000003AA)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_MOB_ESCR0);
+  AsmWriteMsr64 (MSR_PENTIUM_4_MOB_ESCR0, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_MOB_ESCR0 is defined as MSR_MOB_ESCR0 in SDM.
+**/
+#define MSR_PENTIUM_4_MOB_ESCR0                  0x000003AA
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_MOB_ESCR1 (0x000003AB)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_MOB_ESCR1);
+  AsmWriteMsr64 (MSR_PENTIUM_4_MOB_ESCR1, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_MOB_ESCR1 is defined as MSR_MOB_ESCR1 in SDM.
+**/
+#define MSR_PENTIUM_4_MOB_ESCR1                  0x000003AB
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_PMH_ESCR0 (0x000003AC)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_PMH_ESCR0);
+  AsmWriteMsr64 (MSR_PENTIUM_4_PMH_ESCR0, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_PMH_ESCR0 is defined as MSR_PMH_ESCR0 in SDM.
+**/
+#define MSR_PENTIUM_4_PMH_ESCR0                  0x000003AC
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_PMH_ESCR1 (0x000003AD)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_PMH_ESCR1);
+  AsmWriteMsr64 (MSR_PENTIUM_4_PMH_ESCR1, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_PMH_ESCR1 is defined as MSR_PMH_ESCR1 in SDM.
+**/
+#define MSR_PENTIUM_4_PMH_ESCR1                  0x000003AD
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_SAAT_ESCR0 (0x000003AE)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_SAAT_ESCR0);
+  AsmWriteMsr64 (MSR_PENTIUM_4_SAAT_ESCR0, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_SAAT_ESCR0 is defined as MSR_SAAT_ESCR0 in SDM.
+**/
+#define MSR_PENTIUM_4_SAAT_ESCR0                 0x000003AE
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_SAAT_ESCR1 (0x000003AF)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_SAAT_ESCR1);
+  AsmWriteMsr64 (MSR_PENTIUM_4_SAAT_ESCR1, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_SAAT_ESCR1 is defined as MSR_SAAT_ESCR1 in SDM.
+**/
+#define MSR_PENTIUM_4_SAAT_ESCR1                 0x000003AF
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_U2L_ESCR0 (0x000003B0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_U2L_ESCR0);
+  AsmWriteMsr64 (MSR_PENTIUM_4_U2L_ESCR0, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_U2L_ESCR0 is defined as MSR_U2L_ESCR0 in SDM.
+**/
+#define MSR_PENTIUM_4_U2L_ESCR0                  0x000003B0
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_U2L_ESCR1 (0x000003B1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_U2L_ESCR1);
+  AsmWriteMsr64 (MSR_PENTIUM_4_U2L_ESCR1, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_U2L_ESCR1 is defined as MSR_U2L_ESCR1 in SDM.
+**/
+#define MSR_PENTIUM_4_U2L_ESCR1                  0x000003B1
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_BPU_ESCR0 (0x000003B2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_ESCR0);
+  AsmWriteMsr64 (MSR_PENTIUM_4_BPU_ESCR0, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_BPU_ESCR0 is defined as MSR_BPU_ESCR0 in SDM.
+**/
+#define MSR_PENTIUM_4_BPU_ESCR0                  0x000003B2
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_BPU_ESCR1 (0x000003B3)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_ESCR1);
+  AsmWriteMsr64 (MSR_PENTIUM_4_BPU_ESCR1, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_BPU_ESCR1 is defined as MSR_BPU_ESCR1 in SDM.
+**/
+#define MSR_PENTIUM_4_BPU_ESCR1                  0x000003B3
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_IS_ESCR0 (0x000003B4)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_IS_ESCR0);
+  AsmWriteMsr64 (MSR_PENTIUM_4_IS_ESCR0, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_IS_ESCR0 is defined as MSR_IS_ESCR0 in SDM.
+**/
+#define MSR_PENTIUM_4_IS_ESCR0                   0x000003B4
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_IS_ESCR1 (0x000003B5)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_IS_ESCR1);
+  AsmWriteMsr64 (MSR_PENTIUM_4_IS_ESCR1, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_IS_ESCR1 is defined as MSR_IS_ESCR1 in SDM.
+**/
+#define MSR_PENTIUM_4_IS_ESCR1                   0x000003B5
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_ITLB_ESCR0 (0x000003B6)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_ITLB_ESCR0);
+  AsmWriteMsr64 (MSR_PENTIUM_4_ITLB_ESCR0, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_ITLB_ESCR0 is defined as MSR_ITLB_ESCR0 in SDM.
+**/
+#define MSR_PENTIUM_4_ITLB_ESCR0                 0x000003B6
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_ITLB_ESCR1 (0x000003B7)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_ITLB_ESCR1);
+  AsmWriteMsr64 (MSR_PENTIUM_4_ITLB_ESCR1, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_ITLB_ESCR1 is defined as MSR_ITLB_ESCR1 in SDM.
+**/
+#define MSR_PENTIUM_4_ITLB_ESCR1                 0x000003B7
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_CRU_ESCR0 (0x000003B8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_CRU_ESCR0);
+  AsmWriteMsr64 (MSR_PENTIUM_4_CRU_ESCR0, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_CRU_ESCR0 is defined as MSR_CRU_ESCR0 in SDM.
+**/
+#define MSR_PENTIUM_4_CRU_ESCR0                  0x000003B8
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_CRU_ESCR1 (0x000003B9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_CRU_ESCR1);
+  AsmWriteMsr64 (MSR_PENTIUM_4_CRU_ESCR1, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_CRU_ESCR1 is defined as MSR_CRU_ESCR1 in SDM.
+**/
+#define MSR_PENTIUM_4_CRU_ESCR1                  0x000003B9
+
+
+/**
+  0, 1, 2. Shared. See Section 18.6.3.1, "ESCR MSRs." This MSR is not
+  available on later processors. It is only available on processor family 0FH,
+  models 01H-02H.
+
+  @param  ECX  MSR_PENTIUM_4_IQ_ESCR0 (0x000003BA)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_ESCR0);
+  AsmWriteMsr64 (MSR_PENTIUM_4_IQ_ESCR0, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_IQ_ESCR0 is defined as MSR_IQ_ESCR0 in SDM.
+**/
+#define MSR_PENTIUM_4_IQ_ESCR0                   0x000003BA
+
+
+/**
+  0, 1, 2. Shared. See Section 18.6.3.1, "ESCR MSRs." This MSR is not
+  available on later processors. It is only available on processor family 0FH,
+  models 01H-02H.
+
+  @param  ECX  MSR_PENTIUM_4_IQ_ESCR1 (0x000003BB)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_ESCR1);
+  AsmWriteMsr64 (MSR_PENTIUM_4_IQ_ESCR1, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_IQ_ESCR1 is defined as MSR_IQ_ESCR1 in SDM.
+**/
+#define MSR_PENTIUM_4_IQ_ESCR1                   0x000003BB
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_RAT_ESCR0 (0x000003BC)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_RAT_ESCR0);
+  AsmWriteMsr64 (MSR_PENTIUM_4_RAT_ESCR0, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_RAT_ESCR0 is defined as MSR_RAT_ESCR0 in SDM.
+**/
+#define MSR_PENTIUM_4_RAT_ESCR0                  0x000003BC
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_RAT_ESCR1 (0x000003BD)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_RAT_ESCR1);
+  AsmWriteMsr64 (MSR_PENTIUM_4_RAT_ESCR1, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_RAT_ESCR1 is defined as MSR_RAT_ESCR1 in SDM.
+**/
+#define MSR_PENTIUM_4_RAT_ESCR1                  0x000003BD
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_SSU_ESCR0 (0x000003BE)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_SSU_ESCR0);
+  AsmWriteMsr64 (MSR_PENTIUM_4_SSU_ESCR0, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_SSU_ESCR0 is defined as MSR_SSU_ESCR0 in SDM.
+**/
+#define MSR_PENTIUM_4_SSU_ESCR0                  0x000003BE
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_MS_ESCR0 (0x000003C0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_ESCR0);
+  AsmWriteMsr64 (MSR_PENTIUM_4_MS_ESCR0, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_MS_ESCR0 is defined as MSR_MS_ESCR0 in SDM.
+**/
+#define MSR_PENTIUM_4_MS_ESCR0                   0x000003C0
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_MS_ESCR1 (0x000003C1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_ESCR1);
+  AsmWriteMsr64 (MSR_PENTIUM_4_MS_ESCR1, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_MS_ESCR1 is defined as MSR_MS_ESCR1 in SDM.
+**/
+#define MSR_PENTIUM_4_MS_ESCR1                   0x000003C1
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_TBPU_ESCR0 (0x000003C2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_TBPU_ESCR0);
+  AsmWriteMsr64 (MSR_PENTIUM_4_TBPU_ESCR0, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_TBPU_ESCR0 is defined as MSR_TBPU_ESCR0 in SDM.
+**/
+#define MSR_PENTIUM_4_TBPU_ESCR0                 0x000003C2
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_TBPU_ESCR1 (0x000003C3)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_TBPU_ESCR1);
+  AsmWriteMsr64 (MSR_PENTIUM_4_TBPU_ESCR1, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_TBPU_ESCR1 is defined as MSR_TBPU_ESCR1 in SDM.
+**/
+#define MSR_PENTIUM_4_TBPU_ESCR1                 0x000003C3
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_TC_ESCR0 (0x000003C4)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_ESCR0);
+  AsmWriteMsr64 (MSR_PENTIUM_4_TC_ESCR0, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_TC_ESCR0 is defined as MSR_TC_ESCR0 in SDM.
+**/
+#define MSR_PENTIUM_4_TC_ESCR0                   0x000003C4
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_TC_ESCR1 (0x000003C5)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_ESCR1);
+  AsmWriteMsr64 (MSR_PENTIUM_4_TC_ESCR1, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_TC_ESCR1 is defined as MSR_TC_ESCR1 in SDM.
+**/
+#define MSR_PENTIUM_4_TC_ESCR1                   0x000003C5
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_IX_ESCR0 (0x000003C8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_IX_ESCR0);
+  AsmWriteMsr64 (MSR_PENTIUM_4_IX_ESCR0, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_IX_ESCR0 is defined as MSR_IX_ESCR0 in SDM.
+**/
+#define MSR_PENTIUM_4_IX_ESCR0                   0x000003C8
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_IX_ESCR1 (0x000003C9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_IX_ESCR1);
+  AsmWriteMsr64 (MSR_PENTIUM_4_IX_ESCR1, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_IX_ESCR1 is defined as MSR_IX_ESCR1 in SDM.
+**/
+#define MSR_PENTIUM_4_IX_ESCR1                   0x000003C9
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_ALF_ESCRn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_ALF_ESCR0);
+  AsmWriteMsr64 (MSR_PENTIUM_4_ALF_ESCR0, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_ALF_ESCR0 is defined as MSR_ALF_ESCR0 in SDM.
+        MSR_PENTIUM_4_ALF_ESCR1 is defined as MSR_ALF_ESCR1 in SDM.
+        MSR_PENTIUM_4_CRU_ESCR2 is defined as MSR_CRU_ESCR2 in SDM.
+        MSR_PENTIUM_4_CRU_ESCR3 is defined as MSR_CRU_ESCR3 in SDM.
+        MSR_PENTIUM_4_CRU_ESCR4 is defined as MSR_CRU_ESCR4 in SDM.
+        MSR_PENTIUM_4_CRU_ESCR5 is defined as MSR_CRU_ESCR5 in SDM.
+  @{
+**/
+#define MSR_PENTIUM_4_ALF_ESCR0                  0x000003CA
+#define MSR_PENTIUM_4_ALF_ESCR1                  0x000003CB
+#define MSR_PENTIUM_4_CRU_ESCR2                  0x000003CC
+#define MSR_PENTIUM_4_CRU_ESCR3                  0x000003CD
+#define MSR_PENTIUM_4_CRU_ESCR4                  0x000003E0
+#define MSR_PENTIUM_4_CRU_ESCR5                  0x000003E1
+/// @}
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".
+
+  @param  ECX  MSR_PENTIUM_4_TC_PRECISE_EVENT (0x000003F0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_PRECISE_EVENT);
+  AsmWriteMsr64 (MSR_PENTIUM_4_TC_PRECISE_EVENT, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_TC_PRECISE_EVENT is defined as MSR_TC_PRECISE_EVENT in SDM.
+**/
+#define MSR_PENTIUM_4_TC_PRECISE_EVENT           0x000003F0
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. Processor Event Based Sampling (PEBS) (R/W)
+  Controls the enabling of processor event sampling and replay tagging.
+
+  @param  ECX  MSR_PENTIUM_4_PEBS_ENABLE (0x000003F1)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_PENTIUM_4_PEBS_ENABLE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_PENTIUM_4_PEBS_ENABLE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_PENTIUM_4_PEBS_ENABLE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_PEBS_ENABLE);
+  AsmWriteMsr64 (MSR_PENTIUM_4_PEBS_ENABLE, Msr.Uint64);
+  @endcode
+  @note MSR_PENTIUM_4_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
+**/
+#define MSR_PENTIUM_4_PEBS_ENABLE                0x000003F1
+
+/**
+  MSR information returned for MSR index #MSR_PENTIUM_4_PEBS_ENABLE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 12:0] See Table 19-36.
+    ///
+    UINT32  EventNum:13;
+    UINT32  Reserved1:11;
+    ///
+    /// [Bit 24] UOP Tag  Enables replay tagging when set.
+    ///
+    UINT32  UOP:1;
+    ///
+    /// [Bit 25] ENABLE_PEBS_MY_THR (R/W) Enables PEBS for the target logical
+    /// processor when set; disables PEBS when clear (default). See Section
+    /// 18.6.4.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target
+    /// logical processor. This bit is called ENABLE_PEBS in IA-32 processors
+    /// that do not support Intel HyperThreading Technology.
+    ///
+    UINT32  ENABLE_PEBS_MY_THR:1;
+    ///
+    /// [Bit 26] ENABLE_PEBS_OTH_THR (R/W) Enables PEBS for the target logical
+    /// processor when set; disables PEBS when clear (default). See Section
+    /// 18.6.4.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target
+    /// logical processor. This bit is reserved for IA-32 processors that do
+    /// not support Intel Hyper-Threading Technology.
+    ///
+    UINT32  ENABLE_PEBS_OTH_THR:1;
+    UINT32  Reserved2:5;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_PENTIUM_4_PEBS_ENABLE_REGISTER;
+
+
+/**
+  0, 1, 2, 3, 4, 6. Shared. See Table 19-36.
+
+  @param  ECX  MSR_PENTIUM_4_PEBS_MATRIX_VERT (0x000003F2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_PEBS_MATRIX_VERT);
+  AsmWriteMsr64 (MSR_PENTIUM_4_PEBS_MATRIX_VERT, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_PEBS_MATRIX_VERT is defined as MSR_PEBS_MATRIX_VERT in SDM.
+**/
+#define MSR_PENTIUM_4_PEBS_MATRIX_VERT           0x000003F2
+
+
+/**
+  3, 4, 6. Unique. Last Branch Record n (R/W)  One of 16 pairs of last branch
+  record registers on the last branch record stack (680H-68FH). This part of
+  the stack contains pointers to the source instruction for one of the last 16
+  branches, exceptions, or interrupts taken by the processor. The MSRs at
+  680H-68FH, 6C0H-6CfH are not available in processor releases before family
+  0FH, model 03H. These MSRs replace MSRs previously located at
+  1DBH-1DEH.which performed the same function for early releases. See Section
+  17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for
+  Processors based on Skylake Microarchitecture.".
+
+  @param  ECX  MSR_PENTIUM_4_LASTBRANCH_n_FROM_IP
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP);
+  AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP  is defined as MSR_LASTBRANCH_0_FROM_IP  in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP  is defined as MSR_LASTBRANCH_1_FROM_IP  in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP  is defined as MSR_LASTBRANCH_2_FROM_IP  in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP  is defined as MSR_LASTBRANCH_3_FROM_IP  in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP  is defined as MSR_LASTBRANCH_4_FROM_IP  in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP  is defined as MSR_LASTBRANCH_5_FROM_IP  in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP  is defined as MSR_LASTBRANCH_6_FROM_IP  in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP  is defined as MSR_LASTBRANCH_7_FROM_IP  in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP  is defined as MSR_LASTBRANCH_8_FROM_IP  in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP  is defined as MSR_LASTBRANCH_9_FROM_IP  in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.
+  @{
+**/
+#define MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP       0x00000680
+#define MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP       0x00000681
+#define MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP       0x00000682
+#define MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP       0x00000683
+#define MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP       0x00000684
+#define MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP       0x00000685
+#define MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP       0x00000686
+#define MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP       0x00000687
+#define MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP       0x00000688
+#define MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP       0x00000689
+#define MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP      0x0000068A
+#define MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP      0x0000068B
+#define MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP      0x0000068C
+#define MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP      0x0000068D
+#define MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP      0x0000068E
+#define MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP      0x0000068F
+/// @}
+
+
+/**
+  3, 4, 6. Unique. Last Branch Record n (R/W)  One of 16 pairs of last branch
+  record registers on the last branch record stack (6C0H-6CFH). This part of
+  the stack contains pointers to the destination instruction for one of the
+  last 16 branches, exceptions, or interrupts that the processor took. See
+  Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording
+  for Processors based on Skylake Microarchitecture.".
+
+  @param  ECX  MSR_PENTIUM_4_LASTBRANCH_n_TO_IP
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP);
+  AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_LASTBRANCH_0_TO_IP  is defined as MSR_LASTBRANCH_0_TO_IP  in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_1_TO_IP  is defined as MSR_LASTBRANCH_1_TO_IP  in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_2_TO_IP  is defined as MSR_LASTBRANCH_2_TO_IP  in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_3_TO_IP  is defined as MSR_LASTBRANCH_3_TO_IP  in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_4_TO_IP  is defined as MSR_LASTBRANCH_4_TO_IP  in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_5_TO_IP  is defined as MSR_LASTBRANCH_5_TO_IP  in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_6_TO_IP  is defined as MSR_LASTBRANCH_6_TO_IP  in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_7_TO_IP  is defined as MSR_LASTBRANCH_7_TO_IP  in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_8_TO_IP  is defined as MSR_LASTBRANCH_8_TO_IP  in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_9_TO_IP  is defined as MSR_LASTBRANCH_9_TO_IP  in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM.
+        MSR_PENTIUM_4_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.
+  @{
+**/
+#define MSR_PENTIUM_4_LASTBRANCH_0_TO_IP         0x000006C0
+#define MSR_PENTIUM_4_LASTBRANCH_1_TO_IP         0x000006C1
+#define MSR_PENTIUM_4_LASTBRANCH_2_TO_IP         0x000006C2
+#define MSR_PENTIUM_4_LASTBRANCH_3_TO_IP         0x000006C3
+#define MSR_PENTIUM_4_LASTBRANCH_4_TO_IP         0x000006C4
+#define MSR_PENTIUM_4_LASTBRANCH_5_TO_IP         0x000006C5
+#define MSR_PENTIUM_4_LASTBRANCH_6_TO_IP         0x000006C6
+#define MSR_PENTIUM_4_LASTBRANCH_7_TO_IP         0x000006C7
+#define MSR_PENTIUM_4_LASTBRANCH_8_TO_IP         0x000006C8
+#define MSR_PENTIUM_4_LASTBRANCH_9_TO_IP         0x000006C9
+#define MSR_PENTIUM_4_LASTBRANCH_10_TO_IP        0x000006CA
+#define MSR_PENTIUM_4_LASTBRANCH_11_TO_IP        0x000006CB
+#define MSR_PENTIUM_4_LASTBRANCH_12_TO_IP        0x000006CC
+#define MSR_PENTIUM_4_LASTBRANCH_13_TO_IP        0x000006CD
+#define MSR_PENTIUM_4_LASTBRANCH_14_TO_IP        0x000006CE
+#define MSR_PENTIUM_4_LASTBRANCH_15_TO_IP        0x000006CF
+/// @}
+
+
+/**
+  3, 4. Shared. IFSB BUSQ Event Control and Counter Register (R/W) See Section
+  18.6.6, "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to
+  8-MByte L3 Cache.".
+
+  @param  ECX  MSR_PENTIUM_4_IFSB_BUSQ0 (0x000107CC)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_BUSQ0);
+  AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_BUSQ0, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_IFSB_BUSQ0 is defined as MSR_IFSB_BUSQ0 in SDM.
+**/
+#define MSR_PENTIUM_4_IFSB_BUSQ0                 0x000107CC
+
+
+/**
+  3, 4. Shared. IFSB BUSQ Event Control and Counter Register (R/W).
+
+  @param  ECX  MSR_PENTIUM_4_IFSB_BUSQ1 (0x000107CD)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_BUSQ1);
+  AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_BUSQ1, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_IFSB_BUSQ1 is defined as MSR_IFSB_BUSQ1 in SDM.
+**/
+#define MSR_PENTIUM_4_IFSB_BUSQ1                 0x000107CD
+
+
+/**
+  3, 4. Shared. IFSB SNPQ Event Control and Counter Register (R/W) See Section
+  18.6.6, "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to
+  8-MByte L3 Cache.".
+
+  @param  ECX  MSR_PENTIUM_4_IFSB_SNPQ0 (0x000107CE)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_SNPQ0);
+  AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_SNPQ0, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_IFSB_SNPQ0 is defined as MSR_IFSB_SNPQ0 in SDM.
+**/
+#define MSR_PENTIUM_4_IFSB_SNPQ0                 0x000107CE
+
+
+/**
+  3, 4. Shared. IFSB SNPQ Event Control and Counter Register (R/W).
+
+  @param  ECX  MSR_PENTIUM_4_IFSB_SNPQ1 (0x000107CF)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_SNPQ1);
+  AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_SNPQ1, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_IFSB_SNPQ1 is defined as MSR_IFSB_SNPQ1 in SDM.
+**/
+#define MSR_PENTIUM_4_IFSB_SNPQ1                 0x000107CF
+
+
+/**
+  3, 4. Shared. EFSB DRDY Event Control and Counter Register (R/W) See Section
+  18.6.6, "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to
+  8-MByte L3 Cache.".
+
+  @param  ECX  MSR_PENTIUM_4_EFSB_DRDY0 (0x000107D0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_EFSB_DRDY0);
+  AsmWriteMsr64 (MSR_PENTIUM_4_EFSB_DRDY0, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_EFSB_DRDY0 is defined as MSR_EFSB_DRDY0 in SDM.
+**/
+#define MSR_PENTIUM_4_EFSB_DRDY0                 0x000107D0
+
+
+/**
+  3, 4. Shared. EFSB DRDY Event Control and Counter Register (R/W).
+
+  @param  ECX  MSR_PENTIUM_4_EFSB_DRDY1 (0x000107D1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_EFSB_DRDY1);
+  AsmWriteMsr64 (MSR_PENTIUM_4_EFSB_DRDY1, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_EFSB_DRDY1 is defined as MSR_EFSB_DRDY1 in SDM.
+**/
+#define MSR_PENTIUM_4_EFSB_DRDY1                 0x000107D1
+
+
+/**
+  3, 4. Shared. IFSB Latency Event Control Register (R/W) See Section 18.6.6,
+  "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to 8-MByte
+  L3 Cache.".
+
+  @param  ECX  MSR_PENTIUM_4_IFSB_CTL6 (0x000107D2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_CTL6);
+  AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_CTL6, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_IFSB_CTL6 is defined as MSR_IFSB_CTL6 in SDM.
+**/
+#define MSR_PENTIUM_4_IFSB_CTL6                  0x000107D2
+
+
+/**
+  3, 4. Shared. IFSB Latency Event Counter Register (R/W) See Section 18.6.6,
+  "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to 8-MByte
+  L3 Cache.".
+
+  @param  ECX  MSR_PENTIUM_4_IFSB_CNTR7 (0x000107D3)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_CNTR7);
+  AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_CNTR7, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_IFSB_CNTR7 is defined as MSR_IFSB_CNTR7 in SDM.
+**/
+#define MSR_PENTIUM_4_IFSB_CNTR7                 0x000107D3
+
+
+/**
+  6. Shared. GBUSQ Event Control and Counter Register (R/W) See Section
+  18.6.6, "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to
+  8MByte L3 Cache.".
+
+  @param  ECX  MSR_PENTIUM_4_EMON_L3_CTR_CTL0 (0x000107CC)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL0);
+  AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL0, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_EMON_L3_CTR_CTL0 is defined as MSR_EMON_L3_CTR_CTL0 in SDM.
+**/
+#define MSR_PENTIUM_4_EMON_L3_CTR_CTL0           0x000107CC
+
+
+/**
+  6. Shared. GBUSQ Event Control and Counter Register (R/W).
+
+  @param  ECX  MSR_PENTIUM_4_EMON_L3_CTR_CTL1 (0x000107CD)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL1);
+  AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL1, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_EMON_L3_CTR_CTL1 is defined as MSR_EMON_L3_CTR_CTL1 in SDM.
+**/
+#define MSR_PENTIUM_4_EMON_L3_CTR_CTL1           0x000107CD
+
+
+/**
+  6. Shared. GSNPQ Event Control and Counter Register (R/W) See Section
+  18.6.6, "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to
+  8MByte L3 Cache.".
+
+  @param  ECX  MSR_PENTIUM_4_EMON_L3_CTR_CTL2 (0x000107CE)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL2);
+  AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL2, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_EMON_L3_CTR_CTL2 is defined as MSR_EMON_L3_CTR_CTL2 in SDM.
+**/
+#define MSR_PENTIUM_4_EMON_L3_CTR_CTL2           0x000107CE
+
+
+/**
+  6. Shared. GSNPQ Event Control and Counter Register (R/W).
+
+  @param  ECX  MSR_PENTIUM_4_EMON_L3_CTR_CTL3 (0x000107CF)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL3);
+  AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL3, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_EMON_L3_CTR_CTL3 is defined as MSR_EMON_L3_CTR_CTL3 in SDM.
+**/
+#define MSR_PENTIUM_4_EMON_L3_CTR_CTL3           0x000107CF
+
+
+/**
+  6. Shared. FSB Event Control and Counter Register (R/W) See Section 18.6.6,
+  "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8MByte
+  L3 Cache.".
+
+  @param  ECX  MSR_PENTIUM_4_EMON_L3_CTR_CTL4 (0x000107D0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL4);
+  AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL4, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_EMON_L3_CTR_CTL4 is defined as MSR_EMON_L3_CTR_CTL4 in SDM.
+**/
+#define MSR_PENTIUM_4_EMON_L3_CTR_CTL4           0x000107D0
+
+
+/**
+  6. Shared. FSB Event Control and Counter Register (R/W).
+
+  @param  ECX  MSR_PENTIUM_4_EMON_L3_CTR_CTL5 (0x000107D1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL5);
+  AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL5, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_EMON_L3_CTR_CTL5 is defined as MSR_EMON_L3_CTR_CTL5 in SDM.
+**/
+#define MSR_PENTIUM_4_EMON_L3_CTR_CTL5           0x000107D1
+
+
+/**
+  6. Shared. FSB Event Control and Counter Register (R/W).
+
+  @param  ECX  MSR_PENTIUM_4_EMON_L3_CTR_CTL6 (0x000107D2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL6);
+  AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL6, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_EMON_L3_CTR_CTL6 is defined as MSR_EMON_L3_CTR_CTL6 in SDM.
+**/
+#define MSR_PENTIUM_4_EMON_L3_CTR_CTL6           0x000107D2
+
+
+/**
+  6. Shared. FSB Event Control and Counter Register (R/W).
+
+  @param  ECX  MSR_PENTIUM_4_EMON_L3_CTR_CTL7 (0x000107D3)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL7);
+  AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL7, Msr);
+  @endcode
+  @note MSR_PENTIUM_4_EMON_L3_CTR_CTL7 is defined as MSR_EMON_L3_CTR_CTL7 in SDM.
+**/
+#define MSR_PENTIUM_4_EMON_L3_CTR_CTL7           0x000107D3
+
+#endif
diff --git a/MdePkg/Include/Register/Intel/Msr/PentiumMMsr.h b/MdePkg/Include/Register/Intel/Msr/PentiumMMsr.h
new file mode 100644
index 000000000000..e2944f38a1b8
--- /dev/null
+++ b/MdePkg/Include/Register/Intel/Msr/PentiumMMsr.h
@@ -0,0 +1,678 @@
+/** @file
+  MSR Definitions for Pentium M Processors.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+  May 2018, Volume 4: Model-Specific-Registers (MSR)
+
+**/
+
+#ifndef __PENTIUM_M_MSR_H__
+#define __PENTIUM_M_MSR_H__
+
+#include <Register/Intel/ArchitecturalMsr.h>
+
+/**
+  Is Pentium M Processors?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_PENTIUM_M_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   ( \
+    DisplayModel == 0x0D \
+    ) \
+   )
+
+/**
+  See Section 2.22, "MSRs in Pentium Processors.".
+
+  @param  ECX  MSR_PENTIUM_M_P5_MC_ADDR (0x00000000)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_ADDR);
+  AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_ADDR, Msr);
+  @endcode
+  @note MSR_PENTIUM_M_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.
+**/
+#define MSR_PENTIUM_M_P5_MC_ADDR                 0x00000000
+
+
+/**
+  See Section 2.22, "MSRs in Pentium Processors.".
+
+  @param  ECX  MSR_PENTIUM_M_P5_MC_TYPE (0x00000001)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_TYPE);
+  AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_TYPE, Msr);
+  @endcode
+  @note MSR_PENTIUM_M_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.
+**/
+#define MSR_PENTIUM_M_P5_MC_TYPE                 0x00000001
+
+
+/**
+  Processor Hard Power-On Configuration (R/W) Enables and disables processor
+  features. (R) Indicates current processor configuration.
+
+  @param  ECX  MSR_PENTIUM_M_EBL_CR_POWERON (0x0000002A)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON);
+  AsmWriteMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON, Msr.Uint64);
+  @endcode
+  @note MSR_PENTIUM_M_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
+**/
+#define MSR_PENTIUM_M_EBL_CR_POWERON             0x0000002A
+
+/**
+  MSR information returned for MSR index #MSR_PENTIUM_M_EBL_CR_POWERON
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 1] Data Error Checking Enable (R) 0 = Disabled Always 0 on the
+    /// Pentium M processor.
+    ///
+    UINT32  DataErrorCheckingEnable:1;
+    ///
+    /// [Bit 2] Response Error Checking Enable (R) 0 = Disabled Always 0 on
+    /// the Pentium M processor.
+    ///
+    UINT32  ResponseErrorCheckingEnable:1;
+    ///
+    /// [Bit 3] MCERR# Drive Enable (R)  0 = Disabled Always 0 on the Pentium
+    /// M processor.
+    ///
+    UINT32  MCERR_DriveEnable:1;
+    ///
+    /// [Bit 4] Address Parity Enable (R) 0 = Disabled Always 0 on the Pentium
+    /// M processor.
+    ///
+    UINT32  AddressParityEnable:1;
+    UINT32  Reserved2:2;
+    ///
+    /// [Bit 7] BINIT# Driver Enable (R) 1 = Enabled; 0 = Disabled Always 0 on
+    /// the Pentium M processor.
+    ///
+    UINT32  BINIT_DriverEnable:1;
+    ///
+    /// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.
+    ///
+    UINT32  OutputTriStateEnable:1;
+    ///
+    /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
+    ///
+    UINT32  ExecuteBIST:1;
+    ///
+    /// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
+    /// Always 0 on the Pentium M processor.
+    ///
+    UINT32  MCERR_ObservationEnabled:1;
+    UINT32  Reserved3:1;
+    ///
+    /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
+    /// Always 0 on the Pentium M processor.
+    ///
+    UINT32  BINIT_ObservationEnabled:1;
+    UINT32  Reserved4:1;
+    ///
+    /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes
+    /// Always 0 on the Pentium M processor.
+    ///
+    UINT32  ResetVector:1;
+    UINT32  Reserved5:1;
+    ///
+    /// [Bits 17:16] APIC Cluster ID (R/O) Always 00B on the Pentium M
+    /// processor.
+    ///
+    UINT32  APICClusterID:2;
+    ///
+    /// [Bit 18] System Bus Frequency (R/O) 1. = 100 MHz 2. = Reserved Always
+    /// 0 on the Pentium M processor.
+    ///
+    UINT32  SystemBusFrequency:1;
+    UINT32  Reserved6:1;
+    ///
+    /// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B on the Pentium
+    /// M processor.
+    ///
+    UINT32  SymmetricArbitrationID:2;
+    ///
+    /// [Bits 26:22] Clock Frequency Ratio (R/O).
+    ///
+    UINT32  ClockFrequencyRatio:5;
+    UINT32  Reserved7:5;
+    UINT32  Reserved8:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER;
+
+
+/**
+  Last Branch Record n (R/W) One of 8 last branch record registers on the last
+  branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold
+  the to address. See also: -  Last Branch Record Stack TOS at 1C9H -  Section
+  17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M
+  Processors)".
+
+  @param  ECX  MSR_PENTIUM_M_LASTBRANCH_n
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_0);
+  AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_0, Msr);
+  @endcode
+  @note MSR_PENTIUM_M_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM.
+        MSR_PENTIUM_M_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM.
+        MSR_PENTIUM_M_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM.
+        MSR_PENTIUM_M_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.
+        MSR_PENTIUM_M_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM.
+        MSR_PENTIUM_M_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM.
+        MSR_PENTIUM_M_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM.
+        MSR_PENTIUM_M_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.
+  @{
+**/
+#define MSR_PENTIUM_M_LASTBRANCH_0               0x00000040
+#define MSR_PENTIUM_M_LASTBRANCH_1               0x00000041
+#define MSR_PENTIUM_M_LASTBRANCH_2               0x00000042
+#define MSR_PENTIUM_M_LASTBRANCH_3               0x00000043
+#define MSR_PENTIUM_M_LASTBRANCH_4               0x00000044
+#define MSR_PENTIUM_M_LASTBRANCH_5               0x00000045
+#define MSR_PENTIUM_M_LASTBRANCH_6               0x00000046
+#define MSR_PENTIUM_M_LASTBRANCH_7               0x00000047
+/// @}
+
+
+/**
+  Reserved.
+
+  @param  ECX  MSR_PENTIUM_M_BBL_CR_CTL (0x00000119)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL);
+  AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL, Msr);
+  @endcode
+  @note MSR_PENTIUM_M_BBL_CR_CTL is defined as MSR_BBL_CR_CTL in SDM.
+**/
+#define MSR_PENTIUM_M_BBL_CR_CTL                 0x00000119
+
+
+/**
+
+
+  @param  ECX  MSR_PENTIUM_M_BBL_CR_CTL3 (0x0000011E)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3);
+  AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3, Msr.Uint64);
+  @endcode
+  @note MSR_PENTIUM_M_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
+**/
+#define MSR_PENTIUM_M_BBL_CR_CTL3                0x0000011E
+
+/**
+  MSR information returned for MSR index #MSR_PENTIUM_M_BBL_CR_CTL3
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
+    /// Indicates if the L2 is hardware-disabled.
+    ///
+    UINT32  L2HardwareEnabled:1;
+    UINT32  Reserved1:4;
+    ///
+    /// [Bit 5] ECC Check Enable (RO) This bit enables ECC checking on the
+    /// cache data bus. ECC is always generated on write cycles. 1. = Disabled
+    /// (default) 2. = Enabled For the Pentium M processor, ECC checking on
+    /// the cache data bus is always enabled.
+    ///
+    UINT32  ECCCheckEnable:1;
+    UINT32  Reserved2:2;
+    ///
+    /// [Bit 8] L2 Enabled (R/W)  1 = L2 cache has been initialized 0 =
+    /// Disabled (default) Until this bit is set the processor will not
+    /// respond to the WBINVD instruction or the assertion of the FLUSH# input.
+    ///
+    UINT32  L2Enabled:1;
+    UINT32  Reserved3:14;
+    ///
+    /// [Bit 23] L2 Not Present (RO)  1. = L2 Present 2. = L2 Not Present.
+    ///
+    UINT32  L2NotPresent:1;
+    UINT32  Reserved4:8;
+    UINT32  Reserved5:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER;
+
+
+/**
+
+
+  @param  ECX  MSR_PENTIUM_M_THERM2_CTL (0x0000019D)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_PENTIUM_M_THERM2_CTL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_PENTIUM_M_THERM2_CTL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_PENTIUM_M_THERM2_CTL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_THERM2_CTL);
+  AsmWriteMsr64 (MSR_PENTIUM_M_THERM2_CTL, Msr.Uint64);
+  @endcode
+  @note MSR_PENTIUM_M_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
+**/
+#define MSR_PENTIUM_M_THERM2_CTL                 0x0000019D
+
+/**
+  MSR information returned for MSR index #MSR_PENTIUM_M_THERM2_CTL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:16;
+    ///
+    /// [Bit 16] TM_SELECT (R/W)  Mode of automatic thermal monitor: 1. =
+    /// Thermal Monitor 1 (thermally-initiated on-die modulation of the
+    /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated
+    /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is
+    /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled.
+    ///
+    UINT32  TM_SELECT:1;
+    UINT32  Reserved2:15;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_PENTIUM_M_THERM2_CTL_REGISTER;
+
+
+/**
+  Enable Miscellaneous Processor Features (R/W) Allows a variety of processor
+  functions to be enabled and disabled.
+
+  @param  ECX  MSR_PENTIUM_M_IA32_MISC_ENABLE (0x000001A0)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE);
+  AsmWriteMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE, Msr.Uint64);
+  @endcode
+  @note MSR_PENTIUM_M_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
+**/
+#define MSR_PENTIUM_M_IA32_MISC_ENABLE           0x000001A0
+
+/**
+  MSR information returned for MSR index #MSR_PENTIUM_M_IA32_MISC_ENABLE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:3;
+    ///
+    /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W)  1 = Setting
+    /// this bit enables the thermal control circuit (TCC) portion of the
+    /// Intel Thermal Monitor feature. This allows processor clocks to be
+    /// automatically modulated based on the processor's thermal sensor
+    /// operation. 0 = Disabled (default). The automatic thermal control
+    /// circuit enable bit determines if the thermal control circuit (TCC)
+    /// will be activated when the processor's internal thermal sensor
+    /// determines the processor is about to exceed its maximum operating
+    /// temperature. When the TCC is activated and TM1 is enabled, the
+    /// processors clocks will be forced to a 50% duty cycle. BIOS must enable
+    /// this feature. The bit should not be confused with the on-demand
+    /// thermal control circuit enable bit.
+    ///
+    UINT32  AutomaticThermalControlCircuit:1;
+    UINT32  Reserved2:3;
+    ///
+    /// [Bit 7] Performance Monitoring Available (R)  1 = Performance
+    /// monitoring enabled 0 = Performance monitoring disabled.
+    ///
+    UINT32  PerformanceMonitoring:1;
+    UINT32  Reserved3:2;
+    ///
+    /// [Bit 10] FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by the
+    /// processor to indicate a pending break event within the processor 0 =
+    /// Indicates compatible FERR# signaling behavior This bit must be set to
+    /// 1 to support XAPIC interrupt model usage.
+    ///   **Branch Trace Storage Unavailable (RO)** 1 = Processor doesn't
+    ///   support branch trace storage (BTS) 0 = BTS is supported
+    ///
+    UINT32  FERR:1;
+    ///
+    /// [Bit 11] Branch Trace Storage Unavailable (RO)
+    /// 1 = Processor doesn't support branch trace storage (BTS)
+    /// 0 = BTS is supported
+    ///
+    UINT32  BTS:1;
+    ///
+    /// [Bit 12] Processor Event Based Sampling Unavailable (RO)  1 =
+    /// Processor does not support processor event based sampling (PEBS); 0 =
+    /// PEBS is supported. The Pentium M processor does not support PEBS.
+    ///
+    UINT32  PEBS:1;
+    UINT32  Reserved5:3;
+    ///
+    /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W)  1 =
+    /// Enhanced Intel SpeedStep Technology enabled. On the Pentium M
+    /// processor, this bit may be configured to be read-only.
+    ///
+    UINT32  EIST:1;
+    UINT32  Reserved6:6;
+    ///
+    /// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are
+    /// disabled. xTPR messages are optional messages that allow the processor
+    /// to inform the chipset of its priority. The default is processor
+    /// specific.
+    ///
+    UINT32  xTPR_Message_Disable:1;
+    UINT32  Reserved7:8;
+    UINT32  Reserved8:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER;
+
+
+/**
+  Last Branch Record Stack TOS (R/W)  Contains an index (bits 0-3) that points
+  to the MSR containing the most recent branch record. See also: -
+  MSR_LASTBRANCH_0_FROM_IP (at 40H) -  Section 17.13, "Last Branch, Interrupt,
+  and Exception Recording (Pentium M Processors)".
+
+  @param  ECX  MSR_PENTIUM_M_LASTBRANCH_TOS (0x000001C9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS);
+  AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS, Msr);
+  @endcode
+  @note MSR_PENTIUM_M_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
+**/
+#define MSR_PENTIUM_M_LASTBRANCH_TOS             0x000001C9
+
+
+/**
+  Debug Control (R/W)  Controls how several debug features are used. Bit
+  definitions are discussed in the referenced section. See Section 17.15,
+  "Last Branch, Interrupt, and Exception Recording (Pentium M Processors).".
+
+  @param  ECX  MSR_PENTIUM_M_DEBUGCTLB (0x000001D9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_M_DEBUGCTLB);
+  AsmWriteMsr64 (MSR_PENTIUM_M_DEBUGCTLB, Msr);
+  @endcode
+  @note MSR_PENTIUM_M_DEBUGCTLB is defined as MSR_DEBUGCTLB in SDM.
+**/
+#define MSR_PENTIUM_M_DEBUGCTLB                  0x000001D9
+
+
+/**
+  Last Exception Record To Linear IP (R)  This area contains a pointer to the
+  target of the last branch instruction that the processor executed prior to
+  the last exception that was generated or the last interrupt that was
+  handled. See Section 17.15, "Last Branch, Interrupt, and Exception Recording
+  (Pentium M Processors)" and Section 17.16.2, "Last Branch and Last Exception
+  MSRs.".
+
+  @param  ECX  MSR_PENTIUM_M_LER_TO_LIP (0x000001DD)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_TO_LIP);
+  @endcode
+  @note MSR_PENTIUM_M_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
+**/
+#define MSR_PENTIUM_M_LER_TO_LIP                 0x000001DD
+
+
+/**
+  Last Exception Record From Linear IP (R)  Contains a pointer to the last
+  branch instruction that the processor executed prior to the last exception
+  that was generated or the last interrupt that was handled. See Section
+  17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M
+  Processors)" and Section 17.16.2, "Last Branch and Last Exception MSRs.".
+
+  @param  ECX  MSR_PENTIUM_M_LER_FROM_LIP (0x000001DE)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_FROM_LIP);
+  @endcode
+  @note MSR_PENTIUM_M_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
+**/
+#define MSR_PENTIUM_M_LER_FROM_LIP               0x000001DE
+
+
+/**
+  See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
+
+  @param  ECX  MSR_PENTIUM_M_MC4_CTL (0x0000040C)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_CTL);
+  AsmWriteMsr64 (MSR_PENTIUM_M_MC4_CTL, Msr);
+  @endcode
+  @note MSR_PENTIUM_M_MC4_CTL is defined as MSR_MC4_CTL in SDM.
+**/
+#define MSR_PENTIUM_M_MC4_CTL                    0x0000040C
+
+
+/**
+  See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
+
+  @param  ECX  MSR_PENTIUM_M_MC4_STATUS (0x0000040D)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_STATUS);
+  AsmWriteMsr64 (MSR_PENTIUM_M_MC4_STATUS, Msr);
+  @endcode
+  @note MSR_PENTIUM_M_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.
+**/
+#define MSR_PENTIUM_M_MC4_STATUS                 0x0000040D
+
+
+/**
+  See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR register is
+  either not implemented or contains no address if the ADDRV flag in the
+  MSR_MC4_STATUS register is clear. When not implemented in the processor, all
+  reads and writes to this MSR will cause a general-protection exception.
+
+  @param  ECX  MSR_PENTIUM_M_MC4_ADDR (0x0000040E)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_ADDR);
+  AsmWriteMsr64 (MSR_PENTIUM_M_MC4_ADDR, Msr);
+  @endcode
+  @note MSR_PENTIUM_M_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.
+**/
+#define MSR_PENTIUM_M_MC4_ADDR                   0x0000040E
+
+
+/**
+  See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
+
+  @param  ECX  MSR_PENTIUM_M_MC3_CTL (0x00000410)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_CTL);
+  AsmWriteMsr64 (MSR_PENTIUM_M_MC3_CTL, Msr);
+  @endcode
+  @note MSR_PENTIUM_M_MC3_CTL is defined as MSR_MC3_CTL in SDM.
+**/
+#define MSR_PENTIUM_M_MC3_CTL                    0x00000410
+
+
+/**
+  See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".
+
+  @param  ECX  MSR_PENTIUM_M_MC3_STATUS (0x00000411)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_STATUS);
+  AsmWriteMsr64 (MSR_PENTIUM_M_MC3_STATUS, Msr);
+  @endcode
+  @note MSR_PENTIUM_M_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.
+**/
+#define MSR_PENTIUM_M_MC3_STATUS                 0x00000411
+
+
+/**
+  See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR register is
+  either not implemented or contains no address if the ADDRV flag in the
+  MSR_MC3_STATUS register is clear. When not implemented in the processor, all
+  reads and writes to this MSR will cause a general-protection exception.
+
+  @param  ECX  MSR_PENTIUM_M_MC3_ADDR (0x00000412)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_ADDR);
+  AsmWriteMsr64 (MSR_PENTIUM_M_MC3_ADDR, Msr);
+  @endcode
+  @note MSR_PENTIUM_M_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.
+**/
+#define MSR_PENTIUM_M_MC3_ADDR                   0x00000412
+
+#endif
diff --git a/MdePkg/Include/Register/Intel/Msr/PentiumMsr.h b/MdePkg/Include/Register/Intel/Msr/PentiumMsr.h
new file mode 100644
index 000000000000..2e4bf6a25909
--- /dev/null
+++ b/MdePkg/Include/Register/Intel/Msr/PentiumMsr.h
@@ -0,0 +1,139 @@
+/** @file
+  MSR Definitions for Pentium Processors.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+  May 2018, Volume 4: Model-Specific-Registers (MSR)
+
+**/
+
+#ifndef __PENTIUM_MSR_H__
+#define __PENTIUM_MSR_H__
+
+#include <Register/Intel/ArchitecturalMsr.h>
+
+/**
+  Is Pentium Processors?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_PENTIUM_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x05 && \
+   (                        \
+    DisplayModel == 0x01 || \
+    DisplayModel == 0x02 || \
+    DisplayModel == 0x04    \
+    )                       \
+   )
+
+/**
+  See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.".
+
+  @param  ECX  MSR_PENTIUM_P5_MC_ADDR (0x00000000)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_ADDR);
+  AsmWriteMsr64 (MSR_PENTIUM_P5_MC_ADDR, Msr);
+  @endcode
+  @note MSR_PENTIUM_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.
+**/
+#define MSR_PENTIUM_P5_MC_ADDR                   0x00000000
+
+
+/**
+  See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.".
+
+  @param  ECX  MSR_PENTIUM_P5_MC_TYPE (0x00000001)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_TYPE);
+  AsmWriteMsr64 (MSR_PENTIUM_P5_MC_TYPE, Msr);
+  @endcode
+  @note MSR_PENTIUM_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.
+**/
+#define MSR_PENTIUM_P5_MC_TYPE                   0x00000001
+
+
+/**
+  See Section 17.17, "Time-Stamp Counter.".
+
+  @param  ECX  MSR_PENTIUM_TSC (0x00000010)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_TSC);
+  AsmWriteMsr64 (MSR_PENTIUM_TSC, Msr);
+  @endcode
+  @note MSR_PENTIUM_TSC is defined as TSC in SDM.
+**/
+#define MSR_PENTIUM_TSC                          0x00000010
+
+
+/**
+  See Section 18.6.9.1, "Control and Event Select Register (CESR).".
+
+  @param  ECX  MSR_PENTIUM_CESR (0x00000011)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_CESR);
+  AsmWriteMsr64 (MSR_PENTIUM_CESR, Msr);
+  @endcode
+  @note MSR_PENTIUM_CESR is defined as CESR in SDM.
+**/
+#define MSR_PENTIUM_CESR                         0x00000011
+
+
+/**
+  Section 18.6.9.3, "Events Counted.".
+
+  @param  ECX  MSR_PENTIUM_CTRn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_PENTIUM_CTR0);
+  AsmWriteMsr64 (MSR_PENTIUM_CTR0, Msr);
+  @endcode
+  @note MSR_PENTIUM_CTR0 is defined as CTR0 in SDM.
+        MSR_PENTIUM_CTR1 is defined as CTR1 in SDM.
+  @{
+**/
+#define MSR_PENTIUM_CTR0                         0x00000012
+#define MSR_PENTIUM_CTR1                         0x00000013
+/// @}
+
+#endif
diff --git a/MdePkg/Include/Register/Intel/Msr/SandyBridgeMsr.h b/MdePkg/Include/Register/Intel/Msr/SandyBridgeMsr.h
new file mode 100644
index 000000000000..981e5ef2e52d
--- /dev/null
+++ b/MdePkg/Include/Register/Intel/Msr/SandyBridgeMsr.h
@@ -0,0 +1,4791 @@
+/** @file
+  MSR Definitions for Intel processors based on the Sandy Bridge microarchitecture.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+  May 2018, Volume 4: Model-Specific-Registers (MSR)
+
+**/
+
+#ifndef __SANDY_BRIDGE_MSR_H__
+#define __SANDY_BRIDGE_MSR_H__
+
+#include <Register/Intel/ArchitecturalMsr.h>
+
+/**
+  Is Intel processors based on the Sandy Bridge microarchitecture?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_SANDY_BRIDGE_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (                        \
+    DisplayModel == 0x2A || \
+    DisplayModel == 0x2D    \
+    )                       \
+   )
+
+/**
+  Thread. SMI Counter (R/O).
+
+  @param  ECX  MSR_SANDY_BRIDGE_SMI_COUNT (0x00000034)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_SMI_COUNT);
+  @endcode
+  @note MSR_SANDY_BRIDGE_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.
+**/
+#define MSR_SANDY_BRIDGE_SMI_COUNT               0x00000034
+
+/**
+  MSR information returned for MSR index #MSR_SANDY_BRIDGE_SMI_COUNT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 31:0] SMI Count (R/O) Count SMIs.
+    ///
+    UINT32  SMICount:32;
+    UINT32  Reserved:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER;
+
+
+/**
+  Package. Platform Information Contains power management and other model
+  specific features enumeration. See http://biosbits.org.
+
+  @param  ECX  MSR_SANDY_BRIDGE_PLATFORM_INFO (0x000000CE)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PLATFORM_INFO);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_PLATFORM_INFO, Msr.Uint64);
+  @endcode
+  @note MSR_SANDY_BRIDGE_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
+**/
+#define MSR_SANDY_BRIDGE_PLATFORM_INFO           0x000000CE
+
+/**
+  MSR information returned for MSR index #MSR_SANDY_BRIDGE_PLATFORM_INFO
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:8;
+    ///
+    /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O)  The is the ratio
+    /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
+    /// MHz.
+    ///
+    UINT32  MaximumNonTurboRatio:8;
+    UINT32  Reserved2:12;
+    ///
+    /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O)  When
+    /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
+    /// enabled, and when set to 0, indicates Programmable Ratio Limits for
+    /// Turbo mode is disabled.
+    ///
+    UINT32  RatioLimit:1;
+    ///
+    /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O)  When
+    /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
+    /// and when set to 0, indicates TDP Limit for Turbo mode is not
+    /// programmable.
+    ///
+    UINT32  TDPLimit:1;
+    UINT32  Reserved3:2;
+    UINT32  Reserved4:8;
+    ///
+    /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O)  The is the
+    /// minimum ratio (maximum efficiency) that the processor can operates, in
+    /// units of 100MHz.
+    ///
+    UINT32  MaximumEfficiencyRatio:8;
+    UINT32  Reserved5:16;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER;
+
+
+/**
+  Core. C-State Configuration Control (R/W)  Note: C-state values are
+  processor specific C-state code names, unrelated to MWAIT extension C-state
+  parameters or ACPI CStates. See http://biosbits.org.
+
+  @param  ECX  MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL (0x000000E2)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
+  @endcode
+  @note MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
+**/
+#define MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL  0x000000E2
+
+/**
+  MSR information returned for MSR index
+  #MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 2:0] Package C-State Limit (R/W)  Specifies the lowest
+    /// processor-specific C-state code name (consuming the least power). for
+    /// the package. The default is set as factory-configured package C-state
+    /// limit. The following C-state code name encodings are supported: 000b:
+    /// C0/C1 (no package C-sate support) 001b: C2 010b: C6 no retention 011b:
+    /// C6 retention 100b: C7 101b: C7s 111: No package C-state limit. Note:
+    /// This field cannot be used to limit package C-state to C3.
+    ///
+    UINT32  Limit:3;
+    UINT32  Reserved1:7;
+    ///
+    /// [Bit 10] I/O MWAIT Redirection Enable (R/W)  When set, will map
+    /// IO_read instructions sent to IO register specified by
+    /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
+    ///
+    UINT32  IO_MWAIT:1;
+    UINT32  Reserved2:4;
+    ///
+    /// [Bit 15] CFG Lock (R/WO)  When set, lock bits 15:0 of this register
+    /// until next reset.
+    ///
+    UINT32  CFGLock:1;
+    UINT32  Reserved3:9;
+    ///
+    /// [Bit 25] C3 state auto demotion enable (R/W)  When set, the processor
+    /// will conditionally demote C6/C7 requests to C3 based on uncore
+    /// auto-demote information.
+    ///
+    UINT32  C3AutoDemotion:1;
+    ///
+    /// [Bit 26] C1 state auto demotion enable (R/W)  When set, the processor
+    /// will conditionally demote C3/C6/C7 requests to C1 based on uncore
+    /// auto-demote information.
+    ///
+    UINT32  C1AutoDemotion:1;
+    ///
+    /// [Bit 27] Enable C3 undemotion (R/W)  When set, enables undemotion from
+    /// demoted C3.
+    ///
+    UINT32  C3Undemotion:1;
+    ///
+    /// [Bit 28] Enable C1 undemotion (R/W)  When set, enables undemotion from
+    /// demoted C1.
+    ///
+    UINT32  C1Undemotion:1;
+    UINT32  Reserved4:3;
+    UINT32  Reserved5:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER;
+
+
+/**
+  Core. Power Management IO Redirection in C-state (R/W) See
+  http://biosbits.org.
+
+  @param  ECX  MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE (0x000000E4)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE, Msr.Uint64);
+  @endcode
+  @note MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.
+**/
+#define MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE     0x000000E4
+
+/**
+  MSR information returned for MSR index #MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 15:0] LVL_2 Base Address (R/W)  Specifies the base address
+    /// visible to software for IO redirection. If IO MWAIT Redirection is
+    /// enabled, reads to this address will be consumed by the power
+    /// management logic and decoded to MWAIT instructions. When IO port
+    /// address redirection is enabled, this is the IO port address reported
+    /// to the OS/software.
+    ///
+    UINT32  Lvl2Base:16;
+    ///
+    /// [Bits 18:16] C-state Range (R/W)  Specifies the encoding value of the
+    /// maximum C-State code name to be included when IO read to MWAIT
+    /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 000b - C3
+    /// is the max C-State to include 001b - C6 is the max C-State to include
+    /// 010b - C7 is the max C-State to include.
+    ///
+    UINT32  CStateRange:3;
+    UINT32  Reserved1:13;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER;
+
+
+/**
+  Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
+  handler to handle unsuccessful read of this MSR.
+
+  @param  ECX  MSR_SANDY_BRIDGE_FEATURE_CONFIG (0x0000013C)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG, Msr.Uint64);
+  @endcode
+  @note MSR_SANDY_BRIDGE_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
+**/
+#define MSR_SANDY_BRIDGE_FEATURE_CONFIG          0x0000013C
+
+/**
+  MSR information returned for MSR index #MSR_SANDY_BRIDGE_FEATURE_CONFIG
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 1:0] AES Configuration (RW-L)  Upon a successful read of this
+    /// MSR, the configuration of AES instruction set availability is as
+    /// follows: 11b: AES instructions are not available until next RESET.
+    /// otherwise, AES instructions are available. Note, AES instruction set
+    /// is not available if read is unsuccessful. If the configuration is not
+    /// 01b, AES instruction can be mis-configured if a privileged agent
+    /// unintentionally writes 11b.
+    ///
+    UINT32  AESConfiguration:2;
+    UINT32  Reserved1:30;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER;
+
+
+/**
+  Core. See Table 2-2. If CPUID.0AH:EAX[15:8] = 8.
+
+  @param  ECX  MSR_SANDY_BRIDGE_IA32_PERFEVTSELn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4 is defined as IA32_PERFEVTSEL4 in SDM.
+        MSR_SANDY_BRIDGE_IA32_PERFEVTSEL5 is defined as IA32_PERFEVTSEL5 in SDM.
+        MSR_SANDY_BRIDGE_IA32_PERFEVTSEL6 is defined as IA32_PERFEVTSEL6 in SDM.
+        MSR_SANDY_BRIDGE_IA32_PERFEVTSEL7 is defined as IA32_PERFEVTSEL7 in SDM.
+  @{
+**/
+#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4        0x0000018A
+#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL5        0x0000018B
+#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL6        0x0000018C
+#define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL7        0x0000018D
+/// @}
+
+
+/**
+  Package.
+
+  @param  ECX  MSR_SANDY_BRIDGE_PERF_STATUS (0x00000198)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PERF_STATUS);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_PERF_STATUS, Msr.Uint64);
+  @endcode
+  @note MSR_SANDY_BRIDGE_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.
+**/
+#define MSR_SANDY_BRIDGE_PERF_STATUS             0x00000198
+
+/**
+  MSR information returned for MSR index #MSR_SANDY_BRIDGE_PERF_STATUS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:32;
+    ///
+    /// [Bits 47:32] Core Voltage (R/O) P-state core voltage can be computed
+    /// by MSR_PERF_STATUS[37:32] * (float) 1/(2^13).
+    ///
+    UINT32  CoreVoltage:16;
+    UINT32  Reserved2:16;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER;
+
+
+/**
+  Thread. Clock Modulation (R/W) See Table 2-2. IA32_CLOCK_MODULATION MSR was
+  originally named IA32_THERM_CONTROL MSR.
+
+  @param  ECX  MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION (0x0000019A)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION, Msr.Uint64);
+  @endcode
+  @note MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM.
+**/
+#define MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION   0x0000019A
+
+/**
+  MSR information returned for MSR index
+  #MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 3:0] On demand Clock Modulation Duty Cycle (R/W) In 6.25%
+    /// increment.
+    ///
+    UINT32  OnDemandClockModulationDutyCycle:4;
+    ///
+    /// [Bit 4] On demand Clock Modulation Enable (R/W).
+    ///
+    UINT32  OnDemandClockModulationEnable:1;
+    UINT32  Reserved1:27;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER;
+
+
+/**
+  Enable Misc. Processor Features (R/W)  Allows a variety of processor
+  functions to be enabled and disabled.
+
+  @param  ECX  MSR_SANDY_BRIDGE_IA32_MISC_ENABLE (0x000001A0)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MISC_ENABLE);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MISC_ENABLE, Msr.Uint64);
+  @endcode
+  @note MSR_SANDY_BRIDGE_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
+**/
+#define MSR_SANDY_BRIDGE_IA32_MISC_ENABLE        0x000001A0
+
+/**
+  MSR information returned for MSR index #MSR_SANDY_BRIDGE_IA32_MISC_ENABLE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Thread. Fast-Strings Enable See Table 2-2.
+    ///
+    UINT32  FastStrings:1;
+    UINT32  Reserved1:6;
+    ///
+    /// [Bit 7] Thread. Performance Monitoring Available (R) See Table 2-2.
+    ///
+    UINT32  PerformanceMonitoring:1;
+    UINT32  Reserved2:3;
+    ///
+    /// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 2-2.
+    ///
+    UINT32  BTS:1;
+    ///
+    /// [Bit 12] Thread. Processor Event Based Sampling Unavailable (RO) See
+    /// Table 2-2.
+    ///
+    UINT32  PEBS:1;
+    UINT32  Reserved3:3;
+    ///
+    /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See
+    /// Table 2-2.
+    ///
+    UINT32  EIST:1;
+    UINT32  Reserved4:1;
+    ///
+    /// [Bit 18] Thread. ENABLE MONITOR FSM (R/W) See Table 2-2.
+    ///
+    UINT32  MONITOR:1;
+    UINT32  Reserved5:3;
+    ///
+    /// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 2-2.
+    ///
+    UINT32  LimitCpuidMaxval:1;
+    ///
+    /// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 2-2.
+    ///
+    UINT32  xTPR_Message_Disable:1;
+    UINT32  Reserved6:8;
+    UINT32  Reserved7:2;
+    ///
+    /// [Bit 34] Thread. XD Bit Disable (R/W) See Table 2-2.
+    ///
+    UINT32  XD:1;
+    UINT32  Reserved8:3;
+    ///
+    /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors
+    /// that support Intel Turbo Boost Technology, the turbo mode feature is
+    /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:
+    /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:
+    /// EAX[1] reports the processor's support of turbo mode is enabled. Note:
+    /// the power-on default value is used by BIOS to detect hardware support
+    /// of turbo mode. If power-on default value is 1, turbo mode is available
+    /// in the processor. If power-on default value is 0, turbo mode is not
+    /// available.
+    ///
+    UINT32  TurboModeDisable:1;
+    UINT32  Reserved9:25;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER;
+
+
+/**
+  Unique.
+
+  @param  ECX  MSR_SANDY_BRIDGE_TEMPERATURE_TARGET (0x000001A2)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_TEMPERATURE_TARGET);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_TEMPERATURE_TARGET, Msr.Uint64);
+  @endcode
+  @note MSR_SANDY_BRIDGE_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
+**/
+#define MSR_SANDY_BRIDGE_TEMPERATURE_TARGET      0x000001A2
+
+/**
+  MSR information returned for MSR index #MSR_SANDY_BRIDGE_TEMPERATURE_TARGET
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:16;
+    ///
+    /// [Bits 23:16] Temperature Target (R)  The minimum temperature at which
+    /// PROCHOT# will be asserted. The value is degree C.
+    ///
+    UINT32  TemperatureTarget:8;
+    UINT32  Reserved2:8;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER;
+
+
+/**
+  Miscellaneous Feature Control (R/W).
+
+  @param  ECX  MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL (0x000001A4)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL, Msr.Uint64);
+  @endcode
+  @note MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.
+**/
+#define MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL    0x000001A4
+
+/**
+  MSR information returned for MSR index #MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W)  If 1, disables the
+    /// L2 hardware prefetcher, which fetches additional lines of code or data
+    /// into the L2 cache.
+    ///
+    UINT32  L2HardwarePrefetcherDisable:1;
+    ///
+    /// [Bit 1] Core. L2 Adjacent Cache Line Prefetcher Disable (R/W)  If 1,
+    /// disables the adjacent cache line prefetcher, which fetches the cache
+    /// line that comprises a cache line pair (128 bytes).
+    ///
+    UINT32  L2AdjacentCacheLinePrefetcherDisable:1;
+    ///
+    /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W)  If 1, disables
+    /// the L1 data cache prefetcher, which fetches the next cache line into
+    /// L1 data cache.
+    ///
+    UINT32  DCUHardwarePrefetcherDisable:1;
+    ///
+    /// [Bit 3] Core. DCU IP Prefetcher Disable (R/W)  If 1, disables the L1
+    /// data cache IP prefetcher, which uses sequential load history (based on
+    /// instruction Pointer of previous loads) to determine whether to
+    /// prefetch additional lines.
+    ///
+    UINT32  DCUIPPrefetcherDisable:1;
+    UINT32  Reserved1:28;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER;
+
+
+/**
+  Thread. Offcore Response Event Select Register (R/W).
+
+  @param  ECX  MSR_SANDY_BRIDGE_OFFCORE_RSP_0 (0x000001A6)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_0);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_0, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_OFFCORE_RSP_0           0x000001A6
+
+
+/**
+  Thread. Offcore Response Event Select Register (R/W).
+
+  @param  ECX  MSR_SANDY_BRIDGE_OFFCORE_RSP_1 (0x000001A7)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_1);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_1, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_OFFCORE_RSP_1           0x000001A7
+
+
+/**
+  See http://biosbits.org.
+
+  @param  ECX  MSR_SANDY_BRIDGE_MISC_PWR_MGMT (0x000001AA)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MISC_PWR_MGMT);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_MISC_PWR_MGMT, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM.
+**/
+#define MSR_SANDY_BRIDGE_MISC_PWR_MGMT           0x000001AA
+
+
+/**
+  Thread. Last Branch Record Filtering Select Register (R/W) See Section
+  17.9.2, "Filtering of Last Branch Records.".
+
+  @param  ECX  MSR_SANDY_BRIDGE_LBR_SELECT (0x000001C8)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_LBR_SELECT);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_LBR_SELECT, Msr.Uint64);
+  @endcode
+  @note MSR_SANDY_BRIDGE_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
+**/
+#define MSR_SANDY_BRIDGE_LBR_SELECT              0x000001C8
+
+/**
+  MSR information returned for MSR index #MSR_SANDY_BRIDGE_LBR_SELECT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] CPL_EQ_0.
+    ///
+    UINT32  CPL_EQ_0:1;
+    ///
+    /// [Bit 1] CPL_NEQ_0.
+    ///
+    UINT32  CPL_NEQ_0:1;
+    ///
+    /// [Bit 2] JCC.
+    ///
+    UINT32  JCC:1;
+    ///
+    /// [Bit 3] NEAR_REL_CALL.
+    ///
+    UINT32  NEAR_REL_CALL:1;
+    ///
+    /// [Bit 4] NEAR_IND_CALL.
+    ///
+    UINT32  NEAR_IND_CALL:1;
+    ///
+    /// [Bit 5] NEAR_RET.
+    ///
+    UINT32  NEAR_RET:1;
+    ///
+    /// [Bit 6] NEAR_IND_JMP.
+    ///
+    UINT32  NEAR_IND_JMP:1;
+    ///
+    /// [Bit 7] NEAR_REL_JMP.
+    ///
+    UINT32  NEAR_REL_JMP:1;
+    ///
+    /// [Bit 8] FAR_BRANCH.
+    ///
+    UINT32  FAR_BRANCH:1;
+    UINT32  Reserved1:23;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER;
+
+
+/**
+  Thread. Last Branch Record Stack TOS (R/W)  Contains an index (bits 0-3)
+  that points to the MSR containing the most recent branch record. See
+  MSR_LASTBRANCH_0_FROM_IP (at 680H).
+
+  @param  ECX  MSR_SANDY_BRIDGE_LASTBRANCH_TOS (0x000001C9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_TOS);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_TOS, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
+**/
+#define MSR_SANDY_BRIDGE_LASTBRANCH_TOS          0x000001C9
+
+
+/**
+  Thread. Last Exception Record From Linear IP (R)  Contains a pointer to the
+  last branch instruction that the processor executed prior to the last
+  exception that was generated or the last interrupt that was handled.
+
+  @param  ECX  MSR_SANDY_BRIDGE_LER_FROM_LIP (0x000001DD)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LER_FROM_LIP);
+  @endcode
+  @note MSR_SANDY_BRIDGE_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
+**/
+#define MSR_SANDY_BRIDGE_LER_FROM_LIP            0x000001DD
+
+
+/**
+  Thread. Last Exception Record To Linear IP (R)  This area contains a pointer
+  to the target of the last branch instruction that the processor executed
+  prior to the last exception that was generated or the last interrupt that
+  was handled.
+
+  @param  ECX  MSR_SANDY_BRIDGE_LER_TO_LIP (0x000001DE)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LER_TO_LIP);
+  @endcode
+  @note MSR_SANDY_BRIDGE_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
+**/
+#define MSR_SANDY_BRIDGE_LER_TO_LIP              0x000001DE
+
+
+/**
+  Core. See http://biosbits.org.
+
+  @param  ECX  MSR_SANDY_BRIDGE_POWER_CTL (0x000001FC)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_POWER_CTL);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_POWER_CTL, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_POWER_CTL is defined as MSR_POWER_CTL in SDM.
+**/
+#define MSR_SANDY_BRIDGE_POWER_CTL               0x000001FC
+
+
+/**
+  Package. Always 0 (CMCI not supported).
+
+  @param  ECX  MSR_SANDY_BRIDGE_IA32_MC4_CTL2 (0x00000284)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL2);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL2, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_IA32_MC4_CTL2           0x00000284
+
+
+/**
+  See Table 2-2. See Section 18.6.2.2, "Global Counter Control Facilities.".
+
+  @param  ECX  MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS (0x0000038E)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);
+  @endcode
+  @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.
+**/
+#define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS 0x0000038E
+
+/**
+  MSR information returned for MSR index
+  #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Thread. Ovf_PMC0.
+    ///
+    UINT32  Ovf_PMC0:1;
+    ///
+    /// [Bit 1] Thread. Ovf_PMC1.
+    ///
+    UINT32  Ovf_PMC1:1;
+    ///
+    /// [Bit 2] Thread. Ovf_PMC2.
+    ///
+    UINT32  Ovf_PMC2:1;
+    ///
+    /// [Bit 3] Thread. Ovf_PMC3.
+    ///
+    UINT32  Ovf_PMC3:1;
+    ///
+    /// [Bit 4] Core. Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).
+    ///
+    UINT32  Ovf_PMC4:1;
+    ///
+    /// [Bit 5] Core. Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).
+    ///
+    UINT32  Ovf_PMC5:1;
+    ///
+    /// [Bit 6] Core. Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).
+    ///
+    UINT32  Ovf_PMC6:1;
+    ///
+    /// [Bit 7] Core. Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).
+    ///
+    UINT32  Ovf_PMC7:1;
+    UINT32  Reserved1:24;
+    ///
+    /// [Bit 32] Thread. Ovf_FixedCtr0.
+    ///
+    UINT32  Ovf_FixedCtr0:1;
+    ///
+    /// [Bit 33] Thread. Ovf_FixedCtr1.
+    ///
+    UINT32  Ovf_FixedCtr1:1;
+    ///
+    /// [Bit 34] Thread. Ovf_FixedCtr2.
+    ///
+    UINT32  Ovf_FixedCtr2:1;
+    UINT32  Reserved2:26;
+    ///
+    /// [Bit 61] Thread. Ovf_Uncore.
+    ///
+    UINT32  Ovf_Uncore:1;
+    ///
+    /// [Bit 62] Thread. Ovf_BufDSSAVE.
+    ///
+    UINT32  Ovf_BufDSSAVE:1;
+    ///
+    /// [Bit 63] Thread. CondChgd.
+    ///
+    UINT32  CondChgd:1;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER;
+
+
+/**
+  Thread. See Table 2-2. See Section 18.6.2.2, "Global Counter Control
+  Facilities.".
+
+  @param  ECX  MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL (0x0000038F)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL, Msr.Uint64);
+  @endcode
+  @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM.
+**/
+#define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL   0x0000038F
+
+/**
+  MSR information returned for MSR index
+  #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Thread. Set 1 to enable PMC0 to count.
+    ///
+    UINT32  PCM0_EN:1;
+    ///
+    /// [Bit 1] Thread. Set 1 to enable PMC1 to count.
+    ///
+    UINT32  PCM1_EN:1;
+    ///
+    /// [Bit 2] Thread. Set 1 to enable PMC2 to count.
+    ///
+    UINT32  PCM2_EN:1;
+    ///
+    /// [Bit 3] Thread. Set 1 to enable PMC3 to count.
+    ///
+    UINT32  PCM3_EN:1;
+    ///
+    /// [Bit 4] Core. Set 1 to enable PMC4 to count (if CPUID.0AH:EAX[15:8] >
+    /// 4).
+    ///
+    UINT32  PCM4_EN:1;
+    ///
+    /// [Bit 5] Core. Set 1 to enable PMC5 to count (if CPUID.0AH:EAX[15:8] >
+    /// 5).
+    ///
+    UINT32  PCM5_EN:1;
+    ///
+    /// [Bit 6] Core. Set 1 to enable PMC6 to count (if CPUID.0AH:EAX[15:8] >
+    /// 6).
+    ///
+    UINT32  PCM6_EN:1;
+    ///
+    /// [Bit 7] Core. Set 1 to enable PMC7 to count (if CPUID.0AH:EAX[15:8] >
+    /// 7).
+    ///
+    UINT32  PCM7_EN:1;
+    UINT32  Reserved1:24;
+    ///
+    /// [Bit 32] Thread. Set 1 to enable FixedCtr0 to count.
+    ///
+    UINT32  FIXED_CTR0:1;
+    ///
+    /// [Bit 33] Thread. Set 1 to enable FixedCtr1 to count.
+    ///
+    UINT32  FIXED_CTR1:1;
+    ///
+    /// [Bit 34] Thread. Set 1 to enable FixedCtr2 to count.
+    ///
+    UINT32  FIXED_CTR2:1;
+    UINT32  Reserved2:29;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER;
+
+
+/**
+  See Table 2-2. See Section 18.6.2.2, "Global Counter Control Facilities.".
+
+  @param  ECX  MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);
+  @endcode
+  @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM.
+**/
+#define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390
+
+/**
+  MSR information returned for MSR index
+  #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Thread. Set 1 to clear Ovf_PMC0.
+    ///
+    UINT32  Ovf_PMC0:1;
+    ///
+    /// [Bit 1] Thread. Set 1 to clear Ovf_PMC1.
+    ///
+    UINT32  Ovf_PMC1:1;
+    ///
+    /// [Bit 2] Thread. Set 1 to clear Ovf_PMC2.
+    ///
+    UINT32  Ovf_PMC2:1;
+    ///
+    /// [Bit 3] Thread. Set 1 to clear Ovf_PMC3.
+    ///
+    UINT32  Ovf_PMC3:1;
+    ///
+    /// [Bit 4] Core. Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).
+    ///
+    UINT32  Ovf_PMC4:1;
+    ///
+    /// [Bit 5] Core. Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).
+    ///
+    UINT32  Ovf_PMC5:1;
+    ///
+    /// [Bit 6] Core. Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).
+    ///
+    UINT32  Ovf_PMC6:1;
+    ///
+    /// [Bit 7] Core. Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).
+    ///
+    UINT32  Ovf_PMC7:1;
+    UINT32  Reserved1:24;
+    ///
+    /// [Bit 32] Thread. Set 1 to clear Ovf_FixedCtr0.
+    ///
+    UINT32  Ovf_FixedCtr0:1;
+    ///
+    /// [Bit 33] Thread. Set 1 to clear Ovf_FixedCtr1.
+    ///
+    UINT32  Ovf_FixedCtr1:1;
+    ///
+    /// [Bit 34] Thread. Set 1 to clear Ovf_FixedCtr2.
+    ///
+    UINT32  Ovf_FixedCtr2:1;
+    UINT32  Reserved2:26;
+    ///
+    /// [Bit 61] Thread. Set 1 to clear Ovf_Uncore.
+    ///
+    UINT32  Ovf_Uncore:1;
+    ///
+    /// [Bit 62] Thread. Set 1 to clear Ovf_BufDSSAVE.
+    ///
+    UINT32  Ovf_BufDSSAVE:1;
+    ///
+    /// [Bit 63] Thread. Set 1 to clear CondChgd.
+    ///
+    UINT32  CondChgd:1;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER;
+
+
+/**
+  Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).".
+
+  @param  ECX  MSR_SANDY_BRIDGE_PEBS_ENABLE (0x000003F1)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_ENABLE);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_ENABLE, Msr.Uint64);
+  @endcode
+  @note MSR_SANDY_BRIDGE_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
+**/
+#define MSR_SANDY_BRIDGE_PEBS_ENABLE             0x000003F1
+
+/**
+  MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_ENABLE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
+    ///
+    UINT32  PEBS_EN_PMC0:1;
+    ///
+    /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).
+    ///
+    UINT32  PEBS_EN_PMC1:1;
+    ///
+    /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).
+    ///
+    UINT32  PEBS_EN_PMC2:1;
+    ///
+    /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).
+    ///
+    UINT32  PEBS_EN_PMC3:1;
+    UINT32  Reserved1:28;
+    ///
+    /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).
+    ///
+    UINT32  LL_EN_PMC0:1;
+    ///
+    /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).
+    ///
+    UINT32  LL_EN_PMC1:1;
+    ///
+    /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).
+    ///
+    UINT32  LL_EN_PMC2:1;
+    ///
+    /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).
+    ///
+    UINT32  LL_EN_PMC3:1;
+    UINT32  Reserved2:27;
+    ///
+    /// [Bit 63] Enable Precise Store. (R/W).
+    ///
+    UINT32  PS_EN:1;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER;
+
+
+/**
+  Thread. See Section 18.3.1.1.2, "Load Latency Performance Monitoring
+  Facility.".
+
+  @param  ECX  MSR_SANDY_BRIDGE_PEBS_LD_LAT (0x000003F6)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_LD_LAT);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_LD_LAT, Msr.Uint64);
+  @endcode
+  @note MSR_SANDY_BRIDGE_PEBS_LD_LAT is defined as MSR_PEBS_LD_LAT in SDM.
+**/
+#define MSR_SANDY_BRIDGE_PEBS_LD_LAT             0x000003F6
+
+/**
+  MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_LD_LAT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 15:0] Minimum threshold latency value of tagged load operation
+    /// that will be counted. (R/W).
+    ///
+    UINT32  MinimumThreshold:16;
+    UINT32  Reserved1:16;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER;
+
+
+/**
+  Package. Note: C-state values are processor specific C-state code names,
+  unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3
+  Residency Counter. (R/O) Value since last reset that this package is in
+  processor-specific C3 states. Count at the same frequency as the TSC.
+
+  @param  ECX  MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY (0x000003F8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.
+**/
+#define MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY        0x000003F8
+
+
+/**
+  Package. Note: C-state values are processor specific C-state code names,
+  unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6
+  Residency Counter. (R/O) Value since last reset that this package is in
+  processor-specific C6 states. Count at the same frequency as the TSC.
+
+  @param  ECX  MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY (0x000003F9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
+**/
+#define MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY        0x000003F9
+
+
+/**
+  Package. Note: C-state values are processor specific C-state code names,
+  unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C7
+  Residency Counter. (R/O) Value since last reset that this package is in
+  processor-specific C7 states. Count at the same frequency as the TSC.
+
+  @param  ECX  MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY (0x000003FA)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.
+**/
+#define MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY        0x000003FA
+
+
+/**
+  Core. Note: C-state values are processor specific C-state code names,
+  unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3
+  Residency Counter. (R/O) Value since last reset that this core is in
+  processor-specific C3 states. Count at the same frequency as the TSC.
+
+  @param  ECX  MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY (0x000003FC)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM.
+**/
+#define MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY       0x000003FC
+
+
+/**
+  Core. Note: C-state values are processor specific C-state code names,
+  unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6
+  Residency Counter. (R/O) Value since last reset that this core is in
+  processor-specific C6 states. Count at the same frequency as the TSC.
+
+  @param  ECX  MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY (0x000003FD)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.
+**/
+#define MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY       0x000003FD
+
+
+/**
+  Core. Note: C-state values are processor specific C-state code names,
+  unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C7
+  Residency Counter. (R/O) Value since last reset that this core is in
+  processor-specific C7 states. Count at the same frequency as the TSC.
+
+  @param  ECX  MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY (0x000003FE)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY is defined as MSR_CORE_C7_RESIDENCY in SDM.
+**/
+#define MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY       0x000003FE
+
+
+/**
+  Core. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".
+
+  @param  ECX  MSR_SANDY_BRIDGE_IA32_MC4_CTL (0x00000410)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL, Msr.Uint64);
+  @endcode
+  @note MSR_SANDY_BRIDGE_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM.
+**/
+#define MSR_SANDY_BRIDGE_IA32_MC4_CTL            0x00000410
+
+/**
+  MSR information returned for MSR index #MSR_SANDY_BRIDGE_IA32_MC4_CTL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] PCU Hardware Error (R/W)  When set, enables signaling of PCU
+    /// hardware detected errors.
+    ///
+    UINT32  PCUHardwareError:1;
+    ///
+    /// [Bit 1] PCU Controller Error (R/W)  When set, enables signaling of PCU
+    /// controller detected errors.
+    ///
+    UINT32  PCUControllerError:1;
+    ///
+    /// [Bit 2] PCU Firmware Error (R/W)  When set, enables signaling of PCU
+    /// firmware detected errors.
+    ///
+    UINT32  PCUFirmwareError:1;
+    UINT32  Reserved1:29;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER;
+
+
+/**
+  Thread. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2.
+
+  @param  ECX  MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM (0x0000048C)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM);
+  @endcode
+  @note MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.
+**/
+#define MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM  0x0000048C
+
+
+/**
+  Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1,
+  "RAPL Interfaces.".
+
+  @param  ECX  MSR_SANDY_BRIDGE_RAPL_POWER_UNIT (0x00000606)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_RAPL_POWER_UNIT);
+  @endcode
+  @note MSR_SANDY_BRIDGE_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
+**/
+#define MSR_SANDY_BRIDGE_RAPL_POWER_UNIT         0x00000606
+
+
+/**
+  Package. Package C3 Interrupt Response Limit (R/W)  Note: C-state values are
+  processor specific C-state code names, unrelated to MWAIT extension C-state
+  parameters or ACPI CStates.
+
+  @param  ECX  MSR_SANDY_BRIDGE_PKGC3_IRTL (0x0000060A)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC3_IRTL);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC3_IRTL, Msr.Uint64);
+  @endcode
+  @note MSR_SANDY_BRIDGE_PKGC3_IRTL is defined as MSR_PKGC3_IRTL in SDM.
+**/
+#define MSR_SANDY_BRIDGE_PKGC3_IRTL              0x0000060A
+
+/**
+  MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC3_IRTL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 9:0] Interrupt response time limit (R/W)  Specifies the limit
+    /// that should be used to decide if the package should be put into a
+    /// package C3 state.
+    ///
+    UINT32  TimeLimit:10;
+    ///
+    /// [Bits 12:10] Time Unit (R/W)  Specifies the encoding value of time
+    /// unit of the interrupt response time limit. The following time unit
+    /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:
+    /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.
+    ///
+    UINT32  TimeUnit:3;
+    UINT32  Reserved1:2;
+    ///
+    /// [Bit 15] Valid (R/W)  Indicates whether the values in bits 12:0 are
+    /// valid and can be used by the processor for package C-sate management.
+    ///
+    UINT32  Valid:1;
+    UINT32  Reserved2:16;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER;
+
+
+/**
+  Package. Package C6 Interrupt Response Limit (R/W)  This MSR defines the
+  budget allocated for the package to exit from C6 to a C0 state, where
+  interrupt request can be delivered to the core and serviced. Additional
+  core-exit latency amy be applicable depending on the actual C-state the core
+  is in. Note: C-state values are processor specific C-state code names,
+  unrelated to MWAIT extension C-state parameters or ACPI CStates.
+
+  @param  ECX  MSR_SANDY_BRIDGE_PKGC6_IRTL (0x0000060B)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC6_IRTL);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC6_IRTL, Msr.Uint64);
+  @endcode
+  @note MSR_SANDY_BRIDGE_PKGC6_IRTL is defined as MSR_PKGC6_IRTL in SDM.
+**/
+#define MSR_SANDY_BRIDGE_PKGC6_IRTL              0x0000060B
+
+/**
+  MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC6_IRTL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 9:0] Interrupt response time limit (R/W)  Specifies the limit
+    /// that should be used to decide if the package should be put into a
+    /// package C6 state.
+    ///
+    UINT32  TimeLimit:10;
+    ///
+    /// [Bits 12:10] Time Unit (R/W)  Specifies the encoding value of time
+    /// unit of the interrupt response time limit. The following time unit
+    /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:
+    /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.
+    ///
+    UINT32  TimeUnit:3;
+    UINT32  Reserved1:2;
+    ///
+    /// [Bit 15] Valid (R/W)  Indicates whether the values in bits 12:0 are
+    /// valid and can be used by the processor for package C-sate management.
+    ///
+    UINT32  Valid:1;
+    UINT32  Reserved2:16;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER;
+
+
+/**
+  Package. Note: C-state values are processor specific C-state code names,
+  unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C2
+  Residency Counter. (R/O) Value since last reset that this package is in
+  processor-specific C2 states. Count at the same frequency as the TSC.
+
+  @param  ECX  MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY (0x0000060D)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.
+**/
+#define MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY        0x0000060D
+
+
+/**
+  Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package
+  RAPL Domain.".
+
+  @param  ECX  MSR_SANDY_BRIDGE_PKG_POWER_LIMIT (0x00000610)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_LIMIT);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_LIMIT, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.
+**/
+#define MSR_SANDY_BRIDGE_PKG_POWER_LIMIT         0x00000610
+
+
+/**
+  Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
+
+  @param  ECX  MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS (0x00000611)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS);
+  @endcode
+  @note MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.
+**/
+#define MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS       0x00000611
+
+
+/**
+  Package. PKG RAPL Parameters (R/W) See Section 14.9.3, "Package RAPL
+  Domain.".
+
+  @param  ECX  MSR_SANDY_BRIDGE_PKG_POWER_INFO (0x00000614)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_INFO);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_INFO, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.
+**/
+#define MSR_SANDY_BRIDGE_PKG_POWER_INFO          0x00000614
+
+
+/**
+  Package. PP0 RAPL Power Limit Control (R/W)  See Section 14.9.4, "PP0/PP1
+  RAPL Domains.".
+
+  @param  ECX  MSR_SANDY_BRIDGE_PP0_POWER_LIMIT (0x00000638)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_POWER_LIMIT);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP0_POWER_LIMIT, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.
+**/
+#define MSR_SANDY_BRIDGE_PP0_POWER_LIMIT         0x00000638
+
+
+/**
+  Package. PP0 Energy Status (R/O)  See Section 14.9.4, "PP0/PP1 RAPL
+  Domains.".
+
+  @param  ECX  MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS (0x00000639)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS);
+  @endcode
+  @note MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
+**/
+#define MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS       0x00000639
+
+
+/**
+  Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last
+  branch record registers on the last branch record stack. This part of the
+  stack contains pointers to the source instruction. See also: -  Last Branch
+  Record Stack TOS at 1C9H -  Section 17.7.1 and record format in Section
+  17.4.8.1.
+
+  @param  ECX  MSR_SANDY_BRIDGE_LASTBRANCH_n_FROM_IP
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP  is defined as MSR_LASTBRANCH_0_FROM_IP  in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_1_FROM_IP  is defined as MSR_LASTBRANCH_1_FROM_IP  in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_2_FROM_IP  is defined as MSR_LASTBRANCH_2_FROM_IP  in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_3_FROM_IP  is defined as MSR_LASTBRANCH_3_FROM_IP  in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_4_FROM_IP  is defined as MSR_LASTBRANCH_4_FROM_IP  in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_5_FROM_IP  is defined as MSR_LASTBRANCH_5_FROM_IP  in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_6_FROM_IP  is defined as MSR_LASTBRANCH_6_FROM_IP  in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_7_FROM_IP  is defined as MSR_LASTBRANCH_7_FROM_IP  in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_8_FROM_IP  is defined as MSR_LASTBRANCH_8_FROM_IP  in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_9_FROM_IP  is defined as MSR_LASTBRANCH_9_FROM_IP  in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.
+  @{
+**/
+#define MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP    0x00000680
+#define MSR_SANDY_BRIDGE_LASTBRANCH_1_FROM_IP    0x00000681
+#define MSR_SANDY_BRIDGE_LASTBRANCH_2_FROM_IP    0x00000682
+#define MSR_SANDY_BRIDGE_LASTBRANCH_3_FROM_IP    0x00000683
+#define MSR_SANDY_BRIDGE_LASTBRANCH_4_FROM_IP    0x00000684
+#define MSR_SANDY_BRIDGE_LASTBRANCH_5_FROM_IP    0x00000685
+#define MSR_SANDY_BRIDGE_LASTBRANCH_6_FROM_IP    0x00000686
+#define MSR_SANDY_BRIDGE_LASTBRANCH_7_FROM_IP    0x00000687
+#define MSR_SANDY_BRIDGE_LASTBRANCH_8_FROM_IP    0x00000688
+#define MSR_SANDY_BRIDGE_LASTBRANCH_9_FROM_IP    0x00000689
+#define MSR_SANDY_BRIDGE_LASTBRANCH_10_FROM_IP   0x0000068A
+#define MSR_SANDY_BRIDGE_LASTBRANCH_11_FROM_IP   0x0000068B
+#define MSR_SANDY_BRIDGE_LASTBRANCH_12_FROM_IP   0x0000068C
+#define MSR_SANDY_BRIDGE_LASTBRANCH_13_FROM_IP   0x0000068D
+#define MSR_SANDY_BRIDGE_LASTBRANCH_14_FROM_IP   0x0000068E
+#define MSR_SANDY_BRIDGE_LASTBRANCH_15_FROM_IP   0x0000068F
+/// @}
+
+
+/**
+  Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch
+  record registers on the last branch record stack. This part of the stack
+  contains pointers to the destination instruction.
+
+  @param  ECX  MSR_SANDY_BRIDGE_LASTBRANCH_n_TO_IP
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP  is defined as MSR_LASTBRANCH_0_TO_IP  in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_1_TO_IP  is defined as MSR_LASTBRANCH_1_TO_IP  in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_2_TO_IP  is defined as MSR_LASTBRANCH_2_TO_IP  in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_3_TO_IP  is defined as MSR_LASTBRANCH_3_TO_IP  in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_4_TO_IP  is defined as MSR_LASTBRANCH_4_TO_IP  in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_5_TO_IP  is defined as MSR_LASTBRANCH_5_TO_IP  in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_6_TO_IP  is defined as MSR_LASTBRANCH_6_TO_IP  in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_7_TO_IP  is defined as MSR_LASTBRANCH_7_TO_IP  in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_8_TO_IP  is defined as MSR_LASTBRANCH_8_TO_IP  in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_9_TO_IP  is defined as MSR_LASTBRANCH_9_TO_IP  in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM.
+        MSR_SANDY_BRIDGE_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.
+  @{
+**/
+#define MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP      0x000006C0
+#define MSR_SANDY_BRIDGE_LASTBRANCH_1_TO_IP      0x000006C1
+#define MSR_SANDY_BRIDGE_LASTBRANCH_2_TO_IP      0x000006C2
+#define MSR_SANDY_BRIDGE_LASTBRANCH_3_TO_IP      0x000006C3
+#define MSR_SANDY_BRIDGE_LASTBRANCH_4_TO_IP      0x000006C4
+#define MSR_SANDY_BRIDGE_LASTBRANCH_5_TO_IP      0x000006C5
+#define MSR_SANDY_BRIDGE_LASTBRANCH_6_TO_IP      0x000006C6
+#define MSR_SANDY_BRIDGE_LASTBRANCH_7_TO_IP      0x000006C7
+#define MSR_SANDY_BRIDGE_LASTBRANCH_8_TO_IP      0x000006C8
+#define MSR_SANDY_BRIDGE_LASTBRANCH_9_TO_IP      0x000006C9
+#define MSR_SANDY_BRIDGE_LASTBRANCH_10_TO_IP     0x000006CA
+#define MSR_SANDY_BRIDGE_LASTBRANCH_11_TO_IP     0x000006CB
+#define MSR_SANDY_BRIDGE_LASTBRANCH_12_TO_IP     0x000006CC
+#define MSR_SANDY_BRIDGE_LASTBRANCH_13_TO_IP     0x000006CD
+#define MSR_SANDY_BRIDGE_LASTBRANCH_14_TO_IP     0x000006CE
+#define MSR_SANDY_BRIDGE_LASTBRANCH_15_TO_IP     0x000006CF
+/// @}
+
+
+/**
+  Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
+  RW if MSR_PLATFORM_INFO.[28] = 1.
+
+  @param  ECX  MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT (0x000001AD)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT);
+  @endcode
+  @note MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
+**/
+#define MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT       0x000001AD
+
+/**
+  MSR information returned for MSR index #MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
+    /// limit of 1 core active.
+    ///
+    UINT32  Maximum1C:8;
+    ///
+    /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
+    /// limit of 2 core active.
+    ///
+    UINT32  Maximum2C:8;
+    ///
+    /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
+    /// limit of 3 core active.
+    ///
+    UINT32  Maximum3C:8;
+    ///
+    /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
+    /// limit of 4 core active.
+    ///
+    UINT32  Maximum4C:8;
+    ///
+    /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
+    /// limit of 5 core active.
+    ///
+    UINT32  Maximum5C:8;
+    ///
+    /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
+    /// limit of 6 core active.
+    ///
+    UINT32  Maximum6C:8;
+    ///
+    /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio
+    /// limit of 7 core active.
+    ///
+    UINT32  Maximum7C:8;
+    ///
+    /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio
+    /// limit of 8 core active.
+    ///
+    UINT32  Maximum8C:8;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER;
+
+
+/**
+  Package. Uncore PMU global control.
+
+  @param  ECX  MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL (0x00000391)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL, Msr.Uint64);
+  @endcode
+  @note MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.
+**/
+#define MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL    0x00000391
+
+/**
+  MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Slice 0 select.
+    ///
+    UINT32  PMI_Sel_Slice0:1;
+    ///
+    /// [Bit 1] Slice 1 select.
+    ///
+    UINT32  PMI_Sel_Slice1:1;
+    ///
+    /// [Bit 2] Slice 2 select.
+    ///
+    UINT32  PMI_Sel_Slice2:1;
+    ///
+    /// [Bit 3] Slice 3 select.
+    ///
+    UINT32  PMI_Sel_Slice3:1;
+    ///
+    /// [Bit 4] Slice 4 select.
+    ///
+    UINT32  PMI_Sel_Slice4:1;
+    UINT32  Reserved1:14;
+    UINT32  Reserved2:10;
+    ///
+    /// [Bit 29] Enable all uncore counters.
+    ///
+    UINT32  EN:1;
+    ///
+    /// [Bit 30] Enable wake on PMI.
+    ///
+    UINT32  WakePMI:1;
+    ///
+    /// [Bit 31] Enable Freezing counter when overflow.
+    ///
+    UINT32  FREEZE:1;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER;
+
+
+/**
+  Package. Uncore PMU main status.
+
+  @param  ECX  MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS (0x00000392)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS, Msr.Uint64);
+  @endcode
+  @note MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM.
+**/
+#define MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS  0x00000392
+
+/**
+  MSR information returned for MSR index
+  #MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Fixed counter overflowed.
+    ///
+    UINT32  Fixed:1;
+    ///
+    /// [Bit 1] An ARB counter overflowed.
+    ///
+    UINT32  ARB:1;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 3] A CBox counter overflowed (on any slice).
+    ///
+    UINT32  CBox:1;
+    UINT32  Reserved2:28;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER;
+
+
+/**
+  Package. Uncore fixed counter control (R/W).
+
+  @param  ECX  MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL (0x00000394)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL, Msr.Uint64);
+  @endcode
+  @note MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.
+**/
+#define MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL     0x00000394
+
+/**
+  MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:20;
+    ///
+    /// [Bit 20] Enable overflow propagation.
+    ///
+    UINT32  EnableOverflow:1;
+    UINT32  Reserved2:1;
+    ///
+    /// [Bit 22] Enable counting.
+    ///
+    UINT32  EnableCounting:1;
+    UINT32  Reserved3:9;
+    UINT32  Reserved4:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER;
+
+
+/**
+  Package. Uncore fixed counter.
+
+  @param  ECX  MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR (0x00000395)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR, Msr.Uint64);
+  @endcode
+  @note MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.
+**/
+#define MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR      0x00000395
+
+/**
+  MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 31:0] Current count.
+    ///
+    UINT32  CurrentCount:32;
+    ///
+    /// [Bits 47:32] Current count.
+    ///
+    UINT32  CurrentCountHi:16;
+    UINT32  Reserved:16;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER;
+
+
+/**
+  Package. Uncore C-Box configuration information (R/O).
+
+  @param  ECX  MSR_SANDY_BRIDGE_UNC_CBO_CONFIG (0x00000396)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_CONFIG);
+  @endcode
+  @note MSR_SANDY_BRIDGE_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.
+**/
+#define MSR_SANDY_BRIDGE_UNC_CBO_CONFIG          0x00000396
+
+/**
+  MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_CBO_CONFIG
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 3:0] Report the number of C-Box units with performance counters,
+    /// including processor cores and processor graphics".
+    ///
+    UINT32  CBox:4;
+    UINT32  Reserved1:28;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER;
+
+
+/**
+  Package. Uncore Arb unit, performance counter 0.
+
+  @param  ECX  MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 (0x000003B0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0        0x000003B0
+
+
+/**
+  Package. Uncore Arb unit, performance counter 1.
+
+  @param  ECX  MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 (0x000003B1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1        0x000003B1
+
+
+/**
+  Package. Uncore Arb unit, counter 0 event select MSR.
+
+  @param  ECX  MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 (0x000003B2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0     0x000003B2
+
+
+/**
+  Package. Uncore Arb unit, counter 1 event select MSR.
+
+  @param  ECX  MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 (0x000003B3)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 is defined as MSR_UNC_ARB_PERFEVTSEL1 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1     0x000003B3
+
+
+/**
+  Package. Package C7 Interrupt Response Limit (R/W)  This MSR defines the
+  budget allocated for the package to exit from C7 to a C0 state, where
+  interrupt request can be delivered to the core and serviced. Additional
+  core-exit latency amy be applicable depending on the actual C-state the core
+  is in. Note: C-state values are processor specific C-state code names,
+  unrelated to MWAIT extension C-state parameters or ACPI CStates.
+
+  @param  ECX  MSR_SANDY_BRIDGE_PKGC7_IRTL (0x0000060C)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC7_IRTL);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC7_IRTL, Msr.Uint64);
+  @endcode
+  @note MSR_SANDY_BRIDGE_PKGC7_IRTL is defined as MSR_PKGC7_IRTL in SDM.
+**/
+#define MSR_SANDY_BRIDGE_PKGC7_IRTL              0x0000060C
+
+/**
+  MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC7_IRTL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 9:0] Interrupt response time limit (R/W)  Specifies the limit
+    /// that should be used to decide if the package should be put into a
+    /// package C7 state.
+    ///
+    UINT32  TimeLimit:10;
+    ///
+    /// [Bits 12:10] Time Unit (R/W)  Specifies the encoding value of time
+    /// unit of the interrupt response time limit. The following time unit
+    /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:
+    /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.
+    ///
+    UINT32  TimeUnit:3;
+    UINT32  Reserved1:2;
+    ///
+    /// [Bit 15] Valid (R/W)  Indicates whether the values in bits 12:0 are
+    /// valid and can be used by the processor for package C-sate management.
+    ///
+    UINT32  Valid:1;
+    UINT32  Reserved2:16;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER;
+
+
+/**
+  Package. PP0 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL
+  Domains.".
+
+  @param  ECX  MSR_SANDY_BRIDGE_PP0_POLICY (0x0000063A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_POLICY);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP0_POLICY, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_PP0_POLICY is defined as MSR_PP0_POLICY in SDM.
+**/
+#define MSR_SANDY_BRIDGE_PP0_POLICY              0x0000063A
+
+
+/**
+  Package. PP1 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1
+  RAPL Domains.".
+
+  @param  ECX  MSR_SANDY_BRIDGE_PP1_POWER_LIMIT (0x00000640)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_POWER_LIMIT);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP1_POWER_LIMIT, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_PP1_POWER_LIMIT is defined as MSR_PP1_POWER_LIMIT in SDM.
+**/
+#define MSR_SANDY_BRIDGE_PP1_POWER_LIMIT         0x00000640
+
+
+/**
+  Package. PP1 Energy Status (R/O)  See Section 14.9.4, "PP0/PP1 RAPL
+  Domains.".
+
+  @param  ECX  MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS (0x00000641)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS);
+  @endcode
+  @note MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM.
+**/
+#define MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS       0x00000641
+
+
+/**
+  Package. PP1 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL
+  Domains.".
+
+  @param  ECX  MSR_SANDY_BRIDGE_PP1_POLICY (0x00000642)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_POLICY);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP1_POLICY, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_PP1_POLICY is defined as MSR_PP1_POLICY in SDM.
+**/
+#define MSR_SANDY_BRIDGE_PP1_POLICY              0x00000642
+
+
+/**
+  Package. Uncore C-Box 0, counter n event select MSR.
+
+  @param  ECX  MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSELn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.
+        MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.
+        MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL2 is defined as MSR_UNC_CBO_0_PERFEVTSEL2 in SDM.
+        MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL3 is defined as MSR_UNC_CBO_0_PERFEVTSEL3 in SDM.
+  @{
+**/
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0   0x00000700
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1   0x00000701
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL2   0x00000702
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL3   0x00000703
+/// @}
+
+
+/**
+  Package. Uncore C-Box n, unit status for counter 0-3.
+
+  @param  ECX  MSR_SANDY_BRIDGE_UNC_CBO_n_UNIT_STATUS
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS is defined as MSR_UNC_CBO_0_UNIT_STATUS in SDM.
+        MSR_SANDY_BRIDGE_UNC_CBO_1_UNIT_STATUS is defined as MSR_UNC_CBO_1_UNIT_STATUS in SDM.
+        MSR_SANDY_BRIDGE_UNC_CBO_2_UNIT_STATUS is defined as MSR_UNC_CBO_2_UNIT_STATUS in SDM.
+        MSR_SANDY_BRIDGE_UNC_CBO_3_UNIT_STATUS is defined as MSR_UNC_CBO_3_UNIT_STATUS in SDM.
+        MSR_SANDY_BRIDGE_UNC_CBO_4_UNIT_STATUS is defined as MSR_UNC_CBO_4_UNIT_STATUS in SDM.
+  @{
+**/
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS   0x00000705
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_UNIT_STATUS   0x00000715
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_UNIT_STATUS   0x00000725
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_UNIT_STATUS   0x00000735
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_UNIT_STATUS   0x00000745
+/// @}
+
+
+/**
+  Package. Uncore C-Box 0, performance counter n.
+
+  @param  ECX  MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTRn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.
+        MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.
+        MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR2 is defined as MSR_UNC_CBO_0_PERFCTR2 in SDM.
+        MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR3 is defined as MSR_UNC_CBO_0_PERFCTR3 in SDM.
+  @{
+**/
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0      0x00000706
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1      0x00000707
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR2      0x00000708
+#define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR3      0x00000709
+/// @}
+
+
+/**
+  Package. Uncore C-Box 1, counter n event select MSR.
+
+  @param  ECX  MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSELn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.
+        MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.
+        MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL2 is defined as MSR_UNC_CBO_1_PERFEVTSEL2 in SDM.
+        MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL3 is defined as MSR_UNC_CBO_1_PERFEVTSEL3 in SDM.
+  @{
+**/
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0   0x00000710
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1   0x00000711
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL2   0x00000712
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL3   0x00000713
+/// @}
+
+
+/**
+  Package. Uncore C-Box 1, performance counter n.
+
+  @param  ECX  MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTRn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.
+        MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.
+        MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR2 is defined as MSR_UNC_CBO_1_PERFCTR2 in SDM.
+        MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR3 is defined as MSR_UNC_CBO_1_PERFCTR3 in SDM.
+  @{
+**/
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0      0x00000716
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1      0x00000717
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR2      0x00000718
+#define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR3      0x00000719
+/// @}
+
+
+/**
+  Package. Uncore C-Box 2, counter n event select MSR.
+
+  @param  ECX  MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSELn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.
+        MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.
+        MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL2 is defined as MSR_UNC_CBO_2_PERFEVTSEL2 in SDM.
+        MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL3 is defined as MSR_UNC_CBO_2_PERFEVTSEL3 in SDM.
+  @{
+**/
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0   0x00000720
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1   0x00000721
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL2   0x00000722
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL3   0x00000723
+/// @}
+
+
+/**
+  Package. Uncore C-Box 2, performance counter n.
+
+  @param  ECX  MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTRn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.
+        MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.
+        MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR2 is defined as MSR_UNC_CBO_2_PERFCTR2 in SDM.
+        MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR3 is defined as MSR_UNC_CBO_2_PERFCTR3 in SDM.
+  @{
+**/
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0      0x00000726
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1      0x00000727
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR2      0x00000728
+#define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR3      0x00000729
+/// @}
+
+
+/**
+  Package. Uncore C-Box 3, counter n event select MSR.
+
+  @param  ECX  MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSELn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.
+        MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.
+        MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL2 is defined as MSR_UNC_CBO_3_PERFEVTSEL2 in SDM.
+        MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL3 is defined as MSR_UNC_CBO_3_PERFEVTSEL3 in SDM.
+  @{
+**/
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0   0x00000730
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1   0x00000731
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL2   0x00000732
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL3   0x00000733
+/// @}
+
+
+/**
+  Package. Uncore C-Box 3, performance counter n.
+
+  @param  ECX  MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTRn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.
+        MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.
+        MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR2 is defined as MSR_UNC_CBO_3_PERFCTR2 in SDM.
+        MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR3 is defined as MSR_UNC_CBO_3_PERFCTR3 in SDM.
+  @{
+**/
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0      0x00000736
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1      0x00000737
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR2      0x00000738
+#define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR3      0x00000739
+/// @}
+
+
+/**
+  Package. Uncore C-Box 4, counter n event select MSR.
+
+  @param  ECX  MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSELn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0 is defined as MSR_UNC_CBO_4_PERFEVTSEL0 in SDM.
+        MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL1 is defined as MSR_UNC_CBO_4_PERFEVTSEL1 in SDM.
+        MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL2 is defined as MSR_UNC_CBO_4_PERFEVTSEL2 in SDM.
+        MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL3 is defined as MSR_UNC_CBO_4_PERFEVTSEL3 in SDM.
+  @{
+**/
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0   0x00000740
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL1   0x00000741
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL2   0x00000742
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL3   0x00000743
+/// @}
+
+
+/**
+  Package. Uncore C-Box 4, performance counter n.
+
+  @param  ECX  MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTRn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0 is defined as MSR_UNC_CBO_4_PERFCTR0 in SDM.
+        MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR1 is defined as MSR_UNC_CBO_4_PERFCTR1 in SDM.
+        MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR2 is defined as MSR_UNC_CBO_4_PERFCTR2 in SDM.
+        MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR3 is defined as MSR_UNC_CBO_4_PERFCTR3 in SDM.
+  @{
+**/
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0      0x00000746
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR1      0x00000747
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR2      0x00000748
+#define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR3      0x00000749
+/// @}
+
+
+/**
+  Package. MC Bank Error Configuration (R/W).
+
+  @param  ECX  MSR_SANDY_BRIDGE_ERROR_CONTROL (0x0000017F)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_ERROR_CONTROL);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_ERROR_CONTROL, Msr.Uint64);
+  @endcode
+  @note MSR_SANDY_BRIDGE_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.
+**/
+#define MSR_SANDY_BRIDGE_ERROR_CONTROL           0x0000017F
+
+/**
+  MSR information returned for MSR index #MSR_SANDY_BRIDGE_ERROR_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 1] MemError Log Enable (R/W)  When set, enables IMC status bank
+    /// to log additional info in bits 36:32.
+    ///
+    UINT32  MemErrorLogEnable:1;
+    UINT32  Reserved2:30;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER;
+
+
+/**
+  Package.
+
+  @param  ECX  MSR_SANDY_BRIDGE_PEBS_NUM_ALT (0x0000039C)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_NUM_ALT);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_NUM_ALT, Msr.Uint64);
+  @endcode
+  @note MSR_SANDY_BRIDGE_PEBS_NUM_ALT is defined as MSR_PEBS_NUM_ALT in SDM.
+**/
+#define MSR_SANDY_BRIDGE_PEBS_NUM_ALT            0x0000039C
+
+/**
+  MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_NUM_ALT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] ENABLE_PEBS_NUM_ALT (RW) Write 1 to enable alternate PEBS
+    /// counting logic for specific events requiring additional configuration,
+    /// see Table 19-17.
+    ///
+    UINT32  ENABLE_PEBS_NUM_ALT:1;
+    UINT32  Reserved1:31;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER;
+
+
+/**
+  Package. Package RAPL Perf Status (R/O).
+
+  @param  ECX  MSR_SANDY_BRIDGE_PKG_PERF_STATUS (0x00000613)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_PERF_STATUS);
+  @endcode
+  @note MSR_SANDY_BRIDGE_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.
+**/
+#define MSR_SANDY_BRIDGE_PKG_PERF_STATUS         0x00000613
+
+
+/**
+  Package. DRAM RAPL Power Limit Control (R/W)  See Section 14.9.5, "DRAM RAPL
+  Domain.".
+
+  @param  ECX  MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT (0x00000618)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
+**/
+#define MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT        0x00000618
+
+
+/**
+  Package. DRAM Energy Status (R/O)  See Section 14.9.5, "DRAM RAPL Domain.".
+
+  @param  ECX  MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS (0x00000619)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS);
+  @endcode
+  @note MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
+**/
+#define MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS      0x00000619
+
+
+/**
+  Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
+  RAPL Domain.".
+
+  @param  ECX  MSR_SANDY_BRIDGE_DRAM_PERF_STATUS (0x0000061B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_PERF_STATUS);
+  @endcode
+  @note MSR_SANDY_BRIDGE_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
+**/
+#define MSR_SANDY_BRIDGE_DRAM_PERF_STATUS        0x0000061B
+
+
+/**
+  Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
+
+  @param  ECX  MSR_SANDY_BRIDGE_DRAM_POWER_INFO (0x0000061C)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_INFO);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_INFO, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
+**/
+#define MSR_SANDY_BRIDGE_DRAM_POWER_INFO         0x0000061C
+
+
+/**
+  Package. Uncore U-box UCLK fixed counter control.
+
+  @param  ECX  MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL (0x00000C08)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL is defined as MSR_U_PMON_UCLK_FIXED_CTL in SDM.
+**/
+#define MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL   0x00000C08
+
+
+/**
+  Package. Uncore U-box UCLK fixed counter.
+
+  @param  ECX  MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR (0x00000C09)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR is defined as MSR_U_PMON_UCLK_FIXED_CTR in SDM.
+**/
+#define MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR   0x00000C09
+
+
+/**
+  Package. Uncore U-box perfmon event select for U-box counter 0.
+
+  @param  ECX  MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 (0x00000C10)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 is defined as MSR_U_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0         0x00000C10
+
+
+/**
+  Package. Uncore U-box perfmon event select for U-box counter 1.
+
+  @param  ECX  MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 (0x00000C11)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 is defined as MSR_U_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1         0x00000C11
+
+
+/**
+  Package. Uncore U-box perfmon counter 0.
+
+  @param  ECX  MSR_SANDY_BRIDGE_U_PMON_CTR0 (0x00000C16)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR0);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_U_PMON_CTR0 is defined as MSR_U_PMON_CTR0 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_U_PMON_CTR0             0x00000C16
+
+
+/**
+  Package. Uncore U-box perfmon counter 1.
+
+  @param  ECX  MSR_SANDY_BRIDGE_U_PMON_CTR1 (0x00000C17)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR1);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_U_PMON_CTR1 is defined as MSR_U_PMON_CTR1 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_U_PMON_CTR1             0x00000C17
+
+
+/**
+  Package. Uncore PCU perfmon for PCU-box-wide control.
+
+  @param  ECX  MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL (0x00000C24)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL is defined as MSR_PCU_PMON_BOX_CTL in SDM.
+**/
+#define MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL        0x00000C24
+
+
+/**
+  Package. Uncore PCU perfmon event select for PCU counter 0.
+
+  @param  ECX  MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 (0x00000C30)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 is defined as MSR_PCU_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0       0x00000C30
+
+
+/**
+  Package. Uncore PCU perfmon event select for PCU counter 1.
+
+  @param  ECX  MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 (0x00000C31)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 is defined as MSR_PCU_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1       0x00000C31
+
+
+/**
+  Package. Uncore PCU perfmon event select for PCU counter 2.
+
+  @param  ECX  MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 (0x00000C32)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 is defined as MSR_PCU_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2       0x00000C32
+
+
+/**
+  Package. Uncore PCU perfmon event select for PCU counter 3.
+
+  @param  ECX  MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 (0x00000C33)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 is defined as MSR_PCU_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3       0x00000C33
+
+
+/**
+  Package. Uncore PCU perfmon box-wide filter.
+
+  @param  ECX  MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER (0x00000C34)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER is defined as MSR_PCU_PMON_BOX_FILTER in SDM.
+**/
+#define MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER     0x00000C34
+
+
+/**
+  Package. Uncore PCU perfmon counter 0.
+
+  @param  ECX  MSR_SANDY_BRIDGE_PCU_PMON_CTR0 (0x00000C36)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR0);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_PCU_PMON_CTR0 is defined as MSR_PCU_PMON_CTR0 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_PCU_PMON_CTR0           0x00000C36
+
+
+/**
+  Package. Uncore PCU perfmon counter 1.
+
+  @param  ECX  MSR_SANDY_BRIDGE_PCU_PMON_CTR1 (0x00000C37)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR1);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_PCU_PMON_CTR1 is defined as MSR_PCU_PMON_CTR1 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_PCU_PMON_CTR1           0x00000C37
+
+
+/**
+  Package. Uncore PCU perfmon counter 2.
+
+  @param  ECX  MSR_SANDY_BRIDGE_PCU_PMON_CTR2 (0x00000C38)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR2);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_PCU_PMON_CTR2 is defined as MSR_PCU_PMON_CTR2 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_PCU_PMON_CTR2           0x00000C38
+
+
+/**
+  Package. Uncore PCU perfmon counter 3.
+
+  @param  ECX  MSR_SANDY_BRIDGE_PCU_PMON_CTR3 (0x00000C39)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR3);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_PCU_PMON_CTR3 is defined as MSR_PCU_PMON_CTR3 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_PCU_PMON_CTR3           0x00000C39
+
+
+/**
+  Package. Uncore C-box 0 perfmon local box wide control.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL (0x00000D04)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL is defined as MSR_C0_PMON_BOX_CTL in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL         0x00000D04
+
+
+/**
+  Package. Uncore C-box 0 perfmon event select for C-box 0 counter 0.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 (0x00000D10)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 is defined as MSR_C0_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0        0x00000D10
+
+
+/**
+  Package. Uncore C-box 0 perfmon event select for C-box 0 counter 1.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 (0x00000D11)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 is defined as MSR_C0_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1        0x00000D11
+
+
+/**
+  Package. Uncore C-box 0 perfmon event select for C-box 0 counter 2.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 (0x00000D12)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 is defined as MSR_C0_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2        0x00000D12
+
+
+/**
+  Package. Uncore C-box 0 perfmon event select for C-box 0 counter 3.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 (0x00000D13)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 is defined as MSR_C0_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3        0x00000D13
+
+
+/**
+  Package. Uncore C-box 0 perfmon box wide filter.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER (0x00000D14)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER is defined as MSR_C0_PMON_BOX_FILTER in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER      0x00000D14
+
+
+/**
+  Package. Uncore C-box 0 perfmon counter 0.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C0_PMON_CTR0 (0x00000D16)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR0);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C0_PMON_CTR0            0x00000D16
+
+
+/**
+  Package. Uncore C-box 0 perfmon counter 1.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C0_PMON_CTR1 (0x00000D17)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR1);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C0_PMON_CTR1            0x00000D17
+
+
+/**
+  Package. Uncore C-box 0 perfmon counter 2.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C0_PMON_CTR2 (0x00000D18)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR2);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C0_PMON_CTR2            0x00000D18
+
+
+/**
+  Package. Uncore C-box 0 perfmon counter 3.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C0_PMON_CTR3 (0x00000D19)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR3);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C0_PMON_CTR3            0x00000D19
+
+
+/**
+  Package. Uncore C-box 1 perfmon local box wide control.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL (0x00000D24)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL is defined as MSR_C1_PMON_BOX_CTL in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL         0x00000D24
+
+
+/**
+  Package. Uncore C-box 1 perfmon event select for C-box 1 counter 0.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 (0x00000D30)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 is defined as MSR_C1_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0        0x00000D30
+
+
+/**
+  Package. Uncore C-box 1 perfmon event select for C-box 1 counter 1.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 (0x00000D31)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 is defined as MSR_C1_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1        0x00000D31
+
+
+/**
+  Package. Uncore C-box 1 perfmon event select for C-box 1 counter 2.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 (0x00000D32)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 is defined as MSR_C1_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2        0x00000D32
+
+
+/**
+  Package. Uncore C-box 1 perfmon event select for C-box 1 counter 3.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 (0x00000D33)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 is defined as MSR_C1_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3        0x00000D33
+
+
+/**
+  Package. Uncore C-box 1 perfmon box wide filter.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER (0x00000D34)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER is defined as MSR_C1_PMON_BOX_FILTER in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER      0x00000D34
+
+
+/**
+  Package. Uncore C-box 1 perfmon counter 0.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C1_PMON_CTR0 (0x00000D36)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR0);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C1_PMON_CTR0            0x00000D36
+
+
+/**
+  Package. Uncore C-box 1 perfmon counter 1.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C1_PMON_CTR1 (0x00000D37)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR1);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C1_PMON_CTR1            0x00000D37
+
+
+/**
+  Package. Uncore C-box 1 perfmon counter 2.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C1_PMON_CTR2 (0x00000D38)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR2);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C1_PMON_CTR2            0x00000D38
+
+
+/**
+  Package. Uncore C-box 1 perfmon counter 3.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C1_PMON_CTR3 (0x00000D39)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR3);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C1_PMON_CTR3            0x00000D39
+
+
+/**
+  Package. Uncore C-box 2 perfmon local box wide control.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL (0x00000D44)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL is defined as MSR_C2_PMON_BOX_CTL in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL         0x00000D44
+
+
+/**
+  Package. Uncore C-box 2 perfmon event select for C-box 2 counter 0.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 (0x00000D50)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 is defined as MSR_C2_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0        0x00000D50
+
+
+/**
+  Package. Uncore C-box 2 perfmon event select for C-box 2 counter 1.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 (0x00000D51)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 is defined as MSR_C2_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1        0x00000D51
+
+
+/**
+  Package. Uncore C-box 2 perfmon event select for C-box 2 counter 2.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 (0x00000D52)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 is defined as MSR_C2_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2        0x00000D52
+
+
+/**
+  Package. Uncore C-box 2 perfmon event select for C-box 2 counter 3.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 (0x00000D53)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 is defined as MSR_C2_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3        0x00000D53
+
+
+/**
+  Package. Uncore C-box 2 perfmon box wide filter.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER (0x00000D54)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER is defined as MSR_C2_PMON_BOX_FILTER in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER      0x00000D54
+
+
+/**
+  Package. Uncore C-box 2 perfmon counter 0.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C2_PMON_CTR0 (0x00000D56)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR0);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C2_PMON_CTR0            0x00000D56
+
+
+/**
+  Package. Uncore C-box 2 perfmon counter 1.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C2_PMON_CTR1 (0x00000D57)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR1);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C2_PMON_CTR1            0x00000D57
+
+
+/**
+  Package. Uncore C-box 2 perfmon counter 2.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C2_PMON_CTR2 (0x00000D58)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR2);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C2_PMON_CTR2            0x00000D58
+
+
+/**
+  Package. Uncore C-box 2 perfmon counter 3.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C2_PMON_CTR3 (0x00000D59)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR3);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C2_PMON_CTR3            0x00000D59
+
+
+/**
+  Package. Uncore C-box 3 perfmon local box wide control.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL (0x00000D64)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL is defined as MSR_C3_PMON_BOX_CTL in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL         0x00000D64
+
+
+/**
+  Package. Uncore C-box 3 perfmon event select for C-box 3 counter 0.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 (0x00000D70)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 is defined as MSR_C3_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0        0x00000D70
+
+
+/**
+  Package. Uncore C-box 3 perfmon event select for C-box 3 counter 1.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 (0x00000D71)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 is defined as MSR_C3_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1        0x00000D71
+
+
+/**
+  Package. Uncore C-box 3 perfmon event select for C-box 3 counter 2.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 (0x00000D72)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 is defined as MSR_C3_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2        0x00000D72
+
+
+/**
+  Package. Uncore C-box 3 perfmon event select for C-box 3 counter 3.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 (0x00000D73)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 is defined as MSR_C3_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3        0x00000D73
+
+
+/**
+  Package. Uncore C-box 3 perfmon box wide filter.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER (0x00000D74)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER is defined as MSR_C3_PMON_BOX_FILTER in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER      0x00000D74
+
+
+/**
+  Package. Uncore C-box 3 perfmon counter 0.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C3_PMON_CTR0 (0x00000D76)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR0);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C3_PMON_CTR0            0x00000D76
+
+
+/**
+  Package. Uncore C-box 3 perfmon counter 1.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C3_PMON_CTR1 (0x00000D77)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR1);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C3_PMON_CTR1            0x00000D77
+
+
+/**
+  Package. Uncore C-box 3 perfmon counter 2.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C3_PMON_CTR2 (0x00000D78)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR2);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C3_PMON_CTR2            0x00000D78
+
+
+/**
+  Package. Uncore C-box 3 perfmon counter 3.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C3_PMON_CTR3 (0x00000D79)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR3);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C3_PMON_CTR3            0x00000D79
+
+
+/**
+  Package. Uncore C-box 4 perfmon local box wide control.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL (0x00000D84)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL is defined as MSR_C4_PMON_BOX_CTL in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL         0x00000D84
+
+
+/**
+  Package. Uncore C-box 4 perfmon event select for C-box 4 counter 0.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 (0x00000D90)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 is defined as MSR_C4_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0        0x00000D90
+
+
+/**
+  Package. Uncore C-box 4 perfmon event select for C-box 4 counter 1.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 (0x00000D91)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 is defined as MSR_C4_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1        0x00000D91
+
+
+/**
+  Package. Uncore C-box 4 perfmon event select for C-box 4 counter 2.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 (0x00000D92)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 is defined as MSR_C4_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2        0x00000D92
+
+
+/**
+  Package. Uncore C-box 4 perfmon event select for C-box 4 counter 3.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 (0x00000D93)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 is defined as MSR_C4_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3        0x00000D93
+
+
+/**
+  Package. Uncore C-box 4 perfmon box wide filter.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER (0x00000D94)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER is defined as MSR_C4_PMON_BOX_FILTER in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER      0x00000D94
+
+
+/**
+  Package. Uncore C-box 4 perfmon counter 0.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C4_PMON_CTR0 (0x00000D96)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR0);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C4_PMON_CTR0            0x00000D96
+
+
+/**
+  Package. Uncore C-box 4 perfmon counter 1.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C4_PMON_CTR1 (0x00000D97)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR1);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C4_PMON_CTR1            0x00000D97
+
+
+/**
+  Package. Uncore C-box 4 perfmon counter 2.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C4_PMON_CTR2 (0x00000D98)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR2);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C4_PMON_CTR2            0x00000D98
+
+
+/**
+  Package. Uncore C-box 4 perfmon counter 3.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C4_PMON_CTR3 (0x00000D99)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR3);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C4_PMON_CTR3            0x00000D99
+
+
+/**
+  Package. Uncore C-box 5 perfmon local box wide control.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL (0x00000DA4)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL is defined as MSR_C5_PMON_BOX_CTL in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL         0x00000DA4
+
+
+/**
+  Package. Uncore C-box 5 perfmon event select for C-box 5 counter 0.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 (0x00000DB0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 is defined as MSR_C5_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0        0x00000DB0
+
+
+/**
+  Package. Uncore C-box 5 perfmon event select for C-box 5 counter 1.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 (0x00000DB1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 is defined as MSR_C5_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1        0x00000DB1
+
+
+/**
+  Package. Uncore C-box 5 perfmon event select for C-box 5 counter 2.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 (0x00000DB2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 is defined as MSR_C5_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2        0x00000DB2
+
+
+/**
+  Package. Uncore C-box 5 perfmon event select for C-box 5 counter 3.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 (0x00000DB3)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 is defined as MSR_C5_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3        0x00000DB3
+
+
+/**
+  Package. Uncore C-box 5 perfmon box wide filter.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER (0x00000DB4)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER is defined as MSR_C5_PMON_BOX_FILTER in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER      0x00000DB4
+
+
+/**
+  Package. Uncore C-box 5 perfmon counter 0.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C5_PMON_CTR0 (0x00000DB6)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR0);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C5_PMON_CTR0            0x00000DB6
+
+
+/**
+  Package. Uncore C-box 5 perfmon counter 1.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C5_PMON_CTR1 (0x00000DB7)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR1);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C5_PMON_CTR1            0x00000DB7
+
+
+/**
+  Package. Uncore C-box 5 perfmon counter 2.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C5_PMON_CTR2 (0x00000DB8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR2);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C5_PMON_CTR2            0x00000DB8
+
+
+/**
+  Package. Uncore C-box 5 perfmon counter 3.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C5_PMON_CTR3 (0x00000DB9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR3);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C5_PMON_CTR3            0x00000DB9
+
+
+/**
+  Package. Uncore C-box 6 perfmon local box wide control.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL (0x00000DC4)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL is defined as MSR_C6_PMON_BOX_CTL in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL         0x00000DC4
+
+
+/**
+  Package. Uncore C-box 6 perfmon event select for C-box 6 counter 0.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 (0x00000DD0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 is defined as MSR_C6_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0        0x00000DD0
+
+
+/**
+  Package. Uncore C-box 6 perfmon event select for C-box 6 counter 1.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 (0x00000DD1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 is defined as MSR_C6_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1        0x00000DD1
+
+
+/**
+  Package. Uncore C-box 6 perfmon event select for C-box 6 counter 2.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 (0x00000DD2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 is defined as MSR_C6_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2        0x00000DD2
+
+
+/**
+  Package. Uncore C-box 6 perfmon event select for C-box 6 counter 3.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 (0x00000DD3)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 is defined as MSR_C6_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3        0x00000DD3
+
+
+/**
+  Package. Uncore C-box 6 perfmon box wide filter.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER (0x00000DD4)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER is defined as MSR_C6_PMON_BOX_FILTER in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER      0x00000DD4
+
+
+/**
+  Package. Uncore C-box 6 perfmon counter 0.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C6_PMON_CTR0 (0x00000DD6)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR0);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C6_PMON_CTR0            0x00000DD6
+
+
+/**
+  Package. Uncore C-box 6 perfmon counter 1.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C6_PMON_CTR1 (0x00000DD7)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR1);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C6_PMON_CTR1            0x00000DD7
+
+
+/**
+  Package. Uncore C-box 6 perfmon counter 2.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C6_PMON_CTR2 (0x00000DD8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR2);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C6_PMON_CTR2            0x00000DD8
+
+
+/**
+  Package. Uncore C-box 6 perfmon counter 3.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C6_PMON_CTR3 (0x00000DD9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR3);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C6_PMON_CTR3            0x00000DD9
+
+
+/**
+  Package. Uncore C-box 7 perfmon local box wide control.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL (0x00000DE4)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL is defined as MSR_C7_PMON_BOX_CTL in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL         0x00000DE4
+
+
+/**
+  Package. Uncore C-box 7 perfmon event select for C-box 7 counter 0.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 (0x00000DF0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 is defined as MSR_C7_PMON_EVNTSEL0 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0        0x00000DF0
+
+
+/**
+  Package. Uncore C-box 7 perfmon event select for C-box 7 counter 1.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 (0x00000DF1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 is defined as MSR_C7_PMON_EVNTSEL1 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1        0x00000DF1
+
+
+/**
+  Package. Uncore C-box 7 perfmon event select for C-box 7 counter 2.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 (0x00000DF2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 is defined as MSR_C7_PMON_EVNTSEL2 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2        0x00000DF2
+
+
+/**
+  Package. Uncore C-box 7 perfmon event select for C-box 7 counter 3.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 (0x00000DF3)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 is defined as MSR_C7_PMON_EVNTSEL3 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3        0x00000DF3
+
+
+/**
+  Package. Uncore C-box 7 perfmon box wide filter.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER (0x00000DF4)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER is defined as MSR_C7_PMON_BOX_FILTER in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER      0x00000DF4
+
+
+/**
+  Package. Uncore C-box 7 perfmon counter 0.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C7_PMON_CTR0 (0x00000DF6)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR0);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C7_PMON_CTR0            0x00000DF6
+
+
+/**
+  Package. Uncore C-box 7 perfmon counter 1.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C7_PMON_CTR1 (0x00000DF7)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR1);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR1, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C7_PMON_CTR1            0x00000DF7
+
+
+/**
+  Package. Uncore C-box 7 perfmon counter 2.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C7_PMON_CTR2 (0x00000DF8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR2);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR2, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C7_PMON_CTR2            0x00000DF8
+
+
+/**
+  Package. Uncore C-box 7 perfmon counter 3.
+
+  @param  ECX  MSR_SANDY_BRIDGE_C7_PMON_CTR3 (0x00000DF9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR3);
+  AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR3, Msr);
+  @endcode
+  @note MSR_SANDY_BRIDGE_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.
+**/
+#define MSR_SANDY_BRIDGE_C7_PMON_CTR3            0x00000DF9
+
+#endif
diff --git a/MdePkg/Include/Register/Intel/Msr/SilvermontMsr.h b/MdePkg/Include/Register/Intel/Msr/SilvermontMsr.h
new file mode 100644
index 000000000000..8218346da964
--- /dev/null
+++ b/MdePkg/Include/Register/Intel/Msr/SilvermontMsr.h
@@ -0,0 +1,1612 @@
+/** @file
+  MSR Definitions for Intel processors based on the Silvermont microarchitecture.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+  May 2018, Volume 4: Model-Specific-Registers (MSR)
+
+**/
+
+#ifndef __SILVERMONT_MSR_H__
+#define __SILVERMONT_MSR_H__
+
+#include <Register/Intel/ArchitecturalMsr.h>
+
+/**
+  Is Intel processors based on the Silvermont microarchitecture?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_SILVERMONT_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (                        \
+    DisplayModel == 0x37 || \
+    DisplayModel == 0x4A || \
+    DisplayModel == 0x4D || \
+    DisplayModel == 0x5A || \
+    DisplayModel == 0x5D    \
+    )                       \
+   )
+
+/**
+  Module. Model Specific Platform ID (R).
+
+  @param  ECX  MSR_SILVERMONT_PLATFORM_ID (0x00000017)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SILVERMONT_PLATFORM_ID_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SILVERMONT_PLATFORM_ID_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SILVERMONT_PLATFORM_ID_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PLATFORM_ID);
+  @endcode
+  @note MSR_SILVERMONT_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.
+**/
+#define MSR_SILVERMONT_PLATFORM_ID               0x00000017
+
+/**
+  MSR information returned for MSR index #MSR_SILVERMONT_PLATFORM_ID
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:8;
+    ///
+    /// [Bits 12:8] Maximum Qualified Ratio (R)  The maximum allowed bus ratio.
+    ///
+    UINT32  MaximumQualifiedRatio:5;
+    UINT32  Reserved2:19;
+    UINT32  Reserved3:18;
+    ///
+    /// [Bits 52:50] See Table 2-2.
+    ///
+    UINT32  PlatformId:3;
+    UINT32  Reserved4:11;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SILVERMONT_PLATFORM_ID_REGISTER;
+
+
+/**
+  Module. Processor Hard Power-On Configuration (R/W) Writes ignored.
+
+  @param  ECX  MSR_SILVERMONT_EBL_CR_POWERON (0x0000002A)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SILVERMONT_EBL_CR_POWERON_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SILVERMONT_EBL_CR_POWERON_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SILVERMONT_EBL_CR_POWERON_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_EBL_CR_POWERON);
+  AsmWriteMsr64 (MSR_SILVERMONT_EBL_CR_POWERON, Msr.Uint64);
+  @endcode
+  @note MSR_SILVERMONT_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
+**/
+#define MSR_SILVERMONT_EBL_CR_POWERON            0x0000002A
+
+/**
+  MSR information returned for MSR index #MSR_SILVERMONT_EBL_CR_POWERON
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:32;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SILVERMONT_EBL_CR_POWERON_REGISTER;
+
+
+/**
+  Core. SMI Counter (R/O).
+
+  @param  ECX  MSR_SILVERMONT_SMI_COUNT (0x00000034)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SILVERMONT_SMI_COUNT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SILVERMONT_SMI_COUNT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SILVERMONT_SMI_COUNT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_SMI_COUNT);
+  @endcode
+  @note MSR_SILVERMONT_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.
+**/
+#define MSR_SILVERMONT_SMI_COUNT                 0x00000034
+
+/**
+  MSR information returned for MSR index #MSR_SILVERMONT_SMI_COUNT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 31:0] SMI Count (R/O)  Running count of SMI events since last
+    /// RESET.
+    ///
+    UINT32  SMICount:32;
+    UINT32  Reserved:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SILVERMONT_SMI_COUNT_REGISTER;
+
+
+/**
+  Core. Control Features in Intel 64 Processor (R/W). See Table 2-2.
+
+  @param  ECX  MSR_IA32_SILVERMONT_FEATURE_CONTROL (0x0000003A)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type
+               MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type
+               MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_IA32_FEATURE_CONTROL);
+  AsmWriteMsr64 (MSR_SILVERMONT_IA32_FEATURE_CONTROL, Msr.Uint64);
+  @endcode
+  @note MSR_SILVERMONT_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.
+**/
+#define MSR_SILVERMONT_IA32_FEATURE_CONTROL      0x0000003A
+
+/**
+  MSR information returned for MSR index #MSR_SILVERMONT_IA32_FEATURE_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Lock (R/WL).
+    ///
+    UINT32  Lock:1;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 2] Enable VMX outside SMX operation (R/WL).
+    ///
+    UINT32  EnableVmxOutsideSmx:1;
+    UINT32  Reserved2:29;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER;
+
+
+/**
+  Core. Last Branch Record n From IP (R/W) One of eight pairs of last branch
+  record registers on the last branch record stack. The From_IP part of the
+  stack contains pointers to the source instruction. See also: -  Last Branch
+  Record Stack TOS at 1C9H -  Section 17.5 and record format in Section
+  17.4.8.1.
+
+  @param  ECX  MSR_SILVERMONT_LASTBRANCH_n_FROM_IP
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP);
+  AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_FROM_IP, Msr);
+  @endcode
+  @note MSR_SILVERMONT_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.
+        MSR_SILVERMONT_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.
+        MSR_SILVERMONT_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.
+        MSR_SILVERMONT_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.
+        MSR_SILVERMONT_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.
+        MSR_SILVERMONT_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.
+        MSR_SILVERMONT_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.
+        MSR_SILVERMONT_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.
+  @{
+**/
+#define MSR_SILVERMONT_LASTBRANCH_0_FROM_IP      0x00000040
+#define MSR_SILVERMONT_LASTBRANCH_1_FROM_IP      0x00000041
+#define MSR_SILVERMONT_LASTBRANCH_2_FROM_IP      0x00000042
+#define MSR_SILVERMONT_LASTBRANCH_3_FROM_IP      0x00000043
+#define MSR_SILVERMONT_LASTBRANCH_4_FROM_IP      0x00000044
+#define MSR_SILVERMONT_LASTBRANCH_5_FROM_IP      0x00000045
+#define MSR_SILVERMONT_LASTBRANCH_6_FROM_IP      0x00000046
+#define MSR_SILVERMONT_LASTBRANCH_7_FROM_IP      0x00000047
+/// @}
+
+
+/**
+  Core. Last Branch Record n To IP (R/W) One of eight pairs of last branch
+  record registers on the last branch record stack. The To_IP part of the
+  stack contains pointers to the destination instruction.
+
+  @param  ECX  MSR_SILVERMONT_LASTBRANCH_n_TO_IP
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP);
+  AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_0_TO_IP, Msr);
+  @endcode
+  @note MSR_SILVERMONT_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.
+        MSR_SILVERMONT_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.
+        MSR_SILVERMONT_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.
+        MSR_SILVERMONT_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.
+        MSR_SILVERMONT_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.
+        MSR_SILVERMONT_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.
+        MSR_SILVERMONT_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.
+        MSR_SILVERMONT_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.
+  @{
+**/
+#define MSR_SILVERMONT_LASTBRANCH_0_TO_IP        0x00000060
+#define MSR_SILVERMONT_LASTBRANCH_1_TO_IP        0x00000061
+#define MSR_SILVERMONT_LASTBRANCH_2_TO_IP        0x00000062
+#define MSR_SILVERMONT_LASTBRANCH_3_TO_IP        0x00000063
+#define MSR_SILVERMONT_LASTBRANCH_4_TO_IP        0x00000064
+#define MSR_SILVERMONT_LASTBRANCH_5_TO_IP        0x00000065
+#define MSR_SILVERMONT_LASTBRANCH_6_TO_IP        0x00000066
+#define MSR_SILVERMONT_LASTBRANCH_7_TO_IP        0x00000067
+/// @}
+
+
+/**
+  Module. Scalable Bus Speed(RO) This field indicates the intended scalable
+  bus clock speed for processors based on Silvermont microarchitecture:.
+
+  @param  ECX  MSR_SILVERMONT_FSB_FREQ (0x000000CD)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SILVERMONT_FSB_FREQ_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SILVERMONT_FSB_FREQ_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SILVERMONT_FSB_FREQ_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_FSB_FREQ);
+  @endcode
+  @note MSR_SILVERMONT_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.
+**/
+#define MSR_SILVERMONT_FSB_FREQ                  0x000000CD
+
+/**
+  MSR information returned for MSR index #MSR_SILVERMONT_FSB_FREQ
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 3:0] Scalable Bus Speed
+    ///
+    /// Silvermont Processor Family
+    /// ---------------------------
+    ///   100B: 080.0 MHz
+    ///   000B: 083.3 MHz
+    ///   001B: 100.0 MHz
+    ///   010B: 133.3 MHz
+    ///   011B: 116.7 MHz
+    ///
+    /// Airmont Processor Family
+    /// ---------------------------
+    ///   0000B: 083.3 MHz
+    ///   0001B: 100.0 MHz
+    ///   0010B: 133.3 MHz
+    ///   0011B: 116.7 MHz
+    ///   0100B: 080.0 MHz
+    ///   0101B: 093.3 MHz
+    ///   0110B: 090.0 MHz
+    ///   0111B: 088.9 MHz
+    ///   1000B: 087.5 MHz
+    ///
+    UINT32  ScalableBusSpeed:4;
+    UINT32  Reserved1:28;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SILVERMONT_FSB_FREQ_REGISTER;
+
+
+/**
+  Package. Platform Information: Contains power management and other model
+  specific features enumeration. See http://biosbits.org.
+
+  @param  ECX  MSR_SILVERMONT_PLATFORM_INFO (0x000000CE)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SILVERMONT_PLATFORM_INFO_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SILVERMONT_PLATFORM_INFO_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SILVERMONT_PLATFORM_INFO_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PLATFORM_INFO);
+  AsmWriteMsr64 (MSR_SILVERMONT_PLATFORM_INFO, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SILVERMONT_PLATFORM_INFO             0x000000CE
+
+/**
+  MSR information returned for MSR index #MSR_SILVERMONT_PLATFORM_INFO
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:8;
+    ///
+    /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) This is the ratio
+    /// of the maximum frequency that does not require turbo. Frequency =
+    /// ratio * Scalable Bus Frequency.
+    ///
+    UINT32  MaximumNon_TurboRatio:8;
+    UINT32  Reserved2:16;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SILVERMONT_PLATFORM_INFO_REGISTER;
+
+/**
+  Module. C-State Configuration Control (R/W)  Note: C-state values are
+  processor specific C-state code names, unrelated to MWAIT extension C-state
+  parameters or ACPI CStates. See http://biosbits.org.
+
+  @param  ECX  MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL (0x000000E2)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL);
+  AsmWriteMsr64 (MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
+  @endcode
+  @note MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
+**/
+#define MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL    0x000000E2
+
+/**
+  MSR information returned for MSR index #MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 2:0] Package C-State Limit (R/W)  Specifies the lowest
+    /// processor-specific C-state code name (consuming the least power). for
+    /// the package. The default is set as factory-configured package C-state
+    /// limit. The following C-state code name encodings are supported: 000b:
+    /// C0 (no package C-sate support) 001b: C1 (Behavior is the same as 000b)
+    /// 100b: C4 110b: C6 111b: C7 (Silvermont only).
+    ///
+    UINT32  Limit:3;
+    UINT32  Reserved1:7;
+    ///
+    /// [Bit 10] I/O MWAIT Redirection Enable (R/W)  When set, will map
+    /// IO_read instructions sent to IO register specified by
+    /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.
+    ///
+    UINT32  IO_MWAIT:1;
+    UINT32  Reserved2:4;
+    ///
+    /// [Bit 15] CFG Lock (R/WO)  When set, lock bits 15:0 of this register
+    /// until next reset.
+    ///
+    UINT32  CFGLock:1;
+    UINT32  Reserved3:16;
+    UINT32  Reserved4:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER;
+
+
+/**
+  Module. Power Management IO Redirection in C-state (R/W) See
+  http://biosbits.org.
+
+  @param  ECX  MSR_SILVERMONT_PMG_IO_CAPTURE_BASE (0x000000E4)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PMG_IO_CAPTURE_BASE);
+  AsmWriteMsr64 (MSR_SILVERMONT_PMG_IO_CAPTURE_BASE, Msr.Uint64);
+  @endcode
+  @note MSR_SILVERMONT_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.
+**/
+#define MSR_SILVERMONT_PMG_IO_CAPTURE_BASE       0x000000E4
+
+/**
+  MSR information returned for MSR index #MSR_SILVERMONT_PMG_IO_CAPTURE_BASE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 15:0] LVL_2 Base Address (R/W)  Specifies the base address
+    /// visible to software for IO redirection. If IO MWAIT Redirection is
+    /// enabled, reads to this address will be consumed by the power
+    /// management logic and decoded to MWAIT instructions. When IO port
+    /// address redirection is enabled, this is the IO port address reported
+    /// to the OS/software.
+    ///
+    UINT32  Lvl2Base:16;
+    ///
+    /// [Bits 18:16] C-state Range (R/W)  Specifies the encoding value of the
+    /// maximum C-State code name to be included when IO read to MWAIT
+    /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 100b - C4
+    /// is the max C-State to include 110b - C6 is the max C-State to include
+    /// 111b - C7 is the max C-State to include.
+    ///
+    UINT32  CStateRange:3;
+    UINT32  Reserved1:13;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER;
+
+
+/**
+  Module.
+
+  @param  ECX  MSR_SILVERMONT_BBL_CR_CTL3 (0x0000011E)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SILVERMONT_BBL_CR_CTL3_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SILVERMONT_BBL_CR_CTL3_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SILVERMONT_BBL_CR_CTL3_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_BBL_CR_CTL3);
+  AsmWriteMsr64 (MSR_SILVERMONT_BBL_CR_CTL3, Msr.Uint64);
+  @endcode
+  @note MSR_SILVERMONT_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
+**/
+#define MSR_SILVERMONT_BBL_CR_CTL3               0x0000011E
+
+/**
+  MSR information returned for MSR index #MSR_SILVERMONT_BBL_CR_CTL3
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
+    /// Indicates if the L2 is hardware-disabled.
+    ///
+    UINT32  L2HardwareEnabled:1;
+    UINT32  Reserved1:7;
+    ///
+    /// [Bit 8] L2 Enabled. (R/W)  1 = L2 cache has been initialized 0 =
+    /// Disabled (default) Until this bit is set the processor will not
+    /// respond to the WBINVD instruction or the assertion of the FLUSH# input.
+    ///
+    UINT32  L2Enabled:1;
+    UINT32  Reserved2:14;
+    ///
+    /// [Bit 23] L2 Not Present (RO)  1. = L2 Present 2. = L2 Not Present.
+    ///
+    UINT32  L2NotPresent:1;
+    UINT32  Reserved3:8;
+    UINT32  Reserved4:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SILVERMONT_BBL_CR_CTL3_REGISTER;
+
+
+/**
+  Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
+  handler to handle unsuccessful read of this MSR.
+
+  @param  ECX  MSR_SILVERMONT_FEATURE_CONFIG (0x0000013C)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SILVERMONT_FEATURE_CONFIG_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SILVERMONT_FEATURE_CONFIG_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SILVERMONT_FEATURE_CONFIG_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_FEATURE_CONFIG);
+  AsmWriteMsr64 (MSR_SILVERMONT_FEATURE_CONFIG, Msr.Uint64);
+  @endcode
+  @note MSR_SILVERMONT_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
+**/
+#define MSR_SILVERMONT_FEATURE_CONFIG            0x0000013C
+
+/**
+  MSR information returned for MSR index #MSR_SILVERMONT_FEATURE_CONFIG
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 1:0] AES Configuration (RW-L)  Upon a successful read of this
+    /// MSR, the configuration of AES instruction set availability is as
+    /// follows: 11b: AES instructions are not available until next RESET.
+    /// otherwise, AES instructions are available. Note, AES instruction set
+    /// is not available if read is unsuccessful. If the configuration is not
+    /// 01b, AES instruction can be mis-configured if a privileged agent
+    /// unintentionally writes 11b.
+    ///
+    UINT32  AESConfiguration:2;
+    UINT32  Reserved1:30;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SILVERMONT_FEATURE_CONFIG_REGISTER;
+
+
+/**
+  Enable Misc. Processor Features (R/W)  Allows a variety of processor
+  functions to be enabled and disabled.
+
+  @param  ECX  MSR_SILVERMONT_IA32_MISC_ENABLE (0x000001A0)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_IA32_MISC_ENABLE);
+  AsmWriteMsr64 (MSR_SILVERMONT_IA32_MISC_ENABLE, Msr.Uint64);
+  @endcode
+  @note MSR_SILVERMONT_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
+**/
+#define MSR_SILVERMONT_IA32_MISC_ENABLE          0x000001A0
+
+/**
+  MSR information returned for MSR index #MSR_SILVERMONT_IA32_MISC_ENABLE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Core. Fast-Strings Enable See Table 2-2.
+    ///
+    UINT32  FastStrings:1;
+    UINT32  Reserved1:2;
+    ///
+    /// [Bit 3] Module. Automatic Thermal Control Circuit Enable (R/W) See
+    /// Table 2-2. Default value is 0.
+    ///
+    UINT32  AutomaticThermalControlCircuit:1;
+    UINT32  Reserved2:3;
+    ///
+    /// [Bit 7] Core. Performance Monitoring Available (R) See Table 2-2.
+    ///
+    UINT32  PerformanceMonitoring:1;
+    UINT32  Reserved3:3;
+    ///
+    /// [Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 2-2.
+    ///
+    UINT32  BTS:1;
+    ///
+    /// [Bit 12] Core. Processor Event Based Sampling Unavailable (RO) See
+    /// Table 2-2.
+    ///
+    UINT32  PEBS:1;
+    UINT32  Reserved4:3;
+    ///
+    /// [Bit 16] Module. Enhanced Intel SpeedStep Technology Enable (R/W) See
+    /// Table 2-2.
+    ///
+    UINT32  EIST:1;
+    UINT32  Reserved5:1;
+    ///
+    /// [Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 2-2.
+    ///
+    UINT32  MONITOR:1;
+    UINT32  Reserved6:3;
+    ///
+    /// [Bit 22] Core. Limit CPUID Maxval (R/W) See Table 2-2.
+    ///
+    UINT32  LimitCpuidMaxval:1;
+    ///
+    /// [Bit 23] Module. xTPR Message Disable (R/W) See Table 2-2.
+    ///
+    UINT32  xTPR_Message_Disable:1;
+    UINT32  Reserved7:8;
+    UINT32  Reserved8:2;
+    ///
+    /// [Bit 34] Core. XD Bit Disable (R/W) See Table 2-2.
+    ///
+    UINT32  XD:1;
+    UINT32  Reserved9:3;
+    ///
+    /// [Bit 38] Module. Turbo Mode Disable (R/W) When set to 1 on processors
+    /// that support Intel Turbo Boost Technology, the turbo mode feature is
+    /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:
+    /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:
+    /// EAX[1] reports the processor's support of turbo mode is enabled. Note:
+    /// the power-on default value is used by BIOS to detect hardware support
+    /// of turbo mode. If power-on default value is 1, turbo mode is available
+    /// in the processor. If power-on default value is 0, turbo mode is not
+    /// available.
+    ///
+    UINT32  TurboModeDisable:1;
+    UINT32  Reserved10:25;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER;
+
+
+/**
+  Package.
+
+  @param  ECX  MSR_SILVERMONT_TEMPERATURE_TARGET (0x000001A2)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_TEMPERATURE_TARGET);
+  AsmWriteMsr64 (MSR_SILVERMONT_TEMPERATURE_TARGET, Msr.Uint64);
+  @endcode
+  @note MSR_SILVERMONT_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
+**/
+#define MSR_SILVERMONT_TEMPERATURE_TARGET        0x000001A2
+
+/**
+  MSR information returned for MSR index #MSR_SILVERMONT_TEMPERATURE_TARGET
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:16;
+    ///
+    /// [Bits 23:16] Temperature Target (R)  The default thermal throttling or
+    /// PROCHOT# activation temperature in degree C, The effective temperature
+    /// for thermal throttling or PROCHOT# activation is "Temperature Target"
+    /// + "Target Offset".
+    ///
+    UINT32  TemperatureTarget:8;
+    ///
+    /// [Bits 29:24] Target Offset (R/W)  Specifies an offset in degrees C to
+    /// adjust the throttling and PROCHOT# activation temperature from the
+    /// default target specified in TEMPERATURE_TARGET (bits 23:16).
+    ///
+    UINT32  TargetOffset:6;
+    UINT32  Reserved2:2;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER;
+
+
+/**
+  Miscellaneous Feature Control (R/W).
+
+  @param  ECX  MSR_SILVERMONT_MISC_FEATURE_CONTROL (0x000001A4)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_MISC_FEATURE_CONTROL);
+  AsmWriteMsr64 (MSR_SILVERMONT_MISC_FEATURE_CONTROL, Msr.Uint64);
+  @endcode
+  @note MSR_SILVERMONT_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.
+**/
+#define MSR_SILVERMONT_MISC_FEATURE_CONTROL      0x000001A4
+
+/**
+  MSR information returned for MSR index #MSR_SILVERMONT_MISC_FEATURE_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W)  If 1, disables the
+    /// L2 hardware prefetcher, which fetches additional lines of code or data
+    /// into the L2 cache.
+    ///
+    UINT32  L2HardwarePrefetcherDisable:1;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W)  If 1, disables
+    /// the L1 data cache prefetcher, which fetches the next cache line into
+    /// L1 data cache.
+    ///
+    UINT32  DCUHardwarePrefetcherDisable:1;
+    UINT32  Reserved2:29;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER;
+
+
+/**
+  Module. Offcore Response Event Select Register (R/W).
+
+  @param  ECX  MSR_SILVERMONT_OFFCORE_RSP_0 (0x000001A6)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SILVERMONT_OFFCORE_RSP_0);
+  AsmWriteMsr64 (MSR_SILVERMONT_OFFCORE_RSP_0, Msr);
+  @endcode
+  @note MSR_SILVERMONT_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.
+**/
+#define MSR_SILVERMONT_OFFCORE_RSP_0             0x000001A6
+
+
+/**
+  Module. Offcore Response Event Select Register (R/W).
+
+  @param  ECX  MSR_SILVERMONT_OFFCORE_RSP_1 (0x000001A7)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SILVERMONT_OFFCORE_RSP_1);
+  AsmWriteMsr64 (MSR_SILVERMONT_OFFCORE_RSP_1, Msr);
+  @endcode
+  @note MSR_SILVERMONT_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
+**/
+#define MSR_SILVERMONT_OFFCORE_RSP_1             0x000001A7
+
+
+/**
+  Package. Maximum Ratio Limit of Turbo Mode (RW).
+
+  @param  ECX  MSR_SILVERMONT_TURBO_RATIO_LIMIT (0x000001AD)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_TURBO_RATIO_LIMIT);
+  AsmWriteMsr64 (MSR_SILVERMONT_TURBO_RATIO_LIMIT, Msr.Uint64);
+  @endcode
+  @note MSR_SILVERMONT_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
+**/
+#define MSR_SILVERMONT_TURBO_RATIO_LIMIT         0x000001AD
+
+/**
+  MSR information returned for MSR index #MSR_SILVERMONT_TURBO_RATIO_LIMIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
+    /// limit of 1 core active.
+    ///
+    UINT32  Maximum1C:8;
+    ///
+    /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
+    /// limit of 2 core active.
+    ///
+    UINT32  Maximum2C:8;
+    ///
+    /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
+    /// limit of 3 core active.
+    ///
+    UINT32  Maximum3C:8;
+    ///
+    /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
+    /// limit of 4 core active.
+    ///
+    UINT32  Maximum4C:8;
+    ///
+    /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
+    /// limit of 5 core active.
+    ///
+    UINT32  Maximum5C:8;
+    ///
+    /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
+    /// limit of 6 core active.
+    ///
+    UINT32  Maximum6C:8;
+    ///
+    /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio
+    /// limit of 7 core active.
+    ///
+    UINT32  Maximum7C:8;
+    ///
+    /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio
+    /// limit of 8 core active.
+    ///
+    UINT32  Maximum8C:8;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER;
+
+
+/**
+  Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2,
+  "Filtering of Last Branch Records.".
+
+  @param  ECX  MSR_SILVERMONT_LBR_SELECT (0x000001C8)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SILVERMONT_LBR_SELECT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SILVERMONT_LBR_SELECT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SILVERMONT_LBR_SELECT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_LBR_SELECT);
+  AsmWriteMsr64 (MSR_SILVERMONT_LBR_SELECT, Msr.Uint64);
+  @endcode
+  @note MSR_SILVERMONT_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
+**/
+#define MSR_SILVERMONT_LBR_SELECT                0x000001C8
+
+/**
+  MSR information returned for MSR index #MSR_SILVERMONT_LBR_SELECT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] CPL_EQ_0.
+    ///
+    UINT32  CPL_EQ_0:1;
+    ///
+    /// [Bit 1] CPL_NEQ_0.
+    ///
+    UINT32  CPL_NEQ_0:1;
+    ///
+    /// [Bit 2] JCC.
+    ///
+    UINT32  JCC:1;
+    ///
+    /// [Bit 3] NEAR_REL_CALL.
+    ///
+    UINT32  NEAR_REL_CALL:1;
+    ///
+    /// [Bit 4] NEAR_IND_CALL.
+    ///
+    UINT32  NEAR_IND_CALL:1;
+    ///
+    /// [Bit 5] NEAR_RET.
+    ///
+    UINT32  NEAR_RET:1;
+    ///
+    /// [Bit 6] NEAR_IND_JMP.
+    ///
+    UINT32  NEAR_IND_JMP:1;
+    ///
+    /// [Bit 7] NEAR_REL_JMP.
+    ///
+    UINT32  NEAR_REL_JMP:1;
+    ///
+    /// [Bit 8] FAR_BRANCH.
+    ///
+    UINT32  FAR_BRANCH:1;
+    UINT32  Reserved1:23;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SILVERMONT_LBR_SELECT_REGISTER;
+
+
+/**
+  Core. Last Branch Record Stack TOS (R/W)  Contains an index (bits 0-2) that
+  points to the MSR containing the most recent branch record. See
+  MSR_LASTBRANCH_0_FROM_IP.
+
+  @param  ECX  MSR_SILVERMONT_LASTBRANCH_TOS (0x000001C9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SILVERMONT_LASTBRANCH_TOS);
+  AsmWriteMsr64 (MSR_SILVERMONT_LASTBRANCH_TOS, Msr);
+  @endcode
+  @note MSR_SILVERMONT_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
+**/
+#define MSR_SILVERMONT_LASTBRANCH_TOS            0x000001C9
+
+
+/**
+  Core. Last Exception Record From Linear IP (R)  Contains a pointer to the
+  last branch instruction that the processor executed prior to the last
+  exception that was generated or the last interrupt that was handled.
+
+  @param  ECX  MSR_SILVERMONT_LER_FROM_LIP (0x000001DD)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SILVERMONT_LER_FROM_LIP);
+  @endcode
+  @note MSR_SILVERMONT_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
+**/
+#define MSR_SILVERMONT_LER_FROM_LIP              0x000001DD
+
+
+/**
+  Core. Last Exception Record To Linear IP (R)  This area contains a pointer
+  to the target of the last branch instruction that the processor executed
+  prior to the last exception that was generated or the last interrupt that
+  was handled.
+
+  @param  ECX  MSR_SILVERMONT_LER_TO_LIP (0x000001DE)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SILVERMONT_LER_TO_LIP);
+  @endcode
+  @note MSR_SILVERMONT_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
+**/
+#define MSR_SILVERMONT_LER_TO_LIP                0x000001DE
+
+
+/**
+  Core. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling
+  (PEBS).".
+
+  @param  ECX  MSR_SILVERMONT_PEBS_ENABLE (0x000003F1)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SILVERMONT_PEBS_ENABLE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SILVERMONT_PEBS_ENABLE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SILVERMONT_PEBS_ENABLE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PEBS_ENABLE);
+  AsmWriteMsr64 (MSR_SILVERMONT_PEBS_ENABLE, Msr.Uint64);
+  @endcode
+  @note MSR_SILVERMONT_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
+**/
+#define MSR_SILVERMONT_PEBS_ENABLE               0x000003F1
+
+/**
+  MSR information returned for MSR index #MSR_SILVERMONT_PEBS_ENABLE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Enable PEBS for precise event on IA32_PMC0. (R/W).
+    ///
+    UINT32  PEBS:1;
+    UINT32  Reserved1:31;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SILVERMONT_PEBS_ENABLE_REGISTER;
+
+
+/**
+  Package. Note: C-state values are processor specific C-state code names,
+  unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6
+  Residency Counter. (R/O) Value since last reset that this package is in
+  processor-specific C6 states. Counts at the TSC Frequency.
+
+  @param  ECX  MSR_SILVERMONT_PKG_C6_RESIDENCY (0x000003FA)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SILVERMONT_PKG_C6_RESIDENCY);
+  AsmWriteMsr64 (MSR_SILVERMONT_PKG_C6_RESIDENCY, Msr);
+  @endcode
+  @note MSR_SILVERMONT_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
+**/
+#define MSR_SILVERMONT_PKG_C6_RESIDENCY          0x000003FA
+
+
+/**
+  Core. Note: C-state values are processor specific C-state code names,
+  unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6
+  Residency Counter. (R/O) Value since last reset that this core is in
+  processor-specific C6 states. Counts at the TSC Frequency.
+
+  @param  ECX  MSR_SILVERMONT_CORE_C6_RESIDENCY (0x000003FD)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SILVERMONT_CORE_C6_RESIDENCY);
+  AsmWriteMsr64 (MSR_SILVERMONT_CORE_C6_RESIDENCY, Msr);
+  @endcode
+  @note MSR_SILVERMONT_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.
+**/
+#define MSR_SILVERMONT_CORE_C6_RESIDENCY         0x000003FD
+
+
+/**
+  Core. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2.
+
+  @param  ECX  MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM (0x0000048C)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM);
+  @endcode
+  @note MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.
+**/
+#define MSR_SILVERMONT_IA32_VMX_EPT_VPID_ENUM    0x0000048C
+
+
+/**
+  Core. Capability Reporting Register of VM-Function Controls (R/O) See Table
+  2-2.
+
+  @param  ECX  MSR_SILVERMONT_IA32_VMX_FMFUNC (0x00000491)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SILVERMONT_IA32_VMX_FMFUNC);
+  @endcode
+  @note MSR_SILVERMONT_IA32_VMX_FMFUNC is defined as IA32_VMX_FMFUNC in SDM.
+**/
+#define MSR_SILVERMONT_IA32_VMX_FMFUNC           0x00000491
+
+
+/**
+  Core. Note: C-state values are processor specific C-state code names,
+  unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C1
+  Residency Counter. (R/O) Value since last reset that this core is in
+  processor-specific C1 states. Counts at the TSC frequency.
+
+  @param  ECX  MSR_SILVERMONT_CORE_C1_RESIDENCY (0x00000660)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SILVERMONT_CORE_C1_RESIDENCY);
+  AsmWriteMsr64 (MSR_SILVERMONT_CORE_C1_RESIDENCY, Msr);
+  @endcode
+  @note MSR_SILVERMONT_CORE_C1_RESIDENCY is defined as MSR_CORE_C1_RESIDENCY in SDM.
+**/
+#define MSR_SILVERMONT_CORE_C1_RESIDENCY         0x00000660
+
+
+/**
+  Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1,
+  "RAPL Interfaces.".
+
+  @param  ECX  MSR_SILVERMONT_RAPL_POWER_UNIT (0x00000606)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_RAPL_POWER_UNIT);
+  @endcode
+  @note MSR_SILVERMONT_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
+**/
+#define MSR_SILVERMONT_RAPL_POWER_UNIT           0x00000606
+
+/**
+  MSR information returned for MSR index #MSR_SILVERMONT_RAPL_POWER_UNIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 3:0] Power Units. Power related information (in milliWatts) is
+    /// based on the multiplier, 2^PU; where PU is an unsigned integer
+    /// represented by bits 3:0. Default value is 0101b, indicating power unit
+    /// is in 32 milliWatts increment.
+    ///
+    UINT32  PowerUnits:4;
+    UINT32  Reserved1:4;
+    ///
+    /// [Bits 12:8] Energy Status Units. Energy related information (in
+    /// microJoules) is based on the multiplier, 2^ESU; where ESU is an
+    /// unsigned integer represented by bits 12:8. Default value is 00101b,
+    /// indicating energy unit is in 32 microJoules increment.
+    ///
+    UINT32  EnergyStatusUnits:5;
+    UINT32  Reserved2:3;
+    ///
+    /// [Bits 19:16] Time Unit. The value is 0000b, indicating time unit is in
+    /// one second.
+    ///
+    UINT32  TimeUnits:4;
+    UINT32  Reserved3:12;
+    UINT32  Reserved4:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER;
+
+
+/**
+  Package. PKG RAPL Power Limit Control (R/W).
+
+  @param  ECX  MSR_SILVERMONT_PKG_POWER_LIMIT (0x00000610)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_POWER_LIMIT);
+  AsmWriteMsr64 (MSR_SILVERMONT_PKG_POWER_LIMIT, Msr.Uint64);
+  @endcode
+  @note MSR_SILVERMONT_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.
+**/
+#define MSR_SILVERMONT_PKG_POWER_LIMIT           0x00000610
+
+/**
+  MSR information returned for MSR index #MSR_SILVERMONT_PKG_POWER_LIMIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 14:0] Package Power Limit #1 (R/W) See Section 14.9.3, "Package
+    /// RAPL Domain." and MSR_RAPL_POWER_UNIT in Table 2-8.
+    ///
+    UINT32  Limit:15;
+    ///
+    /// [Bit 15] Enable Power Limit #1. (R/W) See Section 14.9.3, "Package
+    /// RAPL Domain.".
+    ///
+    UINT32  Enable:1;
+    ///
+    /// [Bit 16] Package Clamping Limitation #1. (R/W) See Section 14.9.3,
+    /// "Package RAPL Domain.".
+    ///
+    UINT32  ClampingLimit:1;
+    ///
+    /// [Bits 23:17] Time Window for Power Limit #1. (R/W) in unit of second.
+    /// If 0 is specified in bits [23:17], defaults to 1 second window.
+    ///
+    UINT32  Time:7;
+    UINT32  Reserved1:8;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER;
+
+
+/**
+  Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain."
+  and MSR_RAPL_POWER_UNIT in Table 2-8.
+
+  @param  ECX  MSR_SILVERMONT_PKG_ENERGY_STATUS (0x00000611)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SILVERMONT_PKG_ENERGY_STATUS);
+  @endcode
+  @note MSR_SILVERMONT_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.
+**/
+#define MSR_SILVERMONT_PKG_ENERGY_STATUS         0x00000611
+
+
+/**
+  Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL Domains."
+  and MSR_RAPL_POWER_UNIT in Table 2-8.
+
+  @param  ECX  MSR_SILVERMONT_PP0_ENERGY_STATUS (0x00000639)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SILVERMONT_PP0_ENERGY_STATUS);
+  @endcode
+  @note MSR_SILVERMONT_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
+**/
+#define MSR_SILVERMONT_PP0_ENERGY_STATUS         0x00000639
+
+
+/**
+  Package. Core C6 demotion policy config MSR. Controls per-core C6 demotion
+  policy. Writing a value of 0 disables core level HW demotion policy.
+
+  @param  ECX  MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG (0x00000668)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG);
+  AsmWriteMsr64 (MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG, Msr);
+  @endcode
+  @note MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG is defined as MSR_CC6_DEMOTION_POLICY_CONFIG in SDM.
+**/
+#define MSR_SILVERMONT_CC6_DEMOTION_POLICY_CONFIG 0x00000668
+
+
+/**
+  Package. Module C6 demotion policy config MSR. Controls module (i.e. two
+  cores sharing the second-level cache) C6 demotion policy. Writing a value of
+  0 disables module level HW demotion policy.
+
+  @param  ECX  MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG (0x00000669)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG);
+  AsmWriteMsr64 (MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG, Msr);
+  @endcode
+  @note MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG is defined as MSR_MC6_DEMOTION_POLICY_CONFIG in SDM.
+**/
+#define MSR_SILVERMONT_MC6_DEMOTION_POLICY_CONFIG 0x00000669
+
+
+/**
+  Module. Module C6 Residency Counter (R/0) Note: C-state values are processor
+  specific C-state code names, unrelated to MWAIT extension C-state parameters
+  or ACPI CStates. Time that this module is in module-specific C6 states since
+  last reset. Counts at 1 Mhz frequency.
+
+  @param  ECX  MSR_SILVERMONT_MC6_RESIDENCY_COUNTER (0x00000664)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SILVERMONT_MC6_RESIDENCY_COUNTER);
+  @endcode
+  @note MSR_SILVERMONT_MC6_RESIDENCY_COUNTER is defined as MSR_MC6_RESIDENCY_COUNTER in SDM.
+**/
+#define MSR_SILVERMONT_MC6_RESIDENCY_COUNTER     0x00000664
+
+
+/**
+  Package. PKG RAPL Parameter (R/0).
+
+  @param  ECX  MSR_SILVERMONT_PKG_POWER_INFO (0x0000066E)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SILVERMONT_PKG_POWER_INFO_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SILVERMONT_PKG_POWER_INFO_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SILVERMONT_PKG_POWER_INFO_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PKG_POWER_INFO);
+  @endcode
+  @note MSR_SILVERMONT_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.
+**/
+#define MSR_SILVERMONT_PKG_POWER_INFO            0x0000066E
+
+/**
+  MSR information returned for MSR index #MSR_SILVERMONT_PKG_POWER_INFO
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 14:0] Thermal Spec Power. (R/0) The unsigned integer value is
+    /// the equivalent of thermal specification power of the package domain.
+    /// The unit of this field is specified by the "Power Units" field of
+    /// MSR_RAPL_POWER_UNIT.
+    ///
+    UINT32  ThermalSpecPower:15;
+    UINT32  Reserved1:17;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SILVERMONT_PKG_POWER_INFO_REGISTER;
+
+
+/**
+  Package. PP0 RAPL Power Limit Control (R/W).
+
+  @param  ECX  MSR_SILVERMONT_PP0_POWER_LIMIT (0x00000638)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PP0_POWER_LIMIT);
+  AsmWriteMsr64 (MSR_SILVERMONT_PP0_POWER_LIMIT, Msr.Uint64);
+  @endcode
+  @note MSR_SILVERMONT_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.
+**/
+#define MSR_SILVERMONT_PP0_POWER_LIMIT           0x00000638
+
+/**
+  MSR information returned for MSR index #MSR_SILVERMONT_PP0_POWER_LIMIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 14:0] PP0 Power Limit #1. (R/W) See Section 14.9.4, "PP0/PP1
+    /// RAPL Domains." and MSR_RAPL_POWER_UNIT in Table 35-8.
+    ///
+    UINT32  Limit:15;
+    ///
+    /// [Bit 15] Enable Power Limit #1. (R/W) See Section 14.9.4, "PP0/PP1
+    /// RAPL Domains.".
+    ///
+    UINT32  Enable:1;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bits 23:17] Time Window for Power Limit #1. (R/W) Specifies the time
+    /// duration over which the average power must remain below
+    /// PP0_POWER_LIMIT #1(14:0). Supported Encodings: 0x0: 1 second time
+    /// duration. 0x1: 5 second time duration (Default). 0x2: 10 second time
+    /// duration. 0x3: 15 second time duration. 0x4: 20 second time duration.
+    /// 0x5: 25 second time duration. 0x6: 30 second time duration. 0x7: 35
+    /// second time duration. 0x8: 40 second time duration. 0x9: 45 second
+    /// time duration. 0xA: 50 second time duration. 0xB-0x7F - reserved.
+    ///
+    UINT32  Time:7;
+    UINT32  Reserved2:8;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER;
+
+#endif
diff --git a/MdePkg/Include/Register/Intel/Msr/SkylakeMsr.h b/MdePkg/Include/Register/Intel/Msr/SkylakeMsr.h
new file mode 100644
index 000000000000..a33b18ee0b5d
--- /dev/null
+++ b/MdePkg/Include/Register/Intel/Msr/SkylakeMsr.h
@@ -0,0 +1,3810 @@
+/** @file
+  MSR Definitions for Intel processors based on the Skylake/Kabylake/Coffeelake/Cannonlake microarchitecture.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+  May 2018, Volume 4: Model-Specific-Registers (MSR)
+
+**/
+
+#ifndef __SKYLAKE_MSR_H__
+#define __SKYLAKE_MSR_H__
+
+#include <Register/Intel/ArchitecturalMsr.h>
+
+/**
+  Is Intel processors based on the Skylake microarchitecture?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_SKYLAKE_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (                        \
+    DisplayModel == 0x4E || \
+    DisplayModel == 0x5E || \
+    DisplayModel == 0x55 || \
+    DisplayModel == 0x8E || \
+    DisplayModel == 0x9E || \
+    DisplayModel == 0x66    \
+    )                       \
+   )
+
+/**
+  Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
+  RW if MSR_PLATFORM_INFO.[28] = 1.
+
+  @param  ECX  MSR_SKYLAKE_TURBO_RATIO_LIMIT (0x000001AD)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT);
+  @endcode
+  @note MSR_SKYLAKE_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
+**/
+#define MSR_SKYLAKE_TURBO_RATIO_LIMIT            0x000001AD
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_TURBO_RATIO_LIMIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
+    /// limit of 1 core active.
+    ///
+    UINT32  Maximum1C:8;
+    ///
+    /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
+    /// limit of 2 core active.
+    ///
+    UINT32  Maximum2C:8;
+    ///
+    /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
+    /// limit of 3 core active.
+    ///
+    UINT32  Maximum3C:8;
+    ///
+    /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
+    /// limit of 4 core active.
+    ///
+    UINT32  Maximum4C:8;
+    UINT32  Reserved:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER;
+
+
+/**
+  Thread. Last Branch Record Stack TOS (R/W)  Contains an index (bits 0-4)
+  that points to the MSR containing the most recent branch record.
+
+  @param  ECX  MSR_SKYLAKE_LASTBRANCH_TOS (0x000001C9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS);
+  AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS, Msr);
+  @endcode
+  @note MSR_SKYLAKE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
+**/
+#define MSR_SKYLAKE_LASTBRANCH_TOS               0x000001C9
+
+
+/**
+  Core. Power Control Register See http://biosbits.org.
+
+  @param  ECX  MSR_SKYLAKE_POWER_CTL (0x000001FC)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_POWER_CTL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_POWER_CTL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_POWER_CTL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_POWER_CTL);
+  AsmWriteMsr64 (MSR_SKYLAKE_POWER_CTL, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SKYLAKE_POWER_CTL                     0x000001FC
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_POWER_CTL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the CPU
+    /// to switch to the Minimum Enhanced Intel SpeedStep Technology operating
+    /// point when all execution cores enter MWAIT (C1).
+    ///
+    UINT32  C1EEnable:1;
+    UINT32  Reserved2:17;
+    ///
+    /// [Bit 19] Disable Race to Halt Optimization (R/W) Setting this bit
+    /// disables the Race to Halt optimization and avoids this optimization
+    /// limitation to execute below the most efficient frequency ratio.
+    /// Default value is 0 for processors that support Race to Halt
+    /// optimization. Default value is 1 for processors that do not support
+    /// Race to Halt optimization.
+    ///
+    UINT32  Fix_Me_1:1;
+    ///
+    /// [Bit 20] Disable Energy Efficiency Optimization (R/W) Setting this bit
+    /// disables the P-States energy efficiency optimization. Default value is
+    /// 0. Disable/enable the energy efficiency optimization in P-State legacy
+    /// mode (when IA32_PM_ENABLE[HWP_ENABLE] = 0), has an effect only in the
+    /// turbo range or into PERF_MIN_CTL value if it is not zero set. In HWP
+    /// mode (IA32_PM_ENABLE[HWP_ENABLE] == 1), has an effect between the OS
+    /// desired or OS maximize to the OS minimize performance setting.
+    ///
+    UINT32  DisableEnergyEfficiencyOptimization:1;
+    UINT32  Reserved3:11;
+    UINT32  Reserved4:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_POWER_CTL_REGISTER;
+
+
+/**
+  Package. Lower 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update
+  CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in
+  the package. Lower 64 bits of an 128-bit external entropy value for key
+  derivation of an enclave.
+
+  @param  ECX  MSR_SKYLAKE_SGXOWNEREPOCH0 (0x00000300)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = 0;
+  AsmWriteMsr64 (MSR_SKYLAKE_SGXOWNEREPOCH0, Msr);
+  @endcode
+  @note MSR_SKYLAKE_SGXOWNEREPOCH0 is defined as MSR_SGXOWNER0 in SDM.
+**/
+#define MSR_SKYLAKE_SGXOWNEREPOCH0                    0x00000300
+
+//
+// Define MSR_SKYLAKE_SGXOWNER0 for compatibility due to name change in the SDM.
+//
+#define MSR_SKYLAKE_SGXOWNER0                         MSR_SKYLAKE_SGXOWNEREPOCH0
+/**
+  Package. Upper 64 Bit CR_SGXOWNEREPOCH (W) Writes do not update
+  CR_SGXOWNEREPOCH if CPUID.(EAX=12H, ECX=0):EAX.SGX1 is 1 on any thread in
+  the package. Upper 64 bits of an 128-bit external entropy value for key
+  derivation of an enclave.
+
+  @param  ECX  MSR_SKYLAKE_SGXOWNEREPOCH1 (0x00000301)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = 0;
+  AsmWriteMsr64 (MSR_SKYLAKE_SGXOWNEREPOCH1, Msr);
+  @endcode
+  @note MSR_SKYLAKE_SGXOWNEREPOCH1 is defined as MSR_SGXOWNER1 in SDM.
+**/
+#define MSR_SKYLAKE_SGXOWNEREPOCH1                0x00000301
+
+//
+// Define MSR_SKYLAKE_SGXOWNER1 for compatibility due to name change in the SDM.
+//
+#define MSR_SKYLAKE_SGXOWNER1                     MSR_SKYLAKE_SGXOWNEREPOCH1
+
+
+/**
+  See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring
+  Version 4.".
+
+  @param  ECX  MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS (0x0000038E)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS);
+  AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);
+  @endcode
+  @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.
+**/
+#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS      0x0000038E
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Thread. Ovf_PMC0.
+    ///
+    UINT32  Ovf_PMC0:1;
+    ///
+    /// [Bit 1] Thread. Ovf_PMC1.
+    ///
+    UINT32  Ovf_PMC1:1;
+    ///
+    /// [Bit 2] Thread. Ovf_PMC2.
+    ///
+    UINT32  Ovf_PMC2:1;
+    ///
+    /// [Bit 3] Thread. Ovf_PMC3.
+    ///
+    UINT32  Ovf_PMC3:1;
+    ///
+    /// [Bit 4] Thread. Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).
+    ///
+    UINT32  Ovf_PMC4:1;
+    ///
+    /// [Bit 5] Thread. Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).
+    ///
+    UINT32  Ovf_PMC5:1;
+    ///
+    /// [Bit 6] Thread. Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).
+    ///
+    UINT32  Ovf_PMC6:1;
+    ///
+    /// [Bit 7] Thread. Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).
+    ///
+    UINT32  Ovf_PMC7:1;
+    UINT32  Reserved1:24;
+    ///
+    /// [Bit 32] Thread. Ovf_FixedCtr0.
+    ///
+    UINT32  Ovf_FixedCtr0:1;
+    ///
+    /// [Bit 33] Thread. Ovf_FixedCtr1.
+    ///
+    UINT32  Ovf_FixedCtr1:1;
+    ///
+    /// [Bit 34] Thread. Ovf_FixedCtr2.
+    ///
+    UINT32  Ovf_FixedCtr2:1;
+    UINT32  Reserved2:20;
+    ///
+    /// [Bit 55] Thread. Trace_ToPA_PMI.
+    ///
+    UINT32  Trace_ToPA_PMI:1;
+    UINT32  Reserved3:2;
+    ///
+    /// [Bit 58] Thread. LBR_Frz.
+    ///
+    UINT32  LBR_Frz:1;
+    ///
+    /// [Bit 59] Thread. CTR_Frz.
+    ///
+    UINT32  CTR_Frz:1;
+    ///
+    /// [Bit 60] Thread. ASCI.
+    ///
+    UINT32  ASCI:1;
+    ///
+    /// [Bit 61] Thread. Ovf_Uncore.
+    ///
+    UINT32  Ovf_Uncore:1;
+    ///
+    /// [Bit 62] Thread. Ovf_BufDSSAVE.
+    ///
+    UINT32  Ovf_BufDSSAVE:1;
+    ///
+    /// [Bit 63] Thread. CondChgd.
+    ///
+    UINT32  CondChgd:1;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER;
+
+
+/**
+  See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring
+  Version 4.".
+
+  @param  ECX  MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET);
+  AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);
+  @endcode
+  @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.
+**/
+#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390
+
+/**
+  MSR information returned for MSR index
+  #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Thread. Set 1 to clear Ovf_PMC0.
+    ///
+    UINT32  Ovf_PMC0:1;
+    ///
+    /// [Bit 1] Thread. Set 1 to clear Ovf_PMC1.
+    ///
+    UINT32  Ovf_PMC1:1;
+    ///
+    /// [Bit 2] Thread. Set 1 to clear Ovf_PMC2.
+    ///
+    UINT32  Ovf_PMC2:1;
+    ///
+    /// [Bit 3] Thread. Set 1 to clear Ovf_PMC3.
+    ///
+    UINT32  Ovf_PMC3:1;
+    ///
+    /// [Bit 4] Thread. Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).
+    ///
+    UINT32  Ovf_PMC4:1;
+    ///
+    /// [Bit 5] Thread. Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).
+    ///
+    UINT32  Ovf_PMC5:1;
+    ///
+    /// [Bit 6] Thread. Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).
+    ///
+    UINT32  Ovf_PMC6:1;
+    ///
+    /// [Bit 7] Thread. Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).
+    ///
+    UINT32  Ovf_PMC7:1;
+    UINT32  Reserved1:24;
+    ///
+    /// [Bit 32] Thread. Set 1 to clear Ovf_FixedCtr0.
+    ///
+    UINT32  Ovf_FixedCtr0:1;
+    ///
+    /// [Bit 33] Thread. Set 1 to clear Ovf_FixedCtr1.
+    ///
+    UINT32  Ovf_FixedCtr1:1;
+    ///
+    /// [Bit 34] Thread. Set 1 to clear Ovf_FixedCtr2.
+    ///
+    UINT32  Ovf_FixedCtr2:1;
+    UINT32  Reserved2:20;
+    ///
+    /// [Bit 55] Thread. Set 1 to clear Trace_ToPA_PMI.
+    ///
+    UINT32  Trace_ToPA_PMI:1;
+    UINT32  Reserved3:2;
+    ///
+    /// [Bit 58] Thread. Set 1 to clear LBR_Frz.
+    ///
+    UINT32  LBR_Frz:1;
+    ///
+    /// [Bit 59] Thread. Set 1 to clear CTR_Frz.
+    ///
+    UINT32  CTR_Frz:1;
+    ///
+    /// [Bit 60] Thread. Set 1 to clear ASCI.
+    ///
+    UINT32  ASCI:1;
+    ///
+    /// [Bit 61] Thread. Set 1 to clear Ovf_Uncore.
+    ///
+    UINT32  Ovf_Uncore:1;
+    ///
+    /// [Bit 62] Thread. Set 1 to clear Ovf_BufDSSAVE.
+    ///
+    UINT32  Ovf_BufDSSAVE:1;
+    ///
+    /// [Bit 63] Thread. Set 1 to clear CondChgd.
+    ///
+    UINT32  CondChgd:1;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER;
+
+
+/**
+  See Table 2-2. See Section 18.2.4, "Architectural Performance Monitoring
+  Version 4.".
+
+  @param  ECX  MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET);
+  AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);
+  @endcode
+  @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.
+**/
+#define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET  0x00000391
+
+/**
+  MSR information returned for MSR index
+  #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Thread. Set 1 to cause Ovf_PMC0 = 1.
+    ///
+    UINT32  Ovf_PMC0:1;
+    ///
+    /// [Bit 1] Thread. Set 1 to cause Ovf_PMC1 = 1.
+    ///
+    UINT32  Ovf_PMC1:1;
+    ///
+    /// [Bit 2] Thread. Set 1 to cause Ovf_PMC2 = 1.
+    ///
+    UINT32  Ovf_PMC2:1;
+    ///
+    /// [Bit 3] Thread. Set 1 to cause Ovf_PMC3 = 1.
+    ///
+    UINT32  Ovf_PMC3:1;
+    ///
+    /// [Bit 4] Thread. Set 1 to cause Ovf_PMC4=1 (if CPUID.0AH:EAX[15:8] > 4).
+    ///
+    UINT32  Ovf_PMC4:1;
+    ///
+    /// [Bit 5] Thread. Set 1 to cause Ovf_PMC5=1 (if CPUID.0AH:EAX[15:8] > 5).
+    ///
+    UINT32  Ovf_PMC5:1;
+    ///
+    /// [Bit 6] Thread. Set 1 to cause Ovf_PMC6=1 (if CPUID.0AH:EAX[15:8] > 6).
+    ///
+    UINT32  Ovf_PMC6:1;
+    ///
+    /// [Bit 7] Thread. Set 1 to cause Ovf_PMC7=1 (if CPUID.0AH:EAX[15:8] > 7).
+    ///
+    UINT32  Ovf_PMC7:1;
+    UINT32  Reserved1:24;
+    ///
+    /// [Bit 32] Thread. Set 1 to cause Ovf_FixedCtr0 = 1.
+    ///
+    UINT32  Ovf_FixedCtr0:1;
+    ///
+    /// [Bit 33] Thread. Set 1 to cause Ovf_FixedCtr1 = 1.
+    ///
+    UINT32  Ovf_FixedCtr1:1;
+    ///
+    /// [Bit 34] Thread. Set 1 to cause Ovf_FixedCtr2 = 1.
+    ///
+    UINT32  Ovf_FixedCtr2:1;
+    UINT32  Reserved2:20;
+    ///
+    /// [Bit 55] Thread. Set 1 to cause Trace_ToPA_PMI = 1.
+    ///
+    UINT32  Trace_ToPA_PMI:1;
+    UINT32  Reserved3:2;
+    ///
+    /// [Bit 58] Thread. Set 1 to cause LBR_Frz = 1.
+    ///
+    UINT32  LBR_Frz:1;
+    ///
+    /// [Bit 59] Thread. Set 1 to cause CTR_Frz = 1.
+    ///
+    UINT32  CTR_Frz:1;
+    ///
+    /// [Bit 60] Thread. Set 1 to cause ASCI = 1.
+    ///
+    UINT32  ASCI:1;
+    ///
+    /// [Bit 61] Thread. Set 1 to cause Ovf_Uncore.
+    ///
+    UINT32  Ovf_Uncore:1;
+    ///
+    /// [Bit 62] Thread. Set 1 to cause Ovf_BufDSSAVE.
+    ///
+    UINT32  Ovf_BufDSSAVE:1;
+    UINT32  Reserved4:1;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER;
+
+
+/**
+  Thread. FrontEnd Precise Event Condition Select (R/W).
+
+  @param  ECX  MSR_SKYLAKE_PEBS_FRONTEND (0x000003F7)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_PEBS_FRONTEND_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_PEBS_FRONTEND_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_PEBS_FRONTEND_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PEBS_FRONTEND);
+  AsmWriteMsr64 (MSR_SKYLAKE_PEBS_FRONTEND, Msr.Uint64);
+  @endcode
+  @note MSR_SKYLAKE_PEBS_FRONTEND is defined as MSR_PEBS_FRONTEND in SDM.
+**/
+#define MSR_SKYLAKE_PEBS_FRONTEND                0x000003F7
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_PEBS_FRONTEND
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 2:0] Event Code Select.
+    ///
+    UINT32  EventCodeSelect:3;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 4] Event Code Select High.
+    ///
+    UINT32  EventCodeSelectHigh:1;
+    UINT32  Reserved2:3;
+    ///
+    /// [Bits 19:8] IDQ_Bubble_Length Specifier.
+    ///
+    UINT32  IDQ_Bubble_Length:12;
+    ///
+    /// [Bits 22:20] IDQ_Bubble_Width Specifier.
+    ///
+    UINT32  IDQ_Bubble_Width:3;
+    UINT32  Reserved3:9;
+    UINT32  Reserved4:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_PEBS_FRONTEND_REGISTER;
+
+
+/**
+  Package. PP0 Energy Status (R/O)  See Section 14.9.4, "PP0/PP1 RAPL
+  Domains.".
+
+  @param  ECX  MSR_SKYLAKE_PP0_ENERGY_STATUS (0x00000639)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_PP0_ENERGY_STATUS);
+  @endcode
+  @note MSR_SKYLAKE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
+**/
+#define MSR_SKYLAKE_PP0_ENERGY_STATUS            0x00000639
+
+
+/**
+  Platform*. Platform Energy Counter. (R/O). This MSR is valid only if both
+  platform vendor hardware implementation and BIOS enablement support it. This
+  MSR will read 0 if not valid.
+
+  @param  ECX  MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER (0x0000064D)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER);
+  @endcode
+  @note MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER is defined as MSR_PLATFORM_ENERGY_COUNTER in SDM.
+**/
+#define MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER      0x0000064D
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 31:0] Total energy consumed by all devices in the platform that
+    /// receive power from integrated power delivery mechanism, Included
+    /// platform devices are processor cores, SOC, memory, add-on or
+    /// peripheral devices that get powered directly from the platform power
+    /// delivery means. The energy units are specified in the
+    /// MSR_RAPL_POWER_UNIT.Enery_Status_Unit.
+    ///
+    UINT32  TotalEnergy:32;
+    UINT32  Reserved:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER;
+
+
+/**
+  Thread. Productive Performance Count. (R/O). Hardware's view of workload
+  scalability. See Section 14.4.5.1.
+
+  @param  ECX  MSR_SKYLAKE_PPERF (0x0000064E)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_PPERF);
+  @endcode
+  @note MSR_SKYLAKE_PPERF is defined as MSR_PPERF in SDM.
+**/
+#define MSR_SKYLAKE_PPERF                        0x0000064E
+
+
+/**
+  Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
+  refers to processor core frequency).
+
+  @param  ECX  MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS (0x0000064F)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS);
+  AsmWriteMsr64 (MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
+  @endcode
+  @note MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
+**/
+#define MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS      0x0000064F
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the
+    /// operating system request due to assertion of external PROCHOT.
+    ///
+    UINT32  PROCHOT_Status:1;
+    ///
+    /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
+    /// operating system request due to a thermal event.
+    ///
+    UINT32  ThermalStatus:1;
+    UINT32  Reserved1:2;
+    ///
+    /// [Bit 4] Residency State Regulation Status (R0) When set, frequency is
+    /// reduced below the operating system request due to residency state
+    /// regulation limit.
+    ///
+    UINT32  ResidencyStateRegulationStatus:1;
+    ///
+    /// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency
+    /// is reduced below the operating system request due to Running Average
+    /// Thermal Limit (RATL).
+    ///
+    UINT32  RunningAverageThermalLimitStatus:1;
+    ///
+    /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced
+    /// below the operating system request due to a thermal alert from a
+    /// processor Voltage Regulator (VR).
+    ///
+    UINT32  VRThermAlertStatus:1;
+    ///
+    /// [Bit 7] VR Therm Design Current Status (R0) When set, frequency is
+    /// reduced below the operating system request due to VR thermal design
+    /// current limit.
+    ///
+    UINT32  VRThermDesignCurrentStatus:1;
+    ///
+    /// [Bit 8] Other Status (R0) When set, frequency is reduced below the
+    /// operating system request due to electrical or other constraints.
+    ///
+    UINT32  OtherStatus:1;
+    UINT32  Reserved2:1;
+    ///
+    /// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When
+    /// set, frequency is reduced below the operating system request due to
+    /// package/platform-level power limiting PL1.
+    ///
+    UINT32  PL1Status:1;
+    ///
+    /// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When
+    /// set, frequency is reduced below the operating system request due to
+    /// package/platform-level power limiting PL2/PL3.
+    ///
+    UINT32  PL2Status:1;
+    ///
+    /// [Bit 12] Max Turbo Limit Status (R0) When set, frequency is reduced
+    /// below the operating system request due to multi-core turbo limits.
+    ///
+    UINT32  MaxTurboLimitStatus:1;
+    ///
+    /// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency
+    /// is reduced below the operating system request due to Turbo transition
+    /// attenuation. This prevents performance degradation due to frequent
+    /// operating ratio changes.
+    ///
+    UINT32  TurboTransitionAttenuationStatus:1;
+    UINT32  Reserved3:2;
+    ///
+    /// [Bit 16] PROCHOT Log  When set, indicates that the PROCHOT Status bit
+    /// has asserted since the log bit was last cleared. This log bit will
+    /// remain set until cleared by software writing 0.
+    ///
+    UINT32  PROCHOT_Log:1;
+    ///
+    /// [Bit 17] Thermal Log  When set, indicates that the Thermal Status bit
+    /// has asserted since the log bit was last cleared. This log bit will
+    /// remain set until cleared by software writing 0.
+    ///
+    UINT32  ThermalLog:1;
+    UINT32  Reserved4:2;
+    ///
+    /// [Bit 20] Residency State Regulation Log  When set, indicates that the
+    /// Residency State Regulation Status bit has asserted since the log bit
+    /// was last cleared. This log bit will remain set until cleared by
+    /// software writing 0.
+    ///
+    UINT32  ResidencyStateRegulationLog:1;
+    ///
+    /// [Bit 21] Running Average Thermal Limit Log  When set, indicates that
+    /// the RATL Status bit has asserted since the log bit was last cleared.
+    /// This log bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  RunningAverageThermalLimitLog:1;
+    ///
+    /// [Bit 22] VR Therm Alert Log  When set, indicates that the VR Therm
+    /// Alert Status bit has asserted since the log bit was last cleared. This
+    /// log bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  VRThermAlertLog:1;
+    ///
+    /// [Bit 23] VR Thermal Design Current Log  When set, indicates that the
+    /// VR TDC Status bit has asserted since the log bit was last cleared.
+    /// This log bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  VRThermalDesignCurrentLog:1;
+    ///
+    /// [Bit 24] Other Log  When set, indicates that the Other Status bit has
+    /// asserted since the log bit was last cleared. This log bit will remain
+    /// set until cleared by software writing 0.
+    ///
+    UINT32  OtherLog:1;
+    UINT32  Reserved5:1;
+    ///
+    /// [Bit 26] Package/Platform-Level PL1 Power Limiting Log  When set,
+    /// indicates that the Package or Platform Level PL1 Power Limiting Status
+    /// bit has asserted since the log bit was last cleared. This log bit will
+    /// remain set until cleared by software writing 0.
+    ///
+    UINT32  PL1Log:1;
+    ///
+    /// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set,
+    /// indicates that the Package or Platform Level PL2/PL3 Power Limiting
+    /// Status bit has asserted since the log bit was last cleared. This log
+    /// bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  PL2Log:1;
+    ///
+    /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo
+    /// Limit Status bit has asserted since the log bit was last cleared. This
+    /// log bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  MaxTurboLimitLog:1;
+    ///
+    /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the
+    /// Turbo Transition Attenuation Status bit has asserted since the log bit
+    /// was last cleared. This log bit will remain set until cleared by
+    /// software writing 0.
+    ///
+    UINT32  TurboTransitionAttenuationLog:1;
+    UINT32  Reserved6:2;
+    UINT32  Reserved7:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER;
+
+
+/**
+  Package. HDC Configuration (R/W)..
+
+  @param  ECX  MSR_SKYLAKE_PKG_HDC_CONFIG (0x00000652)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_CONFIG);
+  AsmWriteMsr64 (MSR_SKYLAKE_PKG_HDC_CONFIG, Msr.Uint64);
+  @endcode
+  @note MSR_SKYLAKE_PKG_HDC_CONFIG is defined as MSR_PKG_HDC_CONFIG in SDM.
+**/
+#define MSR_SKYLAKE_PKG_HDC_CONFIG               0x00000652
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_PKG_HDC_CONFIG
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 2:0] PKG_Cx_Monitor.  Configures Package Cx state threshold for
+    /// MSR_PKG_HDC_DEEP_RESIDENCY.
+    ///
+    UINT32  PKG_Cx_Monitor:3;
+    UINT32  Reserved1:29;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER;
+
+
+/**
+  Core. Core HDC Idle Residency. (R/O). Core_Cx_Duty_Cycle_Cnt.
+
+  @param  ECX  MSR_SKYLAKE_CORE_HDC_RESIDENCY (0x00000653)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_HDC_RESIDENCY);
+  @endcode
+  @note MSR_SKYLAKE_CORE_HDC_RESIDENCY is defined as MSR_CORE_HDC_RESIDENCY in SDM.
+**/
+#define MSR_SKYLAKE_CORE_HDC_RESIDENCY           0x00000653
+
+
+/**
+  Package. Accumulate the cycles the package was in C2 state and at least one
+  logical processor was in forced idle. (R/O). Pkg_C2_Duty_Cycle_Cnt.
+
+  @param  ECX  MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY (0x00000655)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY);
+  @endcode
+  @note MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY is defined as MSR_PKG_HDC_SHALLOW_RESIDENCY in SDM.
+**/
+#define MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY    0x00000655
+
+
+/**
+  Package. Package Cx HDC Idle Residency. (R/O). Pkg_Cx_Duty_Cycle_Cnt.
+
+  @param  ECX  MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY (0x00000656)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY);
+  @endcode
+  @note MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY is defined as MSR_PKG_HDC_DEEP_RESIDENCY in SDM.
+**/
+#define MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY       0x00000656
+
+
+/**
+  Package. Core-count Weighted C0 Residency. (R/O). Increment at the same rate
+  as the TSC. The increment each cycle is weighted by the number of processor
+  cores in the package that reside in C0. If N cores are simultaneously in C0,
+  then each cycle the counter increments by N.
+
+  @param  ECX  MSR_SKYLAKE_WEIGHTED_CORE_C0 (0x00000658)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_WEIGHTED_CORE_C0);
+  @endcode
+  @note MSR_SKYLAKE_WEIGHTED_CORE_C0 is defined as MSR_WEIGHTED_CORE_C0 in SDM.
+**/
+#define MSR_SKYLAKE_WEIGHTED_CORE_C0             0x00000658
+
+
+/**
+  Package. Any Core C0 Residency. (R/O). Increment at the same rate as the
+  TSC. The increment each cycle is one if any processor core in the package is
+  in C0.
+
+  @param  ECX  MSR_SKYLAKE_ANY_CORE_C0 (0x00000659)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_ANY_CORE_C0);
+  @endcode
+  @note MSR_SKYLAKE_ANY_CORE_C0 is defined as MSR_ANY_CORE_C0 in SDM.
+**/
+#define MSR_SKYLAKE_ANY_CORE_C0                  0x00000659
+
+
+/**
+  Package. Any Graphics Engine C0 Residency. (R/O). Increment at the same rate
+  as the TSC. The increment each cycle is one if any processor graphic
+  device's compute engines are in C0.
+
+  @param  ECX  MSR_SKYLAKE_ANY_GFXE_C0 (0x0000065A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_ANY_GFXE_C0);
+  @endcode
+  @note MSR_SKYLAKE_ANY_GFXE_C0 is defined as MSR_ANY_GFXE_C0 in SDM.
+**/
+#define MSR_SKYLAKE_ANY_GFXE_C0                  0x0000065A
+
+
+/**
+  Package. Core and Graphics Engine Overlapped C0 Residency. (R/O). Increment
+  at the same rate as the TSC. The increment each cycle is one if at least one
+  compute engine of the processor graphics is in C0 and at least one processor
+  core in the package is also in C0.
+
+  @param  ECX  MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 (0x0000065B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0);
+  @endcode
+  @note MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 is defined as MSR_CORE_GFXE_OVERLAP_C0 in SDM.
+**/
+#define MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0         0x0000065B
+
+
+/**
+  Platform*. Platform Power Limit Control (R/W-L) Allows platform BIOS to
+  limit power consumption of the platform devices to the specified values. The
+  Long Duration power consumption is specified via Platform_Power_Limit_1 and
+  Platform_Power_Limit_1_Time. The Short Duration power consumption limit is
+  specified via the Platform_Power_Limit_2 with duration chosen by the
+  processor. The processor implements an exponential-weighted algorithm in the
+  placement of the time windows.
+
+  @param  ECX  MSR_SKYLAKE_PLATFORM_POWER_LIMIT (0x0000065C)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_POWER_LIMIT);
+  AsmWriteMsr64 (MSR_SKYLAKE_PLATFORM_POWER_LIMIT, Msr.Uint64);
+  @endcode
+  @note MSR_SKYLAKE_PLATFORM_POWER_LIMIT is defined as MSR_PLATFORM_POWER_LIMIT in SDM.
+**/
+#define MSR_SKYLAKE_PLATFORM_POWER_LIMIT         0x0000065C
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_POWER_LIMIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 14:0] Platform Power Limit #1. Average Power limit value which
+    /// the platform must not exceed over a time window as specified by
+    /// Power_Limit_1_TIME field. The default value is the Thermal Design
+    /// Power (TDP) and varies with product skus. The unit is specified in
+    /// MSR_RAPLPOWER_UNIT.
+    ///
+    UINT32  PlatformPowerLimit1:15;
+    ///
+    /// [Bit 15] Enable Platform Power Limit #1. When set, enables the
+    /// processor to apply control policy such that the platform power does
+    /// not exceed Platform Power limit #1 over the time window specified by
+    /// Power Limit #1 Time Window.
+    ///
+    UINT32  EnablePlatformPowerLimit1:1;
+    ///
+    /// [Bit 16] Platform Clamping Limitation #1. When set, allows the
+    /// processor to go below the OS requested P states in order to maintain
+    /// the power below specified Platform Power Limit #1 value. This bit is
+    /// writeable only when CPUID (EAX=6):EAX[4] is set.
+    ///
+    UINT32  PlatformClampingLimitation1:1;
+    ///
+    /// [Bits 23:17] Time Window for Platform Power Limit #1. Specifies the
+    /// duration of the time window over which Platform Power Limit 1 value
+    /// should be maintained for sustained long duration. This field is made
+    /// up of two numbers from the following equation: Time Window = (float)
+    /// ((1+(X/4))*(2^Y)), where: X. = POWER_LIMIT_1_TIME[23:22] Y. =
+    /// POWER_LIMIT_1_TIME[21:17]. The maximum allowed value in this field is
+    /// defined in MSR_PKG_POWER_INFO[PKG_MAX_WIN]. The default value is 0DH,
+    /// The unit is specified in MSR_RAPLPOWER_UNIT[Time Unit].
+    ///
+    UINT32  Time:7;
+    UINT32  Reserved1:8;
+    ///
+    /// [Bits 46:32] Platform Power Limit #2. Average Power limit value which
+    /// the platform must not exceed over the Short Duration time window
+    /// chosen by the processor. The recommended default value is 1.25 times
+    /// the Long Duration Power Limit (i.e. Platform Power Limit # 1).
+    ///
+    UINT32  PlatformPowerLimit2:15;
+    ///
+    /// [Bit 47] Enable Platform Power Limit #2. When set, enables the
+    /// processor to apply control policy such that the platform power does
+    /// not exceed Platform Power limit #2 over the Short Duration time window.
+    ///
+    UINT32  EnablePlatformPowerLimit2:1;
+    ///
+    /// [Bit 48] Platform Clamping Limitation #2. When set, allows the
+    /// processor to go below the OS requested P states in order to maintain
+    /// the power below specified Platform Power Limit #2 value.
+    ///
+    UINT32  PlatformClampingLimitation2:1;
+    UINT32  Reserved2:14;
+    ///
+    /// [Bit 63] Lock. Setting this bit will lock all other bits of this MSR
+    /// until system RESET.
+    ///
+    UINT32  Lock:1;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER;
+
+
+/**
+  Thread. Last Branch Record n From IP (R/W) One of 32 triplets of last
+  branch record registers on the last branch record stack. This part of the
+  stack contains pointers to the source instruction. See also: -  Last Branch
+  Record Stack TOS at 1C9H -  Section 17.10.
+
+  @param  ECX  MSR_SKYLAKE_LASTBRANCH_n_FROM_IP
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_16_FROM_IP);
+  AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_16_FROM_IP, Msr);
+  @endcode
+  @note MSR_SKYLAKE_LASTBRANCH_16_FROM_IP is defined as MSR_LASTBRANCH_16_FROM_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_17_FROM_IP is defined as MSR_LASTBRANCH_17_FROM_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_18_FROM_IP is defined as MSR_LASTBRANCH_18_FROM_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_19_FROM_IP is defined as MSR_LASTBRANCH_19_FROM_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_20_FROM_IP is defined as MSR_LASTBRANCH_20_FROM_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_21_FROM_IP is defined as MSR_LASTBRANCH_21_FROM_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_22_FROM_IP is defined as MSR_LASTBRANCH_22_FROM_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_23_FROM_IP is defined as MSR_LASTBRANCH_23_FROM_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_24_FROM_IP is defined as MSR_LASTBRANCH_24_FROM_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_25_FROM_IP is defined as MSR_LASTBRANCH_25_FROM_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_26_FROM_IP is defined as MSR_LASTBRANCH_26_FROM_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_27_FROM_IP is defined as MSR_LASTBRANCH_27_FROM_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_28_FROM_IP is defined as MSR_LASTBRANCH_28_FROM_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_29_FROM_IP is defined as MSR_LASTBRANCH_29_FROM_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_30_FROM_IP is defined as MSR_LASTBRANCH_30_FROM_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_31_FROM_IP is defined as MSR_LASTBRANCH_31_FROM_IP in SDM.
+  @{
+**/
+#define MSR_SKYLAKE_LASTBRANCH_16_FROM_IP        0x00000690
+#define MSR_SKYLAKE_LASTBRANCH_17_FROM_IP        0x00000691
+#define MSR_SKYLAKE_LASTBRANCH_18_FROM_IP        0x00000692
+#define MSR_SKYLAKE_LASTBRANCH_19_FROM_IP        0x00000693
+#define MSR_SKYLAKE_LASTBRANCH_20_FROM_IP        0x00000694
+#define MSR_SKYLAKE_LASTBRANCH_21_FROM_IP        0x00000695
+#define MSR_SKYLAKE_LASTBRANCH_22_FROM_IP        0x00000696
+#define MSR_SKYLAKE_LASTBRANCH_23_FROM_IP        0x00000697
+#define MSR_SKYLAKE_LASTBRANCH_24_FROM_IP        0x00000698
+#define MSR_SKYLAKE_LASTBRANCH_25_FROM_IP        0x00000699
+#define MSR_SKYLAKE_LASTBRANCH_26_FROM_IP        0x0000069A
+#define MSR_SKYLAKE_LASTBRANCH_27_FROM_IP        0x0000069B
+#define MSR_SKYLAKE_LASTBRANCH_28_FROM_IP        0x0000069C
+#define MSR_SKYLAKE_LASTBRANCH_29_FROM_IP        0x0000069D
+#define MSR_SKYLAKE_LASTBRANCH_30_FROM_IP        0x0000069E
+#define MSR_SKYLAKE_LASTBRANCH_31_FROM_IP        0x0000069F
+/// @}
+
+
+/**
+  Package. Indicator of Frequency Clipping in the Processor Graphics (R/W)
+  (frequency refers to processor graphics frequency).
+
+  @param  ECX  MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS (0x000006B0)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS);
+  AsmWriteMsr64 (MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS, Msr.Uint64);
+  @endcode
+  @note MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS is defined as MSR_GRAPHICS_PERF_LIMIT_REASONS in SDM.
+**/
+#define MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS  0x000006B0
+
+/**
+  MSR information returned for MSR index
+  #MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced due to
+    /// assertion of external PROCHOT.
+    ///
+    UINT32  PROCHOT_Status:1;
+    ///
+    /// [Bit 1] Thermal Status (R0) When set, frequency is reduced due to a
+    /// thermal event.
+    ///
+    UINT32  ThermalStatus:1;
+    UINT32  Reserved1:3;
+    ///
+    /// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency
+    /// is reduced due to running average thermal limit.
+    ///
+    UINT32  RunningAverageThermalLimitStatus:1;
+    ///
+    /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced due
+    /// to a thermal alert from a processor Voltage Regulator.
+    ///
+    UINT32  VRThermAlertStatus:1;
+    ///
+    /// [Bit 7] VR Thermal Design Current Status (R0) When set, frequency is
+    /// reduced due to VR TDC limit.
+    ///
+    UINT32  VRThermalDesignCurrentStatus:1;
+    ///
+    /// [Bit 8] Other Status (R0) When set, frequency is reduced due to
+    /// electrical or other constraints.
+    ///
+    UINT32  OtherStatus:1;
+    UINT32  Reserved2:1;
+    ///
+    /// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When
+    /// set, frequency is reduced due to package/platform-level power limiting
+    /// PL1.
+    ///
+    UINT32  PL1Status:1;
+    ///
+    /// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When
+    /// set, frequency is reduced due to package/platform-level power limiting
+    /// PL2/PL3.
+    ///
+    UINT32  PL2Status:1;
+    ///
+    /// [Bit 12] Inefficient Operation Status (R0) When set, processor
+    /// graphics frequency is operating below target frequency.
+    ///
+    UINT32  InefficientOperationStatus:1;
+    UINT32  Reserved3:3;
+    ///
+    /// [Bit 16] PROCHOT Log  When set, indicates that the PROCHOT Status bit
+    /// has asserted since the log bit was last cleared. This log bit will
+    /// remain set until cleared by software writing 0.
+    ///
+    UINT32  PROCHOT_Log:1;
+    ///
+    /// [Bit 17] Thermal Log  When set, indicates that the Thermal Status bit
+    /// has asserted since the log bit was last cleared. This log bit will
+    /// remain set until cleared by software writing 0.
+    ///
+    UINT32  ThermalLog:1;
+    UINT32  Reserved4:3;
+    ///
+    /// [Bit 21] Running Average Thermal Limit Log  When set, indicates that
+    /// the RATL Status bit has asserted since the log bit was last cleared.
+    /// This log bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  RunningAverageThermalLimitLog:1;
+    ///
+    /// [Bit 22] VR Therm Alert Log  When set, indicates that the VR Therm
+    /// Alert Status bit has asserted since the log bit was last cleared. This
+    /// log bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  VRThermAlertLog:1;
+    ///
+    /// [Bit 23] VR Thermal Design Current Log  When set, indicates that the
+    /// VR Therm Alert Status bit has asserted since the log bit was last
+    /// cleared. This log bit will remain set until cleared by software
+    /// writing 0.
+    ///
+    UINT32  VRThermalDesignCurrentLog:1;
+    ///
+    /// [Bit 24] Other Log  When set, indicates that the OTHER Status bit has
+    /// asserted since the log bit was last cleared. This log bit will remain
+    /// set until cleared by software writing 0.
+    ///
+    UINT32  OtherLog:1;
+    UINT32  Reserved5:1;
+    ///
+    /// [Bit 26] Package/Platform-Level PL1 Power Limiting Log  When set,
+    /// indicates that the Package/Platform Level PL1 Power Limiting Status
+    /// bit has asserted since the log bit was last cleared. This log bit will
+    /// remain set until cleared by software writing 0.
+    ///
+    UINT32  PL1Log:1;
+    ///
+    /// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set,
+    /// indicates that the Package/Platform Level PL2 Power Limiting Status
+    /// bit has asserted since the log bit was last cleared. This log bit will
+    /// remain set until cleared by software writing 0.
+    ///
+    UINT32  PL2Log:1;
+    ///
+    /// [Bit 28] Inefficient Operation Log When set, indicates that the
+    /// Inefficient Operation Status bit has asserted since the log bit was
+    /// last cleared. This log bit will remain set until cleared by software
+    /// writing 0.
+    ///
+    UINT32  InefficientOperationLog:1;
+    UINT32  Reserved6:3;
+    UINT32  Reserved7:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER;
+
+
+/**
+  Package. Indicator of Frequency Clipping in the Ring Interconnect (R/W)
+  (frequency refers to ring interconnect in the uncore).
+
+  @param  ECX  MSR_SKYLAKE_RING_PERF_LIMIT_REASONS (0x000006B1)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RING_PERF_LIMIT_REASONS);
+  AsmWriteMsr64 (MSR_SKYLAKE_RING_PERF_LIMIT_REASONS, Msr.Uint64);
+  @endcode
+  @note MSR_SKYLAKE_RING_PERF_LIMIT_REASONS is defined as MSR_RING_PERF_LIMIT_REASONS in SDM.
+**/
+#define MSR_SKYLAKE_RING_PERF_LIMIT_REASONS      0x000006B1
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_RING_PERF_LIMIT_REASONS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced due to
+    /// assertion of external PROCHOT.
+    ///
+    UINT32  PROCHOT_Status:1;
+    ///
+    /// [Bit 1] Thermal Status (R0) When set, frequency is reduced due to a
+    /// thermal event.
+    ///
+    UINT32  ThermalStatus:1;
+    UINT32  Reserved1:3;
+    ///
+    /// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency
+    /// is reduced due to running average thermal limit.
+    ///
+    UINT32  RunningAverageThermalLimitStatus:1;
+    ///
+    /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced due
+    /// to a thermal alert from a processor Voltage Regulator.
+    ///
+    UINT32  VRThermAlertStatus:1;
+    ///
+    /// [Bit 7] VR Thermal Design Current Status (R0) When set, frequency is
+    /// reduced due to VR TDC limit.
+    ///
+    UINT32  VRThermalDesignCurrentStatus:1;
+    ///
+    /// [Bit 8] Other Status (R0) When set, frequency is reduced due to
+    /// electrical or other constraints.
+    ///
+    UINT32  OtherStatus:1;
+    UINT32  Reserved2:1;
+    ///
+    /// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When
+    /// set, frequency is reduced due to package/Platform-level power limiting
+    /// PL1.
+    ///
+    UINT32  PL1Status:1;
+    ///
+    /// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When
+    /// set, frequency is reduced due to package/Platform-level power limiting
+    /// PL2/PL3.
+    ///
+    UINT32  PL2Status:1;
+    UINT32  Reserved3:4;
+    ///
+    /// [Bit 16] PROCHOT Log  When set, indicates that the PROCHOT Status bit
+    /// has asserted since the log bit was last cleared. This log bit will
+    /// remain set until cleared by software writing 0.
+    ///
+    UINT32  PROCHOT_Log:1;
+    ///
+    /// [Bit 17] Thermal Log  When set, indicates that the Thermal Status bit
+    /// has asserted since the log bit was last cleared. This log bit will
+    /// remain set until cleared by software writing 0.
+    ///
+    UINT32  ThermalLog:1;
+    UINT32  Reserved4:3;
+    ///
+    /// [Bit 21] Running Average Thermal Limit Log  When set, indicates that
+    /// the RATL Status bit has asserted since the log bit was last cleared.
+    /// This log bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  RunningAverageThermalLimitLog:1;
+    ///
+    /// [Bit 22] VR Therm Alert Log  When set, indicates that the VR Therm
+    /// Alert Status bit has asserted since the log bit was last cleared. This
+    /// log bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  VRThermAlertLog:1;
+    ///
+    /// [Bit 23] VR Thermal Design Current Log  When set, indicates that the
+    /// VR Therm Alert Status bit has asserted since the log bit was last
+    /// cleared. This log bit will remain set until cleared by software
+    /// writing 0.
+    ///
+    UINT32  VRThermalDesignCurrentLog:1;
+    ///
+    /// [Bit 24] Other Log  When set, indicates that the OTHER Status bit has
+    /// asserted since the log bit was last cleared. This log bit will remain
+    /// set until cleared by software writing 0.
+    ///
+    UINT32  OtherLog:1;
+    UINT32  Reserved5:1;
+    ///
+    /// [Bit 26] Package/Platform-Level PL1 Power Limiting Log  When set,
+    /// indicates that the Package/Platform Level PL1 Power Limiting Status
+    /// bit has asserted since the log bit was last cleared. This log bit will
+    /// remain set until cleared by software writing 0.
+    ///
+    UINT32  PL1Log:1;
+    ///
+    /// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set,
+    /// indicates that the Package/Platform Level PL2 Power Limiting Status
+    /// bit has asserted since the log bit was last cleared. This log bit will
+    /// remain set until cleared by software writing 0.
+    ///
+    UINT32  PL2Log:1;
+    UINT32  Reserved6:4;
+    UINT32  Reserved7:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER;
+
+
+/**
+  Thread. Last Branch Record n To IP (R/W) One of 32 triplets of last branch
+  record registers on the last branch record stack. This part of the stack
+  contains pointers to the destination instruction. See also: -  Last Branch
+  Record Stack TOS at 1C9H -  Section 17.10.
+
+  @param  ECX  MSR_SKYLAKE_LASTBRANCH_n_TO_IP
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_16_TO_IP);
+  AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_16_TO_IP, Msr);
+  @endcode
+  @note MSR_SKYLAKE_LASTBRANCH_16_TO_IP is defined as MSR_LASTBRANCH_16_TO_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_17_TO_IP is defined as MSR_LASTBRANCH_17_TO_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_18_TO_IP is defined as MSR_LASTBRANCH_18_TO_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_19_TO_IP is defined as MSR_LASTBRANCH_19_TO_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_20_TO_IP is defined as MSR_LASTBRANCH_20_TO_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_21_TO_IP is defined as MSR_LASTBRANCH_21_TO_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_22_TO_IP is defined as MSR_LASTBRANCH_22_TO_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_23_TO_IP is defined as MSR_LASTBRANCH_23_TO_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_24_TO_IP is defined as MSR_LASTBRANCH_24_TO_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_25_TO_IP is defined as MSR_LASTBRANCH_25_TO_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_26_TO_IP is defined as MSR_LASTBRANCH_26_TO_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_27_TO_IP is defined as MSR_LASTBRANCH_27_TO_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_28_TO_IP is defined as MSR_LASTBRANCH_28_TO_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_29_TO_IP is defined as MSR_LASTBRANCH_29_TO_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_30_TO_IP is defined as MSR_LASTBRANCH_30_TO_IP in SDM.
+        MSR_SKYLAKE_LASTBRANCH_31_TO_IP is defined as MSR_LASTBRANCH_31_TO_IP in SDM.
+  @{
+**/
+#define MSR_SKYLAKE_LASTBRANCH_16_TO_IP          0x000006D0
+#define MSR_SKYLAKE_LASTBRANCH_17_TO_IP          0x000006D1
+#define MSR_SKYLAKE_LASTBRANCH_18_TO_IP          0x000006D2
+#define MSR_SKYLAKE_LASTBRANCH_19_TO_IP          0x000006D3
+#define MSR_SKYLAKE_LASTBRANCH_20_TO_IP          0x000006D4
+#define MSR_SKYLAKE_LASTBRANCH_21_TO_IP          0x000006D5
+#define MSR_SKYLAKE_LASTBRANCH_22_TO_IP          0x000006D6
+#define MSR_SKYLAKE_LASTBRANCH_23_TO_IP          0x000006D7
+#define MSR_SKYLAKE_LASTBRANCH_24_TO_IP          0x000006D8
+#define MSR_SKYLAKE_LASTBRANCH_25_TO_IP          0x000006D9
+#define MSR_SKYLAKE_LASTBRANCH_26_TO_IP          0x000006DA
+#define MSR_SKYLAKE_LASTBRANCH_27_TO_IP          0x000006DB
+#define MSR_SKYLAKE_LASTBRANCH_28_TO_IP          0x000006DC
+#define MSR_SKYLAKE_LASTBRANCH_29_TO_IP          0x000006DD
+#define MSR_SKYLAKE_LASTBRANCH_30_TO_IP          0x000006DE
+#define MSR_SKYLAKE_LASTBRANCH_31_TO_IP          0x000006DF
+/// @}
+
+
+/**
+  Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet
+  of last branch record registers on the last branch record stack. This part
+  of the stack contains flag, TSX-related and elapsed cycle information. See
+  also: -  Last Branch Record Stack TOS at 1C9H -  Section 17.7.1, "LBR
+  Stack.".
+
+  @param  ECX  MSR_SKYLAKE_LBR_INFO_n
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_LBR_INFO_0);
+  AsmWriteMsr64 (MSR_SKYLAKE_LBR_INFO_0, Msr);
+  @endcode
+  @note MSR_SKYLAKE_LBR_INFO_0  is defined as MSR_LBR_INFO_0  in SDM.
+        MSR_SKYLAKE_LBR_INFO_1  is defined as MSR_LBR_INFO_1  in SDM.
+        MSR_SKYLAKE_LBR_INFO_2  is defined as MSR_LBR_INFO_2  in SDM.
+        MSR_SKYLAKE_LBR_INFO_3  is defined as MSR_LBR_INFO_3  in SDM.
+        MSR_SKYLAKE_LBR_INFO_4  is defined as MSR_LBR_INFO_4  in SDM.
+        MSR_SKYLAKE_LBR_INFO_5  is defined as MSR_LBR_INFO_5  in SDM.
+        MSR_SKYLAKE_LBR_INFO_6  is defined as MSR_LBR_INFO_6  in SDM.
+        MSR_SKYLAKE_LBR_INFO_7  is defined as MSR_LBR_INFO_7  in SDM.
+        MSR_SKYLAKE_LBR_INFO_8  is defined as MSR_LBR_INFO_8  in SDM.
+        MSR_SKYLAKE_LBR_INFO_9  is defined as MSR_LBR_INFO_9  in SDM.
+        MSR_SKYLAKE_LBR_INFO_10 is defined as MSR_LBR_INFO_10 in SDM.
+        MSR_SKYLAKE_LBR_INFO_11 is defined as MSR_LBR_INFO_11 in SDM.
+        MSR_SKYLAKE_LBR_INFO_12 is defined as MSR_LBR_INFO_12 in SDM.
+        MSR_SKYLAKE_LBR_INFO_13 is defined as MSR_LBR_INFO_13 in SDM.
+        MSR_SKYLAKE_LBR_INFO_14 is defined as MSR_LBR_INFO_14 in SDM.
+        MSR_SKYLAKE_LBR_INFO_15 is defined as MSR_LBR_INFO_15 in SDM.
+        MSR_SKYLAKE_LBR_INFO_16 is defined as MSR_LBR_INFO_16 in SDM.
+        MSR_SKYLAKE_LBR_INFO_17 is defined as MSR_LBR_INFO_17 in SDM.
+        MSR_SKYLAKE_LBR_INFO_18 is defined as MSR_LBR_INFO_18 in SDM.
+        MSR_SKYLAKE_LBR_INFO_19 is defined as MSR_LBR_INFO_19 in SDM.
+        MSR_SKYLAKE_LBR_INFO_20 is defined as MSR_LBR_INFO_20 in SDM.
+        MSR_SKYLAKE_LBR_INFO_21 is defined as MSR_LBR_INFO_21 in SDM.
+        MSR_SKYLAKE_LBR_INFO_22 is defined as MSR_LBR_INFO_22 in SDM.
+        MSR_SKYLAKE_LBR_INFO_23 is defined as MSR_LBR_INFO_23 in SDM.
+        MSR_SKYLAKE_LBR_INFO_24 is defined as MSR_LBR_INFO_24 in SDM.
+        MSR_SKYLAKE_LBR_INFO_25 is defined as MSR_LBR_INFO_25 in SDM.
+        MSR_SKYLAKE_LBR_INFO_26 is defined as MSR_LBR_INFO_26 in SDM.
+        MSR_SKYLAKE_LBR_INFO_27 is defined as MSR_LBR_INFO_27 in SDM.
+        MSR_SKYLAKE_LBR_INFO_28 is defined as MSR_LBR_INFO_28 in SDM.
+        MSR_SKYLAKE_LBR_INFO_29 is defined as MSR_LBR_INFO_29 in SDM.
+        MSR_SKYLAKE_LBR_INFO_30 is defined as MSR_LBR_INFO_30 in SDM.
+        MSR_SKYLAKE_LBR_INFO_31 is defined as MSR_LBR_INFO_31 in SDM.
+  @{
+**/
+#define MSR_SKYLAKE_LBR_INFO_0                   0x00000DC0
+#define MSR_SKYLAKE_LBR_INFO_1                   0x00000DC1
+#define MSR_SKYLAKE_LBR_INFO_2                   0x00000DC2
+#define MSR_SKYLAKE_LBR_INFO_3                   0x00000DC3
+#define MSR_SKYLAKE_LBR_INFO_4                   0x00000DC4
+#define MSR_SKYLAKE_LBR_INFO_5                   0x00000DC5
+#define MSR_SKYLAKE_LBR_INFO_6                   0x00000DC6
+#define MSR_SKYLAKE_LBR_INFO_7                   0x00000DC7
+#define MSR_SKYLAKE_LBR_INFO_8                   0x00000DC8
+#define MSR_SKYLAKE_LBR_INFO_9                   0x00000DC9
+#define MSR_SKYLAKE_LBR_INFO_10                  0x00000DCA
+#define MSR_SKYLAKE_LBR_INFO_11                  0x00000DCB
+#define MSR_SKYLAKE_LBR_INFO_12                  0x00000DCC
+#define MSR_SKYLAKE_LBR_INFO_13                  0x00000DCD
+#define MSR_SKYLAKE_LBR_INFO_14                  0x00000DCE
+#define MSR_SKYLAKE_LBR_INFO_15                  0x00000DCF
+#define MSR_SKYLAKE_LBR_INFO_16                  0x00000DD0
+#define MSR_SKYLAKE_LBR_INFO_17                  0x00000DD1
+#define MSR_SKYLAKE_LBR_INFO_18                  0x00000DD2
+#define MSR_SKYLAKE_LBR_INFO_19                  0x00000DD3
+#define MSR_SKYLAKE_LBR_INFO_20                  0x00000DD4
+#define MSR_SKYLAKE_LBR_INFO_21                  0x00000DD5
+#define MSR_SKYLAKE_LBR_INFO_22                  0x00000DD6
+#define MSR_SKYLAKE_LBR_INFO_23                  0x00000DD7
+#define MSR_SKYLAKE_LBR_INFO_24                  0x00000DD8
+#define MSR_SKYLAKE_LBR_INFO_25                  0x00000DD9
+#define MSR_SKYLAKE_LBR_INFO_26                  0x00000DDA
+#define MSR_SKYLAKE_LBR_INFO_27                  0x00000DDB
+#define MSR_SKYLAKE_LBR_INFO_28                  0x00000DDC
+#define MSR_SKYLAKE_LBR_INFO_29                  0x00000DDD
+#define MSR_SKYLAKE_LBR_INFO_30                  0x00000DDE
+#define MSR_SKYLAKE_LBR_INFO_31                  0x00000DDF
+/// @}
+
+
+/**
+  Package. Uncore fixed counter control (R/W).
+
+  @param  ECX  MSR_SKYLAKE_UNC_PERF_FIXED_CTRL (0x00000394)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTRL);
+  AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTRL, Msr.Uint64);
+  @endcode
+  @note MSR_SKYLAKE_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.
+**/
+#define MSR_SKYLAKE_UNC_PERF_FIXED_CTRL          0x00000394
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_FIXED_CTRL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:20;
+    ///
+    /// [Bit 20] Enable overflow propagation.
+    ///
+    UINT32  EnableOverflow:1;
+    UINT32  Reserved2:1;
+    ///
+    /// [Bit 22] Enable counting.
+    ///
+    UINT32  EnableCounting:1;
+    UINT32  Reserved3:9;
+    UINT32  Reserved4:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER;
+
+
+/**
+  Package. Uncore fixed counter.
+
+  @param  ECX  MSR_SKYLAKE_UNC_PERF_FIXED_CTR (0x00000395)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTR);
+  AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTR, Msr.Uint64);
+  @endcode
+  @note MSR_SKYLAKE_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.
+**/
+#define MSR_SKYLAKE_UNC_PERF_FIXED_CTR           0x00000395
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_FIXED_CTR
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 31:0] Current count.
+    ///
+    UINT32  CurrentCount:32;
+    ///
+    /// [Bits 43:32] Current count.
+    ///
+    UINT32  CurrentCountHi:12;
+    UINT32  Reserved:20;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER;
+
+
+/**
+  Package. Uncore C-Box configuration information (R/O).
+
+  @param  ECX  MSR_SKYLAKE_UNC_CBO_CONFIG (0x00000396)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_CONFIG);
+  @endcode
+  @note MSR_SKYLAKE_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.
+**/
+#define MSR_SKYLAKE_UNC_CBO_CONFIG               0x00000396
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_UNC_CBO_CONFIG
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 3:0] Specifies the number of C-Box units with programmable
+    /// counters (including processor cores and processor graphics),.
+    ///
+    UINT32  CBox:4;
+    UINT32  Reserved1:28;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER;
+
+
+/**
+  Package. Uncore Arb unit, performance counter 0.
+
+  @param  ECX  MSR_SKYLAKE_UNC_ARB_PERFCTR0 (0x000003B0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR0);
+  AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR0, Msr);
+  @endcode
+  @note MSR_SKYLAKE_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.
+**/
+#define MSR_SKYLAKE_UNC_ARB_PERFCTR0             0x000003B0
+
+
+/**
+  Package. Uncore Arb unit, performance counter 1.
+
+  @param  ECX  MSR_SKYLAKE_UNC_ARB_PERFCTR1 (0x000003B1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR1);
+  AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR1, Msr);
+  @endcode
+  @note MSR_SKYLAKE_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.
+**/
+#define MSR_SKYLAKE_UNC_ARB_PERFCTR1             0x000003B1
+
+
+/**
+  Package. Uncore Arb unit, counter 0 event select MSR.
+
+  @param  ECX  MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 (0x000003B2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0);
+  AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0, Msr);
+  @endcode
+  @note MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.
+**/
+#define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0          0x000003B2
+
+
+/**
+  Package. Uncore Arb unit, counter 1 event select MSR.
+
+  @param  ECX  MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 (0x000003B3)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1);
+  AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1, Msr);
+  @endcode
+  @note MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 is defined as MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 in SDM.
+**/
+#define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1          0x000003B3
+
+
+/**
+  Package. Uncore C-Box 0, counter 0 event select MSR.
+
+  @param  ECX  MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 (0x00000700)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0);
+  AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0, Msr);
+  @endcode
+  @note MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.
+**/
+#define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0        0x00000700
+
+
+/**
+  Package. Uncore C-Box 0, counter 1 event select MSR.
+
+  @param  ECX  MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 (0x00000701)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1);
+  AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1, Msr);
+  @endcode
+  @note MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.
+**/
+#define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1        0x00000701
+
+
+/**
+  Package. Uncore C-Box 0, performance counter 0.
+
+  @param  ECX  MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 (0x00000706)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR0);
+  AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR0, Msr);
+  @endcode
+  @note MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.
+**/
+#define MSR_SKYLAKE_UNC_CBO_0_PERFCTR0           0x00000706
+
+
+/**
+  Package. Uncore C-Box 0, performance counter 1.
+
+  @param  ECX  MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 (0x00000707)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR1);
+  AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR1, Msr);
+  @endcode
+  @note MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.
+**/
+#define MSR_SKYLAKE_UNC_CBO_0_PERFCTR1           0x00000707
+
+
+/**
+  Package. Uncore C-Box 1, counter 0 event select MSR.
+
+  @param  ECX  MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 (0x00000710)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0);
+  AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0, Msr);
+  @endcode
+  @note MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.
+**/
+#define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0        0x00000710
+
+
+/**
+  Package. Uncore C-Box 1, counter 1 event select MSR.
+
+  @param  ECX  MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 (0x00000711)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1);
+  AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1, Msr);
+  @endcode
+  @note MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.
+**/
+#define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1        0x00000711
+
+
+/**
+  Package. Uncore C-Box 1, performance counter 0.
+
+  @param  ECX  MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 (0x00000716)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR0);
+  AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR0, Msr);
+  @endcode
+  @note MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.
+**/
+#define MSR_SKYLAKE_UNC_CBO_1_PERFCTR0           0x00000716
+
+
+/**
+  Package. Uncore C-Box 1, performance counter 1.
+
+  @param  ECX  MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 (0x00000717)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR1);
+  AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR1, Msr);
+  @endcode
+  @note MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.
+**/
+#define MSR_SKYLAKE_UNC_CBO_1_PERFCTR1           0x00000717
+
+
+/**
+  Package. Uncore C-Box 2, counter 0 event select MSR.
+
+  @param  ECX  MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 (0x00000720)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0);
+  AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0, Msr);
+  @endcode
+  @note MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.
+**/
+#define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0        0x00000720
+
+
+/**
+  Package. Uncore C-Box 2, counter 1 event select MSR.
+
+  @param  ECX  MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 (0x00000721)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1);
+  AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1, Msr);
+  @endcode
+  @note MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.
+**/
+#define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1        0x00000721
+
+
+/**
+  Package. Uncore C-Box 2, performance counter 0.
+
+  @param  ECX  MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 (0x00000726)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR0);
+  AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR0, Msr);
+  @endcode
+  @note MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.
+**/
+#define MSR_SKYLAKE_UNC_CBO_2_PERFCTR0           0x00000726
+
+
+/**
+  Package. Uncore C-Box 2, performance counter 1.
+
+  @param  ECX  MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 (0x00000727)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR1);
+  AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR1, Msr);
+  @endcode
+  @note MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.
+**/
+#define MSR_SKYLAKE_UNC_CBO_2_PERFCTR1           0x00000727
+
+
+/**
+  Package. Uncore C-Box 3, counter 0 event select MSR.
+
+  @param  ECX  MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 (0x00000730)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0);
+  AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0, Msr);
+  @endcode
+  @note MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.
+**/
+#define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0        0x00000730
+
+
+/**
+  Package. Uncore C-Box 3, counter 1 event select MSR.
+
+  @param  ECX  MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 (0x00000731)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1);
+  AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1, Msr);
+  @endcode
+  @note MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.
+**/
+#define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1        0x00000731
+
+
+/**
+  Package. Uncore C-Box 3, performance counter 0.
+
+  @param  ECX  MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 (0x00000736)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR0);
+  AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR0, Msr);
+  @endcode
+  @note MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.
+**/
+#define MSR_SKYLAKE_UNC_CBO_3_PERFCTR0           0x00000736
+
+
+/**
+  Package. Uncore C-Box 3, performance counter 1.
+
+  @param  ECX  MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 (0x00000737)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR1);
+  AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR1, Msr);
+  @endcode
+  @note MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.
+**/
+#define MSR_SKYLAKE_UNC_CBO_3_PERFCTR1           0x00000737
+
+
+/**
+  Package. Uncore PMU global control.
+
+  @param  ECX  MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL (0x00000E01)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL);
+  AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL, Msr.Uint64);
+  @endcode
+  @note MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.
+**/
+#define MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL         0x00000E01
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Slice 0 select.
+    ///
+    UINT32  PMI_Sel_Slice0:1;
+    ///
+    /// [Bit 1] Slice 1 select.
+    ///
+    UINT32  PMI_Sel_Slice1:1;
+    ///
+    /// [Bit 2] Slice 2 select.
+    ///
+    UINT32  PMI_Sel_Slice2:1;
+    ///
+    /// [Bit 3] Slice 3 select.
+    ///
+    UINT32  PMI_Sel_Slice3:1;
+    ///
+    /// [Bit 4] Slice 4select.
+    ///
+    UINT32  PMI_Sel_Slice4:1;
+    UINT32  Reserved1:14;
+    UINT32  Reserved2:10;
+    ///
+    /// [Bit 29] Enable all uncore counters.
+    ///
+    UINT32  EN:1;
+    ///
+    /// [Bit 30] Enable wake on PMI.
+    ///
+    UINT32  WakePMI:1;
+    ///
+    /// [Bit 31] Enable Freezing counter when overflow.
+    ///
+    UINT32  FREEZE:1;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER;
+
+
+/**
+  Package. Uncore PMU main status.
+
+  @param  ECX  MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS (0x00000E02)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS);
+  AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS, Msr.Uint64);
+  @endcode
+  @note MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM.
+**/
+#define MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS       0x00000E02
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Fixed counter overflowed.
+    ///
+    UINT32  Fixed:1;
+    ///
+    /// [Bit 1] An ARB counter overflowed.
+    ///
+    UINT32  ARB:1;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 3] A CBox counter overflowed (on any slice).
+    ///
+    UINT32  CBox:1;
+    UINT32  Reserved2:28;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER;
+
+
+/**
+  Package. NPK Address Used by AET Messages (R/W).
+
+  @param  ECX  MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE (0x00000080)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE);
+  AsmWriteMsr64 (MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE   0x00000080
+
+/**
+  MSR information returned for MSR index
+  #MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Lock Bit If set, this MSR cannot be re-written anymore. Lock
+    /// bit has to be set in order for the AET packets to be directed to NPK
+    /// MMIO.
+    ///
+    UINT32  Fix_Me_1:1;
+    UINT32  Reserved:17;
+    ///
+    /// [Bits 31:18] ACPIBAR_BASE_ADDRESS AET target address in NPK MMIO space.
+    ///
+    UINT32  ACPIBAR_BASE_ADDRESS:14;
+    ///
+    /// [Bits 63:32] ACPIBAR_BASE_ADDRESS AET target address in NPK MMIO space.
+    ///
+    UINT32  Fix_Me_2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER;
+
+
+/**
+  Core. Processor Reserved Memory Range Register - Physical Base Control
+  Register (R/W).
+
+  @param  ECX  MSR_SKYLAKE_PRMRR_PHYS_BASE (0x000001F4)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PRMRR_PHYS_BASE);
+  AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_PHYS_BASE, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SKYLAKE_PRMRR_PHYS_BASE              0x000001F4
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_PHYS_BASE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 2:0] MemType PRMRR BASE MemType.
+    ///
+    UINT32  MemTypePRMRRBASEMemType:3;
+    UINT32  Reserved1:9;
+    ///
+    /// [Bits 31:12] Base PRMRR Base Address.
+    ///
+    UINT32  BasePRMRRBaseAddress:20;
+    ///
+    /// [Bits 45:32] Base PRMRR Base Address.
+    ///
+    UINT32  Fix_Me_1:14;
+    UINT32  Reserved2:18;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER;
+
+
+/**
+  Core. Processor Reserved Memory Range Register - Physical Mask Control
+  Register (R/W).
+
+  @param  ECX  MSR_SKYLAKE_PRMRR_PHYS_MASK (0x000001F5)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PRMRR_PHYS_MASK);
+  AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_PHYS_MASK, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SKYLAKE_PRMRR_PHYS_MASK              0x000001F5
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_PHYS_MASK
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:10;
+    ///
+    /// [Bit 10] Lock Lock bit for the PRMRR.
+    ///
+    UINT32  Fix_Me_1:1;
+    ///
+    /// [Bit 11] VLD Enable bit for the PRMRR.
+    ///
+    UINT32  VLD:1;
+    ///
+    /// [Bits 31:12] Mask PRMRR MASK bits.
+    ///
+    UINT32  Fix_Me_2:20;
+    ///
+    /// [Bits 45:32] Mask PRMRR MASK bits.
+    ///
+    UINT32  Fix_Me_3:14;
+    UINT32  Reserved2:18;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER;
+
+
+/**
+  Core. Valid PRMRR Configurations (R/W).
+
+  @param  ECX  MSR_SKYLAKE_PRMRR_VALID_CONFIG (0x000001FB)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PRMRR_VALID_CONFIG);
+  AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_VALID_CONFIG, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SKYLAKE_PRMRR_VALID_CONFIG           0x000001FB
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_VALID_CONFIG
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] 1M supported MEE size.
+    ///
+    UINT32  Fix_Me_1:1;
+    UINT32  Reserved1:4;
+    ///
+    /// [Bit 5] 32M supported MEE size.
+    ///
+    UINT32  Fix_Me_2:1;
+    ///
+    /// [Bit 6] 64M supported MEE size.
+    ///
+    UINT32  Fix_Me_3:1;
+    ///
+    /// [Bit 7] 128M supported MEE size.
+    ///
+    UINT32  Fix_Me_4:1;
+    UINT32  Reserved2:24;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER;
+
+
+/**
+  Package. (R/W) The PRMRR range is used to protect Xucode memory from
+  unauthorized reads and writes. Any IO access to this range is aborted. This
+  register controls the location of the PRMRR range by indicating its starting
+  address. It functions in tandem with the PRMRR mask register.
+
+  @param  ECX  MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE (0x000002F4)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE);
+  AsmWriteMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE       0x000002F4
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:12;
+    ///
+    /// [Bits 31:12] Range Base This field corresponds to bits 38:12 of the
+    /// base address memory range which is allocated to PRMRR memory.
+    ///
+    UINT32  Fix_Me_1:20;
+    ///
+    /// [Bits 38:32] Range Base This field corresponds to bits 38:12 of the
+    /// base address memory range which is allocated to PRMRR memory.
+    ///
+    UINT32  Fix_Me_2:7;
+    UINT32  Reserved2:25;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER;
+
+
+/**
+  Package. (R/W) This register controls the size of the PRMRR range by
+  indicating which address bits must match the PRMRR base register value.
+
+  @param  ECX  MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK (0x000002F5)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK);
+  AsmWriteMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK       0x000002F5
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:10;
+    ///
+    /// [Bit 10] Lock Setting this bit locks all writeable settings in this
+    /// register, including itself.
+    ///
+    UINT32  Fix_Me_1:1;
+    ///
+    /// [Bit 11] Range_En Indicates whether the PRMRR range is enabled and
+    /// valid.
+    ///
+    UINT32  Fix_Me_2:1;
+    UINT32  Reserved2:20;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER;
+
+/**
+  Package. Ring Ratio Limit (R/W) This register provides Min/Max Ratio Limits
+  for the LLC and Ring.
+
+  @param  ECX  MSR_SKYLAKE_RING_RATIO_LIMIT (0x00000620)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RING_RATIO_LIMIT);
+  AsmWriteMsr64 (MSR_SKYLAKE_RING_RATIO_LIMIT, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SKYLAKE_RING_RATIO_LIMIT             0x00000620
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_RING_RATIO_LIMIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 6:0] MAX_Ratio This field is used to limit the max ratio of the
+    /// LLC/Ring.
+    ///
+    UINT32  Fix_Me_1:7;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bits 14:8] MIN_Ratio Writing to this field controls the minimum
+    /// possible ratio of the LLC/Ring.
+    ///
+    UINT32  Fix_Me_2:7;
+    UINT32  Reserved2:17;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER;
+
+
+/**
+  Branch Monitoring Global Control (R/W).
+
+  @param  ECX  MSR_SKYLAKE_BR_DETECT_CTRL (0x00000350)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_BR_DETECT_CTRL);
+  AsmWriteMsr64 (MSR_SKYLAKE_BR_DETECT_CTRL, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SKYLAKE_BR_DETECT_CTRL               0x00000350
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_BR_DETECT_CTRL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] EnMonitoring Global enable for branch monitoring.
+    ///
+    UINT32  EnMonitoring:1;
+    ///
+    /// [Bit 1] EnExcept Enable branch monitoring event signaling on threshold
+    /// trip. The branch monitoring event handler is signaled via the existing
+    /// PMI signaling mechanism as programmed from the corresponding local
+    /// APIC LVT entry.
+    ///
+    UINT32  EnExcept:1;
+    ///
+    /// [Bit 2] EnLBRFrz Enable LBR freeze on threshold trip. This will cause
+    /// the LBR frozen bit 58 to be set in IA32_PERF_GLOBAL_STATUS when a
+    /// triggering condition occurs and this bit is enabled.
+    ///
+    UINT32  EnLBRFrz:1;
+    ///
+    /// [Bit 3] DisableInGuest When set to '1', branch monitoring, event
+    /// triggering and LBR freeze actions are disabled when operating at VMX
+    /// non-root operation.
+    ///
+    UINT32  DisableInGuest:1;
+    UINT32  Reserved1:4;
+    ///
+    /// [Bits 17:8] WindowSize Window size defined by WindowCntSel. Values 0 -
+    /// 1023 are supported. Once the Window counter reaches the WindowSize
+    /// count both the Window Counter and all Branch Monitoring Counters are
+    /// cleared.
+    ///
+    UINT32  WindowSize:10;
+    UINT32  Reserved2:6;
+    ///
+    /// [Bits 25:24] WindowCntSel Window event count select: '00 =
+    /// Instructions retired. '01 = Branch instructions retired '10 = Return
+    /// instructions retired. '11 = Indirect branch instructions retired.
+    ///
+    UINT32  WindowCntSel:2;
+    ///
+    /// [Bit 26] CntAndMode When set to '1', the overall branch monitoring
+    /// event triggering condition is true only if all enabled counters'
+    /// threshold conditions are true. When '0', the threshold tripping
+    /// condition is true if any enabled counters' threshold is true.
+    ///
+    UINT32  CntAndMode:1;
+    UINT32  Reserved3:5;
+    UINT32  Reserved4:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER;
+
+/**
+  Branch Monitoring Global Status (R/W).
+
+  @param  ECX  MSR_SKYLAKE_BR_DETECT_STATUS (0x00000351)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_BR_DETECT_STATUS);
+  AsmWriteMsr64 (MSR_SKYLAKE_BR_DETECT_STATUS, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SKYLAKE_BR_DETECT_STATUS             0x00000351
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_BR_DETECT_STATUS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Branch Monitoring Event Signaled When set to '1', Branch
+    /// Monitoring event signaling is blocked until this bit is cleared by
+    /// software.
+    ///
+    UINT32  BranchMonitoringEventSignaled:1;
+    ///
+    /// [Bit 1] LBRsValid This status bit is set to '1' if the LBR state is
+    /// considered valid for sampling by branch monitoring software.
+    ///
+    UINT32  LBRsValid:1;
+    UINT32  Reserved1:6;
+    ///
+    /// [Bit 8] CntrHit0 Branch monitoring counter #0 threshold hit. This
+    /// status bit is sticky and once set requires clearing by software.
+    /// Counter operation continues independent of the state of the bit.
+    ///
+    UINT32  CntrHit0:1;
+    ///
+    /// [Bit 9] CntrHit1 Branch monitoring counter #1 threshold hit. This
+    /// status bit is sticky and once set requires clearing by software.
+    /// Counter operation continues independent of the state of the bit.
+    ///
+    UINT32  CntrHit1:1;
+    UINT32  Reserved2:6;
+    ///
+    /// [Bits 25:16] CountWindow The current value of the window counter. The
+    /// count value is frozen on a valid branch monitoring triggering
+    /// condition. This is a 10-bit unsigned value.
+    ///
+    UINT32  CountWindow:10;
+    UINT32  Reserved3:6;
+    ///
+    /// [Bits 39:32] Count0 The current value of counter 0 updated after each
+    /// occurrence of the event being counted. The count value is frozen on a
+    /// valid branch monitoring triggering condition (in which case CntrHit0
+    /// will also be set). This is an 8-bit signed value (2's complement).
+    /// Heuristic events which only increment will saturate and freeze at
+    /// maximum value 0xFF (256). RET-CALL event counter saturate at maximum
+    /// value 0x7F (+127) and minimum value 0x80 (-128).
+    ///
+    UINT32  Count0:8;
+    ///
+    /// [Bits 47:40] Count1 The current value of counter 1 updated after each
+    /// occurrence of the event being counted. The count value is frozen on a
+    /// valid branch monitoring triggering condition (in which case CntrHit1
+    /// will also be set). This is an 8-bit signed value (2's complement).
+    /// Heuristic events which only increment will saturate and freeze at
+    /// maximum value 0xFF (256). RET-CALL event counter saturate at maximum
+    /// value 0x7F (+127) and minimum value 0x80 (-128).
+    ///
+    UINT32  Count1:8;
+    UINT32  Reserved4:16;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER;
+
+
+/**
+  Package. Package C3 Residency Counter (R/O). Note: C-state values are
+  processor specific C-state code names, unrelated to MWAIT extension C-state
+  parameters or ACPI C-states.
+
+  @param  ECX  MSR_SKYLAKE_PKG_C3_RESIDENCY (0x000003F8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_C3_RESIDENCY);
+  @endcode
+**/
+#define MSR_SKYLAKE_PKG_C3_RESIDENCY             0x000003F8
+
+
+/**
+  Core. Core C1 Residency Counter (R/O). Value since last reset for the Core
+  C1 residency. Counter rate is the Max Non-Turbo frequency (same as TSC).
+  This counter counts in case both of the core's threads are in an idle state
+  and at least one of the core's thread residency is in a C1 state or in one
+  of its sub states. The counter is updated only after a core C state exit.
+  Note: Always reads 0 if core C1 is unsupported. A value of zero indicates
+  that this processor does not support core C1 or never entered core C1 level
+  state.
+
+  @param  ECX  MSR_SKYLAKE_CORE_C1_RESIDENCY (0x00000660)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_C1_RESIDENCY);
+  @endcode
+**/
+#define MSR_SKYLAKE_CORE_C1_RESIDENCY            0x00000660
+
+
+/**
+  Core. Core C3 Residency Counter (R/O). Will always return 0.
+
+  @param  ECX  MSR_SKYLAKE_CORE_C3_RESIDENCY (0x00000662)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_C3_RESIDENCY);
+  @endcode
+**/
+#define MSR_SKYLAKE_CORE_C3_RESIDENCY            0x00000662
+
+
+/**
+  Package. Protected Processor Inventory Number Enable Control (R/W).
+
+  @param  ECX  MSR_SKYLAKE_PPIN_CTL (0x0000004E)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_PPIN_CTL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_PPIN_CTL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_PPIN_CTL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PPIN_CTL);
+  AsmWriteMsr64 (MSR_SKYLAKE_PPIN_CTL, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SKYLAKE_PPIN_CTL                     0x0000004E
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_PPIN_CTL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] LockOut (R/WO) See Table 2-25.
+    ///
+    UINT32  LockOut:1;
+    ///
+    /// [Bit 1] Enable_PPIN (R/W) See Table 2-25.
+    ///
+    UINT32  Enable_PPIN:1;
+    UINT32  Reserved1:30;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_PPIN_CTL_REGISTER;
+
+
+/**
+  Package. Protected Processor Inventory Number (R/O). Protected Processor
+  Inventory Number (R/O) See Table 2-25.
+
+  @param  ECX  MSR_SKYLAKE_PPIN (0x0000004F)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_PPIN);
+  @endcode
+**/
+#define MSR_SKYLAKE_PPIN                         0x0000004F
+
+
+/**
+  Package. Platform Information Contains power management and other model
+  specific features enumeration. See http://biosbits.org.
+
+  @param  ECX  MSR_SKYLAKE_PLATFORM_INFO (0x000000CE)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_PLATFORM_INFO_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_PLATFORM_INFO_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_PLATFORM_INFO_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_INFO);
+  AsmWriteMsr64 (MSR_SKYLAKE_PLATFORM_INFO, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SKYLAKE_PLATFORM_INFO                0x000000CE
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_INFO
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:8;
+    ///
+    /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 2-25.
+    ///
+    UINT32  MaximumNon_TurboRatio:8;
+    UINT32  Reserved2:7;
+    ///
+    /// [Bit 23] Package. PPIN_CAP (R/O) See Table 2-25.
+    ///
+    UINT32  PPIN_CAP:1;
+    UINT32  Reserved3:4;
+    ///
+    /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See
+    /// Table 2-25.
+    ///
+    UINT32  ProgrammableRatioLimit:1;
+    ///
+    /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See
+    /// Table 2-25.
+    ///
+    UINT32  ProgrammableTDPLimit:1;
+    ///
+    /// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 2-25.
+    ///
+    UINT32  ProgrammableTJOFFSET:1;
+    UINT32  Reserved4:1;
+    UINT32  Reserved5:8;
+    ///
+    /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 2-25.
+    ///
+    UINT32  MaximumEfficiencyRatio:8;
+    UINT32  Reserved6:16;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_PLATFORM_INFO_REGISTER;
+
+
+/**
+  Core. C-State Configuration Control (R/W) Note: C-state values are processor
+  specific C-state code names, unrelated to MWAIT extension C-state parameters
+  or ACPI C-states. `See http://biosbits.org. <http://biosbits.org/>`__.
+
+  @param  ECX  MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL (0x000000E2)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL);
+  AsmWriteMsr64 (MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL       0x000000E2
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest
+    /// processor-specific C-state code name (consuming the least power) for
+    /// the package. The default is set as factory-configured package Cstate
+    /// limit. The following C-state code name encodings are supported: 000b:
+    /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention)
+    /// 011b: C6 (retention) 111b: No Package C state limits. All C states
+    /// supported by the processor are available.
+    ///
+    UINT32  C_StateLimit:3;
+    UINT32  Reserved1:7;
+    ///
+    /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
+    ///
+    UINT32  MWAITRedirectionEnable:1;
+    UINT32  Reserved2:4;
+    ///
+    /// [Bit 15] CFG Lock (R/WO).
+    ///
+    UINT32  CFGLock:1;
+    ///
+    /// [Bit 16] Automatic C-State Conversion Enable (R/W) If 1, the processor
+    /// will convert HALT or MWAT(C1) to MWAIT(C6).
+    ///
+    UINT32  AutomaticC_StateConversionEnable:1;
+    UINT32  Reserved3:8;
+    ///
+    /// [Bit 25] C3 State Auto Demotion Enable (R/W).
+    ///
+    UINT32  C3StateAutoDemotionEnable:1;
+    ///
+    /// [Bit 26] C1 State Auto Demotion Enable (R/W).
+    ///
+    UINT32  C1StateAutoDemotionEnable:1;
+    ///
+    /// [Bit 27] Enable C3 Undemotion (R/W).
+    ///
+    UINT32  EnableC3Undemotion:1;
+    ///
+    /// [Bit 28] Enable C1 Undemotion (R/W).
+    ///
+    UINT32  EnableC1Undemotion:1;
+    ///
+    /// [Bit 29] Package C State Demotion Enable (R/W).
+    ///
+    UINT32  CStateDemotionEnable:1;
+    ///
+    /// [Bit 30] Package C State UnDemotion Enable (R/W).
+    ///
+    UINT32  CStateUnDemotionEnable:1;
+    UINT32  Reserved4:1;
+    UINT32  Reserved5:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER;
+
+
+/**
+  Thread. Global Machine Check Capability (R/O).
+
+  @param  ECX  MSR_SKYLAKE_IA32_MCG_CAP (0x00000179)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_IA32_MCG_CAP_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_IA32_MCG_CAP_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_IA32_MCG_CAP_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_MCG_CAP);
+  @endcode
+**/
+#define MSR_SKYLAKE_IA32_MCG_CAP                 0x00000179
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_IA32_MCG_CAP
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Count.
+    ///
+    UINT32  Count:8;
+    ///
+    /// [Bit 8] MCG_CTL_P.
+    ///
+    UINT32  MCG_CTL_P:1;
+    ///
+    /// [Bit 9] MCG_EXT_P.
+    ///
+    UINT32  MCG_EXT_P:1;
+    ///
+    /// [Bit 10] MCP_CMCI_P.
+    ///
+    UINT32  MCP_CMCI_P:1;
+    ///
+    /// [Bit 11] MCG_TES_P.
+    ///
+    UINT32  MCG_TES_P:1;
+    UINT32  Reserved1:4;
+    ///
+    /// [Bits 23:16] MCG_EXT_CNT.
+    ///
+    UINT32  MCG_EXT_CNT:8;
+    ///
+    /// [Bit 24] MCG_SER_P.
+    ///
+    UINT32  MCG_SER_P:1;
+    ///
+    /// [Bit 25] MCG_EM_P.
+    ///
+    UINT32  MCG_EM_P:1;
+    ///
+    /// [Bit 26] MCG_ELOG_P.
+    ///
+    UINT32  MCG_ELOG_P:1;
+    UINT32  Reserved2:5;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_IA32_MCG_CAP_REGISTER;
+
+
+/**
+  THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability
+  Enhancement. Accessible only while in SMM.
+
+  @param  ECX  MSR_SKYLAKE_SMM_MCA_CAP (0x0000017D)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_SMM_MCA_CAP_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_SMM_MCA_CAP_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_SMM_MCA_CAP_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_SMM_MCA_CAP);
+  AsmWriteMsr64 (MSR_SKYLAKE_SMM_MCA_CAP, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SKYLAKE_SMM_MCA_CAP                  0x0000017D
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_SMM_MCA_CAP
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:32;
+    UINT32  Reserved2:26;
+    ///
+    /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
+    /// SMM code access restriction is supported and a host-space interface is
+    /// available to SMM handler.
+    ///
+    UINT32  SMM_Code_Access_Chk:1;
+    ///
+    /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the
+    /// SMM long flow indicator is supported and a host-space interface is
+    /// available to SMM handler.
+    ///
+    UINT32  Long_Flow_Indication:1;
+    UINT32  Reserved3:4;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_SMM_MCA_CAP_REGISTER;
+
+
+/**
+  Package. Temperature Target.
+
+  @param  ECX  MSR_SKYLAKE_TEMPERATURE_TARGET (0x000001A2)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TEMPERATURE_TARGET);
+  AsmWriteMsr64 (MSR_SKYLAKE_TEMPERATURE_TARGET, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SKYLAKE_TEMPERATURE_TARGET           0x000001A2
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_TEMPERATURE_TARGET
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:16;
+    ///
+    /// [Bits 23:16] Temperature Target (RO) See Table 2-25.
+    ///
+    UINT32  TemperatureTarget:8;
+    ///
+    /// [Bits 27:24] TCC Activation Offset (R/W) See Table 2-25.
+    ///
+    UINT32  TCCActivationOffset:4;
+    UINT32  Reserved2:4;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER;
+
+/**
+  Package. This register defines the active core ranges for each frequency
+  point. NUMCORE[0:7] must be populated in ascending order. NUMCORE[i+1] must
+  be greater than NUMCORE[i]. Entries with NUMCORE[i] == 0 will be ignored.
+  The last valid entry must have NUMCORE >= the number of cores in the SKU. If
+  any of the rules above are broken, the configuration is silently rejected.
+
+  @param  ECX  MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES (0x000001AE)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES);
+  AsmWriteMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES      0x000001AE
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] NUMCORE_0 Defines the active core ranges for each frequency
+    /// point.
+    ///
+    UINT32  NUMCORE_0:8;
+    ///
+    /// [Bits 15:8] NUMCORE_1 Defines the active core ranges for each
+    /// frequency point.
+    ///
+    UINT32  NUMCORE_1:8;
+    ///
+    /// [Bits 23:16] NUMCORE_2 Defines the active core ranges for each
+    /// frequency point.
+    ///
+    UINT32  NUMCORE_2:8;
+    ///
+    /// [Bits 31:24] NUMCORE_3 Defines the active core ranges for each
+    /// frequency point.
+    ///
+    UINT32  NUMCORE_3:8;
+    ///
+    /// [Bits 39:32] NUMCORE_4 Defines the active core ranges for each
+    /// frequency point.
+    ///
+    UINT32  NUMCORE_4:8;
+    ///
+    /// [Bits 47:40] NUMCORE_5 Defines the active core ranges for each
+    /// frequency point.
+    ///
+    UINT32  NUMCORE_5:8;
+    ///
+    /// [Bits 55:48] NUMCORE_6 Defines the active core ranges for each
+    /// frequency point.
+    ///
+    UINT32  NUMCORE_6:8;
+    ///
+    /// [Bits 63:56] NUMCORE_7 Defines the active core ranges for each
+    /// frequency point.
+    ///
+    UINT32  NUMCORE_7:8;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER;
+
+
+/**
+  Package. Unit Multipliers Used in RAPL Interfaces (R/O).
+
+  @param  ECX  MSR_SKYLAKE_RAPL_POWER_UNIT (0x00000606)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RAPL_POWER_UNIT);
+  @endcode
+**/
+#define MSR_SKYLAKE_RAPL_POWER_UNIT              0x00000606
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_RAPL_POWER_UNIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".
+    ///
+    UINT32  PowerUnits:4;
+    UINT32  Reserved1:4;
+    ///
+    /// [Bits 12:8] Package. Energy Status Units Energy related information
+    /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an
+    /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61
+    /// micro-joules).
+    ///
+    UINT32  EnergyStatusUnits:5;
+    UINT32  Reserved2:3;
+    ///
+    /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL
+    /// Interfaces.".
+    ///
+    UINT32  TimeUnits:4;
+    UINT32  Reserved3:12;
+    UINT32  Reserved4:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER;
+
+
+/**
+  Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL
+  Domain.".
+
+  @param  ECX  MSR_SKYLAKE_DRAM_POWER_LIMIT (0x00000618)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_DRAM_POWER_LIMIT);
+  AsmWriteMsr64 (MSR_SKYLAKE_DRAM_POWER_LIMIT, Msr);
+  @endcode
+**/
+#define MSR_SKYLAKE_DRAM_POWER_LIMIT             0x00000618
+
+
+/**
+  Package. DRAM Energy Status (R/O) Energy consumed by DRAM devices.
+
+  @param  ECX  MSR_SKYLAKE_DRAM_ENERGY_STATUS (0x00000619)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_DRAM_ENERGY_STATUS);
+  @endcode
+**/
+#define MSR_SKYLAKE_DRAM_ENERGY_STATUS           0x00000619
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_DRAM_ENERGY_STATUS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration
+    /// to enable DRAM RAPL mode 0 (Direct VR).
+    ///
+    UINT32  Energy:32;
+    UINT32  Reserved:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER;
+
+
+/**
+  Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
+  RAPL Domain.".
+
+  @param  ECX  MSR_SKYLAKE_DRAM_PERF_STATUS (0x0000061B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_DRAM_PERF_STATUS);
+  @endcode
+**/
+#define MSR_SKYLAKE_DRAM_PERF_STATUS             0x0000061B
+
+
+/**
+  Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
+
+  @param  ECX  MSR_SKYLAKE_DRAM_POWER_INFO (0x0000061C)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_DRAM_POWER_INFO);
+  AsmWriteMsr64 (MSR_SKYLAKE_DRAM_POWER_INFO, Msr);
+  @endcode
+**/
+#define MSR_SKYLAKE_DRAM_POWER_INFO              0x0000061C
+
+
+/**
+  Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio
+  fields represent the widest possible range of uncore frequencies. Writing to
+  these fields allows software to control the minimum and the maximum
+  frequency that hardware will select.
+
+  @param  ECX  MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT (0x00000620)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT);
+  AsmWriteMsr64 (MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT        0x00000620
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the
+    /// LLC/Ring.
+    ///
+    UINT32  MAX_RATIO:7;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum
+    /// possible ratio of the LLC/Ring.
+    ///
+    UINT32  MIN_RATIO:7;
+    UINT32  Reserved2:17;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER;
+
+
+/**
+  Package. Reserved (R/O) Reads return 0.
+
+  @param  ECX  MSR_SKYLAKE_PP0_ENERGY_STATUS (0x00000639)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_SKYLAKE_PP0_ENERGY_STATUS);
+  @endcode
+**/
+#define MSR_SKYLAKE_PP0_ENERGY_STATUS            0x00000639
+
+
+/**
+  THREAD. Monitoring Event Select Register (R/W) If CPUID.(EAX=07H,
+  ECX=0):EBX.RDT-M[bit 12] = 1.
+
+  @param  ECX  MSR_SKYLAKE_IA32_QM_EVTSEL (0x00000C8D)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_QM_EVTSEL);
+  AsmWriteMsr64 (MSR_SKYLAKE_IA32_QM_EVTSEL, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SKYLAKE_IA32_QM_EVTSEL               0x00000C8D
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_IA32_QM_EVTSEL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] EventID (RW) Event encoding: 0x00: No monitoring. 0x01: L3
+    /// occupancy monitoring. 0x02: Total memory bandwidth monitoring. 0x03:
+    /// Local memory bandwidth monitoring. All other encoding reserved.
+    ///
+    UINT32  EventID:8;
+    UINT32  Reserved1:24;
+    ///
+    /// [Bits 41:32] RMID (RW).
+    ///
+    UINT32  RMID:10;
+    UINT32  Reserved2:22;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER;
+
+
+/**
+  THREAD. Resource Association Register (R/W).
+
+  @param  ECX  MSR_SKYLAKE_IA32_PQR_ASSOC (0x00000C8F)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PQR_ASSOC);
+  AsmWriteMsr64 (MSR_SKYLAKE_IA32_PQR_ASSOC, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SKYLAKE_IA32_PQR_ASSOC               0x00000C8F
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_IA32_PQR_ASSOC
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 9:0] RMID.
+    ///
+    UINT32  RMID:10;
+    UINT32  Reserved1:22;
+    ///
+    /// [Bits 51:32] COS (R/W).
+    ///
+    UINT32  COS:20;
+    UINT32  Reserved2:12;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER;
+
+
+/**
+  Package. L3 Class Of Service Mask - COS N (R/W) If CPUID.(EAX=10H,
+  ECX=1):EDX.COS_MAX[15:0] >=0.
+
+  @param  ECX  MSR_SKYLAKE_IA32_L3_QOS_MASK_N
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_L3_QOS_MASK_N);
+  AsmWriteMsr64 (MSR_SKYLAKE_IA32_L3_QOS_MASK_N, Msr.Uint64);
+  @endcode
+**/
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_0           0x00000C90
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_1           0x00000C91
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_2           0x00000C92
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_3           0x00000C93
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_4           0x00000C94
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_5           0x00000C95
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_6           0x00000C96
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_7           0x00000C97
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_8           0x00000C98
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_9           0x00000C99
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_10          0x00000C9A
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_11          0x00000C9B
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_12          0x00000C9C
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_13          0x00000C9D
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_14          0x00000C9E
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_15          0x00000C9F
+
+/**
+  MSR information returned for MSR index #MSR_SKYLAKE_IA32_L3_QOS_MASK_N
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 19:0] CBM: Bit vector of available L3 ways for COS N enforcement.
+    ///
+    UINT32  CBM:20;
+    UINT32  Reserved2:12;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER;
+
+
+#endif
diff --git a/MdePkg/Include/Register/Intel/Msr/Xeon5600Msr.h b/MdePkg/Include/Register/Intel/Msr/Xeon5600Msr.h
new file mode 100644
index 000000000000..7f7824a8d05b
--- /dev/null
+++ b/MdePkg/Include/Register/Intel/Msr/Xeon5600Msr.h
@@ -0,0 +1,197 @@
+/** @file
+  MSR Definitions for Intel(R) Xeon(R) Processor Series 5600.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+  May 2018, Volume 4: Model-Specific-Registers (MSR)
+
+**/
+
+#ifndef __XEON_5600_MSR_H__
+#define __XEON_5600_MSR_H__
+
+#include <Register/Intel/ArchitecturalMsr.h>
+
+/**
+  Is Intel(R) Xeon(R) Processor Series 5600?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_XEON_5600_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (                        \
+    DisplayModel == 0x25 || \
+    DisplayModel == 0x2C    \
+    )                       \
+   )
+
+/**
+  Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
+  handler to handle unsuccessful read of this MSR.
+
+  @param  ECX  MSR_XEON_5600_FEATURE_CONFIG (0x0000013C)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_XEON_5600_FEATURE_CONFIG_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_FEATURE_CONFIG);
+  AsmWriteMsr64 (MSR_XEON_5600_FEATURE_CONFIG, Msr.Uint64);
+  @endcode
+  @note MSR_XEON_5600_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
+**/
+#define MSR_XEON_5600_FEATURE_CONFIG             0x0000013C
+
+/**
+  MSR information returned for MSR index #MSR_XEON_5600_FEATURE_CONFIG
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 1:0] AES Configuration (RW-L)  Upon a successful read of this
+    /// MSR, the configuration of AES instruction set availability is as
+    /// follows: 11b: AES instructions are not available until next RESET.
+    /// otherwise, AES instructions are available. Note, AES instruction set
+    /// is not available if read is unsuccessful. If the configuration is not
+    /// 01b, AES instruction can be mis-configured if a privileged agent
+    /// unintentionally writes 11b.
+    ///
+    UINT32  AESConfiguration:2;
+    UINT32  Reserved1:30;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_5600_FEATURE_CONFIG_REGISTER;
+
+
+/**
+  Thread. Offcore Response Event Select Register (R/W).
+
+  @param  ECX  MSR_XEON_5600_OFFCORE_RSP_1 (0x000001A7)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_5600_OFFCORE_RSP_1);
+  AsmWriteMsr64 (MSR_XEON_5600_OFFCORE_RSP_1, Msr);
+  @endcode
+  @note MSR_XEON_5600_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
+**/
+#define MSR_XEON_5600_OFFCORE_RSP_1              0x000001A7
+
+
+/**
+  Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
+  RW if MSR_PLATFORM_INFO.[28] = 1.
+
+  @param  ECX  MSR_XEON_5600_TURBO_RATIO_LIMIT (0x000001AD)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_TURBO_RATIO_LIMIT);
+  @endcode
+  @note MSR_XEON_5600_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
+**/
+#define MSR_XEON_5600_TURBO_RATIO_LIMIT          0x000001AD
+
+/**
+  MSR information returned for MSR index #MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
+    /// limit of 1 core active.
+    ///
+    UINT32  Maximum1C:8;
+    ///
+    /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
+    /// limit of 2 core active.
+    ///
+    UINT32  Maximum2C:8;
+    ///
+    /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
+    /// limit of 3 core active.
+    ///
+    UINT32  Maximum3C:8;
+    ///
+    /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
+    /// limit of 4 core active.
+    ///
+    UINT32  Maximum4C:8;
+    ///
+    /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
+    /// limit of 5 core active.
+    ///
+    UINT32  Maximum5C:8;
+    ///
+    /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
+    /// limit of 6 core active.
+    ///
+    UINT32  Maximum6C:8;
+    UINT32  Reserved:16;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER;
+
+
+/**
+  Package. See Table 2-2.
+
+  @param  ECX  MSR_XEON_5600_IA32_ENERGY_PERF_BIAS (0x000001B0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS);
+  AsmWriteMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS, Msr);
+  @endcode
+  @note MSR_XEON_5600_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.
+**/
+#define MSR_XEON_5600_IA32_ENERGY_PERF_BIAS      0x000001B0
+
+#endif
diff --git a/MdePkg/Include/Register/Intel/Msr/XeonDMsr.h b/MdePkg/Include/Register/Intel/Msr/XeonDMsr.h
new file mode 100644
index 000000000000..e50c520e2e48
--- /dev/null
+++ b/MdePkg/Include/Register/Intel/Msr/XeonDMsr.h
@@ -0,0 +1,1267 @@
+/** @file
+  MSR Definitions for Intel(R) Xeon(R) Processor D product Family.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+  May 2018, Volume 4: Model-Specific-Registers (MSR)
+
+**/
+
+#ifndef __XEON_D_MSR_H__
+#define __XEON_D_MSR_H__
+
+#include <Register/Intel/ArchitecturalMsr.h>
+
+/**
+  Is Intel(R) Xeon(R) Processor D product Family?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_XEON_D_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (                        \
+    DisplayModel == 0x4F || \
+    DisplayModel == 0x56    \
+    )                       \
+   )
+
+/**
+  Package. Protected Processor Inventory Number Enable Control (R/W).
+
+  @param  ECX  MSR_XEON_D_PPIN_CTL (0x0000004E)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_XEON_D_PPIN_CTL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_XEON_D_PPIN_CTL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_XEON_D_PPIN_CTL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PPIN_CTL);
+  AsmWriteMsr64 (MSR_XEON_D_PPIN_CTL, Msr.Uint64);
+  @endcode
+  @note MSR_XEON_D_PPIN_CTL is defined as MSR_PPIN_CTL in SDM.
+**/
+#define MSR_XEON_D_PPIN_CTL                      0x0000004E
+
+/**
+  MSR information returned for MSR index #MSR_XEON_D_PPIN_CTL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] LockOut (R/WO) See Table 2-25.
+    ///
+    UINT32  LockOut:1;
+    ///
+    /// [Bit 1] Enable_PPIN (R/W) See Table 2-25.
+    ///
+    UINT32  Enable_PPIN:1;
+    UINT32  Reserved1:30;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_D_PPIN_CTL_REGISTER;
+
+
+/**
+  Package. Protected Processor Inventory Number (R/O). Protected Processor
+  Inventory Number (R/O) See Table 2-25.
+
+  @param  ECX  MSR_XEON_D_PPIN (0x0000004F)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_D_PPIN);
+  @endcode
+  @note MSR_XEON_D_PPIN is defined as MSR_PPIN in SDM.
+**/
+#define MSR_XEON_D_PPIN                          0x0000004F
+
+
+/**
+  Package. See http://biosbits.org.
+
+  @param  ECX  MSR_XEON_D_PLATFORM_INFO (0x000000CE)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_XEON_D_PLATFORM_INFO_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_XEON_D_PLATFORM_INFO_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_XEON_D_PLATFORM_INFO_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PLATFORM_INFO);
+  AsmWriteMsr64 (MSR_XEON_D_PLATFORM_INFO, Msr.Uint64);
+  @endcode
+  @note MSR_XEON_D_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
+**/
+#define MSR_XEON_D_PLATFORM_INFO                 0x000000CE
+
+/**
+  MSR information returned for MSR index #MSR_XEON_D_PLATFORM_INFO
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:8;
+    ///
+    /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 2-25.
+    ///
+    UINT32  MaximumNonTurboRatio:8;
+    UINT32  Reserved2:7;
+    ///
+    /// [Bit 23] Package. PPIN_CAP (R/O) See Table 2-25.
+    ///
+    UINT32  PPIN_CAP:1;
+    UINT32  Reserved3:4;
+    ///
+    /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See
+    /// Table 2-25.
+    ///
+    UINT32  RatioLimit:1;
+    ///
+    /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See
+    /// Table 2-25.
+    ///
+    UINT32  TDPLimit:1;
+    ///
+    /// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 2-25.
+    ///
+    UINT32  TJOFFSET:1;
+    UINT32  Reserved4:1;
+    UINT32  Reserved5:8;
+    ///
+    /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 2-25.
+    ///
+    UINT32  MaximumEfficiencyRatio:8;
+    UINT32  Reserved6:16;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_D_PLATFORM_INFO_REGISTER;
+
+
+/**
+  Core. C-State Configuration Control (R/W) Note: C-state values are processor
+  specific C-state code names, unrelated to MWAIT extension C-state parameters
+  or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.
+
+  @param  ECX  MSR_XEON_D_PKG_CST_CONFIG_CONTROL (0x000000E2)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PKG_CST_CONFIG_CONTROL);
+  AsmWriteMsr64 (MSR_XEON_D_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
+  @endcode
+  @note MSR_XEON_D_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
+**/
+#define MSR_XEON_D_PKG_CST_CONFIG_CONTROL        0x000000E2
+
+/**
+  MSR information returned for MSR index #MSR_XEON_D_PKG_CST_CONFIG_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest
+    /// processor-specific C-state code name (consuming the least power) for
+    /// the package. The default is set as factory-configured package C-state
+    /// limit. The following C-state code name encodings are supported: 000b:
+    /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention)
+    /// 011b: C6 (retention) 111b: No Package C state limits. All C states
+    /// supported by the processor are available.
+    ///
+    UINT32  Limit:3;
+    UINT32  Reserved1:7;
+    ///
+    /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
+    ///
+    UINT32  IO_MWAIT:1;
+    UINT32  Reserved2:4;
+    ///
+    /// [Bit 15] CFG Lock (R/WO).
+    ///
+    UINT32  CFGLock:1;
+    ///
+    /// [Bit 16] Automatic C-State Conversion Enable (R/W) If 1, the processor
+    /// will convert HALT or MWAT(C1) to MWAIT(C6).
+    ///
+    UINT32  CStateConversion:1;
+    UINT32  Reserved3:8;
+    ///
+    /// [Bit 25] C3 State Auto Demotion Enable (R/W).
+    ///
+    UINT32  C3AutoDemotion:1;
+    ///
+    /// [Bit 26] C1 State Auto Demotion Enable (R/W).
+    ///
+    UINT32  C1AutoDemotion:1;
+    ///
+    /// [Bit 27] Enable C3 Undemotion (R/W).
+    ///
+    UINT32  C3Undemotion:1;
+    ///
+    /// [Bit 28] Enable C1 Undemotion (R/W).
+    ///
+    UINT32  C1Undemotion:1;
+    ///
+    /// [Bit 29] Package C State Demotion Enable (R/W).
+    ///
+    UINT32  CStateDemotion:1;
+    ///
+    /// [Bit 30] Package C State UnDemotion Enable (R/W).
+    ///
+    UINT32  CStateUndemotion:1;
+    UINT32  Reserved4:1;
+    UINT32  Reserved5:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER;
+
+
+/**
+  Thread. Global Machine Check Capability (R/O).
+
+  @param  ECX  MSR_XEON_D_IA32_MCG_CAP (0x00000179)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_XEON_D_IA32_MCG_CAP_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_XEON_D_IA32_MCG_CAP_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_XEON_D_IA32_MCG_CAP_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_MCG_CAP);
+  @endcode
+  @note MSR_XEON_D_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.
+**/
+#define MSR_XEON_D_IA32_MCG_CAP                  0x00000179
+
+/**
+  MSR information returned for MSR index #MSR_XEON_D_IA32_MCG_CAP
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Count.
+    ///
+    UINT32  Count:8;
+    ///
+    /// [Bit 8] MCG_CTL_P.
+    ///
+    UINT32  MCG_CTL_P:1;
+    ///
+    /// [Bit 9] MCG_EXT_P.
+    ///
+    UINT32  MCG_EXT_P:1;
+    ///
+    /// [Bit 10] MCP_CMCI_P.
+    ///
+    UINT32  MCP_CMCI_P:1;
+    ///
+    /// [Bit 11] MCG_TES_P.
+    ///
+    UINT32  MCG_TES_P:1;
+    UINT32  Reserved1:4;
+    ///
+    /// [Bits 23:16] MCG_EXT_CNT.
+    ///
+    UINT32  MCG_EXT_CNT:8;
+    ///
+    /// [Bit 24] MCG_SER_P.
+    ///
+    UINT32  MCG_SER_P:1;
+    ///
+    /// [Bit 25] MCG_EM_P.
+    ///
+    UINT32  MCG_EM_P:1;
+    ///
+    /// [Bit 26] MCG_ELOG_P.
+    ///
+    UINT32  MCG_ELOG_P:1;
+    UINT32  Reserved2:5;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_D_IA32_MCG_CAP_REGISTER;
+
+
+/**
+  THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability
+  Enhancement. Accessible only while in SMM.
+
+  @param  ECX  MSR_XEON_D_SMM_MCA_CAP (0x0000017D)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_XEON_D_SMM_MCA_CAP_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_XEON_D_SMM_MCA_CAP_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_XEON_D_SMM_MCA_CAP_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_SMM_MCA_CAP);
+  AsmWriteMsr64 (MSR_XEON_D_SMM_MCA_CAP, Msr.Uint64);
+  @endcode
+  @note MSR_XEON_D_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.
+**/
+#define MSR_XEON_D_SMM_MCA_CAP                   0x0000017D
+
+/**
+  MSR information returned for MSR index #MSR_XEON_D_SMM_MCA_CAP
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:32;
+    UINT32  Reserved2:26;
+    ///
+    /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
+    /// SMM code access restriction is supported and a host-space interface
+    /// available to SMM handler.
+    ///
+    UINT32  SMM_Code_Access_Chk:1;
+    ///
+    /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the
+    /// SMM long flow indicator is supported and a host-space interface
+    /// available to SMM handler.
+    ///
+    UINT32  Long_Flow_Indication:1;
+    UINT32  Reserved3:4;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_D_SMM_MCA_CAP_REGISTER;
+
+
+/**
+  Package.
+
+  @param  ECX  MSR_XEON_D_TEMPERATURE_TARGET (0x000001A2)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_XEON_D_TEMPERATURE_TARGET_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_XEON_D_TEMPERATURE_TARGET_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_XEON_D_TEMPERATURE_TARGET_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TEMPERATURE_TARGET);
+  AsmWriteMsr64 (MSR_XEON_D_TEMPERATURE_TARGET, Msr.Uint64);
+  @endcode
+  @note MSR_XEON_D_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
+**/
+#define MSR_XEON_D_TEMPERATURE_TARGET            0x000001A2
+
+/**
+  MSR information returned for MSR index #MSR_XEON_D_TEMPERATURE_TARGET
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:16;
+    ///
+    /// [Bits 23:16] Temperature Target (RO) See Table 2-25.
+    ///
+    UINT32  TemperatureTarget:8;
+    ///
+    /// [Bits 27:24] TCC Activation Offset (R/W) See Table 2-25.
+    ///
+    UINT32  TCCActivationOffset:4;
+    UINT32  Reserved2:4;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_D_TEMPERATURE_TARGET_REGISTER;
+
+
+/**
+  Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
+  RW if MSR_PLATFORM_INFO.[28] = 1.
+
+  @param  ECX  MSR_XEON_D_TURBO_RATIO_LIMIT (0x000001AD)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT);
+  @endcode
+  @note MSR_XEON_D_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
+**/
+#define MSR_XEON_D_TURBO_RATIO_LIMIT             0x000001AD
+
+/**
+  MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Package. Maximum Ratio Limit for 1C.
+    ///
+    UINT32  Maximum1C:8;
+    ///
+    /// [Bits 15:8] Package. Maximum Ratio Limit for 2C.
+    ///
+    UINT32  Maximum2C:8;
+    ///
+    /// [Bits 23:16] Package. Maximum Ratio Limit for 3C.
+    ///
+    UINT32  Maximum3C:8;
+    ///
+    /// [Bits 31:24] Package. Maximum Ratio Limit for 4C.
+    ///
+    UINT32  Maximum4C:8;
+    ///
+    /// [Bits 39:32] Package. Maximum Ratio Limit for 5C.
+    ///
+    UINT32  Maximum5C:8;
+    ///
+    /// [Bits 47:40] Package. Maximum Ratio Limit for 6C.
+    ///
+    UINT32  Maximum6C:8;
+    ///
+    /// [Bits 55:48] Package. Maximum Ratio Limit for 7C.
+    ///
+    UINT32  Maximum7C:8;
+    ///
+    /// [Bits 63:56] Package. Maximum Ratio Limit for 8C.
+    ///
+    UINT32  Maximum8C:8;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER;
+
+
+/**
+  Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
+  RW if MSR_PLATFORM_INFO.[28] = 1.
+
+  @param  ECX  MSR_XEON_D_TURBO_RATIO_LIMIT1 (0x000001AE)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT1);
+  @endcode
+  @note MSR_XEON_D_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.
+**/
+#define MSR_XEON_D_TURBO_RATIO_LIMIT1            0x000001AE
+
+/**
+  MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT1
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Package. Maximum Ratio Limit for 9C.
+    ///
+    UINT32  Maximum9C:8;
+    ///
+    /// [Bits 15:8] Package. Maximum Ratio Limit for 10C.
+    ///
+    UINT32  Maximum10C:8;
+    ///
+    /// [Bits 23:16] Package. Maximum Ratio Limit for 11C.
+    ///
+    UINT32  Maximum11C:8;
+    ///
+    /// [Bits 31:24] Package. Maximum Ratio Limit for 12C.
+    ///
+    UINT32  Maximum12C:8;
+    ///
+    /// [Bits 39:32] Package. Maximum Ratio Limit for 13C.
+    ///
+    UINT32  Maximum13C:8;
+    ///
+    /// [Bits 47:40] Package. Maximum Ratio Limit for 14C.
+    ///
+    UINT32  Maximum14C:8;
+    ///
+    /// [Bits 55:48] Package. Maximum Ratio Limit for 15C.
+    ///
+    UINT32  Maximum15C:8;
+    ///
+    /// [Bits 63:56] Package. Maximum Ratio Limit for 16C.
+    ///
+    UINT32  Maximum16C:8;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER;
+
+
+/**
+  Package. Unit Multipliers used in RAPL Interfaces (R/O).
+
+  @param  ECX  MSR_XEON_D_RAPL_POWER_UNIT (0x00000606)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_XEON_D_RAPL_POWER_UNIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_XEON_D_RAPL_POWER_UNIT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_XEON_D_RAPL_POWER_UNIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_RAPL_POWER_UNIT);
+  @endcode
+  @note MSR_XEON_D_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
+**/
+#define MSR_XEON_D_RAPL_POWER_UNIT               0x00000606
+
+/**
+  MSR information returned for MSR index #MSR_XEON_D_RAPL_POWER_UNIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".
+    ///
+    UINT32  PowerUnits:4;
+    UINT32  Reserved1:4;
+    ///
+    /// [Bits 12:8] Package. Energy Status Units Energy related information
+    /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an
+    /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61
+    /// micro-joules).
+    ///
+    UINT32  EnergyStatusUnits:5;
+    UINT32  Reserved2:3;
+    ///
+    /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL
+    /// Interfaces.".
+    ///
+    UINT32  TimeUnits:4;
+    UINT32  Reserved3:12;
+    UINT32  Reserved4:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_D_RAPL_POWER_UNIT_REGISTER;
+
+
+/**
+  Package. DRAM RAPL Power Limit Control (R/W)  See Section 14.9.5, "DRAM RAPL
+  Domain.".
+
+  @param  ECX  MSR_XEON_D_DRAM_POWER_LIMIT (0x00000618)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_POWER_LIMIT);
+  AsmWriteMsr64 (MSR_XEON_D_DRAM_POWER_LIMIT, Msr);
+  @endcode
+  @note MSR_XEON_D_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
+**/
+#define MSR_XEON_D_DRAM_POWER_LIMIT              0x00000618
+
+
+/**
+  Package. DRAM Energy Status (R/O)  Energy consumed by DRAM devices.
+
+  @param  ECX  MSR_XEON_D_DRAM_ENERGY_STATUS (0x00000619)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_DRAM_ENERGY_STATUS);
+  @endcode
+  @note MSR_XEON_D_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
+**/
+#define MSR_XEON_D_DRAM_ENERGY_STATUS            0x00000619
+
+/**
+  MSR information returned for MSR index #MSR_XEON_D_DRAM_ENERGY_STATUS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration
+    /// to enable DRAM RAPL mode 0 (Direct VR).
+    ///
+    UINT32  Energy:32;
+    UINT32  Reserved:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER;
+
+
+/**
+  Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
+  RAPL Domain.".
+
+  @param  ECX  MSR_XEON_D_DRAM_PERF_STATUS (0x0000061B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_PERF_STATUS);
+  @endcode
+  @note MSR_XEON_D_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
+**/
+#define MSR_XEON_D_DRAM_PERF_STATUS              0x0000061B
+
+
+/**
+  Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
+
+  @param  ECX  MSR_XEON_D_DRAM_POWER_INFO (0x0000061C)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_POWER_INFO);
+  AsmWriteMsr64 (MSR_XEON_D_DRAM_POWER_INFO, Msr);
+  @endcode
+  @note MSR_XEON_D_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
+**/
+#define MSR_XEON_D_DRAM_POWER_INFO               0x0000061C
+
+
+/**
+  Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio
+  fields represent the widest possible range of uncore frequencies. Writing to
+  these fields allows software to control the minimum and the maximum
+  frequency that hardware will select.
+
+  @param  ECX  MSR_XEON_D_MSRUNCORE_RATIO_LIMIT (0x00000620)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_MSRUNCORE_RATIO_LIMIT);
+  AsmWriteMsr64 (MSR_XEON_D_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);
+  @endcode
+**/
+#define MSR_XEON_D_MSRUNCORE_RATIO_LIMIT         0x00000620
+
+/**
+  MSR information returned for MSR index #MSR_XEON_D_MSRUNCORE_RATIO_LIMIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the
+    /// LLC/Ring.
+    ///
+    UINT32  MAX_RATIO:7;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum
+    /// possible ratio of the LLC/Ring.
+    ///
+    UINT32  MIN_RATIO:7;
+    UINT32  Reserved2:17;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER;
+
+/**
+  Package. Reserved (R/O) Reads return 0.
+
+  @param  ECX  MSR_XEON_D_PP0_ENERGY_STATUS (0x00000639)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_D_PP0_ENERGY_STATUS);
+  @endcode
+  @note MSR_XEON_D_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
+**/
+#define MSR_XEON_D_PP0_ENERGY_STATUS             0x00000639
+
+
+/**
+  Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
+  refers to processor core frequency).
+
+  @param  ECX  MSR_XEON_D_CORE_PERF_LIMIT_REASONS (0x00000690)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_CORE_PERF_LIMIT_REASONS);
+  AsmWriteMsr64 (MSR_XEON_D_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
+  @endcode
+  @note MSR_XEON_D_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
+**/
+#define MSR_XEON_D_CORE_PERF_LIMIT_REASONS       0x00000690
+
+/**
+  MSR information returned for MSR index #MSR_XEON_D_CORE_PERF_LIMIT_REASONS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is
+    /// reduced below the operating system request due to assertion of
+    /// external PROCHOT.
+    ///
+    UINT32  PROCHOT_Status:1;
+    ///
+    /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the
+    /// operating system request due to a thermal event.
+    ///
+    UINT32  ThermalStatus:1;
+    ///
+    /// [Bit 2] Power Budget Management Status (R0) When set, frequency is
+    /// reduced below the operating system request due to PBM limit.
+    ///
+    UINT32  PowerBudgetManagementStatus:1;
+    ///
+    /// [Bit 3] Platform Configuration Services Status (R0) When set,
+    /// frequency is reduced below the operating system request due to PCS
+    /// limit.
+    ///
+    UINT32  PlatformConfigurationServicesStatus:1;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)
+    /// When set, frequency is reduced below the operating system request
+    /// because the processor has detected that utilization is low.
+    ///
+    UINT32  AutonomousUtilizationBasedFrequencyControlStatus:1;
+    ///
+    /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced
+    /// below the operating system request due to a thermal alert from the
+    /// Voltage Regulator.
+    ///
+    UINT32  VRThermAlertStatus:1;
+    UINT32  Reserved2:1;
+    ///
+    /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is
+    /// reduced below the operating system request due to electrical design
+    /// point constraints (e.g. maximum electrical current consumption).
+    ///
+    UINT32  ElectricalDesignPointStatus:1;
+    UINT32  Reserved3:1;
+    ///
+    /// [Bit 10] Multi-Core Turbo Status (R0) When set, frequency is reduced
+    /// below the operating system request due to Multi-Core Turbo limits.
+    ///
+    UINT32  MultiCoreTurboStatus:1;
+    UINT32  Reserved4:2;
+    ///
+    /// [Bit 13] Core Frequency P1 Status (R0) When set, frequency is reduced
+    /// below max non-turbo P1.
+    ///
+    UINT32  FrequencyP1Status:1;
+    ///
+    /// [Bit 14] Core Max n-core Turbo Frequency Limiting Status (R0) When
+    /// set, frequency is reduced below max n-core turbo frequency.
+    ///
+    UINT32  TurboFrequencyLimitingStatus:1;
+    ///
+    /// [Bit 15] Core Frequency Limiting Status (R0) When set, frequency is
+    /// reduced below the operating system request.
+    ///
+    UINT32  FrequencyLimitingStatus:1;
+    ///
+    /// [Bit 16] PROCHOT Log  When set, indicates that the PROCHOT Status bit
+    /// has asserted since the log bit was last cleared. This log bit will
+    /// remain set until cleared by software writing 0.
+    ///
+    UINT32  PROCHOT_Log:1;
+    ///
+    /// [Bit 17] Thermal Log  When set, indicates that the Thermal Status bit
+    /// has asserted since the log bit was last cleared. This log bit will
+    /// remain set until cleared by software writing 0.
+    ///
+    UINT32  ThermalLog:1;
+    ///
+    /// [Bit 18] Power Budget Management Log  When set, indicates that the PBM
+    /// Status bit has asserted since the log bit was last cleared. This log
+    /// bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  PowerBudgetManagementLog:1;
+    ///
+    /// [Bit 19] Platform Configuration Services Log  When set, indicates that
+    /// the PCS Status bit has asserted since the log bit was last cleared.
+    /// This log bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  PlatformConfigurationServicesLog:1;
+    UINT32  Reserved5:1;
+    ///
+    /// [Bit 21] Autonomous Utilization-Based Frequency Control Log  When set,
+    /// indicates that the AUBFC Status bit has asserted since the log bit was
+    /// last cleared. This log bit will remain set until cleared by software
+    /// writing 0.
+    ///
+    UINT32  AutonomousUtilizationBasedFrequencyControlLog:1;
+    ///
+    /// [Bit 22] VR Therm Alert Log  When set, indicates that the VR Therm
+    /// Alert Status bit has asserted since the log bit was last cleared. This
+    /// log bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  VRThermAlertLog:1;
+    UINT32  Reserved6:1;
+    ///
+    /// [Bit 24] Electrical Design Point Log  When set, indicates that the EDP
+    /// Status bit has asserted since the log bit was last cleared. This log
+    /// bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  ElectricalDesignPointLog:1;
+    UINT32  Reserved7:1;
+    ///
+    /// [Bit 26] Multi-Core Turbo Log  When set, indicates that the Multi-Core
+    /// Turbo Status bit has asserted since the log bit was last cleared. This
+    /// log bit will remain set until cleared by software writing 0.
+    ///
+    UINT32  MultiCoreTurboLog:1;
+    UINT32  Reserved8:2;
+    ///
+    /// [Bit 29] Core Frequency P1 Log When set, indicates that the Core
+    /// Frequency P1 Status bit has asserted since the log bit was last
+    /// cleared. This log bit will remain set until cleared by software
+    /// writing 0.
+    ///
+    UINT32  CoreFrequencyP1Log:1;
+    ///
+    /// [Bit 30] Core Max n-core Turbo Frequency Limiting Log When set,
+    /// indicates that the Core Max n-core Turbo Frequency Limiting Status bit
+    /// has asserted since the log bit was last cleared. This log bit will
+    /// remain set until cleared by software writing 0.
+    ///
+    UINT32  TurboFrequencyLimitingLog:1;
+    ///
+    /// [Bit 31] Core Frequency Limiting Log When set, indicates that the Core
+    /// Frequency Limiting Status bit has asserted since the log bit was last
+    /// cleared. This log bit will remain set until cleared by software
+    /// writing 0.
+    ///
+    UINT32  CoreFrequencyLimitingLog:1;
+    UINT32  Reserved9:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER;
+
+
+/**
+  THREAD. Monitoring Event Select Register (R/W) if CPUID.(EAX=07H,
+  ECX=0):EBX.RDT-M[bit 12] = 1.
+
+  @param  ECX  MSR_XEON_D_IA32_QM_EVTSEL (0x00000C8D)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_XEON_D_IA32_QM_EVTSEL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_XEON_D_IA32_QM_EVTSEL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_XEON_D_IA32_QM_EVTSEL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_QM_EVTSEL);
+  AsmWriteMsr64 (MSR_XEON_D_IA32_QM_EVTSEL, Msr.Uint64);
+  @endcode
+  @note MSR_XEON_D_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.
+**/
+#define MSR_XEON_D_IA32_QM_EVTSEL                0x00000C8D
+
+/**
+  MSR information returned for MSR index #MSR_XEON_D_IA32_QM_EVTSEL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] EventID (RW) Event encoding: 0x00: no monitoring 0x01: L3
+    /// occupancy monitoring 0x02: Total memory bandwidth monitoring 0x03:
+    /// Local memory bandwidth monitoring All other encoding reserved.
+    ///
+    UINT32  EventID:8;
+    UINT32  Reserved1:24;
+    ///
+    /// [Bits 41:32] RMID (RW).
+    ///
+    UINT32  RMID:10;
+    UINT32  Reserved2:22;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_D_IA32_QM_EVTSEL_REGISTER;
+
+
+/**
+  THREAD. Resource Association Register (R/W).
+
+  @param  ECX  MSR_XEON_D_IA32_PQR_ASSOC (0x00000C8F)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_XEON_D_IA32_PQR_ASSOC_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_XEON_D_IA32_PQR_ASSOC_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_XEON_D_IA32_PQR_ASSOC_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_PQR_ASSOC);
+  AsmWriteMsr64 (MSR_XEON_D_IA32_PQR_ASSOC, Msr.Uint64);
+  @endcode
+  @note MSR_XEON_D_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.
+**/
+#define MSR_XEON_D_IA32_PQR_ASSOC                0x00000C8F
+
+/**
+  MSR information returned for MSR index #MSR_XEON_D_IA32_PQR_ASSOC
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 9:0] RMID.
+    ///
+    UINT32  RMID:10;
+    UINT32  Reserved1:22;
+    ///
+    /// [Bits 51:32] COS (R/W).
+    ///
+    UINT32  COS:20;
+    UINT32  Reserved2:12;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_D_IA32_PQR_ASSOC_REGISTER;
+
+
+/**
+  Package. L3 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H,
+  ECX=1):EDX.COS_MAX[15:0] >= n.
+
+  @param  ECX  MSR_XEON_D_IA32_L3_QOS_MASK_n
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0);
+  AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0, Msr.Uint64);
+  @endcode
+  @note MSR_XEON_D_IA32_L3_QOS_MASK_0  is defined as IA32_L3_QOS_MASK_0  in SDM.
+        MSR_XEON_D_IA32_L3_QOS_MASK_1  is defined as IA32_L3_QOS_MASK_1  in SDM.
+        MSR_XEON_D_IA32_L3_QOS_MASK_2  is defined as IA32_L3_QOS_MASK_2  in SDM.
+        MSR_XEON_D_IA32_L3_QOS_MASK_3  is defined as IA32_L3_QOS_MASK_3  in SDM.
+        MSR_XEON_D_IA32_L3_QOS_MASK_4  is defined as IA32_L3_QOS_MASK_4  in SDM.
+        MSR_XEON_D_IA32_L3_QOS_MASK_5  is defined as IA32_L3_QOS_MASK_5  in SDM.
+        MSR_XEON_D_IA32_L3_QOS_MASK_6  is defined as IA32_L3_QOS_MASK_6  in SDM.
+        MSR_XEON_D_IA32_L3_QOS_MASK_7  is defined as IA32_L3_QOS_MASK_7  in SDM.
+        MSR_XEON_D_IA32_L3_QOS_MASK_8  is defined as IA32_L3_QOS_MASK_8  in SDM.
+        MSR_XEON_D_IA32_L3_QOS_MASK_9  is defined as IA32_L3_QOS_MASK_9  in SDM.
+        MSR_XEON_D_IA32_L3_QOS_MASK_10 is defined as IA32_L3_QOS_MASK_10 in SDM.
+        MSR_XEON_D_IA32_L3_QOS_MASK_11 is defined as IA32_L3_QOS_MASK_11 in SDM.
+        MSR_XEON_D_IA32_L3_QOS_MASK_12 is defined as IA32_L3_QOS_MASK_12 in SDM.
+        MSR_XEON_D_IA32_L3_QOS_MASK_13 is defined as IA32_L3_QOS_MASK_13 in SDM.
+        MSR_XEON_D_IA32_L3_QOS_MASK_14 is defined as IA32_L3_QOS_MASK_14 in SDM.
+        MSR_XEON_D_IA32_L3_QOS_MASK_15 is defined as IA32_L3_QOS_MASK_15 in SDM.
+  @{
+**/
+#define MSR_XEON_D_IA32_L3_QOS_MASK_0            0x00000C90
+#define MSR_XEON_D_IA32_L3_QOS_MASK_1            0x00000C91
+#define MSR_XEON_D_IA32_L3_QOS_MASK_2            0x00000C92
+#define MSR_XEON_D_IA32_L3_QOS_MASK_3            0x00000C93
+#define MSR_XEON_D_IA32_L3_QOS_MASK_4            0x00000C94
+#define MSR_XEON_D_IA32_L3_QOS_MASK_5            0x00000C95
+#define MSR_XEON_D_IA32_L3_QOS_MASK_6            0x00000C96
+#define MSR_XEON_D_IA32_L3_QOS_MASK_7            0x00000C97
+#define MSR_XEON_D_IA32_L3_QOS_MASK_8            0x00000C98
+#define MSR_XEON_D_IA32_L3_QOS_MASK_9            0x00000C99
+#define MSR_XEON_D_IA32_L3_QOS_MASK_10           0x00000C9A
+#define MSR_XEON_D_IA32_L3_QOS_MASK_11           0x00000C9B
+#define MSR_XEON_D_IA32_L3_QOS_MASK_12           0x00000C9C
+#define MSR_XEON_D_IA32_L3_QOS_MASK_13           0x00000C9D
+#define MSR_XEON_D_IA32_L3_QOS_MASK_14           0x00000C9E
+#define MSR_XEON_D_IA32_L3_QOS_MASK_15           0x00000C9F
+/// @}
+
+/**
+  MSR information returned for MSR indexes #MSR_XEON_D_IA32_L3_QOS_MASK_0
+  to #MSR_XEON_D_IA32_L3_QOS_MASK_15.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 19:0] CBM: Bit vector of available L3 ways for COS 0 enforcement.
+    ///
+    UINT32  CBM:20;
+    UINT32  Reserved2:12;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER;
+
+
+/**
+  Package. Config Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
+  RW if MSR_PLATFORM_INFO.[28] = 1.
+
+  @param  ECX  MSR_XEON_D_TURBO_RATIO_LIMIT3 (0x000001AC)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT3);
+  @endcode
+  @note MSR_XEON_D_TURBO_RATIO_LIMIT3 is defined as MSR_TURBO_RATIO_LIMIT3 in SDM.
+**/
+#define MSR_XEON_D_TURBO_RATIO_LIMIT3            0x000001AC
+
+/**
+  MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT3
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:32;
+    UINT32  Reserved2:31;
+    ///
+    /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,
+    /// the processor uses override configuration specified in
+    /// MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1. If 0, the processor
+    /// uses factory-set configuration (Default).
+    ///
+    UINT32  TurboRatioLimitConfigurationSemaphore:1;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER;
+
+
+/**
+  Package. Cache Allocation Technology Configuration (R/W).
+
+  @param  ECX  MSR_XEON_D_IA32_L3_QOS_CFG (0x00000C81)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_CFG);
+  AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_CFG, Msr.Uint64);
+  @endcode
+  @note MSR_XEON_D_IA32_L3_QOS_CFG is defined as IA32_L3_QOS_CFG in SDM.
+**/
+#define MSR_XEON_D_IA32_L3_QOS_CFG               0x00000C81
+
+/**
+  MSR information returned for MSR index #MSR_XEON_D_IA32_L3_QOS_CFG
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] CAT Enable. Set 1 to enable Cache Allocation Technology.
+    ///
+    UINT32  CAT:1;
+    UINT32  Reserved1:31;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER;
+
+#endif
diff --git a/MdePkg/Include/Register/Intel/Msr/XeonE7Msr.h b/MdePkg/Include/Register/Intel/Msr/XeonE7Msr.h
new file mode 100644
index 000000000000..895dd800f714
--- /dev/null
+++ b/MdePkg/Include/Register/Intel/Msr/XeonE7Msr.h
@@ -0,0 +1,367 @@
+/** @file
+  MSR Definitions for Intel(R) Xeon(R) Processor E7 Family.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+  May 2018, Volume 4: Model-Specific-Registers (MSR)
+
+**/
+
+#ifndef __XEON_E7_MSR_H__
+#define __XEON_E7_MSR_H__
+
+#include <Register/Intel/ArchitecturalMsr.h>
+
+/**
+  Is Intel(R) Xeon(R) Processor E7 Family?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_XEON_E7_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (                        \
+    DisplayModel == 0x2F    \
+    )                       \
+   )
+
+/**
+  Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
+  handler to handle unsuccessful read of this MSR.
+
+  @param  ECX  MSR_XEON_E7_FEATURE_CONFIG (0x0000013C)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_XEON_E7_FEATURE_CONFIG_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_XEON_E7_FEATURE_CONFIG_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_E7_FEATURE_CONFIG);
+  AsmWriteMsr64 (MSR_XEON_E7_FEATURE_CONFIG, Msr.Uint64);
+  @endcode
+  @note MSR_XEON_E7_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
+**/
+#define MSR_XEON_E7_FEATURE_CONFIG               0x0000013C
+
+/**
+  MSR information returned for MSR index #MSR_XEON_E7_FEATURE_CONFIG
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 1:0] AES Configuration (RW-L)  Upon a successful read of this
+    /// MSR, the configuration of AES instruction set availability is as
+    /// follows: 11b: AES instructions are not available until next RESET.
+    /// otherwise, AES instructions are available. Note, AES instruction set
+    /// is not available if read is unsuccessful. If the configuration is not
+    /// 01b, AES instruction can be mis-configured if a privileged agent
+    /// unintentionally writes 11b.
+    ///
+    UINT32  AESConfiguration:2;
+    UINT32  Reserved1:30;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_E7_FEATURE_CONFIG_REGISTER;
+
+
+/**
+  Thread. Offcore Response Event Select Register (R/W).
+
+  @param  ECX  MSR_XEON_E7_OFFCORE_RSP_1 (0x000001A7)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_E7_OFFCORE_RSP_1);
+  AsmWriteMsr64 (MSR_XEON_E7_OFFCORE_RSP_1, Msr);
+  @endcode
+  @note MSR_XEON_E7_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
+**/
+#define MSR_XEON_E7_OFFCORE_RSP_1                0x000001A7
+
+
+/**
+  Package. Reserved Attempt to read/write will cause #UD.
+
+  @param  ECX  MSR_XEON_E7_TURBO_RATIO_LIMIT (0x000001AD)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT);
+  AsmWriteMsr64 (MSR_XEON_E7_TURBO_RATIO_LIMIT, Msr);
+  @endcode
+  @note MSR_XEON_E7_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
+**/
+#define MSR_XEON_E7_TURBO_RATIO_LIMIT            0x000001AD
+
+
+/**
+  Package. Uncore C-box 8 perfmon local box control MSR.
+
+  @param  ECX  MSR_XEON_E7_C8_PMON_BOX_CTRL (0x00000F40)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL);
+  AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_CTRL, Msr);
+  @endcode
+  @note MSR_XEON_E7_C8_PMON_BOX_CTRL is defined as MSR_C8_PMON_BOX_CTRL in SDM.
+**/
+#define MSR_XEON_E7_C8_PMON_BOX_CTRL             0x00000F40
+
+
+/**
+  Package. Uncore C-box 8 perfmon local box status MSR.
+
+  @param  ECX  MSR_XEON_E7_C8_PMON_BOX_STATUS (0x00000F41)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_XEON_E7_C8_PMON_BOX_STATUS is defined as MSR_C8_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_XEON_E7_C8_PMON_BOX_STATUS           0x00000F41
+
+
+/**
+  Package. Uncore C-box 8 perfmon local box overflow control MSR.
+
+  @param  ECX  MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL (0x00000F42)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL);
+  AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL, Msr);
+  @endcode
+  @note MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL is defined as MSR_C8_PMON_BOX_OVF_CTRL in SDM.
+**/
+#define MSR_XEON_E7_C8_PMON_BOX_OVF_CTRL         0x00000F42
+
+
+/**
+  Package. Uncore C-box 8 perfmon event select MSR.
+
+  @param  ECX  MSR_XEON_E7_C8_PMON_EVNT_SELn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0);
+  AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_EVNT_SEL0, Msr);
+  @endcode
+  @note MSR_XEON_E7_C8_PMON_EVNT_SEL0 is defined as MSR_C8_PMON_EVNT_SEL0 in SDM.
+        MSR_XEON_E7_C8_PMON_EVNT_SEL1 is defined as MSR_C8_PMON_EVNT_SEL1 in SDM.
+        MSR_XEON_E7_C8_PMON_EVNT_SEL2 is defined as MSR_C8_PMON_EVNT_SEL2 in SDM.
+        MSR_XEON_E7_C8_PMON_EVNT_SEL3 is defined as MSR_C8_PMON_EVNT_SEL3 in SDM.
+        MSR_XEON_E7_C8_PMON_EVNT_SEL4 is defined as MSR_C8_PMON_EVNT_SEL4 in SDM.
+        MSR_XEON_E7_C8_PMON_EVNT_SEL5 is defined as MSR_C8_PMON_EVNT_SEL5 in SDM.
+  @{
+**/
+#define MSR_XEON_E7_C8_PMON_EVNT_SEL0            0x00000F50
+#define MSR_XEON_E7_C8_PMON_EVNT_SEL1            0x00000F52
+#define MSR_XEON_E7_C8_PMON_EVNT_SEL2            0x00000F54
+#define MSR_XEON_E7_C8_PMON_EVNT_SEL3            0x00000F56
+#define MSR_XEON_E7_C8_PMON_EVNT_SEL4            0x00000F58
+#define MSR_XEON_E7_C8_PMON_EVNT_SEL5            0x00000F5A
+/// @}
+
+
+/**
+  Package. Uncore C-box 8 perfmon counter MSR.
+
+  @param  ECX  MSR_XEON_E7_C8_PMON_CTRn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_E7_C8_PMON_CTR0);
+  AsmWriteMsr64 (MSR_XEON_E7_C8_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_XEON_E7_C8_PMON_CTR0 is defined as MSR_C8_PMON_CTR0 in SDM.
+        MSR_XEON_E7_C8_PMON_CTR1 is defined as MSR_C8_PMON_CTR1 in SDM.
+        MSR_XEON_E7_C8_PMON_CTR2 is defined as MSR_C8_PMON_CTR2 in SDM.
+        MSR_XEON_E7_C8_PMON_CTR3 is defined as MSR_C8_PMON_CTR3 in SDM.
+        MSR_XEON_E7_C8_PMON_CTR4 is defined as MSR_C8_PMON_CTR4 in SDM.
+        MSR_XEON_E7_C8_PMON_CTR5 is defined as MSR_C8_PMON_CTR5 in SDM.
+  @{
+**/
+#define MSR_XEON_E7_C8_PMON_CTR0                 0x00000F51
+#define MSR_XEON_E7_C8_PMON_CTR1                 0x00000F53
+#define MSR_XEON_E7_C8_PMON_CTR2                 0x00000F55
+#define MSR_XEON_E7_C8_PMON_CTR3                 0x00000F57
+#define MSR_XEON_E7_C8_PMON_CTR4                 0x00000F59
+#define MSR_XEON_E7_C8_PMON_CTR5                 0x00000F5B
+/// @}
+
+
+/**
+  Package. Uncore C-box 9 perfmon local box control MSR.
+
+  @param  ECX  MSR_XEON_E7_C9_PMON_BOX_CTRL (0x00000FC0)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL);
+  AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_CTRL, Msr);
+  @endcode
+  @note MSR_XEON_E7_C9_PMON_BOX_CTRL is defined as MSR_C9_PMON_BOX_CTRL in SDM.
+**/
+#define MSR_XEON_E7_C9_PMON_BOX_CTRL             0x00000FC0
+
+
+/**
+  Package. Uncore C-box 9 perfmon local box status MSR.
+
+  @param  ECX  MSR_XEON_E7_C9_PMON_BOX_STATUS (0x00000FC1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS);
+  AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_STATUS, Msr);
+  @endcode
+  @note MSR_XEON_E7_C9_PMON_BOX_STATUS is defined as MSR_C9_PMON_BOX_STATUS in SDM.
+**/
+#define MSR_XEON_E7_C9_PMON_BOX_STATUS           0x00000FC1
+
+
+/**
+  Package. Uncore C-box 9 perfmon local box overflow control MSR.
+
+  @param  ECX  MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL (0x00000FC2)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL);
+  AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL, Msr);
+  @endcode
+  @note MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL is defined as MSR_C9_PMON_BOX_OVF_CTRL in SDM.
+**/
+#define MSR_XEON_E7_C9_PMON_BOX_OVF_CTRL         0x00000FC2
+
+
+/**
+  Package. Uncore C-box 9 perfmon event select MSR.
+
+  @param  ECX  MSR_XEON_E7_C9_PMON_EVNT_SELn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0);
+  AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_EVNT_SEL0, Msr);
+  @endcode
+  @note MSR_XEON_E7_C9_PMON_EVNT_SEL0 is defined as MSR_C9_PMON_EVNT_SEL0 in SDM.
+        MSR_XEON_E7_C9_PMON_EVNT_SEL1 is defined as MSR_C9_PMON_EVNT_SEL1 in SDM.
+        MSR_XEON_E7_C9_PMON_EVNT_SEL2 is defined as MSR_C9_PMON_EVNT_SEL2 in SDM.
+        MSR_XEON_E7_C9_PMON_EVNT_SEL3 is defined as MSR_C9_PMON_EVNT_SEL3 in SDM.
+        MSR_XEON_E7_C9_PMON_EVNT_SEL4 is defined as MSR_C9_PMON_EVNT_SEL4 in SDM.
+        MSR_XEON_E7_C9_PMON_EVNT_SEL5 is defined as MSR_C9_PMON_EVNT_SEL5 in SDM.
+  @{
+**/
+#define MSR_XEON_E7_C9_PMON_EVNT_SEL0            0x00000FD0
+#define MSR_XEON_E7_C9_PMON_EVNT_SEL1            0x00000FD2
+#define MSR_XEON_E7_C9_PMON_EVNT_SEL2            0x00000FD4
+#define MSR_XEON_E7_C9_PMON_EVNT_SEL3            0x00000FD6
+#define MSR_XEON_E7_C9_PMON_EVNT_SEL4            0x00000FD8
+#define MSR_XEON_E7_C9_PMON_EVNT_SEL5            0x00000FDA
+/// @}
+
+
+/**
+  Package. Uncore C-box 9 perfmon counter MSR.
+
+  @param  ECX  MSR_XEON_E7_C9_PMON_CTRn
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_E7_C9_PMON_CTR0);
+  AsmWriteMsr64 (MSR_XEON_E7_C9_PMON_CTR0, Msr);
+  @endcode
+  @note MSR_XEON_E7_C9_PMON_CTR0 is defined as MSR_C9_PMON_CTR0 in SDM.
+        MSR_XEON_E7_C9_PMON_CTR1 is defined as MSR_C9_PMON_CTR1 in SDM.
+        MSR_XEON_E7_C9_PMON_CTR2 is defined as MSR_C9_PMON_CTR2 in SDM.
+        MSR_XEON_E7_C9_PMON_CTR3 is defined as MSR_C9_PMON_CTR3 in SDM.
+        MSR_XEON_E7_C9_PMON_CTR4 is defined as MSR_C9_PMON_CTR4 in SDM.
+        MSR_XEON_E7_C9_PMON_CTR5 is defined as MSR_C9_PMON_CTR5 in SDM.
+  @{
+**/
+#define MSR_XEON_E7_C9_PMON_CTR0                 0x00000FD1
+#define MSR_XEON_E7_C9_PMON_CTR1                 0x00000FD3
+#define MSR_XEON_E7_C9_PMON_CTR2                 0x00000FD5
+#define MSR_XEON_E7_C9_PMON_CTR3                 0x00000FD7
+#define MSR_XEON_E7_C9_PMON_CTR4                 0x00000FD9
+#define MSR_XEON_E7_C9_PMON_CTR5                 0x00000FDB
+/// @}
+
+#endif
diff --git a/MdePkg/Include/Register/Intel/Msr/XeonPhiMsr.h b/MdePkg/Include/Register/Intel/Msr/XeonPhiMsr.h
new file mode 100644
index 000000000000..74d1969d3066
--- /dev/null
+++ b/MdePkg/Include/Register/Intel/Msr/XeonPhiMsr.h
@@ -0,0 +1,1673 @@
+/** @file
+  MSR Definitions for Intel(R) Xeon(R) Phi(TM) processor Family.
+
+  Provides defines for Machine Specific Registers(MSR) indexes. Data structures
+  are provided for MSRs that contain one or more bit fields.  If the MSR value
+  returned is a single 32-bit or 64-bit value, then a data structure is not
+  provided for that MSR.
+
+  Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
+  May 2018, Volume 4: Model-Specific-Registers (MSR)
+
+**/
+
+#ifndef __XEON_PHI_MSR_H__
+#define __XEON_PHI_MSR_H__
+
+#include <Register/Intel/ArchitecturalMsr.h>
+
+/**
+  Is Intel(R) Xeon(R) Phi(TM) processor Family?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_XEON_PHI_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (                        \
+    DisplayModel == 0x57 || \
+    DisplayModel == 0x85    \
+    )                       \
+   )
+
+/**
+  Thread. SMI Counter (R/O).
+
+  @param  ECX  MSR_XEON_PHI_SMI_COUNT (0x00000034)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_XEON_PHI_SMI_COUNT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMI_COUNT);
+  @endcode
+  @note MSR_XEON_PHI_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.
+**/
+#define MSR_XEON_PHI_SMI_COUNT                   0x00000034
+
+/**
+  MSR information returned for MSR index #MSR_XEON_PHI_SMI_COUNT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 31:0] SMI Count (R/O).
+    ///
+    UINT32  SMICount:32;
+    UINT32  Reserved:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_PHI_SMI_COUNT_REGISTER;
+
+/**
+  Package. Protected Processor Inventory Number Enable Control (R/W).
+
+  @param  ECX  MSR_XEON_PHI_PPIN_CTL (0x0000004E)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_XEON_PHI_PPIN_CTL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_XEON_PHI_PPIN_CTL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_XEON_PHI_PPIN_CTL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PPIN_CTL);
+  AsmWriteMsr64 (MSR_XEON_PHI_PPIN_CTL, Msr.Uint64);
+  @endcode
+**/
+#define MSR_XEON_PHI_PPIN_CTL                    0x0000004E
+
+/**
+  MSR information returned for MSR index #MSR_XEON_PHI_PPIN_CTL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] LockOut (R/WO) Set 1 to prevent further writes to
+    /// MSR_PPIN_CTL. Writing 1 to MSR_PPINCTL[bit 0] is permitted only if
+    /// MSR_PPIN_CTL[bit 1] is clear. Default is 0. BIOS should provide an
+    /// opt-in menu to enable the user to turn on MSR_PPIN_CTL[bit 1] for a
+    /// privileged inventory initialization agent to access MSR_PPIN. After
+    /// reading MSR_PPIN, the privileged inventory initialization agent should
+    /// write '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and
+    /// prevent unauthorized modification to MSR_PPIN_CTL.
+    ///
+    UINT32  LockOut:1;
+    ///
+    /// [Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible
+    /// using RDMSR. Once set, an attempt to write 1 to MSR_PPIN_CTL[bit 0]
+    /// will cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP.
+    /// Default is 0.
+    ///
+    UINT32  Enable_PPIN:1;
+    UINT32  Reserved1:30;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_PHI_PPIN_CTL_REGISTER;
+
+
+/**
+  Package. Protected Processor Inventory Number (R/O). Protected Processor
+  Inventory Number (R/O) A unique value within a given CPUID
+  family/model/stepping signature that a privileged inventory initialization
+  agent can access to identify each physical processor, when access to
+  MSR_PPIN is enabled. Access to MSR_PPIN is permitted only if
+  MSR_PPIN_CTL[bits 1:0] = '10b'.
+
+  @param  ECX  MSR_XEON_PHI_PPIN (0x0000004F)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_PHI_PPIN);
+  @endcode
+**/
+#define MSR_XEON_PHI_PPIN                        0x0000004F
+
+/**
+  Package. Platform Information Contains power management and other model
+  specific features enumeration. See http://biosbits.org.
+
+  @param  ECX  MSR_XEON_PHI_PLATFORM_INFO (0x000000CE)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_XEON_PHI_PLATFORM_INFO_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PLATFORM_INFO);
+  AsmWriteMsr64 (MSR_XEON_PHI_PLATFORM_INFO, Msr.Uint64);
+  @endcode
+  @note MSR_XEON_PHI_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.
+**/
+#define MSR_XEON_PHI_PLATFORM_INFO               0x000000CE
+
+/**
+  MSR information returned for MSR index #MSR_XEON_PHI_PLATFORM_INFO
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:8;
+    ///
+    /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O)  The is the ratio
+    /// of the frequency that invariant TSC runs at. Frequency = ratio * 100
+    /// MHz.
+    ///
+    UINT32  MaximumNonTurboRatio:8;
+    UINT32  Reserved2:12;
+    ///
+    /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O)  When
+    /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is
+    /// enabled, and when set to 0, indicates Programmable Ratio Limits for
+    /// Turbo mode is disabled.
+    ///
+    UINT32  RatioLimit:1;
+    ///
+    /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O)  When
+    /// set to 1, indicates that TDP Limits for Turbo mode are programmable,
+    /// and when set to 0, indicates TDP Limit for Turbo mode is not
+    /// programmable.
+    ///
+    UINT32  TDPLimit:1;
+    UINT32  Reserved3:2;
+    UINT32  Reserved4:8;
+    ///
+    /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O)  The is the
+    /// minimum ratio (maximum efficiency) that the processor can operates, in
+    /// units of 100MHz.
+    ///
+    UINT32  MaximumEfficiencyRatio:8;
+    UINT32  Reserved5:16;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_PHI_PLATFORM_INFO_REGISTER;
+
+
+/**
+  Module. C-State Configuration Control (R/W).
+
+  @param  ECX  MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL (0x000000E2)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL);
+  AsmWriteMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL, Msr.Uint64);
+  @endcode
+  @note MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.
+**/
+#define MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL      0x000000E2
+
+/**
+  MSR information returned for MSR index #MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 2:0] Package C-State Limit (R/W)  The following C-state code
+    /// name encodings are supported: 000b: C0/C1 001b: C2 010b: C6 No
+    /// Retention 011b: C6 Retention 111b: No limit.
+    ///
+    UINT32  Limit:3;
+    UINT32  Reserved1:7;
+    ///
+    /// [Bit 10] I/O MWAIT Redirection Enable (R/W).
+    ///
+    UINT32  IO_MWAIT:1;
+    UINT32  Reserved2:4;
+    ///
+    /// [Bit 15] CFG Lock (R/WO).
+    ///
+    UINT32  CFGLock:1;
+    UINT32  Reserved5:10;
+    ///
+    /// [Bit 26] C1 State Auto Demotion Enable (R/W) When set, the processor
+    /// will conditionally demote C3/C6/C7 requests to C1 based on uncore
+    /// auto-demote information.
+    ///
+    UINT32  C1StateAutoDemotionEnable:1;
+    UINT32  Reserved6:1;
+    ///
+    /// [Bit 28] C1 State Auto Undemotion Enable (R/W) When set, enables
+    /// Undemotion from Demoted C1.
+    ///
+    UINT32  C1StateAutoUndemotionEnable:1;
+    ///
+    /// [Bit 29] PKG C-State Auto Demotion Enable (R/W) When set, enables
+    /// Package C state demotion.
+    ///
+    UINT32  PKGC_StateAutoDemotionEnable:1;
+    UINT32  Reserved7:2;
+    UINT32  Reserved4:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER;
+
+
+/**
+  Module. Power Management IO Redirection in C-state (R/W).
+
+  @param  ECX  MSR_XEON_PHI_PMG_IO_CAPTURE_BASE (0x000000E4)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE);
+  AsmWriteMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE, Msr.Uint64);
+  @endcode
+  @note MSR_XEON_PHI_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.
+**/
+#define MSR_XEON_PHI_PMG_IO_CAPTURE_BASE         0x000000E4
+
+/**
+  MSR information returned for MSR index #MSR_XEON_PHI_PMG_IO_CAPTURE_BASE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 15:0] LVL_2 Base Address (R/W).
+    ///
+    UINT32  Lvl2Base:16;
+    ///
+    /// [Bits 22:16] C-State Range (R/W) The IO-port block size in which
+    /// IO-redirection will be executed (0-127). Should be programmed based on
+    /// the number of LVLx registers existing in the chipset.
+    ///
+    UINT32  CStateRange:7;
+    UINT32  Reserved3:9;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER;
+
+
+/**
+  Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
+  handler to handle unsuccessful read of this MSR.
+
+  @param  ECX  MSR_XEON_PHI_FEATURE_CONFIG (0x0000013C)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_XEON_PHI_FEATURE_CONFIG_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_XEON_PHI_FEATURE_CONFIG_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_XEON_PHI_FEATURE_CONFIG_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_FEATURE_CONFIG);
+  AsmWriteMsr64 (MSR_XEON_PHI_FEATURE_CONFIG, Msr.Uint64);
+  @endcode
+  @note MSR_XEON_PHI_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
+**/
+#define MSR_XEON_PHI_FEATURE_CONFIG              0x0000013C
+
+/**
+  MSR information returned for MSR index #MSR_XEON_PHI_FEATURE_CONFIG
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 1:0] AES Configuration (RW-L)  Upon a successful read of this
+    /// MSR, the configuration of AES instruction set availability is as
+    /// follows: 11b: AES instructions are not available until next RESET.
+    /// otherwise, AES instructions are available. Note, AES instruction set
+    /// is not available if read is unsuccessful. If the configuration is not
+    /// 01b, AES instruction can be mis-configured if a privileged agent
+    /// unintentionally writes 11b.
+    ///
+    UINT32  AESConfiguration:2;
+    UINT32  Reserved1:30;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_PHI_FEATURE_CONFIG_REGISTER;
+
+
+/**
+  Thread. MISC_FEATURE_ENABLES.
+
+  @param  ECX  MSR_XEON_PHI_MISC_FEATURE_ENABLES (0x00000140)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MISC_FEATURE_ENABLES);
+  AsmWriteMsr64 (MSR_XEON_PHI_MISC_FEATURE_ENABLES, Msr.Uint64);
+  @endcode
+**/
+#define MSR_XEON_PHI_MISC_FEATURE_ENABLES        0x00000140
+
+/**
+  MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_ENABLES
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:1;
+    ///
+    /// [Bit 1] User Mode MONITOR and MWAIT (R/W) If set to 1, the MONITOR and
+    /// MWAIT instructions do not cause invalid-opcode exceptions when
+    /// executed with CPL > 0 or in virtual-8086 mode. If MWAIT is executed
+    /// when CPL > 0 or in virtual-8086 mode, and if EAX indicates a C-state
+    /// other than C0 or C1, the instruction operates as if EAX indicated the
+    /// C-state C1.
+    ///
+    UINT32  UserModeMonitorAndMwait:1;
+    UINT32  Reserved2:30;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER;
+
+/**
+  THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability
+  Enhancement. Accessible only while in SMM.
+
+  @param  ECX  MSR_XEON_PHI_SMM_MCA_CAP (0x0000017D)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_XEON_PHI_SMM_MCA_CAP_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_XEON_PHI_SMM_MCA_CAP_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_XEON_PHI_SMM_MCA_CAP_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMM_MCA_CAP);
+  AsmWriteMsr64 (MSR_XEON_PHI_SMM_MCA_CAP, Msr.Uint64);
+  @endcode
+  @note MSR_XEON_PHI_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.
+**/
+#define MSR_XEON_PHI_SMM_MCA_CAP                 0x0000017D
+
+/**
+  MSR information returned for MSR index #MSR_XEON_PHI_SMM_MCA_CAP
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 31:0] Bank Support (SMM-RO) One bit per MCA bank. If the bit is
+    /// set, that bank supports Enhanced MCA (Default all 0; does not support
+    /// EMCA).
+    ///
+    UINT32  BankSupport:32;
+    UINT32  Reserved4:24;
+    ///
+    /// [Bit 56] Targeted SMI (SMM-RO) Set if targeted SMI is supported.
+    ///
+    UINT32  TargetedSMI:1;
+    ///
+    /// [Bit 57] SMM_CPU_SVRSTR (SMM-RO) Set if SMM SRAM save/restore feature
+    /// is supported.
+    ///
+    UINT32  SMM_CPU_SVRSTR:1;
+    ///
+    /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the
+    /// SMM code access restriction is supported and a host-space interface
+    /// available to SMM handler.
+    ///
+    UINT32  SMM_Code_Access_Chk:1;
+    ///
+    /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the
+    /// SMM long flow indicator is supported and a host-space interface
+    /// available to SMM handler.
+    ///
+    UINT32  Long_Flow_Indication:1;
+    UINT32  Reserved3:4;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_PHI_SMM_MCA_CAP_REGISTER;
+
+
+/**
+  Thread. Enable Misc. Processor Features (R/W)  Allows a variety of processor
+  functions to be enabled and disabled.
+
+  @param  ECX  MSR_XEON_PHI_IA32_MISC_ENABLE (0x000001A0)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE);
+  AsmWriteMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE, Msr.Uint64);
+  @endcode
+  @note MSR_XEON_PHI_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
+**/
+#define MSR_XEON_PHI_IA32_MISC_ENABLE            0x000001A0
+
+/**
+  MSR information returned for MSR index #MSR_XEON_PHI_IA32_MISC_ENABLE
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Fast-Strings Enable.
+    ///
+    UINT32  FastStrings:1;
+    UINT32  Reserved1:2;
+    ///
+    /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) Default value
+    /// is 1.
+    ///
+    UINT32  AutomaticThermalControlCircuit:1;
+    UINT32  Reserved2:3;
+    ///
+    /// [Bit 7] Performance Monitoring Available (R).
+    ///
+    UINT32  PerformanceMonitoring:1;
+    UINT32  Reserved3:3;
+    ///
+    /// [Bit 11] Branch Trace Storage Unavailable (RO).
+    ///
+    UINT32  BTS:1;
+    ///
+    /// [Bit 12] Processor Event Based Sampling Unavailable (RO).
+    ///
+    UINT32  PEBS:1;
+    UINT32  Reserved4:3;
+    ///
+    /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W).
+    ///
+    UINT32  EIST:1;
+    UINT32  Reserved5:1;
+    ///
+    /// [Bit 18] ENABLE MONITOR FSM (R/W).
+    ///
+    UINT32  MONITOR:1;
+    UINT32  Reserved6:3;
+    ///
+    /// [Bit 22] Limit CPUID Maxval (R/W).
+    ///
+    UINT32  LimitCpuidMaxval:1;
+    ///
+    /// [Bit 23] xTPR Message Disable (R/W).
+    ///
+    UINT32  xTPR_Message_Disable:1;
+    UINT32  Reserved7:8;
+    UINT32  Reserved8:2;
+    ///
+    /// [Bit 34] XD Bit Disable (R/W).
+    ///
+    UINT32  XD:1;
+    UINT32  Reserved9:3;
+    ///
+    /// [Bit 38] Turbo Mode Disable (R/W).
+    ///
+    UINT32  TurboModeDisable:1;
+    UINT32  Reserved10:25;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER;
+
+
+/**
+  Package.
+
+  @param  ECX  MSR_XEON_PHI_TEMPERATURE_TARGET (0x000001A2)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET);
+  AsmWriteMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET, Msr.Uint64);
+  @endcode
+  @note MSR_XEON_PHI_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.
+**/
+#define MSR_XEON_PHI_TEMPERATURE_TARGET          0x000001A2
+
+/**
+  MSR information returned for MSR index #MSR_XEON_PHI_TEMPERATURE_TARGET
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved1:16;
+    ///
+    /// [Bits 23:16] Temperature Target (R).
+    ///
+    UINT32  TemperatureTarget:8;
+    ///
+    /// [Bits 29:24] Target Offset (R/W).
+    ///
+    UINT32  TargetOffset:6;
+    UINT32  Reserved2:2;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER;
+
+
+/**
+  Miscellaneous Feature Control (R/W).
+
+  @param  ECX  MSR_XEON_PHI_MISC_FEATURE_CONTROL (0x000001A4)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MISC_FEATURE_CONTROL);
+  AsmWriteMsr64 (MSR_XEON_PHI_MISC_FEATURE_CONTROL, Msr.Uint64);
+  @endcode
+  @note MSR_XEON_PHI_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.
+**/
+#define MSR_XEON_PHI_MISC_FEATURE_CONTROL        0x000001A4
+
+/**
+  MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_CONTROL
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables the
+    /// L1 data cache prefetcher.
+    ///
+    UINT32  DCUHardwarePrefetcherDisable:1;
+    ///
+    /// [Bit 1] Core. L2 Hardware Prefetcher Disable (R/W)  If 1, disables the
+    /// L2 hardware prefetcher.
+    ///
+    UINT32  L2HardwarePrefetcherDisable:1;
+    UINT32  Reserved1:30;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER;
+
+
+/**
+  Shared. Offcore Response Event Select Register (R/W).
+
+  @param  ECX  MSR_XEON_PHI_OFFCORE_RSP_0 (0x000001A6)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0);
+  AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0, Msr);
+  @endcode
+  @note MSR_XEON_PHI_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.
+**/
+#define MSR_XEON_PHI_OFFCORE_RSP_0               0x000001A6
+
+
+/**
+  Shared. Offcore Response Event Select Register (R/W).
+
+  @param  ECX  MSR_XEON_PHI_OFFCORE_RSP_1 (0x000001A7)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1);
+  AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1, Msr);
+  @endcode
+  @note MSR_XEON_PHI_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
+**/
+#define MSR_XEON_PHI_OFFCORE_RSP_1               0x000001A7
+
+
+/**
+  Package. Maximum Ratio Limit of Turbo Mode for Groups of Cores (RW).
+
+  @param  ECX  MSR_XEON_PHI_TURBO_RATIO_LIMIT (0x000001AD)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT);
+  AsmWriteMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT, Msr.Uint64);
+  @endcode
+  @note MSR_XEON_PHI_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
+**/
+#define MSR_XEON_PHI_TURBO_RATIO_LIMIT           0x000001AD
+
+/**
+  MSR information returned for MSR index #MSR_XEON_PHI_TURBO_RATIO_LIMIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    UINT32  Reserved:1;
+    ///
+    /// [Bits 7:1] Package. Maximum Number of Cores in Group 0 Number active
+    /// processor cores which operates under the maximum ratio limit for group
+    /// 0.
+    ///
+    UINT32  MaxCoresGroup0:7;
+    ///
+    /// [Bits 15:8] Package. Maximum Ratio Limit for Group 0 Maximum turbo
+    /// ratio limit when the number of active cores are not more than the
+    /// group 0 maximum core count.
+    ///
+    UINT32  MaxRatioLimitGroup0:8;
+    ///
+    /// [Bits 20:16] Package. Number of Incremental Cores Added to Group 1
+    /// Group 1, which includes the specified number of additional cores plus
+    /// the cores in group 0, operates under the group 1 turbo max ratio limit
+    /// = "group 0 Max ratio limit" - "group ratio delta for group 1".
+    ///
+    UINT32  MaxIncrementalCoresGroup1:5;
+    ///
+    /// [Bits 23:21] Package. Group Ratio Delta for Group 1 An unsigned
+    /// integer specifying the ratio decrement relative to the Max ratio limit
+    /// to Group 0.
+    ///
+    UINT32  DeltaRatioGroup1:3;
+    ///
+    /// [Bits 28:24] Package. Number of Incremental Cores Added to Group 2
+    /// Group 2, which includes the specified number of additional cores plus
+    /// all the cores in group 1, operates under the group 2 turbo max ratio
+    /// limit = "group 1 Max ratio limit" - "group ratio delta for group 2".
+    ///
+    UINT32  MaxIncrementalCoresGroup2:5;
+    ///
+    /// [Bits 31:29] Package. Group Ratio Delta for Group 2 An unsigned
+    /// integer specifying the ratio decrement relative to the Max ratio limit
+    /// for Group 1.
+    ///
+    UINT32  DeltaRatioGroup2:3;
+    ///
+    /// [Bits 36:32] Package. Number of Incremental Cores Added to Group 3
+    /// Group 3, which includes the specified number of additional cores plus
+    /// all the cores in group 2, operates under the group 3 turbo max ratio
+    /// limit = "group 2 Max ratio limit" - "group ratio delta for group 3".
+    ///
+    UINT32  MaxIncrementalCoresGroup3:5;
+    ///
+    /// [Bits 39:37] Package. Group Ratio Delta for Group 3 An unsigned
+    /// integer specifying the ratio decrement relative to the Max ratio limit
+    /// for Group 2.
+    ///
+    UINT32  DeltaRatioGroup3:3;
+    ///
+    /// [Bits 44:40] Package. Number of Incremental Cores Added to Group 4
+    /// Group 4, which includes the specified number of additional cores plus
+    /// all the cores in group 3, operates under the group 4 turbo max ratio
+    /// limit = "group 3 Max ratio limit" - "group ratio delta for group 4".
+    ///
+    UINT32  MaxIncrementalCoresGroup4:5;
+    ///
+    /// [Bits 47:45] Package. Group Ratio Delta for Group 4 An unsigned
+    /// integer specifying the ratio decrement relative to the Max ratio limit
+    /// for Group 3.
+    ///
+    UINT32  DeltaRatioGroup4:3;
+    ///
+    /// [Bits 52:48] Package. Number of Incremental Cores Added to Group 5
+    /// Group 5, which includes the specified number of additional cores plus
+    /// all the cores in group 4, operates under the group 5 turbo max ratio
+    /// limit = "group 4 Max ratio limit" - "group ratio delta for group 5".
+    ///
+    UINT32  MaxIncrementalCoresGroup5:5;
+    ///
+    /// [Bits 55:53] Package. Group Ratio Delta for Group 5 An unsigned
+    /// integer specifying the ratio decrement relative to the Max ratio limit
+    /// for Group 4.
+    ///
+    UINT32  DeltaRatioGroup5:3;
+    ///
+    /// [Bits 60:56] Package. Number of Incremental Cores Added to Group 6
+    /// Group 6, which includes the specified number of additional cores plus
+    /// all the cores in group 5, operates under the group 6 turbo max ratio
+    /// limit = "group 5 Max ratio limit" - "group ratio delta for group 6".
+    ///
+    UINT32  MaxIncrementalCoresGroup6:5;
+    ///
+    /// [Bits 63:61] Package. Group Ratio Delta for Group 6 An unsigned
+    /// integer specifying the ratio decrement relative to the Max ratio limit
+    /// for Group 5.
+    ///
+    UINT32  DeltaRatioGroup6:3;
+  } Bits;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER;
+
+
+/**
+  Thread. Last Branch Record Filtering Select Register (R/W).
+
+  @param  ECX  MSR_XEON_PHI_LBR_SELECT (0x000001C8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_PHI_LBR_SELECT);
+  AsmWriteMsr64 (MSR_XEON_PHI_LBR_SELECT, Msr);
+  @endcode
+  @note MSR_XEON_PHI_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.
+**/
+#define MSR_XEON_PHI_LBR_SELECT                  0x000001C8
+
+
+/**
+  MSR information returned for MSR index #MSR_XEON_PHI_LBR_SELECT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] CPL_EQ_0.
+    ///
+    UINT32  CPL_EQ_0:1;
+    ///
+    /// [Bit 1] CPL_NEQ_0.
+    ///
+    UINT32  CPL_NEQ_0:1;
+    ///
+    /// [Bit 2] JCC.
+    ///
+    UINT32  JCC:1;
+    ///
+    /// [Bit 3] NEAR_REL_CALL.
+    ///
+    UINT32  NEAR_REL_CALL:1;
+    ///
+    /// [Bit 4] NEAR_IND_CALL.
+    ///
+    UINT32  NEAR_IND_CALL:1;
+    ///
+    /// [Bit 5] NEAR_RET.
+    ///
+    UINT32  NEAR_RET:1;
+    ///
+    /// [Bit 6] NEAR_IND_JMP.
+    ///
+    UINT32  NEAR_IND_JMP:1;
+    ///
+    /// [Bit 7] NEAR_REL_JMP.
+    ///
+    UINT32  NEAR_REL_JMP:1;
+    ///
+    /// [Bit 8] FAR_BRANCH.
+    ///
+    UINT32  FAR_BRANCH:1;
+    UINT32  Reserved1:23;
+    UINT32  Reserved2:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_PHI_LBR_SELECT_REGISTER;
+
+/**
+  Thread. Last Branch Record Stack TOS (R/W).
+
+  @param  ECX  MSR_XEON_PHI_LASTBRANCH_TOS (0x000001C9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS);
+  AsmWriteMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS, Msr);
+  @endcode
+  @note MSR_XEON_PHI_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
+**/
+#define MSR_XEON_PHI_LASTBRANCH_TOS              0x000001C9
+
+
+/**
+  Thread. Last Exception Record From Linear IP (R).
+
+  @param  ECX  MSR_XEON_PHI_LER_FROM_LIP (0x000001DD)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_FROM_LIP);
+  @endcode
+  @note MSR_XEON_PHI_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
+**/
+#define MSR_XEON_PHI_LER_FROM_LIP                0x000001DD
+
+
+/**
+  Thread. Last Exception Record To Linear IP (R).
+
+  @param  ECX  MSR_XEON_PHI_LER_TO_LIP (0x000001DE)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_TO_LIP);
+  @endcode
+  @note MSR_XEON_PHI_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
+**/
+#define MSR_XEON_PHI_LER_TO_LIP                  0x000001DE
+
+
+/**
+  Thread. See Table 2-2.
+
+  @param  ECX  MSR_XEON_PHI_PEBS_ENABLE (0x000003F1)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_PHI_PEBS_ENABLE);
+  AsmWriteMsr64 (MSR_XEON_PHI_PEBS_ENABLE, Msr);
+  @endcode
+  @note MSR_XEON_PHI_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
+**/
+#define MSR_XEON_PHI_PEBS_ENABLE                 0x000003F1
+
+
+/**
+  Package. Note: C-state values are processor specific C-state code names,
+  unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C3
+  Residency Counter. (R/O).
+
+  @param  ECX  MSR_XEON_PHI_PKG_C3_RESIDENCY (0x000003F8)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY);
+  AsmWriteMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY, Msr);
+  @endcode
+  @note MSR_XEON_PHI_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.
+**/
+#define MSR_XEON_PHI_PKG_C3_RESIDENCY            0x000003F8
+
+
+/**
+  Package. Package C6 Residency Counter. (R/O).
+
+  @param  ECX  MSR_XEON_PHI_PKG_C6_RESIDENCY (0x000003F9)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY);
+  AsmWriteMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY, Msr);
+  @endcode
+  @note MSR_XEON_PHI_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
+**/
+#define MSR_XEON_PHI_PKG_C6_RESIDENCY            0x000003F9
+
+
+/**
+  Package. Package C7 Residency Counter. (R/O).
+
+  @param  ECX  MSR_XEON_PHI_PKG_C7_RESIDENCY (0x000003FA)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY);
+  AsmWriteMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY, Msr);
+  @endcode
+  @note MSR_XEON_PHI_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.
+**/
+#define MSR_XEON_PHI_PKG_C7_RESIDENCY            0x000003FA
+
+
+/**
+  Module. Note: C-state values are processor specific C-state code names,
+  unrelated to MWAIT extension C-state parameters or ACPI C-States. Module C0
+  Residency Counter. (R/O).
+
+  @param  ECX  MSR_XEON_PHI_MC0_RESIDENCY (0x000003FC)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_PHI_MC0_RESIDENCY);
+  AsmWriteMsr64 (MSR_XEON_PHI_MC0_RESIDENCY, Msr);
+  @endcode
+  @note MSR_XEON_PHI_MC0_RESIDENCY is defined as MSR_MC0_RESIDENCY in SDM.
+**/
+#define MSR_XEON_PHI_MC0_RESIDENCY               0x000003FC
+
+
+/**
+  Module. Module C6 Residency Counter. (R/O).
+
+  @param  ECX  MSR_XEON_PHI_MC6_RESIDENCY (0x000003FD)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_PHI_MC6_RESIDENCY);
+  AsmWriteMsr64 (MSR_XEON_PHI_MC6_RESIDENCY, Msr);
+  @endcode
+  @note MSR_XEON_PHI_MC6_RESIDENCY is defined as MSR_MC6_RESIDENCY in SDM.
+**/
+#define MSR_XEON_PHI_MC6_RESIDENCY               0x000003FD
+
+
+/**
+  Core. Note: C-state values are processor specific C-state code names,
+  unrelated to MWAIT extension C-state parameters or ACPI C-States. CORE C6
+  Residency Counter. (R/O).
+
+  @param  ECX  MSR_XEON_PHI_CORE_C6_RESIDENCY (0x000003FF)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY);
+  AsmWriteMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY, Msr);
+  @endcode
+  @note MSR_XEON_PHI_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.
+**/
+#define MSR_XEON_PHI_CORE_C6_RESIDENCY           0x000003FF
+
+
+/**
+  Core. Capability Reporting Register of EPT and VPID (R/O)  See Table 2-2.
+
+  @param  ECX  MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM (0x0000048C)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM);
+  @endcode
+  @note MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.
+**/
+#define MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM      0x0000048C
+
+
+/**
+  Core. Capability Reporting Register of VM-Function Controls (R/O) See Table
+  2-2.
+
+  @param  ECX  MSR_XEON_PHI_IA32_VMX_FMFUNC (0x00000491)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_FMFUNC);
+  @endcode
+  @note MSR_XEON_PHI_IA32_VMX_FMFUNC is defined as IA32_VMX_FMFUNC in SDM.
+**/
+#define MSR_XEON_PHI_IA32_VMX_FMFUNC             0x00000491
+
+
+/**
+  Package. Unit Multipliers used in RAPL Interfaces (R/O).
+
+  @param  ECX  MSR_XEON_PHI_RAPL_POWER_UNIT (0x00000606)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_RAPL_POWER_UNIT);
+  @endcode
+  @note MSR_XEON_PHI_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.
+**/
+#define MSR_XEON_PHI_RAPL_POWER_UNIT             0x00000606
+
+/**
+  MSR information returned for MSR index #MSR_XEON_PHI_RAPL_POWER_UNIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".
+    ///
+    UINT32  PowerUnits:4;
+    UINT32  Reserved1:4;
+    ///
+    /// [Bits 12:8] Package. Energy Status Units Energy related information
+    /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an
+    /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61
+    /// micro-joules).
+    ///
+    UINT32  EnergyStatusUnits:5;
+    UINT32  Reserved2:3;
+    ///
+    /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL
+    /// Interfaces.".
+    ///
+    UINT32  TimeUnits:4;
+    UINT32  Reserved3:12;
+    UINT32  Reserved4:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER;
+
+
+/**
+  Package. Note: C-state values are processor specific C-state code names,
+  unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C2
+  Residency Counter. (R/O).
+
+  @param  ECX  MSR_XEON_PHI_PKG_C2_RESIDENCY (0x0000060D)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY);
+  AsmWriteMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY, Msr);
+  @endcode
+  @note MSR_XEON_PHI_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.
+**/
+#define MSR_XEON_PHI_PKG_C2_RESIDENCY            0x0000060D
+
+
+/**
+  Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package
+  RAPL Domain.".
+
+  @param  ECX  MSR_XEON_PHI_PKG_POWER_LIMIT (0x00000610)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT);
+  AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT, Msr);
+  @endcode
+  @note MSR_XEON_PHI_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.
+**/
+#define MSR_XEON_PHI_PKG_POWER_LIMIT             0x00000610
+
+
+/**
+  Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
+
+  @param  ECX  MSR_XEON_PHI_PKG_ENERGY_STATUS (0x00000611)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_ENERGY_STATUS);
+  @endcode
+  @note MSR_XEON_PHI_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.
+**/
+#define MSR_XEON_PHI_PKG_ENERGY_STATUS           0x00000611
+
+
+/**
+  Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".
+
+  @param  ECX  MSR_XEON_PHI_PKG_PERF_STATUS (0x00000613)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_PERF_STATUS);
+  @endcode
+  @note MSR_XEON_PHI_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.
+**/
+#define MSR_XEON_PHI_PKG_PERF_STATUS             0x00000613
+
+
+/**
+  Package. PKG RAPL Parameters (R/W) See Section 14.9.3, "Package RAPL
+  Domain.".
+
+  @param  ECX  MSR_XEON_PHI_PKG_POWER_INFO (0x00000614)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_INFO);
+  AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_INFO, Msr);
+  @endcode
+  @note MSR_XEON_PHI_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.
+**/
+#define MSR_XEON_PHI_PKG_POWER_INFO              0x00000614
+
+
+/**
+  Package. DRAM RAPL Power Limit Control (R/W)  See Section 14.9.5, "DRAM RAPL
+  Domain.".
+
+  @param  ECX  MSR_XEON_PHI_DRAM_POWER_LIMIT (0x00000618)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT);
+  AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT, Msr);
+  @endcode
+  @note MSR_XEON_PHI_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.
+**/
+#define MSR_XEON_PHI_DRAM_POWER_LIMIT            0x00000618
+
+
+/**
+  Package. DRAM Energy Status (R/O)  See Section 14.9.5, "DRAM RAPL Domain.".
+
+  @param  ECX  MSR_XEON_PHI_DRAM_ENERGY_STATUS (0x00000619)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_ENERGY_STATUS);
+  @endcode
+  @note MSR_XEON_PHI_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.
+**/
+#define MSR_XEON_PHI_DRAM_ENERGY_STATUS          0x00000619
+
+
+/**
+  Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM
+  RAPL Domain.".
+
+  @param  ECX  MSR_XEON_PHI_DRAM_PERF_STATUS (0x0000061B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_PERF_STATUS);
+  @endcode
+  @note MSR_XEON_PHI_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.
+**/
+#define MSR_XEON_PHI_DRAM_PERF_STATUS            0x0000061B
+
+
+/**
+  Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".
+
+  @param  ECX  MSR_XEON_PHI_DRAM_POWER_INFO (0x0000061C)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO);
+  AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO, Msr);
+  @endcode
+  @note MSR_XEON_PHI_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.
+**/
+#define MSR_XEON_PHI_DRAM_POWER_INFO             0x0000061C
+
+
+/**
+  Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio
+  fields represent the widest possible range of uncore frequencies. Writing to
+  these fields allows software to control the minimum and the maximum
+  frequency that hardware will select.
+
+  @param  ECX  MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT (0x00000620)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT);
+  AsmWriteMsr64 (MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);
+  @endcode
+**/
+#define MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT       0x00000620
+
+/**
+  MSR information returned for MSR index #MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the
+    /// LLC/Ring.
+    ///
+    UINT32  MAX_RATIO:7;
+    UINT32  Reserved1:1;
+    ///
+    /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum
+    /// possible ratio of the LLC/Ring.
+    ///
+    UINT32  MIN_RATIO:7;
+    UINT32  Reserved2:17;
+    UINT32  Reserved3:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER;
+
+
+/**
+  Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1
+  RAPL Domains.".
+
+  @param  ECX  MSR_XEON_PHI_PP0_POWER_LIMIT (0x00000638)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT);
+  AsmWriteMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT, Msr);
+  @endcode
+  @note MSR_XEON_PHI_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.
+**/
+#define MSR_XEON_PHI_PP0_POWER_LIMIT             0x00000638
+
+
+/**
+  Package. PP0 Energy Status (R/O)  See Section 14.9.4, "PP0/PP1 RAPL
+  Domains.".
+
+  @param  ECX  MSR_XEON_PHI_PP0_ENERGY_STATUS (0x00000639)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_ENERGY_STATUS);
+  @endcode
+  @note MSR_XEON_PHI_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.
+**/
+#define MSR_XEON_PHI_PP0_ENERGY_STATUS           0x00000639
+
+
+/**
+  Package. Base TDP Ratio (R/O) See Table 2-24.
+
+  @param  ECX  MSR_XEON_PHI_CONFIG_TDP_NOMINAL (0x00000648)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_NOMINAL);
+  @endcode
+  @note MSR_XEON_PHI_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.
+**/
+#define MSR_XEON_PHI_CONFIG_TDP_NOMINAL          0x00000648
+
+
+/**
+  Package. ConfigTDP Level 1 ratio and power level (R/O) See Table 2-24.
+
+  @param  ECX  MSR_XEON_PHI_CONFIG_TDP_LEVEL1 (0x00000649)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL1);
+  @endcode
+  @note MSR_XEON_PHI_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.
+**/
+#define MSR_XEON_PHI_CONFIG_TDP_LEVEL1           0x00000649
+
+
+/**
+  Package. ConfigTDP Level 2 ratio and power level (R/O) See Table 2-24.
+
+  @param  ECX  MSR_XEON_PHI_CONFIG_TDP_LEVEL2 (0x0000064A)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL2);
+  @endcode
+  @note MSR_XEON_PHI_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.
+**/
+#define MSR_XEON_PHI_CONFIG_TDP_LEVEL2           0x0000064A
+
+
+/**
+  Package. ConfigTDP Control (R/W) See Table 2-24.
+
+  @param  ECX  MSR_XEON_PHI_CONFIG_TDP_CONTROL (0x0000064B)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL);
+  AsmWriteMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL, Msr);
+  @endcode
+  @note MSR_XEON_PHI_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.
+**/
+#define MSR_XEON_PHI_CONFIG_TDP_CONTROL          0x0000064B
+
+
+/**
+  Package. ConfigTDP Control (R/W) See Table 2-24.
+
+  @param  ECX  MSR_XEON_PHI_TURBO_ACTIVATION_RATIO (0x0000064C)
+  @param  EAX  Lower 32-bits of MSR value.
+  @param  EDX  Upper 32-bits of MSR value.
+
+  <b>Example usage</b>
+  @code
+  UINT64  Msr;
+
+  Msr = AsmReadMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO);
+  AsmWriteMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO, Msr);
+  @endcode
+  @note MSR_XEON_PHI_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.
+**/
+#define MSR_XEON_PHI_TURBO_ACTIVATION_RATIO      0x0000064C
+
+
+/**
+  Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency
+  refers to processor core frequency).
+
+  @param  ECX  MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS (0x00000690)
+  @param  EAX  Lower 32-bits of MSR value.
+               Described by the type MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER.
+  @param  EDX  Upper 32-bits of MSR value.
+               Described by the type MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER.
+
+  <b>Example usage</b>
+  @code
+  MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER  Msr;
+
+  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS);
+  AsmWriteMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS, Msr.Uint64);
+  @endcode
+  @note MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.
+**/
+#define MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS     0x00000690
+
+/**
+  MSR information returned for MSR index #MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] PROCHOT Status (R0).
+    ///
+    UINT32  PROCHOT_Status:1;
+    ///
+    /// [Bit 1] Thermal Status (R0).
+    ///
+    UINT32  ThermalStatus:1;
+    UINT32  Reserved1:4;
+    ///
+    /// [Bit 6] VR Therm Alert Status (R0).
+    ///
+    UINT32  VRThermAlertStatus:1;
+    UINT32  Reserved2:1;
+    ///
+    /// [Bit 8] Electrical Design Point Status (R0).
+    ///
+    UINT32  ElectricalDesignPointStatus:1;
+    UINT32  Reserved3:23;
+    UINT32  Reserved4:32;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32  Uint32;
+  ///
+  /// All bit fields as a 64-bit value
+  ///
+  UINT64  Uint64;
+} MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER;
+
+#endif
diff --git a/MdePkg/Include/Register/Intel/SmramSaveStateMap.h b/MdePkg/Include/Register/Intel/SmramSaveStateMap.h
new file mode 100644
index 000000000000..ecdfca8fd4ab
--- /dev/null
+++ b/MdePkg/Include/Register/Intel/SmramSaveStateMap.h
@@ -0,0 +1,184 @@
+/** @file
+SMRAM Save State Map Definitions.
+
+SMRAM Save State Map definitions based on contents of the
+Intel(R) 64 and IA-32 Architectures Software Developer's Manual
+  Volume 3C, Section 34.4 SMRAM
+  Volume 3C, Section 34.5 SMI Handler Execution Environment
+  Volume 3C, Section 34.7 Managing Synchronous and Asynchronous SMIs
+
+Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __INTEL_SMRAM_SAVE_STATE_MAP_H__
+#define __INTEL_SMRAM_SAVE_STATE_MAP_H__
+
+///
+/// Default SMBASE address
+///
+#define SMM_DEFAULT_SMBASE           0x30000
+
+///
+/// Offset of SMM handler from SMBASE
+///
+#define SMM_HANDLER_OFFSET           0x8000
+
+///
+/// Offset of SMRAM Save State Map from SMBASE
+///
+#define SMRAM_SAVE_STATE_MAP_OFFSET  0xfc00
+
+#pragma pack (1)
+
+///
+/// 32-bit SMRAM Save State Map
+///
+typedef struct {
+  UINT8   Reserved[0x200];  // 7c00h
+                            // Padded an extra 0x200 bytes so 32-bit and 64-bit
+                            // SMRAM Save State Maps are the same size
+  UINT8   Reserved1[0xf8];  // 7e00h
+  UINT32  SMBASE;           // 7ef8h
+  UINT32  SMMRevId;         // 7efch
+  UINT16  IORestart;        // 7f00h
+  UINT16  AutoHALTRestart;  // 7f02h
+  UINT8   Reserved2[0x9C];  // 7f08h
+  UINT32  IOMemAddr;        // 7fa0h
+  UINT32  IOMisc;           // 7fa4h
+  UINT32  _ES;              // 7fa8h
+  UINT32  _CS;              // 7fach
+  UINT32  _SS;              // 7fb0h
+  UINT32  _DS;              // 7fb4h
+  UINT32  _FS;              // 7fb8h
+  UINT32  _GS;              // 7fbch
+  UINT32  Reserved3;        // 7fc0h
+  UINT32  _TR;              // 7fc4h
+  UINT32  _DR7;             // 7fc8h
+  UINT32  _DR6;             // 7fcch
+  UINT32  _EAX;             // 7fd0h
+  UINT32  _ECX;             // 7fd4h
+  UINT32  _EDX;             // 7fd8h
+  UINT32  _EBX;             // 7fdch
+  UINT32  _ESP;             // 7fe0h
+  UINT32  _EBP;             // 7fe4h
+  UINT32  _ESI;             // 7fe8h
+  UINT32  _EDI;             // 7fech
+  UINT32  _EIP;             // 7ff0h
+  UINT32  _EFLAGS;          // 7ff4h
+  UINT32  _CR3;             // 7ff8h
+  UINT32  _CR0;             // 7ffch
+} SMRAM_SAVE_STATE_MAP32;
+
+///
+/// 64-bit SMRAM Save State Map
+///
+typedef struct {
+  UINT8   Reserved1[0x1d0];  // 7c00h
+  UINT32  GdtBaseHiDword;    // 7dd0h
+  UINT32  LdtBaseHiDword;    // 7dd4h
+  UINT32  IdtBaseHiDword;    // 7dd8h
+  UINT8   Reserved2[0xc];    // 7ddch
+  UINT64  IO_EIP;            // 7de8h
+  UINT8   Reserved3[0x50];   // 7df0h
+  UINT32  _CR4;              // 7e40h
+  UINT8   Reserved4[0x48];   // 7e44h
+  UINT32  GdtBaseLoDword;    // 7e8ch
+  UINT32  Reserved5;         // 7e90h
+  UINT32  IdtBaseLoDword;    // 7e94h
+  UINT32  Reserved6;         // 7e98h
+  UINT32  LdtBaseLoDword;    // 7e9ch
+  UINT8   Reserved7[0x38];   // 7ea0h
+  UINT64  EptVmxControl;     // 7ed8h
+  UINT32  EnEptVmxControl;   // 7ee0h
+  UINT8   Reserved8[0x14];   // 7ee4h
+  UINT32  SMBASE;            // 7ef8h
+  UINT32  SMMRevId;          // 7efch
+  UINT16  IORestart;         // 7f00h
+  UINT16  AutoHALTRestart;   // 7f02h
+  UINT8   Reserved9[0x18];   // 7f04h
+  UINT64  _R15;              // 7f1ch
+  UINT64  _R14;
+  UINT64  _R13;
+  UINT64  _R12;
+  UINT64  _R11;
+  UINT64  _R10;
+  UINT64  _R9;
+  UINT64  _R8;
+  UINT64  _RAX;              // 7f5ch
+  UINT64  _RCX;
+  UINT64  _RDX;
+  UINT64  _RBX;
+  UINT64  _RSP;
+  UINT64  _RBP;
+  UINT64  _RSI;
+  UINT64  _RDI;
+  UINT64  IOMemAddr;         // 7f9ch
+  UINT32  IOMisc;            // 7fa4h
+  UINT32  _ES;               // 7fa8h
+  UINT32  _CS;
+  UINT32  _SS;
+  UINT32  _DS;
+  UINT32  _FS;
+  UINT32  _GS;
+  UINT32  _LDTR;             // 7fc0h
+  UINT32  _TR;
+  UINT64  _DR7;              // 7fc8h
+  UINT64  _DR6;
+  UINT64  _RIP;              // 7fd8h
+  UINT64  IA32_EFER;         // 7fe0h
+  UINT64  _RFLAGS;           // 7fe8h
+  UINT64  _CR3;              // 7ff0h
+  UINT64  _CR0;              // 7ff8h
+} SMRAM_SAVE_STATE_MAP64;
+
+///
+/// Union of 32-bit and 64-bit SMRAM Save State Maps
+///
+typedef union  {
+  SMRAM_SAVE_STATE_MAP32  x86;
+  SMRAM_SAVE_STATE_MAP64  x64;
+} SMRAM_SAVE_STATE_MAP;
+
+///
+/// Minimum SMM Revision ID that supports IOMisc field in SMRAM Save State Map
+///
+#define SMRAM_SAVE_STATE_MIN_REV_ID_IOMISC  0x30004
+
+///
+/// SMRAM Save State Map IOMisc I/O Length Values
+///
+#define  SMM_IO_LENGTH_BYTE             0x01
+#define  SMM_IO_LENGTH_WORD             0x02
+#define  SMM_IO_LENGTH_DWORD            0x04
+
+///
+/// SMRAM Save State Map IOMisc I/O Instruction Type Values
+///
+#define  SMM_IO_TYPE_IN_IMMEDIATE       0x9
+#define  SMM_IO_TYPE_IN_DX              0x1
+#define  SMM_IO_TYPE_OUT_IMMEDIATE      0x8
+#define  SMM_IO_TYPE_OUT_DX             0x0
+#define  SMM_IO_TYPE_INS                0x3
+#define  SMM_IO_TYPE_OUTS               0x2
+#define  SMM_IO_TYPE_REP_INS            0x7
+#define  SMM_IO_TYPE_REP_OUTS           0x6
+
+///
+/// SMRAM Save State Map IOMisc structure
+///
+typedef union {
+  struct {
+    UINT32  SmiFlag:1;
+    UINT32  Length:3;
+    UINT32  Type:4;
+    UINT32  Reserved1:8;
+    UINT32  Port:16;
+  } Bits;
+  UINT32  Uint32;
+} SMRAM_SAVE_STATE_IOMISC;
+
+#pragma pack ()
+
+#endif
diff --git a/MdePkg/Include/Register/Intel/StmApi.h b/MdePkg/Include/Register/Intel/StmApi.h
new file mode 100644
index 000000000000..15d66aaf7a13
--- /dev/null
+++ b/MdePkg/Include/Register/Intel/StmApi.h
@@ -0,0 +1,948 @@
+/** @file
+  STM API definition
+
+  Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  SMI Transfer Monitor (STM) User Guide Revision 1.00
+
+**/
+
+#ifndef _INTEL_STM_API_H_
+#define _INTEL_STM_API_H_
+
+#include <Register/Intel/StmStatusCode.h>
+#include <Register/Intel/StmResourceDescriptor.h>
+#include <Register/Intel/ArchitecturalMsr.h>
+
+#pragma pack (1)
+
+/**
+  STM Header Structures
+**/
+
+typedef struct {
+  UINT32  Intel64ModeSupported :1;  ///> bitfield
+  UINT32  EptSupported         :1;  ///> bitfield
+  UINT32  Reserved             :30; ///> must be 0
+} STM_FEAT;
+
+#define STM_SPEC_VERSION_MAJOR  1
+#define STM_SPEC_VERSION_MINOR  0
+
+typedef struct {
+  UINT8     StmSpecVerMajor;
+  UINT8     StmSpecVerMinor;
+  ///
+  /// Must be zero
+  ///
+  UINT16    Reserved;
+  UINT32    StaticImageSize;
+  UINT32    PerProcDynamicMemorySize;
+  UINT32    AdditionalDynamicMemorySize;
+  STM_FEAT  StmFeatures;
+  UINT32    NumberOfRevIDs;
+  UINT32    StmSmmRevID[1];
+  ///
+  /// The total STM_HEADER should be 4K.
+  ///
+} SOFTWARE_STM_HEADER;
+
+typedef struct {
+  MSEG_HEADER          HwStmHdr;
+  SOFTWARE_STM_HEADER  SwStmHdr;
+} STM_HEADER;
+
+
+/**
+  VMCALL API Numbers
+  API number convention: BIOS facing VMCALL interfaces have bit 16 clear
+**/
+
+/**
+  StmMapAddressRange enables a SMM guest to create a non-1:1 virtual to
+  physical mapping of an address range into the SMM guest's virtual
+  memory space.
+
+  @param  EAX  #STM_API_MAP_ADDRESS_RANGE (0x00000001)
+  @param  EBX  Low 32 bits of physical address of caller allocated
+               STM_MAP_ADDRESS_RANGE_DESCRIPTOR structure.
+  @param  ECX  High 32 bits of physical address of caller allocated
+               STM_MAP_ADDRESS_RANGE_DESCRIPTOR structure. If Intel64Mode is
+               clear (0), ECX must be 0.
+
+  @note  All fields of STM_MAP_ADDRESS_RANGE_DESCRIPTOR are inputs only. They
+         are not modified by StmMapAddressRange.
+
+  @retval  CF   0
+                No error, EAX set to STM_SUCCESS.
+                The memory range was mapped as requested.
+  @retval  CF   1
+                An error occurred, EAX holds relevant error value.
+  @retval  EAX  #ERROR_STM_SECURITY_VIOLATION
+                The requested mapping contains a protected resource.
+  @retval  EAX  #ERROR_STM_CACHE_TYPE_NOT_SUPPORTED
+                The requested cache type could not be satisfied.
+  @retval  EAX  #ERROR_STM_PAGE_NOT_FOUND
+                Page count must not be zero.
+  @retval  EAX  #ERROR_STM_FUNCTION_NOT_SUPPORTED
+                STM supports EPT and has not implemented StmMapAddressRange().
+  @retval  EAX  #ERROR_STM_UNSPECIFIED
+                An unspecified error occurred.
+
+  @note  All other registers unmodified.
+**/
+#define STM_API_MAP_ADDRESS_RANGE                  0x00000001
+
+/**
+  STM Map Address Range Descriptor for #STM_API_MAP_ADDRESS_RANGE VMCALL
+**/
+typedef struct {
+  UINT64  PhysicalAddress;
+  UINT64  VirtualAddress;
+  UINT32  PageCount;
+  UINT32  PatCacheType;
+} STM_MAP_ADDRESS_RANGE_DESCRIPTOR;
+
+/**
+  Define values for PatCacheType field of #STM_MAP_ADDRESS_RANGE_DESCRIPTOR
+  @{
+**/
+#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_ST_UC        0x00
+#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_WC           0x01
+#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_WT           0x04
+#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_WP           0x05
+#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_WB           0x06
+#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_UC           0x07
+#define STM_MAP_ADDRESS_RANGE_PAT_CACHE_TYPE_FOLLOW_MTRR  0xFFFFFFFF
+/// @}
+
+/**
+  StmUnmapAddressRange enables a SMM guest to remove mappings from its page
+  table.
+
+  If TXT_PROCESSOR_SMM_DESCRIPTOR.EptEnabled bit is set by the STM, BIOS can
+  control its own page tables. In this case, the STM implementation may
+  optionally return ERROR_STM_FUNCTION_NOT_SUPPORTED.
+
+  @param  EAX  #STM_API_UNMAP_ADDRESS_RANGE (0x00000002)
+  @param  EBX  Low 32 bits of virtual address of caller allocated
+               STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR structure.
+  @param  ECX  High 32 bits of virtual address of caller allocated
+               STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR structure. If Intel64Mode is
+               clear (0), ECX must be zero.
+
+  @retval  CF   0
+                No error, EAX set to STM_SUCCESS. The memory range was unmapped
+                as requested.
+  @retval  CF   1
+                An error occurred, EAX holds relevant error value.
+  @retval  EAX  #ERROR_STM_FUNCTION_NOT_SUPPORTED
+                STM supports EPT and has not implemented StmUnmapAddressRange().
+  @retval  EAX  #ERROR_STM_UNSPECIFIED
+                An unspecified error occurred.
+
+  @note  All other registers unmodified.
+**/
+#define STM_API_UNMAP_ADDRESS_RANGE                0x00000002
+
+/**
+  STM Unmap Address Range Descriptor for #STM_API_UNMAP_ADDRESS_RANGE VMCALL
+**/
+typedef struct {
+  UINT64  VirtualAddress;
+  UINT32  Length;
+} STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR;
+
+
+/**
+  Since the normal OS environment runs with a different set of page tables than
+  the SMM guest, virtual mappings will certainly be different. In order to do a
+  guest virtual to host physical translation of an address from the normal OS
+  code (EIP for example), it is necessary to walk the page tables governing the
+  OS page mappings. Since the SMM guest has no direct access to the page tables,
+  it must ask the STM to do this page table walk. This is supported via the
+  StmAddressLookup VMCALL. All OS page table formats need to be supported,
+  (e.g. PAE, PSE, Intel64, EPT, etc.)
+
+  StmAddressLookup takes a CR3 value and a virtual address from the interrupted
+  code as input and returns the corresponding physical address. It also
+  optionally maps the physical address into the SMM guest's virtual address
+  space. This new mapping persists ONLY for the duration of the SMI and if
+  needed in subsequent SMIs it must be remapped. PAT cache types follow the
+  interrupted environment's page table.
+
+  If EPT is enabled, OS CR3 only provides guest physical address information,
+  but the SMM guest might also need to know the host physical address. Since
+  SMM does not have direct access rights to EPT (it is protected by the STM),
+  SMM can input InterruptedEptp to let STM help to walk through it, and output
+  the host physical address.
+
+  @param  EAX  #STM_API_ADDRESS_LOOKUP (0x00000003)
+  @param  EBX  Low 32 bits of virtual address of caller allocated
+               STM_ADDRESS_LOOKUP_DESCRIPTOR structure.
+  @param  ECX  High 32 bits of virtual address of caller allocated
+               STM_ADDRESS_LOOKUP_DESCRIPTOR structure. If Intel64Mode is
+               clear (0), ECX must be zero.
+
+  @retval  CF   0
+                No error, EAX set to STM_SUCCESS.  PhysicalAddress contains the
+                host physical address determined by walking the interrupted SMM
+                guest's page tables.  SmmGuestVirtualAddress contains the SMM
+                guest's virtual mapping of the requested address.
+  @retval  CF   1
+                An error occurred, EAX holds relevant error value.
+  @retval  EAX  #ERROR_STM_SECURITY_VIOLATION
+                The requested page was a protected page.
+  @retval  EAX  #ERROR_STM_PAGE_NOT_FOUND
+                The requested virtual address did not exist in the page given
+                page table.
+  @retval  EAX  #ERROR_STM_BAD_CR3
+                The CR3 input was invalid. CR3 values must be from one of the
+                interrupted guest, or from the interrupted guest of another
+                processor.
+  @retval  EAX  #ERROR_STM_PHYSICAL_OVER_4G
+                The resulting physical address is greater than 4G and no virtual
+                address was supplied. The STM could not determine what address
+                within the SMM guest's virtual address space to do the mapping.
+                STM_ADDRESS_LOOKUP_DESCRIPTOR field PhysicalAddress contains the
+                physical address determined by walking the interrupted
+                environment's page tables.
+  @retval  EAX  #ERROR_STM_VIRTUAL_SPACE_TOO_SMALL
+                A specific virtual mapping was requested, but
+                SmmGuestVirtualAddress + Length exceeds 4G and the SMI handler
+                is running in 32 bit mode.
+  @retval  EAX  #ERROR_STM_UNSPECIFIED
+                An unspecified error occurred.
+
+  @note  All other registers unmodified.
+**/
+#define STM_API_ADDRESS_LOOKUP                     0x00000003
+
+/**
+  STM Lookup Address Range Descriptor for #STM_API_ADDRESS_LOOKUP VMCALL
+**/
+typedef struct {
+  UINT64  InterruptedGuestVirtualAddress;
+  UINT32  Length;
+  UINT64  InterruptedCr3;
+  UINT64  InterruptedEptp;
+  UINT32  MapToSmmGuest:2;
+  UINT32  InterruptedCr4Pae:1;
+  UINT32  InterruptedCr4Pse:1;
+  UINT32  InterruptedIa32eMode:1;
+  UINT32  Reserved1:27;
+  UINT32  Reserved2;
+  UINT64  PhysicalAddress;
+  UINT64  SmmGuestVirtualAddress;
+} STM_ADDRESS_LOOKUP_DESCRIPTOR;
+
+/**
+  Define values for the MapToSmmGuest field of #STM_ADDRESS_LOOKUP_DESCRIPTOR
+  @{
+**/
+#define STM_ADDRESS_LOOKUP_DESCRIPTOR_DO_NOT_MAP                 0
+#define STM_ADDRESS_LOOKUP_DESCRIPTOR_ONE_TO_ONE                 1
+#define STM_ADDRESS_LOOKUP_DESCRIPTOR_VIRTUAL_ADDRESS_SPECIFIED  3
+/// @}
+
+
+/**
+  When returning from a protection exception (see section 6.2), the SMM guest
+  can instruct the STM to take one of two paths. It can either request a value
+  be logged to the TXT.ERRORCODE register and subsequently reset the machine
+  (indicating it couldn't resolve the problem), or it can request that the STM
+  resume the SMM guest again with the specified register state.
+
+  Unlike other VMCALL interfaces, StmReturnFromProtectionException behaves more
+  like a jump or an IRET instruction than a "call". It does not return directly
+  to the caller, but indirectly to a different location specified on the
+  caller's stack (see section 6.2) or not at all.
+
+  If the SMM guest STM protection exception handler itself causes a protection
+  exception (e.g. a single nested exception), or more than 100 un-nested
+  exceptions occur within the scope of a single SMI event, the STM must write
+  STM_CRASH_PROTECTION_EXCEPTION_FAILURE to the TXT.ERRORCODE register and
+  assert TXT.CMD.SYS_RESET. The reason for these restrictions is to simplify
+  the code requirements while still enabling a reasonable debugging capability.
+
+  @param  EAX  #STM_API_RETURN_FROM_PROTECTION_EXCEPTION (0x00000004)
+  @param  EBX  If 0, resume SMM guest using register state found on exception
+               stack.  If in range 0x01..0x0F, EBX contains a BIOS error code
+               which the STM must record in the TXT.ERRORCODE register and
+               subsequently reset the system via TXT.CMD.SYS_RESET. The value
+               of the TXT.ERRORCODE register is calculated as follows:
+
+                 TXT.ERRORCODE = (EBX & 0x0F) | STM_CRASH_BIOS_PANIC
+
+               Values 0x10..0xFFFFFFFF are reserved, do not use.
+
+**/
+#define STM_API_RETURN_FROM_PROTECTION_EXCEPTION   0x00000004
+
+
+/**
+  VMCALL API Numbers
+  API number convention: MLE facing VMCALL interfaces have bit 16 set.
+
+  The STM configuration lifecycle is as follows:
+    1. SENTER->SINIT->MLE: MLE begins execution with SMI disabled (masked).
+    2. MLE invokes #STM_API_INITIALIZE_PROTECTION VMCALL to prepare STM for
+       setup of initial protection profile. This is done on a single CPU and
+       has global effect.
+    3. MLE invokes #STM_API_PROTECT_RESOURCE VMCALL to define the initial
+       protection profile. The protection profile is global across all CPUs.
+    4. MLE invokes #STM_API_START VMCALL to enable the STM to begin receiving
+       SMI events. This must be done on every logical CPU.
+    5. MLE may invoke #STM_API_PROTECT_RESOURCE VMCALL or
+       #STM_API_UNPROTECT_RESOURCE VMCALL during runtime as many times as
+       necessary.
+    6. MLE invokes #STM_API_STOP VMCALL to disable the STM. SMI is again masked
+       following #STM_API_STOP VMCALL.
+**/
+
+/**
+  StartStmVmcall() is used to configure an STM that is present in MSEG. SMIs
+  should remain disabled from the invocation of GETSEC[SENTER] until they are
+  re-enabled by StartStmVMCALL(). When StartStmVMCALL() returns, SMI is
+  enabled and the STM has been started and is active. Prior to invoking
+  StartStmVMCALL(), the MLE root should first invoke
+  InitializeProtectionVMCALL() followed by as many iterations of
+  ProtectResourceVMCALL() as necessary to establish the initial protection
+  profile.  StartStmVmcall() must be invoked on all processor threads.
+
+  @param  EAX  #STM_API_START (0x00010001)
+  @param  EDX  STM configuration options. These provide the MLE with the
+               ability to pass configuration parameters to the STM.
+
+  @retval  CF   0
+                No error, EAX set to STM_SUCCESS. The STM has been configured
+                and is now active and the guarding all requested resources.
+  @retval  CF   1
+                An error occurred, EAX holds relevant error value.
+  @retval  EAX  #ERROR_STM_ALREADY_STARTED
+                The STM is already configured and active. STM remains active and
+                guarding previously enabled resource list.
+  @retval  EAX  #ERROR_STM_WITHOUT_SMX_UNSUPPORTED
+                The StartStmVMCALL() was invoked from VMX root mode, but outside
+                of SMX. This error code indicates the STM or platform does not
+                support the STM outside of SMX. The SMI handler remains active
+                and operates in legacy mode. See Appendix C
+  @retval  EAX  #ERROR_STM_UNSUPPORTED_MSR_BIT
+                The CPU doesn't support the MSR bit. The STM is not active.
+  @retval  EAX  #ERROR_STM_UNSPECIFIED
+                An unspecified error occurred.
+
+  @note  All other registers unmodified.
+**/
+#define STM_API_START                              (BIT16 | 1)
+
+/**
+  Bit values for EDX input parameter to #STM_API_START VMCALL
+  @{
+**/
+#define STM_CONFIG_SMI_UNBLOCKING_BY_VMX_OFF  BIT0
+/// @}
+
+
+/**
+  The StopStmVMCALL() is invoked by the MLE to teardown an active STM. This is
+  normally done as part of a full teardown of the SMX environment when the
+  system is being shut down. At the time the call is invoked, SMI is enabled
+  and the STM is active.  When the call returns, the STM has been stopped and
+  all STM context is discarded and SMI is disabled.
+
+  @param  EAX  #STM_API_STOP (0x00010002)
+
+  @retval  CF   0
+                No error, EAX set to STM_SUCCESS. The STM has been stopped and
+                is no longer processing SMI events. SMI is blocked.
+  @retval  CF   1
+                An error occurred, EAX holds relevant error value.
+  @retval  EAX  #ERROR_STM_STOPPED
+                The STM was not active.
+  @retval  EAX  #ERROR_STM_UNSPECIFIED
+                An unspecified error occurred.
+
+  @note  All other registers unmodified.
+**/
+#define STM_API_STOP                               (BIT16 | 2)
+
+
+/**
+  The ProtectResourceVMCALL() is invoked by the MLE root to request protection
+  of specific resources. The request is defined by a STM_RESOURCE_LIST, which
+  may contain more than one resource descriptor. Each resource descriptor is
+  processed separately by the STM. Whether or not protection for any specific
+  resource is granted is returned by the STM via the ReturnStatus bit in the
+  associated STM_RSC_DESC_HEADER.
+
+  @param  EAX  #STM_API_PROTECT_RESOURCE (0x00010003)
+  @param  EBX  Low 32 bits of physical address of caller allocated
+               STM_RESOURCE_LIST. Bits 11:0 are ignored and assumed to be zero,
+               making the buffer 4K aligned.
+  @param  ECX  High 32 bits of physical address of caller allocated
+               STM_RESOURCE_LIST.
+
+  @note  All fields of STM_RESOURCE_LIST are inputs only, except for the
+         ReturnStatus bit. On input, the ReturnStatus bit must be clear. On
+         return, the ReturnStatus bit is set for each resource request granted,
+         and clear for each resource request denied. There are no other fields
+         modified by ProtectResourceVMCALL(). The STM_RESOURCE_LIST must be
+         contained entirely within a single 4K page.
+
+  @retval  CF   0
+                No error, EAX set to STM_SUCCESS. The STM has successfully
+                merged the entire protection request into the active protection
+                profile.  There is therefore no need to check the ReturnStatus
+                bits in the STM_RESOURCE_LIST.
+  @retval  CF   1
+                An error occurred, EAX holds relevant error value.
+  @retval  EAX  #ERROR_STM_UNPROTECTABLE_RESOURCE
+                At least one of the requested resource protections intersects a
+                BIOS required resource. Therefore, the caller must walk through
+                the STM_RESOURCE_LIST to determine which of the requested
+                resources was not granted protection. The entire list must be
+                traversed since there may be multiple failures.
+  @retval  EAX  #ERROR_STM_MALFORMED_RESOURCE_LIST
+                The resource list could not be parsed correctly, or did not
+                terminate before crossing a 4K page boundary. The caller must
+                walk through the STM_RESOURCE_LIST to determine which of the
+                requested resources was not granted protection. The entire list
+                must be traversed since there may be multiple failures.
+  @retval  EAX  #ERROR_STM_OUT_OF_RESOURCES
+                The STM has encountered an internal error and cannot complete
+                the request.
+  @retval  EAX  #ERROR_STM_UNSPECIFIED
+                An unspecified error occurred.
+
+  @note  All other registers unmodified.
+**/
+#define STM_API_PROTECT_RESOURCE                   (BIT16 | 3)
+
+
+/**
+  The UnProtectResourceVMCALL() is invoked by the MLE root to request that the
+  STM allow the SMI handler access to the specified resources.
+
+  @param  EAX  #STM_API_UNPROTECT_RESOURCE (0x00010004)
+  @param  EBX  Low 32 bits of physical address of caller allocated
+               STM_RESOURCE_LIST. Bits 11:0 are ignored and assumed to be zero,
+               making the buffer 4K aligned.
+  @param  ECX  High 32 bits of physical address of caller allocated
+               STM_RESOURCE_LIST.
+
+  @note  All fields of STM_RESOURCE_LIST are inputs only, except for the
+         ReturnStatus bit. On input, the ReturnStatus bit must be clear. On
+         return, the ReturnStatus bit is set for each resource processed. For
+         a properly formed STM_RESOURCE_LIST, this should be all resources
+         listed. There are no other fields modified by
+         UnProtectResourceVMCALL(). The STM_RESOURCE_LIST must be contained
+         entirely within a single 4K page.
+
+  @retval  CF   0
+                No error, EAX set to STM_SUCCESS. The requested resources are
+                not being guarded by the STM.
+  @retval  CF   1
+                An error occurred, EAX holds relevant error value.
+  @retval  EAX  #ERROR_STM_MALFORMED_RESOURCE_LIST
+                The resource list could not be parsed correctly, or did not
+                terminate before crossing a 4K page boundary. The caller must
+                walk through the STM_RESOURCE_LIST to determine which of the
+                requested resources were not able to be unprotected. The entire
+                list must be traversed since there may be multiple failures.
+  @retval  EAX  #ERROR_STM_UNSPECIFIED
+                An unspecified error occurred.
+
+  @note  All other registers unmodified.
+**/
+#define STM_API_UNPROTECT_RESOURCE                 (BIT16 | 4)
+
+
+/**
+  The GetBiosResourcesVMCALL() is invoked by the MLE root to request the list
+  of BIOS required resources from the STM.
+
+  @param  EAX  #STM_API_GET_BIOS_RESOURCES (0x00010005)
+  @param  EBX  Low 32 bits of physical address of caller allocated destination
+               buffer. Bits 11:0 are ignored and assumed to be zero, making the
+               buffer 4K aligned.
+  @param  ECX  High 32 bits of physical address of caller allocated destination
+               buffer.
+  @param  EDX  Indicates which page of the BIOS resource list to copy into the
+               destination buffer. The first page is indicated by 0, the second
+               page by 1, etc.
+
+  @retval  CF   0
+                No error, EAX set to STM_SUCCESS. The destination buffer
+                contains the BIOS required resources. If the page retrieved is
+                the last page, EDX will be cleared to 0. If there are more pages
+                to retrieve, EDX is incremented to the next page index. Calling
+                software should iterate on GetBiosResourcesVMCALL() until EDX is
+                returned cleared to 0.
+  @retval  CF   1
+                An error occurred, EAX holds relevant error value.
+  @retval  EAX  #ERROR_STM_PAGE_NOT_FOUND
+                The page index supplied in EDX input was out of range.
+  @retval  EAX  #ERROR_STM_UNSPECIFIED
+                An unspecified error occurred.
+  @retval  EDX  Page index of next page to read. A return of EDX=0 signifies
+                that the entire list has been read.
+                @note  EDX is both an input and an output register.
+
+  @note  All other registers unmodified.
+**/
+#define STM_API_GET_BIOS_RESOURCES                 (BIT16 | 5)
+
+
+/**
+  The ManageVmcsDatabaseVMCALL() is invoked by the MLE root to add or remove an
+  MLE guest (including the MLE root) from the list of protected domains.
+
+  @param  EAX  #STM_API_MANAGE_VMCS_DATABASE (0x00010006)
+  @param  EBX  Low 32 bits of physical address of caller allocated
+               STM_VMCS_DATABASE_REQUEST. Bits 11:0 are ignored and assumed to
+               be zero, making the buffer 4K aligned.
+  @param  ECX  High 32 bits of physical address of caller allocated
+               STM_VMCS_DATABASE_REQUEST.
+
+  @note  All fields of STM_VMCS_DATABASE_REQUEST are inputs only.  They are not
+         modified by ManageVmcsDatabaseVMCALL().
+
+  @retval  CF   0
+                No error, EAX set to STM_SUCCESS.
+  @retval  CF   1
+                An error occurred, EAX holds relevant error value.
+  @retval  EAX  #ERROR_STM_INVALID_VMCS
+                Indicates a request to remove a VMCS from the database was made,
+                but the referenced VMCS was not found in the database.
+  @retval  EAX  #ERROR_STM_VMCS_PRESENT
+                Indicates a request to add a VMCS to the database was made, but
+                the referenced VMCS was already present in the database.
+  @retval  EAX  #ERROR_INVALID_PARAMETER
+                Indicates non-zero reserved field.
+  @retval  EAX  #ERROR_STM_UNSPECIFIED
+                An unspecified error occurred
+
+  @note  All other registers unmodified.
+**/
+#define STM_API_MANAGE_VMCS_DATABASE               (BIT16 | 6)
+
+/**
+  STM VMCS Database Request for #STM_API_MANAGE_VMCS_DATABASE VMCALL
+**/
+typedef struct {
+  ///
+  /// bits 11:0 are reserved and must be 0
+  ///
+  UINT64  VmcsPhysPointer;
+  UINT32  DomainType :4;
+  UINT32  XStatePolicy :2;
+  UINT32  DegradationPolicy :4;
+  ///
+  /// Must be 0
+  ///
+  UINT32  Reserved1 :22;
+  UINT32  AddOrRemove;
+} STM_VMCS_DATABASE_REQUEST;
+
+/**
+  Values for the DomainType field of #STM_VMCS_DATABASE_REQUEST
+  @{
+**/
+#define DOMAIN_UNPROTECTED            0
+#define DOMAIN_DISALLOWED_IO_OUT      BIT0
+#define DOMAIN_DISALLOWED_IO_IN       BIT1
+#define DOMAIN_INTEGRITY              BIT2
+#define DOMAIN_CONFIDENTIALITY        BIT3
+#define DOMAIN_INTEGRITY_PROT_OUT_IN  (DOMAIN_INTEGRITY)
+#define DOMAIN_FULLY_PROT_OUT_IN      (DOMAIN_CONFIDENTIALITY | DOMAIN_INTEGRITY)
+#define DOMAIN_FULLY_PROT             (DOMAIN_FULLY_PROT_OUT_IN | DOMAIN_DISALLOWED_IO_IN | DOMAIN_DISALLOWED_IO_OUT)
+/// @}
+
+/**
+  Values for the XStatePolicy field of #STM_VMCS_DATABASE_REQUEST
+  @{
+**/
+#define XSTATE_READWRITE  0x00
+#define XSTATE_READONLY   0x01
+#define XSTATE_SCRUB      0x03
+/// @}
+
+/**
+  Values for the AddOrRemove field of #STM_VMCS_DATABASE_REQUEST
+  @{
+**/
+#define STM_VMCS_DATABASE_REQUEST_ADD     1
+#define STM_VMCS_DATABASE_REQUEST_REMOVE  0
+/// @}
+
+
+/**
+  InitializeProtectionVMCALL() prepares the STM for setup of the initial
+  protection profile which is subsequently communicated via one or more
+  invocations of ProtectResourceVMCALL(), prior to invoking StartStmVMCALL().
+  It is only necessary to invoke InitializeProtectionVMCALL() on one processor
+  thread.  InitializeProtectionVMCALL() does not alter whether SMIs are masked
+  or unmasked. The STM should return back to the MLE with "Blocking by SMI" set
+  to 1 in the GUEST_INTERRUPTIBILITY field for the VMCS the STM created for the
+  MLE guest.
+
+  @param  EAX  #STM_API_INITIALIZE_PROTECTION (0x00010007)
+
+  @retval  CF   0
+                No error, EAX set to STM_SUCCESS, EBX bits set to indicate STM
+                capabilities as defined below. The STM has set up an empty
+                protection profile, except for the resources that it sets up to
+                protect itself. The STM must not allow the SMI handler to map
+                any pages from the MSEG Base to the top of TSEG. The STM must
+                also not allow SMI handler access to those MSRs which the STM
+                requires for its own protection.
+  @retval  CF   1
+                An error occurred, EAX holds relevant error value.
+  @retval  EAX  #ERROR_STM_ALREADY_STARTED
+                The STM is already configured and active. The STM remains active
+                and guarding the previously enabled resource list.
+  @retval  EAX  #ERROR_STM_UNPROTECTABLE
+                The STM determines that based on the platform configuration, the
+                STM is unable to protect itself. For example, the BIOS required
+                resource list contains memory pages in MSEG.
+  @retval  EAX  #ERROR_STM_UNSPECIFIED
+                An unspecified error occurred.
+
+  @note  All other registers unmodified.
+**/
+#define STM_API_INITIALIZE_PROTECTION              (BIT16 | 7)
+
+/**
+  Byte granular support bits returned in EBX from #STM_API_INITIALIZE_PROTECTION
+  @{
+**/
+#define STM_RSC_BGI  BIT1
+#define STM_RSC_BGM  BIT2
+#define STM_RSC_MSR  BIT3
+/// @}
+
+
+/**
+  The ManageEventLogVMCALL() is invoked by the MLE root to control the logging
+  feature. It consists of several sub-functions to facilitate establishment of
+  the log itself, configuring what events will be logged, and functions to
+  start, stop, and clear the log.
+
+  @param  EAX  #STM_API_MANAGE_EVENT_LOG (0x00010008)
+  @param  EBX  Low 32 bits of physical address of caller allocated
+               STM_EVENT_LOG_MANAGEMENT_REQUEST. Bits 11:0 are ignored and
+               assumed to be zero, making the buffer 4K aligned.
+  @param  ECX  High 32 bits of physical address of caller allocated
+               STM_EVENT_LOG_MANAGEMENT_REQUEST.
+
+  @retval  CF=0
+           No error, EAX set to STM_SUCCESS.
+  @retval  CF=1
+           An error occurred, EAX holds relevant error value. See subfunction
+           descriptions below for details.
+
+  @note  All other registers unmodified.
+**/
+#define STM_API_MANAGE_EVENT_LOG                   (BIT16 | 8)
+
+///
+/// STM Event Log Management Request for #STM_API_MANAGE_EVENT_LOG VMCALL
+///
+typedef struct {
+  UINT32      SubFunctionIndex;
+  union {
+    struct {
+      UINT32  PageCount;
+      //
+      // number of elements is PageCount
+      //
+      UINT64  Pages[];
+    } LogBuffer;
+    //
+    // bitmap of EVENT_TYPE
+    //
+    UINT32    EventEnableBitmap;
+  } Data;
+} STM_EVENT_LOG_MANAGEMENT_REQUEST;
+
+/**
+  Defines values for the SubFunctionIndex field of
+  #STM_EVENT_LOG_MANAGEMENT_REQUEST
+  @{
+**/
+#define STM_EVENT_LOG_MANAGEMENT_REQUEST_NEW_LOG        1
+#define STM_EVENT_LOG_MANAGEMENT_REQUEST_CONFIGURE_LOG  2
+#define STM_EVENT_LOG_MANAGEMENT_REQUEST_START_LOG      3
+#define STM_EVENT_LOG_MANAGEMENT_REQUEST_STOP_LOG       4
+#define STM_EVENT_LOG_MANAGEMENT_REQUEST_CLEAR_LOG      5
+#define STM_EVENT_LOG_MANAGEMENT_REQUEST_DELETE_LOG     6
+/// @}
+
+/**
+  Log Entry Header
+**/
+typedef struct {
+  UINT32  EventSerialNumber;
+  UINT16  Type;
+  UINT16  Lock :1;
+  UINT16  Valid :1;
+  UINT16  ReadByMle :1;
+  UINT16  Wrapped :1;
+  UINT16  Reserved :12;
+} LOG_ENTRY_HEADER;
+
+/**
+  Enum values for the Type field of #LOG_ENTRY_HEADER
+**/
+typedef enum {
+  EvtLogStarted,
+  EvtLogStopped,
+  EvtLogInvalidParameterDetected,
+  EvtHandledProtectionException,
+  ///
+  /// unhandled protection exceptions result in reset & cannot be logged
+  ///
+  EvtBiosAccessToUnclaimedResource,
+  EvtMleResourceProtectionGranted,
+  EvtMleResourceProtectionDenied,
+  EvtMleResourceUnprotect,
+  EvtMleResourceUnprotectError,
+  EvtMleDomainTypeDegraded,
+  ///
+  /// add more here
+  ///
+  EvtMleMax,
+  ///
+  /// Not used
+  ///
+  EvtInvalid = 0xFFFFFFFF,
+} EVENT_TYPE;
+
+typedef struct {
+  UINT32  Reserved;
+} ENTRY_EVT_LOG_STARTED;
+
+typedef struct {
+  UINT32  Reserved;
+} ENTRY_EVT_LOG_STOPPED;
+
+typedef struct {
+  UINT32  VmcallApiNumber;
+} ENTRY_EVT_LOG_INVALID_PARAM;
+
+typedef struct {
+  STM_RSC  Resource;
+} ENTRY_EVT_LOG_HANDLED_PROTECTION_EXCEPTION;
+
+typedef struct {
+  STM_RSC  Resource;
+} ENTRY_EVT_BIOS_ACCESS_UNCLAIMED_RSC;
+
+typedef struct {
+  STM_RSC  Resource;
+} ENTRY_EVT_MLE_RSC_PROT_GRANTED;
+
+typedef struct {
+  STM_RSC  Resource;
+} ENTRY_EVT_MLE_RSC_PROT_DENIED;
+
+typedef struct {
+  STM_RSC  Resource;
+} ENTRY_EVT_MLE_RSC_UNPROT;
+
+typedef struct {
+  STM_RSC  Resource;
+} ENTRY_EVT_MLE_RSC_UNPROT_ERROR;
+
+typedef struct {
+  UINT64  VmcsPhysPointer;
+  UINT8   ExpectedDomainType;
+  UINT8   DegradedDomainType;
+} ENTRY_EVT_MLE_DOMAIN_TYPE_DEGRADED;
+
+typedef union {
+  ENTRY_EVT_LOG_STARTED                       Started;
+  ENTRY_EVT_LOG_STOPPED                       Stopped;
+  ENTRY_EVT_LOG_INVALID_PARAM                 InvalidParam;
+  ENTRY_EVT_LOG_HANDLED_PROTECTION_EXCEPTION  HandledProtectionException;
+  ENTRY_EVT_BIOS_ACCESS_UNCLAIMED_RSC         BiosUnclaimedRsc;
+  ENTRY_EVT_MLE_RSC_PROT_GRANTED              MleRscProtGranted;
+  ENTRY_EVT_MLE_RSC_PROT_DENIED               MleRscProtDenied;
+  ENTRY_EVT_MLE_RSC_UNPROT                    MleRscUnprot;
+  ENTRY_EVT_MLE_RSC_UNPROT_ERROR              MleRscUnprotError;
+  ENTRY_EVT_MLE_DOMAIN_TYPE_DEGRADED          MleDomainTypeDegraded;
+} LOG_ENTRY_DATA;
+
+typedef struct {
+  LOG_ENTRY_HEADER  Hdr;
+  LOG_ENTRY_DATA    Data;
+} STM_LOG_ENTRY;
+
+/**
+  Maximum STM Log Entry Size
+**/
+#define STM_LOG_ENTRY_SIZE  256
+
+
+/**
+  STM Protection Exception Stack Frame Structures
+**/
+
+typedef struct {
+  UINT32  Rdi;
+  UINT32  Rsi;
+  UINT32  Rbp;
+  UINT32  Rdx;
+  UINT32  Rcx;
+  UINT32  Rbx;
+  UINT32  Rax;
+  UINT32  Cr3;
+  UINT32  Cr2;
+  UINT32  Cr0;
+  UINT32  VmcsExitInstructionInfo;
+  UINT32  VmcsExitInstructionLength;
+  UINT64  VmcsExitQualification;
+  ///
+  /// An TXT_SMM_PROTECTION_EXCEPTION_TYPE num value
+  ///
+  UINT32  ErrorCode;
+  UINT32  Rip;
+  UINT32  Cs;
+  UINT32  Rflags;
+  UINT32  Rsp;
+  UINT32  Ss;
+} STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32;
+
+typedef struct {
+  UINT64  R15;
+  UINT64  R14;
+  UINT64  R13;
+  UINT64  R12;
+  UINT64  R11;
+  UINT64  R10;
+  UINT64  R9;
+  UINT64  R8;
+  UINT64  Rdi;
+  UINT64  Rsi;
+  UINT64  Rbp;
+  UINT64  Rdx;
+  UINT64  Rcx;
+  UINT64  Rbx;
+  UINT64  Rax;
+  UINT64  Cr8;
+  UINT64  Cr3;
+  UINT64  Cr2;
+  UINT64  Cr0;
+  UINT64  VmcsExitInstructionInfo;
+  UINT64  VmcsExitInstructionLength;
+  UINT64  VmcsExitQualification;
+  ///
+  /// An TXT_SMM_PROTECTION_EXCEPTION_TYPE num value
+  ///
+  UINT64  ErrorCode;
+  UINT64  Rip;
+  UINT64  Cs;
+  UINT64  Rflags;
+  UINT64  Rsp;
+  UINT64  Ss;
+} STM_PROTECTION_EXCEPTION_STACK_FRAME_X64;
+
+typedef union {
+  STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32  *Ia32StackFrame;
+  STM_PROTECTION_EXCEPTION_STACK_FRAME_X64   *X64StackFrame;
+} STM_PROTECTION_EXCEPTION_STACK_FRAME;
+
+/**
+  Enum values for the ErrorCode field in
+  #STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32 and
+  #STM_PROTECTION_EXCEPTION_STACK_FRAME_X64
+**/
+typedef enum {
+  TxtSmmPageViolation = 1,
+  TxtSmmMsrViolation,
+  TxtSmmRegisterViolation,
+  TxtSmmIoViolation,
+  TxtSmmPciViolation
+} TXT_SMM_PROTECTION_EXCEPTION_TYPE;
+
+/**
+  TXT Pocessor SMM Descriptor (PSD) structures
+**/
+
+typedef struct {
+  UINT64  SpeRip;
+  UINT64  SpeRsp;
+  UINT16  SpeSs;
+  UINT16  PageViolationException:1;
+  UINT16  MsrViolationException:1;
+  UINT16  RegisterViolationException:1;
+  UINT16  IoViolationException:1;
+  UINT16  PciViolationException:1;
+  UINT16  Reserved1:11;
+  UINT32  Reserved2;
+} STM_PROTECTION_EXCEPTION_HANDLER;
+
+typedef struct {
+  UINT8  ExecutionDisableOutsideSmrr:1;
+  UINT8  Intel64Mode:1;
+  UINT8  Cr4Pae : 1;
+  UINT8  Cr4Pse : 1;
+  UINT8  Reserved1 : 4;
+} STM_SMM_ENTRY_STATE;
+
+typedef struct {
+  UINT8  SmramToVmcsRestoreRequired : 1; ///> BIOS restore hint
+  UINT8  ReinitializeVmcsRequired : 1;   ///> BIOS request
+  UINT8  Reserved2 : 6;
+} STM_SMM_RESUME_STATE;
+
+typedef struct {
+  UINT8  DomainType : 4;   ///> STM input to BIOS on each SMI
+  UINT8  XStatePolicy : 2; ///> STM input to BIOS on each SMI
+  UINT8  EptEnabled : 1;
+  UINT8  Reserved3 : 1;
+} STM_SMM_STATE;
+
+#define TXT_SMM_PSD_OFFSET                          0xfb00
+#define TXT_PROCESSOR_SMM_DESCRIPTOR_SIGNATURE      SIGNATURE_64('T', 'X', 'T', 'P', 'S', 'S', 'I', 'G')
+#define TXT_PROCESSOR_SMM_DESCRIPTOR_VERSION_MAJOR  1
+#define TXT_PROCESSOR_SMM_DESCRIPTOR_VERSION_MINOR  0
+
+typedef struct {
+  UINT64                            Signature;
+  UINT16                            Size;
+  UINT8                             SmmDescriptorVerMajor;
+  UINT8                             SmmDescriptorVerMinor;
+  UINT32                            LocalApicId;
+  STM_SMM_ENTRY_STATE               SmmEntryState;
+  STM_SMM_RESUME_STATE              SmmResumeState;
+  STM_SMM_STATE                     StmSmmState;
+  UINT8                             Reserved4;
+  UINT16                            SmmCs;
+  UINT16                            SmmDs;
+  UINT16                            SmmSs;
+  UINT16                            SmmOtherSegment;
+  UINT16                            SmmTr;
+  UINT16                            Reserved5;
+  UINT64                            SmmCr3;
+  UINT64                            SmmStmSetupRip;
+  UINT64                            SmmStmTeardownRip;
+  UINT64                            SmmSmiHandlerRip;
+  UINT64                            SmmSmiHandlerRsp;
+  UINT64                            SmmGdtPtr;
+  UINT32                            SmmGdtSize;
+  UINT32                            RequiredStmSmmRevId;
+  STM_PROTECTION_EXCEPTION_HANDLER  StmProtectionExceptionHandler;
+  UINT64                            Reserved6;
+  UINT64                            BiosHwResourceRequirementsPtr;
+  // extend area
+  UINT64                            AcpiRsdp;
+  UINT8                             PhysicalAddressBits;
+} TXT_PROCESSOR_SMM_DESCRIPTOR;
+
+#pragma pack ()
+
+#endif
diff --git a/MdePkg/Include/Register/Intel/StmResourceDescriptor.h b/MdePkg/Include/Register/Intel/StmResourceDescriptor.h
new file mode 100644
index 000000000000..3f9e2b8aacac
--- /dev/null
+++ b/MdePkg/Include/Register/Intel/StmResourceDescriptor.h
@@ -0,0 +1,222 @@
+/** @file
+  STM Resource Descriptor
+
+  Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  SMI Transfer Monitor (STM) User Guide Revision 1.00
+
+**/
+
+#ifndef _INTEL_STM_RESOURCE_DESCRIPTOR_H_
+#define _INTEL_STM_RESOURCE_DESCRIPTOR_H_
+
+#pragma pack (1)
+
+/**
+  STM Resource Descriptor Header
+**/
+typedef struct {
+  UINT32  RscType;
+  UINT16  Length;
+  UINT16  ReturnStatus:1;
+  UINT16  Reserved:14;
+  UINT16  IgnoreResource:1;
+} STM_RSC_DESC_HEADER;
+
+/**
+  Define values for the RscType field of #STM_RSC_DESC_HEADER
+  @{
+**/
+#define END_OF_RESOURCES      0
+#define MEM_RANGE             1
+#define IO_RANGE              2
+#define MMIO_RANGE            3
+#define MACHINE_SPECIFIC_REG  4
+#define PCI_CFG_RANGE         5
+#define TRAPPED_IO_RANGE      6
+#define ALL_RESOURCES         7
+#define REGISTER_VIOLATION    8
+#define MAX_DESC_TYPE         8
+/// @}
+
+/**
+  STM Resource End Descriptor
+**/
+typedef struct {
+  STM_RSC_DESC_HEADER  Hdr;
+  UINT64               ResourceListContinuation;
+} STM_RSC_END;
+
+/**
+  STM Resource Memory Descriptor
+**/
+typedef struct {
+  STM_RSC_DESC_HEADER  Hdr;
+  UINT64               Base;
+  UINT64               Length;
+  UINT32               RWXAttributes:3;
+  UINT32               Reserved:29;
+  UINT32               Reserved_2;
+} STM_RSC_MEM_DESC;
+
+/**
+  Define values for the RWXAttributes field of #STM_RSC_MEM_DESC
+  @{
+**/
+#define STM_RSC_MEM_R  0x1
+#define STM_RSC_MEM_W  0x2
+#define STM_RSC_MEM_X  0x4
+/// @}
+
+/**
+  STM Resource I/O Descriptor
+**/
+typedef struct {
+  STM_RSC_DESC_HEADER  Hdr;
+  UINT16               Base;
+  UINT16               Length;
+  UINT32               Reserved;
+} STM_RSC_IO_DESC;
+
+/**
+  STM Resource MMIO Descriptor
+**/
+typedef struct {
+  STM_RSC_DESC_HEADER  Hdr;
+  UINT64               Base;
+  UINT64               Length;
+  UINT32               RWXAttributes:3;
+  UINT32               Reserved:29;
+  UINT32               Reserved_2;
+} STM_RSC_MMIO_DESC;
+
+/**
+  Define values for the RWXAttributes field of #STM_RSC_MMIO_DESC
+  @{
+**/
+#define STM_RSC_MMIO_R  0x1
+#define STM_RSC_MMIO_W  0x2
+#define STM_RSC_MMIO_X  0x4
+/// @}
+
+/**
+  STM Resource MSR Descriptor
+**/
+typedef struct {
+  STM_RSC_DESC_HEADER  Hdr;
+  UINT32               MsrIndex;
+  UINT32               KernelModeProcessing:1;
+  UINT32               Reserved:31;
+  UINT64               ReadMask;
+  UINT64               WriteMask;
+} STM_RSC_MSR_DESC;
+
+/**
+  STM PCI Device Path node used for the PciDevicePath field of
+  #STM_RSC_PCI_CFG_DESC
+**/
+typedef struct {
+  ///
+  /// Must be 1, indicating Hardware Device Path
+  ///
+  UINT8   Type;
+  ///
+  /// Must be 1, indicating PCI
+  ///
+  UINT8   Subtype;
+  ///
+  /// sizeof(STM_PCI_DEVICE_PATH_NODE) which is 6
+  ///
+  UINT16  Length;
+  UINT8   PciFunction;
+  UINT8   PciDevice;
+} STM_PCI_DEVICE_PATH_NODE;
+
+/**
+  STM Resource PCI Configuration Descriptor
+**/
+typedef struct {
+  STM_RSC_DESC_HEADER       Hdr;
+  UINT16                    RWAttributes:2;
+  UINT16                    Reserved:14;
+  UINT16                    Base;
+  UINT16                    Length;
+  UINT8                     OriginatingBusNumber;
+  UINT8                     LastNodeIndex;
+  STM_PCI_DEVICE_PATH_NODE  PciDevicePath[1];
+//STM_PCI_DEVICE_PATH_NODE  PciDevicePath[LastNodeIndex + 1];
+} STM_RSC_PCI_CFG_DESC;
+
+/**
+  Define values for the RWAttributes field of #STM_RSC_PCI_CFG_DESC
+  @{
+**/
+#define STM_RSC_PCI_CFG_R  0x1
+#define STM_RSC_PCI_CFG_W  0x2
+/// @}
+
+/**
+  STM Resource Trapped I/O Descriptor
+**/
+typedef struct {
+  STM_RSC_DESC_HEADER  Hdr;
+  UINT16               Base;
+  UINT16               Length;
+  UINT16               In:1;
+  UINT16               Out:1;
+  UINT16               Api:1;
+  UINT16               Reserved1:13;
+  UINT16               Reserved2;
+} STM_RSC_TRAPPED_IO_DESC;
+
+/**
+  STM Resource All Descriptor
+**/
+typedef struct {
+  STM_RSC_DESC_HEADER  Hdr;
+} STM_RSC_ALL_RESOURCES_DESC;
+
+/**
+  STM Register Violation Descriptor
+**/
+typedef struct {
+  STM_RSC_DESC_HEADER  Hdr;
+  UINT32               RegisterType;
+  UINT32               Reserved;
+  UINT64               ReadMask;
+  UINT64               WriteMask;
+} STM_REGISTER_VIOLATION_DESC;
+
+/**
+  Enum values for the RWAttributes field of #STM_REGISTER_VIOLATION_DESC
+**/
+typedef enum {
+  StmRegisterCr0,
+  StmRegisterCr2,
+  StmRegisterCr3,
+  StmRegisterCr4,
+  StmRegisterCr8,
+  StmRegisterMax,
+} STM_REGISTER_VIOLATION_TYPE;
+
+/**
+  Union of all STM resource types
+**/
+typedef union {
+  STM_RSC_DESC_HEADER          Header;
+  STM_RSC_END                  End;
+  STM_RSC_MEM_DESC             Mem;
+  STM_RSC_IO_DESC              Io;
+  STM_RSC_MMIO_DESC            Mmio;
+  STM_RSC_MSR_DESC             Msr;
+  STM_RSC_PCI_CFG_DESC         PciCfg;
+  STM_RSC_TRAPPED_IO_DESC      TrappedIo;
+  STM_RSC_ALL_RESOURCES_DESC   All;
+  STM_REGISTER_VIOLATION_DESC  RegisterViolation;
+} STM_RSC;
+
+#pragma pack ()
+
+#endif
diff --git a/MdePkg/Include/Register/Intel/StmStatusCode.h b/MdePkg/Include/Register/Intel/StmStatusCode.h
new file mode 100644
index 000000000000..7bac69dbcd67
--- /dev/null
+++ b/MdePkg/Include/Register/Intel/StmStatusCode.h
@@ -0,0 +1,72 @@
+/** @file
+  STM Status Codes
+
+  Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  SMI Transfer Monitor (STM) User Guide Revision 1.00
+
+**/
+
+#ifndef _INTEL_STM_STATUS_CODE_H_
+#define _INTEL_STM_STATUS_CODE_H_
+
+/**
+  STM Status Codes
+**/
+typedef UINT32  STM_STATUS;
+
+/**
+  Success code have BIT31 clear.
+  All error codes have BIT31 set.
+  STM errors have BIT16 set.
+  SMM errors have BIT17 set
+  Errors that apply to both STM and SMM have bits BIT15, BT16, and BIT17 set.
+  STM TXT.ERRORCODE codes have BIT30 set.
+  @{
+**/
+#define STM_SUCCESS                             0x00000000
+#define SMM_SUCCESS                             0x00000000
+#define ERROR_STM_SECURITY_VIOLATION            (BIT31 | BIT16 | 0x0001)
+#define ERROR_STM_CACHE_TYPE_NOT_SUPPORTED      (BIT31 | BIT16 | 0x0002)
+#define ERROR_STM_PAGE_NOT_FOUND                (BIT31 | BIT16 | 0x0003)
+#define ERROR_STM_BAD_CR3                       (BIT31 | BIT16 | 0x0004)
+#define ERROR_STM_PHYSICAL_OVER_4G              (BIT31 | BIT16 | 0x0005)
+#define ERROR_STM_VIRTUAL_SPACE_TOO_SMALL       (BIT31 | BIT16 | 0x0006)
+#define ERROR_STM_UNPROTECTABLE_RESOURCE        (BIT31 | BIT16 | 0x0007)
+#define ERROR_STM_ALREADY_STARTED               (BIT31 | BIT16 | 0x0008)
+#define ERROR_STM_WITHOUT_SMX_UNSUPPORTED       (BIT31 | BIT16 | 0x0009)
+#define ERROR_STM_STOPPED                       (BIT31 | BIT16 | 0x000A)
+#define ERROR_STM_BUFFER_TOO_SMALL              (BIT31 | BIT16 | 0x000B)
+#define ERROR_STM_INVALID_VMCS_DATABASE         (BIT31 | BIT16 | 0x000C)
+#define ERROR_STM_MALFORMED_RESOURCE_LIST       (BIT31 | BIT16 | 0x000D)
+#define ERROR_STM_INVALID_PAGECOUNT             (BIT31 | BIT16 | 0x000E)
+#define ERROR_STM_LOG_ALLOCATED                 (BIT31 | BIT16 | 0x000F)
+#define ERROR_STM_LOG_NOT_ALLOCATED             (BIT31 | BIT16 | 0x0010)
+#define ERROR_STM_LOG_NOT_STOPPED               (BIT31 | BIT16 | 0x0011)
+#define ERROR_STM_LOG_NOT_STARTED               (BIT31 | BIT16 | 0x0012)
+#define ERROR_STM_RESERVED_BIT_SET              (BIT31 | BIT16 | 0x0013)
+#define ERROR_STM_NO_EVENTS_ENABLED             (BIT31 | BIT16 | 0x0014)
+#define ERROR_STM_OUT_OF_RESOURCES              (BIT31 | BIT16 | 0x0015)
+#define ERROR_STM_FUNCTION_NOT_SUPPORTED        (BIT31 | BIT16 | 0x0016)
+#define ERROR_STM_UNPROTECTABLE                 (BIT31 | BIT16 | 0x0017)
+#define ERROR_STM_UNSUPPORTED_MSR_BIT           (BIT31 | BIT16 | 0x0018)
+#define ERROR_STM_UNSPECIFIED                   (BIT31 | BIT16 | 0xFFFF)
+#define ERROR_SMM_BAD_BUFFER                    (BIT31 | BIT17 | 0x0001)
+#define ERROR_SMM_INVALID_RSC                   (BIT31 | BIT17 | 0x0004)
+#define ERROR_SMM_INVALID_BUFFER_SIZE           (BIT31 | BIT17 | 0x0005)
+#define ERROR_SMM_BUFFER_TOO_SHORT              (BIT31 | BIT17 | 0x0006)
+#define ERROR_SMM_INVALID_LIST                  (BIT31 | BIT17 | 0x0007)
+#define ERROR_SMM_OUT_OF_MEMORY                 (BIT31 | BIT17 | 0x0008)
+#define ERROR_SMM_AFTER_INIT                    (BIT31 | BIT17 | 0x0009)
+#define ERROR_SMM_UNSPECIFIED                   (BIT31 | BIT17 | 0xFFFF)
+#define ERROR_INVALID_API                       (BIT31 | BIT17 | BIT16 | BIT15 | 0x0001)
+#define ERROR_INVALID_PARAMETER                 (BIT31 | BIT17 | BIT16 | BIT15 | 0x0002)
+#define STM_CRASH_PROTECTION_EXCEPTION          (BIT31 | BIT30 | 0xF001)
+#define STM_CRASH_PROTECTION_EXCEPTION_FAILURE  (BIT31 | BIT30 | 0xF002)
+#define STM_CRASH_DOMAIN_DEGRADATION_FAILURE    (BIT31 | BIT30 | 0xF003)
+#define STM_CRASH_BIOS_PANIC                    (BIT31 | BIT30 | 0xE000)
+/// @}
+
+#endif
diff --git a/MdePkg/Include/RiscV64/ProcessorBind.h b/MdePkg/Include/RiscV64/ProcessorBind.h
new file mode 100644
index 000000000000..84fce5ce3899
--- /dev/null
+++ b/MdePkg/Include/RiscV64/ProcessorBind.h
@@ -0,0 +1,173 @@
+/** @file
+  Processor or Compiler specific defines and types for RISC-V
+
+  Copyright (c) 2016 - 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef PROCESSOR_BIND_H__
+#define PROCESSOR_BIND_H__
+
+///
+/// Define the processor type so other code can make processor based choices
+///
+#define MDE_CPU_RISCV64
+
+//
+// Make sure we are using the correct packing rules per EFI specification
+//
+#if !defined(__GNUC__)
+#pragma pack()
+#endif
+
+///
+/// 8-byte unsigned value
+///
+typedef unsigned long long  UINT64  __attribute__ ((aligned (8)));
+///
+/// 8-byte signed value
+///
+typedef long long           INT64  __attribute__ ((aligned (8)));
+///
+/// 4-byte unsigned value
+///
+typedef unsigned int        UINT32 __attribute__ ((aligned (4)));
+///
+/// 4-byte signed value
+///
+typedef int                 INT32  __attribute__ ((aligned (4)));
+///
+/// 2-byte unsigned value
+///
+typedef unsigned short      UINT16  __attribute__ ((aligned (2)));
+///
+/// 2-byte Character.  Unless otherwise specified all strings are stored in the
+/// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.
+///
+typedef unsigned short      CHAR16  __attribute__ ((aligned (2)));
+///
+/// 2-byte signed value
+///
+typedef short               INT16  __attribute__ ((aligned (2)));
+///
+/// Logical Boolean.  1-byte value containing 0 for FALSE or a 1 for TRUE.  Other
+/// values are undefined.
+///
+typedef unsigned char       BOOLEAN;
+///
+/// 1-byte unsigned value
+///
+typedef unsigned char       UINT8;
+///
+/// 1-byte Character
+///
+typedef char                CHAR8;
+///
+/// 1-byte signed value
+///
+typedef signed char         INT8;
+///
+/// Unsigned value of native width.  (4 bytes on supported 32-bit processor instructions,
+/// 8 bytes on supported 64-bit processor instructions)
+///
+typedef UINT64  UINTN __attribute__ ((aligned (8)));
+///
+/// Signed value of native width.  (4 bytes on supported 32-bit processor instructions,
+/// 8 bytes on supported 64-bit processor instructions)
+///
+typedef INT64   INTN __attribute__ ((aligned (8)));
+
+//
+// Processor specific defines
+//
+
+///
+/// A value of native width with the highest bit set.
+///
+#define MAX_BIT     0x8000000000000000ULL
+///
+/// A value of native width with the two highest bits set.
+///
+#define MAX_2_BITS  0xC000000000000000ULL
+
+///
+/// Maximum legal RV64 address
+///
+#define MAX_ADDRESS   0xFFFFFFFFFFFFFFFFULL
+
+///
+/// Maximum usable address at boot time (48 bits using 4 KB pages in Supervisor mode)
+///
+#define MAX_ALLOC_ADDRESS   0xFFFFFFFFFFFFULL
+
+///
+/// Maximum legal RISC-V INTN and UINTN values.
+///
+#define MAX_INTN   ((INTN)0x7FFFFFFFFFFFFFFFULL)
+#define MAX_UINTN  ((UINTN)0xFFFFFFFFFFFFFFFFULL)
+
+///
+/// The stack alignment required for RISC-V
+///
+#define CPU_STACK_ALIGNMENT   16
+
+///
+/// Page allocation granularity for RISC-V
+///
+#define DEFAULT_PAGE_ALLOCATION_GRANULARITY   (0x1000)
+#define RUNTIME_PAGE_ALLOCATION_GRANULARITY   (0x1000)
+
+//
+// Modifier to ensure that all protocol member functions and EFI intrinsics
+// use the correct C calling convention. All protocol member functions and
+// EFI intrinsics are required to modify their member functions with EFIAPI.
+//
+#ifdef EFIAPI
+  ///
+  /// If EFIAPI is already defined, then we use that definition.
+  ///
+#elif defined(__GNUC__)
+  ///
+  /// Define the standard calling convention regardless of optimization level
+  /// The GCC support assumes a GCC compiler that supports the EFI ABI. The EFI
+  /// ABI is much closer to the x64 Microsoft* ABI than standard x64 (x86-64)
+  /// GCC ABI. Thus a standard x64 (x86-64) GCC compiler can not be used for
+  /// x64. Warning the assembly code in the MDE x64 does not follow the correct
+  /// ABI for the standard x64 (x86-64) GCC.
+  ///
+  #define EFIAPI
+#else
+  ///
+  /// The default for a non Microsoft* or GCC compiler is to assume the EFI ABI
+  /// is the standard.
+  ///
+  #define EFIAPI
+#endif
+
+#if defined(__GNUC__)
+  ///
+  /// For GNU assembly code, .global or .globl can declare global symbols.
+  /// Define this macro to unify the usage.
+  ///
+  #define ASM_GLOBAL .globl
+#endif
+
+/**
+  Return the pointer to the first instruction of a function given a function pointer.
+  On x64 CPU architectures, these two pointer values are the same,
+  so the implementation of this macro is very simple.
+
+  @param  FunctionPointer   A pointer to a function.
+
+  @return The pointer to the first instruction of a function given a function pointer.
+
+**/
+#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)
+
+#ifndef __USER_LABEL_PREFIX__
+#define __USER_LABEL_PREFIX__
+#endif
+
+#endif
diff --git a/MdePkg/Include/Uefi.h b/MdePkg/Include/Uefi.h
index 4b210131778f..dd0ece6103a2 100644
--- a/MdePkg/Include/Uefi.h
+++ b/MdePkg/Include/Uefi.h
@@ -2,18 +2,12 @@
 
   Root include file for Mde Package UEFI, UEFI_APPLICATION type modules.
 
-  This is the include file for any module of type UEFI and UEFI_APPLICATION. Uefi modules only use 
-  types defined via this include file and can be ported easily to any 
-  environment. 
-
-Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  This is the include file for any module of type UEFI and UEFI_APPLICATION. Uefi modules only use
+  types defined via this include file and can be ported easily to any
+  environment.
+
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
diff --git a/MdePkg/Include/Uefi/UefiAcpiDataTable.h b/MdePkg/Include/Uefi/UefiAcpiDataTable.h
index 92999de11c48..df0fc5561a90 100644
--- a/MdePkg/Include/Uefi/UefiAcpiDataTable.h
+++ b/MdePkg/Include/Uefi/UefiAcpiDataTable.h
@@ -1,14 +1,8 @@
 /** @file
   UEFI ACPI Data Table Definition.
 
-Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -23,37 +17,6 @@ typedef struct {
   GUID                          Identifier;
   UINT16                        DataOffset;
 } EFI_ACPI_DATA_TABLE;
-
-typedef struct {
-  EFI_ACPI_DATA_TABLE  UefiAcpiDataTable;
-  UINT32               SwSmiNumber;
-  UINT64               BufferPtrAddress;
-} EFI_SMM_COMMUNICATION_ACPI_TABLE;
-
-typedef struct {
-  EFI_SMM_COMMUNICATION_ACPI_TABLE        UefiSmmCommunicationAcpiTable;
-  EFI_ACPI_6_0_GENERIC_ADDRESS_STRUCTURE  InvocationRegister;
-} EFI_SMM_COMMUNICATION_ACPI_TABLE_2;
-
-///
-/// To avoid confusion in interpreting frames, the communication buffer should always 
-/// begin with EFI_SMM_COMMUNICATE_HEADER
-///
-typedef struct {
-  ///
-  /// Allows for disambiguation of the message format.
-  ///
-  EFI_GUID  HeaderGuid;
-  ///
-  /// Describes the size of Data (in bytes) and does not include the size of the header.
-  ///
-  UINTN     MessageLength;
-  ///
-  /// Designates an array of bytes that is MessageLength in size.
-  ///
-  UINT8     Data[1];
-} EFI_SMM_COMMUNICATE_HEADER;
-
 #pragma pack()
 
 #endif
diff --git a/MdePkg/Include/Uefi/UefiBaseType.h b/MdePkg/Include/Uefi/UefiBaseType.h
index 32b39c9fed17..6a2f33039377 100644
--- a/MdePkg/Include/Uefi/UefiBaseType.h
+++ b/MdePkg/Include/Uefi/UefiBaseType.h
@@ -1,16 +1,11 @@
 /** @file
   Defines data types and constants introduced in UEFI.
 
-Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
 Portions copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>
+Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
 
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -114,44 +109,44 @@ typedef union {
 
 ///
 /// Enumeration of EFI_STATUS.
-///@{ 
-#define EFI_SUCCESS               RETURN_SUCCESS              
-#define EFI_LOAD_ERROR            RETURN_LOAD_ERROR           
-#define EFI_INVALID_PARAMETER     RETURN_INVALID_PARAMETER    
-#define EFI_UNSUPPORTED           RETURN_UNSUPPORTED          
-#define EFI_BAD_BUFFER_SIZE       RETURN_BAD_BUFFER_SIZE      
-#define EFI_BUFFER_TOO_SMALL      RETURN_BUFFER_TOO_SMALL     
-#define EFI_NOT_READY             RETURN_NOT_READY            
-#define EFI_DEVICE_ERROR          RETURN_DEVICE_ERROR         
-#define EFI_WRITE_PROTECTED       RETURN_WRITE_PROTECTED      
-#define EFI_OUT_OF_RESOURCES      RETURN_OUT_OF_RESOURCES     
-#define EFI_VOLUME_CORRUPTED      RETURN_VOLUME_CORRUPTED     
-#define EFI_VOLUME_FULL           RETURN_VOLUME_FULL          
-#define EFI_NO_MEDIA              RETURN_NO_MEDIA             
-#define EFI_MEDIA_CHANGED         RETURN_MEDIA_CHANGED        
-#define EFI_NOT_FOUND             RETURN_NOT_FOUND            
-#define EFI_ACCESS_DENIED         RETURN_ACCESS_DENIED        
-#define EFI_NO_RESPONSE           RETURN_NO_RESPONSE          
-#define EFI_NO_MAPPING            RETURN_NO_MAPPING           
-#define EFI_TIMEOUT               RETURN_TIMEOUT              
-#define EFI_NOT_STARTED           RETURN_NOT_STARTED          
-#define EFI_ALREADY_STARTED       RETURN_ALREADY_STARTED      
-#define EFI_ABORTED               RETURN_ABORTED              
-#define EFI_ICMP_ERROR            RETURN_ICMP_ERROR           
-#define EFI_TFTP_ERROR            RETURN_TFTP_ERROR           
-#define EFI_PROTOCOL_ERROR        RETURN_PROTOCOL_ERROR       
-#define EFI_INCOMPATIBLE_VERSION  RETURN_INCOMPATIBLE_VERSION 
-#define EFI_SECURITY_VIOLATION    RETURN_SECURITY_VIOLATION   
-#define EFI_CRC_ERROR             RETURN_CRC_ERROR   
+///@{
+#define EFI_SUCCESS               RETURN_SUCCESS
+#define EFI_LOAD_ERROR            RETURN_LOAD_ERROR
+#define EFI_INVALID_PARAMETER     RETURN_INVALID_PARAMETER
+#define EFI_UNSUPPORTED           RETURN_UNSUPPORTED
+#define EFI_BAD_BUFFER_SIZE       RETURN_BAD_BUFFER_SIZE
+#define EFI_BUFFER_TOO_SMALL      RETURN_BUFFER_TOO_SMALL
+#define EFI_NOT_READY             RETURN_NOT_READY
+#define EFI_DEVICE_ERROR          RETURN_DEVICE_ERROR
+#define EFI_WRITE_PROTECTED       RETURN_WRITE_PROTECTED
+#define EFI_OUT_OF_RESOURCES      RETURN_OUT_OF_RESOURCES
+#define EFI_VOLUME_CORRUPTED      RETURN_VOLUME_CORRUPTED
+#define EFI_VOLUME_FULL           RETURN_VOLUME_FULL
+#define EFI_NO_MEDIA              RETURN_NO_MEDIA
+#define EFI_MEDIA_CHANGED         RETURN_MEDIA_CHANGED
+#define EFI_NOT_FOUND             RETURN_NOT_FOUND
+#define EFI_ACCESS_DENIED         RETURN_ACCESS_DENIED
+#define EFI_NO_RESPONSE           RETURN_NO_RESPONSE
+#define EFI_NO_MAPPING            RETURN_NO_MAPPING
+#define EFI_TIMEOUT               RETURN_TIMEOUT
+#define EFI_NOT_STARTED           RETURN_NOT_STARTED
+#define EFI_ALREADY_STARTED       RETURN_ALREADY_STARTED
+#define EFI_ABORTED               RETURN_ABORTED
+#define EFI_ICMP_ERROR            RETURN_ICMP_ERROR
+#define EFI_TFTP_ERROR            RETURN_TFTP_ERROR
+#define EFI_PROTOCOL_ERROR        RETURN_PROTOCOL_ERROR
+#define EFI_INCOMPATIBLE_VERSION  RETURN_INCOMPATIBLE_VERSION
+#define EFI_SECURITY_VIOLATION    RETURN_SECURITY_VIOLATION
+#define EFI_CRC_ERROR             RETURN_CRC_ERROR
 #define EFI_END_OF_MEDIA          RETURN_END_OF_MEDIA
 #define EFI_END_OF_FILE           RETURN_END_OF_FILE
 #define EFI_INVALID_LANGUAGE      RETURN_INVALID_LANGUAGE
 #define EFI_COMPROMISED_DATA      RETURN_COMPROMISED_DATA
 #define EFI_HTTP_ERROR            RETURN_HTTP_ERROR
 
-#define EFI_WARN_UNKNOWN_GLYPH    RETURN_WARN_UNKNOWN_GLYPH   
-#define EFI_WARN_DELETE_FAILURE   RETURN_WARN_DELETE_FAILURE  
-#define EFI_WARN_WRITE_FAILURE    RETURN_WARN_WRITE_FAILURE   
+#define EFI_WARN_UNKNOWN_GLYPH    RETURN_WARN_UNKNOWN_GLYPH
+#define EFI_WARN_DELETE_FAILURE   RETURN_WARN_DELETE_FAILURE
+#define EFI_WARN_WRITE_FAILURE    RETURN_WARN_WRITE_FAILURE
 #define EFI_WARN_BUFFER_TOO_SMALL RETURN_WARN_BUFFER_TOO_SMALL
 #define EFI_WARN_STALE_DATA       RETURN_WARN_STALE_DATA
 #define EFI_WARN_FILE_SYSTEM      RETURN_WARN_FILE_SYSTEM
@@ -159,7 +154,7 @@ typedef union {
 
 ///
 /// Define macro to encode the status code.
-/// 
+///
 #define EFIERR(_a)                ENCODE_ERROR(_a)
 
 #define EFI_ERROR(A)              RETURN_ERROR(A)
@@ -168,7 +163,7 @@ typedef union {
 /// ICMP error definitions
 ///@{
 #define EFI_NETWORK_UNREACHABLE   EFIERR(100)
-#define EFI_HOST_UNREACHABLE      EFIERR(101) 
+#define EFI_HOST_UNREACHABLE      EFIERR(101)
 #define EFI_PROTOCOL_UNREACHABLE  EFIERR(102)
 #define EFI_PORT_UNREACHABLE      EFIERR(103)
 ///@}
@@ -193,8 +188,8 @@ typedef union {
 /**
   Macro that converts a size, in bytes, to a number of EFI_PAGESs.
 
-  @param  Size      A size in bytes.  This parameter is assumed to be type UINTN.  
-                    Passing in a parameter that is larger than UINTN may produce 
+  @param  Size      A size in bytes.  This parameter is assumed to be type UINTN.
+                    Passing in a parameter that is larger than UINTN may produce
                     unexpected results.
 
   @return  The number of EFI_PAGESs associated with the number of bytes specified
@@ -206,13 +201,13 @@ typedef union {
 /**
   Macro that converts a number of EFI_PAGEs to a size in bytes.
 
-  @param  Pages     The number of EFI_PAGES.  This parameter is assumed to be 
-                    type UINTN.  Passing in a parameter that is larger than 
+  @param  Pages     The number of EFI_PAGES.  This parameter is assumed to be
+                    type UINTN.  Passing in a parameter that is larger than
                     UINTN may produce unexpected results.
 
-  @return  The number of bytes associated with the number of EFI_PAGEs specified 
+  @return  The number of bytes associated with the number of EFI_PAGEs specified
            by Pages.
-  
+
 **/
 #define EFI_PAGES_TO_SIZE(Pages)  ((Pages) << EFI_PAGE_SHIFT)
 
@@ -246,39 +241,43 @@ typedef union {
 ///
 #define EFI_IMAGE_MACHINE_AARCH64  0xAA64
 
+///
+/// PE32+ Machine type for RISC-V 32/64/128
+///
+#define EFI_IMAGE_MACHINE_RISCV32   0x5032
+#define EFI_IMAGE_MACHINE_RISCV64   0x5064
+#define EFI_IMAGE_MACHINE_RISCV128  0x5128
 
 #if   defined (MDE_CPU_IA32)
 
 #define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
-  (((Machine) == EFI_IMAGE_MACHINE_IA32) || ((Machine) == EFI_IMAGE_MACHINE_EBC))
-
-#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_X64) 
-
-#elif defined (MDE_CPU_IPF)
-
-#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
-  (((Machine) == EFI_IMAGE_MACHINE_IA64) || ((Machine) == EFI_IMAGE_MACHINE_EBC))
+  ((Machine) == EFI_IMAGE_MACHINE_IA32)
 
-#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE) 
+#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_X64)
 
 #elif defined (MDE_CPU_X64)
 
 #define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
-  (((Machine) == EFI_IMAGE_MACHINE_X64) || ((Machine) == EFI_IMAGE_MACHINE_EBC))
+  ((Machine) == EFI_IMAGE_MACHINE_X64)
 
-#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_IA32) 
+#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_IA32)
 
 #elif defined (MDE_CPU_ARM)
 
-#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
-  (((Machine) == EFI_IMAGE_MACHINE_ARMTHUMB_MIXED) || ((Machine) == EFI_IMAGE_MACHINE_EBC))
+#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_ARMTHUMB_MIXED)
 
-#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_ARMTHUMB_MIXED) 
+#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
 
 #elif defined (MDE_CPU_AARCH64)
 
 #define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
-  (((Machine) == EFI_IMAGE_MACHINE_AARCH64) || ((Machine) == EFI_IMAGE_MACHINE_EBC))
+  ((Machine) == EFI_IMAGE_MACHINE_AARCH64)
+
+#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
+
+#elif defined (MDE_CPU_RISCV64)
+#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
+  ((Machine) == EFI_IMAGE_MACHINE_RISCV64)
 
 #define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
 
@@ -286,11 +285,11 @@ typedef union {
 
 ///
 /// This is just to make sure you can cross compile with the EBC compiler.
-/// It does not make sense to have a PE loader coded in EBC. 
+/// It does not make sense to have a PE loader coded in EBC.
 ///
 #define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_EBC)
 
-#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE) 
+#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
 
 #else
 #error Unknown Processor Type
diff --git a/MdePkg/Include/Uefi/UefiGpt.h b/MdePkg/Include/Uefi/UefiGpt.h
index aa3c9bec0b5c..af0556131b00 100644
--- a/MdePkg/Include/Uefi/UefiGpt.h
+++ b/MdePkg/Include/Uefi/UefiGpt.h
@@ -1,14 +1,8 @@
 /** @file
   EFI Guid Partition Table Format Definition.
 
-Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -22,8 +16,12 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #define PRIMARY_PART_HEADER_LBA 1
 ///
 /// EFI Partition Table Signature: "EFI PART".
-/// 
+///
 #define EFI_PTAB_HEADER_ID      SIGNATURE_64 ('E','F','I',' ','P','A','R','T')
+///
+/// Minimum bytes reserve for EFI entry array buffer.
+///
+#define EFI_GPT_PART_ENTRY_MIN_SIZE 16384
 
 #pragma pack(1)
 
@@ -119,7 +117,7 @@ typedef struct {
   ///             this partition. By not producing an EFI_BLOCK_IO_PROTOCOL partition, file system
   ///             mappings will not be created for this partition in UEFI.
   /// Bit 2:      This bit is set aside to let systems with traditional PC-AT BIOS firmware implementations
-  ///             inform certain limited, special-purpose software running on these systems that a GPT 
+  ///             inform certain limited, special-purpose software running on these systems that a GPT
   ///             partition may be bootable. The UEFI boot manager must ignore this bit when selecting
   ///             a UEFI-compliant application, e.g., an OS loader.
   /// Bits 3-47:  Undefined and must be zero. Reserved for expansion by future versions of the UEFI
diff --git a/MdePkg/Include/Uefi/UefiInternalFormRepresentation.h b/MdePkg/Include/Uefi/UefiInternalFormRepresentation.h
index 389c12c1f040..0c7835c8e432 100644
--- a/MdePkg/Include/Uefi/UefiInternalFormRepresentation.h
+++ b/MdePkg/Include/Uefi/UefiInternalFormRepresentation.h
@@ -3,15 +3,9 @@
   IFR is primarily consumed by the EFI presentation engine, and produced by EFI
   internal application and drivers as well as all add-in card option-ROM drivers
 
-Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
 (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   These definitions are from UEFI 2.1 and 2.2.
@@ -67,7 +61,7 @@ typedef struct {
 
 //
 // Value of HII package type
-// 
+//
 #define EFI_HII_PACKAGE_TYPE_ALL             0x00
 #define EFI_HII_PACKAGE_TYPE_GUID            0x01
 #define EFI_HII_PACKAGE_FORMS                0x02
@@ -100,7 +94,7 @@ typedef struct {
 ///
 typedef struct {
   ///
-  /// The Unicode representation of the glyph. The term weight is the 
+  /// The Unicode representation of the glyph. The term weight is the
   /// technical term for a character code.
   ///
   CHAR16                 UnicodeWeight;
@@ -109,7 +103,7 @@ typedef struct {
   ///
   UINT8                  Attributes;
   ///
-  /// The column major glyph representation of the character. Bits 
+  /// The column major glyph representation of the character. Bits
   /// with values of one indicate that the corresponding pixel is to be
   /// on when normally displayed; those with zero are off.
   ///
@@ -117,12 +111,12 @@ typedef struct {
 } EFI_NARROW_GLYPH;
 
 ///
-/// The EFI_WIDE_GLYPH has a preferred dimension (w x h) of 16 x 19 pixels, which is large enough 
+/// The EFI_WIDE_GLYPH has a preferred dimension (w x h) of 16 x 19 pixels, which is large enough
 /// to accommodate logographic characters.
 ///
 typedef struct {
   ///
-  /// The Unicode representation of the glyph. The term weight is the 
+  /// The Unicode representation of the glyph. The term weight is the
   /// technical term for a character code.
   ///
   CHAR16                 UnicodeWeight;
@@ -131,20 +125,20 @@ typedef struct {
   ///
   UINT8                  Attributes;
   ///
-  /// The column major glyph representation of the character. Bits 
-  /// with values of one indicate that the corresponding pixel is to be 
+  /// The column major glyph representation of the character. Bits
+  /// with values of one indicate that the corresponding pixel is to be
   /// on when normally displayed; those with zero are off.
   ///
   UINT8                  GlyphCol1[EFI_GLYPH_HEIGHT];
   ///
-  /// The column major glyph representation of the character. Bits 
-  /// with values of one indicate that the corresponding pixel is to be 
+  /// The column major glyph representation of the character. Bits
+  /// with values of one indicate that the corresponding pixel is to be
   /// on when normally displayed; those with zero are off.
   ///
   UINT8                  GlyphCol2[EFI_GLYPH_HEIGHT];
   ///
-  /// Ensures that sizeof (EFI_WIDE_GLYPH) is twice the 
-  /// sizeof (EFI_NARROW_GLYPH). The contents of Pad must 
+  /// Ensures that sizeof (EFI_WIDE_GLYPH) is twice the
+  /// sizeof (EFI_NARROW_GLYPH). The contents of Pad must
   /// be zero.
   ///
   UINT8                  Pad[3];
@@ -268,7 +262,7 @@ typedef struct _EFI_HII_GIBT_GLYPH_BLOCK {
 typedef struct _EFI_HII_GIBT_GLYPHS_BLOCK {
   EFI_HII_GLYPH_BLOCK    Header;
   EFI_HII_GLYPH_INFO     Cell;
-  UINT16                 Count;  
+  UINT16                 Count;
   UINT8                  BitmapData[1];
 } EFI_HII_GIBT_GLYPHS_BLOCK;
 
@@ -831,6 +825,7 @@ typedef struct _EFI_IFR_QUESTION_HEADER {
 #define EFI_IFR_FLAG_READ_ONLY          0x01
 #define EFI_IFR_FLAG_CALLBACK           0x04
 #define EFI_IFR_FLAG_RESET_REQUIRED     0x10
+#define EFI_IFR_FLAG_REST_STYLE         0x20
 #define EFI_IFR_FLAG_RECONNECT_REQUIRED 0x40
 #define EFI_IFR_FLAG_OPTIONS_ONLY       0x80
 
@@ -845,7 +840,7 @@ typedef struct _EFI_IFR_DEFAULTSTORE {
 } EFI_IFR_DEFAULTSTORE;
 
 //
-// Default Identifier of default store 
+// Default Identifier of default store
 //
 #define EFI_HII_DEFAULT_CLASS_STANDARD       0x0000
 #define EFI_HII_DEFAULT_CLASS_MANUFACTURING  0x0001
@@ -1498,12 +1493,12 @@ typedef struct _EFI_IFR_SECURITY {
 
 typedef struct _EFI_IFR_FORM_MAP_METHOD {
   ///
-  /// The string identifier which provides the human-readable name of 
+  /// The string identifier which provides the human-readable name of
   /// the configuration method for this standards map form.
   ///
   EFI_STRING_ID            MethodTitle;
   ///
-  /// Identifier which uniquely specifies the configuration methods 
+  /// Identifier which uniquely specifies the configuration methods
   /// associated with this standards map form.
   ///
   EFI_GUID                 MethodIdentifier;
@@ -1511,8 +1506,8 @@ typedef struct _EFI_IFR_FORM_MAP_METHOD {
 
 typedef struct _EFI_IFR_FORM_MAP {
   ///
-  /// The sequence that defines the type of opcode as well as the length 
-  /// of the opcode being defined. Header.OpCode = EFI_IFR_FORM_MAP_OP. 
+  /// The sequence that defines the type of opcode as well as the length
+  /// of the opcode being defined. Header.OpCode = EFI_IFR_FORM_MAP_OP.
   ///
   EFI_IFR_OP_HEADER        Header;
   ///
@@ -1527,13 +1522,13 @@ typedef struct _EFI_IFR_FORM_MAP {
 
 typedef struct _EFI_IFR_SET {
   ///
-  /// The sequence that defines the type of opcode as well as the length 
-  /// of the opcode being defined. Header.OpCode = EFI_IFR_SET_OP. 
+  /// The sequence that defines the type of opcode as well as the length
+  /// of the opcode being defined. Header.OpCode = EFI_IFR_SET_OP.
   ///
   EFI_IFR_OP_HEADER  Header;
   ///
-  /// Specifies the identifier of a previously declared variable store to 
-  /// use when storing the question's value. 
+  /// Specifies the identifier of a previously declared variable store to
+  /// use when storing the question's value.
   ///
   EFI_VARSTORE_ID    VarStoreId;
   union {
@@ -1547,20 +1542,20 @@ typedef struct _EFI_IFR_SET {
     UINT16           VarOffset;
   }                  VarStoreInfo;
   ///
-  /// Specifies the type used for storage. 
+  /// Specifies the type used for storage.
   ///
   UINT8              VarStoreType;
 } EFI_IFR_SET;
 
 typedef struct _EFI_IFR_GET {
   ///
-  /// The sequence that defines the type of opcode as well as the length 
-  /// of the opcode being defined. Header.OpCode = EFI_IFR_GET_OP. 
+  /// The sequence that defines the type of opcode as well as the length
+  /// of the opcode being defined. Header.OpCode = EFI_IFR_GET_OP.
   ///
   EFI_IFR_OP_HEADER  Header;
   ///
-  /// Specifies the identifier of a previously declared variable store to 
-  /// use when retrieving the value. 
+  /// Specifies the identifier of a previously declared variable store to
+  /// use when retrieving the value.
   ///
   EFI_VARSTORE_ID    VarStoreId;
   union {
@@ -1574,7 +1569,7 @@ typedef struct _EFI_IFR_GET {
     UINT16           VarOffset;
   }                  VarStoreInfo;
   ///
-  /// Specifies the type used for storage. 
+  /// Specifies the type used for storage.
   ///
   UINT8              VarStoreType;
 } EFI_IFR_GET;
@@ -1598,9 +1593,9 @@ typedef struct _EFI_IFR_MAP {
 ///
 /// Each enumeration values maps a physical key on a keyboard.
 ///
-typedef enum {    
+typedef enum {
   EfiKeyLCtrl,
-  EfiKeyA0, 
+  EfiKeyA0,
   EfiKeyLAlt,
   EfiKeySpaceBar,
   EfiKeyA2,
@@ -1728,8 +1723,8 @@ typedef struct {
   ///
   CHAR16                  ShiftedAltGrUnicode;
   ///
-  /// Modifier keys are defined to allow for special functionality that is not necessarily 
-  /// accomplished by a printable character. Many of these modifier keys are flags to toggle 
+  /// Modifier keys are defined to allow for special functionality that is not necessarily
+  /// accomplished by a printable character. Many of these modifier keys are flags to toggle
   /// certain state bits on and off inside of a keyboard driver.
   ///
   UINT16                  Modifier;
@@ -1737,7 +1732,7 @@ typedef struct {
 } EFI_KEY_DESCRIPTOR;
 
 ///
-/// A key which is affected by all the standard shift modifiers.  
+/// A key which is affected by all the standard shift modifiers.
 /// Most keys would be expected to have this bit active.
 ///
 #define EFI_AFFECTED_BY_STANDARD_SHIFT       0x0001
@@ -1830,7 +1825,7 @@ typedef struct {
 ///
 typedef struct _EFI_IFR_ANIMATION {
   ///
-  /// Standard opcode header, where Header.OpCode is 
+  /// Standard opcode header, where Header.OpCode is
   /// EFI_IFR_ANIMATION_OP.
   ///
   EFI_IFR_OP_HEADER        Header;
@@ -1849,7 +1844,7 @@ typedef struct _EFI_HII_ANIMATION_PACKAGE_HDR {
   ///
   EFI_HII_PACKAGE_HEADER  Header;
   ///
-  /// Offset, relative to this header, of the animation information. If 
+  /// Offset, relative to this header, of the animation information. If
   /// this is zero, then there are no animation sequences in the package.
   ///
   UINT32                  AnimationInfoOffset;
@@ -1933,23 +1928,23 @@ typedef struct _EFI_HII_AIBT_EXT4_BLOCK {
 
 typedef struct _EFI_HII_ANIMATION_CELL {
   ///
-  /// The X offset from the upper left hand corner of the logical 
+  /// The X offset from the upper left hand corner of the logical
   /// window to position the indexed image.
   ///
   UINT16                    OffsetX;
   ///
-  /// The Y offset from the upper left hand corner of the logical 
+  /// The Y offset from the upper left hand corner of the logical
   /// window to position the indexed image.
   ///
   UINT16                    OffsetY;
   ///
-  /// The image to display at the specified offset from the upper left 
+  /// The image to display at the specified offset from the upper left
   /// hand corner of the logical window.
   ///
   EFI_IMAGE_ID              ImageId;
   ///
-  /// The number of milliseconds to delay after displaying the indexed 
-  /// image and before continuing on to the next linked image.  If value 
+  /// The number of milliseconds to delay after displaying the indexed
+  /// image and before continuing on to the next linked image.  If value
   /// is zero, no delay.
   ///
   UINT16                    Delay;
@@ -1961,11 +1956,11 @@ typedef struct _EFI_HII_ANIMATION_CELL {
 ///
 typedef struct _EFI_HII_AIBT_OVERLAY_IMAGES_BLOCK {
   ///
-  /// This is image that is to be reference by the image protocols, if the 
-  /// animation function is not supported or disabled. This image can 
-  /// be one particular image from the animation sequence (if any one 
-  /// of the animation frames has a complete image) or an alternate 
-  /// image that can be displayed alone. If the value is zero, no image 
+  /// This is image that is to be reference by the image protocols, if the
+  /// animation function is not supported or disabled. This image can
+  /// be one particular image from the animation sequence (if any one
+  /// of the animation frames has a complete image) or an alternate
+  /// image that can be displayed alone. If the value is zero, no image
   /// is displayed.
   ///
   EFI_IMAGE_ID            DftImageId;
@@ -1978,7 +1973,7 @@ typedef struct _EFI_HII_AIBT_OVERLAY_IMAGES_BLOCK {
   ///
   UINT16                  Height;
   ///
-  /// The number of EFI_HII_ANIMATION_CELL contained in the 
+  /// The number of EFI_HII_ANIMATION_CELL contained in the
   /// animation sequence.
   ///
   UINT16                  CellCount;
@@ -1990,16 +1985,16 @@ typedef struct _EFI_HII_AIBT_OVERLAY_IMAGES_BLOCK {
 
 ///
 /// An animation block to describe an animation sequence that does not cycle,
-/// and where the logical window is cleared to the specified color before 
+/// and where the logical window is cleared to the specified color before
 /// the next image is displayed.
 ///
 typedef struct _EFI_HII_AIBT_CLEAR_IMAGES_BLOCK {
   ///
-  /// This is image that is to be reference by the image protocols, if the 
-  /// animation function is not supported or disabled. This image can 
-  /// be one particular image from the animation sequence (if any one 
-  /// of the animation frames has a complete image) or an alternate 
-  /// image that can be displayed alone. If the value is zero, no image 
+  /// This is image that is to be reference by the image protocols, if the
+  /// animation function is not supported or disabled. This image can
+  /// be one particular image from the animation sequence (if any one
+  /// of the animation frames has a complete image) or an alternate
+  /// image that can be displayed alone. If the value is zero, no image
   /// is displayed.
   ///
   EFI_IMAGE_ID       DftImageId;
@@ -2012,12 +2007,12 @@ typedef struct _EFI_HII_AIBT_CLEAR_IMAGES_BLOCK {
   ///
   UINT16             Height;
   ///
-  /// The number of EFI_HII_ANIMATION_CELL contained in the 
+  /// The number of EFI_HII_ANIMATION_CELL contained in the
   /// animation sequence.
   ///
   UINT16             CellCount;
   ///
-  /// The color to clear the logical window to before displaying the 
+  /// The color to clear the logical window to before displaying the
   /// indexed image.
   ///
   EFI_HII_RGB_PIXEL  BackgndColor;
@@ -2029,16 +2024,16 @@ typedef struct _EFI_HII_AIBT_CLEAR_IMAGES_BLOCK {
 
 ///
 /// An animation block to describe an animation sequence that does not cycle,
-/// and where the screen is restored to the original state before the next 
+/// and where the screen is restored to the original state before the next
 /// image is displayed.
 ///
 typedef struct _EFI_HII_AIBT_RESTORE_SCRN_BLOCK {
   ///
-  /// This is image that is to be reference by the image protocols, if the 
-  /// animation function is not supported or disabled. This image can 
-  /// be one particular image from the animation sequence (if any one 
-  /// of the animation frames has a complete image) or an alternate 
-  /// image that can be displayed alone. If the value is zero, no image 
+  /// This is image that is to be reference by the image protocols, if the
+  /// animation function is not supported or disabled. This image can
+  /// be one particular image from the animation sequence (if any one
+  /// of the animation frames has a complete image) or an alternate
+  /// image that can be displayed alone. If the value is zero, no image
   /// is displayed.
   ///
   EFI_IMAGE_ID            DftImageId;
@@ -2051,7 +2046,7 @@ typedef struct _EFI_HII_AIBT_RESTORE_SCRN_BLOCK {
   ///
   UINT16                  Height;
   ///
-  /// The number of EFI_HII_ANIMATION_CELL contained in the 
+  /// The number of EFI_HII_ANIMATION_CELL contained in the
   /// animation sequence.
   ///
   UINT16                  CellCount;
@@ -2069,14 +2064,14 @@ typedef EFI_HII_AIBT_OVERLAY_IMAGES_BLOCK  EFI_HII_AIBT_OVERLAY_IMAGES_LOOP_BLOC
 
 ///
 /// An animation block to describe an animation sequence that continuously cycles,
-/// and where the logical window is cleared to the specified color before 
+/// and where the logical window is cleared to the specified color before
 /// the next image is displayed.
 ///
 typedef EFI_HII_AIBT_CLEAR_IMAGES_BLOCK    EFI_HII_AIBT_CLEAR_IMAGES_LOOP_BLOCK;
 
 ///
 /// An animation block to describe an animation sequence that continuously cycles,
-/// and where the screen is restored to the original state before 
+/// and where the screen is restored to the original state before
 /// the next image is displayed.
 ///
 typedef EFI_HII_AIBT_RESTORE_SCRN_BLOCK    EFI_HII_AIBT_RESTORE_SCRN_LOOP_BLOCK;
@@ -2086,7 +2081,7 @@ typedef EFI_HII_AIBT_RESTORE_SCRN_BLOCK    EFI_HII_AIBT_RESTORE_SCRN_LOOP_BLOCK;
 ///
 typedef struct _EFI_HII_AIBT_DUPLICATE_BLOCK {
   ///
-  /// The previously defined animation ID with the exact same 
+  /// The previously defined animation ID with the exact same
   /// animation information.
   ///
   EFI_ANIMATION_ID  AnimationId;
@@ -2121,7 +2116,7 @@ typedef struct _EFI_HII_AIBT_SKIP2_BLOCK {
 /// token usages.
 ///
 ///
-/// STRING_TOKEN is not defined in UEFI specification. But it is placed 
+/// STRING_TOKEN is not defined in UEFI specification. But it is placed
 /// here for the easy access by C files and VFR source files.
 ///
 #define STRING_TOKEN(t) t
diff --git a/MdePkg/Include/Uefi/UefiMultiPhase.h b/MdePkg/Include/Uefi/UefiMultiPhase.h
index 30352587ad22..dd97e4e3bfe4 100644
--- a/MdePkg/Include/Uefi/UefiMultiPhase.h
+++ b/MdePkg/Include/Uefi/UefiMultiPhase.h
@@ -1,20 +1,36 @@
 /** @file
   This includes some definitions introduced in UEFI that will be used in both PEI and DXE phases.
 
-Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under
-the terms and conditions of the BSD License that accompanies this distribution.
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
 #ifndef __UEFI_MULTIPHASE_H__
 #define __UEFI_MULTIPHASE_H__
 
+///
+/// Attributes of variable.
+///
+#define EFI_VARIABLE_NON_VOLATILE                            0x00000001
+#define EFI_VARIABLE_BOOTSERVICE_ACCESS                      0x00000002
+#define EFI_VARIABLE_RUNTIME_ACCESS                          0x00000004
+///
+/// This attribute is identified by the mnemonic 'HR'
+/// elsewhere in this specification.
+///
+#define EFI_VARIABLE_HARDWARE_ERROR_RECORD                   0x00000008
+///
+/// Attributes of Authenticated Variable
+///
+#define EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS   0x00000020
+#define EFI_VARIABLE_APPEND_WRITE                            0x00000040
+///
+/// NOTE: EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS is deprecated and should be considered reserved.
+///
+#define EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS              0x00000010
+
+#ifndef VFRCOMPILE
 #include <Guid/WinCertificate.h>
 ///
 /// Enumeration of memory types introduced in UEFI.
@@ -83,7 +99,7 @@ typedef enum {
   ///
   EfiPalCode,
   ///
-  /// A memory region that operates as EfiConventionalMemory, 
+  /// A memory region that operates as EfiConventionalMemory,
   /// however it happens to also support byte-addressable non-volatility.
   ///
   EfiPersistentMemory,
@@ -156,25 +172,6 @@ typedef struct {
 } EFI_TABLE_HEADER;
 
 ///
-/// Attributes of variable.
-///
-#define EFI_VARIABLE_NON_VOLATILE                            0x00000001
-#define EFI_VARIABLE_BOOTSERVICE_ACCESS                      0x00000002
-#define EFI_VARIABLE_RUNTIME_ACCESS                          0x00000004
-///
-/// This attribute is identified by the mnemonic 'HR'
-/// elsewhere in this specification.
-///
-#define EFI_VARIABLE_HARDWARE_ERROR_RECORD                   0x00000008
-///
-/// Attributes of Authenticated Variable
-///
-#define EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS              0x00000010
-#define EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS   0x00000020
-#define EFI_VARIABLE_APPEND_WRITE                            0x00000040
-
-
-///
 /// AuthInfo is a WIN_CERTIFICATE using the wCertificateType
 /// WIN_CERTIFICATE_UEFI_GUID and the CertType
 /// EFI_CERT_TYPE_RSA2048_SHA256_GUID. If the attribute specifies
@@ -227,5 +224,6 @@ typedef struct {
   ///
   WIN_CERTIFICATE_UEFI_GUID   AuthInfo;
  } EFI_VARIABLE_AUTHENTICATION_2;
+#endif // VFRCOMPILE
 
 #endif
diff --git a/MdePkg/Include/Uefi/UefiPxe.h b/MdePkg/Include/Uefi/UefiPxe.h
index aad1d3577dd9..6b92b3e44e4b 100644
--- a/MdePkg/Include/Uefi/UefiPxe.h
+++ b/MdePkg/Include/Uefi/UefiPxe.h
@@ -3,14 +3,8 @@
   structure prototypes, global variables and constants that
   are needed for porting PXE to EFI.
 
-Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   32/64-bit PXE specification:
diff --git a/MdePkg/Include/Uefi/UefiSpec.h b/MdePkg/Include/Uefi/UefiSpec.h
index bea32b7f5e1b..0e165478d6c3 100644
--- a/MdePkg/Include/Uefi/UefiSpec.h
+++ b/MdePkg/Include/Uefi/UefiSpec.h
@@ -1,18 +1,14 @@
 /** @file
   Include file that supports UEFI.
 
-  This include file must contain things defined in the UEFI 2.6 specification.
-  If a code construct is defined in the UEFI 2.6 specification it must be included
+  This include file must contain things defined in the UEFI 2.7 specification.
+  If a code construct is defined in the UEFI 2.7 specification it must be included
   by this include file.
 
-Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
-the terms and conditions of the BSD License that accompanies this distribution.  
-The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
-    
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
+Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -35,7 +31,7 @@ typedef enum {
   ///
   AllocateAnyPages,
   ///
-  /// Allocate any available range of pages whose uppermost address is less than 
+  /// Allocate any available range of pages whose uppermost address is less than
   /// or equal to a specified maximum address.
   ///
   AllocateMaxAddress,
@@ -79,7 +75,7 @@ typedef enum {
 #define EFI_MEMORY_XP               0x0000000000004000ULL
 #define EFI_MEMORY_RO               0x0000000000020000ULL
 //
-// Physical memory persistence attribute. 
+// Physical memory persistence attribute.
 // The memory region supports byte-addressable non-volatility.
 //
 #define EFI_MEMORY_NV               0x0000000000008000ULL
@@ -88,6 +84,26 @@ typedef enum {
 // If all memory has the same reliability, then this bit is not used.
 //
 #define EFI_MEMORY_MORE_RELIABLE    0x0000000000010000ULL
+
+//
+// Note: UEFI spec 2.8 and following:
+//
+// Specific-purpose memory (SPM). The memory is earmarked for
+// specific purposes such as for specific device drivers or applications.
+// The SPM attribute serves as a hint to the OS to avoid allocating this
+// memory for core OS data or code that can not be relocated.
+//
+#define EFI_MEMORY_SP               0x0000000000040000ULL
+//
+// If this flag is set, the memory region is capable of being
+// protected with the CPU?s memory cryptographic
+// capabilities. If this flag is clear, the memory region is not
+// capable of being protected with the CPU?s memory
+// cryptographic capabilities or the CPU does not support CPU
+// memory cryptographic capabilities.
+//
+#define EFI_MEMORY_CPU_CRYPTO       0x0000000000080000ULL
+
 //
 // Runtime memory attribute
 //
@@ -103,26 +119,33 @@ typedef enum {
 ///
 typedef struct {
   ///
-  /// Type of the memory region.  See EFI_MEMORY_TYPE.
+  /// Type of the memory region.
+  /// Type EFI_MEMORY_TYPE is defined in the
+  /// AllocatePages() function description.
   ///
   UINT32                Type;
   ///
-  /// Physical address of the first byte of the memory region.  Must aligned 
-  /// on a 4 KB boundary.
+  /// Physical address of the first byte in the memory region. PhysicalStart must be
+  /// aligned on a 4 KiB boundary, and must not be above 0xfffffffffffff000. Type
+  /// EFI_PHYSICAL_ADDRESS is defined in the AllocatePages() function description
   ///
   EFI_PHYSICAL_ADDRESS  PhysicalStart;
   ///
-  /// Virtual address of the first byte of the memory region.  Must aligned 
-  /// on a 4 KB boundary.
+  /// Virtual address of the first byte in the memory region.
+  /// VirtualStart must be aligned on a 4 KiB boundary,
+  /// and must not be above 0xfffffffffffff000.
   ///
   EFI_VIRTUAL_ADDRESS   VirtualStart;
   ///
-  /// Number of 4KB pages in the memory region.
+  /// NumberOfPagesNumber of 4 KiB pages in the memory region.
+  /// NumberOfPages must not be 0, and must not be any value
+  /// that would represent a memory page with a start address,
+  /// either physical or virtual, above 0xfffffffffffff000.
   ///
   UINT64                NumberOfPages;
   ///
   /// Attributes of the memory region that describe the bit mask of capabilities
-  /// for that memory region, and not necessarily the current settings for that 
+  /// for that memory region, and not necessarily the current settings for that
   /// memory region.
   ///
   UINT64                Attribute;
@@ -188,7 +211,7 @@ EFI_STATUS
                                          On output, it is the size of the buffer returned by the firmware if
                                          the buffer was large enough, or the size of the buffer needed to contain
                                          the map if the buffer was too small.
-  @param[in, out]  MemoryMap             A pointer to the buffer in which firmware places the current memory
+  @param[out]      MemoryMap             A pointer to the buffer in which firmware places the current memory
                                          map.
   @param[out]      MapKey                A pointer to the location in which firmware returns the key for the
                                          current memory map.
@@ -209,7 +232,7 @@ typedef
 EFI_STATUS
 (EFIAPI *EFI_GET_MEMORY_MAP)(
   IN OUT UINTN                       *MemoryMapSize,
-  IN OUT EFI_MEMORY_DESCRIPTOR       *MemoryMap,
+  OUT    EFI_MEMORY_DESCRIPTOR       *MemoryMap,
   OUT    UINTN                       *MapKey,
   OUT    UINTN                       *DescriptorSize,
   OUT    UINT32                      *DescriptorVersion
@@ -306,8 +329,8 @@ EFI_STATUS
   @retval EFI_NOT_FOUND         1) There are no EFI_DRIVER_BINDING_PROTOCOL instances
                                 present in the system.
                                 2) No drivers were connected to ControllerHandle.
-  @retval EFI_SECURITY_VIOLATION 
-                                The user has no permission to start UEFI device drivers on the device path 
+  @retval EFI_SECURITY_VIOLATION
+                                The user has no permission to start UEFI device drivers on the device path
                                 associated with the ControllerHandle or specified by the RemainingDevicePath.
 **/
 typedef
@@ -654,7 +677,8 @@ EFI_STATUS
 /**
   Enumerates the current variable names.
 
-  @param[in, out]  VariableNameSize The size of the VariableName buffer.
+  @param[in, out]  VariableNameSize The size of the VariableName buffer. The size must be large
+                                    enough to fit input string supplied in VariableName buffer.
   @param[in, out]  VariableName     On input, supplies the last VariableName that was returned
                                     by GetNextVariableName(). On output, returns the Nullterminated
                                     string of the current variable.
@@ -665,9 +689,14 @@ EFI_STATUS
   @retval EFI_SUCCESS           The function completed successfully.
   @retval EFI_NOT_FOUND         The next variable was not found.
   @retval EFI_BUFFER_TOO_SMALL  The VariableNameSize is too small for the result.
+                                VariableNameSize has been updated with the size needed to complete the request.
   @retval EFI_INVALID_PARAMETER VariableNameSize is NULL.
   @retval EFI_INVALID_PARAMETER VariableName is NULL.
   @retval EFI_INVALID_PARAMETER VendorGuid is NULL.
+  @retval EFI_INVALID_PARAMETER The input values of VariableName and VendorGuid are not a name and
+                                GUID of an existing variable.
+  @retval EFI_INVALID_PARAMETER Null-terminator is not found in the first VariableNameSize bytes of
+                                the input VariableName buffer.
   @retval EFI_DEVICE_ERROR      The variable could not be retrieved due to a hardware error.
 
 **/
@@ -688,15 +717,14 @@ EFI_STATUS
                                  then EFI_INVALID_PARAMETER is returned.
   @param[in]  VendorGuid         A unique identifier for the vendor.
   @param[in]  Attributes         Attributes bitmask to set for the variable.
-  @param[in]  DataSize           The size in bytes of the Data buffer. Unless the EFI_VARIABLE_APPEND_WRITE, 
-                                 EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS, or 
-                                 EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS attribute is set, a size of zero 
-                                 causes the variable to be deleted. When the EFI_VARIABLE_APPEND_WRITE attribute is 
-                                 set, then a SetVariable() call with a DataSize of zero will not cause any change to 
-                                 the variable value (the timestamp associated with the variable may be updated however 
-                                 even if no new data value is provided,see the description of the 
-                                 EFI_VARIABLE_AUTHENTICATION_2 descriptor below. In this case the DataSize will not 
-                                 be zero since the EFI_VARIABLE_AUTHENTICATION_2 descriptor will be populated). 
+  @param[in]  DataSize           The size in bytes of the Data buffer. Unless the EFI_VARIABLE_APPEND_WRITE or
+                                 EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS attribute is set, a size of zero
+                                 causes the variable to be deleted. When the EFI_VARIABLE_APPEND_WRITE attribute is
+                                 set, then a SetVariable() call with a DataSize of zero will not cause any change to
+                                 the variable value (the timestamp associated with the variable may be updated however
+                                 even if no new data value is provided,see the description of the
+                                 EFI_VARIABLE_AUTHENTICATION_2 descriptor below. In this case the DataSize will not
+                                 be zero since the EFI_VARIABLE_AUTHENTICATION_2 descriptor will be populated).
   @param[in]  Data               The contents for the variable.
 
   @retval EFI_SUCCESS            The firmware has successfully stored the variable and its data as
@@ -708,10 +736,9 @@ EFI_STATUS
   @retval EFI_DEVICE_ERROR       The variable could not be retrieved due to a hardware error.
   @retval EFI_WRITE_PROTECTED    The variable in question is read-only.
   @retval EFI_WRITE_PROTECTED    The variable in question cannot be deleted.
-  @retval EFI_SECURITY_VIOLATION The variable could not be written due to EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS 
-                                 or EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACESS being set, but the AuthInfo 
-                                 does NOT pass the validation check carried out by the firmware.
-  
+  @retval EFI_SECURITY_VIOLATION The variable could not be written due to EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACESS being set,
+                                 but the AuthInfo does NOT pass the validation check carried out by the firmware.
+
   @retval EFI_NOT_FOUND          The variable trying to be updated or deleted was not found.
 
 **/
@@ -859,10 +886,10 @@ EFI_STATUS
   @retval EFI_LOAD_ERROR         Image was not loaded because the image format was corrupt or not
                                  understood.
   @retval EFI_DEVICE_ERROR       Image was not loaded because the device returned a read error.
-  @retval EFI_ACCESS_DENIED      Image was not loaded because the platform policy prohibits the 
+  @retval EFI_ACCESS_DENIED      Image was not loaded because the platform policy prohibits the
                                  image from being loaded. NULL is returned in *ImageHandle.
-  @retval EFI_SECURITY_VIOLATION Image was loaded and an ImageHandle was created with a 
-                                 valid EFI_LOADED_IMAGE_PROTOCOL. However, the current 
+  @retval EFI_SECURITY_VIOLATION Image was loaded and an ImageHandle was created with a
+                                 valid EFI_LOADED_IMAGE_PROTOCOL. However, the current
                                  platform policy specifies that the image should not be started.
 **/
 typedef
@@ -901,15 +928,15 @@ EFI_STATUS
 /**
   Terminates a loaded EFI image and returns control to boot services.
 
-  @param[in]  ImageHandle       Handle that identifies the image. This parameter is passed to the 
+  @param[in]  ImageHandle       Handle that identifies the image. This parameter is passed to the
                                 image on entry.
   @param[in]  ExitStatus        The image's exit code.
   @param[in]  ExitDataSize      The size, in bytes, of ExitData. Ignored if ExitStatus is EFI_SUCCESS.
   @param[in]  ExitData          The pointer to a data buffer that includes a Null-terminated string,
-                                optionally followed by additional binary data. The string is a 
-                                description that the caller may use to further indicate the reason 
-                                for the image's exit. ExitData is only valid if ExitStatus 
-                                is something other than EFI_SUCCESS. The ExitData buffer 
+                                optionally followed by additional binary data. The string is a
+                                description that the caller may use to further indicate the reason
+                                for the image's exit. ExitData is only valid if ExitStatus
+                                is something other than EFI_SUCCESS. The ExitData buffer
                                 must be allocated by calling AllocatePool().
 
   @retval EFI_SUCCESS           The image specified by ImageHandle was unloaded.
@@ -1009,10 +1036,10 @@ EFI_STATUS
                                 EfiResetShutdown the data buffer starts with a Null-terminated
                                 string, optionally followed by additional binary data.
                                 The string is a description that the caller may use to further
-                                indicate the reason for the system reset. ResetData is only
-                                valid if ResetStatus is something other than EFI_SUCCESS
-                                unless the ResetType is EfiResetPlatformSpecific
-                                where a minimum amount of ResetData is always required.
+                                indicate the reason for the system reset.
+                                For a ResetType of EfiResetPlatformSpecific the data buffer
+                                also starts with a Null-terminated string that is followed
+                                by an EFI_GUID that describes the specific type of reset to perform.
 **/
 typedef
 VOID
@@ -1440,7 +1467,7 @@ typedef enum {
   ///
   ByRegisterNotify,
   ///
-  /// Retrieve the set of handles from the handle database that support a 
+  /// Retrieve the set of handles from the handle database that support a
   /// specified protocol.
   ///
   ByProtocol
@@ -1529,7 +1556,7 @@ EFI_STATUS
   @param[in]       Protocol     Provides the protocol to search by.
                                 This parameter is only valid for a SearchType of ByProtocol.
   @param[in]       SearchKey    Supplies the search key depending on the SearchType.
-  @param[in, out]  NoHandles    The number of handles returned in Buffer.
+  @param[out]      NoHandles    The number of handles returned in Buffer.
   @param[out]      Buffer       A pointer to the buffer to return the requested array of handles that
                                 support Protocol.
 
@@ -1547,7 +1574,7 @@ EFI_STATUS
   IN     EFI_LOCATE_SEARCH_TYPE       SearchType,
   IN     EFI_GUID                     *Protocol,      OPTIONAL
   IN     VOID                         *SearchKey,     OPTIONAL
-  IN OUT UINTN                        *NoHandles,
+  OUT    UINTN                        *NoHandles,
   OUT    EFI_HANDLE                   **Buffer
   );
 
@@ -1565,6 +1592,7 @@ EFI_STATUS
   @retval EFI_NOT_FOUND         No protocol instances were found that match Protocol and
                                 Registration.
   @retval EFI_INVALID_PARAMETER Interface is NULL.
+                                Protocol is NULL.
 
 **/
 typedef
@@ -1668,10 +1696,10 @@ typedef struct {
   @retval EFI_INVALID_PARAMETER CapsuleCount is 0.
   @retval EFI_DEVICE_ERROR      The capsule update was started, but failed due to a device error.
   @retval EFI_UNSUPPORTED       The capsule type is not supported on this platform.
-  @retval EFI_OUT_OF_RESOURCES  When ExitBootServices() has been previously called this error indicates the capsule 
-                                is compatible with this platform but is not capable of being submitted or processed 
+  @retval EFI_OUT_OF_RESOURCES  When ExitBootServices() has been previously called this error indicates the capsule
+                                is compatible with this platform but is not capable of being submitted or processed
                                 in runtime. The caller may resubmit the capsule prior to ExitBootServices().
-  @retval EFI_OUT_OF_RESOURCES  When ExitBootServices() has not been previously called then this error indicates 
+  @retval EFI_OUT_OF_RESOURCES  When ExitBootServices() has not been previously called then this error indicates
                                 the capsule is compatible with this platform but there are insufficient resources to process.
 
 **/
@@ -1699,10 +1727,10 @@ EFI_STATUS
   @retval EFI_UNSUPPORTED       The capsule type is not supported on this platform, and
                                 MaximumCapsuleSize and ResetType are undefined.
   @retval EFI_INVALID_PARAMETER MaximumCapsuleSize is NULL.
-  @retval EFI_OUT_OF_RESOURCES  When ExitBootServices() has been previously called this error indicates the capsule 
-                                is compatible with this platform but is not capable of being submitted or processed 
+  @retval EFI_OUT_OF_RESOURCES  When ExitBootServices() has been previously called this error indicates the capsule
+                                is compatible with this platform but is not capable of being submitted or processed
                                 in runtime. The caller may resubmit the capsule prior to ExitBootServices().
-  @retval EFI_OUT_OF_RESOURCES  When ExitBootServices() has not been previously called then this error indicates 
+  @retval EFI_OUT_OF_RESOURCES  When ExitBootServices() has not been previously called then this error indicates
                                 the capsule is compatible with this platform but there are insufficient resources to process.
 
 **/
@@ -1755,11 +1783,14 @@ EFI_STATUS
 #define EFI_OS_INDICATIONS_FMP_CAPSULE_SUPPORTED            0x0000000000000008
 #define EFI_OS_INDICATIONS_CAPSULE_RESULT_VAR_SUPPORTED     0x0000000000000010
 #define EFI_OS_INDICATIONS_START_PLATFORM_RECOVERY          0x0000000000000040
+#define EFI_OS_INDICATIONS_JSON_CONFIG_DATA_REFRESH         0x0000000000000080
 
 //
 // EFI Runtime Services Table
 //
 #define EFI_SYSTEM_TABLE_SIGNATURE      SIGNATURE_64 ('I','B','I',' ','S','Y','S','T')
+#define EFI_2_80_SYSTEM_TABLE_REVISION  ((2 << 16) | (80))
+#define EFI_2_70_SYSTEM_TABLE_REVISION  ((2 << 16) | (70))
 #define EFI_2_60_SYSTEM_TABLE_REVISION  ((2 << 16) | (60))
 #define EFI_2_50_SYSTEM_TABLE_REVISION  ((2 << 16) | (50))
 #define EFI_2_40_SYSTEM_TABLE_REVISION  ((2 << 16) | (40))
@@ -1770,7 +1801,7 @@ EFI_STATUS
 #define EFI_2_00_SYSTEM_TABLE_REVISION  ((2 << 16) | (00))
 #define EFI_1_10_SYSTEM_TABLE_REVISION  ((1 << 16) | (10))
 #define EFI_1_02_SYSTEM_TABLE_REVISION  ((1 << 16) | (02))
-#define EFI_SYSTEM_TABLE_REVISION       EFI_2_60_SYSTEM_TABLE_REVISION
+#define EFI_SYSTEM_TABLE_REVISION       EFI_2_70_SYSTEM_TABLE_REVISION
 #define EFI_SPECIFICATION_VERSION       EFI_SYSTEM_TABLE_REVISION
 
 #define EFI_RUNTIME_SERVICES_SIGNATURE  SIGNATURE_64 ('R','U','N','T','S','E','R','V')
@@ -2171,11 +2202,10 @@ typedef struct {
 #define EFI_REMOVABLE_MEDIA_FILE_NAME_X64     L"\\EFI\\BOOT\\BOOTX64.EFI"
 #define EFI_REMOVABLE_MEDIA_FILE_NAME_ARM     L"\\EFI\\BOOT\\BOOTARM.EFI"
 #define EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH64 L"\\EFI\\BOOT\\BOOTAA64.EFI"
+#define EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV64 L"\\EFI\\BOOT\\BOOTRISCV64.EFI"
 
 #if   defined (MDE_CPU_IA32)
   #define EFI_REMOVABLE_MEDIA_FILE_NAME   EFI_REMOVABLE_MEDIA_FILE_NAME_IA32
-#elif defined (MDE_CPU_IPF)
-  #define EFI_REMOVABLE_MEDIA_FILE_NAME   EFI_REMOVABLE_MEDIA_FILE_NAME_IA64
 #elif defined (MDE_CPU_X64)
   #define EFI_REMOVABLE_MEDIA_FILE_NAME   EFI_REMOVABLE_MEDIA_FILE_NAME_X64
 #elif defined (MDE_CPU_EBC)
@@ -2183,10 +2213,17 @@ typedef struct {
   #define EFI_REMOVABLE_MEDIA_FILE_NAME   EFI_REMOVABLE_MEDIA_FILE_NAME_ARM
 #elif defined (MDE_CPU_AARCH64)
   #define EFI_REMOVABLE_MEDIA_FILE_NAME   EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH64
+#elif defined (MDE_CPU_RISCV64)
+  #define EFI_REMOVABLE_MEDIA_FILE_NAME   EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV64
 #else
   #error Unknown Processor Type
 #endif
 
+//
+// The directory within the active EFI System Partition defined for delivery of capsule to firmware
+//
+#define EFI_CAPSULE_FILE_DIRECTORY            L"\\EFI\\UpdateCapsule\\"
+
 #include <Uefi/UefiPxe.h>
 #include <Uefi/UefiGpt.h>
 #include <Uefi/UefiInternalFormRepresentation.h>
diff --git a/MdePkg/Include/X64/Nasm.inc b/MdePkg/Include/X64/Nasm.inc
new file mode 100644
index 000000000000..2d85a8770830
--- /dev/null
+++ b/MdePkg/Include/X64/Nasm.inc
@@ -0,0 +1,22 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Abstract:
+;
+;   This file provides macro definitions for NASM files.
+;
+;------------------------------------------------------------------------------
+
+%macro SETSSBSY        0
+    DB 0xF3, 0x0F, 0x01, 0xE8
+%endmacro
+
+%macro READSSP_RAX     0
+    DB 0xF3, 0x48, 0x0F, 0x1E, 0xC8
+%endmacro
+
+%macro INCSSP_RAX      0
+    DB 0xF3, 0x48, 0x0F, 0xAE, 0xE8
+%endmacro
diff --git a/MdePkg/Include/X64/ProcessorBind.h b/MdePkg/Include/X64/ProcessorBind.h
index f32842468e38..a1b947c5a3a8 100644
--- a/MdePkg/Include/X64/ProcessorBind.h
+++ b/MdePkg/Include/X64/ProcessorBind.h
@@ -1,14 +1,8 @@
 /** @file
   Processor or Compiler specific defines and types x64 (Intel 64, AMD64).
 
-  Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
 
@@ -27,7 +21,7 @@
 #pragma pack()
 #endif
 
-#if defined(__GNUC__) && defined(__pic__) && !defined(USING_LTO)
+#if defined(__GNUC__) && defined(__pic__) && !defined(USING_LTO)  && !defined(__APPLE__)
 //
 // Mark all symbol declarations and references as hidden, meaning they will
 // not be subject to symbol preemption. This allows the compiler to refer to
@@ -107,24 +101,24 @@
 //
 #pragma warning ( disable : 4206 )
 
-#if _MSC_VER == 1800 || _MSC_VER == 1900
+#if defined(_MSC_VER) && _MSC_VER >= 1800
 
 //
 // Disable these warnings for VS2013.
 //
 
 //
-// This warning is for potentially uninitialized local variable, and it may cause false 
+// This warning is for potentially uninitialized local variable, and it may cause false
 // positive issues in VS2013 and VS2015 build
 //
 #pragma warning ( disable : 4701 )
-  
+
 //
-// This warning is for potentially uninitialized local pointer variable, and it may cause 
+// This warning is for potentially uninitialized local pointer variable, and it may cause
 // false positive issues in VS2013 and VS2015 build
 //
 #pragma warning ( disable : 4703 )
-  
+
 #endif
 
 #endif
@@ -261,12 +255,22 @@ typedef INT64   INTN;
 #define MAX_ADDRESS   0xFFFFFFFFFFFFFFFFULL
 
 ///
+/// Maximum usable address at boot time
+///
+#define MAX_ALLOC_ADDRESS   MAX_ADDRESS
+
+///
 /// Maximum legal x64 INTN and UINTN values.
 ///
 #define MAX_INTN   ((INTN)0x7FFFFFFFFFFFFFFFULL)
 #define MAX_UINTN  ((UINTN)0xFFFFFFFFFFFFFFFFULL)
 
 ///
+/// Minimum legal x64 INTN value.
+///
+#define MIN_INTN   (((INTN)-9223372036854775807LL) - 1)
+
+///
 /// The stack alignment required for x64
 ///
 #define CPU_STACK_ALIGNMENT   16
@@ -289,27 +293,27 @@ typedef INT64   INTN;
 #elif defined(_MSC_EXTENSIONS)
   ///
   /// Microsoft* compiler specific method for EFIAPI calling convention.
-  /// 
-  #define EFIAPI __cdecl  
+  ///
+  #define EFIAPI __cdecl
 #elif defined(__GNUC__)
   ///
   /// Define the standard calling convention regardless of optimization level.
   /// The GCC support assumes a GCC compiler that supports the EFI ABI. The EFI
-  /// ABI is much closer to the x64 Microsoft* ABI than standard x64 (x86-64) 
-  /// GCC ABI. Thus a standard x64 (x86-64) GCC compiler can not be used for 
-  /// x64. Warning the assembly code in the MDE x64 does not follow the correct 
+  /// ABI is much closer to the x64 Microsoft* ABI than standard x64 (x86-64)
+  /// GCC ABI. Thus a standard x64 (x86-64) GCC compiler can not be used for
+  /// x64. Warning the assembly code in the MDE x64 does not follow the correct
   /// ABI for the standard x64 (x86-64) GCC.
   ///
-  #define EFIAPI 
+  #define EFIAPI
 #else
   ///
   /// The default for a non Microsoft* or GCC compiler is to assume the EFI ABI
-  /// is the standard. 
+  /// is the standard.
   ///
-  #define EFIAPI       
+  #define EFIAPI
 #endif
 
-#if defined(__GNUC__)
+#if defined(__GNUC__) || defined(__clang__)
   ///
   /// For GNU assembly code, .global or .globl can declare global symbols.
   /// Define this macro to unify the usage.
@@ -319,13 +323,13 @@ typedef INT64   INTN;
 
 /**
   Return the pointer to the first instruction of a function given a function pointer.
-  On x64 CPU architectures, these two pointer values are the same, 
+  On x64 CPU architectures, these two pointer values are the same,
   so the implementation of this macro is very simple.
-  
+
   @param  FunctionPointer   A pointer to a function.
 
   @return The pointer to the first instruction of a function given a function pointer.
-  
+
 **/
 #define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)