16 files changed, 444 insertions, 89 deletions
diff --git a/MdePkg/Library/BaseLib/AArch64/CpuBreakpoint.S b/MdePkg/Library/BaseLib/AArch64/CpuBreakpoint.S
index 68bc05549d69..b1354b77fcf7 100644
--- a/MdePkg/Library/BaseLib/AArch64/CpuBreakpoint.S
+++ b/MdePkg/Library/BaseLib/AArch64/CpuBreakpoint.S
@@ -5,13 +5,7 @@
 # Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
 # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
 # Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution.  The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php.
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
 #
 #------------------------------------------------------------------------------
 
diff --git a/MdePkg/Library/BaseLib/AArch64/CpuBreakpoint.asm b/MdePkg/Library/BaseLib/AArch64/CpuBreakpoint.asm
new file mode 100644
index 000000000000..57129ee343c5
--- /dev/null
+++ b/MdePkg/Library/BaseLib/AArch64/CpuBreakpoint.asm
@@ -0,0 +1,33 @@
+;------------------------------------------------------------------------------
+;
+; CpuBreakpoint() for AArch64
+;
+; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+; Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+
+  EXPORT CpuBreakpoint
+  AREA BaseLib_LowLevel, CODE, READONLY
+
+;/**
+;  Generates a breakpoint on the CPU.
+;
+;  Generates a breakpoint on the CPU. The breakpoint must be implemented such
+;  that code can resume normal execution after the breakpoint.
+;
+;**/
+;VOID
+;EFIAPI
+;CpuBreakpoint (
+;  VOID
+;  );
+;
+CpuBreakpoint
+    svc   0xdbdb    // Superviser exception. Takes 16bit arg -> Armv7 had 'swi' here.
+    ret
+
+  END
diff --git a/MdePkg/Library/BaseLib/AArch64/DisableInterrupts.S b/MdePkg/Library/BaseLib/AArch64/DisableInterrupts.S
index 9d67d07a86b5..3b3e8309fa22 100644
--- a/MdePkg/Library/BaseLib/AArch64/DisableInterrupts.S
+++ b/MdePkg/Library/BaseLib/AArch64/DisableInterrupts.S
@@ -5,13 +5,7 @@
 # Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
 # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
 # Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution.  The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php.
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
 #
 #------------------------------------------------------------------------------
 
diff --git a/MdePkg/Library/BaseLib/AArch64/DisableInterrupts.asm b/MdePkg/Library/BaseLib/AArch64/DisableInterrupts.asm
new file mode 100644
index 000000000000..c299c51e8a1a
--- /dev/null
+++ b/MdePkg/Library/BaseLib/AArch64/DisableInterrupts.asm
@@ -0,0 +1,31 @@
+;------------------------------------------------------------------------------
+;
+; DisableInterrupts() for AArch64
+;
+; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+; Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+  EXPORT DisableInterrupts
+  AREA BaseLib_LowLevel, CODE, READONLY
+
+DAIF_WR_IRQ_BIT     EQU     (1 << 1)
+
+;/**
+;  Disables CPU interrupts.
+;
+;**/
+;VOID
+;EFIAPI
+;DisableInterrupts (
+;  VOID
+;  );
+;
+DisableInterrupts
+    msr  daifset, #DAIF_WR_IRQ_BIT
+    ret
+
+  END
diff --git a/MdePkg/Library/BaseLib/AArch64/EnableInterrupts.S b/MdePkg/Library/BaseLib/AArch64/EnableInterrupts.S
index 14915ed24b29..42918a16018a 100644
--- a/MdePkg/Library/BaseLib/AArch64/EnableInterrupts.S
+++ b/MdePkg/Library/BaseLib/AArch64/EnableInterrupts.S
@@ -5,13 +5,7 @@
 # Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
 # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
 # Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution.  The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php.
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
 #
 #------------------------------------------------------------------------------
 
diff --git a/MdePkg/Library/BaseLib/AArch64/EnableInterrupts.asm b/MdePkg/Library/BaseLib/AArch64/EnableInterrupts.asm
new file mode 100644
index 000000000000..fd1c21a59a91
--- /dev/null
+++ b/MdePkg/Library/BaseLib/AArch64/EnableInterrupts.asm
@@ -0,0 +1,31 @@
+;------------------------------------------------------------------------------
+;
+; EnableInterrupts() for AArch64
+;
+; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+; Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+  EXPORT EnableInterrupts
+  AREA BaseLib_LowLevel, CODE, READONLY
+
+DAIF_WR_IRQ_BIT     EQU     (1 << 1)
+
+;/**
+;  Enables CPU interrupts.
+;
+;**/
+;VOID
+;EFIAPI
+;EnableInterrupts (
+;  VOID
+;  );
+;
+EnableInterrupts
+    msr  daifclr, #DAIF_WR_IRQ_BIT
+    ret
+
+  END
diff --git a/MdePkg/Library/BaseLib/AArch64/GetInterruptsState.S b/MdePkg/Library/BaseLib/AArch64/GetInterruptsState.S
index 1818c62560fe..feedc4dc9218 100644
--- a/MdePkg/Library/BaseLib/AArch64/GetInterruptsState.S
+++ b/MdePkg/Library/BaseLib/AArch64/GetInterruptsState.S
@@ -5,13 +5,7 @@
 # Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
 # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
 # Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution.  The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php.
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
 #
 #------------------------------------------------------------------------------
 
diff --git a/MdePkg/Library/BaseLib/AArch64/GetInterruptsState.asm b/MdePkg/Library/BaseLib/AArch64/GetInterruptsState.asm
new file mode 100644
index 000000000000..fd1d6eb05e10
--- /dev/null
+++ b/MdePkg/Library/BaseLib/AArch64/GetInterruptsState.asm
@@ -0,0 +1,43 @@
+;------------------------------------------------------------------------------
+;
+; GetInterruptState() function for AArch64
+;
+; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+; Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+  EXPORT GetInterruptState
+  AREA BaseLib_LowLevel, CODE, READONLY
+
+DAIF_RD_IRQ_BIT     EQU     (1 << 7)
+
+;/**
+;  Retrieves the current CPU interrupt state.
+;
+;  Returns TRUE is interrupts are currently enabled. Otherwise
+;  returns FALSE.
+;
+;  @retval TRUE  CPU interrupts are enabled.
+;  @retval FALSE CPU interrupts are disabled.
+;
+;**/
+;
+;BOOLEAN
+;EFIAPI
+;GetInterruptState (
+;  VOID
+; );
+;
+GetInterruptState
+    mrs    x0, daif
+    mov    w0, wzr
+    tst    x0, #DAIF_RD_IRQ_BIT   // Check IRQ mask; set Z=1 if clear/unmasked
+    bne    exit                   // if Z=1 (eq) return 1, else 0
+    mov    w0, #1
+exit
+    ret
+
+  END
diff --git a/MdePkg/Library/BaseLib/AArch64/MemoryFence.S b/MdePkg/Library/BaseLib/AArch64/MemoryFence.S
index 8dbd54aa08cf..457763e6d454 100644
--- a/MdePkg/Library/BaseLib/AArch64/MemoryFence.S
+++ b/MdePkg/Library/BaseLib/AArch64/MemoryFence.S
@@ -4,13 +4,7 @@
 #
 # Copyright (c) 2013, ARM Ltd. All rights reserved.
 #
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution.  The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php.
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
 #
 ##------------------------------------------------------------------------------
 
diff --git a/MdePkg/Library/BaseLib/AArch64/MemoryFence.asm b/MdePkg/Library/BaseLib/AArch64/MemoryFence.asm
new file mode 100644
index 000000000000..209034f551d7
--- /dev/null
+++ b/MdePkg/Library/BaseLib/AArch64/MemoryFence.asm
@@ -0,0 +1,32 @@
+;------------------------------------------------------------------------------
+;
+; MemoryFence() for AArch64
+;
+; Copyright (c) 2013, ARM Ltd. All rights reserved.
+;
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+  EXPORT MemoryFence
+  AREA BaseLib_LowLevel, CODE, READONLY
+
+;/**
+;  Used to serialize load and store operations.
+;
+;  All loads and stores that proceed calls to this function are guaranteed to be
+;  globally visible when this function returns.
+;
+;**/
+;VOID
+;EFIAPI
+;MemoryFence (
+;  VOID
+;  );
+;
+MemoryFence
+    // System wide Data Memory Barrier.
+    dmb sy
+    ret
+
+  END
diff --git a/MdePkg/Library/BaseLib/AArch64/SetJumpLongJump.S b/MdePkg/Library/BaseLib/AArch64/SetJumpLongJump.S
index 9fa096e33b4c..ac70acf586fe 100644
--- a/MdePkg/Library/BaseLib/AArch64/SetJumpLongJump.S
+++ b/MdePkg/Library/BaseLib/AArch64/SetJumpLongJump.S
@@ -1,13 +1,7 @@
 #------------------------------------------------------------------------------
 #
 # Copyright (c) 2009-2013, ARM Ltd.  All rights reserved.
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution.  The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php.
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
 #
 #------------------------------------------------------------------------------
 .text
diff --git a/MdePkg/Library/BaseLib/AArch64/SetJumpLongJump.asm b/MdePkg/Library/BaseLib/AArch64/SetJumpLongJump.asm
new file mode 100644
index 000000000000..84c8053fc4ed
--- /dev/null
+++ b/MdePkg/Library/BaseLib/AArch64/SetJumpLongJump.asm
@@ -0,0 +1,95 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2009-2013, ARM Ltd.  All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+  EXPORT SetJump
+  EXPORT InternalLongJump
+  AREA BaseLib_LowLevel, CODE, READONLY
+
+#define GPR_LAYOUT                          \
+        REG_PAIR (x19, x20,  #0);           \
+        REG_PAIR (x21, x22, #16);           \
+        REG_PAIR (x23, x24, #32);           \
+        REG_PAIR (x25, x26, #48);           \
+        REG_PAIR (x27, x28, #64);           \
+        REG_PAIR (x29, x30, #80);/*FP, LR*/ \
+        REG_ONE  (x16,      #96) /*IP0*/
+
+#define FPR_LAYOUT                       \
+        REG_PAIR ( d8,  d9, #112);       \
+        REG_PAIR (d10, d11, #128);       \
+        REG_PAIR (d12, d13, #144);       \
+        REG_PAIR (d14, d15, #160);
+
+;/**
+;  Saves the current CPU context that can be restored with a call to LongJump() and returns 0.#
+;
+;  Saves the current CPU context in the buffer specified by JumpBuffer and returns 0.  The initial
+;  call to SetJump() must always return 0.  Subsequent calls to LongJump() cause a non-zero
+;  value to be returned by SetJump().
+;
+;  If JumpBuffer is NULL, then ASSERT().
+;  For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().
+;
+;  @param  JumpBuffer    A pointer to CPU context buffer.
+;
+;**/
+;
+;UINTN
+;EFIAPI
+;SetJump (
+;  IN      BASE_LIBRARY_JUMP_BUFFER  *JumpBuffer  // X0
+;  );
+;
+SetJump
+        mov     x16, sp // use IP0 so save SP
+#define REG_PAIR(REG1, REG2, OFFS)      stp REG1, REG2, [x0, OFFS]
+#define REG_ONE(REG1, OFFS)             str REG1, [x0, OFFS]
+        GPR_LAYOUT
+        FPR_LAYOUT
+#undef REG_PAIR
+#undef REG_ONE
+        mov     w0, #0
+        ret
+
+;/**
+;  Restores the CPU context that was saved with SetJump().#
+;
+;  Restores the CPU context from the buffer specified by JumpBuffer.
+;  This function never returns to the caller.
+;  Instead is resumes execution based on the state of JumpBuffer.
+;
+;  @param  JumpBuffer    A pointer to CPU context buffer.
+;  @param  Value         The value to return when the SetJump() context is restored.
+;
+;**/
+;VOID
+;EFIAPI
+;InternalLongJump (
+;  IN      BASE_LIBRARY_JUMP_BUFFER  *JumpBuffer,  // X0
+;  IN      UINTN                     Value         // X1
+;  );
+;
+InternalLongJump
+#define REG_PAIR(REG1, REG2, OFFS)      ldp REG1, REG2, [x0, OFFS]
+#define REG_ONE(REG1, OFFS)             ldr REG1, [x0, OFFS]
+        GPR_LAYOUT
+        FPR_LAYOUT
+#undef REG_PAIR
+#undef REG_ONE
+        mov     sp, x16
+        cmp     w1, #0
+        mov     w0, #1
+        beq     exit
+        mov     w0, w1
+exit
+        // use br not ret, as ret is guaranteed to mispredict
+        br      x30
+
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED
+
+  END
+
diff --git a/MdePkg/Library/BaseLib/AArch64/SpeculationBarrier.S b/MdePkg/Library/BaseLib/AArch64/SpeculationBarrier.S
new file mode 100644
index 000000000000..96831b3b8256
--- /dev/null
+++ b/MdePkg/Library/BaseLib/AArch64/SpeculationBarrier.S
@@ -0,0 +1,33 @@
+##------------------------------------------------------------------------------
+#
+# SpeculationBarrier() for AArch64
+#
+# Copyright (c) 2019, Linaro Ltd. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##------------------------------------------------------------------------------
+
+.text
+.p2align 2
+
+GCC_ASM_EXPORT(SpeculationBarrier)
+
+
+#/**
+#  Uses as a barrier to stop speculative execution.
+#
+#  Ensures that no later instruction will execute speculatively, until all prior
+#  instructions have completed.
+#
+#**/
+#VOID
+#EFIAPI
+#SpeculationBarrier (
+#  VOID
+#  );
+#
+ASM_PFX(SpeculationBarrier):
+    dsb  sy
+    isb
+    ret
diff --git a/MdePkg/Library/BaseLib/AArch64/SpeculationBarrier.asm b/MdePkg/Library/BaseLib/AArch64/SpeculationBarrier.asm
new file mode 100644
index 000000000000..8323cfce4cac
--- /dev/null
+++ b/MdePkg/Library/BaseLib/AArch64/SpeculationBarrier.asm
@@ -0,0 +1,32 @@
+;------------------------------------------------------------------------------
+;
+; SpeculationBarrier() for AArch64
+;
+; Copyright (c) 2019, Linaro Ltd. All rights reserved.
+;
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+  EXPORT SpeculationBarrier
+  AREA BaseLib_LowLevel, CODE, READONLY
+
+;/**
+;  Uses as a barrier to stop speculative execution.
+;
+;  Ensures that no later instruction will execute speculatively, until all prior
+;  instructions have completed.
+;
+;**/
+;VOID
+;EFIAPI
+;SpeculationBarrier (
+;  VOID
+;  );
+;
+SpeculationBarrier
+    dsb   sy
+    isb
+    ret
+
+  END
diff --git a/MdePkg/Library/BaseLib/AArch64/SwitchStack.S b/MdePkg/Library/BaseLib/AArch64/SwitchStack.S
index 1bc6320061b0..00f07c593dde 100644
--- a/MdePkg/Library/BaseLib/AArch64/SwitchStack.S
+++ b/MdePkg/Library/BaseLib/AArch64/SwitchStack.S
@@ -1,17 +1,11 @@
-//------------------------------------------------------------------------------
-//
-// Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
-// Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-// Portions copyright (c) 2011 - 2013, ARM Limited. All rights reserved.<BR>
-// This program and the accompanying materials
-// are licensed and made available under the terms and conditions of the BSD License
-// which accompanies this distribution.  The full text of the license may be found at
-// http://opensource.org/licenses/bsd-license.php.
-//
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-//------------------------------------------------------------------------------
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# Portions copyright (c) 2011 - 2013, ARM Limited. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
 
 .text
 .align 5
@@ -19,26 +13,27 @@
 GCC_ASM_EXPORT(InternalSwitchStackAsm)
 GCC_ASM_EXPORT(CpuPause)
 
-/**
-//
-//  This allows the caller to switch the stack and goes to the new entry point
-//
-// @param      EntryPoint   The pointer to the location to enter
-// @param      Context      Parameter to pass in
-// @param      Context2     Parameter2 to pass in
-// @param      NewStack     New Location of the stack
-//
-// @return     Nothing. Goes to the Entry Point passing in the new parameters
-//
-VOID
-EFIAPI
-InternalSwitchStackAsm (
-  SWITCH_STACK_ENTRY_POINT EntryPoint,
-  VOID  *Context,
-  VOID  *Context2,
-  VOID  *NewStack
-  );
-**/
+#/**
+#
+#  This allows the caller to switch the stack and goes to the new entry point
+#
+# @param      EntryPoint   The pointer to the location to enter
+# @param      Context      Parameter to pass in
+# @param      Context2     Parameter2 to pass in
+# @param      NewStack     New Location of the stack
+#
+# @return     Nothing. Goes to the Entry Point passing in the new parameters
+#
+#**/
+#VOID
+#EFIAPI
+#InternalSwitchStackAsm (
+#  SWITCH_STACK_ENTRY_POINT EntryPoint,
+#  VOID  *Context,
+#  VOID  *Context2,
+#  VOID  *NewStack
+#  );
+#
 ASM_PFX(InternalSwitchStackAsm):
     mov   x29, #0
     mov   x30, x0
@@ -47,19 +42,20 @@ ASM_PFX(InternalSwitchStackAsm):
     mov   x1, x2
     ret
 
-/**
-//
-//  Requests CPU to pause for a short period of time.
-//
-//  Requests CPU to pause for a short period of time. Typically used in MP
-//  systems to prevent memory starvation while waiting for a spin lock.
-//
-VOID
-EFIAPI
-CpuPause (
-  VOID
-  )
-**/
+#/**
+#
+#  Requests CPU to pause for a short period of time.
+#
+#  Requests CPU to pause for a short period of time. Typically used in MP
+#  systems to prevent memory starvation while waiting for a spin lock.
+#
+#**/
+#VOID
+#EFIAPI
+#CpuPause (
+#  VOID
+#  )
+#
 ASM_PFX(CpuPause):
     nop
     nop
diff --git a/MdePkg/Library/BaseLib/AArch64/SwitchStack.asm b/MdePkg/Library/BaseLib/AArch64/SwitchStack.asm
new file mode 100644
index 000000000000..4f813e060dbf
--- /dev/null
+++ b/MdePkg/Library/BaseLib/AArch64/SwitchStack.asm
@@ -0,0 +1,65 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
+; Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+; Portions copyright (c) 2011 - 2013, ARM Limited. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+  EXPORT InternalSwitchStackAsm
+  EXPORT CpuPause
+  AREA BaseLib_LowLevel, CODE, READONLY
+
+;/**
+;
+;  This allows the caller to switch the stack and goes to the new entry point
+;
+; @param      EntryPoint   The pointer to the location to enter
+; @param      Context      Parameter to pass in
+; @param      Context2     Parameter2 to pass in
+; @param      NewStack     New Location of the stack
+;
+; @return     Nothing. Goes to the Entry Point passing in the new parameters
+;
+;**/
+;VOID
+;EFIAPI
+;InternalSwitchStackAsm (
+;  SWITCH_STACK_ENTRY_POINT EntryPoint,
+;  VOID  *Context,
+;  VOID  *Context2,
+;  VOID  *NewStack
+;  );
+;
+InternalSwitchStackAsm
+    mov   x29, #0
+    mov   x30, x0
+    mov   sp, x3
+    mov   x0, x1
+    mov   x1, x2
+    ret
+
+;/**
+;
+;  Requests CPU to pause for a short period of time.
+;
+;  Requests CPU to pause for a short period of time. Typically used in MP
+;  systems to prevent memory starvation while waiting for a spin lock.
+;
+;**/
+;VOID
+;EFIAPI
+;CpuPause (
+;  VOID
+;  )
+;
+CpuPause
+    nop
+    nop
+    nop
+    nop
+    nop
+    ret
+
+  END