diff options
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/AArch64/GISel/select-ssubo.mir')
-rw-r--r-- | contrib/llvm-project/llvm/lib/Target/AArch64/GISel/select-ssubo.mir | 158 |
1 files changed, 158 insertions, 0 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/select-ssubo.mir b/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/select-ssubo.mir new file mode 100644 index 000000000000..f6b1794645f7 --- /dev/null +++ b/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/select-ssubo.mir @@ -0,0 +1,158 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-uknown -global-isel -run-pass=instruction-select %s -o - | FileCheck %s + +... +--- +name: ssubo_s32 +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $w0, $w1, $x2 + + ; CHECK-LABEL: name: ssubo_s32 + ; CHECK: liveins: $w0, $w1, $x2 + ; CHECK: %reg0:gpr32 = COPY $w0 + ; CHECK: %reg1:gpr32 = COPY $w1 + ; CHECK: %ssubo:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv + ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv + ; CHECK: $w0 = COPY %ssubo + ; CHECK: RET_ReallyLR implicit $w0 + %reg0:gpr(s32) = COPY $w0 + %reg1:gpr(s32) = COPY $w1 + %ssubo:gpr(s32), %4:gpr(s1) = G_SSUBO %reg0, %reg1 + $w0 = COPY %ssubo(s32) + RET_ReallyLR implicit $w0 + +... +--- +name: ssubo_s64 +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $x0, $x1, $x2 + + ; CHECK-LABEL: name: ssubo_s64 + ; CHECK: liveins: $x0, $x1, $x2 + ; CHECK: %reg0:gpr64 = COPY $x0 + ; CHECK: %reg1:gpr64 = COPY $x1 + ; CHECK: %ssubo:gpr64 = SUBSXrr %reg0, %reg1, implicit-def $nzcv + ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv + ; CHECK: $x0 = COPY %ssubo + ; CHECK: RET_ReallyLR implicit $x0 + %reg0:gpr(s64) = COPY $x0 + %reg1:gpr(s64) = COPY $x1 + %ssubo:gpr(s64), %4:gpr(s1) = G_SSUBO %reg0, %reg1 + $x0 = COPY %ssubo(s64) + RET_ReallyLR implicit $x0 + +... +--- +name: ssubo_s32_imm +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $w0, $w1, $x2 + ; Check that we get SUBSWri when we can fold in a constant. + ; + ; CHECK-LABEL: name: ssubo_s32_imm + ; CHECK: liveins: $w0, $w1, $x2 + ; CHECK: %copy:gpr32sp = COPY $w0 + ; CHECK: %ssubo:gpr32 = SUBSWri %copy, 16, 0, implicit-def $nzcv + ; CHECK: %overflow:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv + ; CHECK: $w0 = COPY %ssubo + ; CHECK: RET_ReallyLR implicit $w0 + %copy:gpr(s32) = COPY $w0 + %constant:gpr(s32) = G_CONSTANT i32 16 + %ssubo:gpr(s32), %overflow:gpr(s1) = G_SSUBO %copy, %constant + $w0 = COPY %ssubo(s32) + RET_ReallyLR implicit $w0 + +... +--- +name: ssubo_s32_shifted +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $w0, $w1, $x2 + ; Check that we get SUBSWrs when we can fold in a shift. + ; + ; CHECK-LABEL: name: ssubo_s32_shifted + ; CHECK: liveins: $w0, $w1, $x2 + ; CHECK: %reg0:gpr32 = COPY $w0 + ; CHECK: %reg1:gpr32 = COPY $w1 + ; CHECK: %sub:gpr32 = SUBSWrs %reg0, %reg1, 16, implicit-def $nzcv + ; CHECK: %overflow:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv + ; CHECK: $w0 = COPY %sub + ; CHECK: RET_ReallyLR implicit $w0 + %reg0:gpr(s32) = COPY $w0 + %reg1:gpr(s32) = COPY $w1 + %constant:gpr(s32) = G_CONSTANT i32 16 + %shift:gpr(s32) = G_SHL %reg1(s32), %constant(s32) + %sub:gpr(s32), %overflow:gpr(s1) = G_SSUBO %reg0, %shift + $w0 = COPY %sub(s32) + RET_ReallyLR implicit $w0 + +... +--- +name: ssubo_s32_neg_imm +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $w0, $w1, $x2 + ; Check that we get ADDSWri when we can fold in a negative constant. + ; + ; CHECK-LABEL: name: ssubo_s32_neg_imm + ; CHECK: liveins: $w0, $w1, $x2 + ; CHECK: %copy:gpr32sp = COPY $w0 + ; CHECK: %sub:gpr32 = ADDSWri %copy, 16, 0, implicit-def $nzcv + ; CHECK: %overflow:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv + ; CHECK: $w0 = COPY %sub + ; CHECK: RET_ReallyLR implicit $w0 + %copy:gpr(s32) = COPY $w0 + %constant:gpr(s32) = G_CONSTANT i32 -16 + %sub:gpr(s32), %overflow:gpr(s1) = G_SSUBO %copy, %constant + $w0 = COPY %sub(s32) + RET_ReallyLR implicit $w0 + +... +--- +name: ssubo_arith_extended +alignment: 4 +legalized: true +regBankSelected: true +tracksRegLiveness: true +body: | + bb.1.entry: + liveins: $w0, $x0 + ; Check that we get SUBSXrx. + ; CHECK-LABEL: name: ssubo_arith_extended + ; CHECK: liveins: $w0, $x0 + ; CHECK: %reg0:gpr64sp = COPY $x0 + ; CHECK: %reg1:gpr32 = COPY $w0 + ; CHECK: %sub:gpr64 = SUBSXrx %reg0, %reg1, 18, implicit-def $nzcv + ; CHECK: %flags:gpr32 = CSINCWr $wzr, $wzr, 7, implicit $nzcv + ; CHECK: $x0 = COPY %sub + ; CHECK: RET_ReallyLR implicit $x0 + %reg0:gpr(s64) = COPY $x0 + %reg1:gpr(s32) = COPY $w0 + %ext:gpr(s64) = G_ZEXT %reg1(s32) + %cst:gpr(s64) = G_CONSTANT i64 2 + %shift:gpr(s64) = G_SHL %ext, %cst(s64) + %sub:gpr(s64), %flags:gpr(s1) = G_SSUBO %reg0, %shift + $x0 = COPY %sub(s64) + RET_ReallyLR implicit $x0 |