diff options
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/ARM/ARMScheduleSwift.td')
| -rw-r--r-- | contrib/llvm-project/llvm/lib/Target/ARM/ARMScheduleSwift.td | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/ARM/ARMScheduleSwift.td b/contrib/llvm-project/llvm/lib/Target/ARM/ARMScheduleSwift.td index e0e98bfa0e9b..d66b3065c7b7 100644 --- a/contrib/llvm-project/llvm/lib/Target/ARM/ARMScheduleSwift.td +++ b/contrib/llvm-project/llvm/lib/Target/ARM/ARMScheduleSwift.td @@ -558,8 +558,8 @@ let SchedModel = SwiftModel in { (instregex "VADDv", "VSUBv", "VNEG(s|f|v)", "VADDL", "VSUBL", "VADDW", "VSUBW", "VHADD", "VHSUB", "VRHADD", "VPADDi", "VPADDL", "VAND", "VBIC", "VEOR", "VORN", "VORR", "VTST", - "VSHL", "VSHR(s|u)", "VSHLL", "VQSHL(s|u)", "VBIF", - "VBIT", "VBSL", "VSLI", "VSRI", "VCLS", "VCLZ", "VCNT")>; + "VSHL", "VSHR(s|u)", "VSHLL", "VQSHL(s|u)", "VBIF", "VBIT", + "VBSL", "VBSP", "VSLI", "VSRI", "VCLS", "VCLZ", "VCNT")>; def : InstRW<[SwiftWriteP1TwoCycle], (instregex "VEXT", "VREV16", "VREV32", "VREV64")>; |