diff options
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/ARM/ARMSubtarget.cpp')
-rw-r--r-- | contrib/llvm-project/llvm/lib/Target/ARM/ARMSubtarget.cpp | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/ARM/ARMSubtarget.cpp b/contrib/llvm-project/llvm/lib/Target/ARM/ARMSubtarget.cpp index 46802037c2aa..5cb608b74ace 100644 --- a/contrib/llvm-project/llvm/lib/Target/ARM/ARMSubtarget.cpp +++ b/contrib/llvm-project/llvm/lib/Target/ARM/ARMSubtarget.cpp @@ -97,9 +97,9 @@ ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle, bool MinSize) - : ARMGenSubtargetInfo(TT, CPU, FS), UseMulOps(UseFusedMulOps), - CPUString(CPU), OptMinSize(MinSize), IsLittle(IsLittle), - TargetTriple(TT), Options(TM.Options), TM(TM), + : ARMGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), + UseMulOps(UseFusedMulOps), CPUString(CPU), OptMinSize(MinSize), + IsLittle(IsLittle), TargetTriple(TT), Options(TM.Options), TM(TM), FrameLowering(initializeFrameLowering(CPU, FS)), // At this point initializeSubtargetDependencies has been called so // we can query directly. @@ -185,7 +185,7 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { else ArchFS = std::string(FS); } - ParseSubtargetFeatures(CPUString, ArchFS); + ParseSubtargetFeatures(CPUString, /*TuneCPU*/ CPUString, ArchFS); // FIXME: This used enable V6T2 support implicitly for Thumb2 mode. // Assert this for now to make the change obvious. @@ -237,7 +237,7 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { switch (IT) { case DefaultIT: - RestrictIT = hasV8Ops(); + RestrictIT = hasV8Ops() && !hasMinSize(); break; case RestrictedIT: RestrictIT = true; @@ -294,11 +294,13 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { case CortexA76: case CortexA77: case CortexA78: + case CortexA78C: case CortexR4: case CortexR4F: case CortexR5: case CortexR7: case CortexM3: + case CortexM7: case CortexR52: case CortexX1: break; @@ -314,6 +316,8 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { PreISelOperandLatencyAdjustment = 1; break; case NeoverseN1: + case NeoverseN2: + case NeoverseV1: break; case Swift: MaxInterleaveFactor = 2; |