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-rw-r--r--contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp91
1 files changed, 46 insertions, 45 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
index c1d0599830cc..fcc880463925 100644
--- a/contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
+++ b/contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
@@ -174,6 +174,7 @@ namespace {
unsigned CoaCounter = 0;
unsigned TfrCounter = 0;
+ // FIXME: Consolidate duplicate definitions of RegisterRef
struct RegisterRef {
RegisterRef(const MachineOperand &Op) : Reg(Op.getReg()),
Sub(Op.getSubReg()) {}
@@ -187,7 +188,8 @@ namespace {
return Reg < RR.Reg || (Reg == RR.Reg && Sub < RR.Sub);
}
- unsigned Reg, Sub;
+ Register Reg;
+ unsigned Sub;
};
using ReferenceMap = DenseMap<unsigned, unsigned>;
@@ -196,25 +198,25 @@ namespace {
unsigned getMaskForSub(unsigned Sub);
bool isCondset(const MachineInstr &MI);
- LaneBitmask getLaneMask(unsigned Reg, unsigned Sub);
+ LaneBitmask getLaneMask(Register Reg, unsigned Sub);
void addRefToMap(RegisterRef RR, ReferenceMap &Map, unsigned Exec);
bool isRefInMap(RegisterRef, ReferenceMap &Map, unsigned Exec);
- void updateDeadsInRange(unsigned Reg, LaneBitmask LM, LiveRange &Range);
- void updateKillFlags(unsigned Reg);
- void updateDeadFlags(unsigned Reg);
- void recalculateLiveInterval(unsigned Reg);
+ void updateDeadsInRange(Register Reg, LaneBitmask LM, LiveRange &Range);
+ void updateKillFlags(Register Reg);
+ void updateDeadFlags(Register Reg);
+ void recalculateLiveInterval(Register Reg);
void removeInstr(MachineInstr &MI);
- void updateLiveness(std::set<unsigned> &RegSet, bool Recalc,
- bool UpdateKills, bool UpdateDeads);
+ void updateLiveness(std::set<Register> &RegSet, bool Recalc,
+ bool UpdateKills, bool UpdateDeads);
unsigned getCondTfrOpcode(const MachineOperand &SO, bool Cond);
MachineInstr *genCondTfrFor(MachineOperand &SrcOp,
MachineBasicBlock::iterator At, unsigned DstR,
unsigned DstSR, const MachineOperand &PredOp, bool PredSense,
bool ReadUndef, bool ImpUse);
- bool split(MachineInstr &MI, std::set<unsigned> &UpdRegs);
+ bool split(MachineInstr &MI, std::set<Register> &UpdRegs);
bool isPredicable(MachineInstr *MI);
MachineInstr *getReachingDefForPred(RegisterRef RD,
@@ -224,19 +226,18 @@ namespace {
void predicateAt(const MachineOperand &DefOp, MachineInstr &MI,
MachineBasicBlock::iterator Where,
const MachineOperand &PredOp, bool Cond,
- std::set<unsigned> &UpdRegs);
+ std::set<Register> &UpdRegs);
void renameInRange(RegisterRef RO, RegisterRef RN, unsigned PredR,
bool Cond, MachineBasicBlock::iterator First,
MachineBasicBlock::iterator Last);
- bool predicate(MachineInstr &TfrI, bool Cond, std::set<unsigned> &UpdRegs);
- bool predicateInBlock(MachineBasicBlock &B,
- std::set<unsigned> &UpdRegs);
+ bool predicate(MachineInstr &TfrI, bool Cond, std::set<Register> &UpdRegs);
+ bool predicateInBlock(MachineBasicBlock &B, std::set<Register> &UpdRegs);
bool isIntReg(RegisterRef RR, unsigned &BW);
bool isIntraBlocks(LiveInterval &LI);
bool coalesceRegisters(RegisterRef R1, RegisterRef R2);
- bool coalesceSegments(const SmallVectorImpl<MachineInstr*> &Condsets,
- std::set<unsigned> &UpdRegs);
+ bool coalesceSegments(const SmallVectorImpl<MachineInstr *> &Condsets,
+ std::set<Register> &UpdRegs);
};
} // end anonymous namespace
@@ -285,8 +286,8 @@ bool HexagonExpandCondsets::isCondset(const MachineInstr &MI) {
return false;
}
-LaneBitmask HexagonExpandCondsets::getLaneMask(unsigned Reg, unsigned Sub) {
- assert(Register::isVirtualRegister(Reg));
+LaneBitmask HexagonExpandCondsets::getLaneMask(Register Reg, unsigned Sub) {
+ assert(Reg.isVirtual());
return Sub != 0 ? TRI->getSubRegIndexLaneMask(Sub)
: MRI->getMaxLaneMaskForVReg(Reg);
}
@@ -312,7 +313,7 @@ bool HexagonExpandCondsets::isRefInMap(RegisterRef RR, ReferenceMap &Map,
return false;
}
-void HexagonExpandCondsets::updateKillFlags(unsigned Reg) {
+void HexagonExpandCondsets::updateKillFlags(Register Reg) {
auto KillAt = [this,Reg] (SlotIndex K, LaneBitmask LM) -> void {
// Set the <kill> flag on a use of Reg whose lane mask is contained in LM.
MachineInstr *MI = LIS->getInstructionFromIndex(K);
@@ -363,9 +364,9 @@ void HexagonExpandCondsets::updateKillFlags(unsigned Reg) {
}
}
-void HexagonExpandCondsets::updateDeadsInRange(unsigned Reg, LaneBitmask LM,
- LiveRange &Range) {
- assert(Register::isVirtualRegister(Reg));
+void HexagonExpandCondsets::updateDeadsInRange(Register Reg, LaneBitmask LM,
+ LiveRange &Range) {
+ assert(Reg.isVirtual());
if (Range.empty())
return;
@@ -374,7 +375,7 @@ void HexagonExpandCondsets::updateDeadsInRange(unsigned Reg, LaneBitmask LM,
if (!Op.isReg() || !Op.isDef())
return { false, false };
Register DR = Op.getReg(), DSR = Op.getSubReg();
- if (!Register::isVirtualRegister(DR) || DR != Reg)
+ if (!DR.isVirtual() || DR != Reg)
return { false, false };
LaneBitmask SLM = getLaneMask(DR, DSR);
LaneBitmask A = SLM & LM;
@@ -524,7 +525,7 @@ void HexagonExpandCondsets::updateDeadsInRange(unsigned Reg, LaneBitmask LM,
}
}
-void HexagonExpandCondsets::updateDeadFlags(unsigned Reg) {
+void HexagonExpandCondsets::updateDeadFlags(Register Reg) {
LiveInterval &LI = LIS->getInterval(Reg);
if (LI.hasSubRanges()) {
for (LiveInterval::SubRange &S : LI.subranges()) {
@@ -538,7 +539,7 @@ void HexagonExpandCondsets::updateDeadFlags(unsigned Reg) {
}
}
-void HexagonExpandCondsets::recalculateLiveInterval(unsigned Reg) {
+void HexagonExpandCondsets::recalculateLiveInterval(Register Reg) {
LIS->removeInterval(Reg);
LIS->createAndComputeVirtRegInterval(Reg);
}
@@ -548,12 +549,13 @@ void HexagonExpandCondsets::removeInstr(MachineInstr &MI) {
MI.eraseFromParent();
}
-void HexagonExpandCondsets::updateLiveness(std::set<unsigned> &RegSet,
- bool Recalc, bool UpdateKills, bool UpdateDeads) {
+void HexagonExpandCondsets::updateLiveness(std::set<Register> &RegSet,
+ bool Recalc, bool UpdateKills,
+ bool UpdateDeads) {
UpdateKills |= UpdateDeads;
- for (unsigned R : RegSet) {
- if (!Register::isVirtualRegister(R)) {
- assert(Register::isPhysicalRegister(R));
+ for (Register R : RegSet) {
+ if (!R.isVirtual()) {
+ assert(R.isPhysical());
// There shouldn't be any physical registers as operands, except
// possibly reserved registers.
assert(MRI->isReserved(R));
@@ -580,17 +582,16 @@ unsigned HexagonExpandCondsets::getCondTfrOpcode(const MachineOperand &SO,
using namespace Hexagon;
if (SO.isReg()) {
- Register PhysR;
+ MCRegister PhysR;
RegisterRef RS = SO;
- if (Register::isVirtualRegister(RS.Reg)) {
+ if (RS.Reg.isVirtual()) {
const TargetRegisterClass *VC = MRI->getRegClass(RS.Reg);
assert(VC->begin() != VC->end() && "Empty register class");
PhysR = *VC->begin();
} else {
- assert(Register::isPhysicalRegister(RS.Reg));
PhysR = RS.Reg;
}
- Register PhysS = (RS.Sub == 0) ? PhysR : TRI->getSubReg(PhysR, RS.Sub);
+ MCRegister PhysS = (RS.Sub == 0) ? PhysR : TRI->getSubReg(PhysR, RS.Sub);
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(PhysS);
switch (TRI->getRegSizeInBits(*RC)) {
case 32:
@@ -661,7 +662,7 @@ MachineInstr *HexagonExpandCondsets::genCondTfrFor(MachineOperand &SrcOp,
/// Replace a MUX instruction MI with a pair A2_tfrt/A2_tfrf. This function
/// performs all necessary changes to complete the replacement.
bool HexagonExpandCondsets::split(MachineInstr &MI,
- std::set<unsigned> &UpdRegs) {
+ std::set<Register> &UpdRegs) {
if (TfrLimitActive) {
if (TfrCounter >= TfrLimit)
return false;
@@ -803,7 +804,7 @@ bool HexagonExpandCondsets::canMoveOver(MachineInstr &MI, ReferenceMap &Defs,
// For physical register we would need to check register aliases, etc.
// and we don't want to bother with that. It would be of little value
// before the actual register rewriting (from virtual to physical).
- if (!Register::isVirtualRegister(RR.Reg))
+ if (!RR.Reg.isVirtual())
return false;
// No redefs for any operand.
if (isRefInMap(RR, Defs, Exec_Then))
@@ -855,7 +856,7 @@ void HexagonExpandCondsets::predicateAt(const MachineOperand &DefOp,
MachineInstr &MI,
MachineBasicBlock::iterator Where,
const MachineOperand &PredOp, bool Cond,
- std::set<unsigned> &UpdRegs) {
+ std::set<Register> &UpdRegs) {
// The problem with updating live intervals is that we can move one def
// past another def. In particular, this can happen when moving an A2_tfrt
// over an A2_tfrf defining the same register. From the point of view of
@@ -933,7 +934,7 @@ void HexagonExpandCondsets::renameInRange(RegisterRef RO, RegisterRef RN,
/// the copy under the given condition (using the same predicate register as
/// the copy).
bool HexagonExpandCondsets::predicate(MachineInstr &TfrI, bool Cond,
- std::set<unsigned> &UpdRegs) {
+ std::set<Register> &UpdRegs) {
// TfrI - A2_tfr[tf] Instruction (not A2_tfrsi).
unsigned Opc = TfrI.getOpcode();
(void)Opc;
@@ -1000,7 +1001,7 @@ bool HexagonExpandCondsets::predicate(MachineInstr &TfrI, bool Cond,
// subregisters are other physical registers, and we are not checking
// that.
RegisterRef RR = Op;
- if (!Register::isVirtualRegister(RR.Reg))
+ if (!RR.Reg.isVirtual())
return false;
ReferenceMap &Map = Op.isDef() ? Defs : Uses;
@@ -1067,7 +1068,7 @@ bool HexagonExpandCondsets::predicate(MachineInstr &TfrI, bool Cond,
/// Predicate all cases of conditional copies in the specified block.
bool HexagonExpandCondsets::predicateInBlock(MachineBasicBlock &B,
- std::set<unsigned> &UpdRegs) {
+ std::set<Register> &UpdRegs) {
bool Changed = false;
MachineBasicBlock::iterator I, E, NextI;
for (I = B.begin(), E = B.end(); I != E; I = NextI) {
@@ -1092,7 +1093,7 @@ bool HexagonExpandCondsets::predicateInBlock(MachineBasicBlock &B,
}
bool HexagonExpandCondsets::isIntReg(RegisterRef RR, unsigned &BW) {
- if (!Register::isVirtualRegister(RR.Reg))
+ if (!RR.Reg.isVirtual())
return false;
const TargetRegisterClass *RC = MRI->getRegClass(RR.Reg);
if (RC == &Hexagon::IntRegsRegClass) {
@@ -1172,7 +1173,7 @@ bool HexagonExpandCondsets::coalesceRegisters(RegisterRef R1, RegisterRef R2) {
}
L1.addSegment(LiveRange::Segment(I->start, I->end, NewVN));
}
- while (L2.begin() != L2.end())
+ while (!L2.empty())
L2.removeSegment(*L2.begin());
LIS->removeInterval(R2.Reg);
@@ -1187,8 +1188,8 @@ bool HexagonExpandCondsets::coalesceRegisters(RegisterRef R1, RegisterRef R2) {
/// the destination register. This could lead to having only one predicated
/// instruction in the end instead of two.
bool HexagonExpandCondsets::coalesceSegments(
- const SmallVectorImpl<MachineInstr*> &Condsets,
- std::set<unsigned> &UpdRegs) {
+ const SmallVectorImpl<MachineInstr *> &Condsets,
+ std::set<Register> &UpdRegs) {
SmallVector<MachineInstr*,16> TwoRegs;
for (MachineInstr *MI : Condsets) {
MachineOperand &S1 = MI->getOperand(2), &S2 = MI->getOperand(3);
@@ -1262,7 +1263,7 @@ bool HexagonExpandCondsets::runOnMachineFunction(MachineFunction &MF) {
MF.getFunction().getParent()));
bool Changed = false;
- std::set<unsigned> CoalUpd, PredUpd;
+ std::set<Register> CoalUpd, PredUpd;
SmallVector<MachineInstr*,16> Condsets;
for (auto &B : MF)
@@ -1279,7 +1280,7 @@ bool HexagonExpandCondsets::runOnMachineFunction(MachineFunction &MF) {
// in the IR (they have been removed by live range analysis).
// Updating them right before we split is the easiest, because splitting
// adds definitions which would interfere with updating kills afterwards.
- std::set<unsigned> KillUpd;
+ std::set<Register> KillUpd;
for (MachineInstr *MI : Condsets)
for (MachineOperand &Op : MI->operands())
if (Op.isReg() && Op.isUse())
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-30 19:43:29 +0000