diff options
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/Mips')
77 files changed, 1836 insertions, 757 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index e467ed36938b..9dbbdeb34dba 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -179,6 +179,8 @@ class MipsAsmParser : public MCTargetAsmParser { /// Parse a register as used in CFI directives bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; + OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc, + SMLoc &EndLoc) override; bool parseParenSuffix(StringRef Name, OperandVector &Operands); @@ -296,6 +298,12 @@ class MipsAsmParser : public MCTargetAsmParser { bool expandSgtImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI); + bool expandSle(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI); + + bool expandSleImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI); + bool expandRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI); bool expandRotationImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, @@ -332,6 +340,12 @@ class MipsAsmParser : public MCTargetAsmParser { bool expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI); + bool expandSne(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI); + + bool expandSneI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI); + bool expandMXTRAlias(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI); @@ -347,6 +361,7 @@ class MipsAsmParser : public MCTargetAsmParser { bool parseSetArchDirective(); bool parseSetFeature(uint64_t Feature); bool isPicAndNotNxxAbi(); // Used by .cpload, .cprestore, and .cpsetup. + bool parseDirectiveCpAdd(SMLoc Loc); bool parseDirectiveCpLoad(SMLoc Loc); bool parseDirectiveCpLocal(SMLoc Loc); bool parseDirectiveCpRestore(SMLoc Loc); @@ -366,6 +381,7 @@ class MipsAsmParser : public MCTargetAsmParser { bool parseSetMsaDirective(); bool parseSetNoMsaDirective(); bool parseSetNoDspDirective(); + bool parseSetNoMips3DDirective(); bool parseSetReorderDirective(); bool parseSetNoReorderDirective(); bool parseSetMips16Directive(); @@ -2126,10 +2142,10 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, MCSymbolRefExpr::create(JalSym, MCSymbolRefExpr::VK_None, getContext(), IDLoc); - TOut.getStreamer().EmitRelocDirective(*TmpExpr, - inMicroMipsMode() ? "R_MICROMIPS_JALR" : "R_MIPS_JALR", + TOut.getStreamer().emitRelocDirective( + *TmpExpr, inMicroMipsMode() ? "R_MICROMIPS_JALR" : "R_MIPS_JALR", RelocJalrExpr, IDLoc, *STI); - TOut.getStreamer().EmitLabel(TmpLabel); + TOut.getStreamer().emitLabel(TmpLabel); } Inst = JalrInst; @@ -2311,7 +2327,7 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, tryExpandInstruction(Inst, IDLoc, Out, STI); switch (ExpandResult) { case MER_NotAMacro: - Out.EmitInstruction(Inst, *STI); + Out.emitInstruction(Inst, *STI); break; case MER_Success: break; @@ -2512,6 +2528,14 @@ MipsAsmParser::tryExpandInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, case Mips::SGTImm64: case Mips::SGTUImm64: return expandSgtImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; + case Mips::SLE: + case Mips::SLEU: + return expandSle(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; + case Mips::SLEImm: + case Mips::SLEUImm: + case Mips::SLEImm64: + case Mips::SLEUImm64: + return expandSleImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; case Mips::SLTImm64: if (isInt<16>(Inst.getOperand(2).getImm())) { Inst.setOpcode(Mips::SLTi64); @@ -2588,6 +2612,10 @@ MipsAsmParser::tryExpandInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, return expandSeq(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; case Mips::SEQIMacro: return expandSeqI(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; + case Mips::SNEMacro: + return expandSne(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; + case Mips::SNEIMacro: + return expandSneI(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; case Mips::MFTC0: case Mips::MTTC0: case Mips::MFTGPR: case Mips::MTTGPR: case Mips::MFTLO: case Mips::MTTLO: @@ -2638,7 +2666,7 @@ bool MipsAsmParser::expandJalWithRegs(MCInst &Inst, SMLoc IDLoc, const MCOperand SecondRegOp = Inst.getOperand(1); JalrInst.addOperand(SecondRegOp); } - Out.EmitInstruction(JalrInst, *STI); + Out.emitInstruction(JalrInst, *STI); // If .set reorder is active and branch instruction has a delay slot, // emit a NOP after it. @@ -3386,8 +3414,8 @@ bool MipsAsmParser::expandLoadSingleImmToFPR(MCInst &Inst, SMLoc IDLoc, MipsMCExpr::create(MipsMCExpr::MEK_LO, LoSym, getContext()); getStreamer().SwitchSection(ReadOnlySection); - getStreamer().EmitLabel(Sym, IDLoc); - getStreamer().EmitIntValue(ImmOp32, 4); + getStreamer().emitLabel(Sym, IDLoc); + getStreamer().emitInt32(ImmOp32); getStreamer().SwitchSection(CS); if (emitPartialAddress(TOut, IDLoc, Sym)) @@ -3438,9 +3466,9 @@ bool MipsAsmParser::expandLoadDoubleImmToGPR(MCInst &Inst, SMLoc IDLoc, MipsMCExpr::create(MipsMCExpr::MEK_LO, LoSym, getContext()); getStreamer().SwitchSection(ReadOnlySection); - getStreamer().EmitLabel(Sym, IDLoc); - getStreamer().EmitValueToAlignment(8); - getStreamer().EmitIntValue(ImmOp64, 8); + getStreamer().emitLabel(Sym, IDLoc); + getStreamer().emitValueToAlignment(8); + getStreamer().emitIntValue(ImmOp64, 8); getStreamer().SwitchSection(CS); unsigned TmpReg = getATReg(IDLoc); @@ -3521,9 +3549,9 @@ bool MipsAsmParser::expandLoadDoubleImmToFPR(MCInst &Inst, bool Is64FPU, MipsMCExpr::create(MipsMCExpr::MEK_LO, LoSym, getContext()); getStreamer().SwitchSection(ReadOnlySection); - getStreamer().EmitLabel(Sym, IDLoc); - getStreamer().EmitValueToAlignment(8); - getStreamer().EmitIntValue(ImmOp64, 8); + getStreamer().emitLabel(Sym, IDLoc); + getStreamer().emitValueToAlignment(8); + getStreamer().emitIntValue(ImmOp64, 8); getStreamer().SwitchSection(CS); if (emitPartialAddress(TOut, IDLoc, Sym)) @@ -3569,7 +3597,7 @@ bool MipsAsmParser::expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc, Inst.addOperand(MCOperand::createImm(Offset.getImm())); } } - Out.EmitInstruction(Inst, *STI); + Out.emitInstruction(Inst, *STI); // If .set reorder is active and branch instruction has a delay slot, // emit a NOP after it. @@ -3856,7 +3884,7 @@ bool MipsAsmParser::expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc, } Inst.setOpcode(NewOpcode); - Out.EmitInstruction(Inst, *STI); + Out.emitInstruction(Inst, *STI); return false; } @@ -4258,7 +4286,7 @@ bool MipsAsmParser::expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, if (!Signed) { if (!UseTraps) - TOut.getStreamer().EmitLabel(BrTarget); + TOut.getStreamer().emitLabel(BrTarget); TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI); return false; @@ -4269,7 +4297,7 @@ bool MipsAsmParser::expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, return true; if (!UseTraps) - TOut.getStreamer().EmitLabel(BrTarget); + TOut.getStreamer().emitLabel(BrTarget); TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, -1, IDLoc, STI); @@ -4297,7 +4325,7 @@ bool MipsAsmParser::expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, TOut.emitII(Mips::BREAK, 0x6, 0, IDLoc, STI); } - TOut.getStreamer().EmitLabel(BrTargetEnd); + TOut.getStreamer().emitLabel(BrTargetEnd); TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI); return false; } @@ -4636,6 +4664,88 @@ bool MipsAsmParser::expandSgtImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, return false; } +bool MipsAsmParser::expandSle(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI) { + MipsTargetStreamer &TOut = getTargetStreamer(); + + assert(Inst.getNumOperands() == 3 && "Invalid operand count"); + assert(Inst.getOperand(0).isReg() && + Inst.getOperand(1).isReg() && + Inst.getOperand(2).isReg() && "Invalid instruction operand."); + + unsigned DstReg = Inst.getOperand(0).getReg(); + unsigned SrcReg = Inst.getOperand(1).getReg(); + unsigned OpReg = Inst.getOperand(2).getReg(); + unsigned OpCode; + + warnIfNoMacro(IDLoc); + + switch (Inst.getOpcode()) { + case Mips::SLE: + OpCode = Mips::SLT; + break; + case Mips::SLEU: + OpCode = Mips::SLTu; + break; + default: + llvm_unreachable("unexpected 'sge' opcode"); + } + + // $SrcReg <= $OpReg is equal to (not ($OpReg < $SrcReg)) + TOut.emitRRR(OpCode, DstReg, OpReg, SrcReg, IDLoc, STI); + TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI); + + return false; +} + +bool MipsAsmParser::expandSleImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI) { + MipsTargetStreamer &TOut = getTargetStreamer(); + + assert(Inst.getNumOperands() == 3 && "Invalid operand count"); + assert(Inst.getOperand(0).isReg() && + Inst.getOperand(1).isReg() && + Inst.getOperand(2).isImm() && "Invalid instruction operand."); + + unsigned DstReg = Inst.getOperand(0).getReg(); + unsigned SrcReg = Inst.getOperand(1).getReg(); + int64_t ImmValue = Inst.getOperand(2).getImm(); + unsigned OpRegCode; + + warnIfNoMacro(IDLoc); + + switch (Inst.getOpcode()) { + case Mips::SLEImm: + case Mips::SLEImm64: + OpRegCode = Mips::SLT; + break; + case Mips::SLEUImm: + case Mips::SLEUImm64: + OpRegCode = Mips::SLTu; + break; + default: + llvm_unreachable("unexpected 'sge' opcode with immediate"); + } + + // $SrcReg <= Imm is equal to (not (Imm < $SrcReg)) + unsigned ImmReg = DstReg; + if (DstReg == SrcReg) { + unsigned ATReg = getATReg(Inst.getLoc()); + if (!ATReg) + return true; + ImmReg = ATReg; + } + + if (loadImmediate(ImmValue, ImmReg, Mips::NoRegister, isInt<32>(ImmValue), + false, IDLoc, Out, STI)) + return true; + + TOut.emitRRR(OpRegCode, DstReg, ImmReg, SrcReg, IDLoc, STI); + TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI); + + return false; +} + bool MipsAsmParser::expandAliasImmediate(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { @@ -5099,7 +5209,7 @@ bool MipsAsmParser::expandMulO(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, TOut.emitNop(IDLoc, STI); TOut.emitII(Mips::BREAK, 6, 0, IDLoc, STI); - TOut.getStreamer().EmitLabel(BrTarget); + TOut.getStreamer().emitLabel(BrTarget); } TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); @@ -5136,7 +5246,7 @@ bool MipsAsmParser::expandMulOU(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, TOut.emitNop(IDLoc, STI); TOut.emitII(Mips::BREAK, 6, 0, IDLoc, STI); - TOut.getStreamer().EmitLabel(BrTarget); + TOut.getStreamer().emitLabel(BrTarget); } return false; @@ -5325,6 +5435,88 @@ bool MipsAsmParser::expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, return false; } +bool MipsAsmParser::expandSne(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI) { + + MipsTargetStreamer &TOut = getTargetStreamer(); + + assert(Inst.getNumOperands() == 3 && "Invalid operand count"); + assert(Inst.getOperand(0).isReg() && + Inst.getOperand(1).isReg() && + Inst.getOperand(2).isReg() && "Invalid instruction operand."); + + unsigned DstReg = Inst.getOperand(0).getReg(); + unsigned SrcReg = Inst.getOperand(1).getReg(); + unsigned OpReg = Inst.getOperand(2).getReg(); + + warnIfNoMacro(IDLoc); + + if (SrcReg != Mips::ZERO && OpReg != Mips::ZERO) { + TOut.emitRRR(Mips::XOR, DstReg, SrcReg, OpReg, IDLoc, STI); + TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, DstReg, IDLoc, STI); + return false; + } + + unsigned Reg = SrcReg == Mips::ZERO ? OpReg : SrcReg; + TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, Reg, IDLoc, STI); + return false; +} + +bool MipsAsmParser::expandSneI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI) { + MipsTargetStreamer &TOut = getTargetStreamer(); + + assert(Inst.getNumOperands() == 3 && "Invalid operand count"); + assert(Inst.getOperand(0).isReg() && + Inst.getOperand(1).isReg() && + Inst.getOperand(2).isImm() && "Invalid instruction operand."); + + unsigned DstReg = Inst.getOperand(0).getReg(); + unsigned SrcReg = Inst.getOperand(1).getReg(); + int64_t ImmValue = Inst.getOperand(2).getImm(); + + warnIfNoMacro(IDLoc); + + if (ImmValue == 0) { + TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, SrcReg, IDLoc, STI); + return false; + } + + if (SrcReg == Mips::ZERO) { + Warning(IDLoc, "comparison is always true"); + if (loadImmediate(1, DstReg, Mips::NoRegister, true, false, IDLoc, Out, + STI)) + return true; + return false; + } + + unsigned Opc; + if (ImmValue > -0x8000 && ImmValue < 0) { + ImmValue = -ImmValue; + Opc = isGP64bit() ? Mips::DADDiu : Mips::ADDiu; + } else { + Opc = Mips::XORi; + } + + if (isUInt<16>(ImmValue)) { + TOut.emitRRI(Opc, DstReg, SrcReg, ImmValue, IDLoc, STI); + TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, DstReg, IDLoc, STI); + return false; + } + + unsigned ATReg = getATReg(IDLoc); + if (!ATReg) + return true; + + if (loadImmediate(ImmValue, ATReg, Mips::NoRegister, isInt<32>(ImmValue), + false, IDLoc, Out, STI)) + return true; + + TOut.emitRRR(Mips::XOR, DstReg, SrcReg, ATReg, IDLoc, STI); + TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, DstReg, IDLoc, STI); + return false; +} + // Map the DSP accumulator and control register to the corresponding gpr // operand. Unlike the other alias, the m(f|t)t(lo|hi|acx) instructions // do not map the DSP registers contigously to gpr registers. @@ -6202,6 +6394,12 @@ bool MipsAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) { bool MipsAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { + return tryParseRegister(RegNo, StartLoc, EndLoc) != MatchOperand_Success; +} + +OperandMatchResultTy MipsAsmParser::tryParseRegister(unsigned &RegNo, + SMLoc &StartLoc, + SMLoc &EndLoc) { SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands; OperandMatchResultTy ResTy = parseAnyRegister(Operands); if (ResTy == MatchOperand_Success) { @@ -6219,11 +6417,12 @@ bool MipsAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, RegNo = isGP64bit() ? Operand.getGPR64Reg() : Operand.getGPR32Reg(); } - return (RegNo == (unsigned)-1); + return (RegNo == (unsigned)-1) ? MatchOperand_NoMatch + : MatchOperand_Success; } assert(Operands.size() == 0); - return (RegNo == (unsigned)-1); + return (RegNo == (unsigned)-1) ? MatchOperand_NoMatch : MatchOperand_Success; } bool MipsAsmParser::parseMemOffset(const MCExpr *&Res, bool isParenExpr) { @@ -6976,6 +7175,21 @@ bool MipsAsmParser::parseSetNoDspDirective() { return false; } +bool MipsAsmParser::parseSetNoMips3DDirective() { + MCAsmParser &Parser = getParser(); + Parser.Lex(); // Eat "nomips3d". + + // If this is not the end of the statement, report an error. + if (getLexer().isNot(AsmToken::EndOfStatement)) { + reportParseError("unexpected token, expected end of statement"); + return false; + } + + clearFeatureBits(Mips::FeatureMips3D, "mips3d"); + getTargetStreamer().emitDirectiveSetNoMips3D(); + return false; +} + bool MipsAsmParser::parseSetMips16Directive() { MCAsmParser &Parser = getParser(); Parser.Lex(); // Eat "mips16". @@ -7308,6 +7522,10 @@ bool MipsAsmParser::parseSetFeature(uint64_t Feature) { switch (Feature) { default: llvm_unreachable("Unimplemented feature"); + case Mips::FeatureMips3D: + setFeatureBits(Mips::FeatureMips3D, "mips3d"); + getTargetStreamer().emitDirectiveSetMips3D(); + break; case Mips::FeatureDSP: setFeatureBits(Mips::FeatureDSP, "dsp"); getTargetStreamer().emitDirectiveSetDsp(); @@ -7415,6 +7633,31 @@ bool MipsAsmParser::isPicAndNotNxxAbi() { return inPicMode() && !(isABI_N32() || isABI_N64()); } +bool MipsAsmParser::parseDirectiveCpAdd(SMLoc Loc) { + SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Reg; + OperandMatchResultTy ResTy = parseAnyRegister(Reg); + if (ResTy == MatchOperand_NoMatch || ResTy == MatchOperand_ParseFail) { + reportParseError("expected register"); + return false; + } + + MipsOperand &RegOpnd = static_cast<MipsOperand &>(*Reg[0]); + if (!RegOpnd.isGPRAsmReg()) { + reportParseError(RegOpnd.getStartLoc(), "invalid register"); + return false; + } + + // If this is not the end of the statement, report an error. + if (getLexer().isNot(AsmToken::EndOfStatement)) { + reportParseError("unexpected token, expected end of statement"); + return false; + } + getParser().Lex(); // Consume the EndOfStatement. + + getTargetStreamer().emitDirectiveCpAdd(RegOpnd.getGPR32Reg()); + return false; +} + bool MipsAsmParser::parseDirectiveCpLoad(SMLoc Loc) { if (AssemblerOptions.back()->isReorder()) Warning(Loc, ".cpload should be inside a noreorder section"); @@ -7723,6 +7966,10 @@ bool MipsAsmParser::parseDirectiveSet() { return parseSetFeature(Mips::FeatureDSPR2); if (IdVal == "nodsp") return parseSetNoDspDirective(); + if (IdVal == "mips3d") + return parseSetFeature(Mips::FeatureMips3D); + if (IdVal == "nomips3d") + return parseSetNoMips3DDirective(); if (IdVal == "msa") return parseSetMsaDirective(); if (IdVal == "nomsa") @@ -7761,7 +8008,7 @@ bool MipsAsmParser::parseDirectiveGpWord() { // method to evaluate the expression. if (getParser().parseExpression(Value)) return true; - getParser().getStreamer().EmitGPRel32Value(Value); + getParser().getStreamer().emitGPRel32Value(Value); if (getLexer().isNot(AsmToken::EndOfStatement)) return Error(getLexer().getLoc(), @@ -7779,7 +8026,7 @@ bool MipsAsmParser::parseDirectiveGpDWord() { // method to evaluate the expression. if (getParser().parseExpression(Value)) return true; - getParser().getStreamer().EmitGPRel64Value(Value); + getParser().getStreamer().emitGPRel64Value(Value); if (getLexer().isNot(AsmToken::EndOfStatement)) return Error(getLexer().getLoc(), @@ -7797,7 +8044,7 @@ bool MipsAsmParser::parseDirectiveDtpRelWord() { // method to evaluate the expression. if (getParser().parseExpression(Value)) return true; - getParser().getStreamer().EmitDTPRel32Value(Value); + getParser().getStreamer().emitDTPRel32Value(Value); if (getLexer().isNot(AsmToken::EndOfStatement)) return Error(getLexer().getLoc(), @@ -7815,7 +8062,7 @@ bool MipsAsmParser::parseDirectiveDtpRelDWord() { // method to evaluate the expression. if (getParser().parseExpression(Value)) return true; - getParser().getStreamer().EmitDTPRel64Value(Value); + getParser().getStreamer().emitDTPRel64Value(Value); if (getLexer().isNot(AsmToken::EndOfStatement)) return Error(getLexer().getLoc(), @@ -7833,7 +8080,7 @@ bool MipsAsmParser::parseDirectiveTpRelWord() { // method to evaluate the expression. if (getParser().parseExpression(Value)) return true; - getParser().getStreamer().EmitTPRel32Value(Value); + getParser().getStreamer().emitTPRel32Value(Value); if (getLexer().isNot(AsmToken::EndOfStatement)) return Error(getLexer().getLoc(), @@ -7851,7 +8098,7 @@ bool MipsAsmParser::parseDirectiveTpRelDWord() { // method to evaluate the expression. if (getParser().parseExpression(Value)) return true; - getParser().getStreamer().EmitTPRel64Value(Value); + getParser().getStreamer().emitTPRel64Value(Value); if (getLexer().isNot(AsmToken::EndOfStatement)) return Error(getLexer().getLoc(), @@ -8323,6 +8570,10 @@ bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) { MCAsmParser &Parser = getParser(); StringRef IDVal = DirectiveID.getString(); + if (IDVal == ".cpadd") { + parseDirectiveCpAdd(DirectiveID.getLoc()); + return false; + } if (IDVal == ".cpload") { parseDirectiveCpLoad(DirectiveID.getLoc()); return false; diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.cpp index fca1149453c9..c5a1a3e6286e 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.cpp @@ -57,17 +57,17 @@ namespace llvm { MCStreamer &operator<<(MCStreamer &OS, MipsABIFlagsSection &ABIFlagsSection) { // Write out a Elf_Internal_ABIFlags_v0 struct - OS.EmitIntValue(ABIFlagsSection.getVersionValue(), 2); // version - OS.EmitIntValue(ABIFlagsSection.getISALevelValue(), 1); // isa_level - OS.EmitIntValue(ABIFlagsSection.getISARevisionValue(), 1); // isa_rev - OS.EmitIntValue(ABIFlagsSection.getGPRSizeValue(), 1); // gpr_size - OS.EmitIntValue(ABIFlagsSection.getCPR1SizeValue(), 1); // cpr1_size - OS.EmitIntValue(ABIFlagsSection.getCPR2SizeValue(), 1); // cpr2_size - OS.EmitIntValue(ABIFlagsSection.getFpABIValue(), 1); // fp_abi - OS.EmitIntValue(ABIFlagsSection.getISAExtensionValue(), 4); // isa_ext - OS.EmitIntValue(ABIFlagsSection.getASESetValue(), 4); // ases - OS.EmitIntValue(ABIFlagsSection.getFlags1Value(), 4); // flags1 - OS.EmitIntValue(ABIFlagsSection.getFlags2Value(), 4); // flags2 + OS.emitIntValue(ABIFlagsSection.getVersionValue(), 2); // version + OS.emitIntValue(ABIFlagsSection.getISALevelValue(), 1); // isa_level + OS.emitIntValue(ABIFlagsSection.getISARevisionValue(), 1); // isa_rev + OS.emitIntValue(ABIFlagsSection.getGPRSizeValue(), 1); // gpr_size + OS.emitIntValue(ABIFlagsSection.getCPR1SizeValue(), 1); // cpr1_size + OS.emitIntValue(ABIFlagsSection.getCPR2SizeValue(), 1); // cpr2_size + OS.emitIntValue(ABIFlagsSection.getFpABIValue(), 1); // fp_abi + OS.emitIntValue(ABIFlagsSection.getISAExtensionValue(), 4); // isa_ext + OS.emitIntValue(ABIFlagsSection.getASESetValue(), 4); // ases + OS.emitIntValue(ABIFlagsSection.getFlags1Value(), 4); // flags1 + OS.emitIntValue(ABIFlagsSection.getFlags2Value(), 4); // flags2 return OS; } diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h b/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h index 534e6573b63c..046cc686b311 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h @@ -18,7 +18,6 @@ namespace llvm { template <typename T> class ArrayRef; class MCTargetOptions; class StringRef; -class TargetRegisterClass; class MipsABIInfo { public: diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h b/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h index cca75dfc45c2..1126b871cb11 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h @@ -22,9 +22,7 @@ namespace llvm { class MCAssembler; struct MCFixupKindInfo; -class MCObjectWriter; class MCRegisterInfo; -class MCSymbolELF; class Target; class MipsAsmBackend : public MCAsmBackend { @@ -74,17 +72,6 @@ public: return false; } - /// RelaxInstruction - Relax the instruction in the given fragment - /// to the next wider instruction. - /// - /// \param Inst - The instruction to relax, which may be the same - /// as the output. - /// \param [out] Res On return, the relaxed instruction. - void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, - MCInst &Res) const override {} - - /// @} - bool writeNopData(raw_ostream &OS, uint64_t Count) const override; bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp index cc3168790b98..9c317e3f8840 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp @@ -234,14 +234,15 @@ unsigned MipsELFObjectWriter::getRelocType(MCContext &Ctx, case Mips::fixup_Mips_32: case FK_Data_4: return IsPCRel ? ELF::R_MIPS_PC32 : ELF::R_MIPS_32; + case Mips::fixup_Mips_64: + case FK_Data_8: + return IsPCRel + ? setRTypes(ELF::R_MIPS_PC32, ELF::R_MIPS_64, ELF::R_MIPS_NONE) + : (unsigned)ELF::R_MIPS_64; } if (IsPCRel) { switch (Kind) { - case FK_Data_8: - Ctx.reportError(Fixup.getLoc(), - "MIPS does not support 64-bit PC-relative relocations"); - return ELF::R_MIPS_NONE; case Mips::fixup_Mips_Branch_PCRel: case Mips::fixup_Mips_PC16: return ELF::R_MIPS_PC16; @@ -277,9 +278,6 @@ unsigned MipsELFObjectWriter::getRelocType(MCContext &Ctx, } switch (Kind) { - case Mips::fixup_Mips_64: - case FK_Data_8: - return ELF::R_MIPS_64; case FK_DTPRel_4: return ELF::R_MIPS_TLS_DTPREL32; case FK_DTPRel_8: @@ -289,14 +287,9 @@ unsigned MipsELFObjectWriter::getRelocType(MCContext &Ctx, case FK_TPRel_8: return ELF::R_MIPS_TLS_TPREL64; case FK_GPRel_4: - if (is64Bit()) { - unsigned Type = (unsigned)ELF::R_MIPS_NONE; - Type = setRType((unsigned)ELF::R_MIPS_GPREL32, Type); - Type = setRType2((unsigned)ELF::R_MIPS_64, Type); - Type = setRType3((unsigned)ELF::R_MIPS_NONE, Type); - return Type; - } - return ELF::R_MIPS_GPREL32; + return setRTypes(ELF::R_MIPS_GPREL32, + is64Bit() ? ELF::R_MIPS_64 : ELF::R_MIPS_NONE, + ELF::R_MIPS_NONE); case Mips::fixup_Mips_GPREL16: return ELF::R_MIPS_GPREL16; case Mips::fixup_Mips_26: @@ -329,34 +322,16 @@ unsigned MipsELFObjectWriter::getRelocType(MCContext &Ctx, return ELF::R_MIPS_GOT_OFST; case Mips::fixup_Mips_GOT_DISP: return ELF::R_MIPS_GOT_DISP; - case Mips::fixup_Mips_GPOFF_HI: { - unsigned Type = (unsigned)ELF::R_MIPS_NONE; - Type = setRType((unsigned)ELF::R_MIPS_GPREL16, Type); - Type = setRType2((unsigned)ELF::R_MIPS_SUB, Type); - Type = setRType3((unsigned)ELF::R_MIPS_HI16, Type); - return Type; - } - case Mips::fixup_MICROMIPS_GPOFF_HI: { - unsigned Type = (unsigned)ELF::R_MIPS_NONE; - Type = setRType((unsigned)ELF::R_MICROMIPS_GPREL16, Type); - Type = setRType2((unsigned)ELF::R_MICROMIPS_SUB, Type); - Type = setRType3((unsigned)ELF::R_MICROMIPS_HI16, Type); - return Type; - } - case Mips::fixup_Mips_GPOFF_LO: { - unsigned Type = (unsigned)ELF::R_MIPS_NONE; - Type = setRType((unsigned)ELF::R_MIPS_GPREL16, Type); - Type = setRType2((unsigned)ELF::R_MIPS_SUB, Type); - Type = setRType3((unsigned)ELF::R_MIPS_LO16, Type); - return Type; - } - case Mips::fixup_MICROMIPS_GPOFF_LO: { - unsigned Type = (unsigned)ELF::R_MIPS_NONE; - Type = setRType((unsigned)ELF::R_MICROMIPS_GPREL16, Type); - Type = setRType2((unsigned)ELF::R_MICROMIPS_SUB, Type); - Type = setRType3((unsigned)ELF::R_MICROMIPS_LO16, Type); - return Type; - } + case Mips::fixup_Mips_GPOFF_HI: + return setRTypes(ELF::R_MIPS_GPREL16, ELF::R_MIPS_SUB, ELF::R_MIPS_HI16); + case Mips::fixup_MICROMIPS_GPOFF_HI: + return setRTypes(ELF::R_MICROMIPS_GPREL16, ELF::R_MICROMIPS_SUB, + ELF::R_MICROMIPS_HI16); + case Mips::fixup_Mips_GPOFF_LO: + return setRTypes(ELF::R_MIPS_GPREL16, ELF::R_MIPS_SUB, ELF::R_MIPS_LO16); + case Mips::fixup_MICROMIPS_GPOFF_LO: + return setRTypes(ELF::R_MICROMIPS_GPREL16, ELF::R_MICROMIPS_SUB, + ELF::R_MICROMIPS_LO16); case Mips::fixup_Mips_HIGHER: return ELF::R_MIPS_HIGHER; case Mips::fixup_Mips_HIGHEST: diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp index 1b83e9445fb5..e6e32ec7f27c 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp @@ -33,9 +33,9 @@ MipsELFStreamer::MipsELFStreamer(MCContext &Context, std::unique_ptr<MipsRegInfoRecord>(RegInfoRecord)); } -void MipsELFStreamer::EmitInstruction(const MCInst &Inst, +void MipsELFStreamer::emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) { - MCELFStreamer::EmitInstruction(Inst, STI); + MCELFStreamer::emitInstruction(Inst, STI); MCContext &Context = getContext(); const MCRegisterInfo *MCRegInfo = Context.getRegisterInfo(); @@ -53,20 +53,20 @@ void MipsELFStreamer::EmitInstruction(const MCInst &Inst, createPendingLabelRelocs(); } -void MipsELFStreamer::EmitCFIStartProcImpl(MCDwarfFrameInfo &Frame) { +void MipsELFStreamer::emitCFIStartProcImpl(MCDwarfFrameInfo &Frame) { Frame.Begin = getContext().createTempSymbol(); - MCELFStreamer::EmitLabel(Frame.Begin); + MCELFStreamer::emitLabel(Frame.Begin); } -MCSymbol *MipsELFStreamer::EmitCFILabel() { +MCSymbol *MipsELFStreamer::emitCFILabel() { MCSymbol *Label = getContext().createTempSymbol("cfi", true); - MCELFStreamer::EmitLabel(Label); + MCELFStreamer::emitLabel(Label); return Label; } -void MipsELFStreamer::EmitCFIEndProcImpl(MCDwarfFrameInfo &Frame) { +void MipsELFStreamer::emitCFIEndProcImpl(MCDwarfFrameInfo &Frame) { Frame.End = getContext().createTempSymbol(); - MCELFStreamer::EmitLabel(Frame.End); + MCELFStreamer::emitLabel(Frame.End); } void MipsELFStreamer::createPendingLabelRelocs() { @@ -85,8 +85,8 @@ void MipsELFStreamer::createPendingLabelRelocs() { Labels.clear(); } -void MipsELFStreamer::EmitLabel(MCSymbol *Symbol, SMLoc Loc) { - MCELFStreamer::EmitLabel(Symbol); +void MipsELFStreamer::emitLabel(MCSymbol *Symbol, SMLoc Loc) { + MCELFStreamer::emitLabel(Symbol); Labels.push_back(Symbol); } @@ -96,14 +96,14 @@ void MipsELFStreamer::SwitchSection(MCSection *Section, Labels.clear(); } -void MipsELFStreamer::EmitValueImpl(const MCExpr *Value, unsigned Size, +void MipsELFStreamer::emitValueImpl(const MCExpr *Value, unsigned Size, SMLoc Loc) { - MCELFStreamer::EmitValueImpl(Value, Size, Loc); + MCELFStreamer::emitValueImpl(Value, Size, Loc); Labels.clear(); } -void MipsELFStreamer::EmitIntValue(uint64_t Value, unsigned Size) { - MCELFStreamer::EmitIntValue(Value, Size); +void MipsELFStreamer::emitIntValue(uint64_t Value, unsigned Size) { + MCELFStreamer::emitIntValue(Value, Size); Labels.clear(); } diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h b/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h index 2febfbc69b6f..f6a2c039c0c3 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h @@ -41,12 +41,12 @@ public: /// \p Inst is actually emitted. For example, we can inspect the operands and /// gather sufficient information that allows us to reason about the register /// usage for the translation unit. - void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override; + void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override; /// Overriding this function allows us to record all labels that should be /// marked as microMIPS. Based on this data marking is done in /// EmitInstruction. - void EmitLabel(MCSymbol *Symbol, SMLoc Loc = SMLoc()) override; + void emitLabel(MCSymbol *Symbol, SMLoc Loc = SMLoc()) override; /// Overriding this function allows us to dismiss all labels that are /// candidates for marking as microMIPS when .section directive is processed. @@ -56,14 +56,14 @@ public: /// Overriding these functions allows us to dismiss all labels that are /// candidates for marking as microMIPS when .word/.long/.4byte etc /// directives are emitted. - void EmitValueImpl(const MCExpr *Value, unsigned Size, SMLoc Loc) override; - void EmitIntValue(uint64_t Value, unsigned Size) override; + void emitValueImpl(const MCExpr *Value, unsigned Size, SMLoc Loc) override; + void emitIntValue(uint64_t Value, unsigned Size) override; // Overriding these functions allows us to avoid recording of these labels // in EmitLabel and later marking them as microMIPS. - void EmitCFIStartProcImpl(MCDwarfFrameInfo &Frame) override; - void EmitCFIEndProcImpl(MCDwarfFrameInfo &Frame) override; - MCSymbol *EmitCFILabel() override; + void emitCFIStartProcImpl(MCDwarfFrameInfo &Frame) override; + void emitCFIEndProcImpl(MCDwarfFrameInfo &Frame) override; + MCSymbol *emitCFILabel() override; /// Emits all the option records stored up until the point it's called. void EmitMipsOptionRecords(); diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp index 649ba20324bf..3700d6309e1a 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp @@ -109,7 +109,7 @@ void MipsInstPrinter::printInst(const MCInst *MI, uint64_t Address, } // Try to print any aliases first. - if (!printAliasInstr(MI, O) && !printAlias(*MI, O)) + if (!printAliasInstr(MI, Address, O) && !printAlias(*MI, O)) printInstruction(MI, Address, O); printAnnotation(O, Annot); diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h b/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h index 0b1ee800e440..3f534a2f1843 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h @@ -86,12 +86,17 @@ public: void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &O) override; - bool printAliasInstr(const MCInst *MI, raw_ostream &OS); - void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, - unsigned PrintMethodIdx, raw_ostream &O); + bool printAliasInstr(const MCInst *MI, uint64_t Address, raw_ostream &OS); + void printCustomAliasOperand(const MCInst *MI, uint64_t Address, + unsigned OpIdx, unsigned PrintMethodIdx, + raw_ostream &O); private: void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); + void printOperand(const MCInst *MI, uint64_t /*Address*/, unsigned OpNum, + raw_ostream &O) { + printOperand(MI, OpNum, O); + } template <unsigned Bits, unsigned Offset = 0> void printUImm(const MCInst *MI, int opNum, raw_ostream &O); void printMemOperand(const MCInst *MI, int opNum, raw_ostream &O); diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp index 5182205edaea..9c85a39bc348 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp @@ -50,5 +50,4 @@ MipsMCAsmInfo::MipsMCAsmInfo(const Triple &TheTriple, ExceptionsType = ExceptionHandling::DwarfCFI; DwarfRegNumForCFI = true; HasMipsExpressions = true; - UseIntegratedAssembler = true; } diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp index 846f508005f5..9de34cc0e787 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp @@ -129,7 +129,7 @@ void MipsMCCodeEmitter::EmitByte(unsigned char C, raw_ostream &OS) const { OS << (char)C; } -void MipsMCCodeEmitter::EmitInstruction(uint64_t Val, unsigned Size, +void MipsMCCodeEmitter::emitInstruction(uint64_t Val, unsigned Size, const MCSubtargetInfo &STI, raw_ostream &OS) const { // Output the instruction encoding in little endian byte order. @@ -137,8 +137,8 @@ void MipsMCCodeEmitter::EmitInstruction(uint64_t Val, unsigned Size, // mips32r2: 4 | 3 | 2 | 1 // microMIPS: 2 | 1 | 4 | 3 if (IsLittleEndian && Size == 4 && isMicroMips(STI)) { - EmitInstruction(Val >> 16, 2, STI, OS); - EmitInstruction(Val, 2, STI, OS); + emitInstruction(Val >> 16, 2, STI, OS); + emitInstruction(Val, 2, STI, OS); } else { for (unsigned i = 0; i < Size; ++i) { unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8; @@ -226,7 +226,7 @@ encodeInstruction(const MCInst &MI, raw_ostream &OS, if (!Size) llvm_unreachable("Desc.getSize() returns 0"); - EmitInstruction(Binary, Size, STI, OS); + emitInstruction(Binary, Size, STI, OS); } /// getBranchTargetOpValue - Return binary encoding of the branch @@ -723,21 +723,8 @@ getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups, return 0; } - if (Kind == MCExpr::SymbolRef) { - Mips::Fixups FixupKind = Mips::Fixups(0); - - switch(cast<MCSymbolRefExpr>(Expr)->getKind()) { - default: llvm_unreachable("Unknown fixup kind!"); - break; - case MCSymbolRefExpr::VK_None: - // FIXME: This is ok for O32/N32 but not N64. - FixupKind = Mips::fixup_Mips_32; - break; - } // switch - - Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind))); - return 0; - } + if (Kind == MCExpr::SymbolRef) + Ctx.reportError(Expr->getLoc(), "expected an immediate"); return 0; } diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h b/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h index ff6e1d62b05f..16e94c723b34 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h @@ -44,7 +44,7 @@ public: void EmitByte(unsigned char C, raw_ostream &OS) const; - void EmitInstruction(uint64_t Val, unsigned Size, const MCSubtargetInfo &STI, + void emitInstruction(uint64_t Val, unsigned Size, const MCSubtargetInfo &STI, raw_ostream &OS) const; void encodeInstruction(const MCInst &MI, raw_ostream &OS, diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h b/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h index 809be99ff3f4..b7ecb0fdca5e 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h @@ -29,8 +29,6 @@ class MCTargetOptions; class StringRef; class Target; class Triple; -class raw_ostream; -class raw_pwrite_stream; MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp index 0544758f8a25..eade2d9bd745 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp @@ -105,7 +105,7 @@ private: MaskInst.addOperand(MCOperand::createReg(AddrReg)); MaskInst.addOperand(MCOperand::createReg(AddrReg)); MaskInst.addOperand(MCOperand::createReg(MaskReg)); - MipsELFStreamer::EmitInstruction(MaskInst, STI); + MipsELFStreamer::emitInstruction(MaskInst, STI); } // Sandbox indirect branch or return instruction by inserting mask operation @@ -113,10 +113,10 @@ private: void sandboxIndirectJump(const MCInst &MI, const MCSubtargetInfo &STI) { unsigned AddrReg = MI.getOperand(0).getReg(); - EmitBundleLock(false); + emitBundleLock(false); emitMask(AddrReg, IndirectBranchMaskReg, STI); - MipsELFStreamer::EmitInstruction(MI, STI); - EmitBundleUnlock(); + MipsELFStreamer::emitInstruction(MI, STI); + emitBundleUnlock(); } // Sandbox memory access or SP change. Insert mask operation before and/or @@ -124,26 +124,26 @@ private: void sandboxLoadStoreStackChange(const MCInst &MI, unsigned AddrIdx, const MCSubtargetInfo &STI, bool MaskBefore, bool MaskAfter) { - EmitBundleLock(false); + emitBundleLock(false); if (MaskBefore) { // Sandbox memory access. unsigned BaseReg = MI.getOperand(AddrIdx).getReg(); emitMask(BaseReg, LoadStoreStackMaskReg, STI); } - MipsELFStreamer::EmitInstruction(MI, STI); + MipsELFStreamer::emitInstruction(MI, STI); if (MaskAfter) { // Sandbox SP change. unsigned SPReg = MI.getOperand(0).getReg(); assert((Mips::SP == SPReg) && "Unexpected stack-pointer register."); emitMask(SPReg, LoadStoreStackMaskReg, STI); } - EmitBundleUnlock(); + emitBundleUnlock(); } public: /// This function is the one used to emit instruction data into the ELF /// streamer. We override it to mask dangerous instructions. - void EmitInstruction(const MCInst &Inst, + void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override { // Sandbox indirect jumps. if (isIndirectJump(Inst)) { @@ -181,25 +181,25 @@ public: report_fatal_error("Dangerous instruction in branch delay slot!"); // Start the sandboxing sequence by emitting call. - EmitBundleLock(true); + emitBundleLock(true); if (IsIndirectCall) { unsigned TargetReg = Inst.getOperand(1).getReg(); emitMask(TargetReg, IndirectBranchMaskReg, STI); } - MipsELFStreamer::EmitInstruction(Inst, STI); + MipsELFStreamer::emitInstruction(Inst, STI); PendingCall = true; return; } if (PendingCall) { // Finish the sandboxing sequence by emitting branch delay. - MipsELFStreamer::EmitInstruction(Inst, STI); - EmitBundleUnlock(); + MipsELFStreamer::emitInstruction(Inst, STI); + emitBundleUnlock(); PendingCall = false; return; } // None of the sandboxing applies, just emit the instruction. - MipsELFStreamer::EmitInstruction(Inst, STI); + MipsELFStreamer::emitInstruction(Inst, STI); } }; @@ -270,7 +270,7 @@ MCELFStreamer *createMipsNaClELFStreamer(MCContext &Context, S->getAssembler().setRelaxAll(true); // Set bundle-alignment as required by the NaCl ABI for the target. - S->EmitBundleAlignMode(Log2(MIPS_NACL_BUNDLE_ALIGN)); + S->emitBundleAlignMode(Log2(MIPS_NACL_BUNDLE_ALIGN)); return S; } diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsOptionRecord.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsOptionRecord.cpp index bdfb70aa9813..a4a953bcd7c3 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsOptionRecord.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsOptionRecord.cpp @@ -40,17 +40,17 @@ void MipsRegInfoRecord::EmitMipsOptionRecord() { Sec->setAlignment(Align(8)); Streamer->SwitchSection(Sec); - Streamer->EmitIntValue(ELF::ODK_REGINFO, 1); // kind - Streamer->EmitIntValue(40, 1); // size - Streamer->EmitIntValue(0, 2); // section - Streamer->EmitIntValue(0, 4); // info - Streamer->EmitIntValue(ri_gprmask, 4); - Streamer->EmitIntValue(0, 4); // pad - Streamer->EmitIntValue(ri_cprmask[0], 4); - Streamer->EmitIntValue(ri_cprmask[1], 4); - Streamer->EmitIntValue(ri_cprmask[2], 4); - Streamer->EmitIntValue(ri_cprmask[3], 4); - Streamer->EmitIntValue(ri_gp_value, 8); + Streamer->emitInt8(ELF::ODK_REGINFO); // kind + Streamer->emitInt8(40); // size + Streamer->emitInt16(0); // section + Streamer->emitInt32(0); // info + Streamer->emitInt32(ri_gprmask); + Streamer->emitInt32(0); // pad + Streamer->emitInt32(ri_cprmask[0]); + Streamer->emitInt32(ri_cprmask[1]); + Streamer->emitInt32(ri_cprmask[2]); + Streamer->emitInt32(ri_cprmask[3]); + Streamer->emitIntValue(ri_gp_value, 8); } else { MCSectionELF *Sec = Context.getELFSection(".reginfo", ELF::SHT_MIPS_REGINFO, ELF::SHF_ALLOC, 24, ""); @@ -58,13 +58,13 @@ void MipsRegInfoRecord::EmitMipsOptionRecord() { Sec->setAlignment(MTS->getABI().IsN32() ? Align(8) : Align(4)); Streamer->SwitchSection(Sec); - Streamer->EmitIntValue(ri_gprmask, 4); - Streamer->EmitIntValue(ri_cprmask[0], 4); - Streamer->EmitIntValue(ri_cprmask[1], 4); - Streamer->EmitIntValue(ri_cprmask[2], 4); - Streamer->EmitIntValue(ri_cprmask[3], 4); + Streamer->emitInt32(ri_gprmask); + Streamer->emitInt32(ri_cprmask[0]); + Streamer->emitInt32(ri_cprmask[1]); + Streamer->emitInt32(ri_cprmask[2]); + Streamer->emitInt32(ri_cprmask[3]); assert((ri_gp_value & 0xffffffff) == ri_gp_value); - Streamer->EmitIntValue(ri_gp_value, 4); + Streamer->emitInt32(ri_gp_value); } Streamer->PopSection(); diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp index 054dc79f4aa9..6ec8fe805968 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp @@ -109,6 +109,9 @@ void MipsTargetStreamer::emitDirectiveSetHardFloat() { void MipsTargetStreamer::emitDirectiveSetDsp() { forbidModuleDirective(); } void MipsTargetStreamer::emitDirectiveSetDspr2() { forbidModuleDirective(); } void MipsTargetStreamer::emitDirectiveSetNoDsp() { forbidModuleDirective(); } +void MipsTargetStreamer::emitDirectiveSetMips3D() { forbidModuleDirective(); } +void MipsTargetStreamer::emitDirectiveSetNoMips3D() { forbidModuleDirective(); } +void MipsTargetStreamer::emitDirectiveCpAdd(unsigned RegNo) {} void MipsTargetStreamer::emitDirectiveCpLoad(unsigned RegNo) {} void MipsTargetStreamer::emitDirectiveCpLocal(unsigned RegNo) { // .cplocal $reg @@ -169,7 +172,7 @@ void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc, TmpInst.setOpcode(Opcode); TmpInst.addOperand(MCOperand::createReg(Reg0)); TmpInst.setLoc(IDLoc); - getStreamer().EmitInstruction(TmpInst, *STI); + getStreamer().emitInstruction(TmpInst, *STI); } void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, @@ -179,7 +182,7 @@ void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, TmpInst.addOperand(MCOperand::createReg(Reg0)); TmpInst.addOperand(Op1); TmpInst.setLoc(IDLoc); - getStreamer().EmitInstruction(TmpInst, *STI); + getStreamer().emitInstruction(TmpInst, *STI); } void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, @@ -199,7 +202,7 @@ void MipsTargetStreamer::emitII(unsigned Opcode, int16_t Imm1, int16_t Imm2, TmpInst.addOperand(MCOperand::createImm(Imm1)); TmpInst.addOperand(MCOperand::createImm(Imm2)); TmpInst.setLoc(IDLoc); - getStreamer().EmitInstruction(TmpInst, *STI); + getStreamer().emitInstruction(TmpInst, *STI); } void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, @@ -211,7 +214,7 @@ void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, TmpInst.addOperand(MCOperand::createReg(Reg1)); TmpInst.addOperand(Op2); TmpInst.setLoc(IDLoc); - getStreamer().EmitInstruction(TmpInst, *STI); + getStreamer().emitInstruction(TmpInst, *STI); } void MipsTargetStreamer::emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, @@ -230,7 +233,7 @@ void MipsTargetStreamer::emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, TmpInst.addOperand(MCOperand::createReg(Reg2)); TmpInst.addOperand(Op3); TmpInst.setLoc(IDLoc); - getStreamer().EmitInstruction(TmpInst, *STI); + getStreamer().emitInstruction(TmpInst, *STI); } void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, @@ -251,7 +254,7 @@ void MipsTargetStreamer::emitRRIII(unsigned Opcode, unsigned Reg0, TmpInst.addOperand(MCOperand::createImm(Imm1)); TmpInst.addOperand(MCOperand::createImm(Imm2)); TmpInst.setLoc(IDLoc); - getStreamer().EmitInstruction(TmpInst, *STI); + getStreamer().emitInstruction(TmpInst, *STI); } void MipsTargetStreamer::emitAddu(unsigned DstReg, unsigned SrcReg, @@ -609,6 +612,16 @@ void MipsTargetAsmStreamer::emitDirectiveSetNoDsp() { MipsTargetStreamer::emitDirectiveSetNoDsp(); } +void MipsTargetAsmStreamer::emitDirectiveSetMips3D() { + OS << "\t.set\tmips3d\n"; + MipsTargetStreamer::emitDirectiveSetMips3D(); +} + +void MipsTargetAsmStreamer::emitDirectiveSetNoMips3D() { + OS << "\t.set\tnomips3d\n"; + MipsTargetStreamer::emitDirectiveSetNoMips3D(); +} + void MipsTargetAsmStreamer::emitDirectiveSetPop() { OS << "\t.set\tpop\n"; MipsTargetStreamer::emitDirectiveSetPop(); @@ -650,6 +663,12 @@ void MipsTargetAsmStreamer::emitFMask(unsigned FPUBitmask, OS << "," << FPUTopSavedRegOff << '\n'; } +void MipsTargetAsmStreamer::emitDirectiveCpAdd(unsigned RegNo) { + OS << "\t.cpadd\t$" + << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n"; + forbidModuleDirective(); +} + void MipsTargetAsmStreamer::emitDirectiveCpLoad(unsigned RegNo) { OS << "\t.cpload\t$" << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n"; @@ -883,9 +902,9 @@ void MipsTargetELFStreamer::finish() { if (Alignment) { OS.SwitchSection(&Section); if (Section.UseCodeAlign()) - OS.EmitCodeAlignment(Alignment, Alignment); + OS.emitCodeAlignment(Alignment, Alignment); else - OS.EmitValueToAlignment(Alignment, 0, 1, Alignment); + OS.emitValueToAlignment(Alignment, 0, 1, Alignment); } } } @@ -997,17 +1016,17 @@ void MipsTargetELFStreamer::emitDirectiveEnd(StringRef Name) { OS.SwitchSection(Sec); - OS.EmitValueImpl(ExprRef, 4); + OS.emitValueImpl(ExprRef, 4); - OS.EmitIntValue(GPRInfoSet ? GPRBitMask : 0, 4); // reg_mask - OS.EmitIntValue(GPRInfoSet ? GPROffset : 0, 4); // reg_offset + OS.emitIntValue(GPRInfoSet ? GPRBitMask : 0, 4); // reg_mask + OS.emitIntValue(GPRInfoSet ? GPROffset : 0, 4); // reg_offset - OS.EmitIntValue(FPRInfoSet ? FPRBitMask : 0, 4); // fpreg_mask - OS.EmitIntValue(FPRInfoSet ? FPROffset : 0, 4); // fpreg_offset + OS.emitIntValue(FPRInfoSet ? FPRBitMask : 0, 4); // fpreg_mask + OS.emitIntValue(FPRInfoSet ? FPROffset : 0, 4); // fpreg_offset - OS.EmitIntValue(FrameInfoSet ? FrameOffset : 0, 4); // frame_offset - OS.EmitIntValue(FrameInfoSet ? FrameReg : 0, 4); // frame_reg - OS.EmitIntValue(FrameInfoSet ? ReturnReg : 0, 4); // return_reg + OS.emitIntValue(FrameInfoSet ? FrameOffset : 0, 4); // frame_offset + OS.emitIntValue(FrameInfoSet ? FrameReg : 0, 4); // frame_reg + OS.emitIntValue(FrameInfoSet ? ReturnReg : 0, 4); // return_reg // The .end directive marks the end of a procedure. Invalidate // the information gathered up until this point. @@ -1017,7 +1036,7 @@ void MipsTargetELFStreamer::emitDirectiveEnd(StringRef Name) { // .end also implicitly sets the size. MCSymbol *CurPCSym = Context.createTempSymbol(); - OS.EmitLabel(CurPCSym); + OS.emitLabel(CurPCSym); const MCExpr *Size = MCBinaryExpr::createSub( MCSymbolRefExpr::create(CurPCSym, MCSymbolRefExpr::VK_None, Context), ExprRef, Context); @@ -1108,6 +1127,17 @@ void MipsTargetELFStreamer::emitFMask(unsigned FPUBitmask, FPROffset = FPUTopSavedRegOff; } +void MipsTargetELFStreamer::emitDirectiveCpAdd(unsigned RegNo) { + // .cpadd $reg + // This directive inserts code to add $gp to the argument's register + // when support for position independent code is enabled. + if (!Pic) + return; + + emitAddu(RegNo, RegNo, GPReg, getABI().IsN64(), &STI); + forbidModuleDirective(); +} + void MipsTargetELFStreamer::emitDirectiveCpLoad(unsigned RegNo) { // .cpload $reg // This directive expands to: @@ -1139,7 +1169,7 @@ void MipsTargetELFStreamer::emitDirectiveCpLoad(unsigned RegNo) { MCA.getContext()), MCA.getContext()); TmpInst.addOperand(MCOperand::createExpr(HiSym)); - getStreamer().EmitInstruction(TmpInst, STI); + getStreamer().emitInstruction(TmpInst, STI); TmpInst.clear(); @@ -1152,7 +1182,7 @@ void MipsTargetELFStreamer::emitDirectiveCpLoad(unsigned RegNo) { MCA.getContext()), MCA.getContext()); TmpInst.addOperand(MCOperand::createExpr(LoSym)); - getStreamer().EmitInstruction(TmpInst, STI); + getStreamer().emitInstruction(TmpInst, STI); TmpInst.clear(); @@ -1160,7 +1190,7 @@ void MipsTargetELFStreamer::emitDirectiveCpLoad(unsigned RegNo) { TmpInst.addOperand(MCOperand::createReg(GPReg)); TmpInst.addOperand(MCOperand::createReg(GPReg)); TmpInst.addOperand(MCOperand::createReg(RegNo)); - getStreamer().EmitInstruction(TmpInst, STI); + getStreamer().emitInstruction(TmpInst, STI); forbidModuleDirective(); } @@ -1269,7 +1299,7 @@ void MipsTargetELFStreamer::emitDirectiveCpreturn(unsigned SaveLocation, Inst.addOperand(MCOperand::createReg(Mips::SP)); Inst.addOperand(MCOperand::createImm(SaveLocation)); } - getStreamer().EmitInstruction(Inst, STI); + getStreamer().emitInstruction(Inst, STI); forbidModuleDirective(); } diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MicroMipsInstrFormats.td b/contrib/llvm-project/llvm/lib/Target/Mips/MicroMipsInstrFormats.td index e9fb9b310e3b..101d080f9567 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MicroMipsInstrFormats.td +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MicroMipsInstrFormats.td @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// This files descributes the formats of the microMIPS instruction set. +// This files describes the formats of the microMIPS instruction set. // //===----------------------------------------------------------------------===// diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MicroMipsInstrInfo.td b/contrib/llvm-project/llvm/lib/Target/Mips/MicroMipsInstrInfo.td index b707f1b96184..269ad8b548a4 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MicroMipsInstrInfo.td +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MicroMipsInstrInfo.td @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// This files describes the defintions of the microMIPSr3 instructions. +// This files describes the definitions of the microMIPSr3 instructions. // //===----------------------------------------------------------------------===// diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp index db93b3d80ede..55d3c59cbf03 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp @@ -376,12 +376,12 @@ static bool CheckXWPInstr(MachineInstr *MI, bool ReduceToLwp, // Returns true if the registers Reg1 and Reg2 are consecutive static bool ConsecutiveRegisters(unsigned Reg1, unsigned Reg2) { - static SmallVector<unsigned, 31> Registers = { - Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, - Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, - Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, - Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, - Mips::SP, Mips::FP, Mips::RA}; + constexpr std::array<unsigned, 31> Registers = { + {Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, + Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, + Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, + Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, + Mips::SP, Mips::FP, Mips::RA}}; for (uint8_t i = 0; i < Registers.size() - 1; i++) { if (Registers[i] == Reg1) { diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/Mips.td b/contrib/llvm-project/llvm/lib/Target/Mips/Mips.td index b8a69815cc12..7fe750249c58 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/Mips.td +++ b/contrib/llvm-project/llvm/lib/Target/Mips/Mips.td @@ -54,22 +54,6 @@ class AdditionalRequires<list<Predicate> preds> { } //===----------------------------------------------------------------------===// -// Register File, Calling Conv, Instruction Descriptions -//===----------------------------------------------------------------------===// - -include "MipsRegisterInfo.td" -include "MipsSchedule.td" -include "MipsInstrInfo.td" -include "MipsCallingConv.td" -include "MipsRegisterBanks.td" - -// Avoid forward declaration issues. -include "MipsScheduleP5600.td" -include "MipsScheduleGeneric.td" - -def MipsInstrInfo : InstrInfo; - -//===----------------------------------------------------------------------===// // Mips Subtarget features // //===----------------------------------------------------------------------===// @@ -177,6 +161,8 @@ def FeatureDSPR3 : SubtargetFeature<"dspr3", "HasDSPR3", "true", "Mips DSP-R3 ASE", [ FeatureDSP, FeatureDSPR2 ]>; +def FeatureMips3D : SubtargetFeature<"mips3d", "Has3D", "true", "Mips 3D ASE">; + def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">; def FeatureEVA : SubtargetFeature<"eva", "HasEVA", "true", "Mips EVA ASE">; @@ -221,6 +207,23 @@ def FeatureUseIndirectJumpsHazard : SubtargetFeature<"use-indirect-jump-hazard", "UseIndirectJumpsHazard", "true", "Use indirect jump" " guards to prevent certain speculation based attacks">; + +//===----------------------------------------------------------------------===// +// Register File, Calling Conv, Instruction Descriptions +//===----------------------------------------------------------------------===// + +include "MipsRegisterInfo.td" +include "MipsSchedule.td" +include "MipsInstrInfo.td" +include "MipsCallingConv.td" +include "MipsRegisterBanks.td" + +// Avoid forward declaration issues. +include "MipsScheduleP5600.td" +include "MipsScheduleGeneric.td" + +def MipsInstrInfo : InstrInfo; + //===----------------------------------------------------------------------===// // Mips processors supported. //===----------------------------------------------------------------------===// diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/Mips16FrameLowering.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/Mips16FrameLowering.cpp index 5a2a916a6b7a..fefa1134b021 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/Mips16FrameLowering.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/Mips16FrameLowering.cpp @@ -62,8 +62,8 @@ void Mips16FrameLowering::emitPrologue(MachineFunction &MF, TII.makeFrame(Mips::SP, StackSize, MBB, MBBI); // emit ".cfi_def_cfa_offset StackSize" - unsigned CFIIndex = MF.addFrameInst( - MCCFIInstruction::createDefCfaOffset(nullptr, -StackSize)); + unsigned CFIIndex = + MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, StackSize)); BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex); @@ -109,11 +109,9 @@ void Mips16FrameLowering::emitEpilogue(MachineFunction &MF, TII.restoreFrame(Mips::SP, StackSize, MBB, MBBI); } -bool Mips16FrameLowering:: -spillCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector<CalleeSavedInfo> &CSI, - const TargetRegisterInfo *TRI) const { +bool Mips16FrameLowering::spillCalleeSavedRegisters( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, + ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const { MachineFunction *MF = MBB.getParent(); // @@ -137,10 +135,9 @@ spillCalleeSavedRegisters(MachineBasicBlock &MBB, return true; } -bool Mips16FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - std::vector<CalleeSavedInfo> &CSI, - const TargetRegisterInfo *TRI) const { +bool Mips16FrameLowering::restoreCalleeSavedRegisters( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, + MutableArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const { // // Registers RA,S0,S1 are the callee saved registers and they will be restored // with the restore instruction during emitEpilogue. diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/Mips16FrameLowering.h b/contrib/llvm-project/llvm/lib/Target/Mips/Mips16FrameLowering.h index 6b62453f8dfe..7f0f1cd4ea37 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/Mips16FrameLowering.h +++ b/contrib/llvm-project/llvm/lib/Target/Mips/Mips16FrameLowering.h @@ -27,13 +27,14 @@ public: bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, - const std::vector<CalleeSavedInfo> &CSI, + ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const override; - bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - std::vector<CalleeSavedInfo> &CSI, - const TargetRegisterInfo *TRI) const override; + bool + restoreCalleeSavedRegisters(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + MutableArrayRef<CalleeSavedInfo> CSI, + const TargetRegisterInfo *TRI) const override; bool hasReservedCallFrame(const MachineFunction &MF) const override; diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/Mips16HardFloat.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/Mips16HardFloat.cpp index e9a3c7ec4b19..cc1f72c03632 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/Mips16HardFloat.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/Mips16HardFloat.cpp @@ -43,7 +43,7 @@ namespace { } // end anonymous namespace -static void EmitInlineAsm(LLVMContext &C, BasicBlock *BB, StringRef AsmText) { +static void emitInlineAsm(LLVMContext &C, BasicBlock *BB, StringRef AsmText) { std::vector<Type *> AsmArgTypes; std::vector<Value *> AsmArgs; @@ -260,7 +260,7 @@ static void assureFPCallStub(Function &F, Module *M, return; LLVMContext &Context = M->getContext(); bool LE = TM.isLittleEndian(); - std::string Name = F.getName(); + std::string Name(F.getName()); std::string SectionName = ".mips16.call.fp." + Name; std::string StubName = "__call_stub_fp_" + Name; // @@ -339,7 +339,7 @@ static void assureFPCallStub(Function &F, Module *M, AsmText += "jr $$18\n"; else AsmText += "jr $$25\n"; - EmitInlineAsm(Context, BB, AsmText); + emitInlineAsm(Context, BB, AsmText); new UnreachableInst(Context, BB); } @@ -448,7 +448,7 @@ static void createFPFnStub(Function *F, Module *M, FPParamVariant PV, bool PicMode = TM.isPositionIndependent(); bool LE = TM.isLittleEndian(); LLVMContext &Context = M->getContext(); - std::string Name = F->getName(); + std::string Name(F->getName()); std::string SectionName = ".mips16.fn." + Name; std::string StubName = "__fn_stub_" + Name; std::string LocalName = "$$__fn_local_" + Name; @@ -475,7 +475,7 @@ static void createFPFnStub(Function *F, Module *M, FPParamVariant PV, AsmText += swapFPIntParams(PV, M, LE, false); AsmText += "jr $$25\n"; AsmText += LocalName + " = " + Name + "\n"; - EmitInlineAsm(Context, BB, AsmText); + emitInlineAsm(Context, BB, AsmText); new UnreachableInst(FStub->getContext(), BB); } diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp index 768d54fc9c24..ddd28d095e51 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp @@ -72,7 +72,7 @@ void Mips16DAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) { MachineRegisterInfo &RegInfo = MF.getRegInfo(); const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); DebugLoc DL; - Register V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg(); + Register V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg(MF); const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass; V0 = RegInfo.createVirtualRegister(RC); diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/Mips16ISelLowering.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/Mips16ISelLowering.cpp index 5425df77d9b8..a3b86bdc2ca0 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/Mips16ISelLowering.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/Mips16ISelLowering.cpp @@ -492,7 +492,7 @@ getOpndList(SmallVectorImpl<SDValue> &Ops, ExternalSymbolSDNode *S = cast<ExternalSymbolSDNode>(JumpTarget); JumpTarget = getAddrGlobal(S, CLI.DL, JumpTarget.getValueType(), DAG, MipsII::MO_GOT, Chain, - FuncInfo->callPtrInfo(S->getSymbol())); + FuncInfo->callPtrInfo(MF, S->getSymbol())); } else RegsToPass.push_front(std::make_pair((unsigned)Mips::T9, Callee)); } diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/Mips16InstrInfo.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/Mips16InstrInfo.cpp index d2a1ba39cb0e..3403ec01aef2 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/Mips16InstrInfo.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/Mips16InstrInfo.cpp @@ -105,7 +105,7 @@ Mips16InstrInfo::isCopyInstrImpl(const MachineInstr &MI) const { void Mips16InstrInfo::storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, - unsigned SrcReg, bool isKill, int FI, + Register SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const { @@ -123,7 +123,7 @@ void Mips16InstrInfo::storeRegToStack(MachineBasicBlock &MBB, void Mips16InstrInfo::loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, - unsigned DestReg, int FI, + Register DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const { @@ -182,7 +182,7 @@ unsigned Mips16InstrInfo::getOppositeBranchOpc(unsigned Opc) const { } static void addSaveRestoreRegs(MachineInstrBuilder &MIB, - const std::vector<CalleeSavedInfo> &CSI, + ArrayRef<CalleeSavedInfo> CSI, unsigned Flags = 0) { for (unsigned i = 0, e = CSI.size(); i != e; ++i) { // Add the callee-saved register as live-in. Do not add if the register is diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/Mips16InstrInfo.h b/contrib/llvm-project/llvm/lib/Target/Mips/Mips16InstrInfo.h index 2ff849cb2ca2..294afd6460f6 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/Mips16InstrInfo.h +++ b/contrib/llvm-project/llvm/lib/Target/Mips/Mips16InstrInfo.h @@ -54,14 +54,14 @@ public: void storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, - unsigned SrcReg, bool isKill, int FrameIndex, + Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const override; void loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, - unsigned DestReg, int FrameIndex, + Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const override; diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/Mips16InstrInfo.td b/contrib/llvm-project/llvm/lib/Target/Mips/Mips16InstrInfo.td index 19ea50c89b96..990202b23bc0 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/Mips16InstrInfo.td +++ b/contrib/llvm-project/llvm/lib/Target/Mips/Mips16InstrInfo.td @@ -1642,7 +1642,7 @@ def : Mips16Pat<(select (i32 (setle CPU16Regs:$a, CPU16Regs:$b)), CPU16Regs:$b, CPU16Regs:$a)>; // -// unnsigned +// unsigned // x = (a <= b)? x : y // // if (b < a) x = y diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp index 5703f585a6a2..f6f43da9abf8 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp @@ -53,12 +53,10 @@ bool Mips16RegisterInfo::useFPForScavengingIndex return false; } -bool Mips16RegisterInfo::saveScavengerRegister - (MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - MachineBasicBlock::iterator &UseMI, - const TargetRegisterClass *RC, - unsigned Reg) const { +bool Mips16RegisterInfo::saveScavengerRegister( + MachineBasicBlock &MBB, MachineBasicBlock::iterator I, + MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, + Register Reg) const { DebugLoc DL; const TargetInstrInfo &TII = *MBB.getParent()->getSubtarget().getInstrInfo(); TII.copyPhysReg(MBB, I, DL, Mips::T0, Reg, true); @@ -96,7 +94,7 @@ void Mips16RegisterInfo::eliminateFI(MachineBasicBlock::iterator II, // 3. Locations for callee-saved registers. // Everything else is referenced relative to whatever register // getFrameRegister() returns. - unsigned FrameReg; + Register FrameReg; if (FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI) FrameReg = Mips::SP; diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/Mips16RegisterInfo.h b/contrib/llvm-project/llvm/lib/Target/Mips/Mips16RegisterInfo.h index fca78b43f96b..ff115b30162b 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/Mips16RegisterInfo.h +++ b/contrib/llvm-project/llvm/lib/Target/Mips/Mips16RegisterInfo.h @@ -16,7 +16,6 @@ #include "MipsRegisterInfo.h" namespace llvm { -class Mips16InstrInfo; class Mips16RegisterInfo : public MipsRegisterInfo { public: @@ -29,10 +28,10 @@ public: bool useFPForScavengingIndex(const MachineFunction &MF) const override; bool saveScavengerRegister(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - MachineBasicBlock::iterator &UseMI, - const TargetRegisterClass *RC, - unsigned Reg) const override; + MachineBasicBlock::iterator I, + MachineBasicBlock::iterator &UseMI, + const TargetRegisterClass *RC, + Register Reg) const override; const TargetRegisterClass *intRegClass(unsigned Size) const override; diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/Mips64InstrInfo.td b/contrib/llvm-project/llvm/lib/Target/Mips/Mips64InstrInfo.td index 306289d56e4b..bd62a56d3008 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/Mips64InstrInfo.td +++ b/contrib/llvm-project/llvm/lib/Target/Mips/Mips64InstrInfo.td @@ -1248,5 +1248,19 @@ def : MipsInstAlias<"sgtu $rs, $imm", (SGTUImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, imm64:$imm), 0>, GPR_64; +def SLEImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rd), + (ins GPR64Opnd:$rs, imm64:$imm), + "sle\t$rd, $rs, $imm">, GPR_64; +def : MipsInstAlias<"sle $rs, $imm", (SLEImm64 GPR64Opnd:$rs, + GPR64Opnd:$rs, + imm64:$imm), 0>, GPR_64; + +def SLEUImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rd), + (ins GPR64Opnd:$rs, imm64:$imm), + "sleu\t$rd, $rs, $imm">, GPR_64; +def : MipsInstAlias<"sleu $rs, $imm", (SLEUImm64 GPR64Opnd:$rs, + GPR64Opnd:$rs, + imm64:$imm), 0>, GPR_64; + def : MipsInstAlias<"rdhwr $rt, $rs", (RDHWR64 GPR64Opnd:$rt, HWRegsOpnd:$rs, 0), 1>, GPR_64; diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsAsmPrinter.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/MipsAsmPrinter.cpp index 8f75336dce5a..cc073fbf5231 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsAsmPrinter.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsAsmPrinter.cpp @@ -174,18 +174,18 @@ static void emitDirectiveRelocJalr(const MachineInstr &MI, MCSymbolRefExpr::create(OffsetLabel, OutContext); const MCExpr *CaleeExpr = MCSymbolRefExpr::create(Callee, OutContext); - OutStreamer.EmitRelocDirective - (*OffsetExpr, - Subtarget.inMicroMipsMode() ? "R_MICROMIPS_JALR" : "R_MIPS_JALR", - CaleeExpr, SMLoc(), *TM.getMCSubtargetInfo()); - OutStreamer.EmitLabel(OffsetLabel); + OutStreamer.emitRelocDirective( + *OffsetExpr, + Subtarget.inMicroMipsMode() ? "R_MICROMIPS_JALR" : "R_MIPS_JALR", + CaleeExpr, SMLoc(), *TM.getMCSubtargetInfo()); + OutStreamer.emitLabel(OffsetLabel); return; } } } } -void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) { +void MipsAsmPrinter::emitInstruction(const MachineInstr *MI) { MipsTargetStreamer &TS = getTargetStreamer(); unsigned Opc = MI->getOpcode(); TS.forbidModuleDirective(); @@ -202,7 +202,7 @@ void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) { // If we just ended a constant pool, mark it as such. if (InConstantPool && Opc != Mips::CONSTPOOL_ENTRY) { - OutStreamer->EmitDataRegion(MCDR_DataRegionEnd); + OutStreamer->emitDataRegion(MCDR_DataRegionEnd); InConstantPool = false; } if (Opc == Mips::CONSTPOOL_ENTRY) { @@ -218,17 +218,17 @@ void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) { // If this is the first entry of the pool, mark it. if (!InConstantPool) { - OutStreamer->EmitDataRegion(MCDR_DataRegion); + OutStreamer->emitDataRegion(MCDR_DataRegion); InConstantPool = true; } - OutStreamer->EmitLabel(GetCPISymbol(LabelId)); + OutStreamer->emitLabel(GetCPISymbol(LabelId)); const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx]; if (MCPE.isMachineConstantPoolEntry()) - EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal); + emitMachineConstantPoolValue(MCPE.Val.MachineCPVal); else - EmitGlobalConstant(MF->getDataLayout(), MCPE.Val.ConstVal); + emitGlobalConstant(MF->getDataLayout(), MCPE.Val.ConstVal); return; } @@ -280,7 +280,7 @@ void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) { // if (I->isPseudo() && !Subtarget->inMips16Mode() && !isLongBranchPseudo(I->getOpcode())) - llvm_unreachable("Pseudo opcode found in EmitInstruction()"); + llvm_unreachable("Pseudo opcode found in emitInstruction()"); MCInst TmpInst0; MCInstLowering.Lower(&*I, TmpInst0); @@ -398,13 +398,13 @@ const char *MipsAsmPrinter::getCurrentABIString() const { } } -void MipsAsmPrinter::EmitFunctionEntryLabel() { +void MipsAsmPrinter::emitFunctionEntryLabel() { MipsTargetStreamer &TS = getTargetStreamer(); // NaCl sandboxing requires that indirect call instructions are masked. // This means that function entry points should be bundle-aligned. if (Subtarget->isTargetNaCl()) - EmitAlignment(std::max(MF->getAlignment(), MIPS_NACL_BUNDLE_ALIGN)); + emitAlignment(std::max(MF->getAlignment(), MIPS_NACL_BUNDLE_ALIGN)); if (Subtarget->inMicroMipsMode()) { TS.emitDirectiveSetMicroMips(); @@ -419,12 +419,12 @@ void MipsAsmPrinter::EmitFunctionEntryLabel() { TS.emitDirectiveSetNoMips16(); TS.emitDirectiveEnt(*CurrentFnSym); - OutStreamer->EmitLabel(CurrentFnSym); + OutStreamer->emitLabel(CurrentFnSym); } /// EmitFunctionBodyStart - Targets can override this to emit stuff before /// the first basic block in the function. -void MipsAsmPrinter::EmitFunctionBodyStart() { +void MipsAsmPrinter::emitFunctionBodyStart() { MipsTargetStreamer &TS = getTargetStreamer(); MCInstLowering.Initialize(&MF->getContext()); @@ -445,7 +445,7 @@ void MipsAsmPrinter::EmitFunctionBodyStart() { /// EmitFunctionBodyEnd - Targets can override this to emit stuff after /// the last basic block in the function. -void MipsAsmPrinter::EmitFunctionBodyEnd() { +void MipsAsmPrinter::emitFunctionBodyEnd() { MipsTargetStreamer &TS = getTargetStreamer(); // There are instruction for this macros, but they must @@ -462,11 +462,11 @@ void MipsAsmPrinter::EmitFunctionBodyEnd() { if (!InConstantPool) return; InConstantPool = false; - OutStreamer->EmitDataRegion(MCDR_DataRegionEnd); + OutStreamer->emitDataRegion(MCDR_DataRegionEnd); } -void MipsAsmPrinter::EmitBasicBlockEnd(const MachineBasicBlock &MBB) { - AsmPrinter::EmitBasicBlockEnd(MBB); +void MipsAsmPrinter::emitBasicBlockEnd(const MachineBasicBlock &MBB) { + AsmPrinter::emitBasicBlockEnd(MBB); MipsTargetStreamer &TS = getTargetStreamer(); if (MBB.empty()) TS.emitDirectiveInsn(); @@ -770,7 +770,7 @@ printRegisterList(const MachineInstr *MI, int opNum, raw_ostream &O) { } } -void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) { +void MipsAsmPrinter::emitStartOfAsmFile(Module &M) { MipsTargetStreamer &TS = getTargetStreamer(); // MipsTargetStreamer has an initialization order problem when emitting an @@ -860,7 +860,7 @@ void MipsAsmPrinter::EmitJal(const MCSubtargetInfo &STI, MCSymbol *Symbol) { I.setOpcode(Mips::JAL); I.addOperand( MCOperand::createExpr(MCSymbolRefExpr::create(Symbol, OutContext))); - OutStreamer->EmitInstruction(I, STI); + OutStreamer->emitInstruction(I, STI); } void MipsAsmPrinter::EmitInstrReg(const MCSubtargetInfo &STI, unsigned Opcode, @@ -868,7 +868,7 @@ void MipsAsmPrinter::EmitInstrReg(const MCSubtargetInfo &STI, unsigned Opcode, MCInst I; I.setOpcode(Opcode); I.addOperand(MCOperand::createReg(Reg)); - OutStreamer->EmitInstruction(I, STI); + OutStreamer->emitInstruction(I, STI); } void MipsAsmPrinter::EmitInstrRegReg(const MCSubtargetInfo &STI, @@ -888,7 +888,7 @@ void MipsAsmPrinter::EmitInstrRegReg(const MCSubtargetInfo &STI, I.setOpcode(Opcode); I.addOperand(MCOperand::createReg(Reg1)); I.addOperand(MCOperand::createReg(Reg2)); - OutStreamer->EmitInstruction(I, STI); + OutStreamer->emitInstruction(I, STI); } void MipsAsmPrinter::EmitInstrRegRegReg(const MCSubtargetInfo &STI, @@ -899,7 +899,7 @@ void MipsAsmPrinter::EmitInstrRegRegReg(const MCSubtargetInfo &STI, I.addOperand(MCOperand::createReg(Reg1)); I.addOperand(MCOperand::createReg(Reg2)); I.addOperand(MCOperand::createReg(Reg3)); - OutStreamer->EmitInstruction(I, STI); + OutStreamer->emitInstruction(I, STI); } void MipsAsmPrinter::EmitMovFPIntPair(const MCSubtargetInfo &STI, @@ -990,7 +990,7 @@ void MipsAsmPrinter::EmitFPCallStub( // // .global xxxx // - OutStreamer->EmitSymbolAttribute(MSymbol, MCSA_Global); + OutStreamer->emitSymbolAttribute(MSymbol, MCSA_Global); const char *RetType; // // make the comment field identifying the return and parameter @@ -1054,7 +1054,7 @@ void MipsAsmPrinter::EmitFPCallStub( // // .align 2 // - OutStreamer->EmitValueToAlignment(4); + OutStreamer->emitValueToAlignment(4); MipsTargetStreamer &TS = getTargetStreamer(); // // .set nomips16 @@ -1073,8 +1073,8 @@ void MipsAsmPrinter::EmitFPCallStub( TS.emitDirectiveEnt(*Stub); MCSymbol *MType = OutContext.getOrCreateSymbol("__call_stub_fp_" + Twine(Symbol)); - OutStreamer->EmitSymbolAttribute(MType, MCSA_ELF_TypeFunction); - OutStreamer->EmitLabel(Stub); + OutStreamer->emitSymbolAttribute(MType, MCSA_ELF_TypeFunction); + OutStreamer->emitLabel(Stub); // Only handle non-pic for now. assert(!isPositionIndependent() && @@ -1113,7 +1113,7 @@ void MipsAsmPrinter::EmitFPCallStub( EmitInstrReg(*STI, Mips::JR, Mips::S2); MCSymbol *Tmp = OutContext.createTempSymbol(); - OutStreamer->EmitLabel(Tmp); + OutStreamer->emitLabel(Tmp); const MCSymbolRefExpr *E = MCSymbolRefExpr::create(Stub, OutContext); const MCSymbolRefExpr *T = MCSymbolRefExpr::create(Tmp, OutContext); const MCExpr *T_min_E = MCBinaryExpr::createSub(T, E, OutContext); @@ -1122,7 +1122,7 @@ void MipsAsmPrinter::EmitFPCallStub( OutStreamer->PopSection(); } -void MipsAsmPrinter::EmitEndOfAsmFile(Module &M) { +void MipsAsmPrinter::emitEndOfAsmFile(Module &M) { // Emit needed stubs // for (std::map< @@ -1203,9 +1203,9 @@ void MipsAsmPrinter::EmitSled(const MachineInstr &MI, SledKind Kind) { // LD RA, 8(SP) // DADDIU SP, SP, 16 // - OutStreamer->EmitCodeAlignment(4); + OutStreamer->emitCodeAlignment(4); auto CurSled = OutContext.createTempSymbol("xray_sled_", true); - OutStreamer->EmitLabel(CurSled); + OutStreamer->emitLabel(CurSled); auto Target = OutContext.createTempSymbol(); // Emit "B .tmpN" instruction, which jumps over the nop sled to the actual @@ -1223,7 +1223,7 @@ void MipsAsmPrinter::EmitSled(const MachineInstr &MI, SledKind Kind) { .addReg(Mips::ZERO) .addImm(0)); - OutStreamer->EmitLabel(Target); + OutStreamer->emitLabel(Target); if (!Subtarget->isGP64bit()) { EmitToStreamer(*OutStreamer, @@ -1255,15 +1255,15 @@ void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr *MI, // Emit .dtprelword or .dtpreldword directive // and value for debug thread local expression. -void MipsAsmPrinter::EmitDebugValue(const MCExpr *Value, unsigned Size) const { +void MipsAsmPrinter::emitDebugValue(const MCExpr *Value, unsigned Size) const { if (auto *MipsExpr = dyn_cast<MipsMCExpr>(Value)) { if (MipsExpr && MipsExpr->getKind() == MipsMCExpr::MEK_DTPREL) { switch (Size) { case 4: - OutStreamer->EmitDTPRel32Value(MipsExpr->getSubExpr()); + OutStreamer->emitDTPRel32Value(MipsExpr->getSubExpr()); break; case 8: - OutStreamer->EmitDTPRel64Value(MipsExpr->getSubExpr()); + OutStreamer->emitDTPRel64Value(MipsExpr->getSubExpr()); break; default: llvm_unreachable("Unexpected size of expression value."); @@ -1271,7 +1271,7 @@ void MipsAsmPrinter::EmitDebugValue(const MCExpr *Value, unsigned Size) const { return; } } - AsmPrinter::EmitDebugValue(Value, Size); + AsmPrinter::emitDebugValue(Value, Size); } // Align all targets of indirect branches on bundle size. Used only if target diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsAsmPrinter.h b/contrib/llvm-project/llvm/lib/Target/Mips/MipsAsmPrinter.h index 173a1312812e..64424b181504 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsAsmPrinter.h +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsAsmPrinter.h @@ -126,22 +126,22 @@ public: bool runOnMachineFunction(MachineFunction &MF) override; - void EmitConstantPool() override { + void emitConstantPool() override { bool UsingConstantPools = (Subtarget->inMips16Mode() && Subtarget->useConstantIslands()); if (!UsingConstantPools) - AsmPrinter::EmitConstantPool(); + AsmPrinter::emitConstantPool(); // we emit constant pools customly! } - void EmitInstruction(const MachineInstr *MI) override; + void emitInstruction(const MachineInstr *MI) override; void printSavedRegsBitmask(); void emitFrameDirective(); const char *getCurrentABIString() const; - void EmitFunctionEntryLabel() override; - void EmitFunctionBodyStart() override; - void EmitFunctionBodyEnd() override; - void EmitBasicBlockEnd(const MachineBasicBlock &MBB) override; + void emitFunctionEntryLabel() override; + void emitFunctionBodyStart() override; + void emitFunctionBodyEnd() override; + void emitBasicBlockEnd(const MachineBasicBlock &MBB) override; bool isBlockOnlyReachableByFallthrough( const MachineBasicBlock* MBB) const override; bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, @@ -154,10 +154,10 @@ public: void printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O, const char *Modifier = nullptr); void printRegisterList(const MachineInstr *MI, int opNum, raw_ostream &O); - void EmitStartOfAsmFile(Module &M) override; - void EmitEndOfAsmFile(Module &M) override; + void emitStartOfAsmFile(Module &M) override; + void emitEndOfAsmFile(Module &M) override; void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS); - void EmitDebugValue(const MCExpr *Value, unsigned Size) const override; + void emitDebugValue(const MCExpr *Value, unsigned Size) const override; }; } // end namespace llvm diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsBranchExpansion.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/MipsBranchExpansion.cpp index 1523a6c020aa..aa8e298fa759 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsBranchExpansion.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsBranchExpansion.cpp @@ -342,16 +342,25 @@ void MipsBranchExpansion::replaceBranch(MachineBasicBlock &MBB, Iter Br, for (unsigned I = 0, E = Br->getDesc().getNumOperands(); I < E; ++I) { MachineOperand &MO = Br->getOperand(I); - if (!MO.isReg()) { - assert(MO.isMBB() && "MBB operand expected."); + switch (MO.getType()) { + case MachineOperand::MO_Register: + MIB.addReg(MO.getReg()); break; + case MachineOperand::MO_Immediate: + // Octeon BBIT family of branch has an immediate operand + // (e.g. BBIT0 $v0, 3, %bb.1). + if (!TII->isBranchWithImm(Br->getOpcode())) + llvm_unreachable("Unexpected immediate in branch instruction"); + MIB.addImm(MO.getImm()); + break; + case MachineOperand::MO_MachineBasicBlock: + MIB.addMBB(MBBOpnd); + break; + default: + llvm_unreachable("Unexpected operand type in branch instruction"); } - - MIB.addReg(MO.getReg()); } - MIB.addMBB(MBBOpnd); - if (Br->hasDelaySlot()) { // Bundle the instruction in the delay slot to the newly created branch // and erase the original branch. diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsCCState.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/MipsCCState.cpp index ef48c850a1b8..fe3fe82797c3 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsCCState.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsCCState.cpp @@ -30,9 +30,9 @@ static bool isF128SoftLibCall(const char *CallSym) { // Check that LibCalls is sorted alphabetically. auto Comp = [](const char *S1, const char *S2) { return strcmp(S1, S2) < 0; }; - assert(std::is_sorted(std::begin(LibCalls), std::end(LibCalls), Comp)); - return std::binary_search(std::begin(LibCalls), std::end(LibCalls), - CallSym, Comp); + assert(llvm::is_sorted(LibCalls, Comp)); + return std::binary_search(std::begin(LibCalls), std::end(LibCalls), CallSym, + Comp); } /// This function returns true if Ty is fp128, {f128} or i128 which was diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsCallLowering.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/MipsCallLowering.cpp index 6ba15c232867..cffd99affac1 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsCallLowering.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsCallLowering.cpp @@ -110,10 +110,10 @@ private: MIRBuilder.getMBB().addLiveIn(PhysReg); } - void buildLoad(Register Val, const CCValAssign &VA) { + MachineInstrBuilder buildLoad(const DstOp &Res, const CCValAssign &VA) { MachineMemOperand *MMO; Register Addr = getStackAddress(VA, MMO); - MIRBuilder.buildLoad(Val, Addr, *MMO); + return MIRBuilder.buildLoad(Res, Addr, *MMO); } }; @@ -136,29 +136,19 @@ private: void IncomingValueHandler::assignValueToReg(Register ValVReg, const CCValAssign &VA, const EVT &VT) { - const MipsSubtarget &STI = - static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget()); Register PhysReg = VA.getLocReg(); if (VT == MVT::f64 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) { const MipsSubtarget &STI = static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget()); - - MIRBuilder - .buildInstr(STI.isFP64bit() ? Mips::BuildPairF64_64 - : Mips::BuildPairF64) - .addDef(ValVReg) - .addUse(PhysReg + (STI.isLittle() ? 0 : 1)) - .addUse(PhysReg + (STI.isLittle() ? 1 : 0)) - .constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(), - *STI.getRegBankInfo()); + bool IsEL = STI.isLittle(); + LLT s32 = LLT::scalar(32); + auto Lo = MIRBuilder.buildCopy(s32, Register(PhysReg + (IsEL ? 0 : 1))); + auto Hi = MIRBuilder.buildCopy(s32, Register(PhysReg + (IsEL ? 1 : 0))); + MIRBuilder.buildMerge(ValVReg, {Lo, Hi}); markPhysRegUsed(PhysReg); markPhysRegUsed(PhysReg + 1); } else if (VT == MVT::f32 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) { - MIRBuilder.buildInstr(Mips::MTC1) - .addDef(ValVReg) - .addUse(PhysReg) - .constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(), - *STI.getRegBankInfo()); + MIRBuilder.buildCopy(ValVReg, PhysReg); markPhysRegUsed(PhysReg); } else { switch (VA.getLocInfo()) { @@ -189,13 +179,11 @@ Register IncomingValueHandler::getStackAddress(const CCValAssign &VA, MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI); const TargetFrameLowering *TFL = MF.getSubtarget().getFrameLowering(); - unsigned Align = MinAlign(TFL->getStackAlignment(), Offset); - MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, Size, Align); - - Register AddrReg = MRI.createGenericVirtualRegister(LLT::pointer(0, 32)); - MIRBuilder.buildFrameIndex(AddrReg, FI); + Align Alignment = commonAlignment(TFL->getStackAlign(), Offset); + MMO = + MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, Size, Alignment); - return AddrReg; + return MIRBuilder.buildFrameIndex(LLT::pointer(0, 32), FI).getReg(0); } void IncomingValueHandler::assignValueToAddress(Register ValVReg, @@ -203,9 +191,8 @@ void IncomingValueHandler::assignValueToAddress(Register ValVReg, if (VA.getLocInfo() == CCValAssign::SExt || VA.getLocInfo() == CCValAssign::ZExt || VA.getLocInfo() == CCValAssign::AExt) { - Register LoadReg = MRI.createGenericVirtualRegister(LLT::scalar(32)); - buildLoad(LoadReg, VA); - MIRBuilder.buildTrunc(ValVReg, LoadReg); + auto Load = buildLoad(LLT::scalar(32), VA); + MIRBuilder.buildTrunc(ValVReg, Load); } else buildLoad(ValVReg, VA); } @@ -251,32 +238,15 @@ void OutgoingValueHandler::assignValueToReg(Register ValVReg, const CCValAssign &VA, const EVT &VT) { Register PhysReg = VA.getLocReg(); - const MipsSubtarget &STI = - static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget()); - if (VT == MVT::f64 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) { - MIRBuilder - .buildInstr(STI.isFP64bit() ? Mips::ExtractElementF64_64 - : Mips::ExtractElementF64) - .addDef(PhysReg + (STI.isLittle() ? 1 : 0)) - .addUse(ValVReg) - .addImm(1) - .constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(), - *STI.getRegBankInfo()); - MIRBuilder - .buildInstr(STI.isFP64bit() ? Mips::ExtractElementF64_64 - : Mips::ExtractElementF64) - .addDef(PhysReg + (STI.isLittle() ? 0 : 1)) - .addUse(ValVReg) - .addImm(0) - .constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(), - *STI.getRegBankInfo()); + const MipsSubtarget &STI = + static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget()); + bool IsEL = STI.isLittle(); + auto Unmerge = MIRBuilder.buildUnmerge(LLT::scalar(32), ValVReg); + MIRBuilder.buildCopy(Register(PhysReg + (IsEL ? 0 : 1)), Unmerge.getReg(0)); + MIRBuilder.buildCopy(Register(PhysReg + (IsEL ? 1 : 0)), Unmerge.getReg(1)); } else if (VT == MVT::f32 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) { - MIRBuilder.buildInstr(Mips::MFC1) - .addDef(PhysReg) - .addUse(ValVReg) - .constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(), - *STI.getRegBankInfo()); + MIRBuilder.buildCopy(PhysReg, ValVReg); } else { Register ExtReg = extendRegister(ValVReg, VA); MIRBuilder.buildCopy(PhysReg, ExtReg); @@ -291,23 +261,21 @@ Register OutgoingValueHandler::getStackAddress(const CCValAssign &VA, LLT p0 = LLT::pointer(0, 32); LLT s32 = LLT::scalar(32); - Register SPReg = MRI.createGenericVirtualRegister(p0); - MIRBuilder.buildCopy(SPReg, Register(Mips::SP)); + auto SPReg = MIRBuilder.buildCopy(p0, Register(Mips::SP)); - Register OffsetReg = MRI.createGenericVirtualRegister(s32); unsigned Offset = VA.getLocMemOffset(); - MIRBuilder.buildConstant(OffsetReg, Offset); + auto OffsetReg = MIRBuilder.buildConstant(s32, Offset); - Register AddrReg = MRI.createGenericVirtualRegister(p0); - MIRBuilder.buildPtrAdd(AddrReg, SPReg, OffsetReg); + auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); MachinePointerInfo MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset); unsigned Size = alignTo(VA.getValVT().getSizeInBits(), 8) / 8; - unsigned Align = MinAlign(TFL->getStackAlignment(), Offset); - MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOStore, Size, Align); + Align Alignment = commonAlignment(TFL->getStackAlign(), Offset); + MMO = + MF.getMachineMemOperand(MPO, MachineMemOperand::MOStore, Size, Alignment); - return AddrReg; + return AddrReg.getReg(0); } void OutgoingValueHandler::assignValueToAddress(Register ValVReg, @@ -323,19 +291,13 @@ Register OutgoingValueHandler::extendRegister(Register ValReg, LLT LocTy{VA.getLocVT()}; switch (VA.getLocInfo()) { case CCValAssign::SExt: { - Register ExtReg = MRI.createGenericVirtualRegister(LocTy); - MIRBuilder.buildSExt(ExtReg, ValReg); - return ExtReg; + return MIRBuilder.buildSExt(LocTy, ValReg).getReg(0); } case CCValAssign::ZExt: { - Register ExtReg = MRI.createGenericVirtualRegister(LocTy); - MIRBuilder.buildZExt(ExtReg, ValReg); - return ExtReg; + return MIRBuilder.buildZExt(LocTy, ValReg).getReg(0); } case CCValAssign::AExt: { - Register ExtReg = MRI.createGenericVirtualRegister(LocTy); - MIRBuilder.buildAnyExt(ExtReg, ValReg); - return ExtReg; + return MIRBuilder.buildAnyExt(LocTy, ValReg).getReg(0); } // TODO : handle upper extends case CCValAssign::Full: @@ -489,7 +451,7 @@ bool MipsCallLowering::lowerFormalArguments( static_cast<const MipsTargetMachine &>(MF.getTarget()); const MipsABIInfo &ABI = TM.getABI(); CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(F.getCallingConv()), - 1); + Align(1)); CCInfo.AnalyzeFormalArguments(Ins, TLI.CCAssignFnForCall()); setLocInfo(ArgLocs, Ins); @@ -524,9 +486,8 @@ bool MipsCallLowering::lowerFormalArguments( MachinePointerInfo MPO = MachinePointerInfo::getFixedStack(MF, FI); MachineInstrBuilder FrameIndex = MIRBuilder.buildFrameIndex(LLT::pointer(MPO.getAddrSpace(), 32), FI); - MachineMemOperand *MMO = - MF.getMachineMemOperand(MPO, MachineMemOperand::MOStore, RegSize, - /* Alignment */ RegSize); + MachineMemOperand *MMO = MF.getMachineMemOperand( + MPO, MachineMemOperand::MOStore, RegSize, Align(RegSize)); MIRBuilder.buildStore(Copy, FrameIndex, *MMO); } } @@ -611,7 +572,8 @@ bool MipsCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, MipsCCState CCInfo(F.getCallingConv(), IsCalleeVarArg, MF, ArgLocs, F.getContext()); - CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(Info.CallConv), 1); + CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(Info.CallConv), + Align(1)); const char *Call = Info.Callee.isSymbol() ? Info.Callee.getSymbolName() : nullptr; CCInfo.AnalyzeCallOperands(Outs, TLI.CCAssignFnForCall(), FuncOrigArgs, Call); @@ -631,7 +593,7 @@ bool MipsCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, if (IsCalleeGlobalPIC) { MIRBuilder.buildCopy( Register(Mips::GP), - MF.getInfo<MipsFunctionInfo>()->getGlobalBaseRegForGlobalISel()); + MF.getInfo<MipsFunctionInfo>()->getGlobalBaseRegForGlobalISel(MF)); MIB.addDef(Mips::GP, RegState::Implicit); } MIRBuilder.insertInstr(MIB); @@ -691,7 +653,7 @@ void MipsCallLowering::subTargetRegTypeForCallingConv( if (i == 0) Flags.setOrigAlign(TLI.getABIAlignmentForCallingConv(Arg.Ty, DL)); else - Flags.setOrigAlign(Align::None()); + Flags.setOrigAlign(Align(1)); ISDArgs.emplace_back(Flags, RegisterVT, VT, true, OrigArgIndices[ArgNo], 0); diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp index 1f1a1574443c..faf7160e63e2 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp @@ -529,7 +529,7 @@ MipsConstantIslands::doInitialPlacement(std::vector<MachineInstr*> &CPEMIs) { MF->push_back(BB); // MachineConstantPool measures alignment in bytes. We measure in log2(bytes). - const Align MaxAlign(MCP->getConstantPoolAlignment()); + const Align MaxAlign = MCP->getConstantPoolAlign(); // Mark the basic block as required by the const-pool. // If AlignConstantIslands isn't set, use 4-byte alignment for everything. @@ -554,14 +554,13 @@ MipsConstantIslands::doInitialPlacement(std::vector<MachineInstr*> &CPEMIs) { for (unsigned i = 0, e = CPs.size(); i != e; ++i) { unsigned Size = TD.getTypeAllocSize(CPs[i].getType()); assert(Size >= 4 && "Too small constant pool entry"); - unsigned Align = CPs[i].getAlignment(); - assert(isPowerOf2_32(Align) && "Invalid alignment"); + Align Alignment = CPs[i].getAlign(); // Verify that all constant pool entries are a multiple of their alignment. // If not, we would have to pad them out so that instructions stay aligned. - assert((Size % Align) == 0 && "CP Entry not multiple of 4 bytes!"); + assert(isAligned(Alignment, Size) && "CP Entry not multiple of 4 bytes!"); // Insert CONSTPOOL_ENTRY before entries with a smaller alignment. - unsigned LogAlign = Log2_32(Align); + unsigned LogAlign = Log2(Alignment); MachineBasicBlock::iterator InsAt = InsPoint[LogAlign]; MachineInstr *CPEMI = @@ -579,7 +578,7 @@ MipsConstantIslands::doInitialPlacement(std::vector<MachineInstr*> &CPEMIs) { CPEntries.emplace_back(1, CPEntry(CPEMI, i)); ++NumCPEs; LLVM_DEBUG(dbgs() << "Moved CPI#" << i << " to end of function, size = " - << Size << ", align = " << Align << '\n'); + << Size << ", align = " << Alignment.value() << '\n'); } LLVM_DEBUG(BB->dump()); } @@ -628,7 +627,7 @@ Align MipsConstantIslands::getCPEAlign(const MachineInstr &CPEMI) { unsigned CPI = CPEMI.getOperand(1).getIndex(); assert(CPI < MCP->getConstants().size() && "Invalid constant pool index."); - return Align(MCP->getConstants()[CPI].getAlignment()); + return MCP->getConstants()[CPI].getAlign(); } /// initializeFunctionInfo - Do the initial scan of the function, building up @@ -940,7 +939,7 @@ bool MipsConstantIslands::isWaterInRange(unsigned UserOffset, MachineFunction::const_iterator NextBlock = ++Water->getIterator(); if (NextBlock == MF->end()) { NextBlockOffset = BBInfo[Water->getNumber()].postOffset(); - NextBlockAlignment = Align::None(); + NextBlockAlignment = Align(1); } else { NextBlockOffset = BBInfo[NextBlock->getNumber()].Offset; NextBlockAlignment = NextBlock->getAlignment(); @@ -1656,7 +1655,7 @@ void MipsConstantIslands::prescanForConstants() { Type *Int32Ty = Type::getInt32Ty(MF->getFunction().getContext()); const Constant *C = ConstantInt::get(Int32Ty, V); - unsigned index = MCP->getConstantPoolIndex(C, 4); + unsigned index = MCP->getConstantPoolIndex(C, Align(4)); I->getOperand(2).ChangeToImmediate(index); LLVM_DEBUG(dbgs() << "constant island constant " << *I << "\n"); I->setDesc(TII->get(Mips::LwRxPcTcp16)); diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsDSPInstrFormats.td b/contrib/llvm-project/llvm/lib/Target/Mips/MipsDSPInstrFormats.td index 6f062d0f3c25..abb6aea50710 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsDSPInstrFormats.td +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsDSPInstrFormats.td @@ -21,11 +21,11 @@ def Dsp2MicroMips : InstrMapping { } def HasDSP : Predicate<"Subtarget->hasDSP()">, - AssemblerPredicate<"FeatureDSP">; + AssemblerPredicate<(all_of FeatureDSP)>; def HasDSPR2 : Predicate<"Subtarget->hasDSPR2()">, - AssemblerPredicate<"FeatureDSPR2">; + AssemblerPredicate<(all_of FeatureDSPR2)>; def HasDSPR3 : Predicate<"Subtarget->hasDSPR3()">, - AssemblerPredicate<"FeatureDSPR3">; + AssemblerPredicate<(all_of FeatureDSPR3)>; class ISA_DSPR2 { list<Predicate> ASEPredicate = [HasDSPR2]; diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp index 84ff674569cd..155d19ba6959 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp @@ -96,7 +96,7 @@ static cl::opt<CompactBranchPolicy> MipsCompactBranchPolicy( cl::values(clEnumValN(CB_Never, "never", "Do not use compact branches if possible."), clEnumValN(CB_Optimal, "optimal", - "Use compact branches where appropiate (default)."), + "Use compact branches where appropriate (default)."), clEnumValN(CB_Always, "always", "Always use compact branches if possible."))); diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsFastISel.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/MipsFastISel.cpp index 80f288ac500c..8a847eaf6618 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsFastISel.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsFastISel.cpp @@ -420,7 +420,7 @@ unsigned MipsFastISel::materializeGV(const GlobalValue *GV, MVT VT) { if (IsThreadLocal) return 0; emitInst(Mips::LW, DestReg) - .addReg(MFI->getGlobalBaseReg()) + .addReg(MFI->getGlobalBaseReg(*MF)) .addGlobalAddress(GV, 0, MipsII::MO_GOT); if ((GV->hasInternalLinkage() || (GV->hasLocalLinkage() && !isa<Function>(GV)))) { @@ -437,7 +437,7 @@ unsigned MipsFastISel::materializeExternalCallSym(MCSymbol *Sym) { const TargetRegisterClass *RC = &Mips::GPR32RegClass; unsigned DestReg = createResultReg(RC); emitInst(Mips::LW, DestReg) - .addReg(MFI->getGlobalBaseReg()) + .addReg(MFI->getGlobalBaseReg(*MF)) .addSym(Sym, MipsII::MO_GOT); return DestReg; } @@ -795,12 +795,11 @@ bool MipsFastISel::emitLoad(MVT VT, unsigned &ResultReg, Address &Addr, } if (Addr.isFIBase()) { unsigned FI = Addr.getFI(); - unsigned Align = 4; int64_t Offset = Addr.getOffset(); MachineFrameInfo &MFI = MF->getFrameInfo(); MachineMemOperand *MMO = MF->getMachineMemOperand( MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad, - MFI.getObjectSize(FI), Align); + MFI.getObjectSize(FI), Align(4)); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) .addFrameIndex(FI) .addImm(Offset) @@ -846,12 +845,11 @@ bool MipsFastISel::emitStore(MVT VT, unsigned SrcReg, Address &Addr, } if (Addr.isFIBase()) { unsigned FI = Addr.getFI(); - unsigned Align = 4; int64_t Offset = Addr.getOffset(); MachineFrameInfo &MFI = MF->getFrameInfo(); MachineMemOperand *MMO = MF->getMachineMemOperand( MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore, - MFI.getObjectSize(FI), Align); + MFI.getObjectSize(FI), Align(4)); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc)) .addReg(SrcReg) .addFrameIndex(FI) @@ -1263,7 +1261,7 @@ bool MipsFastISel::processCallArgs(CallLoweringInfo &CLI, Addr.setReg(Mips::SP); Addr.setOffset(VA.getLocMemOffset() + BEAlign); - unsigned Alignment = DL.getABITypeAlignment(ArgVal->getType()); + Align Alignment = DL.getABITypeAlign(ArgVal->getType()); MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand( MachinePointerInfo::getStack(*FuncInfo.MF, Addr.getOffset()), MachineMemOperand::MOStore, ArgVT.getStoreSize(), Alignment); diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp index 8c36bcd5c8f2..d88696525e9e 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp @@ -65,7 +65,7 @@ bool MipsDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { /// getGlobalBaseReg - Output the instructions required to put the /// GOT address into a register. SDNode *MipsDAGToDAGISel::getGlobalBaseReg() { - Register GlobalBaseReg = MF->getInfo<MipsFunctionInfo>()->getGlobalBaseReg(); + Register GlobalBaseReg = MF->getInfo<MipsFunctionInfo>()->getGlobalBaseReg(*MF); return CurDAG->getRegister(GlobalBaseReg, getTargetLowering()->getPointerTy( CurDAG->getDataLayout())) .getNode(); @@ -253,7 +253,7 @@ bool MipsDAGToDAGISel::selectVecAddAsVecSubIfProfitable(SDNode *Node) { SDLoc DL(Node); SDValue NegC = CurDAG->FoldConstantArithmetic( - ISD::SUB, DL, VT, CurDAG->getConstant(0, DL, VT).getNode(), C.getNode()); + ISD::SUB, DL, VT, {CurDAG->getConstant(0, DL, VT), C}); assert(NegC && "Constant-folding failed!"); SDValue NewNode = CurDAG->getNode(ISD::SUB, DL, VT, X, NegC); diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsISelLowering.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/MipsISelLowering.cpp index 46b1f35a6fc7..2da35020006e 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsISelLowering.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsISelLowering.cpp @@ -142,8 +142,9 @@ unsigned MipsTargetLowering::getVectorTypeBreakdownForCallingConv( } SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const { - MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>(); - return DAG.getRegister(FI->getGlobalBaseReg(), Ty); + MachineFunction &MF = DAG.getMachineFunction(); + MipsFunctionInfo *FI = MF.getInfo<MipsFunctionInfo>(); + return DAG.getRegister(FI->getGlobalBaseReg(MF), Ty); } SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty, @@ -173,7 +174,7 @@ SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty, SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG, unsigned Flag) const { - return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(), + return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlign(), N->getOffset(), Flag); } @@ -1451,6 +1452,14 @@ MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, case Mips::PseudoD_SELECT_I: case Mips::PseudoD_SELECT_I64: return emitPseudoD_SELECT(MI, BB); + case Mips::LDR_W: + return emitLDR_W(MI, BB); + case Mips::LDR_D: + return emitLDR_D(MI, BB); + case Mips::STR_W: + return emitSTR_W(MI, BB); + case Mips::STR_D: + return emitSTR_D(MI, BB); } } @@ -2900,8 +2909,8 @@ static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, // argument which is not f32 or f64. bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 || State.getFirstUnallocated(F32Regs) != ValNo; - unsigned OrigAlign = ArgFlags.getOrigAlign(); - bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); + Align OrigAlign = ArgFlags.getNonZeroOrigAlign(); + bool isI64 = (ValVT == MVT::i32 && OrigAlign == Align(8)); bool isVectorFloat = MipsState->WasOriginalArgVectorFloat(ValNo); // The MIPS vector ABI for floats passes them in a pair of registers @@ -3201,7 +3210,7 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, // caller side but removing it breaks the frame size calculation. unsigned ReservedArgArea = MemcpyInByVal ? 0 : ABI.GetCalleeAllocdArgSizeInBytes(CallConv); - CCInfo.AllocateStack(ReservedArgArea, 1); + CCInfo.AllocateStack(ReservedArgArea, Align(1)); CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(), ES ? ES->getSymbol() : nullptr); @@ -3209,6 +3218,9 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, // Get a count of how many bytes are to be pushed on the stack. unsigned NextStackOffset = CCInfo.getNextStackOffset(); + // Call site info for function parameters tracking. + MachineFunction::CallSiteInfo CSInfo; + // Check if it's really possible to do a tail call. Restrict it to functions // that are part of this compilation unit. bool InternalLinkage = false; @@ -3223,7 +3235,7 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, G->getGlobal()->hasProtectedVisibility()); } } - if (!IsTailCall && CLI.CS && CLI.CS.isMustTailCall()) + if (!IsTailCall && CLI.CB && CLI.CB->isMustTailCall()) report_fatal_error("failed to perform tail call elimination on a call " "site marked musttail"); @@ -3335,6 +3347,17 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, // RegsToPass vector if (VA.isRegLoc()) { RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); + + // If the parameter is passed through reg $D, which splits into + // two physical registers, avoid creating call site info. + if (Mips::AFGR64RegClass.contains(VA.getLocReg())) + continue; + + // Collect CSInfo about which register passes which parameter. + const TargetOptions &Options = DAG.getTarget().Options; + if (Options.SupportsDebugEntryValues) + CSInfo.emplace_back(VA.getLocReg(), i); + continue; } @@ -3398,11 +3421,11 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, else if (Subtarget.useXGOT()) { Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16, MipsII::MO_CALL_LO16, Chain, - FuncInfo->callPtrInfo(Val)); + FuncInfo->callPtrInfo(MF, Val)); IsCallReloc = true; } else { Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, - FuncInfo->callPtrInfo(Val)); + FuncInfo->callPtrInfo(MF, Val)); IsCallReloc = true; } } else @@ -3420,11 +3443,11 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, else if (Subtarget.useXGOT()) { Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16, MipsII::MO_CALL_LO16, Chain, - FuncInfo->callPtrInfo(Sym)); + FuncInfo->callPtrInfo(MF, Sym)); IsCallReloc = true; } else { // PIC Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, - FuncInfo->callPtrInfo(Sym)); + FuncInfo->callPtrInfo(MF, Sym)); IsCallReloc = true; } @@ -3439,12 +3462,16 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, if (IsTailCall) { MF.getFrameInfo().setHasTailCall(); - return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops); + SDValue Ret = DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops); + DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo)); + return Ret; } Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops); SDValue InFlag = Chain.getValue(1); + DAG.addCallSiteInfo(Chain.getNode(), std::move(CSInfo)); + // Create the CALLSEQ_END node in the case of where it is not a call to // memcpy. if (!(MemcpyInByVal)) { @@ -3605,7 +3632,7 @@ SDValue MipsTargetLowering::LowerFormalArguments( SmallVector<CCValAssign, 16> ArgLocs; MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext()); - CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1); + CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), Align(1)); const Function &Func = DAG.getMachineFunction().getFunction(); Function::const_arg_iterator FuncArg = Func.arg_begin(); @@ -3940,7 +3967,7 @@ MipsTargetLowering::getSingleConstraintMatchWeight( break; case 'f': // FPU or MSA register if (Subtarget.hasMSA() && type->isVectorTy() && - cast<VectorType>(type)->getBitWidth() == 128) + type->getPrimitiveSizeInBits().getFixedSize() == 128) weight = CW_Register; else if (type->isFloatTy()) weight = CW_Register; @@ -4269,9 +4296,7 @@ MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { } EVT MipsTargetLowering::getOptimalMemOpType( - uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, - bool ZeroMemset, bool MemcpyStrSrc, - const AttributeList &FuncAttributes) const { + const MemOp &Op, const AttributeList &FuncAttributes) const { if (Subtarget.hasMips64()) return MVT::i64; @@ -4363,7 +4388,8 @@ void MipsTargetLowering::passByValArg( unsigned ByValSizeInBytes = Flags.getByValSize(); unsigned OffsetInBytes = 0; // From beginning of struct unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); - unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes); + Align Alignment = + std::min(Flags.getNonZeroByValAlign(), Align(RegSizeInBytes)); EVT PtrTy = getPointerTy(DAG.getDataLayout()), RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); unsigned NumRegs = LastReg - FirstReg; @@ -4378,7 +4404,7 @@ void MipsTargetLowering::passByValArg( SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, DAG.getConstant(OffsetInBytes, DL, PtrTy)); SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, - MachinePointerInfo(), Alignment); + MachinePointerInfo(), Alignment.value()); MemOpChains.push_back(LoadVal.getValue(1)); unsigned ArgReg = ArgRegs[FirstReg + I]; RegsToPass.push_back(std::make_pair(ArgReg, LoadVal)); @@ -4405,7 +4431,7 @@ void MipsTargetLowering::passByValArg( PtrTy)); SDValue LoadVal = DAG.getExtLoad( ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(), - MVT::getIntegerVT(LoadSizeInBytes * 8), Alignment); + MVT::getIntegerVT(LoadSizeInBytes * 8), Alignment.value()); MemOpChains.push_back(LoadVal.getValue(1)); // Shift the loaded value. @@ -4426,7 +4452,7 @@ void MipsTargetLowering::passByValArg( OffsetInBytes += LoadSizeInBytes; TotalBytesLoaded += LoadSizeInBytes; - Alignment = std::min(Alignment, LoadSizeInBytes); + Alignment = std::min(Alignment, Align(LoadSizeInBytes)); } unsigned ArgReg = ArgRegs[FirstReg + I]; @@ -4441,11 +4467,10 @@ void MipsTargetLowering::passByValArg( DAG.getConstant(OffsetInBytes, DL, PtrTy)); SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr, DAG.getIntPtrConstant(VA.getLocMemOffset(), DL)); - Chain = DAG.getMemcpy(Chain, DL, Dst, Src, - DAG.getConstant(MemCpySize, DL, PtrTy), - Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false, - /*isTailCall=*/false, - MachinePointerInfo(), MachinePointerInfo()); + Chain = DAG.getMemcpy( + Chain, DL, Dst, Src, DAG.getConstant(MemCpySize, DL, PtrTy), + Align(Alignment), /*isVolatile=*/false, /*AlwaysInline=*/false, + /*isTailCall=*/false, MachinePointerInfo(), MachinePointerInfo()); MemOpChains.push_back(Chain); } @@ -4497,12 +4522,12 @@ void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains, } void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size, - unsigned Align) const { + Align Alignment) const { const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); assert(Size && "Byval argument's size shouldn't be 0."); - Align = std::min(Align, TFL->getStackAlignment()); + Alignment = std::min(Alignment, TFL->getStackAlign()); unsigned FirstReg = 0; unsigned NumRegs = 0; @@ -4516,17 +4541,17 @@ void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size, // We used to check the size as well but we can't do that anymore since // CCState::HandleByVal() rounds up the size after calling this function. - assert(!(Align % RegSizeInBytes) && - "Byval argument's alignment should be a multiple of" - "RegSizeInBytes."); + assert( + Alignment >= Align(RegSizeInBytes) && + "Byval argument's alignment should be a multiple of RegSizeInBytes."); FirstReg = State->getFirstUnallocated(IntArgRegs); - // If Align > RegSizeInBytes, the first arg register must be even. + // If Alignment > RegSizeInBytes, the first arg register must be even. // FIXME: This condition happens to do the right thing but it's not the // right way to test it. We want to check that the stack frame offset // of the register is aligned. - if ((Align > RegSizeInBytes) && (FirstReg % 2)) { + if ((Alignment > RegSizeInBytes) && (FirstReg % 2)) { State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]); ++FirstReg; } @@ -4717,3 +4742,274 @@ MipsTargetLowering::getRegisterByName(const char *RegName, LLT VT, } report_fatal_error("Invalid register name global variable"); } + +MachineBasicBlock *MipsTargetLowering::emitLDR_W(MachineInstr &MI, + MachineBasicBlock *BB) const { + MachineFunction *MF = BB->getParent(); + MachineRegisterInfo &MRI = MF->getRegInfo(); + const TargetInstrInfo *TII = Subtarget.getInstrInfo(); + const bool IsLittle = Subtarget.isLittle(); + DebugLoc DL = MI.getDebugLoc(); + + Register Dest = MI.getOperand(0).getReg(); + Register Address = MI.getOperand(1).getReg(); + unsigned Imm = MI.getOperand(2).getImm(); + + MachineBasicBlock::iterator I(MI); + + if (Subtarget.hasMips32r6() || Subtarget.hasMips64r6()) { + // Mips release 6 can load from adress that is not naturally-aligned. + Register Temp = MRI.createVirtualRegister(&Mips::GPR32RegClass); + BuildMI(*BB, I, DL, TII->get(Mips::LW)) + .addDef(Temp) + .addUse(Address) + .addImm(Imm); + BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Dest).addUse(Temp); + } else { + // Mips release 5 needs to use instructions that can load from an unaligned + // memory address. + Register LoadHalf = MRI.createVirtualRegister(&Mips::GPR32RegClass); + Register LoadFull = MRI.createVirtualRegister(&Mips::GPR32RegClass); + Register Undef = MRI.createVirtualRegister(&Mips::GPR32RegClass); + BuildMI(*BB, I, DL, TII->get(Mips::IMPLICIT_DEF)).addDef(Undef); + BuildMI(*BB, I, DL, TII->get(Mips::LWR)) + .addDef(LoadHalf) + .addUse(Address) + .addImm(Imm + (IsLittle ? 0 : 3)) + .addUse(Undef); + BuildMI(*BB, I, DL, TII->get(Mips::LWL)) + .addDef(LoadFull) + .addUse(Address) + .addImm(Imm + (IsLittle ? 3 : 0)) + .addUse(LoadHalf); + BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Dest).addUse(LoadFull); + } + + MI.eraseFromParent(); + return BB; +} + +MachineBasicBlock *MipsTargetLowering::emitLDR_D(MachineInstr &MI, + MachineBasicBlock *BB) const { + MachineFunction *MF = BB->getParent(); + MachineRegisterInfo &MRI = MF->getRegInfo(); + const TargetInstrInfo *TII = Subtarget.getInstrInfo(); + const bool IsLittle = Subtarget.isLittle(); + DebugLoc DL = MI.getDebugLoc(); + + Register Dest = MI.getOperand(0).getReg(); + Register Address = MI.getOperand(1).getReg(); + unsigned Imm = MI.getOperand(2).getImm(); + + MachineBasicBlock::iterator I(MI); + + if (Subtarget.hasMips32r6() || Subtarget.hasMips64r6()) { + // Mips release 6 can load from adress that is not naturally-aligned. + if (Subtarget.isGP64bit()) { + Register Temp = MRI.createVirtualRegister(&Mips::GPR64RegClass); + BuildMI(*BB, I, DL, TII->get(Mips::LD)) + .addDef(Temp) + .addUse(Address) + .addImm(Imm); + BuildMI(*BB, I, DL, TII->get(Mips::FILL_D)).addDef(Dest).addUse(Temp); + } else { + Register Wtemp = MRI.createVirtualRegister(&Mips::MSA128WRegClass); + Register Lo = MRI.createVirtualRegister(&Mips::GPR32RegClass); + Register Hi = MRI.createVirtualRegister(&Mips::GPR32RegClass); + BuildMI(*BB, I, DL, TII->get(Mips::LW)) + .addDef(Lo) + .addUse(Address) + .addImm(Imm + (IsLittle ? 0 : 4)); + BuildMI(*BB, I, DL, TII->get(Mips::LW)) + .addDef(Hi) + .addUse(Address) + .addImm(Imm + (IsLittle ? 4 : 0)); + BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Wtemp).addUse(Lo); + BuildMI(*BB, I, DL, TII->get(Mips::INSERT_W), Dest) + .addUse(Wtemp) + .addUse(Hi) + .addImm(1); + } + } else { + // Mips release 5 needs to use instructions that can load from an unaligned + // memory address. + Register LoHalf = MRI.createVirtualRegister(&Mips::GPR32RegClass); + Register LoFull = MRI.createVirtualRegister(&Mips::GPR32RegClass); + Register LoUndef = MRI.createVirtualRegister(&Mips::GPR32RegClass); + Register HiHalf = MRI.createVirtualRegister(&Mips::GPR32RegClass); + Register HiFull = MRI.createVirtualRegister(&Mips::GPR32RegClass); + Register HiUndef = MRI.createVirtualRegister(&Mips::GPR32RegClass); + Register Wtemp = MRI.createVirtualRegister(&Mips::MSA128WRegClass); + BuildMI(*BB, I, DL, TII->get(Mips::IMPLICIT_DEF)).addDef(LoUndef); + BuildMI(*BB, I, DL, TII->get(Mips::LWR)) + .addDef(LoHalf) + .addUse(Address) + .addImm(Imm + (IsLittle ? 0 : 7)) + .addUse(LoUndef); + BuildMI(*BB, I, DL, TII->get(Mips::LWL)) + .addDef(LoFull) + .addUse(Address) + .addImm(Imm + (IsLittle ? 3 : 4)) + .addUse(LoHalf); + BuildMI(*BB, I, DL, TII->get(Mips::IMPLICIT_DEF)).addDef(HiUndef); + BuildMI(*BB, I, DL, TII->get(Mips::LWR)) + .addDef(HiHalf) + .addUse(Address) + .addImm(Imm + (IsLittle ? 4 : 3)) + .addUse(HiUndef); + BuildMI(*BB, I, DL, TII->get(Mips::LWL)) + .addDef(HiFull) + .addUse(Address) + .addImm(Imm + (IsLittle ? 7 : 0)) + .addUse(HiHalf); + BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Wtemp).addUse(LoFull); + BuildMI(*BB, I, DL, TII->get(Mips::INSERT_W), Dest) + .addUse(Wtemp) + .addUse(HiFull) + .addImm(1); + } + + MI.eraseFromParent(); + return BB; +} + +MachineBasicBlock *MipsTargetLowering::emitSTR_W(MachineInstr &MI, + MachineBasicBlock *BB) const { + MachineFunction *MF = BB->getParent(); + MachineRegisterInfo &MRI = MF->getRegInfo(); + const TargetInstrInfo *TII = Subtarget.getInstrInfo(); + const bool IsLittle = Subtarget.isLittle(); + DebugLoc DL = MI.getDebugLoc(); + + Register StoreVal = MI.getOperand(0).getReg(); + Register Address = MI.getOperand(1).getReg(); + unsigned Imm = MI.getOperand(2).getImm(); + + MachineBasicBlock::iterator I(MI); + + if (Subtarget.hasMips32r6() || Subtarget.hasMips64r6()) { + // Mips release 6 can store to adress that is not naturally-aligned. + Register BitcastW = MRI.createVirtualRegister(&Mips::MSA128WRegClass); + Register Tmp = MRI.createVirtualRegister(&Mips::GPR32RegClass); + BuildMI(*BB, I, DL, TII->get(Mips::COPY)).addDef(BitcastW).addUse(StoreVal); + BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W)) + .addDef(Tmp) + .addUse(BitcastW) + .addImm(0); + BuildMI(*BB, I, DL, TII->get(Mips::SW)) + .addUse(Tmp) + .addUse(Address) + .addImm(Imm); + } else { + // Mips release 5 needs to use instructions that can store to an unaligned + // memory address. + Register Tmp = MRI.createVirtualRegister(&Mips::GPR32RegClass); + BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W)) + .addDef(Tmp) + .addUse(StoreVal) + .addImm(0); + BuildMI(*BB, I, DL, TII->get(Mips::SWR)) + .addUse(Tmp) + .addUse(Address) + .addImm(Imm + (IsLittle ? 0 : 3)); + BuildMI(*BB, I, DL, TII->get(Mips::SWL)) + .addUse(Tmp) + .addUse(Address) + .addImm(Imm + (IsLittle ? 3 : 0)); + } + + MI.eraseFromParent(); + + return BB; +} + +MachineBasicBlock *MipsTargetLowering::emitSTR_D(MachineInstr &MI, + MachineBasicBlock *BB) const { + MachineFunction *MF = BB->getParent(); + MachineRegisterInfo &MRI = MF->getRegInfo(); + const TargetInstrInfo *TII = Subtarget.getInstrInfo(); + const bool IsLittle = Subtarget.isLittle(); + DebugLoc DL = MI.getDebugLoc(); + + Register StoreVal = MI.getOperand(0).getReg(); + Register Address = MI.getOperand(1).getReg(); + unsigned Imm = MI.getOperand(2).getImm(); + + MachineBasicBlock::iterator I(MI); + + if (Subtarget.hasMips32r6() || Subtarget.hasMips64r6()) { + // Mips release 6 can store to adress that is not naturally-aligned. + if (Subtarget.isGP64bit()) { + Register BitcastD = MRI.createVirtualRegister(&Mips::MSA128DRegClass); + Register Lo = MRI.createVirtualRegister(&Mips::GPR64RegClass); + BuildMI(*BB, I, DL, TII->get(Mips::COPY)) + .addDef(BitcastD) + .addUse(StoreVal); + BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_D)) + .addDef(Lo) + .addUse(BitcastD) + .addImm(0); + BuildMI(*BB, I, DL, TII->get(Mips::SD)) + .addUse(Lo) + .addUse(Address) + .addImm(Imm); + } else { + Register BitcastW = MRI.createVirtualRegister(&Mips::MSA128WRegClass); + Register Lo = MRI.createVirtualRegister(&Mips::GPR32RegClass); + Register Hi = MRI.createVirtualRegister(&Mips::GPR32RegClass); + BuildMI(*BB, I, DL, TII->get(Mips::COPY)) + .addDef(BitcastW) + .addUse(StoreVal); + BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W)) + .addDef(Lo) + .addUse(BitcastW) + .addImm(0); + BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W)) + .addDef(Hi) + .addUse(BitcastW) + .addImm(1); + BuildMI(*BB, I, DL, TII->get(Mips::SW)) + .addUse(Lo) + .addUse(Address) + .addImm(Imm + (IsLittle ? 0 : 4)); + BuildMI(*BB, I, DL, TII->get(Mips::SW)) + .addUse(Hi) + .addUse(Address) + .addImm(Imm + (IsLittle ? 4 : 0)); + } + } else { + // Mips release 5 needs to use instructions that can store to an unaligned + // memory address. + Register Bitcast = MRI.createVirtualRegister(&Mips::MSA128WRegClass); + Register Lo = MRI.createVirtualRegister(&Mips::GPR32RegClass); + Register Hi = MRI.createVirtualRegister(&Mips::GPR32RegClass); + BuildMI(*BB, I, DL, TII->get(Mips::COPY)).addDef(Bitcast).addUse(StoreVal); + BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W)) + .addDef(Lo) + .addUse(Bitcast) + .addImm(0); + BuildMI(*BB, I, DL, TII->get(Mips::COPY_S_W)) + .addDef(Hi) + .addUse(Bitcast) + .addImm(1); + BuildMI(*BB, I, DL, TII->get(Mips::SWR)) + .addUse(Lo) + .addUse(Address) + .addImm(Imm + (IsLittle ? 0 : 3)); + BuildMI(*BB, I, DL, TII->get(Mips::SWL)) + .addUse(Lo) + .addUse(Address) + .addImm(Imm + (IsLittle ? 3 : 0)); + BuildMI(*BB, I, DL, TII->get(Mips::SWR)) + .addUse(Hi) + .addUse(Address) + .addImm(Imm + (IsLittle ? 4 : 7)); + BuildMI(*BB, I, DL, TII->get(Mips::SWL)) + .addUse(Hi) + .addUse(Address) + .addImm(Imm + (IsLittle ? 7 : 4)); + } + + MI.eraseFromParent(); + return BB; +} diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsISelLowering.h b/contrib/llvm-project/llvm/lib/Target/Mips/MipsISelLowering.h index 92cbe1d54c5b..16b4d51d3ca6 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsISelLowering.h +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsISelLowering.h @@ -306,7 +306,7 @@ class TargetRegisterClass; /// Return the correct alignment for the current calling convention. Align getABIAlignmentForCallingConv(Type *ArgTy, DataLayout DL) const override { - const Align ABIAlign(DL.getABITypeAlignment(ArgTy)); + const Align ABIAlign = DL.getABITypeAlign(ArgTy); if (ArgTy->isVectorTy()) return std::min(ABIAlign, Align(8)); return ABIAlign; @@ -346,21 +346,21 @@ class TargetRegisterClass; void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override; - void HandleByVal(CCState *, unsigned &, unsigned) const override; + void HandleByVal(CCState *, unsigned &, Align) const override; Register getRegisterByName(const char* RegName, LLT VT, const MachineFunction &MF) const override; /// If a physical register, this returns the register that receives the /// exception address on entry to an EH pad. - unsigned + Register getExceptionPointerRegister(const Constant *PersonalityFn) const override { return ABI.IsN64() ? Mips::A0_64 : Mips::A0; } /// If a physical register, this returns the register that receives the /// exception typeid on entry to a landing pad. - unsigned + Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override { return ABI.IsN64() ? Mips::A1_64 : Mips::A1; } @@ -669,10 +669,7 @@ class TargetRegisterClass; bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; - EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, - unsigned SrcAlign, - bool IsMemset, bool ZeroMemset, - bool MemcpyStrSrc, + EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override; /// isFPImmLegal - Returns true if the target can instruction select the @@ -709,6 +706,10 @@ class TargetRegisterClass; bool isFPCmp, unsigned Opc) const; MachineBasicBlock *emitPseudoD_SELECT(MachineInstr &MI, MachineBasicBlock *BB) const; + MachineBasicBlock *emitLDR_W(MachineInstr &MI, MachineBasicBlock *BB) const; + MachineBasicBlock *emitLDR_D(MachineInstr &MI, MachineBasicBlock *BB) const; + MachineBasicBlock *emitSTR_W(MachineInstr &MI, MachineBasicBlock *BB) const; + MachineBasicBlock *emitSTR_D(MachineInstr &MI, MachineBasicBlock *BB) const; }; /// Create MipsTargetLowering objects. diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsInstrFPU.td b/contrib/llvm-project/llvm/lib/Target/Mips/MipsInstrFPU.td index 79776998463f..5696df96e798 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsInstrFPU.td +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsInstrFPU.td @@ -48,6 +48,7 @@ def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond, [SDNPHasChain, SDNPOptInGlue]>; def MipsTruncIntFP : SDNode<"MipsISD::TruncIntFP", SDT_MipsTruncIntFP>; def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>; +def : GINodeEquiv<G_MERGE_VALUES, MipsBuildPairF64>; def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64", SDT_MipsExtractElementF64>; @@ -62,15 +63,17 @@ let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in //===----------------------------------------------------------------------===// def IsFP64bit : Predicate<"Subtarget->isFP64bit()">, - AssemblerPredicate<"FeatureFP64Bit">; + AssemblerPredicate<(all_of FeatureFP64Bit)>; def NotFP64bit : Predicate<"!Subtarget->isFP64bit()">, - AssemblerPredicate<"!FeatureFP64Bit">; + AssemblerPredicate<(all_of (not FeatureFP64Bit))>; def IsSingleFloat : Predicate<"Subtarget->isSingleFloat()">, - AssemblerPredicate<"FeatureSingleFloat">; + AssemblerPredicate<(all_of FeatureSingleFloat)>; def IsNotSingleFloat : Predicate<"!Subtarget->isSingleFloat()">, - AssemblerPredicate<"!FeatureSingleFloat">; + AssemblerPredicate<(all_of (not FeatureSingleFloat))>; def IsNotSoftFloat : Predicate<"!Subtarget->useSoftFloat()">, - AssemblerPredicate<"!FeatureSoftFloat">; + AssemblerPredicate<(all_of (not FeatureSoftFloat))>; +def HasMips3D : Predicate<"Subtarget->has3D()">, + AssemblerPredicate<(all_of FeatureMips3D)>; //===----------------------------------------------------------------------===// // Mips FGR size adjectives. @@ -455,6 +458,12 @@ let DecoderNamespace = "MipsFP64" in { def PLU_PS64 : ADDS_FT<"plu.ps", FGR64Opnd, II_CVT, 0>, ADDS_FM<0x2D, 22>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; + def PUL_PS64 : ADDS_FT<"pul.ps", FGR64Opnd, II_CVT, 0>, + ADDS_FM<0x2E, 22>, + ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; + def PUU_PS64 : ADDS_FT<"puu.ps", FGR64Opnd, II_CVT, 0>, + ADDS_FM<0x2F, 22>, + ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; def CVT_S_PU64 : ABSS_FT<"cvt.s.pu", FGR32Opnd, FGR64Opnd, II_CVT>, ABSS_FM<0x20, 22>, @@ -470,6 +479,21 @@ let DecoderNamespace = "MipsFP64" in { } let DecoderNamespace = "MipsFP64" in { + let AdditionalPredicates = [HasMips3D] in { + def ADDR_PS64 : ADDS_FT<"addr.ps", FGR64Opnd, II_ADDR_PS, 0>, + ADDS_FM<0x18, 22>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; + def MULR_PS64 : ADDS_FT<"mulr.ps", FGR64Opnd, II_MULR_PS, 0>, + ADDS_FM<0x1a, 22>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; + def CVT_PS_PW64 : ABSS_FT<"cvt.ps.pw", FGR64Opnd, FGR64Opnd, II_CVT>, + ABSS_FM<0x26, 20>, + ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; + def CVT_PW_PS64 : ABSS_FT<"cvt.pw.ps", FGR64Opnd, FGR64Opnd, II_CVT>, + ABSS_FM<0x24, 22>, + ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; + } +} + +let DecoderNamespace = "MipsFP64" in { let AdditionalPredicates = [NotInMicroMips] in { def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>, ABSS_FM<0x20, 21>, INSN_MIPS3_32R2, FGR_64; diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsInstrFormats.td b/contrib/llvm-project/llvm/lib/Target/Mips/MipsInstrFormats.td index 4624c1f2d04a..10529c7d9e19 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsInstrFormats.td +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsInstrFormats.td @@ -169,39 +169,6 @@ class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr, } //===----------------------------------------------------------------------===// -// Format I instruction class in Mips : <|opcode|rs|rt|immediate|> -//===----------------------------------------------------------------------===// - -class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, - InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI> -{ - bits<5> rt; - bits<5> rs; - bits<16> imm16; - - let Opcode = op; - - let Inst{25-21} = rs; - let Inst{20-16} = rt; - let Inst{15-0} = imm16; -} - -class BranchBase<bits<6> op, dag outs, dag ins, string asmstr, - list<dag> pattern, InstrItinClass itin>: - InstSE<outs, ins, asmstr, pattern, itin, FrmI> -{ - bits<5> rs; - bits<5> rt; - bits<16> imm16; - - let Opcode = op; - - let Inst{25-21} = rs; - let Inst{20-16} = rt; - let Inst{15-0} = imm16; -} - -//===----------------------------------------------------------------------===// // Format J instruction class in Mips : <|opcode|address|> //===----------------------------------------------------------------------===// @@ -711,20 +678,6 @@ class EI_FM<bits<1> sc> : StdArch // Format FI instruction class in Mips : <|opcode|base|ft|immediate|> //===----------------------------------------------------------------------===// -class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>: - InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI> -{ - bits<5> ft; - bits<5> base; - bits<16> imm16; - - let Opcode = op; - - let Inst{25-21} = base; - let Inst{20-16} = ft; - let Inst{15-0} = imm16; -} - class ADDS_FM<bits<6> funct, bits<5> fmt> : StdArch { bits<5> fd; bits<5> fs; diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsInstrInfo.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/MipsInstrInfo.cpp index 25bbe5990827..0c6080258a3a 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsInstrInfo.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsInstrInfo.cpp @@ -23,6 +23,7 @@ #include "llvm/CodeGen/MachineOperand.h" #include "llvm/CodeGen/TargetOpcodes.h" #include "llvm/CodeGen/TargetSubtargetInfo.h" +#include "llvm/IR/DebugInfoMetadata.h" #include "llvm/IR/DebugLoc.h" #include "llvm/MC/MCInstrDesc.h" #include "llvm/Target/TargetMachine.h" @@ -66,10 +67,10 @@ MipsInstrInfo::GetMemOperand(MachineBasicBlock &MBB, int FI, MachineMemOperand::Flags Flags) const { MachineFunction &MF = *MBB.getParent(); MachineFrameInfo &MFI = MF.getFrameInfo(); - unsigned Align = MFI.getObjectAlignment(FI); return MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, FI), - Flags, MFI.getObjectSize(FI), Align); + Flags, MFI.getObjectSize(FI), + MFI.getObjectAlign(FI)); } //===----------------------------------------------------------------------===// @@ -841,3 +842,56 @@ MipsInstrInfo::getSerializableDirectMachineOperandTargetFlags() const { }; return makeArrayRef(Flags); } + +Optional<ParamLoadedValue> +MipsInstrInfo::describeLoadedValue(const MachineInstr &MI, Register Reg) const { + DIExpression *Expr = + DIExpression::get(MI.getMF()->getFunction().getContext(), {}); + + // TODO: Special MIPS instructions that need to be described separately. + if (auto RegImm = isAddImmediate(MI, Reg)) { + Register SrcReg = RegImm->Reg; + int64_t Offset = RegImm->Imm; + // When SrcReg is $zero, treat loaded value as immediate only. + // Ex. $a2 = ADDiu $zero, 10 + if (SrcReg == Mips::ZERO || SrcReg == Mips::ZERO_64) { + return ParamLoadedValue(MI.getOperand(2), Expr); + } + Expr = DIExpression::prepend(Expr, DIExpression::ApplyOffset, Offset); + return ParamLoadedValue(MachineOperand::CreateReg(SrcReg, false), Expr); + } else if (auto DestSrc = isCopyInstr(MI)) { + const MachineFunction *MF = MI.getMF(); + const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); + Register DestReg = DestSrc->Destination->getReg(); + // TODO: Handle cases where the Reg is sub- or super-register of the + // DestReg. + if (TRI->isSuperRegister(Reg, DestReg) || TRI->isSubRegister(Reg, DestReg)) + return None; + } + + return TargetInstrInfo::describeLoadedValue(MI, Reg); +} + +Optional<RegImmPair> MipsInstrInfo::isAddImmediate(const MachineInstr &MI, + Register Reg) const { + // TODO: Handle cases where Reg is a super- or sub-register of the + // destination register. + const MachineOperand &Op0 = MI.getOperand(0); + if (!Op0.isReg() || Reg != Op0.getReg()) + return None; + + switch (MI.getOpcode()) { + case Mips::ADDiu: + case Mips::DADDiu: { + const MachineOperand &Dop = MI.getOperand(0); + const MachineOperand &Sop1 = MI.getOperand(1); + const MachineOperand &Sop2 = MI.getOperand(2); + // Value is sum of register and immediate. Immediate value could be + // global string address which is not supported. + if (Dop.isReg() && Sop1.isReg() && Sop2.isImm()) + return RegImmPair{Sop1.getReg(), Sop2.getImm()}; + // TODO: Handle case where Sop1 is a frame-index. + } + } + return None; +}
\ No newline at end of file diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsInstrInfo.h b/contrib/llvm-project/llvm/lib/Target/Mips/MipsInstrInfo.h index 092a960b4ba7..c96ed202df30 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsInstrInfo.h +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsInstrInfo.h @@ -106,12 +106,16 @@ public: virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0; + virtual bool isBranchWithImm(unsigned Opc) const { + return false; + } + /// Return the number of bytes of code the specified instruction may be. unsigned getInstSizeInBytes(const MachineInstr &MI) const override; void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, - unsigned SrcReg, bool isKill, int FrameIndex, + Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override { storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0); @@ -119,7 +123,7 @@ public: void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, - unsigned DestReg, int FrameIndex, + Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override { loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0); @@ -127,14 +131,14 @@ public: virtual void storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, - unsigned SrcReg, bool isKill, int FrameIndex, + Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const = 0; virtual void loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, - unsigned DestReg, int FrameIndex, + Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const = 0; @@ -161,6 +165,12 @@ public: ArrayRef<std::pair<unsigned, const char *>> getSerializableDirectMachineOperandTargetFlags() const override; + Optional<RegImmPair> isAddImmediate(const MachineInstr &MI, + Register Reg) const override; + + Optional<ParamLoadedValue> describeLoadedValue(const MachineInstr &MI, + Register Reg) const override; + protected: bool isZeroImm(const MachineOperand &op) const; diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsInstrInfo.td b/contrib/llvm-project/llvm/lib/Target/Mips/MipsInstrInfo.td index d9a3ff802708..a3b928870f3f 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -156,69 +156,69 @@ def MipsSDR : SDNode<"MipsISD::SDR", SDTStore, // Mips Instruction Predicate Definitions. //===----------------------------------------------------------------------===// def HasMips2 : Predicate<"Subtarget->hasMips2()">, - AssemblerPredicate<"FeatureMips2">; + AssemblerPredicate<(all_of FeatureMips2)>; def HasMips3_32 : Predicate<"Subtarget->hasMips3_32()">, - AssemblerPredicate<"FeatureMips3_32">; + AssemblerPredicate<(all_of FeatureMips3_32)>; def HasMips3_32r2 : Predicate<"Subtarget->hasMips3_32r2()">, - AssemblerPredicate<"FeatureMips3_32r2">; + AssemblerPredicate<(all_of FeatureMips3_32r2)>; def HasMips3 : Predicate<"Subtarget->hasMips3()">, - AssemblerPredicate<"FeatureMips3">; + AssemblerPredicate<(all_of FeatureMips3)>; def NotMips3 : Predicate<"!Subtarget->hasMips3()">, - AssemblerPredicate<"!FeatureMips3">; + AssemblerPredicate<(all_of (not FeatureMips3))>; def HasMips4_32 : Predicate<"Subtarget->hasMips4_32()">, - AssemblerPredicate<"FeatureMips4_32">; + AssemblerPredicate<(all_of FeatureMips4_32)>; def NotMips4_32 : Predicate<"!Subtarget->hasMips4_32()">, - AssemblerPredicate<"!FeatureMips4_32">; + AssemblerPredicate<(all_of (not FeatureMips4_32))>; def HasMips4_32r2 : Predicate<"Subtarget->hasMips4_32r2()">, - AssemblerPredicate<"FeatureMips4_32r2">; + AssemblerPredicate<(all_of FeatureMips4_32r2)>; def HasMips5_32r2 : Predicate<"Subtarget->hasMips5_32r2()">, - AssemblerPredicate<"FeatureMips5_32r2">; + AssemblerPredicate<(all_of FeatureMips5_32r2)>; def HasMips32 : Predicate<"Subtarget->hasMips32()">, - AssemblerPredicate<"FeatureMips32">; + AssemblerPredicate<(all_of FeatureMips32)>; def HasMips32r2 : Predicate<"Subtarget->hasMips32r2()">, - AssemblerPredicate<"FeatureMips32r2">; + AssemblerPredicate<(all_of FeatureMips32r2)>; def HasMips32r5 : Predicate<"Subtarget->hasMips32r5()">, - AssemblerPredicate<"FeatureMips32r5">; + AssemblerPredicate<(all_of FeatureMips32r5)>; def HasMips32r6 : Predicate<"Subtarget->hasMips32r6()">, - AssemblerPredicate<"FeatureMips32r6">; + AssemblerPredicate<(all_of FeatureMips32r6)>; def NotMips32r6 : Predicate<"!Subtarget->hasMips32r6()">, - AssemblerPredicate<"!FeatureMips32r6">; + AssemblerPredicate<(all_of (not FeatureMips32r6))>; def IsGP64bit : Predicate<"Subtarget->isGP64bit()">, - AssemblerPredicate<"FeatureGP64Bit">; + AssemblerPredicate<(all_of FeatureGP64Bit)>; def IsGP32bit : Predicate<"!Subtarget->isGP64bit()">, - AssemblerPredicate<"!FeatureGP64Bit">; + AssemblerPredicate<(all_of (not FeatureGP64Bit))>; def IsPTR64bit : Predicate<"Subtarget->isABI_N64()">, - AssemblerPredicate<"FeaturePTR64Bit">; + AssemblerPredicate<(all_of FeaturePTR64Bit)>; def IsPTR32bit : Predicate<"!Subtarget->isABI_N64()">, - AssemblerPredicate<"!FeaturePTR64Bit">; + AssemblerPredicate<(all_of (not FeaturePTR64Bit))>; def HasMips64 : Predicate<"Subtarget->hasMips64()">, - AssemblerPredicate<"FeatureMips64">; + AssemblerPredicate<(all_of FeatureMips64)>; def NotMips64 : Predicate<"!Subtarget->hasMips64()">, - AssemblerPredicate<"!FeatureMips64">; + AssemblerPredicate<(all_of (not FeatureMips64))>; def HasMips64r2 : Predicate<"Subtarget->hasMips64r2()">, - AssemblerPredicate<"FeatureMips64r2">; + AssemblerPredicate<(all_of FeatureMips64r2)>; def HasMips64r5 : Predicate<"Subtarget->hasMips64r5()">, - AssemblerPredicate<"FeatureMips64r5">; + AssemblerPredicate<(all_of FeatureMips64r5)>; def HasMips64r6 : Predicate<"Subtarget->hasMips64r6()">, - AssemblerPredicate<"FeatureMips64r6">; + AssemblerPredicate<(all_of FeatureMips64r6)>; def NotMips64r6 : Predicate<"!Subtarget->hasMips64r6()">, - AssemblerPredicate<"!FeatureMips64r6">; + AssemblerPredicate<(all_of (not FeatureMips64r6))>; def InMips16Mode : Predicate<"Subtarget->inMips16Mode()">, - AssemblerPredicate<"FeatureMips16">; + AssemblerPredicate<(all_of FeatureMips16)>; def NotInMips16Mode : Predicate<"!Subtarget->inMips16Mode()">, - AssemblerPredicate<"!FeatureMips16">; + AssemblerPredicate<(all_of (not FeatureMips16))>; def HasCnMips : Predicate<"Subtarget->hasCnMips()">, - AssemblerPredicate<"FeatureCnMips">; + AssemblerPredicate<(all_of FeatureCnMips)>; def NotCnMips : Predicate<"!Subtarget->hasCnMips()">, - AssemblerPredicate<"!FeatureCnMips">; + AssemblerPredicate<(all_of (not FeatureCnMips))>; def HasCnMipsP : Predicate<"Subtarget->hasCnMipsP()">, - AssemblerPredicate<"FeatureCnMipsP">; + AssemblerPredicate<(all_of FeatureCnMipsP)>; def NotCnMipsP : Predicate<"!Subtarget->hasCnMipsP()">, - AssemblerPredicate<"!FeatureCnMipsP">; + AssemblerPredicate<(all_of (not FeatureCnMipsP))>; def IsSym32 : Predicate<"Subtarget->hasSym32()">, - AssemblerPredicate<"FeatureSym32">; + AssemblerPredicate<(all_of FeatureSym32)>; def IsSym64 : Predicate<"!Subtarget->hasSym32()">, - AssemblerPredicate<"!FeatureSym32">; + AssemblerPredicate<(all_of (not FeatureSym32))>; def IsN64 : Predicate<"Subtarget->isABI_N64()">; def IsNotN64 : Predicate<"!Subtarget->isABI_N64()">; def RelocNotPIC : Predicate<"!TM.isPositionIndependent()">; @@ -227,34 +227,34 @@ def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">; def UseAbs : Predicate<"Subtarget->inAbs2008Mode() ||" "TM.Options.NoNaNsFPMath">; def HasStdEnc : Predicate<"Subtarget->hasStandardEncoding()">, - AssemblerPredicate<"!FeatureMips16">; + AssemblerPredicate<(all_of (not FeatureMips16))>; def NotDSP : Predicate<"!Subtarget->hasDSP()">; def InMicroMips : Predicate<"Subtarget->inMicroMipsMode()">, - AssemblerPredicate<"FeatureMicroMips">; + AssemblerPredicate<(all_of FeatureMicroMips)>; def NotInMicroMips : Predicate<"!Subtarget->inMicroMipsMode()">, - AssemblerPredicate<"!FeatureMicroMips">; + AssemblerPredicate<(all_of (not FeatureMicroMips))>; def IsLE : Predicate<"Subtarget->isLittle()">; def IsBE : Predicate<"!Subtarget->isLittle()">; def IsNotNaCl : Predicate<"!Subtarget->isTargetNaCl()">; -def UseTCCInDIV : AssemblerPredicate<"FeatureUseTCCInDIV">; +def UseTCCInDIV : AssemblerPredicate<(all_of FeatureUseTCCInDIV)>; def HasEVA : Predicate<"Subtarget->hasEVA()">, - AssemblerPredicate<"FeatureEVA">; + AssemblerPredicate<(all_of FeatureEVA)>; def HasMSA : Predicate<"Subtarget->hasMSA()">, - AssemblerPredicate<"FeatureMSA">; + AssemblerPredicate<(all_of FeatureMSA)>; def HasMadd4 : Predicate<"!Subtarget->disableMadd4()">, - AssemblerPredicate<"!FeatureMadd4">; + AssemblerPredicate<(all_of (not FeatureMadd4))>; def HasMT : Predicate<"Subtarget->hasMT()">, - AssemblerPredicate<"FeatureMT">; + AssemblerPredicate<(all_of FeatureMT)>; def UseIndirectJumpsHazard : Predicate<"Subtarget->useIndirectJumpsHazard()">, - AssemblerPredicate<"FeatureUseIndirectJumpsHazard">; + AssemblerPredicate<(all_of FeatureUseIndirectJumpsHazard)>; def NoIndirectJumpGuards : Predicate<"!Subtarget->useIndirectJumpsHazard()">, - AssemblerPredicate<"!FeatureUseIndirectJumpsHazard">; + AssemblerPredicate<(all_of (not FeatureUseIndirectJumpsHazard))>; def HasCRC : Predicate<"Subtarget->hasCRC()">, - AssemblerPredicate<"FeatureCRC">; + AssemblerPredicate<(all_of FeatureCRC)>; def HasVirt : Predicate<"Subtarget->hasVirt()">, - AssemblerPredicate<"FeatureVirt">; + AssemblerPredicate<(all_of FeatureVirt)>; def HasGINV : Predicate<"Subtarget->hasGINV()">, - AssemblerPredicate<"FeatureGINV">; + AssemblerPredicate<(all_of FeatureGINV)>; // TODO: Add support for FPOpFusion::Standard def AllowFPOpFusion : Predicate<"TM.Options.AllowFPOpFusion ==" " FPOpFusion::Fast">; @@ -498,7 +498,7 @@ class MADD4 { list<Predicate> AdditionalPredicates = [HasMadd4]; } -// Classses used for separating expansions that differ based on the ABI in +// Classes used for separating expansions that differ based on the ABI in // use. class ABI_N64 { list<Predicate> AdditionalPredicates = [IsN64]; @@ -1286,7 +1286,7 @@ def LUiORiPred : PatLeaf<(imm), [{ return isInt<32>(SVal) && (SVal & 0xffff); }]>; -// Mips Address Mode! SDNode frameindex could possibily be a match +// Mips Address Mode! SDNode frameindex could possibly be a match // since load and store instructions from stack used it. def addr : ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>; @@ -1871,10 +1871,11 @@ class MTC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD, class TrapBase<Instruction RealInst> : PseudoSE<(outs), (ins), [(trap)], II_TRAP>, PseudoInstExpansion<(RealInst 0, 0)> { - let isBarrier = 1; - let isTerminator = 1; + let mayStore = 0; + let mayLoad = 0; + let hasSideEffects = 1; + let isTrap = 1; let isCodeGenOnly = 1; - let isCTI = 1; } //===----------------------------------------------------------------------===// @@ -2588,6 +2589,22 @@ def : MipsInstAlias<"seq $rd, $imm", (SEQIMacro GPR32Opnd:$rd, GPR32Opnd:$rd, simm32:$imm), 0>, NOT_ASE_CNMIPS; +def SNEMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), + (ins GPR32Opnd:$rs, GPR32Opnd:$rt), + "sne $rd, $rs, $rt">, NOT_ASE_CNMIPS; + +def : MipsInstAlias<"sne $rd, $rs", + (SNEMacro GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>, + NOT_ASE_CNMIPS; + +def SNEIMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), + (ins GPR32Opnd:$rs, simm32_relaxed:$imm), + "sne $rd, $rs, $imm">, NOT_ASE_CNMIPS; + +def : MipsInstAlias<"sne $rd, $imm", + (SNEIMacro GPR32Opnd:$rd, GPR32Opnd:$rd, simm32:$imm), 0>, + NOT_ASE_CNMIPS; + def MULImmMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rd, GPR32Opnd:$rs, simm32_relaxed:$imm), "mul\t$rd, $rs, $imm">, @@ -2735,6 +2752,34 @@ let AdditionalPredicates = [NotInMicroMips] in { uimm32_coerced:$imm), 0>, GPR_32; + def SLE : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), + (ins GPR32Opnd:$rs, GPR32Opnd:$rt), + "sle\t$rd, $rs, $rt">, ISA_MIPS1; + def : MipsInstAlias<"sle $rs, $rt", + (SLE GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), 0>, + ISA_MIPS1; + def SLEImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), + (ins GPR32Opnd:$rs, simm32:$imm), + "sle\t$rd, $rs, $imm">, GPR_32; + def : MipsInstAlias<"sle $rs, $imm", (SLEImm GPR32Opnd:$rs, + GPR32Opnd:$rs, + simm32:$imm), 0>, + GPR_32; + + def SLEU : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), + (ins GPR32Opnd:$rs, GPR32Opnd:$rt), + "sleu\t$rd, $rs, $rt">, ISA_MIPS1; + def : MipsInstAlias<"sleu $rs, $rt", + (SLEU GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), 0>, + ISA_MIPS1; + def SLEUImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), + (ins GPR32Opnd:$rs, uimm32_coerced:$imm), + "sleu\t$rd, $rs, $imm">, GPR_32; + def : MipsInstAlias<"sleu $rs, $imm", (SLEUImm GPR32Opnd:$rs, + GPR32Opnd:$rs, + uimm32_coerced:$imm), 0>, + GPR_32; + def : MipsInstAlias< "not $rt, $rs", (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>, ISA_MIPS1; diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsInstructionSelector.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/MipsInstructionSelector.cpp index 2f4c9d74262e..256fb74c1d6c 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsInstructionSelector.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsInstructionSelector.cpp @@ -49,6 +49,12 @@ private: getRegClassForTypeOnBank(Register Reg, MachineRegisterInfo &MRI) const; unsigned selectLoadStoreOpCode(MachineInstr &I, MachineRegisterInfo &MRI) const; + bool buildUnalignedStore(MachineInstr &I, unsigned Opc, + MachineOperand &BaseAddr, unsigned Offset, + MachineMemOperand *MMO) const; + bool buildUnalignedLoad(MachineInstr &I, unsigned Opc, Register Dest, + MachineOperand &BaseAddr, unsigned Offset, + Register TiedDest, MachineMemOperand *MMO) const; const MipsTargetMachine &TM; const MipsSubtarget &STI; @@ -248,6 +254,35 @@ MipsInstructionSelector::selectLoadStoreOpCode(MachineInstr &I, return Opc; } +bool MipsInstructionSelector::buildUnalignedStore( + MachineInstr &I, unsigned Opc, MachineOperand &BaseAddr, unsigned Offset, + MachineMemOperand *MMO) const { + MachineInstr *NewInst = + BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opc)) + .add(I.getOperand(0)) + .add(BaseAddr) + .addImm(Offset) + .addMemOperand(MMO); + if (!constrainSelectedInstRegOperands(*NewInst, TII, TRI, RBI)) + return false; + return true; +} + +bool MipsInstructionSelector::buildUnalignedLoad( + MachineInstr &I, unsigned Opc, Register Dest, MachineOperand &BaseAddr, + unsigned Offset, Register TiedDest, MachineMemOperand *MMO) const { + MachineInstr *NewInst = + BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opc)) + .addDef(Dest) + .add(BaseAddr) + .addImm(Offset) + .addUse(TiedDest) + .addMemOperand(*I.memoperands_begin()); + if (!constrainSelectedInstRegOperands(*NewInst, TII, TRI, RBI)) + return false; + return true; +} + bool MipsInstructionSelector::select(MachineInstr &I) { MachineBasicBlock &MBB = *I.getParent(); @@ -358,7 +393,7 @@ bool MipsInstructionSelector::select(MachineInstr &I) { .addUse(DestAddress) .addJumpTableIndex(I.getOperand(1).getIndex(), MipsII::MO_ABS_LO) .addMemOperand(MF.getMachineMemOperand( - MachinePointerInfo(), MachineMemOperand::MOLoad, 4, 4)); + MachinePointerInfo(), MachineMemOperand::MOLoad, 4, Align(4))); if (!constrainSelectedInstRegOperands(*LW, TII, TRI, RBI)) return false; @@ -369,7 +404,7 @@ bool MipsInstructionSelector::select(MachineInstr &I) { .addDef(Dest) .addUse(DestTmp) .addUse(MF.getInfo<MipsFunctionInfo>() - ->getGlobalBaseRegForGlobalISel()); + ->getGlobalBaseRegForGlobalISel(MF)); if (!constrainSelectedInstRegOperands(*ADDu, TII, TRI, RBI)) return false; } @@ -404,10 +439,7 @@ bool MipsInstructionSelector::select(MachineInstr &I) { case G_LOAD: case G_ZEXTLOAD: case G_SEXTLOAD: { - const unsigned NewOpc = selectLoadStoreOpCode(I, MRI); - if (NewOpc == I.getOpcode()) - return false; - + auto MMO = *I.memoperands_begin(); MachineOperand BaseAddr = I.getOperand(1); int64_t SignedOffset = 0; // Try to fold load/store + G_PTR_ADD + G_CONSTANT @@ -429,11 +461,48 @@ bool MipsInstructionSelector::select(MachineInstr &I) { } } + // Unaligned memory access + if (MMO->getAlign() < MMO->getSize() && + !STI.systemSupportsUnalignedAccess()) { + if (MMO->getSize() != 4 || !isRegInGprb(I.getOperand(0).getReg(), MRI)) + return false; + + if (I.getOpcode() == G_STORE) { + if (!buildUnalignedStore(I, Mips::SWL, BaseAddr, SignedOffset + 3, MMO)) + return false; + if (!buildUnalignedStore(I, Mips::SWR, BaseAddr, SignedOffset, MMO)) + return false; + I.eraseFromParent(); + return true; + } + + if (I.getOpcode() == G_LOAD) { + Register ImplDef = MRI.createVirtualRegister(&Mips::GPR32RegClass); + BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::IMPLICIT_DEF)) + .addDef(ImplDef); + Register Tmp = MRI.createVirtualRegister(&Mips::GPR32RegClass); + if (!buildUnalignedLoad(I, Mips::LWL, Tmp, BaseAddr, SignedOffset + 3, + ImplDef, MMO)) + return false; + if (!buildUnalignedLoad(I, Mips::LWR, I.getOperand(0).getReg(), + BaseAddr, SignedOffset, Tmp, MMO)) + return false; + I.eraseFromParent(); + return true; + } + + return false; + } + + const unsigned NewOpc = selectLoadStoreOpCode(I, MRI); + if (NewOpc == I.getOpcode()) + return false; + MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc)) .add(I.getOperand(0)) .add(BaseAddr) .addImm(SignedOffset) - .addMemOperand(*I.memoperands_begin()); + .addMemOperand(MMO); break; } case G_UDIV: @@ -472,6 +541,36 @@ bool MipsInstructionSelector::select(MachineInstr &I) { .add(I.getOperand(3)); break; } + case G_UNMERGE_VALUES: { + if (I.getNumOperands() != 3) + return false; + Register Src = I.getOperand(2).getReg(); + Register Lo = I.getOperand(0).getReg(); + Register Hi = I.getOperand(1).getReg(); + if (!isRegInFprb(Src, MRI) || + !(isRegInGprb(Lo, MRI) && isRegInGprb(Hi, MRI))) + return false; + + unsigned Opcode = + STI.isFP64bit() ? Mips::ExtractElementF64_64 : Mips::ExtractElementF64; + + MachineInstr *ExtractLo = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode)) + .addDef(Lo) + .addUse(Src) + .addImm(0); + if (!constrainSelectedInstRegOperands(*ExtractLo, TII, TRI, RBI)) + return false; + + MachineInstr *ExtractHi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode)) + .addDef(Hi) + .addUse(Src) + .addImm(1); + if (!constrainSelectedInstRegOperands(*ExtractHi, TII, TRI, RBI)) + return false; + + I.eraseFromParent(); + return true; + } case G_IMPLICIT_DEF: { Register Dst = I.getOperand(0).getReg(); MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::IMPLICIT_DEF)) @@ -570,7 +669,7 @@ bool MipsInstructionSelector::select(MachineInstr &I) { MachineInstr *LWGOT = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)) .addDef(I.getOperand(0).getReg()) .addReg(MF.getInfo<MipsFunctionInfo>() - ->getGlobalBaseRegForGlobalISel()) + ->getGlobalBaseRegForGlobalISel(MF)) .addGlobalAddress(GVal); // Global Values that don't have local linkage are handled differently // when they are part of call sequence. MipsCallLowering::lowerCall @@ -582,7 +681,7 @@ bool MipsInstructionSelector::select(MachineInstr &I) { LWGOT->getOperand(2).setTargetFlags(MipsII::MO_GOT); LWGOT->addMemOperand( MF, MF.getMachineMemOperand(MachinePointerInfo::getGOT(MF), - MachineMemOperand::MOLoad, 4, 4)); + MachineMemOperand::MOLoad, 4, Align(4))); if (!constrainSelectedInstRegOperands(*LWGOT, TII, TRI, RBI)) return false; @@ -626,11 +725,11 @@ bool MipsInstructionSelector::select(MachineInstr &I) { MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)) .addDef(I.getOperand(0).getReg()) .addReg(MF.getInfo<MipsFunctionInfo>() - ->getGlobalBaseRegForGlobalISel()) + ->getGlobalBaseRegForGlobalISel(MF)) .addJumpTableIndex(I.getOperand(1).getIndex(), MipsII::MO_GOT) - .addMemOperand( - MF.getMachineMemOperand(MachinePointerInfo::getGOT(MF), - MachineMemOperand::MOLoad, 4, 4)); + .addMemOperand(MF.getMachineMemOperand( + MachinePointerInfo::getGOT(MF), MachineMemOperand::MOLoad, 4, + Align(4))); } else { MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi)) diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp index 9645aa24dc05..b489c8137769 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp @@ -21,22 +21,38 @@ struct TypesAndMemOps { LLT ValTy; LLT PtrTy; unsigned MemSize; - bool MustBeNaturallyAligned; + bool SystemSupportsUnalignedAccess; }; +// Assumes power of 2 memory size. Subtargets that have only naturally-aligned +// memory access need to perform additional legalization here. +static bool isUnalignedMemmoryAccess(uint64_t MemSize, uint64_t AlignInBits) { + assert(isPowerOf2_64(MemSize) && "Expected power of 2 memory size"); + assert(isPowerOf2_64(AlignInBits) && "Expected power of 2 align"); + if (MemSize > AlignInBits) + return true; + return false; +} + static bool CheckTy0Ty1MemSizeAlign(const LegalityQuery &Query, std::initializer_list<TypesAndMemOps> SupportedValues) { + unsigned QueryMemSize = Query.MMODescrs[0].SizeInBits; + + // Non power of two memory access is never legal. + if (!isPowerOf2_64(QueryMemSize)) + return false; + for (auto &Val : SupportedValues) { if (Val.ValTy != Query.Types[0]) continue; if (Val.PtrTy != Query.Types[1]) continue; - if (Val.MemSize != Query.MMODescrs[0].SizeInBits) - continue; - if (Val.MustBeNaturallyAligned && - Query.MMODescrs[0].SizeInBits % Query.MMODescrs[0].AlignInBits != 0) + if (Val.MemSize != QueryMemSize) continue; + if (!Val.SystemSupportsUnalignedAccess && + isUnalignedMemmoryAccess(QueryMemSize, Query.MMODescrs[0].AlignInBits)) + return false; return true; } return false; @@ -79,20 +95,55 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) { .legalFor({s32}) .maxScalar(0, s32); + // MIPS32r6 does not have alignment restrictions for memory access. + // For MIPS32r5 and older memory access must be naturally-aligned i.e. aligned + // to at least a multiple of its own size. There is however a two instruction + // combination that performs 4 byte unaligned access (lwr/lwl and swl/swr) + // therefore 4 byte load and store are legal and will use NoAlignRequirements. + bool NoAlignRequirements = true; + getActionDefinitionsBuilder({G_LOAD, G_STORE}) .legalIf([=, &ST](const LegalityQuery &Query) { - if (CheckTy0Ty1MemSizeAlign(Query, {{s32, p0, 8, ST.hasMips32r6()}, - {s32, p0, 16, ST.hasMips32r6()}, - {s32, p0, 32, ST.hasMips32r6()}, - {p0, p0, 32, ST.hasMips32r6()}, - {s64, p0, 64, ST.hasMips32r6()}})) + if (CheckTy0Ty1MemSizeAlign( + Query, {{s32, p0, 8, NoAlignRequirements}, + {s32, p0, 16, ST.systemSupportsUnalignedAccess()}, + {s32, p0, 32, NoAlignRequirements}, + {p0, p0, 32, NoAlignRequirements}, + {s64, p0, 64, ST.systemSupportsUnalignedAccess()}})) + return true; + if (ST.hasMSA() && CheckTy0Ty1MemSizeAlign( + Query, {{v16s8, p0, 128, NoAlignRequirements}, + {v8s16, p0, 128, NoAlignRequirements}, + {v4s32, p0, 128, NoAlignRequirements}, + {v2s64, p0, 128, NoAlignRequirements}})) + return true; + return false; + }) + // Custom lower scalar memory access, up to 8 bytes, for: + // - non-power-of-2 MemSizes + // - unaligned 2 or 8 byte MemSizes for MIPS32r5 and older + .customIf([=, &ST](const LegalityQuery &Query) { + if (!Query.Types[0].isScalar() || Query.Types[1] != p0 || + Query.Types[0] == s1) + return false; + + unsigned Size = Query.Types[0].getSizeInBits(); + unsigned QueryMemSize = Query.MMODescrs[0].SizeInBits; + assert(QueryMemSize <= Size && "Scalar can't hold MemSize"); + + if (Size > 64 || QueryMemSize > 64) + return false; + + if (!isPowerOf2_64(Query.MMODescrs[0].SizeInBits)) return true; - if (ST.hasMSA() && - CheckTy0Ty1MemSizeAlign(Query, {{v16s8, p0, 128, false}, - {v8s16, p0, 128, false}, - {v4s32, p0, 128, false}, - {v2s64, p0, 128, false}})) + + if (!ST.systemSupportsUnalignedAccess() && + isUnalignedMemmoryAccess(QueryMemSize, + Query.MMODescrs[0].AlignInBits)) { + assert(QueryMemSize != 32 && "4 byte load and store are legal"); return true; + } + return false; }) .minScalar(0, s32); @@ -111,7 +162,7 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) { {s32, p0, 16, 8}}) .clampScalar(0, s32, s32); - getActionDefinitionsBuilder({G_ZEXT, G_SEXT}) + getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT}) .legalIf([](const LegalityQuery &Query) { return false; }) .maxScalar(0, s32); @@ -202,6 +253,25 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) { .lowerFor({s32}) .maxScalar(0, s32); + getActionDefinitionsBuilder(G_CTLZ) + .legalFor({{s32, s32}}) + .maxScalar(0, s32) + .maxScalar(1, s32); + getActionDefinitionsBuilder(G_CTLZ_ZERO_UNDEF) + .lowerFor({{s32, s32}}); + + getActionDefinitionsBuilder(G_CTTZ) + .lowerFor({{s32, s32}}) + .maxScalar(0, s32) + .maxScalar(1, s32); + getActionDefinitionsBuilder(G_CTTZ_ZERO_UNDEF) + .lowerFor({{s32, s32}, {s64, s64}}); + + getActionDefinitionsBuilder(G_CTPOP) + .lowerFor({{s32, s32}}) + .clampScalar(0, s32, s32) + .clampScalar(1, s32, s32); + // FP instructions getActionDefinitionsBuilder(G_FCONSTANT) .legalFor({s32, s64}); @@ -256,20 +326,98 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) { verify(*ST.getInstrInfo()); } -bool MipsLegalizerInfo::legalizeCustom(MachineInstr &MI, - MachineRegisterInfo &MRI, - MachineIRBuilder &MIRBuilder, - GISelChangeObserver &Observer) const { - +bool MipsLegalizerInfo::legalizeCustom(LegalizerHelper &Helper, + MachineInstr &MI) const { using namespace TargetOpcode; - MIRBuilder.setInstr(MI); - const MipsSubtarget &STI = - static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget()); + MachineIRBuilder &MIRBuilder = Helper.MIRBuilder; + MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); + const LLT s32 = LLT::scalar(32); const LLT s64 = LLT::scalar(64); switch (MI.getOpcode()) { + case G_LOAD: + case G_STORE: { + unsigned MemSize = (**MI.memoperands_begin()).getSize(); + Register Val = MI.getOperand(0).getReg(); + unsigned Size = MRI.getType(Val).getSizeInBits(); + + MachineMemOperand *MMOBase = *MI.memoperands_begin(); + + assert(MemSize <= 8 && "MemSize is too large"); + assert(Size <= 64 && "Scalar size is too large"); + + // Split MemSize into two, P2HalfMemSize is largest power of two smaller + // then MemSize. e.g. 8 = 4 + 4 , 6 = 4 + 2, 3 = 2 + 1. + unsigned P2HalfMemSize, RemMemSize; + if (isPowerOf2_64(MemSize)) { + P2HalfMemSize = RemMemSize = MemSize / 2; + } else { + P2HalfMemSize = 1 << Log2_32(MemSize); + RemMemSize = MemSize - P2HalfMemSize; + } + + Register BaseAddr = MI.getOperand(1).getReg(); + LLT PtrTy = MRI.getType(BaseAddr); + MachineFunction &MF = MIRBuilder.getMF(); + + auto P2HalfMemOp = MF.getMachineMemOperand(MMOBase, 0, P2HalfMemSize); + auto RemMemOp = MF.getMachineMemOperand(MMOBase, P2HalfMemSize, RemMemSize); + + if (MI.getOpcode() == G_STORE) { + // Widen Val to s32 or s64 in order to create legal G_LSHR or G_UNMERGE. + if (Size < 32) + Val = MIRBuilder.buildAnyExt(s32, Val).getReg(0); + if (Size > 32 && Size < 64) + Val = MIRBuilder.buildAnyExt(s64, Val).getReg(0); + + auto C_P2HalfMemSize = MIRBuilder.buildConstant(s32, P2HalfMemSize); + auto Addr = MIRBuilder.buildPtrAdd(PtrTy, BaseAddr, C_P2HalfMemSize); + + if (MI.getOpcode() == G_STORE && MemSize <= 4) { + MIRBuilder.buildStore(Val, BaseAddr, *P2HalfMemOp); + auto C_P2Half_InBits = MIRBuilder.buildConstant(s32, P2HalfMemSize * 8); + auto Shift = MIRBuilder.buildLShr(s32, Val, C_P2Half_InBits); + MIRBuilder.buildStore(Shift, Addr, *RemMemOp); + } else { + auto Unmerge = MIRBuilder.buildUnmerge(s32, Val); + MIRBuilder.buildStore(Unmerge.getReg(0), BaseAddr, *P2HalfMemOp); + MIRBuilder.buildStore(Unmerge.getReg(1), Addr, *RemMemOp); + } + } + + if (MI.getOpcode() == G_LOAD) { + + if (MemSize <= 4) { + // This is anyextending load, use 4 byte lwr/lwl. + auto *Load4MMO = MF.getMachineMemOperand(MMOBase, 0, 4); + + if (Size == 32) + MIRBuilder.buildLoad(Val, BaseAddr, *Load4MMO); + else { + auto Load = MIRBuilder.buildLoad(s32, BaseAddr, *Load4MMO); + MIRBuilder.buildTrunc(Val, Load.getReg(0)); + } + + } else { + auto C_P2HalfMemSize = MIRBuilder.buildConstant(s32, P2HalfMemSize); + auto Addr = MIRBuilder.buildPtrAdd(PtrTy, BaseAddr, C_P2HalfMemSize); + + auto Load_P2Half = MIRBuilder.buildLoad(s32, BaseAddr, *P2HalfMemOp); + auto Load_Rem = MIRBuilder.buildLoad(s32, Addr, *RemMemOp); + + if (Size == 64) + MIRBuilder.buildMerge(Val, {Load_P2Half, Load_Rem}); + else { + auto Merge = MIRBuilder.buildMerge(s64, {Load_P2Half, Load_Rem}); + MIRBuilder.buildTrunc(Val, Merge); + } + } + } + MI.eraseFromParent(); + break; + } case G_UITOFP: { Register Dst = MI.getOperand(0).getReg(); Register Src = MI.getOperand(1).getReg(); @@ -288,11 +436,8 @@ bool MipsLegalizerInfo::legalizeCustom(MachineInstr &MI, // Next, subtract 2^52 * 0x1.0000000000000 i.e. 0x10000000000000.0 from it. // Done. Trunc double to float if needed. - MachineInstrBuilder Bitcast = MIRBuilder.buildInstr( - STI.isFP64bit() ? Mips::BuildPairF64_64 : Mips::BuildPairF64, {s64}, - {Src, MIRBuilder.buildConstant(s32, UINT32_C(0x43300000))}); - Bitcast.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(), - *STI.getRegBankInfo()); + auto C_HiMask = MIRBuilder.buildConstant(s32, UINT32_C(0x43300000)); + auto Bitcast = MIRBuilder.buildMerge(s64, {Src, C_HiMask.getReg(0)}); MachineInstrBuilder TwoP52FP = MIRBuilder.buildFConstant( s64, BitsToDouble(UINT64_C(0x4330000000000000))); @@ -352,15 +497,15 @@ static bool MSA2OpIntrinsicToGeneric(MachineInstr &MI, unsigned Opcode, return true; } -bool MipsLegalizerInfo::legalizeIntrinsic(MachineInstr &MI, - MachineRegisterInfo &MRI, - MachineIRBuilder &MIRBuilder) const { +bool MipsLegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper, + MachineInstr &MI) const { + MachineIRBuilder &MIRBuilder = Helper.MIRBuilder; + MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); const MipsSubtarget &ST = static_cast<const MipsSubtarget &>(MI.getMF()->getSubtarget()); const MipsInstrInfo &TII = *ST.getInstrInfo(); const MipsRegisterInfo &TRI = *ST.getRegisterInfo(); const RegisterBankInfo &RBI = *ST.getRegBankInfo(); - MIRBuilder.setInstr(MI); switch (MI.getIntrinsicID()) { case Intrinsic::memcpy: @@ -377,14 +522,14 @@ bool MipsLegalizerInfo::legalizeIntrinsic(MachineInstr &MI, return constrainSelectedInstRegOperands(*Trap, TII, TRI, RBI); } case Intrinsic::vacopy: { - Register Tmp = MRI.createGenericVirtualRegister(LLT::pointer(0, 32)); MachinePointerInfo MPO; - MIRBuilder.buildLoad(Tmp, MI.getOperand(2), - *MI.getMF()->getMachineMemOperand( - MPO, MachineMemOperand::MOLoad, 4, 4)); + auto Tmp = + MIRBuilder.buildLoad(LLT::pointer(0, 32), MI.getOperand(2), + *MI.getMF()->getMachineMemOperand( + MPO, MachineMemOperand::MOLoad, 4, Align(4))); MIRBuilder.buildStore(Tmp, MI.getOperand(1), *MI.getMF()->getMachineMemOperand( - MPO, MachineMemOperand::MOStore, 4, 4)); + MPO, MachineMemOperand::MOStore, 4, Align(4))); MI.eraseFromParent(); return true; } diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsLegalizerInfo.h b/contrib/llvm-project/llvm/lib/Target/Mips/MipsLegalizerInfo.h index 9696c262b2db..05027b718a85 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsLegalizerInfo.h +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsLegalizerInfo.h @@ -25,12 +25,10 @@ class MipsLegalizerInfo : public LegalizerInfo { public: MipsLegalizerInfo(const MipsSubtarget &ST); - bool legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI, - MachineIRBuilder &MIRBuilder, - GISelChangeObserver &Observer) const override; + bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI) const override; - bool legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI, - MachineIRBuilder &MIRBuilder) const override; + bool legalizeIntrinsic(LegalizerHelper &Helper, + MachineInstr &MI) const override; }; } // end namespace llvm #endif diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsMSAInstrInfo.td b/contrib/llvm-project/llvm/lib/Target/Mips/MipsMSAInstrInfo.td index 0fef518c240e..3e32574596ca 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsMSAInstrInfo.td +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsMSAInstrInfo.td @@ -2339,6 +2339,16 @@ class LDI_H_DESC : MSA_I10_LDI_DESC_BASE<"ldi.h", MSA128HOpnd>; class LDI_W_DESC : MSA_I10_LDI_DESC_BASE<"ldi.w", MSA128WOpnd>; class LDI_D_DESC : MSA_I10_LDI_DESC_BASE<"ldi.d", MSA128DOpnd>; +class MSA_LOAD_PSEUDO_BASE<SDPatternOperator intrinsic, RegisterOperand RO> : + PseudoSE<(outs RO:$dst), (ins PtrRC:$ptr, GPR32:$imm), + [(set RO:$dst, (intrinsic iPTR:$ptr, GPR32:$imm))]> { + let hasNoSchedulingInfo = 1; + let usesCustomInserter = 1; +} + +def LDR_D : MSA_LOAD_PSEUDO_BASE<int_mips_ldr_d, MSA128DOpnd>; +def LDR_W : MSA_LOAD_PSEUDO_BASE<int_mips_ldr_w, MSA128WOpnd>; + class LSA_DESC_BASE<string instr_asm, RegisterOperand RORD, InstrItinClass itin = NoItinerary> { dag OutOperandList = (outs RORD:$rd); @@ -2671,6 +2681,16 @@ class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128WOpnd, class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128DOpnd, mem_simm10_lsl3, addrimm10lsl3>; +class MSA_STORE_PSEUDO_BASE<SDPatternOperator intrinsic, RegisterOperand RO> : + PseudoSE<(outs), (ins RO:$dst, PtrRC:$ptr, GPR32:$imm), + [(intrinsic RO:$dst, iPTR:$ptr, GPR32:$imm)]> { + let hasNoSchedulingInfo = 1; + let usesCustomInserter = 1; +} + +def STR_D : MSA_STORE_PSEUDO_BASE<int_mips_str_d, MSA128DOpnd>; +def STR_W : MSA_STORE_PSEUDO_BASE<int_mips_str_w, MSA128WOpnd>; + class SUBS_S_B_DESC : MSA_3R_DESC_BASE<"subs_s.b", int_mips_subs_s_b, MSA128BOpnd>; class SUBS_S_H_DESC : MSA_3R_DESC_BASE<"subs_s.h", int_mips_subs_s_h, diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsMachineFunction.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/MipsMachineFunction.cpp index 85b20fc58231..a7a2be30f58a 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsMachineFunction.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsMachineFunction.cpp @@ -44,22 +44,22 @@ static const TargetRegisterClass &getGlobalBaseRegClass(MachineFunction &MF) { return Mips::GPR32RegClass; } -Register MipsFunctionInfo::getGlobalBaseReg() { +Register MipsFunctionInfo::getGlobalBaseReg(MachineFunction &MF) { if (!GlobalBaseReg) GlobalBaseReg = MF.getRegInfo().createVirtualRegister(&getGlobalBaseRegClass(MF)); return GlobalBaseReg; } -Register MipsFunctionInfo::getGlobalBaseRegForGlobalISel() { +Register MipsFunctionInfo::getGlobalBaseRegForGlobalISel(MachineFunction &MF) { if (!GlobalBaseReg) { - getGlobalBaseReg(); - initGlobalBaseReg(); + getGlobalBaseReg(MF); + initGlobalBaseReg(MF); } return GlobalBaseReg; } -void MipsFunctionInfo::initGlobalBaseReg() { +void MipsFunctionInfo::initGlobalBaseReg(MachineFunction &MF) { if (!GlobalBaseReg) return; @@ -68,14 +68,13 @@ void MipsFunctionInfo::initGlobalBaseReg() { MachineRegisterInfo &RegInfo = MF.getRegInfo(); const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); DebugLoc DL; - unsigned V0, V1; const TargetRegisterClass *RC; const MipsABIInfo &ABI = static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI(); RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; - V0 = RegInfo.createVirtualRegister(RC); - V1 = RegInfo.createVirtualRegister(RC); + Register V0 = RegInfo.createVirtualRegister(RC); + Register V1 = RegInfo.createVirtualRegister(RC); if (ABI.IsN64()) { MF.getRegInfo().addLiveIn(Mips::T9_64); @@ -147,7 +146,7 @@ void MipsFunctionInfo::initGlobalBaseReg() { .addReg(Mips::V0).addReg(Mips::T9); } -void MipsFunctionInfo::createEhDataRegsFI() { +void MipsFunctionInfo::createEhDataRegsFI(MachineFunction &MF) { const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); for (int I = 0; I < 4; ++I) { const TargetRegisterClass &RC = @@ -155,12 +154,12 @@ void MipsFunctionInfo::createEhDataRegsFI() { ? Mips::GPR64RegClass : Mips::GPR32RegClass; - EhDataRegFI[I] = MF.getFrameInfo().CreateStackObject(TRI.getSpillSize(RC), - TRI.getSpillAlignment(RC), false); + EhDataRegFI[I] = MF.getFrameInfo().CreateStackObject( + TRI.getSpillSize(RC), TRI.getSpillAlign(RC), false); } } -void MipsFunctionInfo::createISRRegFI() { +void MipsFunctionInfo::createISRRegFI(MachineFunction &MF) { // ISRs require spill slots for Status & ErrorPC Coprocessor 0 registers. // The current implementation only supports Mips32r2+ not Mips64rX. Status // is always 32 bits, ErrorPC is 32 or 64 bits dependent on architecture, @@ -170,7 +169,7 @@ void MipsFunctionInfo::createISRRegFI() { for (int I = 0; I < 2; ++I) ISRDataRegFI[I] = MF.getFrameInfo().CreateStackObject( - TRI.getSpillSize(RC), TRI.getSpillAlignment(RC), false); + TRI.getSpillSize(RC), TRI.getSpillAlign(RC), false); } bool MipsFunctionInfo::isEhDataRegFI(int FI) const { @@ -181,19 +180,22 @@ bool MipsFunctionInfo::isEhDataRegFI(int FI) const { bool MipsFunctionInfo::isISRRegFI(int FI) const { return IsISR && (FI == ISRDataRegFI[0] || FI == ISRDataRegFI[1]); } -MachinePointerInfo MipsFunctionInfo::callPtrInfo(const char *ES) { +MachinePointerInfo MipsFunctionInfo::callPtrInfo(MachineFunction &MF, + const char *ES) { return MachinePointerInfo(MF.getPSVManager().getExternalSymbolCallEntry(ES)); } -MachinePointerInfo MipsFunctionInfo::callPtrInfo(const GlobalValue *GV) { +MachinePointerInfo MipsFunctionInfo::callPtrInfo(MachineFunction &MF, + const GlobalValue *GV) { return MachinePointerInfo(MF.getPSVManager().getGlobalValueCallEntry(GV)); } -int MipsFunctionInfo::getMoveF64ViaSpillFI(const TargetRegisterClass *RC) { +int MipsFunctionInfo::getMoveF64ViaSpillFI(MachineFunction &MF, + const TargetRegisterClass *RC) { const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); if (MoveF64ViaSpillFI == -1) { MoveF64ViaSpillFI = MF.getFrameInfo().CreateStackObject( - TRI.getSpillSize(*RC), TRI.getSpillAlignment(*RC), false); + TRI.getSpillSize(*RC), TRI.getSpillAlign(*RC), false); } return MoveF64ViaSpillFI; } diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsMachineFunction.h b/contrib/llvm-project/llvm/lib/Target/Mips/MipsMachineFunction.h index aaa1e0e18441..786d210e2aaa 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsMachineFunction.h +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsMachineFunction.h @@ -24,7 +24,7 @@ namespace llvm { /// Mips target-specific information for each MachineFunction. class MipsFunctionInfo : public MachineFunctionInfo { public: - MipsFunctionInfo(MachineFunction &MF) : MF(MF) {} + MipsFunctionInfo(MachineFunction &MF) {} ~MipsFunctionInfo() override; @@ -32,12 +32,12 @@ public: void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } bool globalBaseRegSet() const; - Register getGlobalBaseReg(); - Register getGlobalBaseRegForGlobalISel(); + Register getGlobalBaseReg(MachineFunction &MF); + Register getGlobalBaseRegForGlobalISel(MachineFunction &MF); // Insert instructions to initialize the global base register in the // first MBB of the function. - void initGlobalBaseReg(); + void initGlobalBaseReg(MachineFunction &MF); int getVarArgsFrameIndex() const { return VarArgsFrameIndex; } void setVarArgsFrameIndex(int Index) { VarArgsFrameIndex = Index; } @@ -53,30 +53,30 @@ public: bool callsEhReturn() const { return CallsEhReturn; } void setCallsEhReturn() { CallsEhReturn = true; } - void createEhDataRegsFI(); + void createEhDataRegsFI(MachineFunction &MF); int getEhDataRegFI(unsigned Reg) const { return EhDataRegFI[Reg]; } bool isEhDataRegFI(int FI) const; /// Create a MachinePointerInfo that has an ExternalSymbolPseudoSourceValue /// object representing a GOT entry for an external function. - MachinePointerInfo callPtrInfo(const char *ES); + MachinePointerInfo callPtrInfo(MachineFunction &MF, const char *ES); // Functions with the "interrupt" attribute require special prologues, // epilogues and additional spill slots. bool isISR() const { return IsISR; } void setISR() { IsISR = true; } - void createISRRegFI(); - int getISRRegFI(unsigned Reg) const { return ISRDataRegFI[Reg]; } + void createISRRegFI(MachineFunction &MF); + int getISRRegFI(Register Reg) const { return ISRDataRegFI[Reg]; } bool isISRRegFI(int FI) const; /// Create a MachinePointerInfo that has a GlobalValuePseudoSourceValue object /// representing a GOT entry for a global function. - MachinePointerInfo callPtrInfo(const GlobalValue *GV); + MachinePointerInfo callPtrInfo(MachineFunction &MF, const GlobalValue *GV); void setSaveS2() { SaveS2 = true; } bool hasSaveS2() const { return SaveS2; } - int getMoveF64ViaSpillFI(const TargetRegisterClass *RC); + int getMoveF64ViaSpillFI(MachineFunction &MF, const TargetRegisterClass *RC); std::map<const char *, const Mips16HardFloatInfo::FuncSignature *> StubsNeeded; @@ -84,17 +84,15 @@ public: private: virtual void anchor(); - MachineFunction& MF; - /// SRetReturnReg - Some subtargets require that sret lowering includes /// returning the value of the returned struct in a register. This field /// holds the virtual register into which the sret argument is passed. - unsigned SRetReturnReg = 0; + Register SRetReturnReg; /// GlobalBaseReg - keeps track of the virtual register initialized for /// use as the global base register. This is used for PIC in some PIC /// relocation models. - unsigned GlobalBaseReg = 0; + Register GlobalBaseReg; /// VarArgsFrameIndex - FrameIndex for start of varargs area. int VarArgsFrameIndex = 0; diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp index 8bd64ff6cb27..2823d300dc6e 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp @@ -218,8 +218,7 @@ bool OptimizePICCall::runOnMachineFunction(MachineFunction &F) { MBBI.preVisit(ScopedHT); Changed |= visitNode(MBBI); const MachineDomTreeNode *Node = MBBI.getNode(); - const std::vector<MachineDomTreeNode *> &Children = Node->getChildren(); - WorkList.append(Children.begin(), Children.end()); + WorkList.append(Node->begin(), Node->end()); } return Changed; diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsPreLegalizerCombiner.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/MipsPreLegalizerCombiner.cpp index f9d93ca29658..310e54b0ea8d 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsPreLegalizerCombiner.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsPreLegalizerCombiner.cpp @@ -44,9 +44,22 @@ bool MipsPreLegalizerCombinerInfo::combine(GISelChangeObserver &Observer, return false; case TargetOpcode::G_LOAD: case TargetOpcode::G_SEXTLOAD: - case TargetOpcode::G_ZEXTLOAD: + case TargetOpcode::G_ZEXTLOAD: { + // Don't attempt to combine non power of 2 loads or unaligned loads when + // subtarget doesn't support them. + auto MMO = *MI.memoperands_begin(); + const MipsSubtarget &STI = + static_cast<const MipsSubtarget &>(MI.getMF()->getSubtarget()); + if (!isPowerOf2_64(MMO->getSize())) + return false; + bool isUnaligned = MMO->getAlign() < MMO->getSize(); + if (!STI.systemSupportsUnalignedAccess() && isUnaligned) + return false; + return Helper.tryCombineExtendingLoads(MI); } + } + return false; } diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp index 2a3f5a05dfe0..6325e513f9f8 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp @@ -132,9 +132,6 @@ static bool isFloatingPointOpcodeUse(unsigned Opc) { case TargetOpcode::G_FPTOSI: case TargetOpcode::G_FPTOUI: case TargetOpcode::G_FCMP: - case Mips::MFC1: - case Mips::ExtractElementF64: - case Mips::ExtractElementF64_64: return true; default: return isFloatingPointOpcode(Opc); @@ -147,15 +144,25 @@ static bool isFloatingPointOpcodeDef(unsigned Opc) { switch (Opc) { case TargetOpcode::G_SITOFP: case TargetOpcode::G_UITOFP: - case Mips::MTC1: - case Mips::BuildPairF64: - case Mips::BuildPairF64_64: return true; default: return isFloatingPointOpcode(Opc); } } +static bool isGprbTwoInstrUnalignedLoadOrStore(const MachineInstr *MI) { + if (MI->getOpcode() == TargetOpcode::G_LOAD || + MI->getOpcode() == TargetOpcode::G_STORE) { + auto MMO = *MI->memoperands_begin(); + const MipsSubtarget &STI = + static_cast<const MipsSubtarget &>(MI->getMF()->getSubtarget()); + if (MMO->getSize() == 4 && (!STI.systemSupportsUnalignedAccess() && + MMO->getAlign() < MMO->getSize())) + return true; + } + return false; +} + static bool isAmbiguous(unsigned Opc) { switch (Opc) { case TargetOpcode::G_LOAD: @@ -163,6 +170,8 @@ static bool isAmbiguous(unsigned Opc) { case TargetOpcode::G_PHI: case TargetOpcode::G_SELECT: case TargetOpcode::G_IMPLICIT_DEF: + case TargetOpcode::G_UNMERGE_VALUES: + case TargetOpcode::G_MERGE_VALUES: return true; default: return false; @@ -247,10 +256,17 @@ MipsRegisterBankInfo::AmbiguousRegDefUseContainer::AmbiguousRegDefUseContainer( if (MI->getOpcode() == TargetOpcode::G_IMPLICIT_DEF) addDefUses(MI->getOperand(0).getReg(), MRI); + + if (MI->getOpcode() == TargetOpcode::G_UNMERGE_VALUES) + addUseDef(MI->getOperand(MI->getNumOperands() - 1).getReg(), MRI); + + if (MI->getOpcode() == TargetOpcode::G_MERGE_VALUES) + addDefUses(MI->getOperand(0).getReg(), MRI); } bool MipsRegisterBankInfo::TypeInfoForMF::visit( - const MachineInstr *MI, const MachineInstr *WaitingForTypeOfMI) { + const MachineInstr *MI, const MachineInstr *WaitingForTypeOfMI, + InstType &AmbiguousTy) { assert(isAmbiguous(MI->getOpcode()) && "Visiting non-Ambiguous opcode.\n"); if (wasVisited(MI)) return true; // InstType has already been determined for MI. @@ -258,18 +274,28 @@ bool MipsRegisterBankInfo::TypeInfoForMF::visit( startVisit(MI); AmbiguousRegDefUseContainer DefUseContainer(MI); + if (isGprbTwoInstrUnalignedLoadOrStore(MI)) { + setTypes(MI, Integer); + return true; + } + + if (AmbiguousTy == InstType::Ambiguous && + (MI->getOpcode() == TargetOpcode::G_MERGE_VALUES || + MI->getOpcode() == TargetOpcode::G_UNMERGE_VALUES)) + AmbiguousTy = InstType::AmbiguousWithMergeOrUnmerge; + // Visit instructions where MI's DEF operands are USED. - if (visitAdjacentInstrs(MI, DefUseContainer.getDefUses(), true)) + if (visitAdjacentInstrs(MI, DefUseContainer.getDefUses(), true, AmbiguousTy)) return true; // Visit instructions that DEFINE MI's USE operands. - if (visitAdjacentInstrs(MI, DefUseContainer.getUseDefs(), false)) + if (visitAdjacentInstrs(MI, DefUseContainer.getUseDefs(), false, AmbiguousTy)) return true; // All MI's adjacent instructions, are ambiguous. if (!WaitingForTypeOfMI) { // This is chain of ambiguous instructions. - setTypes(MI, InstType::Ambiguous); + setTypes(MI, AmbiguousTy); return true; } // Excluding WaitingForTypeOfMI, MI is either connected to chains of ambiguous @@ -286,7 +312,7 @@ bool MipsRegisterBankInfo::TypeInfoForMF::visit( bool MipsRegisterBankInfo::TypeInfoForMF::visitAdjacentInstrs( const MachineInstr *MI, SmallVectorImpl<MachineInstr *> &AdjacentInstrs, - bool isDefUse) { + bool isDefUse, InstType &AmbiguousTy) { while (!AdjacentInstrs.empty()) { MachineInstr *AdjMI = AdjacentInstrs.pop_back_val(); @@ -303,9 +329,11 @@ bool MipsRegisterBankInfo::TypeInfoForMF::visitAdjacentInstrs( return true; } - // Defaults to integer instruction. Includes G_MERGE_VALUES and - // G_UNMERGE_VALUES. - if (!isAmbiguous(AdjMI->getOpcode())) { + // Defaults to integer instruction. Small registers in G_MERGE (uses) and + // G_UNMERGE (defs) will always be gprb. + if ((!isDefUse && AdjMI->getOpcode() == TargetOpcode::G_UNMERGE_VALUES) || + (isDefUse && AdjMI->getOpcode() == TargetOpcode::G_MERGE_VALUES) || + !isAmbiguous(AdjMI->getOpcode())) { setTypes(MI, InstType::Integer); return true; } @@ -314,7 +342,7 @@ bool MipsRegisterBankInfo::TypeInfoForMF::visitAdjacentInstrs( // adjacent instructions and determine InstType without visiting AdjMI. if (!wasVisited(AdjMI) || getRecordedTypeForInstr(AdjMI) != InstType::NotDetermined) { - if (visit(AdjMI, MI)) { + if (visit(AdjMI, MI, AmbiguousTy)) { // InstType is successfully determined and is same as for AdjMI. setTypes(MI, getRecordedTypeForInstr(AdjMI)); return true; @@ -355,14 +383,15 @@ void MipsRegisterBankInfo::TypeInfoForMF::setTypesAccordingToPhysicalRegister( MipsRegisterBankInfo::InstType MipsRegisterBankInfo::TypeInfoForMF::determineInstType(const MachineInstr *MI) { - visit(MI, nullptr); + InstType DefaultAmbiguousType = InstType::Ambiguous; + visit(MI, nullptr, DefaultAmbiguousType); return getRecordedTypeForInstr(MI); } void MipsRegisterBankInfo::TypeInfoForMF::cleanupIfNewFunction( llvm::StringRef FunctionName) { if (MFName != FunctionName) { - MFName = FunctionName; + MFName = std::string(FunctionName); WaitingQueues.clear(); Types.clear(); } @@ -453,6 +482,7 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { case G_BRINDIRECT: case G_VASTART: case G_BSWAP: + case G_CTLZ: OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx]; break; case G_ADD: @@ -467,7 +497,7 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { OperandsMapping = getMSAMapping(MF); break; case G_STORE: - case G_LOAD: + case G_LOAD: { if (Op0Size == 128) { OperandsMapping = getOperandsMapping( {getMSAMapping(MF), &Mips::ValueMappings[Mips::GPRIdx]}); @@ -477,41 +507,56 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { if (!Op0Ty.isPointer()) InstTy = TI.determineInstType(&MI); - if (InstTy == InstType::FloatingPoint || - (Op0Size == 64 && InstTy == InstType::Ambiguous)) + if (isFloatingPoint_32or64(InstTy, Op0Size) || + isAmbiguous_64(InstTy, Op0Size)) { OperandsMapping = getOperandsMapping( {getFprbMapping(Op0Size), &Mips::ValueMappings[Mips::GPRIdx]}); - else + } else { + assert((isInteger_32(InstTy, Op0Size) || + isAmbiguous_32(InstTy, Op0Size) || + isAmbiguousWithMergeOrUnmerge_64(InstTy, Op0Size)) && + "Unexpected Inst type"); OperandsMapping = getOperandsMapping({getGprbOrCustomMapping(Op0Size, MappingID), &Mips::ValueMappings[Mips::GPRIdx]}); + } break; - case G_PHI: + } + case G_PHI: { if (!Op0Ty.isPointer()) InstTy = TI.determineInstType(&MI); // PHI is copylike and should have one regbank in mapping for def register. - if (InstTy == InstType::Integer && Op0Size == 64) { + if (isAmbiguousWithMergeOrUnmerge_64(InstTy, Op0Size)) { OperandsMapping = getOperandsMapping({&Mips::ValueMappings[Mips::DPRIdx]}); + TI.clearTypeInfoData(&MI); return getInstructionMapping(CustomMappingID, /*Cost=*/1, OperandsMapping, /*NumOperands=*/1); } + assert((isInteger_32(InstTy, Op0Size) || + isFloatingPoint_32or64(InstTy, Op0Size) || + isAmbiguous_32or64(InstTy, Op0Size)) && + "Unexpected Inst type"); // Use default handling for PHI, i.e. set reg bank of def operand to match // register banks of use operands. return getInstrMappingImpl(MI); + } case G_SELECT: { if (!Op0Ty.isPointer()) InstTy = TI.determineInstType(&MI); - - if (InstTy == InstType::FloatingPoint || - (Op0Size == 64 && InstTy == InstType::Ambiguous)) { + if (isFloatingPoint_32or64(InstTy, Op0Size) || + isAmbiguous_64(InstTy, Op0Size)) { const RegisterBankInfo::ValueMapping *Bank = getFprbMapping(Op0Size); OperandsMapping = getOperandsMapping( {Bank, &Mips::ValueMappings[Mips::GPRIdx], Bank, Bank}); break; } else { + assert((isInteger_32(InstTy, Op0Size) || + isAmbiguous_32(InstTy, Op0Size) || + isAmbiguousWithMergeOrUnmerge_64(InstTy, Op0Size)) && + "Unexpected Inst type"); const RegisterBankInfo::ValueMapping *Bank = getGprbOrCustomMapping(Op0Size, MappingID); OperandsMapping = getOperandsMapping( @@ -519,28 +564,45 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { } break; } - case G_IMPLICIT_DEF: + case G_IMPLICIT_DEF: { if (!Op0Ty.isPointer()) InstTy = TI.determineInstType(&MI); - if (InstTy == InstType::FloatingPoint) + if (isFloatingPoint_32or64(InstTy, Op0Size)) OperandsMapping = getFprbMapping(Op0Size); - else + else { + assert((isInteger_32(InstTy, Op0Size) || + isAmbiguousWithMergeOrUnmerge_64(InstTy, Op0Size)) && + "Unexpected Inst type"); OperandsMapping = getGprbOrCustomMapping(Op0Size, MappingID); - - break; - case G_UNMERGE_VALUES: + } + } break; + case G_UNMERGE_VALUES: { + assert(MI.getNumOperands() == 3 && "Unsupported G_UNMERGE_VALUES"); + unsigned Op3Size = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits(); + InstTy = TI.determineInstType(&MI); + assert((isAmbiguousWithMergeOrUnmerge_64(InstTy, Op3Size) || + isFloatingPoint_64(InstTy, Op3Size)) && + "Unexpected Inst type"); OperandsMapping = getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], &Mips::ValueMappings[Mips::GPRIdx], &Mips::ValueMappings[Mips::DPRIdx]}); - MappingID = CustomMappingID; + if (isAmbiguousWithMergeOrUnmerge_64(InstTy, Op3Size)) + MappingID = CustomMappingID; break; - case G_MERGE_VALUES: + } + case G_MERGE_VALUES: { + InstTy = TI.determineInstType(&MI); + assert((isAmbiguousWithMergeOrUnmerge_64(InstTy, Op0Size) || + isFloatingPoint_64(InstTy, Op0Size)) && + "Unexpected Inst type"); OperandsMapping = getOperandsMapping({&Mips::ValueMappings[Mips::DPRIdx], &Mips::ValueMappings[Mips::GPRIdx], &Mips::ValueMappings[Mips::GPRIdx]}); - MappingID = CustomMappingID; + if (isAmbiguousWithMergeOrUnmerge_64(InstTy, Op0Size)) + MappingID = CustomMappingID; break; + } case G_FADD: case G_FSUB: case G_FMUL: @@ -605,6 +667,8 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { return getInvalidInstructionMapping(); } + if (MappingID == CustomMappingID) + TI.clearTypeInfoData(&MI); return getInstructionMapping(MappingID, /*Cost=*/1, OperandsMapping, NumOperands); } @@ -652,10 +716,10 @@ void MipsRegisterBankInfo::setRegBank(MachineInstr &MI, static void combineAwayG_UNMERGE_VALUES(LegalizationArtifactCombiner &ArtCombiner, - MachineInstr &MI) { + MachineInstr &MI, GISelObserverWrapper &Observer) { SmallVector<Register, 4> UpdatedDefs; SmallVector<MachineInstr *, 2> DeadInstrs; - ArtCombiner.tryCombineMerges(MI, DeadInstrs, UpdatedDefs); + ArtCombiner.tryCombineMerges(MI, DeadInstrs, UpdatedDefs, Observer); for (MachineInstr *DeadMI : DeadInstrs) DeadMI->eraseFromParent(); } @@ -688,7 +752,7 @@ void MipsRegisterBankInfo::applyMappingImpl( // not be considered for regbank selection. RegBankSelect for mips // visits/makes corresponding G_MERGE first. Combine them here. if (NewMI->getOpcode() == TargetOpcode::G_UNMERGE_VALUES) - combineAwayG_UNMERGE_VALUES(ArtCombiner, *NewMI); + combineAwayG_UNMERGE_VALUES(ArtCombiner, *NewMI, WrapperObserver); // This G_MERGE will be combined away when its corresponding G_UNMERGE // gets regBankSelected. else if (NewMI->getOpcode() == TargetOpcode::G_MERGE_VALUES) @@ -700,7 +764,7 @@ void MipsRegisterBankInfo::applyMappingImpl( return; } case TargetOpcode::G_UNMERGE_VALUES: - combineAwayG_UNMERGE_VALUES(ArtCombiner, MI); + combineAwayG_UNMERGE_VALUES(ArtCombiner, MI, WrapperObserver); return; default: break; diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsRegisterBankInfo.h b/contrib/llvm-project/llvm/lib/Target/Mips/MipsRegisterBankInfo.h index 66267f8d794d..55eeaf096b14 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsRegisterBankInfo.h +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsRegisterBankInfo.h @@ -66,9 +66,55 @@ private: /// Represents moving 'bags of bits' around. Select same bank for entire /// chain to avoid cross bank copies. Currently we select fprb for s64 and /// gprb for s32 Ambiguous operands. - Ambiguous + Ambiguous, + /// Only used for s64. Unlike Ambiguous s64, AmbiguousWithMergeOrUnmerge s64 + /// is mapped to gprb (legalized using narrow scalar to s32). + AmbiguousWithMergeOrUnmerge }; + bool isAmbiguous_64(InstType InstTy, unsigned OpSize) const { + if (InstTy == InstType::Ambiguous && OpSize == 64) + return true; + return false; + } + + bool isAmbiguous_32(InstType InstTy, unsigned OpSize) const { + if (InstTy == InstType::Ambiguous && OpSize == 32) + return true; + return false; + } + + bool isAmbiguous_32or64(InstType InstTy, unsigned OpSize) const { + if (InstTy == InstType::Ambiguous && (OpSize == 32 || OpSize == 64)) + return true; + return false; + } + + bool isAmbiguousWithMergeOrUnmerge_64(InstType InstTy, + unsigned OpSize) const { + if (InstTy == InstType::AmbiguousWithMergeOrUnmerge && OpSize == 64) + return true; + return false; + } + + bool isFloatingPoint_32or64(InstType InstTy, unsigned OpSize) const { + if (InstTy == InstType::FloatingPoint && (OpSize == 32 || OpSize == 64)) + return true; + return false; + } + + bool isFloatingPoint_64(InstType InstTy, unsigned OpSize) const { + if (InstTy == InstType::FloatingPoint && OpSize == 64) + return true; + return false; + } + + bool isInteger_32(InstType InstTy, unsigned OpSize) const { + if (InstTy == InstType::Integer && OpSize == 32) + return true; + return false; + } + /// Some generic instructions have operands that can be mapped to either fprb /// or gprb e.g. for G_LOAD we consider only operand 0 as ambiguous, operand 1 /// is always gprb since it is a pointer. @@ -113,12 +159,13 @@ private: DenseMap<const MachineInstr *, InstType> Types; /// Recursively visit MI's adjacent instructions and find MI's InstType. - bool visit(const MachineInstr *MI, const MachineInstr *WaitingForTypeOfMI); + bool visit(const MachineInstr *MI, const MachineInstr *WaitingForTypeOfMI, + InstType &AmbiguousTy); /// Visit MI's adjacent UseDefs or DefUses. bool visitAdjacentInstrs(const MachineInstr *MI, SmallVectorImpl<MachineInstr *> &AdjacentInstrs, - bool isDefUse); + bool isDefUse, InstType &AmbiguousTy); /// Set type for MI, and recursively for all instructions that are /// waiting for MI's type. @@ -170,6 +217,13 @@ private: InstType determineInstType(const MachineInstr *MI); void cleanupIfNewFunction(llvm::StringRef FunctionName); + + /// MI is about to get destroyed (using narrow scalar). Internal data is + /// saved based on MI's address, clear it since it is no longer valid. + void clearTypeInfoData(const MachineInstr *MI) { + Types.erase(MI); + WaitingQueues.erase(MI); + }; }; }; } // end namespace llvm diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsRegisterInfo.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/MipsRegisterInfo.cpp index 7b02d126eb28..3452bf495a34 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsRegisterInfo.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsRegisterInfo.cpp @@ -245,11 +245,6 @@ MipsRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const { return true; } -bool -MipsRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const { - return true; -} - // FrameIndex represent objects inside a abstract stack. // We must replace FrameIndex with an stack/frame pointer // direct reference. @@ -271,7 +266,7 @@ eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, << "spOffset : " << spOffset << "\n" << "stackSize : " << stackSize << "\n" << "alignment : " - << MF.getFrameInfo().getObjectAlignment(FrameIndex) + << DebugStr(MF.getFrameInfo().getObjectAlign(FrameIndex)) << "\n"); eliminateFI(MI, FIOperandNum, FrameIndex, stackSize, spOffset); diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsRegisterInfo.h b/contrib/llvm-project/llvm/lib/Target/Mips/MipsRegisterInfo.h index 4ed32b09718b..06f214c2d6b1 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsRegisterInfo.h +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsRegisterInfo.h @@ -58,8 +58,6 @@ public: bool requiresRegisterScavenging(const MachineFunction &MF) const override; - bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override; - /// Stack Frame Processing Methods void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsRegisterInfo.td b/contrib/llvm-project/llvm/lib/Target/Mips/MipsRegisterInfo.td index 8a6279da46b7..7d4dcca89e31 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsRegisterInfo.td +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsRegisterInfo.td @@ -194,23 +194,23 @@ let Namespace = "Mips" in { // FP control registers. foreach I = 0-31 in - def FCR#I : MipsReg<#I, ""#I>; + def FCR#I : MipsReg<I, ""#I>; // FP condition code registers. foreach I = 0-7 in - def FCC#I : MipsReg<#I, "fcc"#I>; + def FCC#I : MipsReg<I, "fcc"#I>; // COP0 registers. foreach I = 0-31 in - def COP0#I : MipsReg<#I, ""#I>; + def COP0#I : MipsReg<I, ""#I>; // COP2 registers. foreach I = 0-31 in - def COP2#I : MipsReg<#I, ""#I>; + def COP2#I : MipsReg<I, ""#I>; // COP3 registers. foreach I = 0-31 in - def COP3#I : MipsReg<#I, ""#I>; + def COP3#I : MipsReg<I, ""#I>; // PC register def PC : Register<"pc">; @@ -222,11 +222,11 @@ let Namespace = "Mips" in { def HWR3 : MipsReg<3, "hwr_ccres">; foreach I = 4-31 in - def HWR#I : MipsReg<#I, ""#I>; + def HWR#I : MipsReg<I, ""#I>; // Accum registers foreach I = 0-3 in - def AC#I : ACCReg<#I, "ac"#I, + def AC#I : ACCReg<I, "ac"#I, [!cast<Register>("LO"#I), !cast<Register>("HI"#I)]>; def AC0_64 : ACCReg<0, "ac0", [LO0_64, HI0_64]>; @@ -262,7 +262,7 @@ let Namespace = "Mips" in { // These registers do not exist, but instructions like `cfcmsa` // and `ctcmsa` allows to specify them. foreach I = 8-31 in - def MSA#I : MipsReg<#I, ""#I>; + def MSA#I : MipsReg<I, ""#I>; // Octeon multiplier and product registers def MPL0 : MipsReg<0, "mpl0">; diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp index 166ddea0431f..a657bb44ac78 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp @@ -320,7 +320,7 @@ bool ExpandPseudo::expandBuildPairF64(MachineBasicBlock &MBB, // We re-use the same spill slot each time so that the stack frame doesn't // grow too much in functions with a large number of moves. - int FI = MF.getInfo<MipsFunctionInfo>()->getMoveF64ViaSpillFI(RC2); + int FI = MF.getInfo<MipsFunctionInfo>()->getMoveF64ViaSpillFI(MF, RC2); if (!Subtarget.isLittle()) std::swap(LoReg, HiReg); TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC, @@ -386,7 +386,7 @@ bool ExpandPseudo::expandExtractElementF64(MachineBasicBlock &MBB, // We re-use the same spill slot each time so that the stack frame doesn't // grow too much in functions with a large number of moves. - int FI = MF.getInfo<MipsFunctionInfo>()->getMoveF64ViaSpillFI(RC); + int FI = MF.getInfo<MipsFunctionInfo>()->getMoveF64ViaSpillFI(MF, RC); TII.storeRegToStack(MBB, I, SrcReg, Op1.isKill(), FI, RC, &RegInfo, 0); TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &RegInfo, Offset); return true; @@ -434,8 +434,8 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF, TII.adjustStackPtr(SP, -StackSize, MBB, MBBI); // emit ".cfi_def_cfa_offset StackSize" - unsigned CFIIndex = MF.addFrameInst( - MCCFIInstruction::createDefCfaOffset(nullptr, -StackSize)); + unsigned CFIIndex = + MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, StackSize)); BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex); @@ -539,11 +539,11 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF, // addiu $Reg, $zero, -MaxAlignment // andi $sp, $sp, $Reg Register VR = MF.getRegInfo().createVirtualRegister(RC); - assert(isInt<16>(MFI.getMaxAlignment()) && + assert((Log2(MFI.getMaxAlign()) < 16) && "Function's alignment size requirement is not supported."); - int MaxAlign = -(int)MFI.getMaxAlignment(); + int64_t MaxAlign = -(int64_t)MFI.getMaxAlign().value(); - BuildMI(MBB, MBBI, dl, TII.get(ADDiu), VR).addReg(ZERO) .addImm(MaxAlign); + BuildMI(MBB, MBBI, dl, TII.get(ADDiu), VR).addReg(ZERO).addImm(MaxAlign); BuildMI(MBB, MBBI, dl, TII.get(AND), SP).addReg(SP).addReg(VR); if (hasBP(MF)) { @@ -776,7 +776,7 @@ void MipsSEFrameLowering::emitInterruptEpilogueStub( int MipsSEFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, - unsigned &FrameReg) const { + Register &FrameReg) const { const MachineFrameInfo &MFI = MF.getFrameInfo(); MipsABIInfo ABI = STI.getABI(); @@ -789,11 +789,9 @@ int MipsSEFrameLowering::getFrameIndexReference(const MachineFunction &MF, getOffsetOfLocalArea() + MFI.getOffsetAdjustment(); } -bool MipsSEFrameLowering:: -spillCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector<CalleeSavedInfo> &CSI, - const TargetRegisterInfo *TRI) const { +bool MipsSEFrameLowering::spillCalleeSavedRegisters( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, + ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const { MachineFunction *MF = MBB.getParent(); const TargetInstrInfo &TII = *STI.getInstrInfo(); @@ -880,11 +878,11 @@ void MipsSEFrameLowering::determineCalleeSaves(MachineFunction &MF, // Create spill slots for eh data registers if function calls eh_return. if (MipsFI->callsEhReturn()) - MipsFI->createEhDataRegsFI(); + MipsFI->createEhDataRegsFI(MF); // Create spill slots for Coprocessor 0 registers if function is an ISR. if (MipsFI->isISR()) - MipsFI->createISRRegFI(); + MipsFI->createISRRegFI(MF); // Expand pseudo instructions which load, store or copy accumulators. // Add an emergency spill slot if a pseudo was expanded. @@ -895,8 +893,7 @@ void MipsSEFrameLowering::determineCalleeSaves(MachineFunction &MF, const TargetRegisterClass &RC = STI.isGP64bit() ? Mips::GPR64RegClass : Mips::GPR32RegClass; int FI = MF.getFrameInfo().CreateStackObject(TRI->getSpillSize(RC), - TRI->getSpillAlignment(RC), - false); + TRI->getSpillAlign(RC), false); RS->addScavengingFrameIndex(FI); } @@ -912,8 +909,7 @@ void MipsSEFrameLowering::determineCalleeSaves(MachineFunction &MF, const TargetRegisterClass &RC = ABI.ArePtrs64bit() ? Mips::GPR64RegClass : Mips::GPR32RegClass; int FI = MF.getFrameInfo().CreateStackObject(TRI->getSpillSize(RC), - TRI->getSpillAlignment(RC), - false); + TRI->getSpillAlign(RC), false); RS->addScavengingFrameIndex(FI); } diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsSEFrameLowering.h b/contrib/llvm-project/llvm/lib/Target/Mips/MipsSEFrameLowering.h index 78ffe161d9c6..c818a65f5b14 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsSEFrameLowering.h +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsSEFrameLowering.h @@ -28,11 +28,11 @@ public: void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override; int getFrameIndexReference(const MachineFunction &MF, int FI, - unsigned &FrameReg) const override; + Register &FrameReg) const override; bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, - const std::vector<CalleeSavedInfo> &CSI, + ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const override; bool hasReservedCallFrame(const MachineFunction &MF) const override; diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp index bef1a3657ea5..7be5fc33a0af 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp @@ -153,7 +153,7 @@ void MipsSEDAGToDAGISel::emitMCountABI(MachineInstr &MI, MachineBasicBlock &MBB, } void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) { - MF.getInfo<MipsFunctionInfo>()->initGlobalBaseReg(); + MF.getInfo<MipsFunctionInfo>()->initGlobalBaseReg(MF); MachineRegisterInfo *MRI = &MF.getRegInfo(); @@ -833,7 +833,9 @@ bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) { } case ISD::INTRINSIC_W_CHAIN: { - switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) { + const unsigned IntrinsicOpcode = + cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); + switch (IntrinsicOpcode) { default: break; @@ -845,6 +847,41 @@ bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) { ReplaceNode(Node, Reg.getNode()); return true; } + case Intrinsic::mips_ldr_d: + case Intrinsic::mips_ldr_w: { + unsigned Op = (IntrinsicOpcode == Intrinsic::mips_ldr_d) ? Mips::LDR_D + : Mips::LDR_W; + + SDLoc DL(Node); + assert(Node->getNumOperands() == 4 && "Unexpected number of operands."); + const SDValue &Chain = Node->getOperand(0); + const SDValue &Intrinsic = Node->getOperand(1); + const SDValue &Pointer = Node->getOperand(2); + const SDValue &Constant = Node->getOperand(3); + + assert(Chain.getValueType() == MVT::Other); + (void)Intrinsic; + assert(Intrinsic.getOpcode() == ISD::TargetConstant && + Constant.getOpcode() == ISD::Constant && + "Invalid instruction operand."); + + // Convert Constant to TargetConstant. + const ConstantInt *Val = + cast<ConstantSDNode>(Constant)->getConstantIntValue(); + SDValue Imm = + CurDAG->getTargetConstant(*Val, DL, Constant.getValueType()); + + SmallVector<SDValue, 3> Ops{Pointer, Imm, Chain}; + + assert(Node->getNumValues() == 2); + assert(Node->getValueType(0).is128BitVector()); + assert(Node->getValueType(1) == MVT::Other); + SmallVector<EVT, 2> ResTys{Node->getValueType(0), Node->getValueType(1)}; + + ReplaceNode(Node, CurDAG->getMachineNode(Op, DL, ResTys, Ops)); + + return true; + } } break; } @@ -866,7 +903,9 @@ bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) { } case ISD::INTRINSIC_VOID: { - switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) { + const unsigned IntrinsicOpcode = + cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); + switch (IntrinsicOpcode) { default: break; @@ -879,6 +918,40 @@ bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) { ReplaceNode(Node, ChainOut.getNode()); return true; } + case Intrinsic::mips_str_d: + case Intrinsic::mips_str_w: { + unsigned Op = (IntrinsicOpcode == Intrinsic::mips_str_d) ? Mips::STR_D + : Mips::STR_W; + + SDLoc DL(Node); + assert(Node->getNumOperands() == 5 && "Unexpected number of operands."); + const SDValue &Chain = Node->getOperand(0); + const SDValue &Intrinsic = Node->getOperand(1); + const SDValue &Vec = Node->getOperand(2); + const SDValue &Pointer = Node->getOperand(3); + const SDValue &Constant = Node->getOperand(4); + + assert(Chain.getValueType() == MVT::Other); + (void)Intrinsic; + assert(Intrinsic.getOpcode() == ISD::TargetConstant && + Constant.getOpcode() == ISD::Constant && + "Invalid instruction operand."); + + // Convert Constant to TargetConstant. + const ConstantInt *Val = + cast<ConstantSDNode>(Constant)->getConstantIntValue(); + SDValue Imm = + CurDAG->getTargetConstant(*Val, DL, Constant.getValueType()); + + SmallVector<SDValue, 4> Ops{Vec, Pointer, Imm, Chain}; + + assert(Node->getNumValues() == 1); + assert(Node->getValueType(0) == MVT::Other); + SmallVector<EVT, 1> ResTys{Node->getValueType(0)}; + + ReplaceNode(Node, CurDAG->getMachineNode(Op, DL, ResTys, Ops)); + return true; + } } break; } diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsSEISelLowering.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/MipsSEISelLowering.cpp index 798e8784405f..bdf29c53cbd5 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsSEISelLowering.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsSEISelLowering.cpp @@ -1342,9 +1342,8 @@ static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) { // Scan output. SmallVector<EVT, 2> ResTys; - for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end(); - I != E; ++I) - ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I); + for (EVT Ty : Op->values()) + ResTys.push_back((Ty == MVT::i64) ? MVT::Untyped : Ty); // Create node. SDValue Val = DAG.getNode(Opc, DL, ResTys, Ops); diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp index d4f09a2f3586..901a4fe4e2ac 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp @@ -243,7 +243,7 @@ MipsSEInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const { void MipsSEInstrInfo:: storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, - unsigned SrcReg, bool isKill, int FI, + Register SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const { DebugLoc DL; @@ -317,7 +317,7 @@ storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, void MipsSEInstrInfo:: loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, - unsigned DestReg, int FI, const TargetRegisterClass *RC, + Register DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const { DebugLoc DL; if (I != MBB.end()) DL = I->getDebugLoc(); @@ -483,6 +483,20 @@ bool MipsSEInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { return true; } +/// isBranchWithImm - Return true if the branch contains an immediate +/// operand (\see lib/Target/Mips/MipsBranchExpansion.cpp). +bool MipsSEInstrInfo::isBranchWithImm(unsigned Opc) const { + switch (Opc) { + default: + return false; + case Mips::BBIT0: + case Mips::BBIT1: + case Mips::BBIT032: + case Mips::BBIT132: + return true; + } +} + /// getOppositeBranchOpc - Return the inverse of the specified /// opcode, e.g. turning BEQ to BNE. unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const { diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsSEInstrInfo.h b/contrib/llvm-project/llvm/lib/Target/Mips/MipsSEInstrInfo.h index 08c00ec8ccef..44a6dac2ccbd 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsSEInstrInfo.h +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsSEInstrInfo.h @@ -48,20 +48,22 @@ public: void storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, - unsigned SrcReg, bool isKill, int FrameIndex, + Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const override; void loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, - unsigned DestReg, int FrameIndex, + Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const override; bool expandPostRAPseudo(MachineInstr &MI) const override; + bool isBranchWithImm(unsigned Opc) const override; + unsigned getOppositeBranchOpc(unsigned Opc) const override; /// Adjust SP by Amount bytes. diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsSERegisterInfo.h b/contrib/llvm-project/llvm/lib/Target/Mips/MipsSERegisterInfo.h index 82ddf40f56a7..cc8496e0268b 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsSERegisterInfo.h +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsSERegisterInfo.h @@ -17,7 +17,6 @@ #include "MipsRegisterInfo.h" namespace llvm { -class MipsSEInstrInfo; class MipsSERegisterInfo : public MipsRegisterInfo { public: diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsSchedule.td b/contrib/llvm-project/llvm/lib/Target/Mips/MipsSchedule.td index 0c0ddeab22c4..568c85af655d 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsSchedule.td +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsSchedule.td @@ -27,6 +27,7 @@ def II_ADD : InstrItinClass; def II_ADDU : InstrItinClass; def II_ADD_D : InstrItinClass; def II_ADD_S : InstrItinClass; +def II_ADDR_PS : InstrItinClass; def II_ALIGN : InstrItinClass; def II_AND : InstrItinClass; def II_ANDI : InstrItinClass; @@ -278,6 +279,7 @@ def II_MUL : InstrItinClass; def II_MUH : InstrItinClass; def II_MUHU : InstrItinClass; def II_MULU : InstrItinClass; +def II_MULR_PS : InstrItinClass; def II_MULT : InstrItinClass; def II_MULTU : InstrItinClass; def II_MUL_D : InstrItinClass; diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsScheduleGeneric.td b/contrib/llvm-project/llvm/lib/Target/Mips/MipsScheduleGeneric.td index faccb37c2361..3888ca4e82f5 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsScheduleGeneric.td +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsScheduleGeneric.td @@ -822,17 +822,19 @@ def : InstRW<[GenericWriteFPUS], (instrs FABS_S, FABS_D32, FABS_D64, FADD_D32, // madd.d, msub.dm mul.d, mul.ps, nmadd.d, nmsub.d, ceil.[wl].[sd], cvt.d.[sw], // cvt.s.[dw], cvt.w.[sd], cvt.[sw].ps, round.[lw].[ds], floor.[lw].ds, // trunc.w.[ds], trunc.w.ps, -def : InstRW<[GenericWriteFPUL], (instrs CEIL_L_D64, CEIL_L_S, CEIL_W_D32, +def : InstRW<[GenericWriteFPUL], (instrs ADDR_PS64, + CEIL_L_D64, CEIL_L_S, CEIL_W_D32, CEIL_W_D64, CEIL_W_S, CVT_D32_S, CVT_D32_W, CVT_D64_L, CVT_D64_S, CVT_D64_W, CVT_L_D64, CVT_L_S, CVT_S_D32, CVT_S_D64, CVT_S_L, CVT_S_W, CVT_W_D32, CVT_W_D64, CVT_W_S, CVT_PS_S64, CVT_S_PL64, CVT_S_PU64, + CVT_PS_PW64, CVT_PW_PS64, FLOOR_L_D64, FLOOR_L_S, FLOOR_W_D32, FLOOR_W_D64, FLOOR_W_S, FMUL_D32, FMUL_D64, - MADD_D32, MADD_D64, MSUB_D32, MSUB_D64, + MADD_D32, MADD_D64, MSUB_D32, MSUB_D64, MULR_PS64, NMADD_D32, NMADD_D64, NMSUB_D32, NMSUB_D64, - PLL_PS64, PLU_PS64, + PLL_PS64, PLU_PS64, PUL_PS64, PUU_PS64, ROUND_L_D64, ROUND_L_S, ROUND_W_D32, ROUND_W_D64, ROUND_W_S, TRUNC_L_D64, TRUNC_L_S, TRUNC_W_D32, TRUNC_W_D64, diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsScheduleP5600.td b/contrib/llvm-project/llvm/lib/Target/Mips/MipsScheduleP5600.td index 7331917baa25..3d159d412489 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsScheduleP5600.td +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsScheduleP5600.td @@ -20,7 +20,8 @@ def MipsP5600Model : SchedMachineModel { IsGP64bit, IsPTR64bit, InMicroMips, InMips16Mode, HasCnMips, HasCnMipsP, - HasDSP, HasDSPR2, HasMT, HasCRC]; + HasDSP, HasDSPR2, HasMips3D, HasMT, + HasCRC]; } let SchedModel = MipsP5600Model in { @@ -457,7 +458,7 @@ def : InstRW<[P5600WriteFPUL], (instrs CVT_PS_S64, CVT_S_PL64, CVT_S_PU64)>; def : InstRW<[P5600WriteFPUL], (instregex "^C_[A-Z]+_(S|D32|D64)$")>; def : InstRW<[P5600WriteFPUL], (instregex "^FCMP_(S32|D32|D64)$")>; def : InstRW<[P5600WriteFPUL], (instregex "^PseudoCVT_(S|D32|D64)_(L|W)$")>; -def : InstRW<[P5600WriteFPUL], (instrs PLL_PS64, PLU_PS64)>; +def : InstRW<[P5600WriteFPUL], (instrs PLL_PS64, PLU_PS64, PUL_PS64, PUU_PS64)>; // div.[ds], div.ps def : InstRW<[P5600WriteFPUDivS], (instrs FDIV_S)>; diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsSubtarget.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/MipsSubtarget.cpp index 133b818114c8..ef4191cec3df 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsSubtarget.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsSubtarget.cpp @@ -237,7 +237,7 @@ CodeGenOpt::Level MipsSubtarget::getOptLevelToEnablePostRAScheduler() const { MipsSubtarget & MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS, const TargetMachine &TM) { - std::string CPUName = MIPS_MC::selectMipsCPU(TM.getTargetTriple(), CPU); + StringRef CPUName = MIPS_MC::selectMipsCPU(TM.getTargetTriple(), CPU); // Parse features string. ParseSubtargetFeatures(CPUName, FS); diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsSubtarget.h b/contrib/llvm-project/llvm/lib/Target/Mips/MipsSubtarget.h index 5a1dfec41a47..26ee961fc95d 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsSubtarget.h +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsSubtarget.h @@ -149,6 +149,9 @@ class MipsSubtarget : public MipsGenSubtargetInfo { // HasDSP, HasDSPR2, HasDSPR3 -- supports DSP ASE. bool HasDSP, HasDSPR2, HasDSPR3; + // Has3D -- Supports Mips3D ASE. + bool Has3D; + // Allow mixed Mips16 and Mips32 in one source file bool AllowMixed16_32; @@ -312,6 +315,7 @@ public: bool hasDSP() const { return HasDSP; } bool hasDSPR2() const { return HasDSPR2; } bool hasDSPR3() const { return HasDSPR3; } + bool has3D() const { return Has3D; } bool hasMSA() const { return HasMSA; } bool disableMadd4() const { return DisableMadd4; } bool hasEVA() const { return HasEVA; } diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsTargetMachine.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/MipsTargetMachine.cpp index 8fec6db00cb9..80cb6ce7ac0c 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsTargetMachine.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsTargetMachine.cpp @@ -131,6 +131,9 @@ MipsTargetMachine::MipsTargetMachine(const Target &T, const Triple &TT, MaybeAlign(Options.StackAlignmentOverride)) { Subtarget = &DefaultSubtarget; initAsmInfo(); + + // Mips supports the debug entry values. + setSupportsDebugEntryValues(true); } MipsTargetMachine::~MipsTargetMachine() = default; diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsTargetObjectFile.cpp b/contrib/llvm-project/llvm/lib/Target/Mips/MipsTargetObjectFile.cpp index 0852b5a18c68..481157a8aa89 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsTargetObjectFile.cpp +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsTargetObjectFile.cpp @@ -44,7 +44,6 @@ EmbeddedData("membedded-data", cl::Hidden, void MipsTargetObjectFile::Initialize(MCContext &Ctx, const TargetMachine &TM){ TargetLoweringObjectFileELF::Initialize(Ctx, TM); - InitializeELF(TM.Options.UseInitArray); SmallDataSection = getContext().getELFSection( ".sdata", ELF::SHT_PROGBITS, @@ -177,12 +176,13 @@ bool MipsTargetObjectFile::IsConstantInSmallSection( MCSection *MipsTargetObjectFile::getSectionForConstant(const DataLayout &DL, SectionKind Kind, const Constant *C, - unsigned &Align) const { + Align &Alignment) const { if (IsConstantInSmallSection(DL, C, *TM)) return SmallDataSection; // Otherwise, we work the same as ELF. - return TargetLoweringObjectFileELF::getSectionForConstant(DL, Kind, C, Align); + return TargetLoweringObjectFileELF::getSectionForConstant(DL, Kind, C, + Alignment); } const MCExpr * diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsTargetObjectFile.h b/contrib/llvm-project/llvm/lib/Target/Mips/MipsTargetObjectFile.h index bdf485f83260..07e9caf0dd09 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsTargetObjectFile.h +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsTargetObjectFile.h @@ -40,7 +40,7 @@ class MipsTargetMachine; MCSection *getSectionForConstant(const DataLayout &DL, SectionKind Kind, const Constant *C, - unsigned &Align) const override; + Align &Alignment) const override; /// Describe a TLS variable address within debug info. const MCExpr *getDebugThreadLocalSymbol(const MCSymbol *Sym) const override; }; diff --git a/contrib/llvm-project/llvm/lib/Target/Mips/MipsTargetStreamer.h b/contrib/llvm-project/llvm/lib/Target/Mips/MipsTargetStreamer.h index b389ba8938c4..f4282f5d6974 100644 --- a/contrib/llvm-project/llvm/lib/Target/Mips/MipsTargetStreamer.h +++ b/contrib/llvm-project/llvm/lib/Target/Mips/MipsTargetStreamer.h @@ -19,8 +19,6 @@ namespace llvm { -struct MipsABIFlagsSection; - class MipsTargetStreamer : public MCTargetStreamer { public: MipsTargetStreamer(MCStreamer &S); @@ -84,12 +82,15 @@ public: virtual void emitDirectiveSetDsp(); virtual void emitDirectiveSetDspr2(); virtual void emitDirectiveSetNoDsp(); + virtual void emitDirectiveSetMips3D(); + virtual void emitDirectiveSetNoMips3D(); virtual void emitDirectiveSetPop(); virtual void emitDirectiveSetPush(); virtual void emitDirectiveSetSoftFloat(); virtual void emitDirectiveSetHardFloat(); // PIC support + virtual void emitDirectiveCpAdd(unsigned RegNo); virtual void emitDirectiveCpLoad(unsigned RegNo); virtual void emitDirectiveCpLocal(unsigned RegNo); virtual bool emitDirectiveCpRestore(int Offset, @@ -263,12 +264,15 @@ public: void emitDirectiveSetDsp() override; void emitDirectiveSetDspr2() override; void emitDirectiveSetNoDsp() override; + void emitDirectiveSetMips3D() override; + void emitDirectiveSetNoMips3D() override; void emitDirectiveSetPop() override; void emitDirectiveSetPush() override; void emitDirectiveSetSoftFloat() override; void emitDirectiveSetHardFloat() override; // PIC support + void emitDirectiveCpAdd(unsigned RegNo) override; void emitDirectiveCpLoad(unsigned RegNo) override; void emitDirectiveCpLocal(unsigned RegNo) override; @@ -341,6 +345,7 @@ public: void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) override; // PIC support + void emitDirectiveCpAdd(unsigned RegNo) override; void emitDirectiveCpLoad(unsigned RegNo) override; void emitDirectiveCpLocal(unsigned RegNo) override; bool emitDirectiveCpRestore(int Offset, function_ref<unsigned()> GetATReg, |