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-rw-r--r--contrib/llvm-project/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td2
1 files changed, 1 insertions, 1 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td b/contrib/llvm-project/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
index 56ceb88f35d4..6a28aec6f846 100644
--- a/contrib/llvm-project/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
+++ b/contrib/llvm-project/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
@@ -206,7 +206,7 @@ def : InstRW<[WLat1, FXa, NormalGr], (instregex "LLIL(F|H|L)$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "LG(F|H)I$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "LHI(Mux)?$")>;
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "LR(Mux)?$")>;
+def : InstRW<[WLat1, FXa, NormalGr], (instregex "LR$")>;
// Load and zero rightmost byte
def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LZR(F|G)$")>;