diff options
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp')
| -rw-r--r-- | contrib/llvm-project/llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp | 55 |
1 files changed, 54 insertions, 1 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp b/contrib/llvm-project/llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp index 35885a4e3cae..20d609bc6b32 100644 --- a/contrib/llvm-project/llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp +++ b/contrib/llvm-project/llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp @@ -47,7 +47,7 @@ static MCDisassembler *createVEDisassembler(const Target &T, return new VEDisassembler(STI, Ctx); } -extern "C" void LLVMInitializeVEDisassembler() { +extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeVEDisassembler() { // Register the disassembler. TargetRegistry::RegisterMCDisassembler(getTheVETarget(), createVEDisassembler); @@ -95,6 +95,25 @@ static const unsigned F128RegDecoderTable[] = { VE::Q16, VE::Q17, VE::Q18, VE::Q19, VE::Q20, VE::Q21, VE::Q22, VE::Q23, VE::Q24, VE::Q25, VE::Q26, VE::Q27, VE::Q28, VE::Q29, VE::Q30, VE::Q31}; +static const unsigned V64RegDecoderTable[] = { + VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7, + VE::V8, VE::V9, VE::V10, VE::V11, VE::V12, VE::V13, VE::V14, VE::V15, + VE::V16, VE::V17, VE::V18, VE::V19, VE::V20, VE::V21, VE::V22, VE::V23, + VE::V24, VE::V25, VE::V26, VE::V27, VE::V28, VE::V29, VE::V30, VE::V31, + VE::V32, VE::V33, VE::V34, VE::V35, VE::V36, VE::V37, VE::V38, VE::V39, + VE::V40, VE::V41, VE::V42, VE::V43, VE::V44, VE::V45, VE::V46, VE::V47, + VE::V48, VE::V49, VE::V50, VE::V51, VE::V52, VE::V53, VE::V54, VE::V55, + VE::V56, VE::V57, VE::V58, VE::V59, VE::V60, VE::V61, VE::V62, VE::V63}; + +static const unsigned VMRegDecoderTable[] = { + VE::VM0, VE::VM1, VE::VM2, VE::VM3, VE::VM4, VE::VM5, + VE::VM6, VE::VM7, VE::VM8, VE::VM9, VE::VM10, VE::VM11, + VE::VM12, VE::VM13, VE::VM14, VE::VM15}; + +static const unsigned VM512RegDecoderTable[] = {VE::VMP0, VE::VMP1, VE::VMP2, + VE::VMP3, VE::VMP4, VE::VMP5, + VE::VMP6, VE::VMP7}; + static const unsigned MiscRegDecoderTable[] = { VE::USRCC, VE::PSW, VE::SAR, VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::PMMR, @@ -145,6 +164,40 @@ static DecodeStatus DecodeF128RegisterClass(MCInst &Inst, unsigned RegNo, return MCDisassembler::Success; } +static DecodeStatus DecodeV64RegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { + unsigned Reg = VE::NoRegister; + if (RegNo == 255) + Reg = VE::VIX; + else if (RegNo > 63) + return MCDisassembler::Fail; + else + Reg = V64RegDecoderTable[RegNo]; + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} + +static DecodeStatus DecodeVMRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { + if (RegNo > 15) + return MCDisassembler::Fail; + unsigned Reg = VMRegDecoderTable[RegNo]; + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} + +static DecodeStatus DecodeVM512RegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { + if (RegNo % 2 || RegNo > 15) + return MCDisassembler::Fail; + unsigned Reg = VM512RegDecoderTable[RegNo / 2]; + Inst.addOperand(MCOperand::createReg(Reg)); + return MCDisassembler::Success; +} + static DecodeStatus DecodeMISCRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { |