diff options
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/VE/VERegisterInfo.cpp')
| -rw-r--r-- | contrib/llvm-project/llvm/lib/Target/VE/VERegisterInfo.cpp | 105 |
1 files changed, 77 insertions, 28 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/VE/VERegisterInfo.cpp b/contrib/llvm-project/llvm/lib/Target/VE/VERegisterInfo.cpp index 5783a8df69d2..d175ad26c742 100644 --- a/contrib/llvm-project/llvm/lib/Target/VE/VERegisterInfo.cpp +++ b/contrib/llvm-project/llvm/lib/Target/VE/VERegisterInfo.cpp @@ -22,6 +22,7 @@ #include "llvm/CodeGen/TargetInstrInfo.h" #include "llvm/IR/Type.h" #include "llvm/Support/CommandLine.h" +#include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" using namespace llvm; @@ -35,6 +36,8 @@ VERegisterInfo::VERegisterInfo() : VEGenRegisterInfo(VE::SX10) {} const MCPhysReg * VERegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { switch (MF->getFunction().getCallingConv()) { + case CallingConv::Fast: + // Being explicit (same as standard CC). default: return CSR_SaveList; case CallingConv::PreserveAll: @@ -45,6 +48,8 @@ VERegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { const uint32_t *VERegisterInfo::getCallPreservedMask(const MachineFunction &MF, CallingConv::ID CC) const { switch (CC) { + case CallingConv::Fast: + // Being explicit (same as standard CC). default: return CSR_RegMask; case CallingConv::PreserveAll: @@ -82,10 +87,22 @@ BitVector VERegisterInfo::getReservedRegs(const MachineFunction &MF) const { ++ItAlias) Reserved.set(*ItAlias); + // Reserve constant registers. + Reserved.set(VE::VM0); + Reserved.set(VE::VMP0); + return Reserved; } -bool VERegisterInfo::isConstantPhysReg(MCRegister PhysReg) const { return false; } +bool VERegisterInfo::isConstantPhysReg(MCRegister PhysReg) const { + switch (PhysReg) { + case VE::VM0: + case VE::VMP0: + return true; + default: + return false; + } +} const TargetRegisterClass * VERegisterInfo::getPointerRegClass(const MachineFunction &MF, @@ -93,6 +110,29 @@ VERegisterInfo::getPointerRegClass(const MachineFunction &MF, return &VE::I64RegClass; } +static unsigned offsetToDisp(MachineInstr &MI) { + // Default offset in instruction's operands (reg+reg+imm). + unsigned OffDisp = 2; + +#define RRCAS_multi_cases(NAME) NAME##rir : case NAME##rii + + { + using namespace llvm::VE; + switch (MI.getOpcode()) { + case RRCAS_multi_cases(TS1AML): + case RRCAS_multi_cases(TS1AMW): + case RRCAS_multi_cases(CASL): + case RRCAS_multi_cases(CASW): + // These instructions use AS format (reg+imm). + OffDisp = 1; + break; + } + } +#undef RRCAS_multi_cases + + return OffDisp; +} + static void replaceFI(MachineFunction &MF, MachineBasicBlock::iterator II, MachineInstr &MI, const DebugLoc &dl, unsigned FIOperandNum, int Offset, Register FrameReg) { @@ -100,7 +140,7 @@ static void replaceFI(MachineFunction &MF, MachineBasicBlock::iterator II, // VE has 32 bit offset field, so no need to expand a target instruction. // Directly encode it. MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false); - MI.getOperand(FIOperandNum + 2).ChangeToImmediate(Offset); + MI.getOperand(FIOperandNum + offsetToDisp(MI)).ChangeToImmediate(Offset); } void VERegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, @@ -116,9 +156,41 @@ void VERegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, Register FrameReg; int Offset; - Offset = TFI->getFrameIndexReference(MF, FrameIndex, FrameReg); - - Offset += MI.getOperand(FIOperandNum + 2).getImm(); + Offset = TFI->getFrameIndexReference(MF, FrameIndex, FrameReg).getFixed(); + + Offset += MI.getOperand(FIOperandNum + offsetToDisp(MI)).getImm(); + + if (MI.getOpcode() == VE::STQrii) { + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); + Register SrcReg = MI.getOperand(3).getReg(); + Register SrcHiReg = getSubReg(SrcReg, VE::sub_even); + Register SrcLoReg = getSubReg(SrcReg, VE::sub_odd); + // VE stores HiReg to 8(addr) and LoReg to 0(addr) + MachineInstr *StMI = BuildMI(*MI.getParent(), II, dl, TII.get(VE::STrii)) + .addReg(FrameReg) + .addImm(0) + .addImm(0) + .addReg(SrcLoReg); + replaceFI(MF, II, *StMI, dl, 0, Offset, FrameReg); + MI.setDesc(TII.get(VE::STrii)); + MI.getOperand(3).setReg(SrcHiReg); + Offset += 8; + } else if (MI.getOpcode() == VE::LDQrii) { + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); + Register DestReg = MI.getOperand(0).getReg(); + Register DestHiReg = getSubReg(DestReg, VE::sub_even); + Register DestLoReg = getSubReg(DestReg, VE::sub_odd); + // VE loads HiReg from 8(addr) and LoReg from 0(addr) + MachineInstr *StMI = + BuildMI(*MI.getParent(), II, dl, TII.get(VE::LDrii), DestLoReg) + .addReg(FrameReg) + .addImm(0) + .addImm(0); + replaceFI(MF, II, *StMI, dl, 1, Offset, FrameReg); + MI.setDesc(TII.get(VE::LDrii)); + MI.getOperand(0).setReg(DestHiReg); + Offset += 8; + } replaceFI(MF, II, MI, dl, FIOperandNum, Offset, FrameReg); } @@ -126,26 +198,3 @@ void VERegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, Register VERegisterInfo::getFrameRegister(const MachineFunction &MF) const { return VE::SX9; } - -// VE has no architectural need for stack realignment support, -// except that LLVM unfortunately currently implements overaligned -// stack objects by depending upon stack realignment support. -// If that ever changes, this can probably be deleted. -bool VERegisterInfo::canRealignStack(const MachineFunction &MF) const { - if (!TargetRegisterInfo::canRealignStack(MF)) - return false; - - // VE always has a fixed frame pointer register, so don't need to - // worry about needing to reserve it. [even if we don't have a frame - // pointer for our frame, it still cannot be used for other things, - // or register window traps will be SADNESS.] - - // If there's a reserved call frame, we can use VE to access locals. - if (getFrameLowering(MF)->hasReservedCallFrame(MF)) - return true; - - // Otherwise, we'd need a base pointer, but those aren't implemented - // for VE at the moment. - - return false; -} |