diff options
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/X86/X86InstrAMX.td')
| -rw-r--r-- | contrib/llvm-project/llvm/lib/Target/X86/X86InstrAMX.td | 54 |
1 files changed, 42 insertions, 12 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/X86/X86InstrAMX.td b/contrib/llvm-project/llvm/lib/Target/X86/X86InstrAMX.td index e26dd5050a23..e4f3290cab9f 100644 --- a/contrib/llvm-project/llvm/lib/Target/X86/X86InstrAMX.td +++ b/contrib/llvm-project/llvm/lib/Target/X86/X86InstrAMX.td @@ -16,17 +16,21 @@ let Predicates = [HasAMXTILE, In64BitMode] in { let SchedRW = [WriteSystem] in { - let Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in + let hasSideEffects = 1, + Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in def LDTILECFG : I <0x49, MRM0m, (outs), (ins opaquemem:$src), "ldtilecfg\t$src", [(int_x86_ldtilecfg addr:$src)]>, VEX, T8PS; + let hasSideEffects = 1 in def STTILECFG : I <0x49, MRM0m, (outs), (ins opaquemem:$src), "sttilecfg\t$src", [(int_x86_sttilecfg addr:$src)]>, VEX, T8PD; + let mayLoad = 1 in def TILELOADD : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst), (ins sibmem:$src), "tileloadd\t{$src, $dst|$dst, $src}", []>, VEX, T8XD; + let mayLoad = 1 in def TILELOADDT1 : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst), (ins sibmem:$src), "tileloaddt1\t{$src, $dst|$dst, $src}", []>, @@ -34,6 +38,7 @@ let Predicates = [HasAMXTILE, In64BitMode] in { let Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in def TILERELEASE : I<0x49, MRM_C0, (outs), (ins), "tilerelease", [(int_x86_tilerelease)]>, VEX, T8PS; + let mayStore = 1 in def TILESTORED : I<0x4b, MRMDestMemFSIB, (outs), (ins sibmem:$dst, TILE:$src), "tilestored\t{$src, $dst|$dst, $src}", []>, @@ -42,6 +47,25 @@ let Predicates = [HasAMXTILE, In64BitMode] in { "tilezero\t$dst", []>, VEX, T8XD; + // Pseduo instruction for RA. + let hasSideEffects = 1, mayLoad = 1, + Defs = [TMM0,TMM1,TMM2,TMM3,TMM4,TMM5,TMM6,TMM7] in + def PLDTILECFG : PseudoI <(outs TILECFG:$cfg), (ins opaquemem:$src), []>; + + let hasSideEffects = 1, mayStore = 1 in + def PSTTILECFG : PseudoI<(outs), (ins opaquemem:$dst, TILECFG:$cfg), []>; + + def PTILELOADDV : PseudoI<(outs TILE: $dst), (ins GR16:$src1, + GR16:$src2, + opaquemem:$src3, + TILECFG:$cfg), []>; + def PTILESTOREDV : PseudoI<(outs), (ins GR16:$src1, + GR16:$src2, opaquemem:$src3, + TILE:$src4, TILECFG:$cfg), []>; + def PTILEZEROV : PseudoI<(outs TILE: $dst), (ins GR16:$src1, + GR16:$src2, + TILECFG:$cfg), []>; + let usesCustomInserter = 1 in { // Pseudo instructions, using immediates instead of tile registers. // To be translated to the actual instructions in X86ISelLowering.cpp @@ -50,7 +74,7 @@ let Predicates = [HasAMXTILE, In64BitMode] in { sibmem:$src2), []>; def PTILESTORED : PseudoI<(outs), (ins i8mem:$dst, u8imm:$src), []>; def PTILEZERO : PseudoI<(outs), (ins u8imm:$src), - [(int_x86_tilezero imm:$src)]>; + [(int_x86_tilezero timm:$src)]>; } } // SchedRW } // HasAMXTILE @@ -76,25 +100,31 @@ let Predicates = [HasAMXINT8, In64BitMode] in { VEX_4V, T8PS; } + // Pseduo instruction for RA. + let Constraints = "$src4 = $dst" in + def PTDPBSSDV : PseudoI<(outs TILE: $dst), (ins GR16:$src1, + GR16:$src2, GR16:$src3, TILE:$src4, + TILE:$src5, TILE:$src6, TILECFG:$cfg), []>; + let usesCustomInserter = 1 in { // Pseudo instructions, using immediates instead of tile registers. // To be translated to the actual instructions in X86ISelLowering.cpp def PTDPBSSD : PseudoI<(outs), (ins u8imm:$src1, u8imm:$src2, u8imm:$src3), - [(int_x86_tdpbssd imm:$src1, - imm:$src2, imm:$src3)]>; + [(int_x86_tdpbssd timm:$src1, + timm:$src2, timm:$src3)]>; def PTDPBSUD : PseudoI<(outs), (ins u8imm:$src1, u8imm:$src2, u8imm:$src3), - [(int_x86_tdpbsud imm:$src1, - imm:$src2, imm:$src3)]>; + [(int_x86_tdpbsud timm:$src1, + timm:$src2, timm:$src3)]>; def PTDPBUSD : PseudoI<(outs), (ins u8imm:$src1, u8imm:$src2, u8imm:$src3), - [(int_x86_tdpbusd imm:$src1, - imm:$src2, imm:$src3)]>; + [(int_x86_tdpbusd timm:$src1, + timm:$src2, timm:$src3)]>; def PTDPBUUD : PseudoI<(outs), (ins u8imm:$src1, u8imm:$src2, u8imm:$src3), - [(int_x86_tdpbuud imm:$src1, - imm:$src2, imm:$src3)]>; + [(int_x86_tdpbuud timm:$src1, + timm:$src2, timm:$src3)]>; } } } // HasAMXTILE @@ -112,8 +142,8 @@ let Predicates = [HasAMXBF16, In64BitMode] in { // To be translated to the actual instructions in X86ISelLowering.cpp def PTDPBF16PS : PseudoI<(outs), (ins u8imm:$src1, u8imm:$src2, u8imm:$src3), - [(int_x86_tdpbf16ps imm:$src1, - imm:$src2, imm:$src3)]>; + [(int_x86_tdpbf16ps timm:$src1, + timm:$src2, timm:$src3)]>; } } } // HasAMXTILE, HasAMXBF16 |