diff options
Diffstat (limited to 'contrib/llvm-project/llvm/lib/Target/X86/X86InstrInfo.h')
| -rw-r--r-- | contrib/llvm-project/llvm/lib/Target/X86/X86InstrInfo.h | 32 |
1 files changed, 20 insertions, 12 deletions
diff --git a/contrib/llvm-project/llvm/lib/Target/X86/X86InstrInfo.h b/contrib/llvm-project/llvm/lib/Target/X86/X86InstrInfo.h index 89f2ff118c37..d7d2370c6f67 100644 --- a/contrib/llvm-project/llvm/lib/Target/X86/X86InstrInfo.h +++ b/contrib/llvm-project/llvm/lib/Target/X86/X86InstrInfo.h @@ -317,6 +317,17 @@ public: SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const override; + Optional<ExtAddrMode> + getAddrModeFromMemoryOp(const MachineInstr &MemI, + const TargetRegisterInfo *TRI) const override; + + bool getConstValDefinedInReg(const MachineInstr &MI, const Register Reg, + int64_t &ImmVal) const override; + + bool preservesZeroValueInReg(const MachineInstr *MI, + const Register NullValueReg, + const TargetRegisterInfo *TRI) const override; + bool getMemOperandsWithOffsetWidth( const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset, @@ -409,6 +420,13 @@ public: bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override; + /// isSchedulingBoundary - Overrides the isSchedulingBoundary from + /// Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR + /// intructions and prevent it from being re-scheduled. + bool isSchedulingBoundary(const MachineInstr &MI, + const MachineBasicBlock *MBB, + const MachineFunction &MF) const override; + /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads /// should be scheduled togther. On some targets if two loads are loading from @@ -430,16 +448,6 @@ public: /// instruction that defines the specified register class. bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override; - /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction tha - /// would clobber the EFLAGS condition register. Note the result may be - /// conservative. If it cannot definitely determine the safety after visiting - /// a few instructions in each direction it assumes it's not safe. - bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I) const { - return MBB.computeRegisterLiveness(&RI, X86::EFLAGS, I, 4) == - MachineBasicBlock::LQR_Dead; - } - /// True if MI has a condition code def, e.g. EFLAGS, that is /// not marked dead. bool hasLiveCondCodeDef(MachineInstr &MI) const; @@ -462,7 +470,7 @@ public: unsigned getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override; - unsigned getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum, + unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override; void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override; @@ -517,7 +525,7 @@ public: /// the machine instruction generated due to folding. MachineInstr *optimizeLoadInstr(MachineInstr &MI, const MachineRegisterInfo *MRI, - unsigned &FoldAsLoadDefReg, + Register &FoldAsLoadDefReg, MachineInstr *&DefMI) const override; std::pair<unsigned, unsigned> |